2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
128 #include <sys/turnstile.h>
129 #include <sys/vmem.h>
130 #include <sys/vmmeter.h>
131 #include <sys/sched.h>
132 #include <sys/sysctl.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
148 #include <vm/vm_phys.h>
149 #include <vm/vm_radix.h>
150 #include <vm/vm_reserv.h>
153 #include <machine/intr_machdep.h>
154 #include <x86/apicvar.h>
155 #include <x86/ifunc.h>
156 #include <machine/cpu.h>
157 #include <machine/cputypes.h>
158 #include <machine/md_var.h>
159 #include <machine/pcb.h>
160 #include <machine/specialreg.h>
162 #include <machine/smp.h>
164 #include <machine/sysarch.h>
165 #include <machine/tss.h>
167 static __inline boolean_t
168 pmap_type_guest(pmap_t pmap)
171 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
174 static __inline boolean_t
175 pmap_emulate_ad_bits(pmap_t pmap)
178 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
181 static __inline pt_entry_t
182 pmap_valid_bit(pmap_t pmap)
186 switch (pmap->pm_type) {
192 if (pmap_emulate_ad_bits(pmap))
193 mask = EPT_PG_EMUL_V;
198 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
204 static __inline pt_entry_t
205 pmap_rw_bit(pmap_t pmap)
209 switch (pmap->pm_type) {
215 if (pmap_emulate_ad_bits(pmap))
216 mask = EPT_PG_EMUL_RW;
221 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
227 static pt_entry_t pg_g;
229 static __inline pt_entry_t
230 pmap_global_bit(pmap_t pmap)
234 switch (pmap->pm_type) {
243 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
249 static __inline pt_entry_t
250 pmap_accessed_bit(pmap_t pmap)
254 switch (pmap->pm_type) {
260 if (pmap_emulate_ad_bits(pmap))
266 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
272 static __inline pt_entry_t
273 pmap_modified_bit(pmap_t pmap)
277 switch (pmap->pm_type) {
283 if (pmap_emulate_ad_bits(pmap))
289 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
295 static __inline pt_entry_t
296 pmap_pku_mask_bit(pmap_t pmap)
299 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
302 #if !defined(DIAGNOSTIC)
303 #ifdef __GNUC_GNU_INLINE__
304 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
306 #define PMAP_INLINE extern inline
313 #define PV_STAT(x) do { x ; } while (0)
315 #define PV_STAT(x) do { } while (0)
318 #define pa_index(pa) ((pa) >> PDRSHIFT)
319 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
321 #define NPV_LIST_LOCKS MAXCPU
323 #define PHYS_TO_PV_LIST_LOCK(pa) \
324 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
326 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
327 struct rwlock **_lockp = (lockp); \
328 struct rwlock *_new_lock; \
330 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
331 if (_new_lock != *_lockp) { \
332 if (*_lockp != NULL) \
333 rw_wunlock(*_lockp); \
334 *_lockp = _new_lock; \
339 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
340 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
342 #define RELEASE_PV_LIST_LOCK(lockp) do { \
343 struct rwlock **_lockp = (lockp); \
345 if (*_lockp != NULL) { \
346 rw_wunlock(*_lockp); \
351 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
352 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
354 struct pmap kernel_pmap_store;
356 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
357 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
360 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
361 "Number of kernel page table pages allocated on bootup");
364 vm_paddr_t dmaplimit;
365 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
368 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
370 static int pg_ps_enabled = 1;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
372 &pg_ps_enabled, 0, "Are large page mappings enabled?");
374 #define PAT_INDEX_SIZE 8
375 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
377 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
378 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
379 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
380 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
382 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
383 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
384 static int ndmpdpphys; /* number of DMPDPphys pages */
386 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
389 * pmap_mapdev support pre initialization (i.e. console)
391 #define PMAP_PREINIT_MAPPING_COUNT 8
392 static struct pmap_preinit_mapping {
397 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
398 static int pmap_initialized;
401 * Data for the pv entry allocation mechanism.
402 * Updates to pv_invl_gen are protected by the pv_list_locks[]
403 * elements, but reads are not.
405 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
406 static struct mtx __exclusive_cache_line pv_chunks_mutex;
407 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
408 static u_long pv_invl_gen[NPV_LIST_LOCKS];
409 static struct md_page *pv_table;
410 static struct md_page pv_dummy;
413 * All those kernel PT submaps that BSD is so fond of
415 pt_entry_t *CMAP1 = NULL;
417 static vm_offset_t qframe = 0;
418 static struct mtx qframe_mtx;
420 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
422 static vmem_t *large_vmem;
423 static u_int lm_ents;
425 int pmap_pcid_enabled = 1;
426 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
427 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
428 int invpcid_works = 0;
429 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
430 "Is the invpcid instruction available ?");
432 int __read_frequently pti = 0;
433 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
435 "Page Table Isolation enabled");
436 static vm_object_t pti_obj;
437 static pml4_entry_t *pti_pml4;
438 static vm_pindex_t pti_pg_idx;
439 static bool pti_finalized;
441 struct pmap_pkru_range {
442 struct rs_el pkru_rs_el;
447 static uma_zone_t pmap_pkru_ranges_zone;
448 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
449 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
450 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
451 static void *pkru_dup_range(void *ctx, void *data);
452 static void pkru_free_range(void *ctx, void *node);
453 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
454 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
455 static void pmap_pkru_deassign_all(pmap_t pmap);
458 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
465 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
467 return (sysctl_handle_64(oidp, &res, 0, req));
469 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
470 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
471 "Count of saved TLB context on switch");
473 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
474 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
475 static struct mtx invl_gen_mtx;
476 /* Fake lock object to satisfy turnstiles interface. */
477 static struct lock_object invl_gen_ts = {
480 static struct pmap_invl_gen pmap_invl_gen_head = {
484 static u_long pmap_invl_gen = 1;
486 #define PMAP_ASSERT_NOT_IN_DI() \
487 KASSERT(pmap_not_in_di(), ("DI already started"))
494 if ((cpu_feature2 & CPUID2_CX16) == 0)
497 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
502 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
506 locked = pmap_di_locked();
507 return (sysctl_handle_int(oidp, &locked, 0, req));
509 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
510 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
511 "Locked delayed invalidation");
513 static bool pmap_not_in_di_l(void);
514 static bool pmap_not_in_di_u(void);
515 DEFINE_IFUNC(, bool, pmap_not_in_di, (void), static)
518 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
522 pmap_not_in_di_l(void)
524 struct pmap_invl_gen *invl_gen;
526 invl_gen = &curthread->td_md.md_invl_gen;
527 return (invl_gen->gen == 0);
531 pmap_thread_init_invl_gen_l(struct thread *td)
533 struct pmap_invl_gen *invl_gen;
535 invl_gen = &td->td_md.md_invl_gen;
540 * Start a new Delayed Invalidation (DI) block of code, executed by
541 * the current thread. Within a DI block, the current thread may
542 * destroy both the page table and PV list entries for a mapping and
543 * then release the corresponding PV list lock before ensuring that
544 * the mapping is flushed from the TLBs of any processors with the
548 pmap_delayed_invl_start_l(void)
550 struct pmap_invl_gen *invl_gen;
553 invl_gen = &curthread->td_md.md_invl_gen;
554 PMAP_ASSERT_NOT_IN_DI();
555 mtx_lock(&invl_gen_mtx);
556 if (LIST_EMPTY(&pmap_invl_gen_tracker))
557 currgen = pmap_invl_gen;
559 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
560 invl_gen->gen = currgen + 1;
561 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
562 mtx_unlock(&invl_gen_mtx);
566 * Finish the DI block, previously started by the current thread. All
567 * required TLB flushes for the pages marked by
568 * pmap_delayed_invl_page() must be finished before this function is
571 * This function works by bumping the global DI generation number to
572 * the generation number of the current thread's DI, unless there is a
573 * pending DI that started earlier. In the latter case, bumping the
574 * global DI generation number would incorrectly signal that the
575 * earlier DI had finished. Instead, this function bumps the earlier
576 * DI's generation number to match the generation number of the
577 * current thread's DI.
580 pmap_delayed_invl_finish_l(void)
582 struct pmap_invl_gen *invl_gen, *next;
583 struct turnstile *ts;
585 invl_gen = &curthread->td_md.md_invl_gen;
586 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
587 mtx_lock(&invl_gen_mtx);
588 next = LIST_NEXT(invl_gen, link);
590 turnstile_chain_lock(&invl_gen_ts);
591 ts = turnstile_lookup(&invl_gen_ts);
592 pmap_invl_gen = invl_gen->gen;
594 turnstile_broadcast(ts, TS_SHARED_QUEUE);
595 turnstile_unpend(ts);
597 turnstile_chain_unlock(&invl_gen_ts);
599 next->gen = invl_gen->gen;
601 LIST_REMOVE(invl_gen, link);
602 mtx_unlock(&invl_gen_mtx);
607 pmap_not_in_di_u(void)
609 struct pmap_invl_gen *invl_gen;
611 invl_gen = &curthread->td_md.md_invl_gen;
612 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
616 pmap_thread_init_invl_gen_u(struct thread *td)
618 struct pmap_invl_gen *invl_gen;
620 invl_gen = &td->td_md.md_invl_gen;
622 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
626 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
628 uint64_t new_high, new_low, old_high, old_low;
631 old_low = new_low = 0;
632 old_high = new_high = (uintptr_t)0;
634 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
635 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
636 : "b"(new_low), "c" (new_high)
639 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
642 out->next = (void *)old_high;
645 out->next = (void *)new_high;
651 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
652 struct pmap_invl_gen *new_val)
654 uint64_t new_high, new_low, old_high, old_low;
657 new_low = new_val->gen;
658 new_high = (uintptr_t)new_val->next;
659 old_low = old_val->gen;
660 old_high = (uintptr_t)old_val->next;
662 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
663 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
664 : "b"(new_low), "c" (new_high)
670 static long invl_start_restart;
671 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
672 &invl_start_restart, 0,
674 static long invl_finish_restart;
675 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
676 &invl_finish_restart, 0,
678 static int invl_max_qlen;
679 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
684 static struct lock_delay_config __read_frequently di_delay;
685 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
688 pmap_delayed_invl_start_u(void)
690 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
692 struct lock_delay_arg lda;
700 invl_gen = &td->td_md.md_invl_gen;
701 PMAP_ASSERT_NOT_IN_DI();
702 lock_delay_arg_init(&lda, &di_delay);
704 pri = td->td_base_pri;
706 invl_gen->saved_pri = 0;
708 invl_gen->saved_pri = pri;
715 for (p = &pmap_invl_gen_head;; p = prev.next) {
717 prevl = atomic_load_ptr(&p->next);
718 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
719 PV_STAT(atomic_add_long(&invl_start_restart, 1));
725 prev.next = (void *)prevl;
728 if ((ii = invl_max_qlen) < i)
729 atomic_cmpset_int(&invl_max_qlen, ii, i);
732 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
733 PV_STAT(atomic_add_long(&invl_start_restart, 1));
738 new_prev.gen = prev.gen;
739 new_prev.next = invl_gen;
740 invl_gen->gen = prev.gen + 1;
742 /* Formal fence between store to invl->gen and updating *p. */
743 atomic_thread_fence_rel();
746 * After inserting an invl_gen element with invalid bit set,
747 * this thread blocks any other thread trying to enter the
748 * delayed invalidation block. Do not allow to remove us from
749 * the CPU, because it causes starvation for other threads.
754 * ABA for *p is not possible there, since p->gen can only
755 * increase. So if the *p thread finished its di, then
756 * started a new one and got inserted into the list at the
757 * same place, its gen will appear greater than the previously
760 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
762 PV_STAT(atomic_add_long(&invl_start_restart, 1));
768 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
769 * invl_gen->next, allowing other threads to iterate past us.
770 * pmap_di_store_invl() provides fence between the generation
771 * write and the update of next.
773 invl_gen->next = NULL;
778 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
779 struct pmap_invl_gen *p)
781 struct pmap_invl_gen prev, new_prev;
785 * Load invl_gen->gen after setting invl_gen->next
786 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
787 * generations to propagate to our invl_gen->gen. Lock prefix
788 * in atomic_set_ptr() worked as seq_cst fence.
790 mygen = atomic_load_long(&invl_gen->gen);
792 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
795 KASSERT(prev.gen < mygen,
796 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
797 new_prev.gen = mygen;
798 new_prev.next = (void *)((uintptr_t)invl_gen->next &
799 ~PMAP_INVL_GEN_NEXT_INVALID);
801 /* Formal fence between load of prev and storing update to it. */
802 atomic_thread_fence_rel();
804 return (pmap_di_store_invl(p, &prev, &new_prev));
808 pmap_delayed_invl_finish_u(void)
810 struct pmap_invl_gen *invl_gen, *p;
812 struct lock_delay_arg lda;
816 invl_gen = &td->td_md.md_invl_gen;
817 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
818 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
819 ("missed invl_start: INVALID"));
820 lock_delay_arg_init(&lda, &di_delay);
823 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
824 prevl = atomic_load_ptr(&p->next);
825 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
826 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
830 if ((void *)prevl == invl_gen)
835 * It is legitimate to not find ourself on the list if a
836 * thread before us finished its DI and started it again.
838 if (__predict_false(p == NULL)) {
839 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
845 atomic_set_ptr((uintptr_t *)&invl_gen->next,
846 PMAP_INVL_GEN_NEXT_INVALID);
847 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
848 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
849 PMAP_INVL_GEN_NEXT_INVALID);
851 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
856 if (invl_gen->saved_pri != 0) {
858 sched_prio(td, invl_gen->saved_pri);
864 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
866 struct pmap_invl_gen *p, *pn;
871 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
873 nextl = atomic_load_ptr(&p->next);
874 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
875 td = first ? NULL : __containerof(p, struct thread,
877 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
878 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
879 td != NULL ? td->td_tid : -1);
885 static long invl_wait;
886 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
887 "Number of times DI invalidation blocked pmap_remove_all/write");
891 pmap_delayed_invl_genp(vm_page_t m)
894 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
898 * Ensure that all currently executing DI blocks, that need to flush
899 * TLB for the given page m, actually flushed the TLB at the time the
900 * function returned. If the page m has an empty PV list and we call
901 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
902 * valid mapping for the page m in either its page table or TLB.
904 * This function works by blocking until the global DI generation
905 * number catches up with the generation number associated with the
906 * given page m and its PV list. Since this function's callers
907 * typically own an object lock and sometimes own a page lock, it
908 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
912 pmap_delayed_invl_wait_l(vm_page_t m)
914 struct turnstile *ts;
917 bool accounted = false;
920 m_gen = pmap_delayed_invl_genp(m);
921 while (*m_gen > pmap_invl_gen) {
924 atomic_add_long(&invl_wait, 1);
928 ts = turnstile_trywait(&invl_gen_ts);
929 if (*m_gen > pmap_invl_gen)
930 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
932 turnstile_cancel(ts);
937 pmap_delayed_invl_wait_u(vm_page_t m)
941 bool accounted = false;
944 m_gen = pmap_delayed_invl_genp(m);
945 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
948 atomic_add_long(&invl_wait, 1);
952 kern_yield(PRI_USER);
956 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *), static)
959 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
960 pmap_thread_init_invl_gen_u);
963 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void), static)
966 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
967 pmap_delayed_invl_start_u);
970 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void), static)
973 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
974 pmap_delayed_invl_finish_u);
977 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t), static)
980 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
981 pmap_delayed_invl_wait_u);
985 * Mark the page m's PV list as participating in the current thread's
986 * DI block. Any threads concurrently using m's PV list to remove or
987 * restrict all mappings to m will wait for the current thread's DI
988 * block to complete before proceeding.
990 * The function works by setting the DI generation number for m's PV
991 * list to at least the DI generation number of the current thread.
992 * This forces a caller of pmap_delayed_invl_wait() to block until
993 * current thread calls pmap_delayed_invl_finish().
996 pmap_delayed_invl_page(vm_page_t m)
1000 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1001 gen = curthread->td_md.md_invl_gen.gen;
1004 m_gen = pmap_delayed_invl_genp(m);
1012 static caddr_t crashdumpmap;
1015 * Internal flags for pmap_enter()'s helper functions.
1017 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1018 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1020 static void free_pv_chunk(struct pv_chunk *pc);
1021 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1022 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1023 static int popcnt_pc_map_pq(uint64_t *map);
1024 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1025 static void reserve_pv_entries(pmap_t pmap, int needed,
1026 struct rwlock **lockp);
1027 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1028 struct rwlock **lockp);
1029 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1030 u_int flags, struct rwlock **lockp);
1031 #if VM_NRESERVLEVEL > 0
1032 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1033 struct rwlock **lockp);
1035 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1036 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1039 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
1041 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1042 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1043 vm_offset_t va, struct rwlock **lockp);
1044 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1046 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1047 vm_prot_t prot, struct rwlock **lockp);
1048 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1049 u_int flags, vm_page_t m, struct rwlock **lockp);
1050 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1051 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1052 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1053 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
1054 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1056 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1058 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1060 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1061 static vm_page_t pmap_large_map_getptp_unlocked(void);
1062 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
1063 #if VM_NRESERVLEVEL > 0
1064 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1065 struct rwlock **lockp);
1067 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1069 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
1070 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1072 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1073 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1074 static void pmap_pti_wire_pte(void *pte);
1075 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1076 struct spglist *free, struct rwlock **lockp);
1077 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1078 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1079 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1080 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1081 struct spglist *free);
1082 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1083 pd_entry_t *pde, struct spglist *free,
1084 struct rwlock **lockp);
1085 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1086 vm_page_t m, struct rwlock **lockp);
1087 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1089 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1091 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1092 struct rwlock **lockp);
1093 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1094 struct rwlock **lockp);
1095 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1096 struct rwlock **lockp);
1098 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1099 struct spglist *free);
1100 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1102 /********************/
1103 /* Inline functions */
1104 /********************/
1106 /* Return a non-clipped PD index for a given VA */
1107 static __inline vm_pindex_t
1108 pmap_pde_pindex(vm_offset_t va)
1110 return (va >> PDRSHIFT);
1114 /* Return a pointer to the PML4 slot that corresponds to a VA */
1115 static __inline pml4_entry_t *
1116 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1119 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1122 /* Return a pointer to the PDP slot that corresponds to a VA */
1123 static __inline pdp_entry_t *
1124 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1128 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1129 return (&pdpe[pmap_pdpe_index(va)]);
1132 /* Return a pointer to the PDP slot that corresponds to a VA */
1133 static __inline pdp_entry_t *
1134 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1136 pml4_entry_t *pml4e;
1139 PG_V = pmap_valid_bit(pmap);
1140 pml4e = pmap_pml4e(pmap, va);
1141 if ((*pml4e & PG_V) == 0)
1143 return (pmap_pml4e_to_pdpe(pml4e, va));
1146 /* Return a pointer to the PD slot that corresponds to a VA */
1147 static __inline pd_entry_t *
1148 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1152 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1153 return (&pde[pmap_pde_index(va)]);
1156 /* Return a pointer to the PD slot that corresponds to a VA */
1157 static __inline pd_entry_t *
1158 pmap_pde(pmap_t pmap, vm_offset_t va)
1163 PG_V = pmap_valid_bit(pmap);
1164 pdpe = pmap_pdpe(pmap, va);
1165 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1167 return (pmap_pdpe_to_pde(pdpe, va));
1170 /* Return a pointer to the PT slot that corresponds to a VA */
1171 static __inline pt_entry_t *
1172 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1176 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1177 return (&pte[pmap_pte_index(va)]);
1180 /* Return a pointer to the PT slot that corresponds to a VA */
1181 static __inline pt_entry_t *
1182 pmap_pte(pmap_t pmap, vm_offset_t va)
1187 PG_V = pmap_valid_bit(pmap);
1188 pde = pmap_pde(pmap, va);
1189 if (pde == NULL || (*pde & PG_V) == 0)
1191 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1192 return ((pt_entry_t *)pde);
1193 return (pmap_pde_to_pte(pde, va));
1196 static __inline void
1197 pmap_resident_count_inc(pmap_t pmap, int count)
1200 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1201 pmap->pm_stats.resident_count += count;
1204 static __inline void
1205 pmap_resident_count_dec(pmap_t pmap, int count)
1208 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1209 KASSERT(pmap->pm_stats.resident_count >= count,
1210 ("pmap %p resident count underflow %ld %d", pmap,
1211 pmap->pm_stats.resident_count, count));
1212 pmap->pm_stats.resident_count -= count;
1215 PMAP_INLINE pt_entry_t *
1216 vtopte(vm_offset_t va)
1218 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1220 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1222 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1225 static __inline pd_entry_t *
1226 vtopde(vm_offset_t va)
1228 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1230 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1232 return (PDmap + ((va >> PDRSHIFT) & mask));
1236 allocpages(vm_paddr_t *firstaddr, int n)
1241 bzero((void *)ret, n * PAGE_SIZE);
1242 *firstaddr += n * PAGE_SIZE;
1246 CTASSERT(powerof2(NDMPML4E));
1248 /* number of kernel PDP slots */
1249 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1252 nkpt_init(vm_paddr_t addr)
1259 pt_pages = howmany(addr, 1 << PDRSHIFT);
1260 pt_pages += NKPDPE(pt_pages);
1263 * Add some slop beyond the bare minimum required for bootstrapping
1266 * This is quite important when allocating KVA for kernel modules.
1267 * The modules are required to be linked in the negative 2GB of
1268 * the address space. If we run out of KVA in this region then
1269 * pmap_growkernel() will need to allocate page table pages to map
1270 * the entire 512GB of KVA space which is an unnecessary tax on
1273 * Secondly, device memory mapped as part of setting up the low-
1274 * level console(s) is taken from KVA, starting at virtual_avail.
1275 * This is because cninit() is called after pmap_bootstrap() but
1276 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1279 pt_pages += 32; /* 64MB additional slop. */
1285 * Returns the proper write/execute permission for a physical page that is
1286 * part of the initial boot allocations.
1288 * If the page has kernel text, it is marked as read-only. If the page has
1289 * kernel read-only data, it is marked as read-only/not-executable. If the
1290 * page has only read-write data, it is marked as read-write/not-executable.
1291 * If the page is below/above the kernel range, it is marked as read-write.
1293 * This function operates on 2M pages, since we map the kernel space that
1296 * Note that this doesn't currently provide any protection for modules.
1298 static inline pt_entry_t
1299 bootaddr_rwx(vm_paddr_t pa)
1303 * Everything in the same 2M page as the start of the kernel
1304 * should be static. On the other hand, things in the same 2M
1305 * page as the end of the kernel could be read-write/executable,
1306 * as the kernel image is not guaranteed to end on a 2M boundary.
1308 if (pa < trunc_2mpage(btext - KERNBASE) ||
1309 pa >= trunc_2mpage(_end - KERNBASE))
1312 * The linker should ensure that the read-only and read-write
1313 * portions don't share the same 2M page, so this shouldn't
1314 * impact read-only data. However, in any case, any page with
1315 * read-write data needs to be read-write.
1317 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1318 return (X86_PG_RW | pg_nx);
1320 * Mark any 2M page containing kernel text as read-only. Mark
1321 * other pages with read-only data as read-only and not executable.
1322 * (It is likely a small portion of the read-only data section will
1323 * be marked as read-only, but executable. This should be acceptable
1324 * since the read-only protection will keep the data from changing.)
1325 * Note that fixups to the .text section will still work until we
1328 if (pa < round_2mpage(etext - KERNBASE))
1334 create_pagetables(vm_paddr_t *firstaddr)
1336 int i, j, ndm1g, nkpdpe, nkdmpde;
1341 uint64_t DMPDkernphys;
1343 /* Allocate page table pages for the direct map */
1344 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1345 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1347 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1348 if (ndmpdpphys > NDMPML4E) {
1350 * Each NDMPML4E allows 512 GB, so limit to that,
1351 * and then readjust ndmpdp and ndmpdpphys.
1353 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1354 Maxmem = atop(NDMPML4E * NBPML4);
1355 ndmpdpphys = NDMPML4E;
1356 ndmpdp = NDMPML4E * NPDEPG;
1358 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1360 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1362 * Calculate the number of 1G pages that will fully fit in
1365 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1368 * Allocate 2M pages for the kernel. These will be used in
1369 * place of the first one or more 1G pages from ndm1g.
1371 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1372 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1375 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1376 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1378 /* Allocate pages */
1379 KPML4phys = allocpages(firstaddr, 1);
1380 KPDPphys = allocpages(firstaddr, NKPML4E);
1383 * Allocate the initial number of kernel page table pages required to
1384 * bootstrap. We defer this until after all memory-size dependent
1385 * allocations are done (e.g. direct map), so that we don't have to
1386 * build in too much slop in our estimate.
1388 * Note that when NKPML4E > 1, we have an empty page underneath
1389 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1390 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1392 nkpt_init(*firstaddr);
1393 nkpdpe = NKPDPE(nkpt);
1395 KPTphys = allocpages(firstaddr, nkpt);
1396 KPDphys = allocpages(firstaddr, nkpdpe);
1398 /* Fill in the underlying page table pages */
1399 /* XXX not fully used, underneath 2M pages */
1400 pt_p = (pt_entry_t *)KPTphys;
1401 for (i = 0; ptoa(i) < *firstaddr; i++)
1402 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
1404 /* Now map the page tables at their location within PTmap */
1405 pd_p = (pd_entry_t *)KPDphys;
1406 for (i = 0; i < nkpt; i++)
1407 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1409 /* Map from zero to end of allocations under 2M pages */
1410 /* This replaces some of the KPTphys entries above */
1411 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1412 /* Preset PG_M and PG_A because demotion expects it. */
1413 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1414 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1417 * Because we map the physical blocks in 2M pages, adjust firstaddr
1418 * to record the physical blocks we've actually mapped into kernel
1419 * virtual address space.
1421 *firstaddr = round_2mpage(*firstaddr);
1423 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1424 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1425 for (i = 0; i < nkpdpe; i++)
1426 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1429 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1430 * the end of physical memory is not aligned to a 1GB page boundary,
1431 * then the residual physical memory is mapped with 2MB pages. Later,
1432 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1433 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1434 * that are partially used.
1436 pd_p = (pd_entry_t *)DMPDphys;
1437 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1438 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1439 /* Preset PG_M and PG_A because demotion expects it. */
1440 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1441 X86_PG_M | X86_PG_A | pg_nx;
1443 pdp_p = (pdp_entry_t *)DMPDPphys;
1444 for (i = 0; i < ndm1g; i++) {
1445 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1446 /* Preset PG_M and PG_A because demotion expects it. */
1447 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1448 X86_PG_M | X86_PG_A | pg_nx;
1450 for (j = 0; i < ndmpdp; i++, j++) {
1451 pdp_p[i] = DMPDphys + ptoa(j);
1452 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1456 * Instead of using a 1G page for the memory containing the kernel,
1457 * use 2M pages with appropriate permissions. (If using 1G pages,
1458 * this will partially overwrite the PDPEs above.)
1461 pd_p = (pd_entry_t *)DMPDkernphys;
1462 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1463 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1464 X86_PG_M | X86_PG_A | pg_nx |
1465 bootaddr_rwx(i << PDRSHIFT);
1466 for (i = 0; i < nkdmpde; i++)
1467 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1471 /* And recursively map PML4 to itself in order to get PTmap */
1472 p4_p = (pml4_entry_t *)KPML4phys;
1473 p4_p[PML4PML4I] = KPML4phys;
1474 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1476 /* Connect the Direct Map slot(s) up to the PML4. */
1477 for (i = 0; i < ndmpdpphys; i++) {
1478 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1479 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1482 /* Connect the KVA slots up to the PML4 */
1483 for (i = 0; i < NKPML4E; i++) {
1484 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1485 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1490 * Bootstrap the system enough to run with virtual memory.
1492 * On amd64 this is called after mapping has already been enabled
1493 * and just syncs the pmap module with what has already been done.
1494 * [We can't call it easily with mapping off since the kernel is not
1495 * mapped with PA == VA, hence we would have to relocate every address
1496 * from the linked base (virtual) address "KERNBASE" to the actual
1497 * (physical) address starting relative to 0]
1500 pmap_bootstrap(vm_paddr_t *firstaddr)
1508 KERNend = *firstaddr;
1509 res = atop(KERNend - (vm_paddr_t)kernphys);
1515 * Create an initial set of page tables to run the kernel in.
1517 create_pagetables(firstaddr);
1520 * Add a physical memory segment (vm_phys_seg) corresponding to the
1521 * preallocated kernel page table pages so that vm_page structures
1522 * representing these pages will be created. The vm_page structures
1523 * are required for promotion of the corresponding kernel virtual
1524 * addresses to superpage mappings.
1526 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1528 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1529 virtual_end = VM_MAX_KERNEL_ADDRESS;
1532 * Enable PG_G global pages, then switch to the kernel page
1533 * table from the bootstrap page table. After the switch, it
1534 * is possible to enable SMEP and SMAP since PG_U bits are
1540 load_cr3(KPML4phys);
1541 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1543 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1548 * Initialize the kernel pmap (which is statically allocated).
1549 * Count bootstrap data as being resident in case any of this data is
1550 * later unmapped (using pmap_remove()) and freed.
1552 PMAP_LOCK_INIT(kernel_pmap);
1553 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1554 kernel_pmap->pm_cr3 = KPML4phys;
1555 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1556 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1557 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1558 kernel_pmap->pm_stats.resident_count = res;
1559 kernel_pmap->pm_flags = pmap_flags;
1562 * Initialize the TLB invalidations generation number lock.
1564 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1567 * Reserve some special page table entries/VA space for temporary
1570 #define SYSMAP(c, p, v, n) \
1571 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1577 * Crashdump maps. The first page is reused as CMAP1 for the
1580 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1581 CADDR1 = crashdumpmap;
1586 * Initialize the PAT MSR.
1587 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1588 * side-effect, invalidates stale PG_G TLB entries that might
1589 * have been created in our pre-boot environment.
1593 /* Initialize TLB Context Id. */
1594 if (pmap_pcid_enabled) {
1595 for (i = 0; i < MAXCPU; i++) {
1596 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1597 kernel_pmap->pm_pcids[i].pm_gen = 1;
1601 * PMAP_PCID_KERN + 1 is used for initialization of
1602 * proc0 pmap. The pmap' pcid state might be used by
1603 * EFIRT entry before first context switch, so it
1604 * needs to be valid.
1606 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1607 PCPU_SET(pcid_gen, 1);
1610 * pcpu area for APs is zeroed during AP startup.
1611 * pc_pcid_next and pc_pcid_gen are initialized by AP
1612 * during pcpu setup.
1614 load_cr4(rcr4() | CR4_PCIDE);
1619 * Setup the PAT MSR.
1628 /* Bail if this CPU doesn't implement PAT. */
1629 if ((cpu_feature & CPUID_PAT) == 0)
1632 /* Set default PAT index table. */
1633 for (i = 0; i < PAT_INDEX_SIZE; i++)
1635 pat_index[PAT_WRITE_BACK] = 0;
1636 pat_index[PAT_WRITE_THROUGH] = 1;
1637 pat_index[PAT_UNCACHEABLE] = 3;
1638 pat_index[PAT_WRITE_COMBINING] = 6;
1639 pat_index[PAT_WRITE_PROTECTED] = 5;
1640 pat_index[PAT_UNCACHED] = 2;
1643 * Initialize default PAT entries.
1644 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1645 * Program 5 and 6 as WP and WC.
1647 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1648 * mapping for a 2M page uses a PAT value with the bit 3 set due
1649 * to its overload with PG_PS.
1651 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1652 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1653 PAT_VALUE(2, PAT_UNCACHED) |
1654 PAT_VALUE(3, PAT_UNCACHEABLE) |
1655 PAT_VALUE(4, PAT_WRITE_BACK) |
1656 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1657 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1658 PAT_VALUE(7, PAT_UNCACHEABLE);
1662 load_cr4(cr4 & ~CR4_PGE);
1664 /* Disable caches (CD = 1, NW = 0). */
1666 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1668 /* Flushes caches and TLBs. */
1672 /* Update PAT and index table. */
1673 wrmsr(MSR_PAT, pat_msr);
1675 /* Flush caches and TLBs again. */
1679 /* Restore caches and PGE. */
1685 * Initialize a vm_page's machine-dependent fields.
1688 pmap_page_init(vm_page_t m)
1691 TAILQ_INIT(&m->md.pv_list);
1692 m->md.pat_mode = PAT_WRITE_BACK;
1696 * Initialize the pmap module.
1697 * Called by vm_init, to initialize any structures that the pmap
1698 * system needs to map virtual memory.
1703 struct pmap_preinit_mapping *ppim;
1706 int error, i, pv_npg, ret, skz63;
1708 /* L1TF, reserve page @0 unconditionally */
1709 vm_page_blacklist_add(0, bootverbose);
1711 /* Detect bare-metal Skylake Server and Skylake-X. */
1712 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1713 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1715 * Skylake-X errata SKZ63. Processor May Hang When
1716 * Executing Code In an HLE Transaction Region between
1717 * 40000000H and 403FFFFFH.
1719 * Mark the pages in the range as preallocated. It
1720 * seems to be impossible to distinguish between
1721 * Skylake Server and Skylake X.
1724 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1727 printf("SKZ63: skipping 4M RAM starting "
1728 "at physical 1G\n");
1729 for (i = 0; i < atop(0x400000); i++) {
1730 ret = vm_page_blacklist_add(0x40000000 +
1732 if (!ret && bootverbose)
1733 printf("page at %#lx already used\n",
1734 0x40000000 + ptoa(i));
1740 * Initialize the vm page array entries for the kernel pmap's
1743 PMAP_LOCK(kernel_pmap);
1744 for (i = 0; i < nkpt; i++) {
1745 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1746 KASSERT(mpte >= vm_page_array &&
1747 mpte < &vm_page_array[vm_page_array_size],
1748 ("pmap_init: page table page is out of range"));
1749 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1750 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1751 mpte->wire_count = 1;
1752 if (i << PDRSHIFT < KERNend &&
1753 pmap_insert_pt_page(kernel_pmap, mpte))
1754 panic("pmap_init: pmap_insert_pt_page failed");
1756 PMAP_UNLOCK(kernel_pmap);
1760 * If the kernel is running on a virtual machine, then it must assume
1761 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1762 * be prepared for the hypervisor changing the vendor and family that
1763 * are reported by CPUID. Consequently, the workaround for AMD Family
1764 * 10h Erratum 383 is enabled if the processor's feature set does not
1765 * include at least one feature that is only supported by older Intel
1766 * or newer AMD processors.
1768 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1769 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1770 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1772 workaround_erratum383 = 1;
1775 * Are large page mappings enabled?
1777 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1778 if (pg_ps_enabled) {
1779 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1780 ("pmap_init: can't assign to pagesizes[1]"));
1781 pagesizes[1] = NBPDR;
1785 * Initialize the pv chunk list mutex.
1787 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1790 * Initialize the pool of pv list locks.
1792 for (i = 0; i < NPV_LIST_LOCKS; i++)
1793 rw_init(&pv_list_locks[i], "pmap pv list");
1796 * Calculate the size of the pv head table for superpages.
1798 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1801 * Allocate memory for the pv head table for superpages.
1803 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1805 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1806 for (i = 0; i < pv_npg; i++)
1807 TAILQ_INIT(&pv_table[i].pv_list);
1808 TAILQ_INIT(&pv_dummy.pv_list);
1810 pmap_initialized = 1;
1811 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1812 ppim = pmap_preinit_mapping + i;
1815 /* Make the direct map consistent */
1816 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1817 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1818 ppim->sz, ppim->mode);
1822 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1823 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1826 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1827 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1828 (vmem_addr_t *)&qframe);
1830 panic("qframe allocation failed");
1833 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1834 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1835 lm_ents = LMEPML4I - LMSPML4I + 1;
1837 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1838 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1840 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1841 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1842 if (large_vmem == NULL) {
1843 printf("pmap: cannot create large map\n");
1846 for (i = 0; i < lm_ents; i++) {
1847 m = pmap_large_map_getptp_unlocked();
1848 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1849 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1855 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1856 "2MB page mapping counters");
1858 static u_long pmap_pde_demotions;
1859 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1860 &pmap_pde_demotions, 0, "2MB page demotions");
1862 static u_long pmap_pde_mappings;
1863 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1864 &pmap_pde_mappings, 0, "2MB page mappings");
1866 static u_long pmap_pde_p_failures;
1867 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1868 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1870 static u_long pmap_pde_promotions;
1871 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1872 &pmap_pde_promotions, 0, "2MB page promotions");
1874 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1875 "1GB page mapping counters");
1877 static u_long pmap_pdpe_demotions;
1878 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1879 &pmap_pdpe_demotions, 0, "1GB page demotions");
1881 /***************************************************
1882 * Low level helper routines.....
1883 ***************************************************/
1886 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1888 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1890 switch (pmap->pm_type) {
1893 /* Verify that both PAT bits are not set at the same time */
1894 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1895 ("Invalid PAT bits in entry %#lx", entry));
1897 /* Swap the PAT bits if one of them is set */
1898 if ((entry & x86_pat_bits) != 0)
1899 entry ^= x86_pat_bits;
1903 * Nothing to do - the memory attributes are represented
1904 * the same way for regular pages and superpages.
1908 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1915 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1918 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1919 pat_index[(int)mode] >= 0);
1923 * Determine the appropriate bits to set in a PTE or PDE for a specified
1927 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1929 int cache_bits, pat_flag, pat_idx;
1931 if (!pmap_is_valid_memattr(pmap, mode))
1932 panic("Unknown caching mode %d\n", mode);
1934 switch (pmap->pm_type) {
1937 /* The PAT bit is different for PTE's and PDE's. */
1938 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1940 /* Map the caching mode to a PAT index. */
1941 pat_idx = pat_index[mode];
1943 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1946 cache_bits |= pat_flag;
1948 cache_bits |= PG_NC_PCD;
1950 cache_bits |= PG_NC_PWT;
1954 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1958 panic("unsupported pmap type %d", pmap->pm_type);
1961 return (cache_bits);
1965 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1969 switch (pmap->pm_type) {
1972 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1975 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1978 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1985 pmap_ps_enabled(pmap_t pmap)
1988 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1992 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1995 switch (pmap->pm_type) {
2002 * This is a little bogus since the generation number is
2003 * supposed to be bumped up when a region of the address
2004 * space is invalidated in the page tables.
2006 * In this case the old PDE entry is valid but yet we want
2007 * to make sure that any mappings using the old entry are
2008 * invalidated in the TLB.
2010 * The reason this works as expected is because we rendezvous
2011 * "all" host cpus and force any vcpu context to exit as a
2014 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2017 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2019 pde_store(pde, newpde);
2023 * After changing the page size for the specified virtual address in the page
2024 * table, flush the corresponding entries from the processor's TLB. Only the
2025 * calling processor's TLB is affected.
2027 * The calling thread must be pinned to a processor.
2030 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2034 if (pmap_type_guest(pmap))
2037 KASSERT(pmap->pm_type == PT_X86,
2038 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2040 PG_G = pmap_global_bit(pmap);
2042 if ((newpde & PG_PS) == 0)
2043 /* Demotion: flush a specific 2MB page mapping. */
2045 else if ((newpde & PG_G) == 0)
2047 * Promotion: flush every 4KB page mapping from the TLB
2048 * because there are too many to flush individually.
2053 * Promotion: flush every 4KB page mapping from the TLB,
2054 * including any global (PG_G) mappings.
2062 * For SMP, these functions have to use the IPI mechanism for coherence.
2064 * N.B.: Before calling any of the following TLB invalidation functions,
2065 * the calling processor must ensure that all stores updating a non-
2066 * kernel page table are globally performed. Otherwise, another
2067 * processor could cache an old, pre-update entry without being
2068 * invalidated. This can happen one of two ways: (1) The pmap becomes
2069 * active on another processor after its pm_active field is checked by
2070 * one of the following functions but before a store updating the page
2071 * table is globally performed. (2) The pmap becomes active on another
2072 * processor before its pm_active field is checked but due to
2073 * speculative loads one of the following functions stills reads the
2074 * pmap as inactive on the other processor.
2076 * The kernel page table is exempt because its pm_active field is
2077 * immutable. The kernel page table is always active on every
2082 * Interrupt the cpus that are executing in the guest context.
2083 * This will force the vcpu to exit and the cached EPT mappings
2084 * will be invalidated by the host before the next vmresume.
2086 static __inline void
2087 pmap_invalidate_ept(pmap_t pmap)
2092 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2093 ("pmap_invalidate_ept: absurd pm_active"));
2096 * The TLB mappings associated with a vcpu context are not
2097 * flushed each time a different vcpu is chosen to execute.
2099 * This is in contrast with a process's vtop mappings that
2100 * are flushed from the TLB on each context switch.
2102 * Therefore we need to do more than just a TLB shootdown on
2103 * the active cpus in 'pmap->pm_active'. To do this we keep
2104 * track of the number of invalidations performed on this pmap.
2106 * Each vcpu keeps a cache of this counter and compares it
2107 * just before a vmresume. If the counter is out-of-date an
2108 * invept will be done to flush stale mappings from the TLB.
2110 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2113 * Force the vcpu to exit and trap back into the hypervisor.
2115 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2116 ipi_selected(pmap->pm_active, ipinum);
2121 pmap_invalidate_cpu_mask(pmap_t pmap)
2124 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2128 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2129 const bool invpcid_works1)
2131 struct invpcid_descr d;
2132 uint64_t kcr3, ucr3;
2136 cpuid = PCPU_GET(cpuid);
2137 if (pmap == PCPU_GET(curpmap)) {
2138 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2140 * Because pm_pcid is recalculated on a
2141 * context switch, we must disable switching.
2142 * Otherwise, we might use a stale value
2146 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2147 if (invpcid_works1) {
2148 d.pcid = pcid | PMAP_PCID_USER_PT;
2151 invpcid(&d, INVPCID_ADDR);
2153 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2154 ucr3 = pmap->pm_ucr3 | pcid |
2155 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2156 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2161 pmap->pm_pcids[cpuid].pm_gen = 0;
2165 pmap->pm_pcids[i].pm_gen = 0;
2169 * The fence is between stores to pm_gen and the read of the
2170 * pm_active mask. We need to ensure that it is impossible
2171 * for us to miss the bit update in pm_active and
2172 * simultaneously observe a non-zero pm_gen in
2173 * pmap_activate_sw(), otherwise TLB update is missed.
2174 * Without the fence, IA32 allows such an outcome. Note that
2175 * pm_active is updated by a locked operation, which provides
2176 * the reciprocal fence.
2178 atomic_thread_fence_seq_cst();
2182 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2185 pmap_invalidate_page_pcid(pmap, va, true);
2189 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2192 pmap_invalidate_page_pcid(pmap, va, false);
2196 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2200 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t),
2204 if (pmap_pcid_enabled)
2205 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2206 pmap_invalidate_page_pcid_noinvpcid);
2207 return (pmap_invalidate_page_nopcid);
2211 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2214 if (pmap_type_guest(pmap)) {
2215 pmap_invalidate_ept(pmap);
2219 KASSERT(pmap->pm_type == PT_X86,
2220 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2223 if (pmap == kernel_pmap) {
2226 if (pmap == PCPU_GET(curpmap))
2228 pmap_invalidate_page_mode(pmap, va);
2230 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2234 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2235 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2238 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2239 const bool invpcid_works1)
2241 struct invpcid_descr d;
2242 uint64_t kcr3, ucr3;
2246 cpuid = PCPU_GET(cpuid);
2247 if (pmap == PCPU_GET(curpmap)) {
2248 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2250 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2251 if (invpcid_works1) {
2252 d.pcid = pcid | PMAP_PCID_USER_PT;
2255 for (; d.addr < eva; d.addr += PAGE_SIZE)
2256 invpcid(&d, INVPCID_ADDR);
2258 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2259 ucr3 = pmap->pm_ucr3 | pcid |
2260 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2261 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2266 pmap->pm_pcids[cpuid].pm_gen = 0;
2270 pmap->pm_pcids[i].pm_gen = 0;
2272 /* See the comment in pmap_invalidate_page_pcid(). */
2273 atomic_thread_fence_seq_cst();
2277 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2281 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2285 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2289 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2293 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2297 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2298 vm_offset_t), static)
2301 if (pmap_pcid_enabled)
2302 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2303 pmap_invalidate_range_pcid_noinvpcid);
2304 return (pmap_invalidate_range_nopcid);
2308 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2312 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2313 pmap_invalidate_all(pmap);
2317 if (pmap_type_guest(pmap)) {
2318 pmap_invalidate_ept(pmap);
2322 KASSERT(pmap->pm_type == PT_X86,
2323 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2326 if (pmap == kernel_pmap) {
2327 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2330 if (pmap == PCPU_GET(curpmap)) {
2331 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2334 pmap_invalidate_range_mode(pmap, sva, eva);
2336 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2341 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2343 struct invpcid_descr d;
2344 uint64_t kcr3, ucr3;
2348 if (pmap == kernel_pmap) {
2349 if (invpcid_works1) {
2350 bzero(&d, sizeof(d));
2351 invpcid(&d, INVPCID_CTXGLOB);
2356 cpuid = PCPU_GET(cpuid);
2357 if (pmap == PCPU_GET(curpmap)) {
2359 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2360 if (invpcid_works1) {
2364 invpcid(&d, INVPCID_CTX);
2365 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2366 d.pcid |= PMAP_PCID_USER_PT;
2367 invpcid(&d, INVPCID_CTX);
2370 kcr3 = pmap->pm_cr3 | pcid;
2371 ucr3 = pmap->pm_ucr3;
2372 if (ucr3 != PMAP_NO_CR3) {
2373 ucr3 |= pcid | PMAP_PCID_USER_PT;
2374 pmap_pti_pcid_invalidate(ucr3, kcr3);
2381 pmap->pm_pcids[cpuid].pm_gen = 0;
2384 pmap->pm_pcids[i].pm_gen = 0;
2387 /* See the comment in pmap_invalidate_page_pcid(). */
2388 atomic_thread_fence_seq_cst();
2392 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2395 pmap_invalidate_all_pcid(pmap, true);
2399 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2402 pmap_invalidate_all_pcid(pmap, false);
2406 pmap_invalidate_all_nopcid(pmap_t pmap)
2409 if (pmap == kernel_pmap)
2411 else if (pmap == PCPU_GET(curpmap))
2415 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t), static)
2418 if (pmap_pcid_enabled)
2419 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2420 pmap_invalidate_all_pcid_noinvpcid);
2421 return (pmap_invalidate_all_nopcid);
2425 pmap_invalidate_all(pmap_t pmap)
2428 if (pmap_type_guest(pmap)) {
2429 pmap_invalidate_ept(pmap);
2433 KASSERT(pmap->pm_type == PT_X86,
2434 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2437 pmap_invalidate_all_mode(pmap);
2438 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2443 pmap_invalidate_cache(void)
2453 cpuset_t invalidate; /* processors that invalidate their TLB */
2458 u_int store; /* processor that updates the PDE */
2462 pmap_update_pde_action(void *arg)
2464 struct pde_action *act = arg;
2466 if (act->store == PCPU_GET(cpuid))
2467 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2471 pmap_update_pde_teardown(void *arg)
2473 struct pde_action *act = arg;
2475 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2476 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2480 * Change the page size for the specified virtual address in a way that
2481 * prevents any possibility of the TLB ever having two entries that map the
2482 * same virtual address using different page sizes. This is the recommended
2483 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2484 * machine check exception for a TLB state that is improperly diagnosed as a
2488 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2490 struct pde_action act;
2491 cpuset_t active, other_cpus;
2495 cpuid = PCPU_GET(cpuid);
2496 other_cpus = all_cpus;
2497 CPU_CLR(cpuid, &other_cpus);
2498 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2501 active = pmap->pm_active;
2503 if (CPU_OVERLAP(&active, &other_cpus)) {
2505 act.invalidate = active;
2509 act.newpde = newpde;
2510 CPU_SET(cpuid, &active);
2511 smp_rendezvous_cpus(active,
2512 smp_no_rendezvous_barrier, pmap_update_pde_action,
2513 pmap_update_pde_teardown, &act);
2515 pmap_update_pde_store(pmap, pde, newpde);
2516 if (CPU_ISSET(cpuid, &active))
2517 pmap_update_pde_invalidate(pmap, va, newpde);
2523 * Normal, non-SMP, invalidation functions.
2526 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2528 struct invpcid_descr d;
2529 uint64_t kcr3, ucr3;
2532 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2536 KASSERT(pmap->pm_type == PT_X86,
2537 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2539 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2541 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2542 pmap->pm_ucr3 != PMAP_NO_CR3) {
2544 pcid = pmap->pm_pcids[0].pm_pcid;
2545 if (invpcid_works) {
2546 d.pcid = pcid | PMAP_PCID_USER_PT;
2549 invpcid(&d, INVPCID_ADDR);
2551 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2552 ucr3 = pmap->pm_ucr3 | pcid |
2553 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2554 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2558 } else if (pmap_pcid_enabled)
2559 pmap->pm_pcids[0].pm_gen = 0;
2563 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2565 struct invpcid_descr d;
2567 uint64_t kcr3, ucr3;
2569 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2573 KASSERT(pmap->pm_type == PT_X86,
2574 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2576 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2577 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2579 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2580 pmap->pm_ucr3 != PMAP_NO_CR3) {
2582 if (invpcid_works) {
2583 d.pcid = pmap->pm_pcids[0].pm_pcid |
2587 for (; d.addr < eva; d.addr += PAGE_SIZE)
2588 invpcid(&d, INVPCID_ADDR);
2590 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2591 pm_pcid | CR3_PCID_SAVE;
2592 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2593 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2594 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2598 } else if (pmap_pcid_enabled) {
2599 pmap->pm_pcids[0].pm_gen = 0;
2604 pmap_invalidate_all(pmap_t pmap)
2606 struct invpcid_descr d;
2607 uint64_t kcr3, ucr3;
2609 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2613 KASSERT(pmap->pm_type == PT_X86,
2614 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2616 if (pmap == kernel_pmap) {
2617 if (pmap_pcid_enabled && invpcid_works) {
2618 bzero(&d, sizeof(d));
2619 invpcid(&d, INVPCID_CTXGLOB);
2623 } else if (pmap == PCPU_GET(curpmap)) {
2624 if (pmap_pcid_enabled) {
2626 if (invpcid_works) {
2627 d.pcid = pmap->pm_pcids[0].pm_pcid;
2630 invpcid(&d, INVPCID_CTX);
2631 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2632 d.pcid |= PMAP_PCID_USER_PT;
2633 invpcid(&d, INVPCID_CTX);
2636 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2637 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2638 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2639 0].pm_pcid | PMAP_PCID_USER_PT;
2640 pmap_pti_pcid_invalidate(ucr3, kcr3);
2648 } else if (pmap_pcid_enabled) {
2649 pmap->pm_pcids[0].pm_gen = 0;
2654 pmap_invalidate_cache(void)
2661 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2664 pmap_update_pde_store(pmap, pde, newpde);
2665 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2666 pmap_update_pde_invalidate(pmap, va, newpde);
2668 pmap->pm_pcids[0].pm_gen = 0;
2673 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2677 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2678 * by a promotion that did not invalidate the 512 4KB page mappings
2679 * that might exist in the TLB. Consequently, at this point, the TLB
2680 * may hold both 4KB and 2MB page mappings for the address range [va,
2681 * va + NBPDR). Therefore, the entire range must be invalidated here.
2682 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2683 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2684 * single INVLPG suffices to invalidate the 2MB page mapping from the
2687 if ((pde & PG_PROMOTED) != 0)
2688 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2690 pmap_invalidate_page(pmap, va);
2693 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2694 (vm_offset_t sva, vm_offset_t eva), static)
2697 if ((cpu_feature & CPUID_SS) != 0)
2698 return (pmap_invalidate_cache_range_selfsnoop);
2699 if ((cpu_feature & CPUID_CLFSH) != 0)
2700 return (pmap_force_invalidate_cache_range);
2701 return (pmap_invalidate_cache_range_all);
2704 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2707 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2710 KASSERT((sva & PAGE_MASK) == 0,
2711 ("pmap_invalidate_cache_range: sva not page-aligned"));
2712 KASSERT((eva & PAGE_MASK) == 0,
2713 ("pmap_invalidate_cache_range: eva not page-aligned"));
2717 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2720 pmap_invalidate_cache_range_check_align(sva, eva);
2724 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2727 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2730 * XXX: Some CPUs fault, hang, or trash the local APIC
2731 * registers if we use CLFLUSH on the local APIC range. The
2732 * local APIC is always uncached, so we don't need to flush
2733 * for that range anyway.
2735 if (pmap_kextract(sva) == lapic_paddr)
2738 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2740 * Do per-cache line flush. Use the sfence
2741 * instruction to insure that previous stores are
2742 * included in the write-back. The processor
2743 * propagates flush to other processors in the cache
2747 for (; sva < eva; sva += cpu_clflush_line_size)
2752 * Writes are ordered by CLFLUSH on Intel CPUs.
2754 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2756 for (; sva < eva; sva += cpu_clflush_line_size)
2758 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2764 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2767 pmap_invalidate_cache_range_check_align(sva, eva);
2768 pmap_invalidate_cache();
2772 * Remove the specified set of pages from the data and instruction caches.
2774 * In contrast to pmap_invalidate_cache_range(), this function does not
2775 * rely on the CPU's self-snoop feature, because it is intended for use
2776 * when moving pages into a different cache domain.
2779 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2781 vm_offset_t daddr, eva;
2785 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2786 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2787 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2788 pmap_invalidate_cache();
2792 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2794 for (i = 0; i < count; i++) {
2795 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2796 eva = daddr + PAGE_SIZE;
2797 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2806 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2812 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2815 pmap_invalidate_cache_range_check_align(sva, eva);
2817 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2818 pmap_force_invalidate_cache_range(sva, eva);
2822 /* See comment in pmap_force_invalidate_cache_range(). */
2823 if (pmap_kextract(sva) == lapic_paddr)
2827 for (; sva < eva; sva += cpu_clflush_line_size)
2833 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2837 int error, pte_bits;
2839 KASSERT((spa & PAGE_MASK) == 0,
2840 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2841 KASSERT((epa & PAGE_MASK) == 0,
2842 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2844 if (spa < dmaplimit) {
2845 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2847 if (dmaplimit >= epa)
2852 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
2854 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2856 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
2857 pte = vtopte(vaddr);
2858 for (; spa < epa; spa += PAGE_SIZE) {
2860 pte_store(pte, spa | pte_bits);
2862 /* XXXKIB sfences inside flush_cache_range are excessive */
2863 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
2866 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
2870 * Routine: pmap_extract
2872 * Extract the physical page address associated
2873 * with the given map/virtual_address pair.
2876 pmap_extract(pmap_t pmap, vm_offset_t va)
2880 pt_entry_t *pte, PG_V;
2884 PG_V = pmap_valid_bit(pmap);
2886 pdpe = pmap_pdpe(pmap, va);
2887 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2888 if ((*pdpe & PG_PS) != 0)
2889 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2891 pde = pmap_pdpe_to_pde(pdpe, va);
2892 if ((*pde & PG_V) != 0) {
2893 if ((*pde & PG_PS) != 0) {
2894 pa = (*pde & PG_PS_FRAME) |
2897 pte = pmap_pde_to_pte(pde, va);
2898 pa = (*pte & PG_FRAME) |
2909 * Routine: pmap_extract_and_hold
2911 * Atomically extract and hold the physical page
2912 * with the given pmap and virtual address pair
2913 * if that mapping permits the given protection.
2916 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2918 pd_entry_t pde, *pdep;
2919 pt_entry_t pte, PG_RW, PG_V;
2925 PG_RW = pmap_rw_bit(pmap);
2926 PG_V = pmap_valid_bit(pmap);
2929 pdep = pmap_pde(pmap, va);
2930 if (pdep != NULL && (pde = *pdep)) {
2932 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2933 if (vm_page_pa_tryrelock(pmap, (pde &
2934 PG_PS_FRAME) | (va & PDRMASK), &pa))
2936 m = PHYS_TO_VM_PAGE(pa);
2939 pte = *pmap_pde_to_pte(pdep, va);
2941 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2942 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2945 m = PHYS_TO_VM_PAGE(pa);
2957 pmap_kextract(vm_offset_t va)
2962 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2963 pa = DMAP_TO_PHYS(va);
2967 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2970 * Beware of a concurrent promotion that changes the
2971 * PDE at this point! For example, vtopte() must not
2972 * be used to access the PTE because it would use the
2973 * new PDE. It is, however, safe to use the old PDE
2974 * because the page table page is preserved by the
2977 pa = *pmap_pde_to_pte(&pde, va);
2978 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2984 /***************************************************
2985 * Low level mapping routines.....
2986 ***************************************************/
2989 * Add a wired page to the kva.
2990 * Note: not SMP coherent.
2993 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2998 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
3001 static __inline void
3002 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3008 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3009 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
3013 * Remove a page from the kernel pagetables.
3014 * Note: not SMP coherent.
3017 pmap_kremove(vm_offset_t va)
3026 * Used to map a range of physical addresses into kernel
3027 * virtual address space.
3029 * The value passed in '*virt' is a suggested virtual address for
3030 * the mapping. Architectures which can support a direct-mapped
3031 * physical to virtual region can return the appropriate address
3032 * within that region, leaving '*virt' unchanged. Other
3033 * architectures should map the pages starting at '*virt' and
3034 * update '*virt' with the first usable address after the mapped
3038 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3040 return PHYS_TO_DMAP(start);
3045 * Add a list of wired pages to the kva
3046 * this routine is only used for temporary
3047 * kernel mappings that do not need to have
3048 * page modification or references recorded.
3049 * Note that old mappings are simply written
3050 * over. The page *must* be wired.
3051 * Note: SMP coherent. Uses a ranged shootdown IPI.
3054 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3056 pt_entry_t *endpte, oldpte, pa, *pte;
3062 endpte = pte + count;
3063 while (pte < endpte) {
3065 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3066 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3067 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3069 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3073 if (__predict_false((oldpte & X86_PG_V) != 0))
3074 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3079 * This routine tears out page mappings from the
3080 * kernel -- it is meant only for temporary mappings.
3081 * Note: SMP coherent. Uses a ranged shootdown IPI.
3084 pmap_qremove(vm_offset_t sva, int count)
3089 while (count-- > 0) {
3090 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3094 pmap_invalidate_range(kernel_pmap, sva, va);
3097 /***************************************************
3098 * Page table page management routines.....
3099 ***************************************************/
3101 * Schedule the specified unused page table page to be freed. Specifically,
3102 * add the page to the specified list of pages that will be released to the
3103 * physical memory manager after the TLB has been updated.
3105 static __inline void
3106 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3107 boolean_t set_PG_ZERO)
3111 m->flags |= PG_ZERO;
3113 m->flags &= ~PG_ZERO;
3114 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3118 * Inserts the specified page table page into the specified pmap's collection
3119 * of idle page table pages. Each of a pmap's page table pages is responsible
3120 * for mapping a distinct range of virtual addresses. The pmap's collection is
3121 * ordered by this virtual address range.
3124 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
3127 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3128 return (vm_radix_insert(&pmap->pm_root, mpte));
3132 * Removes the page table page mapping the specified virtual address from the
3133 * specified pmap's collection of idle page table pages, and returns it.
3134 * Otherwise, returns NULL if there is no page table page corresponding to the
3135 * specified virtual address.
3137 static __inline vm_page_t
3138 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3141 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3142 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3146 * Decrements a page table page's wire count, which is used to record the
3147 * number of valid page table entries within the page. If the wire count
3148 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3149 * page table page was unmapped and FALSE otherwise.
3151 static inline boolean_t
3152 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3156 if (m->wire_count == 0) {
3157 _pmap_unwire_ptp(pmap, va, m, free);
3164 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3167 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3169 * unmap the page table page
3171 if (m->pindex >= (NUPDE + NUPDPE)) {
3174 pml4 = pmap_pml4e(pmap, va);
3176 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3177 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3180 } else if (m->pindex >= NUPDE) {
3183 pdp = pmap_pdpe(pmap, va);
3188 pd = pmap_pde(pmap, va);
3191 pmap_resident_count_dec(pmap, 1);
3192 if (m->pindex < NUPDE) {
3193 /* We just released a PT, unhold the matching PD */
3196 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3197 pmap_unwire_ptp(pmap, va, pdpg, free);
3199 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3200 /* We just released a PD, unhold the matching PDP */
3203 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3204 pmap_unwire_ptp(pmap, va, pdppg, free);
3208 * Put page on a list so that it is released after
3209 * *ALL* TLB shootdown is done
3211 pmap_add_delayed_free_list(m, free, TRUE);
3215 * After removing a page table entry, this routine is used to
3216 * conditionally free the page, and manage the hold/wire counts.
3219 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3220 struct spglist *free)
3224 if (va >= VM_MAXUSER_ADDRESS)
3226 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3227 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3228 return (pmap_unwire_ptp(pmap, va, mpte, free));
3232 pmap_pinit0(pmap_t pmap)
3238 PMAP_LOCK_INIT(pmap);
3239 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3240 pmap->pm_pml4u = NULL;
3241 pmap->pm_cr3 = KPML4phys;
3242 /* hack to keep pmap_pti_pcid_invalidate() alive */
3243 pmap->pm_ucr3 = PMAP_NO_CR3;
3244 pmap->pm_root.rt_root = 0;
3245 CPU_ZERO(&pmap->pm_active);
3246 TAILQ_INIT(&pmap->pm_pvchunk);
3247 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3248 pmap->pm_flags = pmap_flags;
3250 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3251 pmap->pm_pcids[i].pm_gen = 1;
3253 pmap_activate_boot(pmap);
3258 p->p_md.md_flags |= P_MD_KPTI;
3261 pmap_thread_init_invl_gen(td);
3263 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3264 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3265 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3271 pmap_pinit_pml4(vm_page_t pml4pg)
3273 pml4_entry_t *pm_pml4;
3276 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3278 /* Wire in kernel global address entries. */
3279 for (i = 0; i < NKPML4E; i++) {
3280 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3283 for (i = 0; i < ndmpdpphys; i++) {
3284 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3288 /* install self-referential address mapping entry(s) */
3289 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3290 X86_PG_A | X86_PG_M;
3292 /* install large map entries if configured */
3293 for (i = 0; i < lm_ents; i++)
3294 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3298 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3300 pml4_entry_t *pm_pml4;
3303 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3304 for (i = 0; i < NPML4EPG; i++)
3305 pm_pml4[i] = pti_pml4[i];
3309 * Initialize a preallocated and zeroed pmap structure,
3310 * such as one in a vmspace structure.
3313 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3315 vm_page_t pml4pg, pml4pgu;
3316 vm_paddr_t pml4phys;
3320 * allocate the page directory page
3322 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3323 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3325 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3326 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3328 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3329 pmap->pm_pcids[i].pm_gen = 0;
3331 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3332 pmap->pm_ucr3 = PMAP_NO_CR3;
3333 pmap->pm_pml4u = NULL;
3335 pmap->pm_type = pm_type;
3336 if ((pml4pg->flags & PG_ZERO) == 0)
3337 pagezero(pmap->pm_pml4);
3340 * Do not install the host kernel mappings in the nested page
3341 * tables. These mappings are meaningless in the guest physical
3343 * Install minimal kernel mappings in PTI case.
3345 if (pm_type == PT_X86) {
3346 pmap->pm_cr3 = pml4phys;
3347 pmap_pinit_pml4(pml4pg);
3348 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3349 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3350 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3351 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3352 VM_PAGE_TO_PHYS(pml4pgu));
3353 pmap_pinit_pml4_pti(pml4pgu);
3354 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3356 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3357 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3358 pkru_free_range, pmap, M_NOWAIT);
3362 pmap->pm_root.rt_root = 0;
3363 CPU_ZERO(&pmap->pm_active);
3364 TAILQ_INIT(&pmap->pm_pvchunk);
3365 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3366 pmap->pm_flags = flags;
3367 pmap->pm_eptgen = 0;
3373 pmap_pinit(pmap_t pmap)
3376 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3380 * This routine is called if the desired page table page does not exist.
3382 * If page table page allocation fails, this routine may sleep before
3383 * returning NULL. It sleeps only if a lock pointer was given.
3385 * Note: If a page allocation fails at page table level two or three,
3386 * one or two pages may be held during the wait, only to be released
3387 * afterwards. This conservative approach is easily argued to avoid
3391 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3393 vm_page_t m, pdppg, pdpg;
3394 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3396 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3398 PG_A = pmap_accessed_bit(pmap);
3399 PG_M = pmap_modified_bit(pmap);
3400 PG_V = pmap_valid_bit(pmap);
3401 PG_RW = pmap_rw_bit(pmap);
3404 * Allocate a page table page.
3406 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3407 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3408 if (lockp != NULL) {
3409 RELEASE_PV_LIST_LOCK(lockp);
3411 PMAP_ASSERT_NOT_IN_DI();
3417 * Indicate the need to retry. While waiting, the page table
3418 * page may have been allocated.
3422 if ((m->flags & PG_ZERO) == 0)
3426 * Map the pagetable page into the process address space, if
3427 * it isn't already there.
3430 if (ptepindex >= (NUPDE + NUPDPE)) {
3431 pml4_entry_t *pml4, *pml4u;
3432 vm_pindex_t pml4index;
3434 /* Wire up a new PDPE page */
3435 pml4index = ptepindex - (NUPDE + NUPDPE);
3436 pml4 = &pmap->pm_pml4[pml4index];
3437 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3438 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3440 * PTI: Make all user-space mappings in the
3441 * kernel-mode page table no-execute so that
3442 * we detect any programming errors that leave
3443 * the kernel-mode page table active on return
3446 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3449 pml4u = &pmap->pm_pml4u[pml4index];
3450 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3454 } else if (ptepindex >= NUPDE) {
3455 vm_pindex_t pml4index;
3456 vm_pindex_t pdpindex;
3460 /* Wire up a new PDE page */
3461 pdpindex = ptepindex - NUPDE;
3462 pml4index = pdpindex >> NPML4EPGSHIFT;
3464 pml4 = &pmap->pm_pml4[pml4index];
3465 if ((*pml4 & PG_V) == 0) {
3466 /* Have to allocate a new pdp, recurse */
3467 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3469 vm_page_unwire_noq(m);
3470 vm_page_free_zero(m);
3474 /* Add reference to pdp page */
3475 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3476 pdppg->wire_count++;
3478 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3480 /* Now find the pdp page */
3481 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3482 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3485 vm_pindex_t pml4index;
3486 vm_pindex_t pdpindex;
3491 /* Wire up a new PTE page */
3492 pdpindex = ptepindex >> NPDPEPGSHIFT;
3493 pml4index = pdpindex >> NPML4EPGSHIFT;
3495 /* First, find the pdp and check that its valid. */
3496 pml4 = &pmap->pm_pml4[pml4index];
3497 if ((*pml4 & PG_V) == 0) {
3498 /* Have to allocate a new pd, recurse */
3499 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3501 vm_page_unwire_noq(m);
3502 vm_page_free_zero(m);
3505 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3506 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3508 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3509 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3510 if ((*pdp & PG_V) == 0) {
3511 /* Have to allocate a new pd, recurse */
3512 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3514 vm_page_unwire_noq(m);
3515 vm_page_free_zero(m);
3519 /* Add reference to the pd page */
3520 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3524 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3526 /* Now we know where the page directory page is */
3527 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3528 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3531 pmap_resident_count_inc(pmap, 1);
3537 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3539 vm_pindex_t pdpindex, ptepindex;
3540 pdp_entry_t *pdpe, PG_V;
3543 PG_V = pmap_valid_bit(pmap);
3546 pdpe = pmap_pdpe(pmap, va);
3547 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3548 /* Add a reference to the pd page. */
3549 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3552 /* Allocate a pd page. */
3553 ptepindex = pmap_pde_pindex(va);
3554 pdpindex = ptepindex >> NPDPEPGSHIFT;
3555 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3556 if (pdpg == NULL && lockp != NULL)
3563 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3565 vm_pindex_t ptepindex;
3566 pd_entry_t *pd, PG_V;
3569 PG_V = pmap_valid_bit(pmap);
3572 * Calculate pagetable page index
3574 ptepindex = pmap_pde_pindex(va);
3577 * Get the page directory entry
3579 pd = pmap_pde(pmap, va);
3582 * This supports switching from a 2MB page to a
3585 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3586 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3588 * Invalidation of the 2MB page mapping may have caused
3589 * the deallocation of the underlying PD page.
3596 * If the page table page is mapped, we just increment the
3597 * hold count, and activate it.
3599 if (pd != NULL && (*pd & PG_V) != 0) {
3600 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3604 * Here if the pte page isn't mapped, or if it has been
3607 m = _pmap_allocpte(pmap, ptepindex, lockp);
3608 if (m == NULL && lockp != NULL)
3615 /***************************************************
3616 * Pmap allocation/deallocation routines.
3617 ***************************************************/
3620 * Release any resources held by the given physical map.
3621 * Called when a pmap initialized by pmap_pinit is being released.
3622 * Should only be called if the map contains no valid mappings.
3625 pmap_release(pmap_t pmap)
3630 KASSERT(pmap->pm_stats.resident_count == 0,
3631 ("pmap_release: pmap resident count %ld != 0",
3632 pmap->pm_stats.resident_count));
3633 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3634 ("pmap_release: pmap has reserved page table page(s)"));
3635 KASSERT(CPU_EMPTY(&pmap->pm_active),
3636 ("releasing active pmap %p", pmap));
3638 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3640 for (i = 0; i < NKPML4E; i++) /* KVA */
3641 pmap->pm_pml4[KPML4BASE + i] = 0;
3642 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3643 pmap->pm_pml4[DMPML4I + i] = 0;
3644 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3645 for (i = 0; i < lm_ents; i++) /* Large Map */
3646 pmap->pm_pml4[LMSPML4I + i] = 0;
3648 vm_page_unwire_noq(m);
3649 vm_page_free_zero(m);
3651 if (pmap->pm_pml4u != NULL) {
3652 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3653 vm_page_unwire_noq(m);
3656 if (pmap->pm_type == PT_X86 &&
3657 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3658 rangeset_fini(&pmap->pm_pkru);
3662 kvm_size(SYSCTL_HANDLER_ARGS)
3664 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3666 return sysctl_handle_long(oidp, &ksize, 0, req);
3668 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3669 0, 0, kvm_size, "LU", "Size of KVM");
3672 kvm_free(SYSCTL_HANDLER_ARGS)
3674 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3676 return sysctl_handle_long(oidp, &kfree, 0, req);
3678 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3679 0, 0, kvm_free, "LU", "Amount of KVM free");
3682 * grow the number of kernel page table entries, if needed
3685 pmap_growkernel(vm_offset_t addr)
3689 pd_entry_t *pde, newpdir;
3692 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3695 * Return if "addr" is within the range of kernel page table pages
3696 * that were preallocated during pmap bootstrap. Moreover, leave
3697 * "kernel_vm_end" and the kernel page table as they were.
3699 * The correctness of this action is based on the following
3700 * argument: vm_map_insert() allocates contiguous ranges of the
3701 * kernel virtual address space. It calls this function if a range
3702 * ends after "kernel_vm_end". If the kernel is mapped between
3703 * "kernel_vm_end" and "addr", then the range cannot begin at
3704 * "kernel_vm_end". In fact, its beginning address cannot be less
3705 * than the kernel. Thus, there is no immediate need to allocate
3706 * any new kernel page table pages between "kernel_vm_end" and
3709 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3712 addr = roundup2(addr, NBPDR);
3713 if (addr - 1 >= vm_map_max(kernel_map))
3714 addr = vm_map_max(kernel_map);
3715 while (kernel_vm_end < addr) {
3716 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3717 if ((*pdpe & X86_PG_V) == 0) {
3718 /* We need a new PDP entry */
3719 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3720 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3721 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3723 panic("pmap_growkernel: no memory to grow kernel");
3724 if ((nkpg->flags & PG_ZERO) == 0)
3725 pmap_zero_page(nkpg);
3726 paddr = VM_PAGE_TO_PHYS(nkpg);
3727 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3728 X86_PG_A | X86_PG_M);
3729 continue; /* try again */
3731 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3732 if ((*pde & X86_PG_V) != 0) {
3733 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3734 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3735 kernel_vm_end = vm_map_max(kernel_map);
3741 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3742 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3745 panic("pmap_growkernel: no memory to grow kernel");
3746 if ((nkpg->flags & PG_ZERO) == 0)
3747 pmap_zero_page(nkpg);
3748 paddr = VM_PAGE_TO_PHYS(nkpg);
3749 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3750 pde_store(pde, newpdir);
3752 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3753 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3754 kernel_vm_end = vm_map_max(kernel_map);
3761 /***************************************************
3762 * page management routines.
3763 ***************************************************/
3765 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3766 CTASSERT(_NPCM == 3);
3767 CTASSERT(_NPCPV == 168);
3769 static __inline struct pv_chunk *
3770 pv_to_chunk(pv_entry_t pv)
3773 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3776 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3778 #define PC_FREE0 0xfffffffffffffffful
3779 #define PC_FREE1 0xfffffffffffffffful
3780 #define PC_FREE2 0x000000fffffffffful
3782 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3785 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3787 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3788 "Current number of pv entry chunks");
3789 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3790 "Current number of pv entry chunks allocated");
3791 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3792 "Current number of pv entry chunks frees");
3793 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3794 "Number of times tried to get a chunk page but failed.");
3796 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3797 static int pv_entry_spare;
3799 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3800 "Current number of pv entry frees");
3801 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3802 "Current number of pv entry allocs");
3803 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3804 "Current number of pv entries");
3805 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3806 "Current number of spare pv entries");
3810 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3815 pmap_invalidate_all(pmap);
3816 if (pmap != locked_pmap)
3819 pmap_delayed_invl_finish();
3823 * We are in a serious low memory condition. Resort to
3824 * drastic measures to free some pages so we can allocate
3825 * another pv entry chunk.
3827 * Returns NULL if PV entries were reclaimed from the specified pmap.
3829 * We do not, however, unmap 2mpages because subsequent accesses will
3830 * allocate per-page pv entries until repromotion occurs, thereby
3831 * exacerbating the shortage of free pv entries.
3834 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3836 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3837 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3838 struct md_page *pvh;
3840 pmap_t next_pmap, pmap;
3841 pt_entry_t *pte, tpte;
3842 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3846 struct spglist free;
3848 int bit, field, freed;
3850 static int active_reclaims = 0;
3852 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3853 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3856 PG_G = PG_A = PG_M = PG_RW = 0;
3858 bzero(&pc_marker_b, sizeof(pc_marker_b));
3859 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3860 pc_marker = (struct pv_chunk *)&pc_marker_b;
3861 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3864 * A delayed invalidation block should already be active if
3865 * pmap_advise() or pmap_remove() called this function by way
3866 * of pmap_demote_pde_locked().
3868 start_di = pmap_not_in_di();
3870 mtx_lock(&pv_chunks_mutex);
3872 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3873 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3874 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3875 SLIST_EMPTY(&free)) {
3876 next_pmap = pc->pc_pmap;
3877 if (next_pmap == NULL) {
3879 * The next chunk is a marker. However, it is
3880 * not our marker, so active_reclaims must be
3881 * > 1. Consequently, the next_chunk code
3882 * will not rotate the pv_chunks list.
3886 mtx_unlock(&pv_chunks_mutex);
3889 * A pv_chunk can only be removed from the pc_lru list
3890 * when both pc_chunks_mutex is owned and the
3891 * corresponding pmap is locked.
3893 if (pmap != next_pmap) {
3894 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3897 /* Avoid deadlock and lock recursion. */
3898 if (pmap > locked_pmap) {
3899 RELEASE_PV_LIST_LOCK(lockp);
3902 pmap_delayed_invl_start();
3903 mtx_lock(&pv_chunks_mutex);
3905 } else if (pmap != locked_pmap) {
3906 if (PMAP_TRYLOCK(pmap)) {
3908 pmap_delayed_invl_start();
3909 mtx_lock(&pv_chunks_mutex);
3912 pmap = NULL; /* pmap is not locked */
3913 mtx_lock(&pv_chunks_mutex);
3914 pc = TAILQ_NEXT(pc_marker, pc_lru);
3916 pc->pc_pmap != next_pmap)
3920 } else if (start_di)
3921 pmap_delayed_invl_start();
3922 PG_G = pmap_global_bit(pmap);
3923 PG_A = pmap_accessed_bit(pmap);
3924 PG_M = pmap_modified_bit(pmap);
3925 PG_RW = pmap_rw_bit(pmap);
3929 * Destroy every non-wired, 4 KB page mapping in the chunk.
3932 for (field = 0; field < _NPCM; field++) {
3933 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3934 inuse != 0; inuse &= ~(1UL << bit)) {
3936 pv = &pc->pc_pventry[field * 64 + bit];
3938 pde = pmap_pde(pmap, va);
3939 if ((*pde & PG_PS) != 0)
3941 pte = pmap_pde_to_pte(pde, va);
3942 if ((*pte & PG_W) != 0)
3944 tpte = pte_load_clear(pte);
3945 if ((tpte & PG_G) != 0)
3946 pmap_invalidate_page(pmap, va);
3947 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3948 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3950 if ((tpte & PG_A) != 0)
3951 vm_page_aflag_set(m, PGA_REFERENCED);
3952 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3953 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3955 if (TAILQ_EMPTY(&m->md.pv_list) &&
3956 (m->flags & PG_FICTITIOUS) == 0) {
3957 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3958 if (TAILQ_EMPTY(&pvh->pv_list)) {
3959 vm_page_aflag_clear(m,
3963 pmap_delayed_invl_page(m);
3964 pc->pc_map[field] |= 1UL << bit;
3965 pmap_unuse_pt(pmap, va, *pde, &free);
3970 mtx_lock(&pv_chunks_mutex);
3973 /* Every freed mapping is for a 4 KB page. */
3974 pmap_resident_count_dec(pmap, freed);
3975 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3976 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3977 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3978 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3979 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3980 pc->pc_map[2] == PC_FREE2) {
3981 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3982 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3983 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3984 /* Entire chunk is free; return it. */
3985 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3986 dump_drop_page(m_pc->phys_addr);
3987 mtx_lock(&pv_chunks_mutex);
3988 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3991 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3992 mtx_lock(&pv_chunks_mutex);
3993 /* One freed pv entry in locked_pmap is sufficient. */
3994 if (pmap == locked_pmap)
3997 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3998 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3999 if (active_reclaims == 1 && pmap != NULL) {
4001 * Rotate the pv chunks list so that we do not
4002 * scan the same pv chunks that could not be
4003 * freed (because they contained a wired
4004 * and/or superpage mapping) on every
4005 * invocation of reclaim_pv_chunk().
4007 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4008 MPASS(pc->pc_pmap != NULL);
4009 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4010 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4014 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4015 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4017 mtx_unlock(&pv_chunks_mutex);
4018 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4019 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4020 m_pc = SLIST_FIRST(&free);
4021 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4022 /* Recycle a freed page table page. */
4023 m_pc->wire_count = 1;
4025 vm_page_free_pages_toq(&free, true);
4030 * free the pv_entry back to the free list
4033 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4035 struct pv_chunk *pc;
4036 int idx, field, bit;
4038 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4039 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4040 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4041 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4042 pc = pv_to_chunk(pv);
4043 idx = pv - &pc->pc_pventry[0];
4046 pc->pc_map[field] |= 1ul << bit;
4047 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4048 pc->pc_map[2] != PC_FREE2) {
4049 /* 98% of the time, pc is already at the head of the list. */
4050 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4051 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4052 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4056 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4061 free_pv_chunk(struct pv_chunk *pc)
4065 mtx_lock(&pv_chunks_mutex);
4066 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4067 mtx_unlock(&pv_chunks_mutex);
4068 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4069 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4070 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4071 /* entire chunk is free, return it */
4072 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4073 dump_drop_page(m->phys_addr);
4074 vm_page_unwire(m, PQ_NONE);
4079 * Returns a new PV entry, allocating a new PV chunk from the system when
4080 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4081 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4084 * The given PV list lock may be released.
4087 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4091 struct pv_chunk *pc;
4094 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4095 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4097 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4099 for (field = 0; field < _NPCM; field++) {
4100 if (pc->pc_map[field]) {
4101 bit = bsfq(pc->pc_map[field]);
4105 if (field < _NPCM) {
4106 pv = &pc->pc_pventry[field * 64 + bit];
4107 pc->pc_map[field] &= ~(1ul << bit);
4108 /* If this was the last item, move it to tail */
4109 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4110 pc->pc_map[2] == 0) {
4111 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4112 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4115 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4116 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4120 /* No free items, allocate another chunk */
4121 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4124 if (lockp == NULL) {
4125 PV_STAT(pc_chunk_tryfail++);
4128 m = reclaim_pv_chunk(pmap, lockp);
4132 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4133 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4134 dump_add_page(m->phys_addr);
4135 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4137 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4138 pc->pc_map[1] = PC_FREE1;
4139 pc->pc_map[2] = PC_FREE2;
4140 mtx_lock(&pv_chunks_mutex);
4141 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4142 mtx_unlock(&pv_chunks_mutex);
4143 pv = &pc->pc_pventry[0];
4144 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4145 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4146 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4151 * Returns the number of one bits within the given PV chunk map.
4153 * The erratas for Intel processors state that "POPCNT Instruction May
4154 * Take Longer to Execute Than Expected". It is believed that the
4155 * issue is the spurious dependency on the destination register.
4156 * Provide a hint to the register rename logic that the destination
4157 * value is overwritten, by clearing it, as suggested in the
4158 * optimization manual. It should be cheap for unaffected processors
4161 * Reference numbers for erratas are
4162 * 4th Gen Core: HSD146
4163 * 5th Gen Core: BDM85
4164 * 6th Gen Core: SKL029
4167 popcnt_pc_map_pq(uint64_t *map)
4171 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4172 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4173 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4174 : "=&r" (result), "=&r" (tmp)
4175 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4180 * Ensure that the number of spare PV entries in the specified pmap meets or
4181 * exceeds the given count, "needed".
4183 * The given PV list lock may be released.
4186 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4188 struct pch new_tail;
4189 struct pv_chunk *pc;
4194 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4195 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4198 * Newly allocated PV chunks must be stored in a private list until
4199 * the required number of PV chunks have been allocated. Otherwise,
4200 * reclaim_pv_chunk() could recycle one of these chunks. In
4201 * contrast, these chunks must be added to the pmap upon allocation.
4203 TAILQ_INIT(&new_tail);
4206 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4208 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4209 bit_count((bitstr_t *)pc->pc_map, 0,
4210 sizeof(pc->pc_map) * NBBY, &free);
4213 free = popcnt_pc_map_pq(pc->pc_map);
4217 if (avail >= needed)
4220 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4221 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4224 m = reclaim_pv_chunk(pmap, lockp);
4229 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4230 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4231 dump_add_page(m->phys_addr);
4232 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4234 pc->pc_map[0] = PC_FREE0;
4235 pc->pc_map[1] = PC_FREE1;
4236 pc->pc_map[2] = PC_FREE2;
4237 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4238 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4239 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4242 * The reclaim might have freed a chunk from the current pmap.
4243 * If that chunk contained available entries, we need to
4244 * re-count the number of available entries.
4249 if (!TAILQ_EMPTY(&new_tail)) {
4250 mtx_lock(&pv_chunks_mutex);
4251 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4252 mtx_unlock(&pv_chunks_mutex);
4257 * First find and then remove the pv entry for the specified pmap and virtual
4258 * address from the specified pv list. Returns the pv entry if found and NULL
4259 * otherwise. This operation can be performed on pv lists for either 4KB or
4260 * 2MB page mappings.
4262 static __inline pv_entry_t
4263 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4267 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4268 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4269 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4278 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4279 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4280 * entries for each of the 4KB page mappings.
4283 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4284 struct rwlock **lockp)
4286 struct md_page *pvh;
4287 struct pv_chunk *pc;
4289 vm_offset_t va_last;
4293 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4294 KASSERT((pa & PDRMASK) == 0,
4295 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4296 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4299 * Transfer the 2mpage's pv entry for this mapping to the first
4300 * page's pv list. Once this transfer begins, the pv list lock
4301 * must not be released until the last pv entry is reinstantiated.
4303 pvh = pa_to_pvh(pa);
4304 va = trunc_2mpage(va);
4305 pv = pmap_pvh_remove(pvh, pmap, va);
4306 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4307 m = PHYS_TO_VM_PAGE(pa);
4308 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4310 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4311 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4312 va_last = va + NBPDR - PAGE_SIZE;
4314 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4315 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4316 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4317 for (field = 0; field < _NPCM; field++) {
4318 while (pc->pc_map[field]) {
4319 bit = bsfq(pc->pc_map[field]);
4320 pc->pc_map[field] &= ~(1ul << bit);
4321 pv = &pc->pc_pventry[field * 64 + bit];
4325 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4326 ("pmap_pv_demote_pde: page %p is not managed", m));
4327 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4333 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4334 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4337 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4338 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4339 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4341 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4342 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4345 #if VM_NRESERVLEVEL > 0
4347 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4348 * replace the many pv entries for the 4KB page mappings by a single pv entry
4349 * for the 2MB page mapping.
4352 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4353 struct rwlock **lockp)
4355 struct md_page *pvh;
4357 vm_offset_t va_last;
4360 KASSERT((pa & PDRMASK) == 0,
4361 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4362 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4365 * Transfer the first page's pv entry for this mapping to the 2mpage's
4366 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4367 * a transfer avoids the possibility that get_pv_entry() calls
4368 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4369 * mappings that is being promoted.
4371 m = PHYS_TO_VM_PAGE(pa);
4372 va = trunc_2mpage(va);
4373 pv = pmap_pvh_remove(&m->md, pmap, va);
4374 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4375 pvh = pa_to_pvh(pa);
4376 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4378 /* Free the remaining NPTEPG - 1 pv entries. */
4379 va_last = va + NBPDR - PAGE_SIZE;
4383 pmap_pvh_free(&m->md, pmap, va);
4384 } while (va < va_last);
4386 #endif /* VM_NRESERVLEVEL > 0 */
4389 * First find and then destroy the pv entry for the specified pmap and virtual
4390 * address. This operation can be performed on pv lists for either 4KB or 2MB
4394 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4398 pv = pmap_pvh_remove(pvh, pmap, va);
4399 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4400 free_pv_entry(pmap, pv);
4404 * Conditionally create the PV entry for a 4KB page mapping if the required
4405 * memory can be allocated without resorting to reclamation.
4408 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4409 struct rwlock **lockp)
4413 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4414 /* Pass NULL instead of the lock pointer to disable reclamation. */
4415 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4417 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4418 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4426 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4427 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4428 * false if the PV entry cannot be allocated without resorting to reclamation.
4431 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4432 struct rwlock **lockp)
4434 struct md_page *pvh;
4438 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4439 /* Pass NULL instead of the lock pointer to disable reclamation. */
4440 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4441 NULL : lockp)) == NULL)
4444 pa = pde & PG_PS_FRAME;
4445 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4446 pvh = pa_to_pvh(pa);
4447 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4453 * Fills a page table page with mappings to consecutive physical pages.
4456 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4460 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4462 newpte += PAGE_SIZE;
4467 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4468 * mapping is invalidated.
4471 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4473 struct rwlock *lock;
4477 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4484 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4485 struct rwlock **lockp)
4487 pd_entry_t newpde, oldpde;
4488 pt_entry_t *firstpte, newpte;
4489 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4492 struct spglist free;
4496 PG_G = pmap_global_bit(pmap);
4497 PG_A = pmap_accessed_bit(pmap);
4498 PG_M = pmap_modified_bit(pmap);
4499 PG_RW = pmap_rw_bit(pmap);
4500 PG_V = pmap_valid_bit(pmap);
4501 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4502 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4506 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4507 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4508 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
4510 KASSERT((oldpde & PG_W) == 0,
4511 ("pmap_demote_pde: page table page for a wired mapping"
4515 * Invalidate the 2MB page mapping and return "failure" if the
4516 * mapping was never accessed or the allocation of the new
4517 * page table page fails. If the 2MB page mapping belongs to
4518 * the direct map region of the kernel's address space, then
4519 * the page allocation request specifies the highest possible
4520 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
4521 * normal. Page table pages are preallocated for every other
4522 * part of the kernel address space, so the direct map region
4523 * is the only part of the kernel address space that must be
4526 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
4527 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
4528 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4529 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4531 sva = trunc_2mpage(va);
4532 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4533 if ((oldpde & PG_G) == 0)
4534 pmap_invalidate_pde_page(pmap, sva, oldpde);
4535 vm_page_free_pages_toq(&free, true);
4536 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
4537 " in pmap %p", va, pmap);
4540 if (va < VM_MAXUSER_ADDRESS)
4541 pmap_resident_count_inc(pmap, 1);
4543 mptepa = VM_PAGE_TO_PHYS(mpte);
4544 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4545 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4546 KASSERT((oldpde & PG_A) != 0,
4547 ("pmap_demote_pde: oldpde is missing PG_A"));
4548 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4549 ("pmap_demote_pde: oldpde is missing PG_M"));
4550 newpte = oldpde & ~PG_PS;
4551 newpte = pmap_swap_pat(pmap, newpte);
4554 * If the page table page is new, initialize it.
4556 if (mpte->wire_count == 1) {
4557 mpte->wire_count = NPTEPG;
4558 pmap_fill_ptp(firstpte, newpte);
4560 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4561 ("pmap_demote_pde: firstpte and newpte map different physical"
4565 * If the mapping has changed attributes, update the page table
4568 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4569 pmap_fill_ptp(firstpte, newpte);
4572 * The spare PV entries must be reserved prior to demoting the
4573 * mapping, that is, prior to changing the PDE. Otherwise, the state
4574 * of the PDE and the PV lists will be inconsistent, which can result
4575 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4576 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4577 * PV entry for the 2MB page mapping that is being demoted.
4579 if ((oldpde & PG_MANAGED) != 0)
4580 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4583 * Demote the mapping. This pmap is locked. The old PDE has
4584 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4585 * set. Thus, there is no danger of a race with another
4586 * processor changing the setting of PG_A and/or PG_M between
4587 * the read above and the store below.
4589 if (workaround_erratum383)
4590 pmap_update_pde(pmap, va, pde, newpde);
4592 pde_store(pde, newpde);
4595 * Invalidate a stale recursive mapping of the page table page.
4597 if (va >= VM_MAXUSER_ADDRESS)
4598 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4601 * Demote the PV entry.
4603 if ((oldpde & PG_MANAGED) != 0)
4604 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4606 atomic_add_long(&pmap_pde_demotions, 1);
4607 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
4608 " in pmap %p", va, pmap);
4613 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4616 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4622 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4623 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4624 mpte = pmap_remove_pt_page(pmap, va);
4626 panic("pmap_remove_kernel_pde: Missing pt page.");
4628 mptepa = VM_PAGE_TO_PHYS(mpte);
4629 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4632 * Initialize the page table page.
4634 pagezero((void *)PHYS_TO_DMAP(mptepa));
4637 * Demote the mapping.
4639 if (workaround_erratum383)
4640 pmap_update_pde(pmap, va, pde, newpde);
4642 pde_store(pde, newpde);
4645 * Invalidate a stale recursive mapping of the page table page.
4647 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4651 * pmap_remove_pde: do the things to unmap a superpage in a process
4654 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4655 struct spglist *free, struct rwlock **lockp)
4657 struct md_page *pvh;
4659 vm_offset_t eva, va;
4661 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4663 PG_G = pmap_global_bit(pmap);
4664 PG_A = pmap_accessed_bit(pmap);
4665 PG_M = pmap_modified_bit(pmap);
4666 PG_RW = pmap_rw_bit(pmap);
4668 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4669 KASSERT((sva & PDRMASK) == 0,
4670 ("pmap_remove_pde: sva is not 2mpage aligned"));
4671 oldpde = pte_load_clear(pdq);
4673 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4674 if ((oldpde & PG_G) != 0)
4675 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4676 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4677 if (oldpde & PG_MANAGED) {
4678 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4679 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4680 pmap_pvh_free(pvh, pmap, sva);
4682 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4683 va < eva; va += PAGE_SIZE, m++) {
4684 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4687 vm_page_aflag_set(m, PGA_REFERENCED);
4688 if (TAILQ_EMPTY(&m->md.pv_list) &&
4689 TAILQ_EMPTY(&pvh->pv_list))
4690 vm_page_aflag_clear(m, PGA_WRITEABLE);
4691 pmap_delayed_invl_page(m);
4694 if (pmap == kernel_pmap) {
4695 pmap_remove_kernel_pde(pmap, pdq, sva);
4697 mpte = pmap_remove_pt_page(pmap, sva);
4699 pmap_resident_count_dec(pmap, 1);
4700 KASSERT(mpte->wire_count == NPTEPG,
4701 ("pmap_remove_pde: pte page wire count error"));
4702 mpte->wire_count = 0;
4703 pmap_add_delayed_free_list(mpte, free, FALSE);
4706 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4710 * pmap_remove_pte: do the things to unmap a page in a process
4713 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4714 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4716 struct md_page *pvh;
4717 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4720 PG_A = pmap_accessed_bit(pmap);
4721 PG_M = pmap_modified_bit(pmap);
4722 PG_RW = pmap_rw_bit(pmap);
4724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4725 oldpte = pte_load_clear(ptq);
4727 pmap->pm_stats.wired_count -= 1;
4728 pmap_resident_count_dec(pmap, 1);
4729 if (oldpte & PG_MANAGED) {
4730 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4731 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4734 vm_page_aflag_set(m, PGA_REFERENCED);
4735 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4736 pmap_pvh_free(&m->md, pmap, va);
4737 if (TAILQ_EMPTY(&m->md.pv_list) &&
4738 (m->flags & PG_FICTITIOUS) == 0) {
4739 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4740 if (TAILQ_EMPTY(&pvh->pv_list))
4741 vm_page_aflag_clear(m, PGA_WRITEABLE);
4743 pmap_delayed_invl_page(m);
4745 return (pmap_unuse_pt(pmap, va, ptepde, free));
4749 * Remove a single page from a process address space
4752 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4753 struct spglist *free)
4755 struct rwlock *lock;
4756 pt_entry_t *pte, PG_V;
4758 PG_V = pmap_valid_bit(pmap);
4759 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4760 if ((*pde & PG_V) == 0)
4762 pte = pmap_pde_to_pte(pde, va);
4763 if ((*pte & PG_V) == 0)
4766 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4769 pmap_invalidate_page(pmap, va);
4773 * Removes the specified range of addresses from the page table page.
4776 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4777 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4779 pt_entry_t PG_G, *pte;
4783 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4784 PG_G = pmap_global_bit(pmap);
4787 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4791 pmap_invalidate_range(pmap, va, sva);
4796 if ((*pte & PG_G) == 0)
4800 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4806 pmap_invalidate_range(pmap, va, sva);
4811 * Remove the given range of addresses from the specified map.
4813 * It is assumed that the start and end are properly
4814 * rounded to the page size.
4817 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4819 struct rwlock *lock;
4820 vm_offset_t va_next;
4821 pml4_entry_t *pml4e;
4823 pd_entry_t ptpaddr, *pde;
4824 pt_entry_t PG_G, PG_V;
4825 struct spglist free;
4828 PG_G = pmap_global_bit(pmap);
4829 PG_V = pmap_valid_bit(pmap);
4832 * Perform an unsynchronized read. This is, however, safe.
4834 if (pmap->pm_stats.resident_count == 0)
4840 pmap_delayed_invl_start();
4844 * special handling of removing one page. a very
4845 * common operation and easy to short circuit some
4848 if (sva + PAGE_SIZE == eva) {
4849 pde = pmap_pde(pmap, sva);
4850 if (pde && (*pde & PG_PS) == 0) {
4851 pmap_remove_page(pmap, sva, pde, &free);
4857 for (; sva < eva; sva = va_next) {
4859 if (pmap->pm_stats.resident_count == 0)
4862 pml4e = pmap_pml4e(pmap, sva);
4863 if ((*pml4e & PG_V) == 0) {
4864 va_next = (sva + NBPML4) & ~PML4MASK;
4870 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4871 if ((*pdpe & PG_V) == 0) {
4872 va_next = (sva + NBPDP) & ~PDPMASK;
4879 * Calculate index for next page table.
4881 va_next = (sva + NBPDR) & ~PDRMASK;
4885 pde = pmap_pdpe_to_pde(pdpe, sva);
4889 * Weed out invalid mappings.
4895 * Check for large page.
4897 if ((ptpaddr & PG_PS) != 0) {
4899 * Are we removing the entire large page? If not,
4900 * demote the mapping and fall through.
4902 if (sva + NBPDR == va_next && eva >= va_next) {
4904 * The TLB entry for a PG_G mapping is
4905 * invalidated by pmap_remove_pde().
4907 if ((ptpaddr & PG_G) == 0)
4909 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4911 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4913 /* The large page mapping was destroyed. */
4920 * Limit our scan to either the end of the va represented
4921 * by the current page table page, or to the end of the
4922 * range being removed.
4927 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4934 pmap_invalidate_all(pmap);
4935 pmap_pkru_on_remove(pmap, sva, eva);
4937 pmap_delayed_invl_finish();
4938 vm_page_free_pages_toq(&free, true);
4942 * Routine: pmap_remove_all
4944 * Removes this physical page from
4945 * all physical maps in which it resides.
4946 * Reflects back modify bits to the pager.
4949 * Original versions of this routine were very
4950 * inefficient because they iteratively called
4951 * pmap_remove (slow...)
4955 pmap_remove_all(vm_page_t m)
4957 struct md_page *pvh;
4960 struct rwlock *lock;
4961 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4964 struct spglist free;
4965 int pvh_gen, md_gen;
4967 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4968 ("pmap_remove_all: page %p is not managed", m));
4970 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4971 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4972 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4975 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4977 if (!PMAP_TRYLOCK(pmap)) {
4978 pvh_gen = pvh->pv_gen;
4982 if (pvh_gen != pvh->pv_gen) {
4989 pde = pmap_pde(pmap, va);
4990 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4993 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4995 if (!PMAP_TRYLOCK(pmap)) {
4996 pvh_gen = pvh->pv_gen;
4997 md_gen = m->md.pv_gen;
5001 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5007 PG_A = pmap_accessed_bit(pmap);
5008 PG_M = pmap_modified_bit(pmap);
5009 PG_RW = pmap_rw_bit(pmap);
5010 pmap_resident_count_dec(pmap, 1);
5011 pde = pmap_pde(pmap, pv->pv_va);
5012 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5013 " a 2mpage in page %p's pv list", m));
5014 pte = pmap_pde_to_pte(pde, pv->pv_va);
5015 tpte = pte_load_clear(pte);
5017 pmap->pm_stats.wired_count--;
5019 vm_page_aflag_set(m, PGA_REFERENCED);
5022 * Update the vm_page_t clean and reference bits.
5024 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5026 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5027 pmap_invalidate_page(pmap, pv->pv_va);
5028 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5030 free_pv_entry(pmap, pv);
5033 vm_page_aflag_clear(m, PGA_WRITEABLE);
5035 pmap_delayed_invl_wait(m);
5036 vm_page_free_pages_toq(&free, true);
5040 * pmap_protect_pde: do the things to protect a 2mpage in a process
5043 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5045 pd_entry_t newpde, oldpde;
5046 vm_offset_t eva, va;
5048 boolean_t anychanged;
5049 pt_entry_t PG_G, PG_M, PG_RW;
5051 PG_G = pmap_global_bit(pmap);
5052 PG_M = pmap_modified_bit(pmap);
5053 PG_RW = pmap_rw_bit(pmap);
5055 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5056 KASSERT((sva & PDRMASK) == 0,
5057 ("pmap_protect_pde: sva is not 2mpage aligned"));
5060 oldpde = newpde = *pde;
5061 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5062 (PG_MANAGED | PG_M | PG_RW)) {
5064 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5065 va < eva; va += PAGE_SIZE, m++)
5068 if ((prot & VM_PROT_WRITE) == 0)
5069 newpde &= ~(PG_RW | PG_M);
5070 if ((prot & VM_PROT_EXECUTE) == 0)
5072 if (newpde != oldpde) {
5074 * As an optimization to future operations on this PDE, clear
5075 * PG_PROMOTED. The impending invalidation will remove any
5076 * lingering 4KB page mappings from the TLB.
5078 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5080 if ((oldpde & PG_G) != 0)
5081 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5085 return (anychanged);
5089 * Set the physical protection on the
5090 * specified range of this map as requested.
5093 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5095 vm_offset_t va_next;
5096 pml4_entry_t *pml4e;
5098 pd_entry_t ptpaddr, *pde;
5099 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5100 boolean_t anychanged;
5102 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5103 if (prot == VM_PROT_NONE) {
5104 pmap_remove(pmap, sva, eva);
5108 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5109 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5112 PG_G = pmap_global_bit(pmap);
5113 PG_M = pmap_modified_bit(pmap);
5114 PG_V = pmap_valid_bit(pmap);
5115 PG_RW = pmap_rw_bit(pmap);
5119 * Although this function delays and batches the invalidation
5120 * of stale TLB entries, it does not need to call
5121 * pmap_delayed_invl_start() and
5122 * pmap_delayed_invl_finish(), because it does not
5123 * ordinarily destroy mappings. Stale TLB entries from
5124 * protection-only changes need only be invalidated before the
5125 * pmap lock is released, because protection-only changes do
5126 * not destroy PV entries. Even operations that iterate over
5127 * a physical page's PV list of mappings, like
5128 * pmap_remove_write(), acquire the pmap lock for each
5129 * mapping. Consequently, for protection-only changes, the
5130 * pmap lock suffices to synchronize both page table and TLB
5133 * This function only destroys a mapping if pmap_demote_pde()
5134 * fails. In that case, stale TLB entries are immediately
5139 for (; sva < eva; sva = va_next) {
5141 pml4e = pmap_pml4e(pmap, sva);
5142 if ((*pml4e & PG_V) == 0) {
5143 va_next = (sva + NBPML4) & ~PML4MASK;
5149 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5150 if ((*pdpe & PG_V) == 0) {
5151 va_next = (sva + NBPDP) & ~PDPMASK;
5157 va_next = (sva + NBPDR) & ~PDRMASK;
5161 pde = pmap_pdpe_to_pde(pdpe, sva);
5165 * Weed out invalid mappings.
5171 * Check for large page.
5173 if ((ptpaddr & PG_PS) != 0) {
5175 * Are we protecting the entire large page? If not,
5176 * demote the mapping and fall through.
5178 if (sva + NBPDR == va_next && eva >= va_next) {
5180 * The TLB entry for a PG_G mapping is
5181 * invalidated by pmap_protect_pde().
5183 if (pmap_protect_pde(pmap, pde, sva, prot))
5186 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5188 * The large page mapping was destroyed.
5197 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5199 pt_entry_t obits, pbits;
5203 obits = pbits = *pte;
5204 if ((pbits & PG_V) == 0)
5207 if ((prot & VM_PROT_WRITE) == 0) {
5208 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5209 (PG_MANAGED | PG_M | PG_RW)) {
5210 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5213 pbits &= ~(PG_RW | PG_M);
5215 if ((prot & VM_PROT_EXECUTE) == 0)
5218 if (pbits != obits) {
5219 if (!atomic_cmpset_long(pte, obits, pbits))
5222 pmap_invalidate_page(pmap, sva);
5229 pmap_invalidate_all(pmap);
5233 #if VM_NRESERVLEVEL > 0
5235 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5236 * single page table page (PTP) to a single 2MB page mapping. For promotion
5237 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5238 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5239 * identical characteristics.
5242 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5243 struct rwlock **lockp)
5246 pt_entry_t *firstpte, oldpte, pa, *pte;
5247 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5251 PG_A = pmap_accessed_bit(pmap);
5252 PG_G = pmap_global_bit(pmap);
5253 PG_M = pmap_modified_bit(pmap);
5254 PG_V = pmap_valid_bit(pmap);
5255 PG_RW = pmap_rw_bit(pmap);
5256 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5257 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5259 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5262 * Examine the first PTE in the specified PTP. Abort if this PTE is
5263 * either invalid, unused, or does not map the first 4KB physical page
5264 * within a 2MB page.
5266 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5269 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
5270 atomic_add_long(&pmap_pde_p_failures, 1);
5271 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5272 " in pmap %p", va, pmap);
5275 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5277 * When PG_M is already clear, PG_RW can be cleared without
5278 * a TLB invalidation.
5280 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5286 * Examine each of the other PTEs in the specified PTP. Abort if this
5287 * PTE maps an unexpected 4KB physical page or does not have identical
5288 * characteristics to the first PTE.
5290 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5291 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5294 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5295 atomic_add_long(&pmap_pde_p_failures, 1);
5296 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5297 " in pmap %p", va, pmap);
5300 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5302 * When PG_M is already clear, PG_RW can be cleared
5303 * without a TLB invalidation.
5305 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5308 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5309 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5310 (va & ~PDRMASK), pmap);
5312 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5313 atomic_add_long(&pmap_pde_p_failures, 1);
5314 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5315 " in pmap %p", va, pmap);
5322 * Save the page table page in its current state until the PDE
5323 * mapping the superpage is demoted by pmap_demote_pde() or
5324 * destroyed by pmap_remove_pde().
5326 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5327 KASSERT(mpte >= vm_page_array &&
5328 mpte < &vm_page_array[vm_page_array_size],
5329 ("pmap_promote_pde: page table page is out of range"));
5330 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5331 ("pmap_promote_pde: page table page's pindex is wrong"));
5332 if (pmap_insert_pt_page(pmap, mpte)) {
5333 atomic_add_long(&pmap_pde_p_failures, 1);
5335 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5341 * Promote the pv entries.
5343 if ((newpde & PG_MANAGED) != 0)
5344 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5347 * Propagate the PAT index to its proper position.
5349 newpde = pmap_swap_pat(pmap, newpde);
5352 * Map the superpage.
5354 if (workaround_erratum383)
5355 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5357 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5359 atomic_add_long(&pmap_pde_promotions, 1);
5360 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5361 " in pmap %p", va, pmap);
5363 #endif /* VM_NRESERVLEVEL > 0 */
5366 * Insert the given physical page (p) at
5367 * the specified virtual address (v) in the
5368 * target physical map with the protection requested.
5370 * If specified, the page will be wired down, meaning
5371 * that the related pte can not be reclaimed.
5373 * NB: This is the only routine which MAY NOT lazy-evaluate
5374 * or lose information. That is, this routine must actually
5375 * insert this page into the given map NOW.
5377 * When destroying both a page table and PV entry, this function
5378 * performs the TLB invalidation before releasing the PV list
5379 * lock, so we do not need pmap_delayed_invl_page() calls here.
5382 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5383 u_int flags, int8_t psind)
5385 struct rwlock *lock;
5387 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5388 pt_entry_t newpte, origpte;
5395 PG_A = pmap_accessed_bit(pmap);
5396 PG_G = pmap_global_bit(pmap);
5397 PG_M = pmap_modified_bit(pmap);
5398 PG_V = pmap_valid_bit(pmap);
5399 PG_RW = pmap_rw_bit(pmap);
5401 va = trunc_page(va);
5402 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5403 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5404 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5406 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5407 va >= kmi.clean_eva,
5408 ("pmap_enter: managed mapping within the clean submap"));
5409 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5410 VM_OBJECT_ASSERT_LOCKED(m->object);
5411 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5412 ("pmap_enter: flags %u has reserved bits set", flags));
5413 pa = VM_PAGE_TO_PHYS(m);
5414 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5415 if ((flags & VM_PROT_WRITE) != 0)
5417 if ((prot & VM_PROT_WRITE) != 0)
5419 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5420 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5421 if ((prot & VM_PROT_EXECUTE) == 0)
5423 if ((flags & PMAP_ENTER_WIRED) != 0)
5425 if (va < VM_MAXUSER_ADDRESS)
5427 if (pmap == kernel_pmap)
5429 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5432 * Set modified bit gratuitously for writeable mappings if
5433 * the page is unmanaged. We do not want to take a fault
5434 * to do the dirty bit accounting for these mappings.
5436 if ((m->oflags & VPO_UNMANAGED) != 0) {
5437 if ((newpte & PG_RW) != 0)
5440 newpte |= PG_MANAGED;
5445 /* Assert the required virtual and physical alignment. */
5446 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5447 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5448 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5454 * In the case that a page table page is not
5455 * resident, we are creating it here.
5458 pde = pmap_pde(pmap, va);
5459 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5460 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5461 pte = pmap_pde_to_pte(pde, va);
5462 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5463 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5466 } else if (va < VM_MAXUSER_ADDRESS) {
5468 * Here if the pte page isn't mapped, or if it has been
5471 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5472 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5473 nosleep ? NULL : &lock);
5474 if (mpte == NULL && nosleep) {
5475 rv = KERN_RESOURCE_SHORTAGE;
5480 panic("pmap_enter: invalid page directory va=%#lx", va);
5484 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5485 newpte |= pmap_pkru_get(pmap, va);
5488 * Is the specified virtual address already mapped?
5490 if ((origpte & PG_V) != 0) {
5492 * Wiring change, just update stats. We don't worry about
5493 * wiring PT pages as they remain resident as long as there
5494 * are valid mappings in them. Hence, if a user page is wired,
5495 * the PT page will be also.
5497 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5498 pmap->pm_stats.wired_count++;
5499 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5500 pmap->pm_stats.wired_count--;
5503 * Remove the extra PT page reference.
5507 KASSERT(mpte->wire_count > 0,
5508 ("pmap_enter: missing reference to page table page,"
5513 * Has the physical page changed?
5515 opa = origpte & PG_FRAME;
5518 * No, might be a protection or wiring change.
5520 if ((origpte & PG_MANAGED) != 0 &&
5521 (newpte & PG_RW) != 0)
5522 vm_page_aflag_set(m, PGA_WRITEABLE);
5523 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5529 * The physical page has changed. Temporarily invalidate
5530 * the mapping. This ensures that all threads sharing the
5531 * pmap keep a consistent view of the mapping, which is
5532 * necessary for the correct handling of COW faults. It
5533 * also permits reuse of the old mapping's PV entry,
5534 * avoiding an allocation.
5536 * For consistency, handle unmanaged mappings the same way.
5538 origpte = pte_load_clear(pte);
5539 KASSERT((origpte & PG_FRAME) == opa,
5540 ("pmap_enter: unexpected pa update for %#lx", va));
5541 if ((origpte & PG_MANAGED) != 0) {
5542 om = PHYS_TO_VM_PAGE(opa);
5545 * The pmap lock is sufficient to synchronize with
5546 * concurrent calls to pmap_page_test_mappings() and
5547 * pmap_ts_referenced().
5549 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5551 if ((origpte & PG_A) != 0)
5552 vm_page_aflag_set(om, PGA_REFERENCED);
5553 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5554 pv = pmap_pvh_remove(&om->md, pmap, va);
5556 ("pmap_enter: no PV entry for %#lx", va));
5557 if ((newpte & PG_MANAGED) == 0)
5558 free_pv_entry(pmap, pv);
5559 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5560 TAILQ_EMPTY(&om->md.pv_list) &&
5561 ((om->flags & PG_FICTITIOUS) != 0 ||
5562 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5563 vm_page_aflag_clear(om, PGA_WRITEABLE);
5565 if ((origpte & PG_A) != 0)
5566 pmap_invalidate_page(pmap, va);
5570 * Increment the counters.
5572 if ((newpte & PG_W) != 0)
5573 pmap->pm_stats.wired_count++;
5574 pmap_resident_count_inc(pmap, 1);
5578 * Enter on the PV list if part of our managed memory.
5580 if ((newpte & PG_MANAGED) != 0) {
5582 pv = get_pv_entry(pmap, &lock);
5585 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5586 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5588 if ((newpte & PG_RW) != 0)
5589 vm_page_aflag_set(m, PGA_WRITEABLE);
5595 if ((origpte & PG_V) != 0) {
5597 origpte = pte_load_store(pte, newpte);
5598 KASSERT((origpte & PG_FRAME) == pa,
5599 ("pmap_enter: unexpected pa update for %#lx", va));
5600 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5602 if ((origpte & PG_MANAGED) != 0)
5606 * Although the PTE may still have PG_RW set, TLB
5607 * invalidation may nonetheless be required because
5608 * the PTE no longer has PG_M set.
5610 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5612 * This PTE change does not require TLB invalidation.
5616 if ((origpte & PG_A) != 0)
5617 pmap_invalidate_page(pmap, va);
5619 pte_store(pte, newpte);
5623 #if VM_NRESERVLEVEL > 0
5625 * If both the page table page and the reservation are fully
5626 * populated, then attempt promotion.
5628 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5629 pmap_ps_enabled(pmap) &&
5630 (m->flags & PG_FICTITIOUS) == 0 &&
5631 vm_reserv_level_iffullpop(m) == 0)
5632 pmap_promote_pde(pmap, pde, va, &lock);
5644 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5645 * if successful. Returns false if (1) a page table page cannot be allocated
5646 * without sleeping, (2) a mapping already exists at the specified virtual
5647 * address, or (3) a PV entry cannot be allocated without reclaiming another
5651 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5652 struct rwlock **lockp)
5657 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5658 PG_V = pmap_valid_bit(pmap);
5659 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5661 if ((m->oflags & VPO_UNMANAGED) == 0)
5662 newpde |= PG_MANAGED;
5663 if ((prot & VM_PROT_EXECUTE) == 0)
5665 if (va < VM_MAXUSER_ADDRESS)
5667 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5668 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5673 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5674 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5675 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5676 * a mapping already exists at the specified virtual address. Returns
5677 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5678 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5679 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5681 * The parameter "m" is only used when creating a managed, writeable mapping.
5684 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5685 vm_page_t m, struct rwlock **lockp)
5687 struct spglist free;
5688 pd_entry_t oldpde, *pde;
5689 pt_entry_t PG_G, PG_RW, PG_V;
5692 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
5693 ("pmap_enter_pde: cannot create wired user mapping"));
5694 PG_G = pmap_global_bit(pmap);
5695 PG_RW = pmap_rw_bit(pmap);
5696 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5697 ("pmap_enter_pde: newpde is missing PG_M"));
5698 PG_V = pmap_valid_bit(pmap);
5699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5701 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5702 NULL : lockp)) == NULL) {
5703 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5704 " in pmap %p", va, pmap);
5705 return (KERN_RESOURCE_SHORTAGE);
5709 * If pkru is not same for the whole pde range, return failure
5710 * and let vm_fault() cope. Check after pde allocation, since
5713 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5715 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5716 pmap_invalidate_page(pmap, va);
5717 vm_page_free_pages_toq(&free, true);
5719 return (KERN_FAILURE);
5721 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5722 newpde &= ~X86_PG_PKU_MASK;
5723 newpde |= pmap_pkru_get(pmap, va);
5726 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5727 pde = &pde[pmap_pde_index(va)];
5729 if ((oldpde & PG_V) != 0) {
5730 KASSERT(pdpg->wire_count > 1,
5731 ("pmap_enter_pde: pdpg's wire count is too low"));
5732 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5734 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5735 " in pmap %p", va, pmap);
5736 return (KERN_FAILURE);
5738 /* Break the existing mapping(s). */
5740 if ((oldpde & PG_PS) != 0) {
5742 * The reference to the PD page that was acquired by
5743 * pmap_allocpde() ensures that it won't be freed.
5744 * However, if the PDE resulted from a promotion, then
5745 * a reserved PT page could be freed.
5747 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5748 if ((oldpde & PG_G) == 0)
5749 pmap_invalidate_pde_page(pmap, va, oldpde);
5751 pmap_delayed_invl_start();
5752 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5754 pmap_invalidate_all(pmap);
5755 pmap_delayed_invl_finish();
5757 vm_page_free_pages_toq(&free, true);
5758 if (va >= VM_MAXUSER_ADDRESS) {
5759 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5760 if (pmap_insert_pt_page(pmap, mt)) {
5762 * XXX Currently, this can't happen because
5763 * we do not perform pmap_enter(psind == 1)
5764 * on the kernel pmap.
5766 panic("pmap_enter_pde: trie insert failed");
5769 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5772 if ((newpde & PG_MANAGED) != 0) {
5774 * Abort this mapping if its PV entry could not be created.
5776 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5778 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5780 * Although "va" is not mapped, paging-
5781 * structure caches could nonetheless have
5782 * entries that refer to the freed page table
5783 * pages. Invalidate those entries.
5785 pmap_invalidate_page(pmap, va);
5786 vm_page_free_pages_toq(&free, true);
5788 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5789 " in pmap %p", va, pmap);
5790 return (KERN_RESOURCE_SHORTAGE);
5792 if ((newpde & PG_RW) != 0) {
5793 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5794 vm_page_aflag_set(mt, PGA_WRITEABLE);
5799 * Increment counters.
5801 if ((newpde & PG_W) != 0)
5802 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5803 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5806 * Map the superpage. (This is not a promoted mapping; there will not
5807 * be any lingering 4KB page mappings in the TLB.)
5809 pde_store(pde, newpde);
5811 atomic_add_long(&pmap_pde_mappings, 1);
5812 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5813 " in pmap %p", va, pmap);
5814 return (KERN_SUCCESS);
5818 * Maps a sequence of resident pages belonging to the same object.
5819 * The sequence begins with the given page m_start. This page is
5820 * mapped at the given virtual address start. Each subsequent page is
5821 * mapped at a virtual address that is offset from start by the same
5822 * amount as the page is offset from m_start within the object. The
5823 * last page in the sequence is the page with the largest offset from
5824 * m_start that can be mapped at a virtual address less than the given
5825 * virtual address end. Not every virtual page between start and end
5826 * is mapped; only those for which a resident page exists with the
5827 * corresponding offset from m_start are mapped.
5830 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5831 vm_page_t m_start, vm_prot_t prot)
5833 struct rwlock *lock;
5836 vm_pindex_t diff, psize;
5838 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5840 psize = atop(end - start);
5845 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5846 va = start + ptoa(diff);
5847 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5848 m->psind == 1 && pmap_ps_enabled(pmap) &&
5849 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5850 m = &m[NBPDR / PAGE_SIZE - 1];
5852 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5854 m = TAILQ_NEXT(m, listq);
5862 * this code makes some *MAJOR* assumptions:
5863 * 1. Current pmap & pmap exists.
5866 * 4. No page table pages.
5867 * but is *MUCH* faster than pmap_enter...
5871 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5873 struct rwlock *lock;
5877 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5884 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5885 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5887 struct spglist free;
5888 pt_entry_t newpte, *pte, PG_V;
5890 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5891 (m->oflags & VPO_UNMANAGED) != 0,
5892 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5893 PG_V = pmap_valid_bit(pmap);
5894 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5897 * In the case that a page table page is not
5898 * resident, we are creating it here.
5900 if (va < VM_MAXUSER_ADDRESS) {
5901 vm_pindex_t ptepindex;
5905 * Calculate pagetable page index
5907 ptepindex = pmap_pde_pindex(va);
5908 if (mpte && (mpte->pindex == ptepindex)) {
5912 * Get the page directory entry
5914 ptepa = pmap_pde(pmap, va);
5917 * If the page table page is mapped, we just increment
5918 * the hold count, and activate it. Otherwise, we
5919 * attempt to allocate a page table page. If this
5920 * attempt fails, we don't retry. Instead, we give up.
5922 if (ptepa && (*ptepa & PG_V) != 0) {
5925 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5929 * Pass NULL instead of the PV list lock
5930 * pointer, because we don't intend to sleep.
5932 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5937 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5938 pte = &pte[pmap_pte_index(va)];
5952 * Enter on the PV list if part of our managed memory.
5954 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5955 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5958 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5960 * Although "va" is not mapped, paging-
5961 * structure caches could nonetheless have
5962 * entries that refer to the freed page table
5963 * pages. Invalidate those entries.
5965 pmap_invalidate_page(pmap, va);
5966 vm_page_free_pages_toq(&free, true);
5974 * Increment counters
5976 pmap_resident_count_inc(pmap, 1);
5978 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
5979 pmap_cache_bits(pmap, m->md.pat_mode, 0);
5980 if ((m->oflags & VPO_UNMANAGED) == 0)
5981 newpte |= PG_MANAGED;
5982 if ((prot & VM_PROT_EXECUTE) == 0)
5984 if (va < VM_MAXUSER_ADDRESS)
5985 newpte |= PG_U | pmap_pkru_get(pmap, va);
5986 pte_store(pte, newpte);
5991 * Make a temporary mapping for a physical address. This is only intended
5992 * to be used for panic dumps.
5995 pmap_kenter_temporary(vm_paddr_t pa, int i)
5999 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6000 pmap_kenter(va, pa);
6002 return ((void *)crashdumpmap);
6006 * This code maps large physical mmap regions into the
6007 * processor address space. Note that some shortcuts
6008 * are taken, but the code works.
6011 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6012 vm_pindex_t pindex, vm_size_t size)
6015 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6016 vm_paddr_t pa, ptepa;
6020 PG_A = pmap_accessed_bit(pmap);
6021 PG_M = pmap_modified_bit(pmap);
6022 PG_V = pmap_valid_bit(pmap);
6023 PG_RW = pmap_rw_bit(pmap);
6025 VM_OBJECT_ASSERT_WLOCKED(object);
6026 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6027 ("pmap_object_init_pt: non-device object"));
6028 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6029 if (!pmap_ps_enabled(pmap))
6031 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6033 p = vm_page_lookup(object, pindex);
6034 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6035 ("pmap_object_init_pt: invalid page %p", p));
6036 pat_mode = p->md.pat_mode;
6039 * Abort the mapping if the first page is not physically
6040 * aligned to a 2MB page boundary.
6042 ptepa = VM_PAGE_TO_PHYS(p);
6043 if (ptepa & (NBPDR - 1))
6047 * Skip the first page. Abort the mapping if the rest of
6048 * the pages are not physically contiguous or have differing
6049 * memory attributes.
6051 p = TAILQ_NEXT(p, listq);
6052 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6054 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6055 ("pmap_object_init_pt: invalid page %p", p));
6056 if (pa != VM_PAGE_TO_PHYS(p) ||
6057 pat_mode != p->md.pat_mode)
6059 p = TAILQ_NEXT(p, listq);
6063 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6064 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6065 * will not affect the termination of this loop.
6068 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6069 pa < ptepa + size; pa += NBPDR) {
6070 pdpg = pmap_allocpde(pmap, addr, NULL);
6073 * The creation of mappings below is only an
6074 * optimization. If a page directory page
6075 * cannot be allocated without blocking,
6076 * continue on to the next mapping rather than
6082 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6083 pde = &pde[pmap_pde_index(addr)];
6084 if ((*pde & PG_V) == 0) {
6085 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6086 PG_U | PG_RW | PG_V);
6087 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6088 atomic_add_long(&pmap_pde_mappings, 1);
6090 /* Continue on if the PDE is already valid. */
6092 KASSERT(pdpg->wire_count > 0,
6093 ("pmap_object_init_pt: missing reference "
6094 "to page directory page, va: 0x%lx", addr));
6103 * Clear the wired attribute from the mappings for the specified range of
6104 * addresses in the given pmap. Every valid mapping within that range
6105 * must have the wired attribute set. In contrast, invalid mappings
6106 * cannot have the wired attribute set, so they are ignored.
6108 * The wired attribute of the page table entry is not a hardware
6109 * feature, so there is no need to invalidate any TLB entries.
6110 * Since pmap_demote_pde() for the wired entry must never fail,
6111 * pmap_delayed_invl_start()/finish() calls around the
6112 * function are not needed.
6115 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6117 vm_offset_t va_next;
6118 pml4_entry_t *pml4e;
6121 pt_entry_t *pte, PG_V;
6123 PG_V = pmap_valid_bit(pmap);
6125 for (; sva < eva; sva = va_next) {
6126 pml4e = pmap_pml4e(pmap, sva);
6127 if ((*pml4e & PG_V) == 0) {
6128 va_next = (sva + NBPML4) & ~PML4MASK;
6133 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6134 if ((*pdpe & PG_V) == 0) {
6135 va_next = (sva + NBPDP) & ~PDPMASK;
6140 va_next = (sva + NBPDR) & ~PDRMASK;
6143 pde = pmap_pdpe_to_pde(pdpe, sva);
6144 if ((*pde & PG_V) == 0)
6146 if ((*pde & PG_PS) != 0) {
6147 if ((*pde & PG_W) == 0)
6148 panic("pmap_unwire: pde %#jx is missing PG_W",
6152 * Are we unwiring the entire large page? If not,
6153 * demote the mapping and fall through.
6155 if (sva + NBPDR == va_next && eva >= va_next) {
6156 atomic_clear_long(pde, PG_W);
6157 pmap->pm_stats.wired_count -= NBPDR /
6160 } else if (!pmap_demote_pde(pmap, pde, sva))
6161 panic("pmap_unwire: demotion failed");
6165 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6167 if ((*pte & PG_V) == 0)
6169 if ((*pte & PG_W) == 0)
6170 panic("pmap_unwire: pte %#jx is missing PG_W",
6174 * PG_W must be cleared atomically. Although the pmap
6175 * lock synchronizes access to PG_W, another processor
6176 * could be setting PG_M and/or PG_A concurrently.
6178 atomic_clear_long(pte, PG_W);
6179 pmap->pm_stats.wired_count--;
6186 * Copy the range specified by src_addr/len
6187 * from the source map to the range dst_addr/len
6188 * in the destination map.
6190 * This routine is only advisory and need not do anything.
6194 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6195 vm_offset_t src_addr)
6197 struct rwlock *lock;
6198 struct spglist free;
6200 vm_offset_t end_addr = src_addr + len;
6201 vm_offset_t va_next;
6202 vm_page_t dst_pdpg, dstmpte, srcmpte;
6203 pt_entry_t PG_A, PG_M, PG_V;
6205 if (dst_addr != src_addr)
6208 if (dst_pmap->pm_type != src_pmap->pm_type)
6212 * EPT page table entries that require emulation of A/D bits are
6213 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6214 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6215 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6216 * implementations flag an EPT misconfiguration for exec-only
6217 * mappings we skip this function entirely for emulated pmaps.
6219 if (pmap_emulate_ad_bits(dst_pmap))
6223 if (dst_pmap < src_pmap) {
6224 PMAP_LOCK(dst_pmap);
6225 PMAP_LOCK(src_pmap);
6227 PMAP_LOCK(src_pmap);
6228 PMAP_LOCK(dst_pmap);
6231 PG_A = pmap_accessed_bit(dst_pmap);
6232 PG_M = pmap_modified_bit(dst_pmap);
6233 PG_V = pmap_valid_bit(dst_pmap);
6235 for (addr = src_addr; addr < end_addr; addr = va_next) {
6236 pt_entry_t *src_pte, *dst_pte;
6237 pml4_entry_t *pml4e;
6239 pd_entry_t srcptepaddr, *pde;
6241 KASSERT(addr < UPT_MIN_ADDRESS,
6242 ("pmap_copy: invalid to pmap_copy page tables"));
6244 pml4e = pmap_pml4e(src_pmap, addr);
6245 if ((*pml4e & PG_V) == 0) {
6246 va_next = (addr + NBPML4) & ~PML4MASK;
6252 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6253 if ((*pdpe & PG_V) == 0) {
6254 va_next = (addr + NBPDP) & ~PDPMASK;
6260 va_next = (addr + NBPDR) & ~PDRMASK;
6264 pde = pmap_pdpe_to_pde(pdpe, addr);
6266 if (srcptepaddr == 0)
6269 if (srcptepaddr & PG_PS) {
6270 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6272 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6273 if (dst_pdpg == NULL)
6275 pde = (pd_entry_t *)
6276 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6277 pde = &pde[pmap_pde_index(addr)];
6278 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6279 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6280 PMAP_ENTER_NORECLAIM, &lock))) {
6281 *pde = srcptepaddr & ~PG_W;
6282 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
6283 atomic_add_long(&pmap_pde_mappings, 1);
6285 dst_pdpg->wire_count--;
6289 srcptepaddr &= PG_FRAME;
6290 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6291 KASSERT(srcmpte->wire_count > 0,
6292 ("pmap_copy: source page table page is unused"));
6294 if (va_next > end_addr)
6297 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6298 src_pte = &src_pte[pmap_pte_index(addr)];
6300 while (addr < va_next) {
6304 * we only virtual copy managed pages
6306 if ((ptetemp & PG_MANAGED) != 0) {
6307 if (dstmpte != NULL &&
6308 dstmpte->pindex == pmap_pde_pindex(addr))
6309 dstmpte->wire_count++;
6310 else if ((dstmpte = pmap_allocpte(dst_pmap,
6311 addr, NULL)) == NULL)
6313 dst_pte = (pt_entry_t *)
6314 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6315 dst_pte = &dst_pte[pmap_pte_index(addr)];
6316 if (*dst_pte == 0 &&
6317 pmap_try_insert_pv_entry(dst_pmap, addr,
6318 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
6321 * Clear the wired, modified, and
6322 * accessed (referenced) bits
6325 *dst_pte = ptetemp & ~(PG_W | PG_M |
6327 pmap_resident_count_inc(dst_pmap, 1);
6330 if (pmap_unwire_ptp(dst_pmap, addr,
6333 * Although "addr" is not
6334 * mapped, paging-structure
6335 * caches could nonetheless
6336 * have entries that refer to
6337 * the freed page table pages.
6338 * Invalidate those entries.
6340 pmap_invalidate_page(dst_pmap,
6342 vm_page_free_pages_toq(&free,
6347 if (dstmpte->wire_count >= srcmpte->wire_count)
6357 PMAP_UNLOCK(src_pmap);
6358 PMAP_UNLOCK(dst_pmap);
6362 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6366 if (dst_pmap->pm_type != src_pmap->pm_type ||
6367 dst_pmap->pm_type != PT_X86 ||
6368 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6371 if (dst_pmap < src_pmap) {
6372 PMAP_LOCK(dst_pmap);
6373 PMAP_LOCK(src_pmap);
6375 PMAP_LOCK(src_pmap);
6376 PMAP_LOCK(dst_pmap);
6378 error = pmap_pkru_copy(dst_pmap, src_pmap);
6379 /* Clean up partial copy on failure due to no memory. */
6380 if (error == ENOMEM)
6381 pmap_pkru_deassign_all(dst_pmap);
6382 PMAP_UNLOCK(src_pmap);
6383 PMAP_UNLOCK(dst_pmap);
6384 if (error != ENOMEM)
6392 * Zero the specified hardware page.
6395 pmap_zero_page(vm_page_t m)
6397 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6399 pagezero((void *)va);
6403 * Zero an an area within a single hardware page. off and size must not
6404 * cover an area beyond a single hardware page.
6407 pmap_zero_page_area(vm_page_t m, int off, int size)
6409 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6411 if (off == 0 && size == PAGE_SIZE)
6412 pagezero((void *)va);
6414 bzero((char *)va + off, size);
6418 * Copy 1 specified hardware page to another.
6421 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6423 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6424 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6426 pagecopy((void *)src, (void *)dst);
6429 int unmapped_buf_allowed = 1;
6432 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6433 vm_offset_t b_offset, int xfersize)
6437 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6441 while (xfersize > 0) {
6442 a_pg_offset = a_offset & PAGE_MASK;
6443 pages[0] = ma[a_offset >> PAGE_SHIFT];
6444 b_pg_offset = b_offset & PAGE_MASK;
6445 pages[1] = mb[b_offset >> PAGE_SHIFT];
6446 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6447 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6448 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6449 a_cp = (char *)vaddr[0] + a_pg_offset;
6450 b_cp = (char *)vaddr[1] + b_pg_offset;
6451 bcopy(a_cp, b_cp, cnt);
6452 if (__predict_false(mapped))
6453 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6461 * Returns true if the pmap's pv is one of the first
6462 * 16 pvs linked to from this page. This count may
6463 * be changed upwards or downwards in the future; it
6464 * is only necessary that true be returned for a small
6465 * subset of pmaps for proper page aging.
6468 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6470 struct md_page *pvh;
6471 struct rwlock *lock;
6476 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6477 ("pmap_page_exists_quick: page %p is not managed", m));
6479 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6481 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6482 if (PV_PMAP(pv) == pmap) {
6490 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6491 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6492 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6493 if (PV_PMAP(pv) == pmap) {
6507 * pmap_page_wired_mappings:
6509 * Return the number of managed mappings to the given physical page
6513 pmap_page_wired_mappings(vm_page_t m)
6515 struct rwlock *lock;
6516 struct md_page *pvh;
6520 int count, md_gen, pvh_gen;
6522 if ((m->oflags & VPO_UNMANAGED) != 0)
6524 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6528 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6530 if (!PMAP_TRYLOCK(pmap)) {
6531 md_gen = m->md.pv_gen;
6535 if (md_gen != m->md.pv_gen) {
6540 pte = pmap_pte(pmap, pv->pv_va);
6541 if ((*pte & PG_W) != 0)
6545 if ((m->flags & PG_FICTITIOUS) == 0) {
6546 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6547 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6549 if (!PMAP_TRYLOCK(pmap)) {
6550 md_gen = m->md.pv_gen;
6551 pvh_gen = pvh->pv_gen;
6555 if (md_gen != m->md.pv_gen ||
6556 pvh_gen != pvh->pv_gen) {
6561 pte = pmap_pde(pmap, pv->pv_va);
6562 if ((*pte & PG_W) != 0)
6572 * Returns TRUE if the given page is mapped individually or as part of
6573 * a 2mpage. Otherwise, returns FALSE.
6576 pmap_page_is_mapped(vm_page_t m)
6578 struct rwlock *lock;
6581 if ((m->oflags & VPO_UNMANAGED) != 0)
6583 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6585 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6586 ((m->flags & PG_FICTITIOUS) == 0 &&
6587 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6593 * Destroy all managed, non-wired mappings in the given user-space
6594 * pmap. This pmap cannot be active on any processor besides the
6597 * This function cannot be applied to the kernel pmap. Moreover, it
6598 * is not intended for general use. It is only to be used during
6599 * process termination. Consequently, it can be implemented in ways
6600 * that make it faster than pmap_remove(). First, it can more quickly
6601 * destroy mappings by iterating over the pmap's collection of PV
6602 * entries, rather than searching the page table. Second, it doesn't
6603 * have to test and clear the page table entries atomically, because
6604 * no processor is currently accessing the user address space. In
6605 * particular, a page table entry's dirty bit won't change state once
6606 * this function starts.
6608 * Although this function destroys all of the pmap's managed,
6609 * non-wired mappings, it can delay and batch the invalidation of TLB
6610 * entries without calling pmap_delayed_invl_start() and
6611 * pmap_delayed_invl_finish(). Because the pmap is not active on
6612 * any other processor, none of these TLB entries will ever be used
6613 * before their eventual invalidation. Consequently, there is no need
6614 * for either pmap_remove_all() or pmap_remove_write() to wait for
6615 * that eventual TLB invalidation.
6618 pmap_remove_pages(pmap_t pmap)
6621 pt_entry_t *pte, tpte;
6622 pt_entry_t PG_M, PG_RW, PG_V;
6623 struct spglist free;
6624 vm_page_t m, mpte, mt;
6626 struct md_page *pvh;
6627 struct pv_chunk *pc, *npc;
6628 struct rwlock *lock;
6630 uint64_t inuse, bitmask;
6631 int allfree, field, freed, idx;
6632 boolean_t superpage;
6636 * Assert that the given pmap is only active on the current
6637 * CPU. Unfortunately, we cannot block another CPU from
6638 * activating the pmap while this function is executing.
6640 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6643 cpuset_t other_cpus;
6645 other_cpus = all_cpus;
6647 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6648 CPU_AND(&other_cpus, &pmap->pm_active);
6650 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6655 PG_M = pmap_modified_bit(pmap);
6656 PG_V = pmap_valid_bit(pmap);
6657 PG_RW = pmap_rw_bit(pmap);
6661 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6664 for (field = 0; field < _NPCM; field++) {
6665 inuse = ~pc->pc_map[field] & pc_freemask[field];
6666 while (inuse != 0) {
6668 bitmask = 1UL << bit;
6669 idx = field * 64 + bit;
6670 pv = &pc->pc_pventry[idx];
6673 pte = pmap_pdpe(pmap, pv->pv_va);
6675 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6677 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6680 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6682 pte = &pte[pmap_pte_index(pv->pv_va)];
6686 * Keep track whether 'tpte' is a
6687 * superpage explicitly instead of
6688 * relying on PG_PS being set.
6690 * This is because PG_PS is numerically
6691 * identical to PG_PTE_PAT and thus a
6692 * regular page could be mistaken for
6698 if ((tpte & PG_V) == 0) {
6699 panic("bad pte va %lx pte %lx",
6704 * We cannot remove wired pages from a process' mapping at this time
6712 pa = tpte & PG_PS_FRAME;
6714 pa = tpte & PG_FRAME;
6716 m = PHYS_TO_VM_PAGE(pa);
6717 KASSERT(m->phys_addr == pa,
6718 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6719 m, (uintmax_t)m->phys_addr,
6722 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6723 m < &vm_page_array[vm_page_array_size],
6724 ("pmap_remove_pages: bad tpte %#jx",
6730 * Update the vm_page_t clean/reference bits.
6732 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6734 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6740 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6743 pc->pc_map[field] |= bitmask;
6745 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6746 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6747 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6749 if (TAILQ_EMPTY(&pvh->pv_list)) {
6750 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6751 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6752 TAILQ_EMPTY(&mt->md.pv_list))
6753 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6755 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6757 pmap_resident_count_dec(pmap, 1);
6758 KASSERT(mpte->wire_count == NPTEPG,
6759 ("pmap_remove_pages: pte page wire count error"));
6760 mpte->wire_count = 0;
6761 pmap_add_delayed_free_list(mpte, &free, FALSE);
6764 pmap_resident_count_dec(pmap, 1);
6765 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6767 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6768 TAILQ_EMPTY(&m->md.pv_list) &&
6769 (m->flags & PG_FICTITIOUS) == 0) {
6770 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6771 if (TAILQ_EMPTY(&pvh->pv_list))
6772 vm_page_aflag_clear(m, PGA_WRITEABLE);
6775 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6779 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6780 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6781 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6783 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6789 pmap_invalidate_all(pmap);
6790 pmap_pkru_deassign_all(pmap);
6792 vm_page_free_pages_toq(&free, true);
6796 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6798 struct rwlock *lock;
6800 struct md_page *pvh;
6801 pt_entry_t *pte, mask;
6802 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6804 int md_gen, pvh_gen;
6808 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6811 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6813 if (!PMAP_TRYLOCK(pmap)) {
6814 md_gen = m->md.pv_gen;
6818 if (md_gen != m->md.pv_gen) {
6823 pte = pmap_pte(pmap, pv->pv_va);
6826 PG_M = pmap_modified_bit(pmap);
6827 PG_RW = pmap_rw_bit(pmap);
6828 mask |= PG_RW | PG_M;
6831 PG_A = pmap_accessed_bit(pmap);
6832 PG_V = pmap_valid_bit(pmap);
6833 mask |= PG_V | PG_A;
6835 rv = (*pte & mask) == mask;
6840 if ((m->flags & PG_FICTITIOUS) == 0) {
6841 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6842 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6844 if (!PMAP_TRYLOCK(pmap)) {
6845 md_gen = m->md.pv_gen;
6846 pvh_gen = pvh->pv_gen;
6850 if (md_gen != m->md.pv_gen ||
6851 pvh_gen != pvh->pv_gen) {
6856 pte = pmap_pde(pmap, pv->pv_va);
6859 PG_M = pmap_modified_bit(pmap);
6860 PG_RW = pmap_rw_bit(pmap);
6861 mask |= PG_RW | PG_M;
6864 PG_A = pmap_accessed_bit(pmap);
6865 PG_V = pmap_valid_bit(pmap);
6866 mask |= PG_V | PG_A;
6868 rv = (*pte & mask) == mask;
6882 * Return whether or not the specified physical page was modified
6883 * in any physical maps.
6886 pmap_is_modified(vm_page_t m)
6889 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6890 ("pmap_is_modified: page %p is not managed", m));
6893 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6894 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6895 * is clear, no PTEs can have PG_M set.
6897 VM_OBJECT_ASSERT_WLOCKED(m->object);
6898 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6900 return (pmap_page_test_mappings(m, FALSE, TRUE));
6904 * pmap_is_prefaultable:
6906 * Return whether or not the specified virtual address is eligible
6910 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6913 pt_entry_t *pte, PG_V;
6916 PG_V = pmap_valid_bit(pmap);
6919 pde = pmap_pde(pmap, addr);
6920 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6921 pte = pmap_pde_to_pte(pde, addr);
6922 rv = (*pte & PG_V) == 0;
6929 * pmap_is_referenced:
6931 * Return whether or not the specified physical page was referenced
6932 * in any physical maps.
6935 pmap_is_referenced(vm_page_t m)
6938 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6939 ("pmap_is_referenced: page %p is not managed", m));
6940 return (pmap_page_test_mappings(m, TRUE, FALSE));
6944 * Clear the write and modified bits in each of the given page's mappings.
6947 pmap_remove_write(vm_page_t m)
6949 struct md_page *pvh;
6951 struct rwlock *lock;
6952 pv_entry_t next_pv, pv;
6954 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6956 int pvh_gen, md_gen;
6958 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6959 ("pmap_remove_write: page %p is not managed", m));
6962 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6963 * set by another thread while the object is locked. Thus,
6964 * if PGA_WRITEABLE is clear, no page table entries need updating.
6966 VM_OBJECT_ASSERT_WLOCKED(m->object);
6967 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6969 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6970 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6971 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6974 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6976 if (!PMAP_TRYLOCK(pmap)) {
6977 pvh_gen = pvh->pv_gen;
6981 if (pvh_gen != pvh->pv_gen) {
6987 PG_RW = pmap_rw_bit(pmap);
6989 pde = pmap_pde(pmap, va);
6990 if ((*pde & PG_RW) != 0)
6991 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6992 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6993 ("inconsistent pv lock %p %p for page %p",
6994 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6997 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6999 if (!PMAP_TRYLOCK(pmap)) {
7000 pvh_gen = pvh->pv_gen;
7001 md_gen = m->md.pv_gen;
7005 if (pvh_gen != pvh->pv_gen ||
7006 md_gen != m->md.pv_gen) {
7012 PG_M = pmap_modified_bit(pmap);
7013 PG_RW = pmap_rw_bit(pmap);
7014 pde = pmap_pde(pmap, pv->pv_va);
7015 KASSERT((*pde & PG_PS) == 0,
7016 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7018 pte = pmap_pde_to_pte(pde, pv->pv_va);
7021 if (oldpte & PG_RW) {
7022 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7025 if ((oldpte & PG_M) != 0)
7027 pmap_invalidate_page(pmap, pv->pv_va);
7032 vm_page_aflag_clear(m, PGA_WRITEABLE);
7033 pmap_delayed_invl_wait(m);
7036 static __inline boolean_t
7037 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7040 if (!pmap_emulate_ad_bits(pmap))
7043 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7046 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7047 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7048 * if the EPT_PG_WRITE bit is set.
7050 if ((pte & EPT_PG_WRITE) != 0)
7054 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7056 if ((pte & EPT_PG_EXECUTE) == 0 ||
7057 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7064 * pmap_ts_referenced:
7066 * Return a count of reference bits for a page, clearing those bits.
7067 * It is not necessary for every reference bit to be cleared, but it
7068 * is necessary that 0 only be returned when there are truly no
7069 * reference bits set.
7071 * As an optimization, update the page's dirty field if a modified bit is
7072 * found while counting reference bits. This opportunistic update can be
7073 * performed at low cost and can eliminate the need for some future calls
7074 * to pmap_is_modified(). However, since this function stops after
7075 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7076 * dirty pages. Those dirty pages will only be detected by a future call
7077 * to pmap_is_modified().
7079 * A DI block is not needed within this function, because
7080 * invalidations are performed before the PV list lock is
7084 pmap_ts_referenced(vm_page_t m)
7086 struct md_page *pvh;
7089 struct rwlock *lock;
7090 pd_entry_t oldpde, *pde;
7091 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7094 int cleared, md_gen, not_cleared, pvh_gen;
7095 struct spglist free;
7098 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7099 ("pmap_ts_referenced: page %p is not managed", m));
7102 pa = VM_PAGE_TO_PHYS(m);
7103 lock = PHYS_TO_PV_LIST_LOCK(pa);
7104 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7108 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7109 goto small_mappings;
7115 if (!PMAP_TRYLOCK(pmap)) {
7116 pvh_gen = pvh->pv_gen;
7120 if (pvh_gen != pvh->pv_gen) {
7125 PG_A = pmap_accessed_bit(pmap);
7126 PG_M = pmap_modified_bit(pmap);
7127 PG_RW = pmap_rw_bit(pmap);
7129 pde = pmap_pde(pmap, pv->pv_va);
7131 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7133 * Although "oldpde" is mapping a 2MB page, because
7134 * this function is called at a 4KB page granularity,
7135 * we only update the 4KB page under test.
7139 if ((oldpde & PG_A) != 0) {
7141 * Since this reference bit is shared by 512 4KB
7142 * pages, it should not be cleared every time it is
7143 * tested. Apply a simple "hash" function on the
7144 * physical page number, the virtual superpage number,
7145 * and the pmap address to select one 4KB page out of
7146 * the 512 on which testing the reference bit will
7147 * result in clearing that reference bit. This
7148 * function is designed to avoid the selection of the
7149 * same 4KB page for every 2MB page mapping.
7151 * On demotion, a mapping that hasn't been referenced
7152 * is simply destroyed. To avoid the possibility of a
7153 * subsequent page fault on a demoted wired mapping,
7154 * always leave its reference bit set. Moreover,
7155 * since the superpage is wired, the current state of
7156 * its reference bit won't affect page replacement.
7158 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7159 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7160 (oldpde & PG_W) == 0) {
7161 if (safe_to_clear_referenced(pmap, oldpde)) {
7162 atomic_clear_long(pde, PG_A);
7163 pmap_invalidate_page(pmap, pv->pv_va);
7165 } else if (pmap_demote_pde_locked(pmap, pde,
7166 pv->pv_va, &lock)) {
7168 * Remove the mapping to a single page
7169 * so that a subsequent access may
7170 * repromote. Since the underlying
7171 * page table page is fully populated,
7172 * this removal never frees a page
7176 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7178 pte = pmap_pde_to_pte(pde, va);
7179 pmap_remove_pte(pmap, pte, va, *pde,
7181 pmap_invalidate_page(pmap, va);
7187 * The superpage mapping was removed
7188 * entirely and therefore 'pv' is no
7196 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7197 ("inconsistent pv lock %p %p for page %p",
7198 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7203 /* Rotate the PV list if it has more than one entry. */
7204 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7205 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7206 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7209 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7211 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7213 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7220 if (!PMAP_TRYLOCK(pmap)) {
7221 pvh_gen = pvh->pv_gen;
7222 md_gen = m->md.pv_gen;
7226 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7231 PG_A = pmap_accessed_bit(pmap);
7232 PG_M = pmap_modified_bit(pmap);
7233 PG_RW = pmap_rw_bit(pmap);
7234 pde = pmap_pde(pmap, pv->pv_va);
7235 KASSERT((*pde & PG_PS) == 0,
7236 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7238 pte = pmap_pde_to_pte(pde, pv->pv_va);
7239 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7241 if ((*pte & PG_A) != 0) {
7242 if (safe_to_clear_referenced(pmap, *pte)) {
7243 atomic_clear_long(pte, PG_A);
7244 pmap_invalidate_page(pmap, pv->pv_va);
7246 } else if ((*pte & PG_W) == 0) {
7248 * Wired pages cannot be paged out so
7249 * doing accessed bit emulation for
7250 * them is wasted effort. We do the
7251 * hard work for unwired pages only.
7253 pmap_remove_pte(pmap, pte, pv->pv_va,
7254 *pde, &free, &lock);
7255 pmap_invalidate_page(pmap, pv->pv_va);
7260 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7261 ("inconsistent pv lock %p %p for page %p",
7262 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7267 /* Rotate the PV list if it has more than one entry. */
7268 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7269 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7270 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7273 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7274 not_cleared < PMAP_TS_REFERENCED_MAX);
7277 vm_page_free_pages_toq(&free, true);
7278 return (cleared + not_cleared);
7282 * Apply the given advice to the specified range of addresses within the
7283 * given pmap. Depending on the advice, clear the referenced and/or
7284 * modified flags in each mapping and set the mapped page's dirty field.
7287 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7289 struct rwlock *lock;
7290 pml4_entry_t *pml4e;
7292 pd_entry_t oldpde, *pde;
7293 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7294 vm_offset_t va, va_next;
7296 boolean_t anychanged;
7298 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7302 * A/D bit emulation requires an alternate code path when clearing
7303 * the modified and accessed bits below. Since this function is
7304 * advisory in nature we skip it entirely for pmaps that require
7305 * A/D bit emulation.
7307 if (pmap_emulate_ad_bits(pmap))
7310 PG_A = pmap_accessed_bit(pmap);
7311 PG_G = pmap_global_bit(pmap);
7312 PG_M = pmap_modified_bit(pmap);
7313 PG_V = pmap_valid_bit(pmap);
7314 PG_RW = pmap_rw_bit(pmap);
7316 pmap_delayed_invl_start();
7318 for (; sva < eva; sva = va_next) {
7319 pml4e = pmap_pml4e(pmap, sva);
7320 if ((*pml4e & PG_V) == 0) {
7321 va_next = (sva + NBPML4) & ~PML4MASK;
7326 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7327 if ((*pdpe & PG_V) == 0) {
7328 va_next = (sva + NBPDP) & ~PDPMASK;
7333 va_next = (sva + NBPDR) & ~PDRMASK;
7336 pde = pmap_pdpe_to_pde(pdpe, sva);
7338 if ((oldpde & PG_V) == 0)
7340 else if ((oldpde & PG_PS) != 0) {
7341 if ((oldpde & PG_MANAGED) == 0)
7344 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7349 * The large page mapping was destroyed.
7355 * Unless the page mappings are wired, remove the
7356 * mapping to a single page so that a subsequent
7357 * access may repromote. Since the underlying page
7358 * table page is fully populated, this removal never
7359 * frees a page table page.
7361 if ((oldpde & PG_W) == 0) {
7362 pte = pmap_pde_to_pte(pde, sva);
7363 KASSERT((*pte & PG_V) != 0,
7364 ("pmap_advise: invalid PTE"));
7365 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
7375 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7377 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7379 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7380 if (advice == MADV_DONTNEED) {
7382 * Future calls to pmap_is_modified()
7383 * can be avoided by making the page
7386 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7389 atomic_clear_long(pte, PG_M | PG_A);
7390 } else if ((*pte & PG_A) != 0)
7391 atomic_clear_long(pte, PG_A);
7395 if ((*pte & PG_G) != 0) {
7402 if (va != va_next) {
7403 pmap_invalidate_range(pmap, va, sva);
7408 pmap_invalidate_range(pmap, va, sva);
7411 pmap_invalidate_all(pmap);
7413 pmap_delayed_invl_finish();
7417 * Clear the modify bits on the specified physical page.
7420 pmap_clear_modify(vm_page_t m)
7422 struct md_page *pvh;
7424 pv_entry_t next_pv, pv;
7425 pd_entry_t oldpde, *pde;
7426 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
7427 struct rwlock *lock;
7429 int md_gen, pvh_gen;
7431 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7432 ("pmap_clear_modify: page %p is not managed", m));
7433 VM_OBJECT_ASSERT_WLOCKED(m->object);
7434 KASSERT(!vm_page_xbusied(m),
7435 ("pmap_clear_modify: page %p is exclusive busied", m));
7438 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7439 * If the object containing the page is locked and the page is not
7440 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7442 if ((m->aflags & PGA_WRITEABLE) == 0)
7444 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7445 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7446 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7449 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7451 if (!PMAP_TRYLOCK(pmap)) {
7452 pvh_gen = pvh->pv_gen;
7456 if (pvh_gen != pvh->pv_gen) {
7461 PG_M = pmap_modified_bit(pmap);
7462 PG_V = pmap_valid_bit(pmap);
7463 PG_RW = pmap_rw_bit(pmap);
7465 pde = pmap_pde(pmap, va);
7467 if ((oldpde & PG_RW) != 0) {
7468 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
7469 if ((oldpde & PG_W) == 0) {
7471 * Write protect the mapping to a
7472 * single page so that a subsequent
7473 * write access may repromote.
7475 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7477 pte = pmap_pde_to_pte(pde, va);
7479 if ((oldpte & PG_V) != 0) {
7480 while (!atomic_cmpset_long(pte,
7482 oldpte & ~(PG_M | PG_RW)))
7485 pmap_invalidate_page(pmap, va);
7492 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7494 if (!PMAP_TRYLOCK(pmap)) {
7495 md_gen = m->md.pv_gen;
7496 pvh_gen = pvh->pv_gen;
7500 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7505 PG_M = pmap_modified_bit(pmap);
7506 PG_RW = pmap_rw_bit(pmap);
7507 pde = pmap_pde(pmap, pv->pv_va);
7508 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7509 " a 2mpage in page %p's pv list", m));
7510 pte = pmap_pde_to_pte(pde, pv->pv_va);
7511 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7512 atomic_clear_long(pte, PG_M);
7513 pmap_invalidate_page(pmap, pv->pv_va);
7521 * Miscellaneous support routines follow
7524 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7525 static __inline void
7526 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7531 * The cache mode bits are all in the low 32-bits of the
7532 * PTE, so we can just spin on updating the low 32-bits.
7535 opte = *(u_int *)pte;
7536 npte = opte & ~mask;
7538 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7541 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7542 static __inline void
7543 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7548 * The cache mode bits are all in the low 32-bits of the
7549 * PDE, so we can just spin on updating the low 32-bits.
7552 opde = *(u_int *)pde;
7553 npde = opde & ~mask;
7555 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7559 * Map a set of physical memory pages into the kernel virtual
7560 * address space. Return a pointer to where it is mapped. This
7561 * routine is intended to be used for mapping device memory,
7565 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, bool noflush)
7567 struct pmap_preinit_mapping *ppim;
7568 vm_offset_t va, offset;
7572 offset = pa & PAGE_MASK;
7573 size = round_page(offset + size);
7574 pa = trunc_page(pa);
7576 if (!pmap_initialized) {
7578 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7579 ppim = pmap_preinit_mapping + i;
7580 if (ppim->va == 0) {
7584 ppim->va = virtual_avail;
7585 virtual_avail += size;
7591 panic("%s: too many preinit mappings", __func__);
7594 * If we have a preinit mapping, re-use it.
7596 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7597 ppim = pmap_preinit_mapping + i;
7598 if (ppim->pa == pa && ppim->sz == size &&
7600 return ((void *)(ppim->va + offset));
7603 * If the specified range of physical addresses fits within
7604 * the direct map window, use the direct map.
7606 if (pa < dmaplimit && pa + size <= dmaplimit) {
7607 va = PHYS_TO_DMAP(pa);
7608 PMAP_LOCK(kernel_pmap);
7609 i = pmap_change_attr_locked(va, size, mode, noflush);
7610 PMAP_UNLOCK(kernel_pmap);
7612 return ((void *)(va + offset));
7614 va = kva_alloc(size);
7616 panic("%s: Couldn't allocate KVA", __func__);
7618 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7619 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7620 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7622 pmap_invalidate_cache_range(va, va + tmpsize);
7623 return ((void *)(va + offset));
7627 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7630 return (pmap_mapdev_internal(pa, size, mode, false));
7634 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7637 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, false));
7641 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7644 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, true));
7648 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7651 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK, false));
7655 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7657 struct pmap_preinit_mapping *ppim;
7661 /* If we gave a direct map region in pmap_mapdev, do nothing */
7662 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7664 offset = va & PAGE_MASK;
7665 size = round_page(offset + size);
7666 va = trunc_page(va);
7667 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7668 ppim = pmap_preinit_mapping + i;
7669 if (ppim->va == va && ppim->sz == size) {
7670 if (pmap_initialized)
7676 if (va + size == virtual_avail)
7681 if (pmap_initialized)
7686 * Tries to demote a 1GB page mapping.
7689 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7691 pdp_entry_t newpdpe, oldpdpe;
7692 pd_entry_t *firstpde, newpde, *pde;
7693 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7697 PG_A = pmap_accessed_bit(pmap);
7698 PG_M = pmap_modified_bit(pmap);
7699 PG_V = pmap_valid_bit(pmap);
7700 PG_RW = pmap_rw_bit(pmap);
7702 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7704 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7705 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7706 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7707 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7708 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7709 " in pmap %p", va, pmap);
7712 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7713 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7714 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7715 KASSERT((oldpdpe & PG_A) != 0,
7716 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7717 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7718 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7722 * Initialize the page directory page.
7724 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7730 * Demote the mapping.
7735 * Invalidate a stale recursive mapping of the page directory page.
7737 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7739 pmap_pdpe_demotions++;
7740 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7741 " in pmap %p", va, pmap);
7746 * Sets the memory attribute for the specified page.
7749 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7752 m->md.pat_mode = ma;
7755 * If "m" is a normal page, update its direct mapping. This update
7756 * can be relied upon to perform any cache operations that are
7757 * required for data coherence.
7759 if ((m->flags & PG_FICTITIOUS) == 0 &&
7760 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7762 panic("memory attribute change on the direct map failed");
7766 * Changes the specified virtual address range's memory type to that given by
7767 * the parameter "mode". The specified virtual address range must be
7768 * completely contained within either the direct map or the kernel map. If
7769 * the virtual address range is contained within the kernel map, then the
7770 * memory type for each of the corresponding ranges of the direct map is also
7771 * changed. (The corresponding ranges of the direct map are those ranges that
7772 * map the same physical pages as the specified virtual address range.) These
7773 * changes to the direct map are necessary because Intel describes the
7774 * behavior of their processors as "undefined" if two or more mappings to the
7775 * same physical page have different memory types.
7777 * Returns zero if the change completed successfully, and either EINVAL or
7778 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7779 * of the virtual address range was not mapped, and ENOMEM is returned if
7780 * there was insufficient memory available to complete the change. In the
7781 * latter case, the memory type may have been changed on some part of the
7782 * virtual address range or the direct map.
7785 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7789 PMAP_LOCK(kernel_pmap);
7790 error = pmap_change_attr_locked(va, size, mode, false);
7791 PMAP_UNLOCK(kernel_pmap);
7796 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, bool noflush)
7798 vm_offset_t base, offset, tmpva;
7799 vm_paddr_t pa_start, pa_end, pa_end1;
7803 int cache_bits_pte, cache_bits_pde, error;
7806 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7807 base = trunc_page(va);
7808 offset = va & PAGE_MASK;
7809 size = round_page(offset + size);
7812 * Only supported on kernel virtual addresses, including the direct
7813 * map but excluding the recursive map.
7815 if (base < DMAP_MIN_ADDRESS)
7818 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7819 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7823 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7824 * into 4KB pages if required.
7826 for (tmpva = base; tmpva < base + size; ) {
7827 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7828 if (pdpe == NULL || *pdpe == 0)
7830 if (*pdpe & PG_PS) {
7832 * If the current 1GB page already has the required
7833 * memory type, then we need not demote this page. Just
7834 * increment tmpva to the next 1GB page frame.
7836 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7837 tmpva = trunc_1gpage(tmpva) + NBPDP;
7842 * If the current offset aligns with a 1GB page frame
7843 * and there is at least 1GB left within the range, then
7844 * we need not break down this page into 2MB pages.
7846 if ((tmpva & PDPMASK) == 0 &&
7847 tmpva + PDPMASK < base + size) {
7851 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7854 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7859 * If the current 2MB page already has the required
7860 * memory type, then we need not demote this page. Just
7861 * increment tmpva to the next 2MB page frame.
7863 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7864 tmpva = trunc_2mpage(tmpva) + NBPDR;
7869 * If the current offset aligns with a 2MB page frame
7870 * and there is at least 2MB left within the range, then
7871 * we need not break down this page into 4KB pages.
7873 if ((tmpva & PDRMASK) == 0 &&
7874 tmpva + PDRMASK < base + size) {
7878 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7881 pte = pmap_pde_to_pte(pde, tmpva);
7889 * Ok, all the pages exist, so run through them updating their
7890 * cache mode if required.
7892 pa_start = pa_end = 0;
7893 for (tmpva = base; tmpva < base + size; ) {
7894 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7895 if (*pdpe & PG_PS) {
7896 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7897 pmap_pde_attr(pdpe, cache_bits_pde,
7901 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7902 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7903 if (pa_start == pa_end) {
7904 /* Start physical address run. */
7905 pa_start = *pdpe & PG_PS_FRAME;
7906 pa_end = pa_start + NBPDP;
7907 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7910 /* Run ended, update direct map. */
7911 error = pmap_change_attr_locked(
7912 PHYS_TO_DMAP(pa_start),
7913 pa_end - pa_start, mode, noflush);
7916 /* Start physical address run. */
7917 pa_start = *pdpe & PG_PS_FRAME;
7918 pa_end = pa_start + NBPDP;
7921 tmpva = trunc_1gpage(tmpva) + NBPDP;
7924 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7926 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7927 pmap_pde_attr(pde, cache_bits_pde,
7931 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7932 (*pde & PG_PS_FRAME) < dmaplimit) {
7933 if (pa_start == pa_end) {
7934 /* Start physical address run. */
7935 pa_start = *pde & PG_PS_FRAME;
7936 pa_end = pa_start + NBPDR;
7937 } else if (pa_end == (*pde & PG_PS_FRAME))
7940 /* Run ended, update direct map. */
7941 error = pmap_change_attr_locked(
7942 PHYS_TO_DMAP(pa_start),
7943 pa_end - pa_start, mode, noflush);
7946 /* Start physical address run. */
7947 pa_start = *pde & PG_PS_FRAME;
7948 pa_end = pa_start + NBPDR;
7951 tmpva = trunc_2mpage(tmpva) + NBPDR;
7953 pte = pmap_pde_to_pte(pde, tmpva);
7954 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7955 pmap_pte_attr(pte, cache_bits_pte,
7959 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7960 (*pte & PG_FRAME) < dmaplimit) {
7961 if (pa_start == pa_end) {
7962 /* Start physical address run. */
7963 pa_start = *pte & PG_FRAME;
7964 pa_end = pa_start + PAGE_SIZE;
7965 } else if (pa_end == (*pte & PG_FRAME))
7966 pa_end += PAGE_SIZE;
7968 /* Run ended, update direct map. */
7969 error = pmap_change_attr_locked(
7970 PHYS_TO_DMAP(pa_start),
7971 pa_end - pa_start, mode, noflush);
7974 /* Start physical address run. */
7975 pa_start = *pte & PG_FRAME;
7976 pa_end = pa_start + PAGE_SIZE;
7982 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7983 pa_end1 = MIN(pa_end, dmaplimit);
7984 if (pa_start != pa_end1)
7985 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7986 pa_end1 - pa_start, mode, noflush);
7990 * Flush CPU caches if required to make sure any data isn't cached that
7991 * shouldn't be, etc.
7994 pmap_invalidate_range(kernel_pmap, base, tmpva);
7996 pmap_invalidate_cache_range(base, tmpva);
8002 * Demotes any mapping within the direct map region that covers more than the
8003 * specified range of physical addresses. This range's size must be a power
8004 * of two and its starting address must be a multiple of its size. Since the
8005 * demotion does not change any attributes of the mapping, a TLB invalidation
8006 * is not mandatory. The caller may, however, request a TLB invalidation.
8009 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8018 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8019 KASSERT((base & (len - 1)) == 0,
8020 ("pmap_demote_DMAP: base is not a multiple of len"));
8021 if (len < NBPDP && base < dmaplimit) {
8022 va = PHYS_TO_DMAP(base);
8024 PMAP_LOCK(kernel_pmap);
8025 pdpe = pmap_pdpe(kernel_pmap, va);
8026 if ((*pdpe & X86_PG_V) == 0)
8027 panic("pmap_demote_DMAP: invalid PDPE");
8028 if ((*pdpe & PG_PS) != 0) {
8029 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8030 panic("pmap_demote_DMAP: PDPE failed");
8034 pde = pmap_pdpe_to_pde(pdpe, va);
8035 if ((*pde & X86_PG_V) == 0)
8036 panic("pmap_demote_DMAP: invalid PDE");
8037 if ((*pde & PG_PS) != 0) {
8038 if (!pmap_demote_pde(kernel_pmap, pde, va))
8039 panic("pmap_demote_DMAP: PDE failed");
8043 if (changed && invalidate)
8044 pmap_invalidate_page(kernel_pmap, va);
8045 PMAP_UNLOCK(kernel_pmap);
8050 * perform the pmap work for mincore
8053 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8056 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8060 PG_A = pmap_accessed_bit(pmap);
8061 PG_M = pmap_modified_bit(pmap);
8062 PG_V = pmap_valid_bit(pmap);
8063 PG_RW = pmap_rw_bit(pmap);
8067 pdep = pmap_pde(pmap, addr);
8068 if (pdep != NULL && (*pdep & PG_V)) {
8069 if (*pdep & PG_PS) {
8071 /* Compute the physical address of the 4KB page. */
8072 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8074 val = MINCORE_SUPER;
8076 pte = *pmap_pde_to_pte(pdep, addr);
8077 pa = pte & PG_FRAME;
8085 if ((pte & PG_V) != 0) {
8086 val |= MINCORE_INCORE;
8087 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8088 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8089 if ((pte & PG_A) != 0)
8090 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8092 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8093 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8094 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8095 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8096 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8099 PA_UNLOCK_COND(*locked_pa);
8105 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8107 uint32_t gen, new_gen, pcid_next;
8109 CRITICAL_ASSERT(curthread);
8110 gen = PCPU_GET(pcid_gen);
8111 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8112 return (pti ? 0 : CR3_PCID_SAVE);
8113 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8114 return (CR3_PCID_SAVE);
8115 pcid_next = PCPU_GET(pcid_next);
8116 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8117 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8118 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8119 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8120 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8124 PCPU_SET(pcid_gen, new_gen);
8125 pcid_next = PMAP_PCID_KERN + 1;
8129 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8130 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8131 PCPU_SET(pcid_next, pcid_next + 1);
8136 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8140 cached = pmap_pcid_alloc(pmap, cpuid);
8141 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8142 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8143 pmap->pm_pcids[cpuid].pm_pcid));
8144 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8145 pmap == kernel_pmap,
8146 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8147 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8152 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8155 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8156 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
8160 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8162 struct invpcid_descr d;
8163 uint64_t cached, cr3, kcr3, ucr3;
8165 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8167 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8168 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8169 PCPU_SET(curpmap, pmap);
8170 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8171 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8174 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8176 * Explicitly invalidate translations cached from the
8177 * user page table. They are not automatically
8178 * flushed by reload of cr3 with the kernel page table
8181 * Note that the if() condition is resolved statically
8182 * by using the function argument instead of
8183 * runtime-evaluated invpcid_works value.
8185 if (invpcid_works1) {
8186 d.pcid = PMAP_PCID_USER_PT |
8187 pmap->pm_pcids[cpuid].pm_pcid;
8190 invpcid(&d, INVPCID_CTX);
8192 pmap_pti_pcid_invalidate(ucr3, kcr3);
8196 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8197 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8199 PCPU_INC(pm_save_cnt);
8203 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8206 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8207 pmap_activate_sw_pti_post(td, pmap);
8211 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8217 * If the INVPCID instruction is not available,
8218 * invltlb_pcid_handler() is used to handle an invalidate_all
8219 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8220 * sequence of operations has a window where %CR3 is loaded
8221 * with the new pmap's PML4 address, but the curpmap value has
8222 * not yet been updated. This causes the invltlb IPI handler,
8223 * which is called between the updates, to execute as a NOP,
8224 * which leaves stale TLB entries.
8226 * Note that the most typical use of pmap_activate_sw(), from
8227 * the context switch, is immune to this race, because
8228 * interrupts are disabled (while the thread lock is owned),
8229 * and the IPI happens after curpmap is updated. Protect
8230 * other callers in a similar way, by disabling interrupts
8231 * around the %cr3 register reload and curpmap assignment.
8233 rflags = intr_disable();
8234 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8235 intr_restore(rflags);
8236 pmap_activate_sw_pti_post(td, pmap);
8240 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8243 uint64_t cached, cr3;
8245 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8247 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8248 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8250 PCPU_SET(curpmap, pmap);
8252 PCPU_INC(pm_save_cnt);
8256 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8261 rflags = intr_disable();
8262 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8263 intr_restore(rflags);
8267 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8268 u_int cpuid __unused)
8271 load_cr3(pmap->pm_cr3);
8272 PCPU_SET(curpmap, pmap);
8276 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8277 u_int cpuid __unused)
8280 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8281 PCPU_SET(kcr3, pmap->pm_cr3);
8282 PCPU_SET(ucr3, pmap->pm_ucr3);
8283 pmap_activate_sw_pti_post(td, pmap);
8286 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8290 if (pmap_pcid_enabled && pti && invpcid_works)
8291 return (pmap_activate_sw_pcid_invpcid_pti);
8292 else if (pmap_pcid_enabled && pti && !invpcid_works)
8293 return (pmap_activate_sw_pcid_noinvpcid_pti);
8294 else if (pmap_pcid_enabled && !pti && invpcid_works)
8295 return (pmap_activate_sw_pcid_nopti);
8296 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8297 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8298 else if (!pmap_pcid_enabled && pti)
8299 return (pmap_activate_sw_nopcid_pti);
8300 else /* if (!pmap_pcid_enabled && !pti) */
8301 return (pmap_activate_sw_nopcid_nopti);
8305 pmap_activate_sw(struct thread *td)
8307 pmap_t oldpmap, pmap;
8310 oldpmap = PCPU_GET(curpmap);
8311 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8312 if (oldpmap == pmap)
8314 cpuid = PCPU_GET(cpuid);
8316 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8318 CPU_SET(cpuid, &pmap->pm_active);
8320 pmap_activate_sw_mode(td, pmap, cpuid);
8322 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8324 CPU_CLR(cpuid, &oldpmap->pm_active);
8329 pmap_activate(struct thread *td)
8333 pmap_activate_sw(td);
8338 pmap_activate_boot(pmap_t pmap)
8344 * kernel_pmap must be never deactivated, and we ensure that
8345 * by never activating it at all.
8347 MPASS(pmap != kernel_pmap);
8349 cpuid = PCPU_GET(cpuid);
8351 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8353 CPU_SET(cpuid, &pmap->pm_active);
8355 PCPU_SET(curpmap, pmap);
8357 kcr3 = pmap->pm_cr3;
8358 if (pmap_pcid_enabled)
8359 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8363 PCPU_SET(kcr3, kcr3);
8364 PCPU_SET(ucr3, PMAP_NO_CR3);
8368 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8373 * Increase the starting virtual address of the given mapping if a
8374 * different alignment might result in more superpage mappings.
8377 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8378 vm_offset_t *addr, vm_size_t size)
8380 vm_offset_t superpage_offset;
8384 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8385 offset += ptoa(object->pg_color);
8386 superpage_offset = offset & PDRMASK;
8387 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8388 (*addr & PDRMASK) == superpage_offset)
8390 if ((*addr & PDRMASK) < superpage_offset)
8391 *addr = (*addr & ~PDRMASK) + superpage_offset;
8393 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8397 static unsigned long num_dirty_emulations;
8398 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8399 &num_dirty_emulations, 0, NULL);
8401 static unsigned long num_accessed_emulations;
8402 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8403 &num_accessed_emulations, 0, NULL);
8405 static unsigned long num_superpage_accessed_emulations;
8406 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8407 &num_superpage_accessed_emulations, 0, NULL);
8409 static unsigned long ad_emulation_superpage_promotions;
8410 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8411 &ad_emulation_superpage_promotions, 0, NULL);
8412 #endif /* INVARIANTS */
8415 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8418 struct rwlock *lock;
8419 #if VM_NRESERVLEVEL > 0
8423 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8425 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8426 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8428 if (!pmap_emulate_ad_bits(pmap))
8431 PG_A = pmap_accessed_bit(pmap);
8432 PG_M = pmap_modified_bit(pmap);
8433 PG_V = pmap_valid_bit(pmap);
8434 PG_RW = pmap_rw_bit(pmap);
8440 pde = pmap_pde(pmap, va);
8441 if (pde == NULL || (*pde & PG_V) == 0)
8444 if ((*pde & PG_PS) != 0) {
8445 if (ftype == VM_PROT_READ) {
8447 atomic_add_long(&num_superpage_accessed_emulations, 1);
8455 pte = pmap_pde_to_pte(pde, va);
8456 if ((*pte & PG_V) == 0)
8459 if (ftype == VM_PROT_WRITE) {
8460 if ((*pte & PG_RW) == 0)
8463 * Set the modified and accessed bits simultaneously.
8465 * Intel EPT PTEs that do software emulation of A/D bits map
8466 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8467 * An EPT misconfiguration is triggered if the PTE is writable
8468 * but not readable (WR=10). This is avoided by setting PG_A
8469 * and PG_M simultaneously.
8471 *pte |= PG_M | PG_A;
8476 #if VM_NRESERVLEVEL > 0
8477 /* try to promote the mapping */
8478 if (va < VM_MAXUSER_ADDRESS)
8479 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8483 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8485 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8486 pmap_ps_enabled(pmap) &&
8487 (m->flags & PG_FICTITIOUS) == 0 &&
8488 vm_reserv_level_iffullpop(m) == 0) {
8489 pmap_promote_pde(pmap, pde, va, &lock);
8491 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8497 if (ftype == VM_PROT_WRITE)
8498 atomic_add_long(&num_dirty_emulations, 1);
8500 atomic_add_long(&num_accessed_emulations, 1);
8502 rv = 0; /* success */
8511 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8516 pt_entry_t *pte, PG_V;
8520 PG_V = pmap_valid_bit(pmap);
8523 pml4 = pmap_pml4e(pmap, va);
8525 if ((*pml4 & PG_V) == 0)
8528 pdp = pmap_pml4e_to_pdpe(pml4, va);
8530 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8533 pde = pmap_pdpe_to_pde(pdp, va);
8535 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8538 pte = pmap_pde_to_pte(pde, va);
8547 * Get the kernel virtual address of a set of physical pages. If there are
8548 * physical addresses not covered by the DMAP perform a transient mapping
8549 * that will be removed when calling pmap_unmap_io_transient.
8551 * \param page The pages the caller wishes to obtain the virtual
8552 * address on the kernel memory map.
8553 * \param vaddr On return contains the kernel virtual memory address
8554 * of the pages passed in the page parameter.
8555 * \param count Number of pages passed in.
8556 * \param can_fault TRUE if the thread using the mapped pages can take
8557 * page faults, FALSE otherwise.
8559 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8560 * finished or FALSE otherwise.
8564 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8565 boolean_t can_fault)
8568 boolean_t needs_mapping;
8570 int cache_bits, error __unused, i;
8573 * Allocate any KVA space that we need, this is done in a separate
8574 * loop to prevent calling vmem_alloc while pinned.
8576 needs_mapping = FALSE;
8577 for (i = 0; i < count; i++) {
8578 paddr = VM_PAGE_TO_PHYS(page[i]);
8579 if (__predict_false(paddr >= dmaplimit)) {
8580 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8581 M_BESTFIT | M_WAITOK, &vaddr[i]);
8582 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8583 needs_mapping = TRUE;
8585 vaddr[i] = PHYS_TO_DMAP(paddr);
8589 /* Exit early if everything is covered by the DMAP */
8594 * NB: The sequence of updating a page table followed by accesses
8595 * to the corresponding pages used in the !DMAP case is subject to
8596 * the situation described in the "AMD64 Architecture Programmer's
8597 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8598 * Coherency Considerations". Therefore, issuing the INVLPG right
8599 * after modifying the PTE bits is crucial.
8603 for (i = 0; i < count; i++) {
8604 paddr = VM_PAGE_TO_PHYS(page[i]);
8605 if (paddr >= dmaplimit) {
8608 * Slow path, since we can get page faults
8609 * while mappings are active don't pin the
8610 * thread to the CPU and instead add a global
8611 * mapping visible to all CPUs.
8613 pmap_qenter(vaddr[i], &page[i], 1);
8615 pte = vtopte(vaddr[i]);
8616 cache_bits = pmap_cache_bits(kernel_pmap,
8617 page[i]->md.pat_mode, 0);
8618 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8625 return (needs_mapping);
8629 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8630 boolean_t can_fault)
8637 for (i = 0; i < count; i++) {
8638 paddr = VM_PAGE_TO_PHYS(page[i]);
8639 if (paddr >= dmaplimit) {
8641 pmap_qremove(vaddr[i], 1);
8642 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8648 pmap_quick_enter_page(vm_page_t m)
8652 paddr = VM_PAGE_TO_PHYS(m);
8653 if (paddr < dmaplimit)
8654 return (PHYS_TO_DMAP(paddr));
8655 mtx_lock_spin(&qframe_mtx);
8656 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8657 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8658 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8663 pmap_quick_remove_page(vm_offset_t addr)
8668 pte_store(vtopte(qframe), 0);
8670 mtx_unlock_spin(&qframe_mtx);
8674 * Pdp pages from the large map are managed differently from either
8675 * kernel or user page table pages. They are permanently allocated at
8676 * initialization time, and their wire count is permanently set to
8677 * zero. The pml4 entries pointing to those pages are copied into
8678 * each allocated pmap.
8680 * In contrast, pd and pt pages are managed like user page table
8681 * pages. They are dynamically allocated, and their wire count
8682 * represents the number of valid entries within the page.
8685 pmap_large_map_getptp_unlocked(void)
8689 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8691 if (m != NULL && (m->flags & PG_ZERO) == 0)
8697 pmap_large_map_getptp(void)
8701 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8702 m = pmap_large_map_getptp_unlocked();
8704 PMAP_UNLOCK(kernel_pmap);
8706 PMAP_LOCK(kernel_pmap);
8707 /* Callers retry. */
8712 static pdp_entry_t *
8713 pmap_large_map_pdpe(vm_offset_t va)
8715 vm_pindex_t pml4_idx;
8718 pml4_idx = pmap_pml4e_index(va);
8719 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8720 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8722 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8723 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8724 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8725 "LMSPML4I %#jx lm_ents %d",
8726 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8727 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8728 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8732 pmap_large_map_pde(vm_offset_t va)
8739 pdpe = pmap_large_map_pdpe(va);
8741 m = pmap_large_map_getptp();
8744 mphys = VM_PAGE_TO_PHYS(m);
8745 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8747 MPASS((*pdpe & X86_PG_PS) == 0);
8748 mphys = *pdpe & PG_FRAME;
8750 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
8754 pmap_large_map_pte(vm_offset_t va)
8761 pde = pmap_large_map_pde(va);
8763 m = pmap_large_map_getptp();
8766 mphys = VM_PAGE_TO_PHYS(m);
8767 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8768 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
8770 MPASS((*pde & X86_PG_PS) == 0);
8771 mphys = *pde & PG_FRAME;
8773 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
8777 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
8778 vmem_addr_t *vmem_res)
8782 * Large mappings are all but static. Consequently, there
8783 * is no point in waiting for an earlier allocation to be
8786 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
8787 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
8791 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
8797 vm_offset_t va, inc;
8798 vmem_addr_t vmem_res;
8802 if (len == 0 || spa + len < spa)
8805 /* See if DMAP can serve. */
8806 if (spa + len <= dmaplimit) {
8807 va = PHYS_TO_DMAP(spa);
8809 return (pmap_change_attr(va, len, mattr));
8813 * No, allocate KVA. Fit the address with best possible
8814 * alignment for superpages. Fall back to worse align if
8818 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
8819 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
8820 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
8822 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
8824 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
8827 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
8832 * Fill pagetable. PG_M is not pre-set, we scan modified bits
8833 * in the pagetable to minimize flushing. No need to
8834 * invalidate TLB, since we only update invalid entries.
8836 PMAP_LOCK(kernel_pmap);
8837 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
8839 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
8840 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
8841 pdpe = pmap_large_map_pdpe(va);
8843 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
8844 X86_PG_V | X86_PG_A | pg_nx |
8845 pmap_cache_bits(kernel_pmap, mattr, TRUE);
8847 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
8848 (va & PDRMASK) == 0) {
8849 pde = pmap_large_map_pde(va);
8851 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
8852 X86_PG_V | X86_PG_A | pg_nx |
8853 pmap_cache_bits(kernel_pmap, mattr, TRUE);
8854 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
8858 pte = pmap_large_map_pte(va);
8860 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
8861 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
8863 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
8868 PMAP_UNLOCK(kernel_pmap);
8871 *addr = (void *)vmem_res;
8876 pmap_large_unmap(void *svaa, vm_size_t len)
8878 vm_offset_t sva, va;
8880 pdp_entry_t *pdpe, pdp;
8881 pd_entry_t *pde, pd;
8884 struct spglist spgf;
8886 sva = (vm_offset_t)svaa;
8887 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
8888 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
8892 KASSERT(LARGEMAP_MIN_ADDRESS <= sva && sva + len <=
8893 LARGEMAP_MAX_ADDRESS + NBPML4 * (u_long)lm_ents,
8894 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
8895 PMAP_LOCK(kernel_pmap);
8896 for (va = sva; va < sva + len; va += inc) {
8897 pdpe = pmap_large_map_pdpe(va);
8899 KASSERT((pdp & X86_PG_V) != 0,
8900 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
8901 (u_long)pdpe, pdp));
8902 if ((pdp & X86_PG_PS) != 0) {
8903 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
8904 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
8905 (u_long)pdpe, pdp));
8906 KASSERT((va & PDPMASK) == 0,
8907 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
8908 (u_long)pdpe, pdp));
8909 KASSERT(va + NBPDP <= sva + len,
8910 ("unmap covers partial 1GB page, sva %#lx va %#lx "
8911 "pdpe %#lx pdp %#lx len %#lx", sva, va,
8912 (u_long)pdpe, pdp, len));
8917 pde = pmap_pdpe_to_pde(pdpe, va);
8919 KASSERT((pd & X86_PG_V) != 0,
8920 ("invalid pd va %#lx pde %#lx pd %#lx", va,
8922 if ((pd & X86_PG_PS) != 0) {
8923 KASSERT((va & PDRMASK) == 0,
8924 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
8926 KASSERT(va + NBPDR <= sva + len,
8927 ("unmap covers partial 2MB page, sva %#lx va %#lx "
8928 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
8932 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
8934 if (m->wire_count == 0) {
8936 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8940 pte = pmap_pde_to_pte(pde, va);
8941 KASSERT((*pte & X86_PG_V) != 0,
8942 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8943 (u_long)pte, *pte));
8946 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
8948 if (m->wire_count == 0) {
8950 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8951 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
8953 if (m->wire_count == 0) {
8955 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8959 pmap_invalidate_range(kernel_pmap, sva, sva + len);
8960 PMAP_UNLOCK(kernel_pmap);
8961 vm_page_free_pages_toq(&spgf, false);
8962 vmem_free(large_vmem, sva, len);
8966 pmap_large_map_wb_fence_mfence(void)
8973 pmap_large_map_wb_fence_sfence(void)
8980 pmap_large_map_wb_fence_nop(void)
8984 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void), static)
8987 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8988 return (pmap_large_map_wb_fence_mfence);
8989 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
8990 CPUID_STDEXT_CLFLUSHOPT)) == 0)
8991 return (pmap_large_map_wb_fence_sfence);
8993 /* clflush is strongly enough ordered */
8994 return (pmap_large_map_wb_fence_nop);
8998 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9001 for (; len > 0; len -= cpu_clflush_line_size,
9002 va += cpu_clflush_line_size)
9007 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9010 for (; len > 0; len -= cpu_clflush_line_size,
9011 va += cpu_clflush_line_size)
9016 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9019 for (; len > 0; len -= cpu_clflush_line_size,
9020 va += cpu_clflush_line_size)
9025 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9029 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t),
9033 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9034 return (pmap_large_map_flush_range_clwb);
9035 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9036 return (pmap_large_map_flush_range_clflushopt);
9037 else if ((cpu_feature & CPUID_CLFSH) != 0)
9038 return (pmap_large_map_flush_range_clflush);
9040 return (pmap_large_map_flush_range_nop);
9044 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9046 volatile u_long *pe;
9052 for (va = sva; va < eva; va += inc) {
9054 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9055 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9057 if ((p & X86_PG_PS) != 0)
9061 pe = (volatile u_long *)pmap_large_map_pde(va);
9063 if ((p & X86_PG_PS) != 0)
9067 pe = (volatile u_long *)pmap_large_map_pte(va);
9073 if ((p & X86_PG_AVAIL1) != 0) {
9075 * Spin-wait for the end of a parallel
9082 * If we saw other write-back
9083 * occuring, we cannot rely on PG_M to
9084 * indicate state of the cache. The
9085 * PG_M bit is cleared before the
9086 * flush to avoid ignoring new writes,
9087 * and writes which are relevant for
9088 * us might happen after.
9094 if ((p & X86_PG_M) != 0 || seen_other) {
9095 if (!atomic_fcmpset_long(pe, &p,
9096 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9098 * If we saw PG_M without
9099 * PG_AVAIL1, and then on the
9100 * next attempt we do not
9101 * observe either PG_M or
9102 * PG_AVAIL1, the other
9103 * write-back started after us
9104 * and finished before us. We
9105 * can rely on it doing our
9109 pmap_large_map_flush_range(va, inc);
9110 atomic_clear_long(pe, X86_PG_AVAIL1);
9119 * Write-back cache lines for the given address range.
9121 * Must be called only on the range or sub-range returned from
9122 * pmap_large_map(). Must not be called on the coalesced ranges.
9124 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9125 * instructions support.
9128 pmap_large_map_wb(void *svap, vm_size_t len)
9130 vm_offset_t eva, sva;
9132 sva = (vm_offset_t)svap;
9134 pmap_large_map_wb_fence();
9135 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9136 pmap_large_map_flush_range(sva, len);
9138 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9139 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9140 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9141 pmap_large_map_wb_large(sva, eva);
9143 pmap_large_map_wb_fence();
9147 pmap_pti_alloc_page(void)
9151 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9152 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9153 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9158 pmap_pti_free_page(vm_page_t m)
9161 KASSERT(m->wire_count > 0, ("page %p not wired", m));
9162 if (!vm_page_unwire_noq(m))
9164 vm_page_free_zero(m);
9178 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9179 VM_OBJECT_WLOCK(pti_obj);
9180 pml4_pg = pmap_pti_alloc_page();
9181 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9182 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9183 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9184 pdpe = pmap_pti_pdpe(va);
9185 pmap_pti_wire_pte(pdpe);
9187 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9188 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9189 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9190 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9191 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9192 sizeof(struct gate_descriptor) * NIDT, false);
9193 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9194 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9196 /* Doublefault stack IST 1 */
9197 va = common_tss[i].tss_ist1;
9198 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9199 /* NMI stack IST 2 */
9200 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9201 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9202 /* MC# stack IST 3 */
9203 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9204 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9205 /* DB# stack IST 4 */
9206 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9207 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9209 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9210 (vm_offset_t)etext, true);
9211 pti_finalized = true;
9212 VM_OBJECT_WUNLOCK(pti_obj);
9214 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9216 static pdp_entry_t *
9217 pmap_pti_pdpe(vm_offset_t va)
9219 pml4_entry_t *pml4e;
9222 vm_pindex_t pml4_idx;
9225 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9227 pml4_idx = pmap_pml4e_index(va);
9228 pml4e = &pti_pml4[pml4_idx];
9232 panic("pml4 alloc after finalization\n");
9233 m = pmap_pti_alloc_page();
9235 pmap_pti_free_page(m);
9236 mphys = *pml4e & ~PAGE_MASK;
9238 mphys = VM_PAGE_TO_PHYS(m);
9239 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9242 mphys = *pml4e & ~PAGE_MASK;
9244 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9249 pmap_pti_wire_pte(void *pte)
9253 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9254 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9259 pmap_pti_unwire_pde(void *pde, bool only_ref)
9263 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9264 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9265 MPASS(m->wire_count > 0);
9266 MPASS(only_ref || m->wire_count > 1);
9267 pmap_pti_free_page(m);
9271 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9276 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9277 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9278 MPASS(m->wire_count > 0);
9279 if (pmap_pti_free_page(m)) {
9280 pde = pmap_pti_pde(va);
9281 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9283 pmap_pti_unwire_pde(pde, false);
9288 pmap_pti_pde(vm_offset_t va)
9296 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9298 pdpe = pmap_pti_pdpe(va);
9300 m = pmap_pti_alloc_page();
9302 pmap_pti_free_page(m);
9303 MPASS((*pdpe & X86_PG_PS) == 0);
9304 mphys = *pdpe & ~PAGE_MASK;
9306 mphys = VM_PAGE_TO_PHYS(m);
9307 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9310 MPASS((*pdpe & X86_PG_PS) == 0);
9311 mphys = *pdpe & ~PAGE_MASK;
9314 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9315 pd_idx = pmap_pde_index(va);
9321 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9328 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9330 pde = pmap_pti_pde(va);
9331 if (unwire_pde != NULL) {
9333 pmap_pti_wire_pte(pde);
9336 m = pmap_pti_alloc_page();
9338 pmap_pti_free_page(m);
9339 MPASS((*pde & X86_PG_PS) == 0);
9340 mphys = *pde & ~(PAGE_MASK | pg_nx);
9342 mphys = VM_PAGE_TO_PHYS(m);
9343 *pde = mphys | X86_PG_RW | X86_PG_V;
9344 if (unwire_pde != NULL)
9345 *unwire_pde = false;
9348 MPASS((*pde & X86_PG_PS) == 0);
9349 mphys = *pde & ~(PAGE_MASK | pg_nx);
9352 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9353 pte += pmap_pte_index(va);
9359 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9363 pt_entry_t *pte, ptev;
9366 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9368 sva = trunc_page(sva);
9369 MPASS(sva > VM_MAXUSER_ADDRESS);
9370 eva = round_page(eva);
9372 for (; sva < eva; sva += PAGE_SIZE) {
9373 pte = pmap_pti_pte(sva, &unwire_pde);
9374 pa = pmap_kextract(sva);
9375 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9376 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9377 VM_MEMATTR_DEFAULT, FALSE);
9379 pte_store(pte, ptev);
9380 pmap_pti_wire_pte(pte);
9382 KASSERT(!pti_finalized,
9383 ("pti overlap after fin %#lx %#lx %#lx",
9385 KASSERT(*pte == ptev,
9386 ("pti non-identical pte after fin %#lx %#lx %#lx",
9390 pde = pmap_pti_pde(sva);
9391 pmap_pti_unwire_pde(pde, true);
9397 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9402 VM_OBJECT_WLOCK(pti_obj);
9403 pmap_pti_add_kva_locked(sva, eva, exec);
9404 VM_OBJECT_WUNLOCK(pti_obj);
9408 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9415 sva = rounddown2(sva, PAGE_SIZE);
9416 MPASS(sva > VM_MAXUSER_ADDRESS);
9417 eva = roundup2(eva, PAGE_SIZE);
9419 VM_OBJECT_WLOCK(pti_obj);
9420 for (va = sva; va < eva; va += PAGE_SIZE) {
9421 pte = pmap_pti_pte(va, NULL);
9422 KASSERT((*pte & X86_PG_V) != 0,
9423 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9424 (u_long)pte, *pte));
9426 pmap_pti_unwire_pte(pte, va);
9428 pmap_invalidate_range(kernel_pmap, sva, eva);
9429 VM_OBJECT_WUNLOCK(pti_obj);
9433 pkru_dup_range(void *ctx __unused, void *data)
9435 struct pmap_pkru_range *node, *new_node;
9437 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9438 if (new_node == NULL)
9441 memcpy(new_node, node, sizeof(*node));
9446 pkru_free_range(void *ctx __unused, void *node)
9449 uma_zfree(pmap_pkru_ranges_zone, node);
9453 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9456 struct pmap_pkru_range *ppr;
9459 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9460 MPASS(pmap->pm_type == PT_X86);
9461 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9462 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9463 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9465 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9468 ppr->pkru_keyidx = keyidx;
9469 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9470 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9472 uma_zfree(pmap_pkru_ranges_zone, ppr);
9477 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9480 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9481 MPASS(pmap->pm_type == PT_X86);
9482 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9483 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9487 pmap_pkru_deassign_all(pmap_t pmap)
9490 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9491 if (pmap->pm_type == PT_X86 &&
9492 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9493 rangeset_remove_all(&pmap->pm_pkru);
9497 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9499 struct pmap_pkru_range *ppr, *prev_ppr;
9502 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9503 if (pmap->pm_type != PT_X86 ||
9504 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9505 sva >= VM_MAXUSER_ADDRESS)
9507 MPASS(eva <= VM_MAXUSER_ADDRESS);
9508 for (va = sva, prev_ppr = NULL; va < eva;) {
9509 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9510 if ((ppr == NULL) ^ (prev_ppr == NULL))
9516 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9518 va = ppr->pkru_rs_el.re_end;
9524 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9526 struct pmap_pkru_range *ppr;
9528 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9529 if (pmap->pm_type != PT_X86 ||
9530 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9531 va >= VM_MAXUSER_ADDRESS)
9533 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9535 return (X86_PG_PKU(ppr->pkru_keyidx));
9540 pred_pkru_on_remove(void *ctx __unused, void *r)
9542 struct pmap_pkru_range *ppr;
9545 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9549 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9552 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9553 if (pmap->pm_type == PT_X86 &&
9554 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9555 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9556 pred_pkru_on_remove);
9561 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9564 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9565 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9566 MPASS(dst_pmap->pm_type == PT_X86);
9567 MPASS(src_pmap->pm_type == PT_X86);
9568 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9569 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9571 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9575 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9578 pml4_entry_t *pml4e;
9580 pd_entry_t newpde, ptpaddr, *pde;
9581 pt_entry_t newpte, *ptep, pte;
9582 vm_offset_t va, va_next;
9585 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9586 MPASS(pmap->pm_type == PT_X86);
9587 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9589 for (changed = false, va = sva; va < eva; va = va_next) {
9590 pml4e = pmap_pml4e(pmap, va);
9591 if ((*pml4e & X86_PG_V) == 0) {
9592 va_next = (va + NBPML4) & ~PML4MASK;
9598 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9599 if ((*pdpe & X86_PG_V) == 0) {
9600 va_next = (va + NBPDP) & ~PDPMASK;
9606 va_next = (va + NBPDR) & ~PDRMASK;
9610 pde = pmap_pdpe_to_pde(pdpe, va);
9615 MPASS((ptpaddr & X86_PG_V) != 0);
9616 if ((ptpaddr & PG_PS) != 0) {
9617 if (va + NBPDR == va_next && eva >= va_next) {
9618 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9620 if (newpde != ptpaddr) {
9625 } else if (!pmap_demote_pde(pmap, pde, va)) {
9633 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9634 ptep++, va += PAGE_SIZE) {
9636 if ((pte & X86_PG_V) == 0)
9638 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9639 if (newpte != pte) {
9646 pmap_invalidate_range(pmap, sva, eva);
9650 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9651 u_int keyidx, int flags)
9654 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9655 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9657 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9659 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9665 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9670 sva = trunc_page(sva);
9671 eva = round_page(eva);
9672 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9677 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9679 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9681 if (error != ENOMEM)
9689 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9693 sva = trunc_page(sva);
9694 eva = round_page(eva);
9695 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9700 error = pmap_pkru_deassign(pmap, sva, eva);
9702 pmap_pkru_update_range(pmap, sva, eva, 0);
9704 if (error != ENOMEM)
9712 DB_SHOW_COMMAND(pte, pmap_print_pte)
9718 pt_entry_t *pte, PG_V;
9722 db_printf("show pte addr\n");
9725 va = (vm_offset_t)addr;
9727 if (kdb_thread != NULL)
9728 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
9730 pmap = PCPU_GET(curpmap);
9732 PG_V = pmap_valid_bit(pmap);
9733 pml4 = pmap_pml4e(pmap, va);
9734 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
9735 if ((*pml4 & PG_V) == 0) {
9739 pdp = pmap_pml4e_to_pdpe(pml4, va);
9740 db_printf(" pdpe %#016lx", *pdp);
9741 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
9745 pde = pmap_pdpe_to_pde(pdp, va);
9746 db_printf(" pde %#016lx", *pde);
9747 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
9751 pte = pmap_pde_to_pte(pde, va);
9752 db_printf(" pte %#016lx\n", *pte);
9755 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
9760 a = (vm_paddr_t)addr;
9761 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
9763 db_printf("show phys2dmap addr\n");