2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/asan.h>
116 #include <sys/bitstring.h>
118 #include <sys/systm.h>
119 #include <sys/counter.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/malloc.h>
124 #include <sys/mman.h>
125 #include <sys/mutex.h>
126 #include <sys/proc.h>
127 #include <sys/rangeset.h>
128 #include <sys/rwlock.h>
129 #include <sys/sbuf.h>
132 #include <sys/turnstile.h>
133 #include <sys/vmem.h>
134 #include <sys/vmmeter.h>
135 #include <sys/sched.h>
136 #include <sys/sysctl.h>
144 #include <vm/vm_param.h>
145 #include <vm/vm_kern.h>
146 #include <vm/vm_page.h>
147 #include <vm/vm_map.h>
148 #include <vm/vm_object.h>
149 #include <vm/vm_extern.h>
150 #include <vm/vm_pageout.h>
151 #include <vm/vm_pager.h>
152 #include <vm/vm_phys.h>
153 #include <vm/vm_radix.h>
154 #include <vm/vm_reserv.h>
155 #include <vm/vm_dumpset.h>
158 #include <machine/asan.h>
159 #include <machine/intr_machdep.h>
160 #include <x86/apicvar.h>
161 #include <x86/ifunc.h>
162 #include <machine/cpu.h>
163 #include <machine/cputypes.h>
164 #include <machine/intr_machdep.h>
165 #include <machine/md_var.h>
166 #include <machine/pcb.h>
167 #include <machine/specialreg.h>
169 #include <machine/smp.h>
171 #include <machine/sysarch.h>
172 #include <machine/tss.h>
175 #define PMAP_MEMDOM MAXMEMDOM
177 #define PMAP_MEMDOM 1
180 static __inline boolean_t
181 pmap_type_guest(pmap_t pmap)
184 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
187 static __inline boolean_t
188 pmap_emulate_ad_bits(pmap_t pmap)
191 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
194 static __inline pt_entry_t
195 pmap_valid_bit(pmap_t pmap)
199 switch (pmap->pm_type) {
205 if (pmap_emulate_ad_bits(pmap))
206 mask = EPT_PG_EMUL_V;
211 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
217 static __inline pt_entry_t
218 pmap_rw_bit(pmap_t pmap)
222 switch (pmap->pm_type) {
228 if (pmap_emulate_ad_bits(pmap))
229 mask = EPT_PG_EMUL_RW;
234 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
240 static pt_entry_t pg_g;
242 static __inline pt_entry_t
243 pmap_global_bit(pmap_t pmap)
247 switch (pmap->pm_type) {
256 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
262 static __inline pt_entry_t
263 pmap_accessed_bit(pmap_t pmap)
267 switch (pmap->pm_type) {
273 if (pmap_emulate_ad_bits(pmap))
279 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
285 static __inline pt_entry_t
286 pmap_modified_bit(pmap_t pmap)
290 switch (pmap->pm_type) {
296 if (pmap_emulate_ad_bits(pmap))
302 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
308 static __inline pt_entry_t
309 pmap_pku_mask_bit(pmap_t pmap)
312 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
315 #if !defined(DIAGNOSTIC)
316 #ifdef __GNUC_GNU_INLINE__
317 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
319 #define PMAP_INLINE extern inline
326 #define PV_STAT(x) do { x ; } while (0)
328 #define PV_STAT(x) do { } while (0)
333 #define pa_index(pa) ({ \
334 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
335 ("address %lx beyond the last segment", (pa))); \
338 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
339 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
340 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
341 struct rwlock *_lock; \
342 if (__predict_false((pa) > pmap_last_pa)) \
343 _lock = &pv_dummy_large.pv_lock; \
345 _lock = &(pa_to_pmdp(pa)->pv_lock); \
349 #define pa_index(pa) ((pa) >> PDRSHIFT)
350 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
352 #define NPV_LIST_LOCKS MAXCPU
354 #define PHYS_TO_PV_LIST_LOCK(pa) \
355 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
358 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
359 struct rwlock **_lockp = (lockp); \
360 struct rwlock *_new_lock; \
362 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
363 if (_new_lock != *_lockp) { \
364 if (*_lockp != NULL) \
365 rw_wunlock(*_lockp); \
366 *_lockp = _new_lock; \
371 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
372 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
374 #define RELEASE_PV_LIST_LOCK(lockp) do { \
375 struct rwlock **_lockp = (lockp); \
377 if (*_lockp != NULL) { \
378 rw_wunlock(*_lockp); \
383 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
384 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
386 struct pmap kernel_pmap_store;
388 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
389 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
392 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
393 "Number of kernel page table pages allocated on bootup");
396 vm_paddr_t dmaplimit;
397 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
400 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
401 "VM/pmap parameters");
403 static int pg_ps_enabled = 1;
404 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
405 &pg_ps_enabled, 0, "Are large page mappings enabled?");
407 int __read_frequently la57 = 0;
408 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
410 "5-level paging for host is enabled");
413 pmap_is_la57(pmap_t pmap)
415 if (pmap->pm_type == PT_X86)
417 return (false); /* XXXKIB handle EPT */
420 #define PAT_INDEX_SIZE 8
421 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
423 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
424 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
425 static u_int64_t KPDPphys; /* phys addr of kernel level 3 */
426 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
427 u_int64_t KPML5phys; /* phys addr of kernel level 5,
431 static uint64_t KASANPDPphys;
434 static pml4_entry_t *kernel_pml4;
435 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
436 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
437 static int ndmpdpphys; /* number of DMPDPphys pages */
439 vm_paddr_t kernphys; /* phys addr of start of bootstrap data */
440 vm_paddr_t KERNend; /* and the end */
443 * pmap_mapdev support pre initialization (i.e. console)
445 #define PMAP_PREINIT_MAPPING_COUNT 8
446 static struct pmap_preinit_mapping {
451 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
452 static int pmap_initialized;
455 * Data for the pv entry allocation mechanism.
456 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
460 pc_to_domain(struct pv_chunk *pc)
463 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
467 pc_to_domain(struct pv_chunk *pc __unused)
474 struct pv_chunks_list {
476 TAILQ_HEAD(pch, pv_chunk) pvc_list;
478 } __aligned(CACHE_LINE_SIZE);
480 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
483 struct pmap_large_md_page {
484 struct rwlock pv_lock;
485 struct md_page pv_page;
488 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
489 #define pv_dummy pv_dummy_large.pv_page
490 __read_mostly static struct pmap_large_md_page *pv_table;
491 __read_mostly vm_paddr_t pmap_last_pa;
493 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
494 static u_long pv_invl_gen[NPV_LIST_LOCKS];
495 static struct md_page *pv_table;
496 static struct md_page pv_dummy;
500 * All those kernel PT submaps that BSD is so fond of
502 pt_entry_t *CMAP1 = NULL;
504 static vm_offset_t qframe = 0;
505 static struct mtx qframe_mtx;
507 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
509 static vmem_t *large_vmem;
510 static u_int lm_ents;
511 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
512 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
514 int pmap_pcid_enabled = 1;
515 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
516 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
517 int invpcid_works = 0;
518 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
519 "Is the invpcid instruction available ?");
521 int __read_frequently pti = 0;
522 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
524 "Page Table Isolation enabled");
525 static vm_object_t pti_obj;
526 static pml4_entry_t *pti_pml4;
527 static vm_pindex_t pti_pg_idx;
528 static bool pti_finalized;
530 struct pmap_pkru_range {
531 struct rs_el pkru_rs_el;
536 static uma_zone_t pmap_pkru_ranges_zone;
537 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
538 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
539 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
540 static void *pkru_dup_range(void *ctx, void *data);
541 static void pkru_free_range(void *ctx, void *node);
542 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
543 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
544 static void pmap_pkru_deassign_all(pmap_t pmap);
546 static COUNTER_U64_DEFINE_EARLY(pcid_save_cnt);
547 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLFLAG_RD,
548 &pcid_save_cnt, "Count of saved TLB context on switch");
550 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
551 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
552 static struct mtx invl_gen_mtx;
553 /* Fake lock object to satisfy turnstiles interface. */
554 static struct lock_object invl_gen_ts = {
557 static struct pmap_invl_gen pmap_invl_gen_head = {
561 static u_long pmap_invl_gen = 1;
562 static int pmap_invl_waiters;
563 static struct callout pmap_invl_callout;
564 static bool pmap_invl_callout_inited;
566 #define PMAP_ASSERT_NOT_IN_DI() \
567 KASSERT(pmap_not_in_di(), ("DI already started"))
574 if ((cpu_feature2 & CPUID2_CX16) == 0)
577 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
582 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
586 locked = pmap_di_locked();
587 return (sysctl_handle_int(oidp, &locked, 0, req));
589 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
590 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
591 "Locked delayed invalidation");
593 static bool pmap_not_in_di_l(void);
594 static bool pmap_not_in_di_u(void);
595 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
598 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
602 pmap_not_in_di_l(void)
604 struct pmap_invl_gen *invl_gen;
606 invl_gen = &curthread->td_md.md_invl_gen;
607 return (invl_gen->gen == 0);
611 pmap_thread_init_invl_gen_l(struct thread *td)
613 struct pmap_invl_gen *invl_gen;
615 invl_gen = &td->td_md.md_invl_gen;
620 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
622 struct turnstile *ts;
624 ts = turnstile_trywait(&invl_gen_ts);
625 if (*m_gen > atomic_load_long(invl_gen))
626 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
628 turnstile_cancel(ts);
632 pmap_delayed_invl_finish_unblock(u_long new_gen)
634 struct turnstile *ts;
636 turnstile_chain_lock(&invl_gen_ts);
637 ts = turnstile_lookup(&invl_gen_ts);
639 pmap_invl_gen = new_gen;
641 turnstile_broadcast(ts, TS_SHARED_QUEUE);
642 turnstile_unpend(ts);
644 turnstile_chain_unlock(&invl_gen_ts);
648 * Start a new Delayed Invalidation (DI) block of code, executed by
649 * the current thread. Within a DI block, the current thread may
650 * destroy both the page table and PV list entries for a mapping and
651 * then release the corresponding PV list lock before ensuring that
652 * the mapping is flushed from the TLBs of any processors with the
656 pmap_delayed_invl_start_l(void)
658 struct pmap_invl_gen *invl_gen;
661 invl_gen = &curthread->td_md.md_invl_gen;
662 PMAP_ASSERT_NOT_IN_DI();
663 mtx_lock(&invl_gen_mtx);
664 if (LIST_EMPTY(&pmap_invl_gen_tracker))
665 currgen = pmap_invl_gen;
667 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
668 invl_gen->gen = currgen + 1;
669 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
670 mtx_unlock(&invl_gen_mtx);
674 * Finish the DI block, previously started by the current thread. All
675 * required TLB flushes for the pages marked by
676 * pmap_delayed_invl_page() must be finished before this function is
679 * This function works by bumping the global DI generation number to
680 * the generation number of the current thread's DI, unless there is a
681 * pending DI that started earlier. In the latter case, bumping the
682 * global DI generation number would incorrectly signal that the
683 * earlier DI had finished. Instead, this function bumps the earlier
684 * DI's generation number to match the generation number of the
685 * current thread's DI.
688 pmap_delayed_invl_finish_l(void)
690 struct pmap_invl_gen *invl_gen, *next;
692 invl_gen = &curthread->td_md.md_invl_gen;
693 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
694 mtx_lock(&invl_gen_mtx);
695 next = LIST_NEXT(invl_gen, link);
697 pmap_delayed_invl_finish_unblock(invl_gen->gen);
699 next->gen = invl_gen->gen;
700 LIST_REMOVE(invl_gen, link);
701 mtx_unlock(&invl_gen_mtx);
706 pmap_not_in_di_u(void)
708 struct pmap_invl_gen *invl_gen;
710 invl_gen = &curthread->td_md.md_invl_gen;
711 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
715 pmap_thread_init_invl_gen_u(struct thread *td)
717 struct pmap_invl_gen *invl_gen;
719 invl_gen = &td->td_md.md_invl_gen;
721 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
725 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
727 uint64_t new_high, new_low, old_high, old_low;
730 old_low = new_low = 0;
731 old_high = new_high = (uintptr_t)0;
733 __asm volatile("lock;cmpxchg16b\t%1"
734 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
735 : "b"(new_low), "c" (new_high)
738 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
741 out->next = (void *)old_high;
744 out->next = (void *)new_high;
750 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
751 struct pmap_invl_gen *new_val)
753 uint64_t new_high, new_low, old_high, old_low;
756 new_low = new_val->gen;
757 new_high = (uintptr_t)new_val->next;
758 old_low = old_val->gen;
759 old_high = (uintptr_t)old_val->next;
761 __asm volatile("lock;cmpxchg16b\t%1"
762 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
763 : "b"(new_low), "c" (new_high)
768 static COUNTER_U64_DEFINE_EARLY(pv_page_count);
769 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_page_count, CTLFLAG_RD,
770 &pv_page_count, "Current number of allocated pv pages");
772 static COUNTER_U64_DEFINE_EARLY(user_pt_page_count);
773 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, user_pt_page_count, CTLFLAG_RD,
775 "Current number of allocated page table pages for userspace");
777 static COUNTER_U64_DEFINE_EARLY(kernel_pt_page_count);
778 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, kernel_pt_page_count, CTLFLAG_RD,
779 &kernel_pt_page_count,
780 "Current number of allocated page table pages for the kernel");
784 static COUNTER_U64_DEFINE_EARLY(invl_start_restart);
785 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_start_restart,
786 CTLFLAG_RD, &invl_start_restart,
787 "Number of delayed TLB invalidation request restarts");
789 static COUNTER_U64_DEFINE_EARLY(invl_finish_restart);
790 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
791 &invl_finish_restart,
792 "Number of delayed TLB invalidation completion restarts");
794 static int invl_max_qlen;
795 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
797 "Maximum delayed TLB invalidation request queue length");
800 #define di_delay locks_delay
803 pmap_delayed_invl_start_u(void)
805 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
807 struct lock_delay_arg lda;
815 invl_gen = &td->td_md.md_invl_gen;
816 PMAP_ASSERT_NOT_IN_DI();
817 lock_delay_arg_init(&lda, &di_delay);
818 invl_gen->saved_pri = 0;
819 pri = td->td_base_pri;
822 pri = td->td_base_pri;
824 invl_gen->saved_pri = pri;
831 for (p = &pmap_invl_gen_head;; p = prev.next) {
833 prevl = (uintptr_t)atomic_load_ptr(&p->next);
834 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
835 PV_STAT(counter_u64_add(invl_start_restart, 1));
841 prev.next = (void *)prevl;
844 if ((ii = invl_max_qlen) < i)
845 atomic_cmpset_int(&invl_max_qlen, ii, i);
848 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
849 PV_STAT(counter_u64_add(invl_start_restart, 1));
854 new_prev.gen = prev.gen;
855 new_prev.next = invl_gen;
856 invl_gen->gen = prev.gen + 1;
858 /* Formal fence between store to invl->gen and updating *p. */
859 atomic_thread_fence_rel();
862 * After inserting an invl_gen element with invalid bit set,
863 * this thread blocks any other thread trying to enter the
864 * delayed invalidation block. Do not allow to remove us from
865 * the CPU, because it causes starvation for other threads.
870 * ABA for *p is not possible there, since p->gen can only
871 * increase. So if the *p thread finished its di, then
872 * started a new one and got inserted into the list at the
873 * same place, its gen will appear greater than the previously
876 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
878 PV_STAT(counter_u64_add(invl_start_restart, 1));
884 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
885 * invl_gen->next, allowing other threads to iterate past us.
886 * pmap_di_store_invl() provides fence between the generation
887 * write and the update of next.
889 invl_gen->next = NULL;
894 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
895 struct pmap_invl_gen *p)
897 struct pmap_invl_gen prev, new_prev;
901 * Load invl_gen->gen after setting invl_gen->next
902 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
903 * generations to propagate to our invl_gen->gen. Lock prefix
904 * in atomic_set_ptr() worked as seq_cst fence.
906 mygen = atomic_load_long(&invl_gen->gen);
908 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
911 KASSERT(prev.gen < mygen,
912 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
913 new_prev.gen = mygen;
914 new_prev.next = (void *)((uintptr_t)invl_gen->next &
915 ~PMAP_INVL_GEN_NEXT_INVALID);
917 /* Formal fence between load of prev and storing update to it. */
918 atomic_thread_fence_rel();
920 return (pmap_di_store_invl(p, &prev, &new_prev));
924 pmap_delayed_invl_finish_u(void)
926 struct pmap_invl_gen *invl_gen, *p;
928 struct lock_delay_arg lda;
932 invl_gen = &td->td_md.md_invl_gen;
933 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
934 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
935 ("missed invl_start: INVALID"));
936 lock_delay_arg_init(&lda, &di_delay);
939 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
940 prevl = (uintptr_t)atomic_load_ptr(&p->next);
941 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
942 PV_STAT(counter_u64_add(invl_finish_restart, 1));
946 if ((void *)prevl == invl_gen)
951 * It is legitimate to not find ourself on the list if a
952 * thread before us finished its DI and started it again.
954 if (__predict_false(p == NULL)) {
955 PV_STAT(counter_u64_add(invl_finish_restart, 1));
961 atomic_set_ptr((uintptr_t *)&invl_gen->next,
962 PMAP_INVL_GEN_NEXT_INVALID);
963 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
964 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
965 PMAP_INVL_GEN_NEXT_INVALID);
967 PV_STAT(counter_u64_add(invl_finish_restart, 1));
972 if (atomic_load_int(&pmap_invl_waiters) > 0)
973 pmap_delayed_invl_finish_unblock(0);
974 if (invl_gen->saved_pri != 0) {
976 sched_prio(td, invl_gen->saved_pri);
982 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
984 struct pmap_invl_gen *p, *pn;
989 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
991 nextl = (uintptr_t)atomic_load_ptr(&p->next);
992 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
993 td = first ? NULL : __containerof(p, struct thread,
995 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
996 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
997 td != NULL ? td->td_tid : -1);
1003 static COUNTER_U64_DEFINE_EARLY(invl_wait);
1004 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait,
1005 CTLFLAG_RD, &invl_wait,
1006 "Number of times DI invalidation blocked pmap_remove_all/write");
1008 static COUNTER_U64_DEFINE_EARLY(invl_wait_slow);
1009 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD,
1010 &invl_wait_slow, "Number of slow invalidation waits for lockless DI");
1016 pmap_delayed_invl_genp(vm_page_t m)
1021 pa = VM_PAGE_TO_PHYS(m);
1022 if (__predict_false((pa) > pmap_last_pa))
1023 gen = &pv_dummy_large.pv_invl_gen;
1025 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1031 pmap_delayed_invl_genp(vm_page_t m)
1034 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1039 pmap_delayed_invl_callout_func(void *arg __unused)
1042 if (atomic_load_int(&pmap_invl_waiters) == 0)
1044 pmap_delayed_invl_finish_unblock(0);
1048 pmap_delayed_invl_callout_init(void *arg __unused)
1051 if (pmap_di_locked())
1053 callout_init(&pmap_invl_callout, 1);
1054 pmap_invl_callout_inited = true;
1056 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1057 pmap_delayed_invl_callout_init, NULL);
1060 * Ensure that all currently executing DI blocks, that need to flush
1061 * TLB for the given page m, actually flushed the TLB at the time the
1062 * function returned. If the page m has an empty PV list and we call
1063 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1064 * valid mapping for the page m in either its page table or TLB.
1066 * This function works by blocking until the global DI generation
1067 * number catches up with the generation number associated with the
1068 * given page m and its PV list. Since this function's callers
1069 * typically own an object lock and sometimes own a page lock, it
1070 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1074 pmap_delayed_invl_wait_l(vm_page_t m)
1078 bool accounted = false;
1081 m_gen = pmap_delayed_invl_genp(m);
1082 while (*m_gen > pmap_invl_gen) {
1085 counter_u64_add(invl_wait, 1);
1089 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1094 pmap_delayed_invl_wait_u(vm_page_t m)
1097 struct lock_delay_arg lda;
1101 m_gen = pmap_delayed_invl_genp(m);
1102 lock_delay_arg_init(&lda, &di_delay);
1103 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1104 if (fast || !pmap_invl_callout_inited) {
1105 PV_STAT(counter_u64_add(invl_wait, 1));
1110 * The page's invalidation generation number
1111 * is still below the current thread's number.
1112 * Prepare to block so that we do not waste
1113 * CPU cycles or worse, suffer livelock.
1115 * Since it is impossible to block without
1116 * racing with pmap_delayed_invl_finish_u(),
1117 * prepare for the race by incrementing
1118 * pmap_invl_waiters and arming a 1-tick
1119 * callout which will unblock us if we lose
1122 atomic_add_int(&pmap_invl_waiters, 1);
1125 * Re-check the current thread's invalidation
1126 * generation after incrementing
1127 * pmap_invl_waiters, so that there is no race
1128 * with pmap_delayed_invl_finish_u() setting
1129 * the page generation and checking
1130 * pmap_invl_waiters. The only race allowed
1131 * is for a missed unblock, which is handled
1135 atomic_load_long(&pmap_invl_gen_head.gen)) {
1136 callout_reset(&pmap_invl_callout, 1,
1137 pmap_delayed_invl_callout_func, NULL);
1138 PV_STAT(counter_u64_add(invl_wait_slow, 1));
1139 pmap_delayed_invl_wait_block(m_gen,
1140 &pmap_invl_gen_head.gen);
1142 atomic_add_int(&pmap_invl_waiters, -1);
1147 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1150 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1151 pmap_thread_init_invl_gen_u);
1154 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1157 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1158 pmap_delayed_invl_start_u);
1161 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1164 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1165 pmap_delayed_invl_finish_u);
1168 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1171 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1172 pmap_delayed_invl_wait_u);
1176 * Mark the page m's PV list as participating in the current thread's
1177 * DI block. Any threads concurrently using m's PV list to remove or
1178 * restrict all mappings to m will wait for the current thread's DI
1179 * block to complete before proceeding.
1181 * The function works by setting the DI generation number for m's PV
1182 * list to at least the DI generation number of the current thread.
1183 * This forces a caller of pmap_delayed_invl_wait() to block until
1184 * current thread calls pmap_delayed_invl_finish().
1187 pmap_delayed_invl_page(vm_page_t m)
1191 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1192 gen = curthread->td_md.md_invl_gen.gen;
1195 m_gen = pmap_delayed_invl_genp(m);
1203 static caddr_t crashdumpmap;
1206 * Internal flags for pmap_enter()'s helper functions.
1208 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1209 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1212 * Internal flags for pmap_mapdev_internal() and
1213 * pmap_change_props_locked().
1215 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1216 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1217 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1219 TAILQ_HEAD(pv_chunklist, pv_chunk);
1221 static void free_pv_chunk(struct pv_chunk *pc);
1222 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1223 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1224 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1225 static int popcnt_pc_map_pq(uint64_t *map);
1226 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1227 static void reserve_pv_entries(pmap_t pmap, int needed,
1228 struct rwlock **lockp);
1229 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1230 struct rwlock **lockp);
1231 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1232 u_int flags, struct rwlock **lockp);
1233 #if VM_NRESERVLEVEL > 0
1234 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1235 struct rwlock **lockp);
1237 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1238 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1241 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1242 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1243 vm_prot_t prot, int mode, int flags);
1244 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1245 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1246 vm_offset_t va, struct rwlock **lockp);
1247 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1249 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1250 vm_prot_t prot, struct rwlock **lockp);
1251 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1252 u_int flags, vm_page_t m, struct rwlock **lockp);
1253 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1254 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1255 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1256 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1257 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1259 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1261 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1263 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1264 static vm_page_t pmap_large_map_getptp_unlocked(void);
1265 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1266 #if VM_NRESERVLEVEL > 0
1267 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1268 struct rwlock **lockp);
1270 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1272 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1273 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1275 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1276 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1277 static void pmap_pti_wire_pte(void *pte);
1278 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1279 struct spglist *free, struct rwlock **lockp);
1280 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1281 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1282 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1283 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1284 struct spglist *free);
1285 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1286 pd_entry_t *pde, struct spglist *free,
1287 struct rwlock **lockp);
1288 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1289 vm_page_t m, struct rwlock **lockp);
1290 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1292 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1294 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1295 struct rwlock **lockp);
1296 static vm_page_t pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex,
1297 struct rwlock **lockp, vm_offset_t va);
1298 static vm_page_t pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex,
1299 struct rwlock **lockp, vm_offset_t va);
1300 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1301 struct rwlock **lockp);
1303 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1304 struct spglist *free);
1305 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1307 static vm_page_t pmap_alloc_pt_page(pmap_t, vm_pindex_t, int);
1308 static void pmap_free_pt_page(pmap_t, vm_page_t, bool);
1310 /********************/
1311 /* Inline functions */
1312 /********************/
1315 * Return a non-clipped indexes for a given VA, which are page table
1316 * pages indexes at the corresponding level.
1318 static __inline vm_pindex_t
1319 pmap_pde_pindex(vm_offset_t va)
1321 return (va >> PDRSHIFT);
1324 static __inline vm_pindex_t
1325 pmap_pdpe_pindex(vm_offset_t va)
1327 return (NUPDE + (va >> PDPSHIFT));
1330 static __inline vm_pindex_t
1331 pmap_pml4e_pindex(vm_offset_t va)
1333 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1336 static __inline vm_pindex_t
1337 pmap_pml5e_pindex(vm_offset_t va)
1339 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1342 static __inline pml4_entry_t *
1343 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1346 MPASS(pmap_is_la57(pmap));
1347 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1350 static __inline pml4_entry_t *
1351 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1354 MPASS(pmap_is_la57(pmap));
1355 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1358 static __inline pml4_entry_t *
1359 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1361 pml4_entry_t *pml4e;
1363 /* XXX MPASS(pmap_is_la57(pmap); */
1364 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1365 return (&pml4e[pmap_pml4e_index(va)]);
1368 /* Return a pointer to the PML4 slot that corresponds to a VA */
1369 static __inline pml4_entry_t *
1370 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1372 pml5_entry_t *pml5e;
1373 pml4_entry_t *pml4e;
1376 if (pmap_is_la57(pmap)) {
1377 pml5e = pmap_pml5e(pmap, va);
1378 PG_V = pmap_valid_bit(pmap);
1379 if ((*pml5e & PG_V) == 0)
1381 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1383 pml4e = pmap->pm_pmltop;
1385 return (&pml4e[pmap_pml4e_index(va)]);
1388 static __inline pml4_entry_t *
1389 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1391 MPASS(!pmap_is_la57(pmap));
1392 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1395 /* Return a pointer to the PDP slot that corresponds to a VA */
1396 static __inline pdp_entry_t *
1397 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1401 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1402 return (&pdpe[pmap_pdpe_index(va)]);
1405 /* Return a pointer to the PDP slot that corresponds to a VA */
1406 static __inline pdp_entry_t *
1407 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1409 pml4_entry_t *pml4e;
1412 PG_V = pmap_valid_bit(pmap);
1413 pml4e = pmap_pml4e(pmap, va);
1414 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1416 return (pmap_pml4e_to_pdpe(pml4e, va));
1419 /* Return a pointer to the PD slot that corresponds to a VA */
1420 static __inline pd_entry_t *
1421 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1425 KASSERT((*pdpe & PG_PS) == 0,
1426 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1427 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1428 return (&pde[pmap_pde_index(va)]);
1431 /* Return a pointer to the PD slot that corresponds to a VA */
1432 static __inline pd_entry_t *
1433 pmap_pde(pmap_t pmap, vm_offset_t va)
1438 PG_V = pmap_valid_bit(pmap);
1439 pdpe = pmap_pdpe(pmap, va);
1440 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1442 KASSERT((*pdpe & PG_PS) == 0,
1443 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1444 return (pmap_pdpe_to_pde(pdpe, va));
1447 /* Return a pointer to the PT slot that corresponds to a VA */
1448 static __inline pt_entry_t *
1449 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1453 KASSERT((*pde & PG_PS) == 0,
1454 ("%s: pde %#lx is a leaf", __func__, *pde));
1455 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1456 return (&pte[pmap_pte_index(va)]);
1459 /* Return a pointer to the PT slot that corresponds to a VA */
1460 static __inline pt_entry_t *
1461 pmap_pte(pmap_t pmap, vm_offset_t va)
1466 PG_V = pmap_valid_bit(pmap);
1467 pde = pmap_pde(pmap, va);
1468 if (pde == NULL || (*pde & PG_V) == 0)
1470 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1471 return ((pt_entry_t *)pde);
1472 return (pmap_pde_to_pte(pde, va));
1475 static __inline void
1476 pmap_resident_count_adj(pmap_t pmap, int count)
1479 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1480 KASSERT(pmap->pm_stats.resident_count + count >= 0,
1481 ("pmap %p resident count underflow %ld %d", pmap,
1482 pmap->pm_stats.resident_count, count));
1483 pmap->pm_stats.resident_count += count;
1486 static __inline void
1487 pmap_pt_page_count_pinit(pmap_t pmap, int count)
1489 KASSERT(pmap->pm_stats.resident_count + count >= 0,
1490 ("pmap %p resident count underflow %ld %d", pmap,
1491 pmap->pm_stats.resident_count, count));
1492 pmap->pm_stats.resident_count += count;
1495 static __inline void
1496 pmap_pt_page_count_adj(pmap_t pmap, int count)
1498 if (pmap == kernel_pmap)
1499 counter_u64_add(kernel_pt_page_count, count);
1502 pmap_resident_count_adj(pmap, count);
1503 counter_u64_add(user_pt_page_count, count);
1507 PMAP_INLINE pt_entry_t *
1508 vtopte(vm_offset_t va)
1512 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1515 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1516 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1517 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1519 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1520 NPML4EPGSHIFT)) - 1);
1521 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1525 static __inline pd_entry_t *
1526 vtopde(vm_offset_t va)
1530 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1533 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1534 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1535 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1537 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1538 NPML4EPGSHIFT)) - 1);
1539 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1544 allocpages(vm_paddr_t *firstaddr, int n)
1549 bzero((void *)ret, n * PAGE_SIZE);
1550 *firstaddr += n * PAGE_SIZE;
1554 CTASSERT(powerof2(NDMPML4E));
1556 /* number of kernel PDP slots */
1557 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1560 nkpt_init(vm_paddr_t addr)
1567 pt_pages = howmany(addr - kernphys, NBPDR) + 1; /* +1 for 2M hole @0 */
1568 pt_pages += NKPDPE(pt_pages);
1571 * Add some slop beyond the bare minimum required for bootstrapping
1574 * This is quite important when allocating KVA for kernel modules.
1575 * The modules are required to be linked in the negative 2GB of
1576 * the address space. If we run out of KVA in this region then
1577 * pmap_growkernel() will need to allocate page table pages to map
1578 * the entire 512GB of KVA space which is an unnecessary tax on
1581 * Secondly, device memory mapped as part of setting up the low-
1582 * level console(s) is taken from KVA, starting at virtual_avail.
1583 * This is because cninit() is called after pmap_bootstrap() but
1584 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1587 pt_pages += 32; /* 64MB additional slop. */
1593 * Returns the proper write/execute permission for a physical page that is
1594 * part of the initial boot allocations.
1596 * If the page has kernel text, it is marked as read-only. If the page has
1597 * kernel read-only data, it is marked as read-only/not-executable. If the
1598 * page has only read-write data, it is marked as read-write/not-executable.
1599 * If the page is below/above the kernel range, it is marked as read-write.
1601 * This function operates on 2M pages, since we map the kernel space that
1604 static inline pt_entry_t
1605 bootaddr_rwx(vm_paddr_t pa)
1608 * The kernel is loaded at a 2MB-aligned address, and memory below that
1609 * need not be executable. The .bss section is padded to a 2MB
1610 * boundary, so memory following the kernel need not be executable
1611 * either. Preloaded kernel modules have their mapping permissions
1612 * fixed up by the linker.
1614 if (pa < trunc_2mpage(kernphys + btext - KERNSTART) ||
1615 pa >= trunc_2mpage(kernphys + _end - KERNSTART))
1616 return (X86_PG_RW | pg_nx);
1619 * The linker should ensure that the read-only and read-write
1620 * portions don't share the same 2M page, so this shouldn't
1621 * impact read-only data. However, in any case, any page with
1622 * read-write data needs to be read-write.
1624 if (pa >= trunc_2mpage(kernphys + brwsection - KERNSTART))
1625 return (X86_PG_RW | pg_nx);
1628 * Mark any 2M page containing kernel text as read-only. Mark
1629 * other pages with read-only data as read-only and not executable.
1630 * (It is likely a small portion of the read-only data section will
1631 * be marked as read-only, but executable. This should be acceptable
1632 * since the read-only protection will keep the data from changing.)
1633 * Note that fixups to the .text section will still work until we
1636 if (pa < round_2mpage(kernphys + etext - KERNSTART))
1642 create_pagetables(vm_paddr_t *firstaddr)
1647 uint64_t DMPDkernphys;
1651 uint64_t KASANPDphys, KASANPTphys, KASANphys;
1652 vm_offset_t kasankernbase;
1653 int kasankpdpi, kasankpdi, nkasanpte;
1655 int i, j, ndm1g, nkpdpe, nkdmpde;
1657 /* Allocate page table pages for the direct map */
1658 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1659 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1661 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1662 if (ndmpdpphys > NDMPML4E) {
1664 * Each NDMPML4E allows 512 GB, so limit to that,
1665 * and then readjust ndmpdp and ndmpdpphys.
1667 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1668 Maxmem = atop(NDMPML4E * NBPML4);
1669 ndmpdpphys = NDMPML4E;
1670 ndmpdp = NDMPML4E * NPDEPG;
1672 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1674 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1676 * Calculate the number of 1G pages that will fully fit in
1679 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1682 * Allocate 2M pages for the kernel. These will be used in
1683 * place of the one or more 1G pages from ndm1g that maps
1684 * kernel memory into DMAP.
1686 nkdmpde = howmany((vm_offset_t)brwsection - KERNSTART +
1687 kernphys - rounddown2(kernphys, NBPDP), NBPDP);
1688 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1691 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1692 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1694 /* Allocate pages */
1695 KPML4phys = allocpages(firstaddr, 1);
1696 KPDPphys = allocpages(firstaddr, NKPML4E);
1698 KASANPDPphys = allocpages(firstaddr, NKASANPML4E);
1699 KASANPDphys = allocpages(firstaddr, 1);
1703 * Allocate the initial number of kernel page table pages required to
1704 * bootstrap. We defer this until after all memory-size dependent
1705 * allocations are done (e.g. direct map), so that we don't have to
1706 * build in too much slop in our estimate.
1708 * Note that when NKPML4E > 1, we have an empty page underneath
1709 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1710 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1712 nkpt_init(*firstaddr);
1713 nkpdpe = NKPDPE(nkpt);
1715 KPTphys = allocpages(firstaddr, nkpt);
1716 KPDphys = allocpages(firstaddr, nkpdpe);
1719 nkasanpte = howmany(nkpt, KASAN_SHADOW_SCALE);
1720 KASANPTphys = allocpages(firstaddr, nkasanpte);
1721 KASANphys = allocpages(firstaddr, nkasanpte * NPTEPG);
1725 * Connect the zero-filled PT pages to their PD entries. This
1726 * implicitly maps the PT pages at their correct locations within
1729 pd_p = (pd_entry_t *)KPDphys;
1730 for (i = 0; i < nkpt; i++)
1731 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1734 * Map from start of the kernel in physical memory (staging
1735 * area) to the end of loader preallocated memory using 2MB
1736 * pages. This replaces some of the PD entries created above.
1737 * For compatibility, identity map 2M at the start.
1739 pd_p[0] = X86_PG_V | PG_PS | pg_g | X86_PG_M | X86_PG_A |
1741 for (i = 1, pax = kernphys; pax < KERNend; i++, pax += NBPDR) {
1742 /* Preset PG_M and PG_A because demotion expects it. */
1743 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M |
1744 X86_PG_A | bootaddr_rwx(pax);
1748 * Because we map the physical blocks in 2M pages, adjust firstaddr
1749 * to record the physical blocks we've actually mapped into kernel
1750 * virtual address space.
1752 if (*firstaddr < round_2mpage(KERNend))
1753 *firstaddr = round_2mpage(KERNend);
1755 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1756 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1757 for (i = 0; i < nkpdpe; i++)
1758 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1761 kasankernbase = kasan_md_addr_to_shad(KERNBASE);
1762 kasankpdpi = pmap_pdpe_index(kasankernbase);
1763 kasankpdi = pmap_pde_index(kasankernbase);
1765 pdp_p = (pdp_entry_t *)KASANPDPphys;
1766 pdp_p[kasankpdpi] = (KASANPDphys | X86_PG_RW | X86_PG_V | pg_nx);
1768 pd_p = (pd_entry_t *)KASANPDphys;
1769 for (i = 0; i < nkasanpte; i++)
1770 pd_p[i + kasankpdi] = (KASANPTphys + ptoa(i)) | X86_PG_RW |
1773 pt_p = (pt_entry_t *)KASANPTphys;
1774 for (i = 0; i < nkasanpte * NPTEPG; i++)
1775 pt_p[i] = (KASANphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
1776 X86_PG_M | X86_PG_A | pg_nx;
1780 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1781 * the end of physical memory is not aligned to a 1GB page boundary,
1782 * then the residual physical memory is mapped with 2MB pages. Later,
1783 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1784 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1785 * that are partially used.
1787 pd_p = (pd_entry_t *)DMPDphys;
1788 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1789 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1790 /* Preset PG_M and PG_A because demotion expects it. */
1791 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1792 X86_PG_M | X86_PG_A | pg_nx;
1794 pdp_p = (pdp_entry_t *)DMPDPphys;
1795 for (i = 0; i < ndm1g; i++) {
1796 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1797 /* Preset PG_M and PG_A because demotion expects it. */
1798 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1799 X86_PG_M | X86_PG_A | pg_nx;
1801 for (j = 0; i < ndmpdp; i++, j++) {
1802 pdp_p[i] = DMPDphys + ptoa(j);
1803 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1807 * Instead of using a 1G page for the memory containing the kernel,
1808 * use 2M pages with read-only and no-execute permissions. (If using 1G
1809 * pages, this will partially overwrite the PDPEs above.)
1812 pd_p = (pd_entry_t *)DMPDkernphys;
1813 for (i = 0, pax = rounddown2(kernphys, NBPDP);
1814 i < NPDEPG * nkdmpde; i++, pax += NBPDR) {
1815 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M |
1816 X86_PG_A | pg_nx | bootaddr_rwx(pax);
1818 j = rounddown2(kernphys, NBPDP) >> PDPSHIFT;
1819 for (i = 0; i < nkdmpde; i++) {
1820 pdp_p[i + j] = (DMPDkernphys + ptoa(i)) |
1821 X86_PG_RW | X86_PG_V | pg_nx;
1825 /* And recursively map PML4 to itself in order to get PTmap */
1826 p4_p = (pml4_entry_t *)KPML4phys;
1827 p4_p[PML4PML4I] = KPML4phys;
1828 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1831 /* Connect the KASAN shadow map slots up to the PML4. */
1832 for (i = 0; i < NKASANPML4E; i++) {
1833 p4_p[KASANPML4I + i] = KASANPDPphys + ptoa(i);
1834 p4_p[KASANPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1838 /* Connect the Direct Map slots up to the PML4. */
1839 for (i = 0; i < ndmpdpphys; i++) {
1840 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1841 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1844 /* Connect the KVA slots up to the PML4 */
1845 for (i = 0; i < NKPML4E; i++) {
1846 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1847 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1850 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1854 * Bootstrap the system enough to run with virtual memory.
1856 * On amd64 this is called after mapping has already been enabled
1857 * and just syncs the pmap module with what has already been done.
1858 * [We can't call it easily with mapping off since the kernel is not
1859 * mapped with PA == VA, hence we would have to relocate every address
1860 * from the linked base (virtual) address "KERNBASE" to the actual
1861 * (physical) address starting relative to 0]
1864 pmap_bootstrap(vm_paddr_t *firstaddr)
1867 pt_entry_t *pte, *pcpu_pte;
1868 struct region_descriptor r_gdt;
1869 uint64_t cr4, pcpu_phys;
1873 KERNend = *firstaddr;
1874 res = atop(KERNend - (vm_paddr_t)kernphys);
1880 * Create an initial set of page tables to run the kernel in.
1882 create_pagetables(firstaddr);
1884 pcpu_phys = allocpages(firstaddr, MAXCPU);
1887 * Add a physical memory segment (vm_phys_seg) corresponding to the
1888 * preallocated kernel page table pages so that vm_page structures
1889 * representing these pages will be created. The vm_page structures
1890 * are required for promotion of the corresponding kernel virtual
1891 * addresses to superpage mappings.
1893 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1896 * Account for the virtual addresses mapped by create_pagetables().
1898 virtual_avail = (vm_offset_t)KERNSTART + round_2mpage(KERNend -
1899 (vm_paddr_t)kernphys);
1900 virtual_end = VM_MAX_KERNEL_ADDRESS;
1903 * Enable PG_G global pages, then switch to the kernel page
1904 * table from the bootstrap page table. After the switch, it
1905 * is possible to enable SMEP and SMAP since PG_U bits are
1911 load_cr3(KPML4phys);
1912 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1914 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1919 * Initialize the kernel pmap (which is statically allocated).
1920 * Count bootstrap data as being resident in case any of this data is
1921 * later unmapped (using pmap_remove()) and freed.
1923 PMAP_LOCK_INIT(kernel_pmap);
1924 kernel_pmap->pm_pmltop = kernel_pml4;
1925 kernel_pmap->pm_cr3 = KPML4phys;
1926 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1927 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1928 kernel_pmap->pm_stats.resident_count = res;
1929 kernel_pmap->pm_flags = pmap_flags;
1932 * The kernel pmap is always active on all CPUs. Once CPUs are
1933 * enumerated, the mask will be set equal to all_cpus.
1935 CPU_FILL(&kernel_pmap->pm_active);
1938 * Initialize the TLB invalidations generation number lock.
1940 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1943 * Reserve some special page table entries/VA space for temporary
1946 #define SYSMAP(c, p, v, n) \
1947 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1953 * Crashdump maps. The first page is reused as CMAP1 for the
1956 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1957 CADDR1 = crashdumpmap;
1959 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1962 for (i = 0; i < MAXCPU; i++) {
1963 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1964 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1968 * Re-initialize PCPU area for BSP after switching.
1969 * Make hardware use gdt and common_tss from the new PCPU.
1971 STAILQ_INIT(&cpuhead);
1972 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1973 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1974 amd64_bsp_pcpu_init1(&__pcpu[0]);
1975 amd64_bsp_ist_init(&__pcpu[0]);
1976 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1978 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1979 sizeof(struct user_segment_descriptor));
1980 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1981 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1982 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1983 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1984 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1986 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1987 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1988 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1989 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1992 * Initialize the PAT MSR.
1993 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1994 * side-effect, invalidates stale PG_G TLB entries that might
1995 * have been created in our pre-boot environment.
1999 /* Initialize TLB Context Id. */
2000 if (pmap_pcid_enabled) {
2001 for (i = 0; i < MAXCPU; i++) {
2002 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
2003 kernel_pmap->pm_pcids[i].pm_gen = 1;
2007 * PMAP_PCID_KERN + 1 is used for initialization of
2008 * proc0 pmap. The pmap' pcid state might be used by
2009 * EFIRT entry before first context switch, so it
2010 * needs to be valid.
2012 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
2013 PCPU_SET(pcid_gen, 1);
2016 * pcpu area for APs is zeroed during AP startup.
2017 * pc_pcid_next and pc_pcid_gen are initialized by AP
2018 * during pcpu setup.
2020 load_cr4(rcr4() | CR4_PCIDE);
2025 * Setup the PAT MSR.
2034 /* Bail if this CPU doesn't implement PAT. */
2035 if ((cpu_feature & CPUID_PAT) == 0)
2038 /* Set default PAT index table. */
2039 for (i = 0; i < PAT_INDEX_SIZE; i++)
2041 pat_index[PAT_WRITE_BACK] = 0;
2042 pat_index[PAT_WRITE_THROUGH] = 1;
2043 pat_index[PAT_UNCACHEABLE] = 3;
2044 pat_index[PAT_WRITE_COMBINING] = 6;
2045 pat_index[PAT_WRITE_PROTECTED] = 5;
2046 pat_index[PAT_UNCACHED] = 2;
2049 * Initialize default PAT entries.
2050 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
2051 * Program 5 and 6 as WP and WC.
2053 * Leave 4 and 7 as WB and UC. Note that a recursive page table
2054 * mapping for a 2M page uses a PAT value with the bit 3 set due
2055 * to its overload with PG_PS.
2057 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
2058 PAT_VALUE(1, PAT_WRITE_THROUGH) |
2059 PAT_VALUE(2, PAT_UNCACHED) |
2060 PAT_VALUE(3, PAT_UNCACHEABLE) |
2061 PAT_VALUE(4, PAT_WRITE_BACK) |
2062 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
2063 PAT_VALUE(6, PAT_WRITE_COMBINING) |
2064 PAT_VALUE(7, PAT_UNCACHEABLE);
2068 load_cr4(cr4 & ~CR4_PGE);
2070 /* Disable caches (CD = 1, NW = 0). */
2072 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
2074 /* Flushes caches and TLBs. */
2078 /* Update PAT and index table. */
2079 wrmsr(MSR_PAT, pat_msr);
2081 /* Flush caches and TLBs again. */
2085 /* Restore caches and PGE. */
2091 pmap_page_alloc_below_4g(bool zeroed)
2093 return (vm_page_alloc_noobj_contig((zeroed ? VM_ALLOC_ZERO : 0),
2094 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT));
2097 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
2098 la57_trampoline_gdt[], la57_trampoline_end[];
2101 pmap_bootstrap_la57(void *arg __unused)
2104 pml5_entry_t *v_pml5;
2105 pml4_entry_t *v_pml4;
2109 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2110 void (*la57_tramp)(uint64_t pml5);
2111 struct region_descriptor r_gdt;
2113 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2115 TUNABLE_INT_FETCH("vm.pmap.la57", &la57);
2119 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2120 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2122 m_code = pmap_page_alloc_below_4g(true);
2123 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2124 m_pml5 = pmap_page_alloc_below_4g(true);
2125 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2126 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2127 m_pml4 = pmap_page_alloc_below_4g(true);
2128 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2129 m_pdp = pmap_page_alloc_below_4g(true);
2130 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2131 m_pd = pmap_page_alloc_below_4g(true);
2132 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2133 m_pt = pmap_page_alloc_below_4g(true);
2134 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2137 * Map m_code 1:1, it appears below 4G in KVA due to physical
2138 * address being below 4G. Since kernel KVA is in upper half,
2139 * the pml4e should be zero and free for temporary use.
2141 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2142 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2144 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2145 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2147 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2148 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2150 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2151 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2155 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2156 * entering all existing kernel mappings into level 5 table.
2158 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2159 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2162 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2164 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2165 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2167 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2168 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2172 * Copy and call the 48->57 trampoline, hope we return there, alive.
2174 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2175 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2176 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2177 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2178 invlpg((vm_offset_t)la57_tramp);
2179 la57_tramp(KPML5phys);
2182 * gdt was necessary reset, switch back to our gdt.
2185 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2189 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2190 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2191 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2194 * Now unmap the trampoline, and free the pages.
2195 * Clear pml5 entry used for 1:1 trampoline mapping.
2197 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2198 invlpg((vm_offset_t)v_code);
2199 vm_page_free(m_code);
2200 vm_page_free(m_pdp);
2205 * Recursively map PML5 to itself in order to get PTmap and
2208 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2210 kernel_pmap->pm_cr3 = KPML5phys;
2211 kernel_pmap->pm_pmltop = v_pml5;
2212 pmap_pt_page_count_adj(kernel_pmap, 1);
2214 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2217 * Initialize a vm_page's machine-dependent fields.
2220 pmap_page_init(vm_page_t m)
2223 TAILQ_INIT(&m->md.pv_list);
2224 m->md.pat_mode = PAT_WRITE_BACK;
2227 static int pmap_allow_2m_x_ept;
2228 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2229 &pmap_allow_2m_x_ept, 0,
2230 "Allow executable superpage mappings in EPT");
2233 pmap_allow_2m_x_ept_recalculate(void)
2236 * SKL002, SKL012S. Since the EPT format is only used by
2237 * Intel CPUs, the vendor check is merely a formality.
2239 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2240 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2241 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2242 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2243 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2244 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2245 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2246 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2247 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2248 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2249 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2250 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2251 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2252 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2253 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2254 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2255 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2256 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2257 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2258 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2259 CPUID_TO_MODEL(cpu_id) == 0x85))))
2260 pmap_allow_2m_x_ept = 1;
2261 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2265 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2268 return (pmap->pm_type != PT_EPT || !executable ||
2269 !pmap_allow_2m_x_ept);
2274 pmap_init_pv_table(void)
2276 struct pmap_large_md_page *pvd;
2278 long start, end, highest, pv_npg;
2279 int domain, i, j, pages;
2282 * We strongly depend on the size being a power of two, so the assert
2283 * is overzealous. However, should the struct be resized to a
2284 * different power of two, the code below needs to be revisited.
2286 CTASSERT((sizeof(*pvd) == 64));
2289 * Calculate the size of the array.
2291 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2292 pv_npg = howmany(pmap_last_pa, NBPDR);
2293 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2295 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2296 if (pv_table == NULL)
2297 panic("%s: kva_alloc failed\n", __func__);
2300 * Iterate physical segments to allocate space for respective pages.
2304 for (i = 0; i < vm_phys_nsegs; i++) {
2305 end = vm_phys_segs[i].end / NBPDR;
2306 domain = vm_phys_segs[i].domain;
2311 start = highest + 1;
2312 pvd = &pv_table[start];
2314 pages = end - start + 1;
2315 s = round_page(pages * sizeof(*pvd));
2316 highest = start + (s / sizeof(*pvd)) - 1;
2318 for (j = 0; j < s; j += PAGE_SIZE) {
2319 vm_page_t m = vm_page_alloc_noobj_domain(domain, 0);
2321 panic("failed to allocate PV table page");
2322 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2325 for (j = 0; j < s / sizeof(*pvd); j++) {
2326 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2327 TAILQ_INIT(&pvd->pv_page.pv_list);
2328 pvd->pv_page.pv_gen = 0;
2329 pvd->pv_page.pat_mode = 0;
2330 pvd->pv_invl_gen = 0;
2334 pvd = &pv_dummy_large;
2335 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2336 TAILQ_INIT(&pvd->pv_page.pv_list);
2337 pvd->pv_page.pv_gen = 0;
2338 pvd->pv_page.pat_mode = 0;
2339 pvd->pv_invl_gen = 0;
2343 pmap_init_pv_table(void)
2349 * Initialize the pool of pv list locks.
2351 for (i = 0; i < NPV_LIST_LOCKS; i++)
2352 rw_init(&pv_list_locks[i], "pmap pv list");
2355 * Calculate the size of the pv head table for superpages.
2357 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2360 * Allocate memory for the pv head table for superpages.
2362 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2364 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2365 for (i = 0; i < pv_npg; i++)
2366 TAILQ_INIT(&pv_table[i].pv_list);
2367 TAILQ_INIT(&pv_dummy.pv_list);
2372 * Initialize the pmap module.
2373 * Called by vm_init, to initialize any structures that the pmap
2374 * system needs to map virtual memory.
2379 struct pmap_preinit_mapping *ppim;
2381 int error, i, ret, skz63;
2383 /* L1TF, reserve page @0 unconditionally */
2384 vm_page_blacklist_add(0, bootverbose);
2386 /* Detect bare-metal Skylake Server and Skylake-X. */
2387 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2388 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2390 * Skylake-X errata SKZ63. Processor May Hang When
2391 * Executing Code In an HLE Transaction Region between
2392 * 40000000H and 403FFFFFH.
2394 * Mark the pages in the range as preallocated. It
2395 * seems to be impossible to distinguish between
2396 * Skylake Server and Skylake X.
2399 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2402 printf("SKZ63: skipping 4M RAM starting "
2403 "at physical 1G\n");
2404 for (i = 0; i < atop(0x400000); i++) {
2405 ret = vm_page_blacklist_add(0x40000000 +
2407 if (!ret && bootverbose)
2408 printf("page at %#lx already used\n",
2409 0x40000000 + ptoa(i));
2415 pmap_allow_2m_x_ept_recalculate();
2418 * Initialize the vm page array entries for the kernel pmap's
2421 PMAP_LOCK(kernel_pmap);
2422 for (i = 0; i < nkpt; i++) {
2423 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2424 KASSERT(mpte >= vm_page_array &&
2425 mpte < &vm_page_array[vm_page_array_size],
2426 ("pmap_init: page table page is out of range"));
2427 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2428 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2429 mpte->ref_count = 1;
2432 * Collect the page table pages that were replaced by a 2MB
2433 * page in create_pagetables(). They are zero filled.
2436 kernphys + ((vm_paddr_t)(i - 1) << PDRSHIFT) < KERNend) &&
2437 pmap_insert_pt_page(kernel_pmap, mpte, false))
2438 panic("pmap_init: pmap_insert_pt_page failed");
2440 PMAP_UNLOCK(kernel_pmap);
2444 * If the kernel is running on a virtual machine, then it must assume
2445 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2446 * be prepared for the hypervisor changing the vendor and family that
2447 * are reported by CPUID. Consequently, the workaround for AMD Family
2448 * 10h Erratum 383 is enabled if the processor's feature set does not
2449 * include at least one feature that is only supported by older Intel
2450 * or newer AMD processors.
2452 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2453 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2454 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2456 workaround_erratum383 = 1;
2459 * Are large page mappings enabled?
2461 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2462 if (pg_ps_enabled) {
2463 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2464 ("pmap_init: can't assign to pagesizes[1]"));
2465 pagesizes[1] = NBPDR;
2466 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2467 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2468 ("pmap_init: can't assign to pagesizes[2]"));
2469 pagesizes[2] = NBPDP;
2474 * Initialize pv chunk lists.
2476 for (i = 0; i < PMAP_MEMDOM; i++) {
2477 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2478 TAILQ_INIT(&pv_chunks[i].pvc_list);
2480 pmap_init_pv_table();
2482 pmap_initialized = 1;
2483 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2484 ppim = pmap_preinit_mapping + i;
2487 /* Make the direct map consistent */
2488 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2489 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2490 ppim->sz, ppim->mode);
2494 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2495 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2498 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2499 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2500 (vmem_addr_t *)&qframe);
2502 panic("qframe allocation failed");
2505 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2506 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2507 lm_ents = LMEPML4I - LMSPML4I + 1;
2509 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2510 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2512 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2513 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2514 if (large_vmem == NULL) {
2515 printf("pmap: cannot create large map\n");
2518 for (i = 0; i < lm_ents; i++) {
2519 m = pmap_large_map_getptp_unlocked();
2521 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2522 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2528 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2529 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2530 "Maximum number of PML4 entries for use by large map (tunable). "
2531 "Each entry corresponds to 512GB of address space.");
2533 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2534 "2MB page mapping counters");
2536 static COUNTER_U64_DEFINE_EARLY(pmap_pde_demotions);
2537 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, demotions,
2538 CTLFLAG_RD, &pmap_pde_demotions, "2MB page demotions");
2540 static COUNTER_U64_DEFINE_EARLY(pmap_pde_mappings);
2541 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2542 &pmap_pde_mappings, "2MB page mappings");
2544 static COUNTER_U64_DEFINE_EARLY(pmap_pde_p_failures);
2545 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2546 &pmap_pde_p_failures, "2MB page promotion failures");
2548 static COUNTER_U64_DEFINE_EARLY(pmap_pde_promotions);
2549 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2550 &pmap_pde_promotions, "2MB page promotions");
2552 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2553 "1GB page mapping counters");
2555 static COUNTER_U64_DEFINE_EARLY(pmap_pdpe_demotions);
2556 SYSCTL_COUNTER_U64(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2557 &pmap_pdpe_demotions, "1GB page demotions");
2559 /***************************************************
2560 * Low level helper routines.....
2561 ***************************************************/
2564 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2566 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2568 switch (pmap->pm_type) {
2571 /* Verify that both PAT bits are not set at the same time */
2572 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2573 ("Invalid PAT bits in entry %#lx", entry));
2575 /* Swap the PAT bits if one of them is set */
2576 if ((entry & x86_pat_bits) != 0)
2577 entry ^= x86_pat_bits;
2581 * Nothing to do - the memory attributes are represented
2582 * the same way for regular pages and superpages.
2586 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2593 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2596 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2597 pat_index[(int)mode] >= 0);
2601 * Determine the appropriate bits to set in a PTE or PDE for a specified
2605 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2607 int cache_bits, pat_flag, pat_idx;
2609 if (!pmap_is_valid_memattr(pmap, mode))
2610 panic("Unknown caching mode %d\n", mode);
2612 switch (pmap->pm_type) {
2615 /* The PAT bit is different for PTE's and PDE's. */
2616 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2618 /* Map the caching mode to a PAT index. */
2619 pat_idx = pat_index[mode];
2621 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2624 cache_bits |= pat_flag;
2626 cache_bits |= PG_NC_PCD;
2628 cache_bits |= PG_NC_PWT;
2632 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2636 panic("unsupported pmap type %d", pmap->pm_type);
2639 return (cache_bits);
2643 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2647 switch (pmap->pm_type) {
2650 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2653 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2656 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2663 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2665 int pat_flag, pat_idx;
2668 switch (pmap->pm_type) {
2671 /* The PAT bit is different for PTE's and PDE's. */
2672 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2674 if ((pte & pat_flag) != 0)
2676 if ((pte & PG_NC_PCD) != 0)
2678 if ((pte & PG_NC_PWT) != 0)
2682 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2683 panic("EPT PTE %#lx has no PAT memory type", pte);
2684 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2688 /* See pmap_init_pat(). */
2698 pmap_ps_enabled(pmap_t pmap)
2701 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2705 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2708 switch (pmap->pm_type) {
2715 * This is a little bogus since the generation number is
2716 * supposed to be bumped up when a region of the address
2717 * space is invalidated in the page tables.
2719 * In this case the old PDE entry is valid but yet we want
2720 * to make sure that any mappings using the old entry are
2721 * invalidated in the TLB.
2723 * The reason this works as expected is because we rendezvous
2724 * "all" host cpus and force any vcpu context to exit as a
2727 atomic_add_long(&pmap->pm_eptgen, 1);
2730 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2732 pde_store(pde, newpde);
2736 * After changing the page size for the specified virtual address in the page
2737 * table, flush the corresponding entries from the processor's TLB. Only the
2738 * calling processor's TLB is affected.
2740 * The calling thread must be pinned to a processor.
2743 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2747 if (pmap_type_guest(pmap))
2750 KASSERT(pmap->pm_type == PT_X86,
2751 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2753 PG_G = pmap_global_bit(pmap);
2755 if ((newpde & PG_PS) == 0)
2756 /* Demotion: flush a specific 2MB page mapping. */
2758 else if ((newpde & PG_G) == 0)
2760 * Promotion: flush every 4KB page mapping from the TLB
2761 * because there are too many to flush individually.
2766 * Promotion: flush every 4KB page mapping from the TLB,
2767 * including any global (PG_G) mappings.
2774 * The amd64 pmap uses different approaches to TLB invalidation
2775 * depending on the kernel configuration, available hardware features,
2776 * and known hardware errata. The kernel configuration option that
2777 * has the greatest operational impact on TLB invalidation is PTI,
2778 * which is enabled automatically on affected Intel CPUs. The most
2779 * impactful hardware features are first PCID, and then INVPCID
2780 * instruction presence. PCID usage is quite different for PTI
2783 * * Kernel Page Table Isolation (PTI or KPTI) is used to mitigate
2784 * the Meltdown bug in some Intel CPUs. Under PTI, each user address
2785 * space is served by two page tables, user and kernel. The user
2786 * page table only maps user space and a kernel trampoline. The
2787 * kernel trampoline includes the entirety of the kernel text but
2788 * only the kernel data that is needed to switch from user to kernel
2789 * mode. The kernel page table maps the user and kernel address
2790 * spaces in their entirety. It is identical to the per-process
2791 * page table used in non-PTI mode.
2793 * User page tables are only used when the CPU is in user mode.
2794 * Consequently, some TLB invalidations can be postponed until the
2795 * switch from kernel to user mode. In contrast, the user
2796 * space part of the kernel page table is used for copyout(9), so
2797 * TLB invalidations on this page table cannot be similarly postponed.
2799 * The existence of a user mode page table for the given pmap is
2800 * indicated by a pm_ucr3 value that differs from PMAP_NO_CR3, in
2801 * which case pm_ucr3 contains the %cr3 register value for the user
2802 * mode page table's root.
2804 * * The pm_active bitmask indicates which CPUs currently have the
2805 * pmap active. A CPU's bit is set on context switch to the pmap, and
2806 * cleared on switching off this CPU. For the kernel page table,
2807 * the pm_active field is immutable and contains all CPUs. The
2808 * kernel page table is always logically active on every processor,
2809 * but not necessarily in use by the hardware, e.g., in PTI mode.
2811 * When requesting invalidation of virtual addresses with
2812 * pmap_invalidate_XXX() functions, the pmap sends shootdown IPIs to
2813 * all CPUs recorded as active in pm_active. Updates to and reads
2814 * from pm_active are not synchronized, and so they may race with
2815 * each other. Shootdown handlers are prepared to handle the race.
2817 * * PCID is an optional feature of the long mode x86 MMU where TLB
2818 * entries are tagged with the 'Process ID' of the address space
2819 * they belong to. This feature provides a limited namespace for
2820 * process identifiers, 12 bits, supporting 4095 simultaneous IDs
2823 * Allocation of a PCID to a pmap is done by an algorithm described
2824 * in section 15.12, "Other TLB Consistency Algorithms", of
2825 * Vahalia's book "Unix Internals". A PCID cannot be allocated for
2826 * the whole lifetime of a pmap in pmap_pinit() due to the limited
2827 * namespace. Instead, a per-CPU, per-pmap PCID is assigned when
2828 * the CPU is about to start caching TLB entries from a pmap,
2829 * i.e., on the context switch that activates the pmap on the CPU.
2831 * The PCID allocator maintains a per-CPU, per-pmap generation
2832 * count, pm_gen, which is incremented each time a new PCID is
2833 * allocated. On TLB invalidation, the generation counters for the
2834 * pmap are zeroed, which signals the context switch code that the
2835 * previously allocated PCID is no longer valid. Effectively,
2836 * zeroing any of these counters triggers a TLB shootdown for the
2837 * given CPU/address space, due to the allocation of a new PCID.
2839 * Zeroing can be performed remotely. Consequently, if a pmap is
2840 * inactive on a CPU, then a TLB shootdown for that pmap and CPU can
2841 * be initiated by an ordinary memory access to reset the target
2842 * CPU's generation count within the pmap. The CPU initiating the
2843 * TLB shootdown does not need to send an IPI to the target CPU.
2845 * * PTI + PCID. The available PCIDs are divided into two sets: PCIDs
2846 * for complete (kernel) page tables, and PCIDs for user mode page
2847 * tables. A user PCID value is obtained from the kernel PCID value
2848 * by setting the highest bit, 11, to 1 (0x800 == PMAP_PCID_USER_PT).
2850 * User space page tables are activated on return to user mode, by
2851 * loading pm_ucr3 into %cr3. If the PCPU(ucr3_load_mask) requests
2852 * clearing bit 63 of the loaded ucr3, this effectively causes
2853 * complete invalidation of the user mode TLB entries for the
2854 * current pmap. In which case, local invalidations of individual
2855 * pages in the user page table are skipped.
2857 * * Local invalidation, all modes. If the requested invalidation is
2858 * for a specific address or the total invalidation of a currently
2859 * active pmap, then the TLB is flushed using INVLPG for a kernel
2860 * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a
2861 * user space page table(s).
2863 * If the INVPCID instruction is available, it is used to flush entries
2864 * from the kernel page table.
2866 * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its
2867 * address space, all other 4095 PCIDs are used for user mode spaces
2868 * as described above. A context switch allocates a new PCID if
2869 * the recorded PCID is zero or the recorded generation does not match
2870 * the CPU's generation, effectively flushing the TLB for this address space.
2871 * Total remote invalidation is performed by zeroing pm_gen for all CPUs.
2872 * local user page: INVLPG
2873 * local kernel page: INVLPG
2874 * local user total: INVPCID(CTX)
2875 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2876 * remote user page, inactive pmap: zero pm_gen
2877 * remote user page, active pmap: zero pm_gen + IPI:INVLPG
2878 * (Both actions are required to handle the aforementioned pm_active races.)
2879 * remote kernel page: IPI:INVLPG
2880 * remote user total, inactive pmap: zero pm_gen
2881 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) or
2883 * (See note above about pm_active races.)
2884 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2886 * PTI enabled, PCID present.
2887 * local user page: INVLPG for kpt, INVPCID(ADDR) or (INVLPG for ucr3)
2889 * local kernel page: INVLPG
2890 * local user total: INVPCID(CTX) or reload %cr3 for kpt, clear PCID_SAVE
2891 * on loading UCR3 into %cr3 for upt
2892 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2893 * remote user page, inactive pmap: zero pm_gen
2894 * remote user page, active pmap: zero pm_gen + IPI:(INVLPG for kpt,
2895 * INVPCID(ADDR) for upt)
2896 * remote kernel page: IPI:INVLPG
2897 * remote user total, inactive pmap: zero pm_gen
2898 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) for kpt,
2899 * clear PCID_SAVE on loading UCR3 into $cr3 for upt)
2900 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2903 * local user page: INVLPG
2904 * local kernel page: INVLPG
2905 * local user total: reload %cr3
2906 * local kernel total: invltlb_glob()
2907 * remote user page, inactive pmap: -
2908 * remote user page, active pmap: IPI:INVLPG
2909 * remote kernel page: IPI:INVLPG
2910 * remote user total, inactive pmap: -
2911 * remote user total, active pmap: IPI:(reload %cr3)
2912 * remote kernel total: IPI:invltlb_glob()
2913 * Since on return to user mode, the reload of %cr3 with ucr3 causes
2914 * TLB invalidation, no specific action is required for user page table.
2916 * EPT. EPT pmaps do not map KVA, all mappings are userspace.
2922 * Interrupt the cpus that are executing in the guest context.
2923 * This will force the vcpu to exit and the cached EPT mappings
2924 * will be invalidated by the host before the next vmresume.
2926 static __inline void
2927 pmap_invalidate_ept(pmap_t pmap)
2933 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2934 ("pmap_invalidate_ept: absurd pm_active"));
2937 * The TLB mappings associated with a vcpu context are not
2938 * flushed each time a different vcpu is chosen to execute.
2940 * This is in contrast with a process's vtop mappings that
2941 * are flushed from the TLB on each context switch.
2943 * Therefore we need to do more than just a TLB shootdown on
2944 * the active cpus in 'pmap->pm_active'. To do this we keep
2945 * track of the number of invalidations performed on this pmap.
2947 * Each vcpu keeps a cache of this counter and compares it
2948 * just before a vmresume. If the counter is out-of-date an
2949 * invept will be done to flush stale mappings from the TLB.
2951 * To ensure that all vCPU threads have observed the new counter
2952 * value before returning, we use SMR. Ordering is important here:
2953 * the VMM enters an SMR read section before loading the counter
2954 * and after updating the pm_active bit set. Thus, pm_active is
2955 * a superset of active readers, and any reader that has observed
2956 * the goal has observed the new counter value.
2958 atomic_add_long(&pmap->pm_eptgen, 1);
2960 goal = smr_advance(pmap->pm_eptsmr);
2963 * Force the vcpu to exit and trap back into the hypervisor.
2965 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2966 ipi_selected(pmap->pm_active, ipinum);
2970 * Ensure that all active vCPUs will observe the new generation counter
2971 * value before executing any more guest instructions.
2973 smr_wait(pmap->pm_eptsmr, goal);
2977 pmap_invalidate_preipi_pcid(pmap_t pmap)
2983 cpuid = PCPU_GET(cpuid);
2984 if (pmap != PCPU_GET(curpmap))
2985 cpuid = 0xffffffff; /* An impossible value */
2989 pmap->pm_pcids[i].pm_gen = 0;
2993 * The fence is between stores to pm_gen and the read of the
2994 * pm_active mask. We need to ensure that it is impossible
2995 * for us to miss the bit update in pm_active and
2996 * simultaneously observe a non-zero pm_gen in
2997 * pmap_activate_sw(), otherwise TLB update is missed.
2998 * Without the fence, IA32 allows such an outcome. Note that
2999 * pm_active is updated by a locked operation, which provides
3000 * the reciprocal fence.
3002 atomic_thread_fence_seq_cst();
3006 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
3011 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t))
3013 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
3014 pmap_invalidate_preipi_nopcid);
3018 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
3019 const bool invpcid_works1)
3021 struct invpcid_descr d;
3022 uint64_t kcr3, ucr3;
3027 * Because pm_pcid is recalculated on a context switch, we
3028 * must ensure there is no preemption, not just pinning.
3029 * Otherwise, we might use a stale value below.
3031 CRITICAL_ASSERT(curthread);
3034 * No need to do anything with user page tables invalidation
3035 * if there is no user page table, or invalidation is deferred
3036 * until the return to userspace. ucr3_load_mask is stable
3037 * because we have preemption disabled.
3039 if (pmap->pm_ucr3 == PMAP_NO_CR3 ||
3040 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3043 cpuid = PCPU_GET(cpuid);
3045 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3046 if (invpcid_works1) {
3047 d.pcid = pcid | PMAP_PCID_USER_PT;
3050 invpcid(&d, INVPCID_ADDR);
3052 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3053 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3054 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3059 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
3061 pmap_invalidate_page_pcid_cb(pmap, va, true);
3065 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
3067 pmap_invalidate_page_pcid_cb(pmap, va, false);
3071 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
3075 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t))
3077 if (pmap_pcid_enabled)
3078 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
3079 pmap_invalidate_page_pcid_noinvpcid_cb);
3080 return (pmap_invalidate_page_nopcid_cb);
3084 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
3085 vm_offset_t addr2 __unused)
3087 if (pmap == kernel_pmap) {
3089 } else if (pmap == PCPU_GET(curpmap)) {
3091 pmap_invalidate_page_cb(pmap, va);
3096 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3098 if (pmap_type_guest(pmap)) {
3099 pmap_invalidate_ept(pmap);
3103 KASSERT(pmap->pm_type == PT_X86,
3104 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
3106 pmap_invalidate_preipi(pmap);
3107 smp_masked_invlpg(va, pmap, pmap_invalidate_page_curcpu_cb);
3110 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
3111 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
3114 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3115 const bool invpcid_works1)
3117 struct invpcid_descr d;
3118 uint64_t kcr3, ucr3;
3122 CRITICAL_ASSERT(curthread);
3124 if (pmap != PCPU_GET(curpmap) ||
3125 pmap->pm_ucr3 == PMAP_NO_CR3 ||
3126 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3129 cpuid = PCPU_GET(cpuid);
3131 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3132 if (invpcid_works1) {
3133 d.pcid = pcid | PMAP_PCID_USER_PT;
3135 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
3136 invpcid(&d, INVPCID_ADDR);
3138 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3139 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3140 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3145 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
3148 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
3152 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
3155 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
3159 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
3160 vm_offset_t eva __unused)
3164 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
3167 if (pmap_pcid_enabled)
3168 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
3169 pmap_invalidate_range_pcid_noinvpcid_cb);
3170 return (pmap_invalidate_range_nopcid_cb);
3174 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3178 if (pmap == kernel_pmap) {
3179 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3181 } else if (pmap == PCPU_GET(curpmap)) {
3182 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3184 pmap_invalidate_range_cb(pmap, sva, eva);
3189 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3191 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
3192 pmap_invalidate_all(pmap);
3196 if (pmap_type_guest(pmap)) {
3197 pmap_invalidate_ept(pmap);
3201 KASSERT(pmap->pm_type == PT_X86,
3202 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3204 pmap_invalidate_preipi(pmap);
3205 smp_masked_invlpg_range(sva, eva, pmap,
3206 pmap_invalidate_range_curcpu_cb);
3210 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
3212 struct invpcid_descr d;
3217 if (pmap == kernel_pmap) {
3218 if (invpcid_works1) {
3219 bzero(&d, sizeof(d));
3220 invpcid(&d, INVPCID_CTXGLOB);
3224 } else if (pmap == PCPU_GET(curpmap)) {
3225 CRITICAL_ASSERT(curthread);
3226 cpuid = PCPU_GET(cpuid);
3228 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3229 if (invpcid_works1) {
3233 invpcid(&d, INVPCID_CTX);
3235 kcr3 = pmap->pm_cr3 | pcid;
3238 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3239 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3244 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
3246 pmap_invalidate_all_pcid_cb(pmap, true);
3250 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
3252 pmap_invalidate_all_pcid_cb(pmap, false);
3256 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
3258 if (pmap == kernel_pmap)
3260 else if (pmap == PCPU_GET(curpmap))
3264 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t))
3266 if (pmap_pcid_enabled)
3267 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
3268 pmap_invalidate_all_pcid_noinvpcid_cb);
3269 return (pmap_invalidate_all_nopcid_cb);
3273 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3274 vm_offset_t addr2 __unused)
3276 pmap_invalidate_all_cb(pmap);
3280 pmap_invalidate_all(pmap_t pmap)
3282 if (pmap_type_guest(pmap)) {
3283 pmap_invalidate_ept(pmap);
3287 KASSERT(pmap->pm_type == PT_X86,
3288 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3290 pmap_invalidate_preipi(pmap);
3291 smp_masked_invltlb(pmap, pmap_invalidate_all_curcpu_cb);
3295 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3296 vm_offset_t addr2 __unused)
3302 pmap_invalidate_cache(void)
3305 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3309 cpuset_t invalidate; /* processors that invalidate their TLB */
3314 u_int store; /* processor that updates the PDE */
3318 pmap_update_pde_action(void *arg)
3320 struct pde_action *act = arg;
3322 if (act->store == PCPU_GET(cpuid))
3323 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3327 pmap_update_pde_teardown(void *arg)
3329 struct pde_action *act = arg;
3331 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3332 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3336 * Change the page size for the specified virtual address in a way that
3337 * prevents any possibility of the TLB ever having two entries that map the
3338 * same virtual address using different page sizes. This is the recommended
3339 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3340 * machine check exception for a TLB state that is improperly diagnosed as a
3344 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3346 struct pde_action act;
3347 cpuset_t active, other_cpus;
3351 cpuid = PCPU_GET(cpuid);
3352 other_cpus = all_cpus;
3353 CPU_CLR(cpuid, &other_cpus);
3354 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3357 active = pmap->pm_active;
3359 if (CPU_OVERLAP(&active, &other_cpus)) {
3361 act.invalidate = active;
3365 act.newpde = newpde;
3366 CPU_SET(cpuid, &active);
3367 smp_rendezvous_cpus(active,
3368 smp_no_rendezvous_barrier, pmap_update_pde_action,
3369 pmap_update_pde_teardown, &act);
3371 pmap_update_pde_store(pmap, pde, newpde);
3372 if (CPU_ISSET(cpuid, &active))
3373 pmap_update_pde_invalidate(pmap, va, newpde);
3379 * Normal, non-SMP, invalidation functions.
3382 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3384 struct invpcid_descr d;
3385 uint64_t kcr3, ucr3;
3388 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3392 KASSERT(pmap->pm_type == PT_X86,
3393 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3395 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3397 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3398 pmap->pm_ucr3 != PMAP_NO_CR3) {
3400 pcid = pmap->pm_pcids[0].pm_pcid;
3401 if (invpcid_works) {
3402 d.pcid = pcid | PMAP_PCID_USER_PT;
3405 invpcid(&d, INVPCID_ADDR);
3407 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3408 ucr3 = pmap->pm_ucr3 | pcid |
3409 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3410 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3414 } else if (pmap_pcid_enabled)
3415 pmap->pm_pcids[0].pm_gen = 0;
3419 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3421 struct invpcid_descr d;
3423 uint64_t kcr3, ucr3;
3425 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3429 KASSERT(pmap->pm_type == PT_X86,
3430 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3432 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3433 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3435 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3436 pmap->pm_ucr3 != PMAP_NO_CR3) {
3438 if (invpcid_works) {
3439 d.pcid = pmap->pm_pcids[0].pm_pcid |
3443 for (; d.addr < eva; d.addr += PAGE_SIZE)
3444 invpcid(&d, INVPCID_ADDR);
3446 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3447 pm_pcid | CR3_PCID_SAVE;
3448 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3449 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3450 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3454 } else if (pmap_pcid_enabled) {
3455 pmap->pm_pcids[0].pm_gen = 0;
3460 pmap_invalidate_all(pmap_t pmap)
3462 struct invpcid_descr d;
3463 uint64_t kcr3, ucr3;
3465 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3469 KASSERT(pmap->pm_type == PT_X86,
3470 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3472 if (pmap == kernel_pmap) {
3473 if (pmap_pcid_enabled && invpcid_works) {
3474 bzero(&d, sizeof(d));
3475 invpcid(&d, INVPCID_CTXGLOB);
3479 } else if (pmap == PCPU_GET(curpmap)) {
3480 if (pmap_pcid_enabled) {
3482 if (invpcid_works) {
3483 d.pcid = pmap->pm_pcids[0].pm_pcid;
3486 invpcid(&d, INVPCID_CTX);
3487 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3488 d.pcid |= PMAP_PCID_USER_PT;
3489 invpcid(&d, INVPCID_CTX);
3492 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3493 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3494 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3495 0].pm_pcid | PMAP_PCID_USER_PT;
3496 pmap_pti_pcid_invalidate(ucr3, kcr3);
3504 } else if (pmap_pcid_enabled) {
3505 pmap->pm_pcids[0].pm_gen = 0;
3510 pmap_invalidate_cache(void)
3517 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3520 pmap_update_pde_store(pmap, pde, newpde);
3521 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3522 pmap_update_pde_invalidate(pmap, va, newpde);
3524 pmap->pm_pcids[0].pm_gen = 0;
3529 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3533 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3534 * by a promotion that did not invalidate the 512 4KB page mappings
3535 * that might exist in the TLB. Consequently, at this point, the TLB
3536 * may hold both 4KB and 2MB page mappings for the address range [va,
3537 * va + NBPDR). Therefore, the entire range must be invalidated here.
3538 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3539 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3540 * single INVLPG suffices to invalidate the 2MB page mapping from the
3543 if ((pde & PG_PROMOTED) != 0)
3544 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3546 pmap_invalidate_page(pmap, va);
3549 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3550 (vm_offset_t sva, vm_offset_t eva))
3553 if ((cpu_feature & CPUID_SS) != 0)
3554 return (pmap_invalidate_cache_range_selfsnoop);
3555 if ((cpu_feature & CPUID_CLFSH) != 0)
3556 return (pmap_force_invalidate_cache_range);
3557 return (pmap_invalidate_cache_range_all);
3560 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3563 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3566 KASSERT((sva & PAGE_MASK) == 0,
3567 ("pmap_invalidate_cache_range: sva not page-aligned"));
3568 KASSERT((eva & PAGE_MASK) == 0,
3569 ("pmap_invalidate_cache_range: eva not page-aligned"));
3573 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3576 pmap_invalidate_cache_range_check_align(sva, eva);
3580 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3583 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3586 * XXX: Some CPUs fault, hang, or trash the local APIC
3587 * registers if we use CLFLUSH on the local APIC range. The
3588 * local APIC is always uncached, so we don't need to flush
3589 * for that range anyway.
3591 if (pmap_kextract(sva) == lapic_paddr)
3594 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3596 * Do per-cache line flush. Use a locked
3597 * instruction to insure that previous stores are
3598 * included in the write-back. The processor
3599 * propagates flush to other processors in the cache
3602 atomic_thread_fence_seq_cst();
3603 for (; sva < eva; sva += cpu_clflush_line_size)
3605 atomic_thread_fence_seq_cst();
3608 * Writes are ordered by CLFLUSH on Intel CPUs.
3610 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3612 for (; sva < eva; sva += cpu_clflush_line_size)
3614 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3620 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3623 pmap_invalidate_cache_range_check_align(sva, eva);
3624 pmap_invalidate_cache();
3628 * Remove the specified set of pages from the data and instruction caches.
3630 * In contrast to pmap_invalidate_cache_range(), this function does not
3631 * rely on the CPU's self-snoop feature, because it is intended for use
3632 * when moving pages into a different cache domain.
3635 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3637 vm_offset_t daddr, eva;
3641 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3642 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3643 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3644 pmap_invalidate_cache();
3647 atomic_thread_fence_seq_cst();
3648 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3650 for (i = 0; i < count; i++) {
3651 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3652 eva = daddr + PAGE_SIZE;
3653 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3661 atomic_thread_fence_seq_cst();
3662 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3668 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3671 pmap_invalidate_cache_range_check_align(sva, eva);
3673 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3674 pmap_force_invalidate_cache_range(sva, eva);
3678 /* See comment in pmap_force_invalidate_cache_range(). */
3679 if (pmap_kextract(sva) == lapic_paddr)
3682 atomic_thread_fence_seq_cst();
3683 for (; sva < eva; sva += cpu_clflush_line_size)
3685 atomic_thread_fence_seq_cst();
3689 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3693 int error, pte_bits;
3695 KASSERT((spa & PAGE_MASK) == 0,
3696 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3697 KASSERT((epa & PAGE_MASK) == 0,
3698 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3700 if (spa < dmaplimit) {
3701 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3703 if (dmaplimit >= epa)
3708 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3710 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3712 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3713 pte = vtopte(vaddr);
3714 for (; spa < epa; spa += PAGE_SIZE) {
3716 pte_store(pte, spa | pte_bits);
3718 /* XXXKIB atomic inside flush_cache_range are excessive */
3719 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3722 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3726 * Routine: pmap_extract
3728 * Extract the physical page address associated
3729 * with the given map/virtual_address pair.
3732 pmap_extract(pmap_t pmap, vm_offset_t va)
3736 pt_entry_t *pte, PG_V;
3740 PG_V = pmap_valid_bit(pmap);
3742 pdpe = pmap_pdpe(pmap, va);
3743 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3744 if ((*pdpe & PG_PS) != 0)
3745 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3747 pde = pmap_pdpe_to_pde(pdpe, va);
3748 if ((*pde & PG_V) != 0) {
3749 if ((*pde & PG_PS) != 0) {
3750 pa = (*pde & PG_PS_FRAME) |
3753 pte = pmap_pde_to_pte(pde, va);
3754 pa = (*pte & PG_FRAME) |
3765 * Routine: pmap_extract_and_hold
3767 * Atomically extract and hold the physical page
3768 * with the given pmap and virtual address pair
3769 * if that mapping permits the given protection.
3772 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3774 pdp_entry_t pdpe, *pdpep;
3775 pd_entry_t pde, *pdep;
3776 pt_entry_t pte, PG_RW, PG_V;
3780 PG_RW = pmap_rw_bit(pmap);
3781 PG_V = pmap_valid_bit(pmap);
3784 pdpep = pmap_pdpe(pmap, va);
3785 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3787 if ((pdpe & PG_PS) != 0) {
3788 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3790 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3794 pdep = pmap_pdpe_to_pde(pdpep, va);
3795 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3797 if ((pde & PG_PS) != 0) {
3798 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3800 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3804 pte = *pmap_pde_to_pte(pdep, va);
3805 if ((pte & PG_V) == 0 ||
3806 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3808 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3811 if (m != NULL && !vm_page_wire_mapped(m))
3819 pmap_kextract(vm_offset_t va)
3824 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3825 pa = DMAP_TO_PHYS(va);
3826 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3827 pa = pmap_large_map_kextract(va);
3831 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3834 * Beware of a concurrent promotion that changes the
3835 * PDE at this point! For example, vtopte() must not
3836 * be used to access the PTE because it would use the
3837 * new PDE. It is, however, safe to use the old PDE
3838 * because the page table page is preserved by the
3841 pa = *pmap_pde_to_pte(&pde, va);
3842 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3848 /***************************************************
3849 * Low level mapping routines.....
3850 ***************************************************/
3853 * Add a wired page to the kva.
3854 * Note: not SMP coherent.
3857 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3862 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3865 static __inline void
3866 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3872 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3873 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3877 * Remove a page from the kernel pagetables.
3878 * Note: not SMP coherent.
3881 pmap_kremove(vm_offset_t va)
3890 * Used to map a range of physical addresses into kernel
3891 * virtual address space.
3893 * The value passed in '*virt' is a suggested virtual address for
3894 * the mapping. Architectures which can support a direct-mapped
3895 * physical to virtual region can return the appropriate address
3896 * within that region, leaving '*virt' unchanged. Other
3897 * architectures should map the pages starting at '*virt' and
3898 * update '*virt' with the first usable address after the mapped
3902 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3904 return PHYS_TO_DMAP(start);
3908 * Add a list of wired pages to the kva
3909 * this routine is only used for temporary
3910 * kernel mappings that do not need to have
3911 * page modification or references recorded.
3912 * Note that old mappings are simply written
3913 * over. The page *must* be wired.
3914 * Note: SMP coherent. Uses a ranged shootdown IPI.
3917 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3919 pt_entry_t *endpte, oldpte, pa, *pte;
3925 endpte = pte + count;
3926 while (pte < endpte) {
3928 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3929 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3930 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3932 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3936 if (__predict_false((oldpte & X86_PG_V) != 0))
3937 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3942 * This routine tears out page mappings from the
3943 * kernel -- it is meant only for temporary mappings.
3944 * Note: SMP coherent. Uses a ranged shootdown IPI.
3947 pmap_qremove(vm_offset_t sva, int count)
3952 while (count-- > 0) {
3953 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3957 pmap_invalidate_range(kernel_pmap, sva, va);
3960 /***************************************************
3961 * Page table page management routines.....
3962 ***************************************************/
3964 * Schedule the specified unused page table page to be freed. Specifically,
3965 * add the page to the specified list of pages that will be released to the
3966 * physical memory manager after the TLB has been updated.
3968 static __inline void
3969 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3970 boolean_t set_PG_ZERO)
3974 m->flags |= PG_ZERO;
3976 m->flags &= ~PG_ZERO;
3977 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3981 * Inserts the specified page table page into the specified pmap's collection
3982 * of idle page table pages. Each of a pmap's page table pages is responsible
3983 * for mapping a distinct range of virtual addresses. The pmap's collection is
3984 * ordered by this virtual address range.
3986 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3989 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3992 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3993 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3994 return (vm_radix_insert(&pmap->pm_root, mpte));
3998 * Removes the page table page mapping the specified virtual address from the
3999 * specified pmap's collection of idle page table pages, and returns it.
4000 * Otherwise, returns NULL if there is no page table page corresponding to the
4001 * specified virtual address.
4003 static __inline vm_page_t
4004 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
4007 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4008 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
4012 * Decrements a page table page's reference count, which is used to record the
4013 * number of valid page table entries within the page. If the reference count
4014 * drops to zero, then the page table page is unmapped. Returns TRUE if the
4015 * page table page was unmapped and FALSE otherwise.
4017 static inline boolean_t
4018 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4022 if (m->ref_count == 0) {
4023 _pmap_unwire_ptp(pmap, va, m, free);
4030 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4036 vm_page_t pdpg, pdppg, pml4pg;
4038 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4041 * unmap the page table page
4043 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
4045 MPASS(pmap_is_la57(pmap));
4046 pml5 = pmap_pml5e(pmap, va);
4048 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
4049 pml5 = pmap_pml5e_u(pmap, va);
4052 } else if (m->pindex >= NUPDE + NUPDPE) {
4054 pml4 = pmap_pml4e(pmap, va);
4056 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4057 va <= VM_MAXUSER_ADDRESS) {
4058 pml4 = pmap_pml4e_u(pmap, va);
4061 } else if (m->pindex >= NUPDE) {
4063 pdp = pmap_pdpe(pmap, va);
4067 pd = pmap_pde(pmap, va);
4070 if (m->pindex < NUPDE) {
4071 /* We just released a PT, unhold the matching PD */
4072 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
4073 pmap_unwire_ptp(pmap, va, pdpg, free);
4074 } else if (m->pindex < NUPDE + NUPDPE) {
4075 /* We just released a PD, unhold the matching PDP */
4076 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
4077 pmap_unwire_ptp(pmap, va, pdppg, free);
4078 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
4079 /* We just released a PDP, unhold the matching PML4 */
4080 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
4081 pmap_unwire_ptp(pmap, va, pml4pg, free);
4084 pmap_pt_page_count_adj(pmap, -1);
4087 * Put page on a list so that it is released after
4088 * *ALL* TLB shootdown is done
4090 pmap_add_delayed_free_list(m, free, TRUE);
4094 * After removing a page table entry, this routine is used to
4095 * conditionally free the page, and manage the reference count.
4098 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
4099 struct spglist *free)
4103 if (va >= VM_MAXUSER_ADDRESS)
4105 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
4106 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
4107 return (pmap_unwire_ptp(pmap, va, mpte, free));
4111 * Release a page table page reference after a failed attempt to create a
4115 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
4117 struct spglist free;
4120 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4122 * Although "va" was never mapped, paging-structure caches
4123 * could nonetheless have entries that refer to the freed
4124 * page table pages. Invalidate those entries.
4126 pmap_invalidate_page(pmap, va);
4127 vm_page_free_pages_toq(&free, true);
4132 pmap_pinit0(pmap_t pmap)
4138 PMAP_LOCK_INIT(pmap);
4139 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
4140 pmap->pm_pmltopu = NULL;
4141 pmap->pm_cr3 = kernel_pmap->pm_cr3;
4142 /* hack to keep pmap_pti_pcid_invalidate() alive */
4143 pmap->pm_ucr3 = PMAP_NO_CR3;
4144 vm_radix_init(&pmap->pm_root);
4145 CPU_ZERO(&pmap->pm_active);
4146 TAILQ_INIT(&pmap->pm_pvchunk);
4147 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4148 pmap->pm_flags = pmap_flags;
4150 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
4151 pmap->pm_pcids[i].pm_gen = 1;
4153 pmap_activate_boot(pmap);
4158 p->p_md.md_flags |= P_MD_KPTI;
4161 pmap_thread_init_invl_gen(td);
4163 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4164 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
4165 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
4171 pmap_pinit_pml4(vm_page_t pml4pg)
4173 pml4_entry_t *pm_pml4;
4176 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
4178 /* Wire in kernel global address entries. */
4179 for (i = 0; i < NKPML4E; i++) {
4180 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
4184 for (i = 0; i < NKASANPML4E; i++) {
4185 pm_pml4[KASANPML4I + i] = (KASANPDPphys + ptoa(i)) | X86_PG_RW |
4189 for (i = 0; i < ndmpdpphys; i++) {
4190 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
4194 /* install self-referential address mapping entry(s) */
4195 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
4196 X86_PG_A | X86_PG_M;
4198 /* install large map entries if configured */
4199 for (i = 0; i < lm_ents; i++)
4200 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4204 pmap_pinit_pml5(vm_page_t pml5pg)
4206 pml5_entry_t *pm_pml5;
4208 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4211 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4212 * entering all existing kernel mappings into level 5 table.
4214 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4215 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4216 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4219 * Install self-referential address mapping entry.
4221 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4222 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4223 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4227 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4229 pml4_entry_t *pm_pml4u;
4232 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4233 for (i = 0; i < NPML4EPG; i++)
4234 pm_pml4u[i] = pti_pml4[i];
4238 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4240 pml5_entry_t *pm_pml5u;
4242 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4246 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4247 * table, entering all kernel mappings needed for usermode
4248 * into level 5 table.
4250 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4251 pmap_kextract((vm_offset_t)pti_pml4) |
4252 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4253 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4256 /* Allocate a page table page and do related bookkeeping */
4258 pmap_alloc_pt_page(pmap_t pmap, vm_pindex_t pindex, int flags)
4262 m = vm_page_alloc_noobj(flags);
4263 if (__predict_false(m == NULL))
4266 pmap_pt_page_count_adj(pmap, 1);
4271 pmap_free_pt_page(pmap_t pmap, vm_page_t m, bool zerofilled)
4274 * This function assumes the page will need to be unwired,
4275 * even though the counterpart allocation in pmap_alloc_pt_page()
4276 * doesn't enforce VM_ALLOC_WIRED. However, all current uses
4277 * of pmap_free_pt_page() require unwiring. The case in which
4278 * a PT page doesn't require unwiring because its ref_count has
4279 * naturally reached 0 is handled through _pmap_unwire_ptp().
4281 vm_page_unwire_noq(m);
4283 vm_page_free_zero(m);
4287 pmap_pt_page_count_adj(pmap, -1);
4291 * Initialize a preallocated and zeroed pmap structure,
4292 * such as one in a vmspace structure.
4295 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4297 vm_page_t pmltop_pg, pmltop_pgu;
4298 vm_paddr_t pmltop_phys;
4301 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4304 * Allocate the page directory page. Pass NULL instead of a
4305 * pointer to the pmap here to avoid calling
4306 * pmap_resident_count_adj() through pmap_pt_page_count_adj(),
4307 * since that requires pmap lock. Instead do the accounting
4310 * Note that final call to pmap_remove() optimization that
4311 * checks for zero resident_count is basically disabled by
4312 * accounting for top-level page. But the optimization was
4313 * not effective since we started using non-managed mapping of
4316 pmltop_pg = pmap_alloc_pt_page(NULL, 0, VM_ALLOC_WIRED | VM_ALLOC_ZERO |
4318 pmap_pt_page_count_pinit(pmap, 1);
4320 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4321 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4324 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4325 pmap->pm_pcids[i].pm_gen = 0;
4327 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4328 pmap->pm_ucr3 = PMAP_NO_CR3;
4329 pmap->pm_pmltopu = NULL;
4331 pmap->pm_type = pm_type;
4334 * Do not install the host kernel mappings in the nested page
4335 * tables. These mappings are meaningless in the guest physical
4337 * Install minimal kernel mappings in PTI case.
4341 pmap->pm_cr3 = pmltop_phys;
4342 if (pmap_is_la57(pmap))
4343 pmap_pinit_pml5(pmltop_pg);
4345 pmap_pinit_pml4(pmltop_pg);
4346 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4348 * As with pmltop_pg, pass NULL instead of a
4349 * pointer to the pmap to ensure that the PTI
4350 * page counted explicitly.
4352 pmltop_pgu = pmap_alloc_pt_page(NULL, 0,
4353 VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4354 pmap_pt_page_count_pinit(pmap, 1);
4355 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4356 VM_PAGE_TO_PHYS(pmltop_pgu));
4357 if (pmap_is_la57(pmap))
4358 pmap_pinit_pml5_pti(pmltop_pgu);
4360 pmap_pinit_pml4_pti(pmltop_pgu);
4361 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4363 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4364 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4365 pkru_free_range, pmap, M_NOWAIT);
4370 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4374 vm_radix_init(&pmap->pm_root);
4375 CPU_ZERO(&pmap->pm_active);
4376 TAILQ_INIT(&pmap->pm_pvchunk);
4377 pmap->pm_flags = flags;
4378 pmap->pm_eptgen = 0;
4384 pmap_pinit(pmap_t pmap)
4387 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4391 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4394 struct spglist free;
4396 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4397 if (mpg->ref_count != 0)
4400 _pmap_unwire_ptp(pmap, va, mpg, &free);
4401 pmap_invalidate_page(pmap, va);
4402 vm_page_free_pages_toq(&free, true);
4405 static pml4_entry_t *
4406 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4409 vm_pindex_t pml5index;
4416 if (!pmap_is_la57(pmap))
4417 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4419 PG_V = pmap_valid_bit(pmap);
4420 pml5index = pmap_pml5e_index(va);
4421 pml5 = &pmap->pm_pmltop[pml5index];
4422 if ((*pml5 & PG_V) == 0) {
4423 if (pmap_allocpte_nosleep(pmap, pmap_pml5e_pindex(va), lockp,
4430 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4431 pml4 = &pml4[pmap_pml4e_index(va)];
4432 if ((*pml4 & PG_V) == 0) {
4433 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4434 if (allocated && !addref)
4435 pml4pg->ref_count--;
4436 else if (!allocated && addref)
4437 pml4pg->ref_count++;
4442 static pdp_entry_t *
4443 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4452 PG_V = pmap_valid_bit(pmap);
4454 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4458 if ((*pml4 & PG_V) == 0) {
4459 /* Have to allocate a new pdp, recurse */
4460 if (pmap_allocpte_nosleep(pmap, pmap_pml4e_pindex(va), lockp,
4462 if (pmap_is_la57(pmap))
4463 pmap_allocpte_free_unref(pmap, va,
4464 pmap_pml5e(pmap, va));
4471 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4472 pdp = &pdp[pmap_pdpe_index(va)];
4473 if ((*pdp & PG_V) == 0) {
4474 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4475 if (allocated && !addref)
4477 else if (!allocated && addref)
4484 * The ptepindexes, i.e. page indices, of the page table pages encountered
4485 * while translating virtual address va are defined as follows:
4486 * - for the page table page (last level),
4487 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4488 * in other words, it is just the index of the PDE that maps the page
4490 * - for the page directory page,
4491 * ptepindex = NUPDE (number of userland PD entries) +
4492 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4493 * i.e. index of PDPE is put after the last index of PDE,
4494 * - for the page directory pointer page,
4495 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4497 * i.e. index of pml4e is put after the last index of PDPE,
4498 * - for the PML4 page (if LA57 mode is enabled),
4499 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4500 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4501 * i.e. index of pml5e is put after the last index of PML4E.
4503 * Define an order on the paging entries, where all entries of the
4504 * same height are put together, then heights are put from deepest to
4505 * root. Then ptexpindex is the sequential number of the
4506 * corresponding paging entry in this order.
4508 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4509 * LA57 paging structures even in LA48 paging mode. Moreover, the
4510 * ptepindexes are calculated as if the paging structures were 5-level
4511 * regardless of the actual mode of operation.
4513 * The root page at PML4/PML5 does not participate in this indexing scheme,
4514 * since it is statically allocated by pmap_pinit() and not by pmap_allocpte().
4517 pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4520 vm_pindex_t pml5index, pml4index;
4521 pml5_entry_t *pml5, *pml5u;
4522 pml4_entry_t *pml4, *pml4u;
4526 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4528 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4530 PG_A = pmap_accessed_bit(pmap);
4531 PG_M = pmap_modified_bit(pmap);
4532 PG_V = pmap_valid_bit(pmap);
4533 PG_RW = pmap_rw_bit(pmap);
4536 * Allocate a page table page.
4538 m = pmap_alloc_pt_page(pmap, ptepindex,
4539 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4544 * Map the pagetable page into the process address space, if
4545 * it isn't already there.
4547 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4548 MPASS(pmap_is_la57(pmap));
4550 pml5index = pmap_pml5e_index(va);
4551 pml5 = &pmap->pm_pmltop[pml5index];
4552 KASSERT((*pml5 & PG_V) == 0,
4553 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4554 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4556 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4557 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4560 pml5u = &pmap->pm_pmltopu[pml5index];
4561 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4564 } else if (ptepindex >= NUPDE + NUPDPE) {
4565 pml4index = pmap_pml4e_index(va);
4566 /* Wire up a new PDPE page */
4567 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4569 pmap_free_pt_page(pmap, m, true);
4572 KASSERT((*pml4 & PG_V) == 0,
4573 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4574 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4576 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4577 pml4index < NUPML4E) {
4579 * PTI: Make all user-space mappings in the
4580 * kernel-mode page table no-execute so that
4581 * we detect any programming errors that leave
4582 * the kernel-mode page table active on return
4585 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4588 pml4u = &pmap->pm_pmltopu[pml4index];
4589 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4592 } else if (ptepindex >= NUPDE) {
4593 /* Wire up a new PDE page */
4594 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4596 pmap_free_pt_page(pmap, m, true);
4599 KASSERT((*pdp & PG_V) == 0,
4600 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4601 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4603 /* Wire up a new PTE page */
4604 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4606 pmap_free_pt_page(pmap, m, true);
4609 if ((*pdp & PG_V) == 0) {
4610 /* Have to allocate a new pd, recurse */
4611 if (pmap_allocpte_nosleep(pmap, pmap_pdpe_pindex(va),
4612 lockp, va) == NULL) {
4613 pmap_allocpte_free_unref(pmap, va,
4614 pmap_pml4e(pmap, va));
4615 pmap_free_pt_page(pmap, m, true);
4619 /* Add reference to the pd page */
4620 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4623 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4625 /* Now we know where the page directory page is */
4626 pd = &pd[pmap_pde_index(va)];
4627 KASSERT((*pd & PG_V) == 0,
4628 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4629 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4636 * This routine is called if the desired page table page does not exist.
4638 * If page table page allocation fails, this routine may sleep before
4639 * returning NULL. It sleeps only if a lock pointer was given. Sleep
4640 * occurs right before returning to the caller. This way, we never
4641 * drop pmap lock to sleep while a page table page has ref_count == 0,
4642 * which prevents the page from being freed under us.
4645 pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4650 m = pmap_allocpte_nosleep(pmap, ptepindex, lockp, va);
4651 if (m == NULL && lockp != NULL) {
4652 RELEASE_PV_LIST_LOCK(lockp);
4654 PMAP_ASSERT_NOT_IN_DI();
4662 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4663 struct rwlock **lockp)
4665 pdp_entry_t *pdpe, PG_V;
4668 vm_pindex_t pdpindex;
4670 PG_V = pmap_valid_bit(pmap);
4673 pdpe = pmap_pdpe(pmap, va);
4674 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4675 pde = pmap_pdpe_to_pde(pdpe, va);
4676 if (va < VM_MAXUSER_ADDRESS) {
4677 /* Add a reference to the pd page. */
4678 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4682 } else if (va < VM_MAXUSER_ADDRESS) {
4683 /* Allocate a pd page. */
4684 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4685 pdpg = pmap_allocpte_alloc(pmap, NUPDE + pdpindex, lockp, va);
4692 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4693 pde = &pde[pmap_pde_index(va)];
4695 panic("pmap_alloc_pde: missing page table page for va %#lx",
4702 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4704 vm_pindex_t ptepindex;
4705 pd_entry_t *pd, PG_V;
4708 PG_V = pmap_valid_bit(pmap);
4711 * Calculate pagetable page index
4713 ptepindex = pmap_pde_pindex(va);
4716 * Get the page directory entry
4718 pd = pmap_pde(pmap, va);
4721 * This supports switching from a 2MB page to a
4724 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4725 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4727 * Invalidation of the 2MB page mapping may have caused
4728 * the deallocation of the underlying PD page.
4735 * If the page table page is mapped, we just increment the
4736 * hold count, and activate it.
4738 if (pd != NULL && (*pd & PG_V) != 0) {
4739 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4743 * Here if the pte page isn't mapped, or if it has been
4746 m = pmap_allocpte_alloc(pmap, ptepindex, lockp, va);
4747 if (m == NULL && lockp != NULL)
4753 /***************************************************
4754 * Pmap allocation/deallocation routines.
4755 ***************************************************/
4758 * Release any resources held by the given physical map.
4759 * Called when a pmap initialized by pmap_pinit is being released.
4760 * Should only be called if the map contains no valid mappings.
4763 pmap_release(pmap_t pmap)
4768 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4769 ("pmap_release: pmap %p has reserved page table page(s)",
4771 KASSERT(CPU_EMPTY(&pmap->pm_active),
4772 ("releasing active pmap %p", pmap));
4774 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4776 if (pmap_is_la57(pmap)) {
4777 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4778 pmap->pm_pmltop[PML5PML5I] = 0;
4780 for (i = 0; i < NKPML4E; i++) /* KVA */
4781 pmap->pm_pmltop[KPML4BASE + i] = 0;
4783 for (i = 0; i < NKASANPML4E; i++) /* KASAN shadow map */
4784 pmap->pm_pmltop[KASANPML4I + i] = 0;
4786 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4787 pmap->pm_pmltop[DMPML4I + i] = 0;
4788 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4789 for (i = 0; i < lm_ents; i++) /* Large Map */
4790 pmap->pm_pmltop[LMSPML4I + i] = 0;
4793 pmap_free_pt_page(NULL, m, true);
4794 pmap_pt_page_count_pinit(pmap, -1);
4796 if (pmap->pm_pmltopu != NULL) {
4797 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4799 pmap_free_pt_page(NULL, m, false);
4800 pmap_pt_page_count_pinit(pmap, -1);
4802 if (pmap->pm_type == PT_X86 &&
4803 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4804 rangeset_fini(&pmap->pm_pkru);
4806 KASSERT(pmap->pm_stats.resident_count == 0,
4807 ("pmap_release: pmap %p resident count %ld != 0",
4808 pmap, pmap->pm_stats.resident_count));
4812 kvm_size(SYSCTL_HANDLER_ARGS)
4814 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4816 return sysctl_handle_long(oidp, &ksize, 0, req);
4818 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4819 0, 0, kvm_size, "LU",
4823 kvm_free(SYSCTL_HANDLER_ARGS)
4825 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4827 return sysctl_handle_long(oidp, &kfree, 0, req);
4829 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4830 0, 0, kvm_free, "LU",
4831 "Amount of KVM free");
4834 * Allocate physical memory for the vm_page array and map it into KVA,
4835 * attempting to back the vm_pages with domain-local memory.
4838 pmap_page_array_startup(long pages)
4841 pd_entry_t *pde, newpdir;
4842 vm_offset_t va, start, end;
4847 vm_page_array_size = pages;
4849 start = VM_MIN_KERNEL_ADDRESS;
4850 end = start + pages * sizeof(struct vm_page);
4851 for (va = start; va < end; va += NBPDR) {
4852 pfn = first_page + (va - start) / sizeof(struct vm_page);
4853 domain = vm_phys_domain(ptoa(pfn));
4854 pdpe = pmap_pdpe(kernel_pmap, va);
4855 if ((*pdpe & X86_PG_V) == 0) {
4856 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4858 pagezero((void *)PHYS_TO_DMAP(pa));
4859 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4860 X86_PG_A | X86_PG_M);
4862 pde = pmap_pdpe_to_pde(pdpe, va);
4863 if ((*pde & X86_PG_V) != 0)
4864 panic("Unexpected pde");
4865 pa = vm_phys_early_alloc(domain, NBPDR);
4866 for (i = 0; i < NPDEPG; i++)
4867 dump_add_page(pa + i * PAGE_SIZE);
4868 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4869 X86_PG_M | PG_PS | pg_g | pg_nx);
4870 pde_store(pde, newpdir);
4872 vm_page_array = (vm_page_t)start;
4876 * grow the number of kernel page table entries, if needed
4879 pmap_growkernel(vm_offset_t addr)
4883 pd_entry_t *pde, newpdir;
4886 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4889 * Return if "addr" is within the range of kernel page table pages
4890 * that were preallocated during pmap bootstrap. Moreover, leave
4891 * "kernel_vm_end" and the kernel page table as they were.
4893 * The correctness of this action is based on the following
4894 * argument: vm_map_insert() allocates contiguous ranges of the
4895 * kernel virtual address space. It calls this function if a range
4896 * ends after "kernel_vm_end". If the kernel is mapped between
4897 * "kernel_vm_end" and "addr", then the range cannot begin at
4898 * "kernel_vm_end". In fact, its beginning address cannot be less
4899 * than the kernel. Thus, there is no immediate need to allocate
4900 * any new kernel page table pages between "kernel_vm_end" and
4903 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4906 addr = roundup2(addr, NBPDR);
4907 if (addr - 1 >= vm_map_max(kernel_map))
4908 addr = vm_map_max(kernel_map);
4909 if (kernel_vm_end < addr)
4910 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
4911 while (kernel_vm_end < addr) {
4912 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4913 if ((*pdpe & X86_PG_V) == 0) {
4914 /* We need a new PDP entry */
4915 nkpg = pmap_alloc_pt_page(kernel_pmap,
4916 kernel_vm_end >> PDPSHIFT, VM_ALLOC_WIRED |
4917 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
4919 panic("pmap_growkernel: no memory to grow kernel");
4920 paddr = VM_PAGE_TO_PHYS(nkpg);
4921 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4922 X86_PG_A | X86_PG_M);
4923 continue; /* try again */
4925 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4926 if ((*pde & X86_PG_V) != 0) {
4927 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4928 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4929 kernel_vm_end = vm_map_max(kernel_map);
4935 nkpg = pmap_alloc_pt_page(kernel_pmap,
4936 pmap_pde_pindex(kernel_vm_end), VM_ALLOC_WIRED |
4937 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
4939 panic("pmap_growkernel: no memory to grow kernel");
4940 paddr = VM_PAGE_TO_PHYS(nkpg);
4941 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4942 pde_store(pde, newpdir);
4944 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4945 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4946 kernel_vm_end = vm_map_max(kernel_map);
4952 /***************************************************
4953 * page management routines.
4954 ***************************************************/
4956 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4957 CTASSERT(_NPCM == 3);
4958 CTASSERT(_NPCPV == 168);
4960 static __inline struct pv_chunk *
4961 pv_to_chunk(pv_entry_t pv)
4964 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4967 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4969 #define PC_FREE0 0xfffffffffffffffful
4970 #define PC_FREE1 0xfffffffffffffffful
4971 #define PC_FREE2 0x000000fffffffffful
4973 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4977 static COUNTER_U64_DEFINE_EARLY(pc_chunk_count);
4978 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD,
4979 &pc_chunk_count, "Current number of pv entry cnunks");
4981 static COUNTER_U64_DEFINE_EARLY(pc_chunk_allocs);
4982 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD,
4983 &pc_chunk_allocs, "Total number of pv entry chunks allocated");
4985 static COUNTER_U64_DEFINE_EARLY(pc_chunk_frees);
4986 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD,
4987 &pc_chunk_frees, "Total number of pv entry chunks freed");
4989 static COUNTER_U64_DEFINE_EARLY(pc_chunk_tryfail);
4990 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD,
4992 "Number of failed attempts to get a pv entry chunk page");
4994 static COUNTER_U64_DEFINE_EARLY(pv_entry_frees);
4995 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD,
4996 &pv_entry_frees, "Total number of pv entries freed");
4998 static COUNTER_U64_DEFINE_EARLY(pv_entry_allocs);
4999 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD,
5000 &pv_entry_allocs, "Total number of pv entries allocated");
5002 static COUNTER_U64_DEFINE_EARLY(pv_entry_count);
5003 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD,
5004 &pv_entry_count, "Current number of pv entries");
5006 static COUNTER_U64_DEFINE_EARLY(pv_entry_spare);
5007 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD,
5008 &pv_entry_spare, "Current number of spare pv entries");
5012 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
5017 pmap_invalidate_all(pmap);
5018 if (pmap != locked_pmap)
5021 pmap_delayed_invl_finish();
5025 * We are in a serious low memory condition. Resort to
5026 * drastic measures to free some pages so we can allocate
5027 * another pv entry chunk.
5029 * Returns NULL if PV entries were reclaimed from the specified pmap.
5031 * We do not, however, unmap 2mpages because subsequent accesses will
5032 * allocate per-page pv entries until repromotion occurs, thereby
5033 * exacerbating the shortage of free pv entries.
5036 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
5038 struct pv_chunks_list *pvc;
5039 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
5040 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
5041 struct md_page *pvh;
5043 pmap_t next_pmap, pmap;
5044 pt_entry_t *pte, tpte;
5045 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5049 struct spglist free;
5051 int bit, field, freed;
5052 bool start_di, restart;
5054 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
5055 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
5058 PG_G = PG_A = PG_M = PG_RW = 0;
5060 bzero(&pc_marker_b, sizeof(pc_marker_b));
5061 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
5062 pc_marker = (struct pv_chunk *)&pc_marker_b;
5063 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
5066 * A delayed invalidation block should already be active if
5067 * pmap_advise() or pmap_remove() called this function by way
5068 * of pmap_demote_pde_locked().
5070 start_di = pmap_not_in_di();
5072 pvc = &pv_chunks[domain];
5073 mtx_lock(&pvc->pvc_lock);
5074 pvc->active_reclaims++;
5075 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
5076 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
5077 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
5078 SLIST_EMPTY(&free)) {
5079 next_pmap = pc->pc_pmap;
5080 if (next_pmap == NULL) {
5082 * The next chunk is a marker. However, it is
5083 * not our marker, so active_reclaims must be
5084 * > 1. Consequently, the next_chunk code
5085 * will not rotate the pv_chunks list.
5089 mtx_unlock(&pvc->pvc_lock);
5092 * A pv_chunk can only be removed from the pc_lru list
5093 * when both pc_chunks_mutex is owned and the
5094 * corresponding pmap is locked.
5096 if (pmap != next_pmap) {
5098 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
5101 /* Avoid deadlock and lock recursion. */
5102 if (pmap > locked_pmap) {
5103 RELEASE_PV_LIST_LOCK(lockp);
5106 pmap_delayed_invl_start();
5107 mtx_lock(&pvc->pvc_lock);
5109 } else if (pmap != locked_pmap) {
5110 if (PMAP_TRYLOCK(pmap)) {
5112 pmap_delayed_invl_start();
5113 mtx_lock(&pvc->pvc_lock);
5116 pmap = NULL; /* pmap is not locked */
5117 mtx_lock(&pvc->pvc_lock);
5118 pc = TAILQ_NEXT(pc_marker, pc_lru);
5120 pc->pc_pmap != next_pmap)
5124 } else if (start_di)
5125 pmap_delayed_invl_start();
5126 PG_G = pmap_global_bit(pmap);
5127 PG_A = pmap_accessed_bit(pmap);
5128 PG_M = pmap_modified_bit(pmap);
5129 PG_RW = pmap_rw_bit(pmap);
5135 * Destroy every non-wired, 4 KB page mapping in the chunk.
5138 for (field = 0; field < _NPCM; field++) {
5139 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
5140 inuse != 0; inuse &= ~(1UL << bit)) {
5142 pv = &pc->pc_pventry[field * 64 + bit];
5144 pde = pmap_pde(pmap, va);
5145 if ((*pde & PG_PS) != 0)
5147 pte = pmap_pde_to_pte(pde, va);
5148 if ((*pte & PG_W) != 0)
5150 tpte = pte_load_clear(pte);
5151 if ((tpte & PG_G) != 0)
5152 pmap_invalidate_page(pmap, va);
5153 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
5154 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5156 if ((tpte & PG_A) != 0)
5157 vm_page_aflag_set(m, PGA_REFERENCED);
5158 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5159 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5161 if (TAILQ_EMPTY(&m->md.pv_list) &&
5162 (m->flags & PG_FICTITIOUS) == 0) {
5163 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5164 if (TAILQ_EMPTY(&pvh->pv_list)) {
5165 vm_page_aflag_clear(m,
5169 pmap_delayed_invl_page(m);
5170 pc->pc_map[field] |= 1UL << bit;
5171 pmap_unuse_pt(pmap, va, *pde, &free);
5176 mtx_lock(&pvc->pvc_lock);
5179 /* Every freed mapping is for a 4 KB page. */
5180 pmap_resident_count_adj(pmap, -freed);
5181 PV_STAT(counter_u64_add(pv_entry_frees, freed));
5182 PV_STAT(counter_u64_add(pv_entry_spare, freed));
5183 PV_STAT(counter_u64_add(pv_entry_count, -freed));
5184 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5185 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
5186 pc->pc_map[2] == PC_FREE2) {
5187 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5188 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5189 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5190 /* Entire chunk is free; return it. */
5191 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5192 dump_drop_page(m_pc->phys_addr);
5193 mtx_lock(&pvc->pvc_lock);
5194 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5197 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5198 mtx_lock(&pvc->pvc_lock);
5199 /* One freed pv entry in locked_pmap is sufficient. */
5200 if (pmap == locked_pmap)
5203 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5204 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
5205 if (pvc->active_reclaims == 1 && pmap != NULL) {
5207 * Rotate the pv chunks list so that we do not
5208 * scan the same pv chunks that could not be
5209 * freed (because they contained a wired
5210 * and/or superpage mapping) on every
5211 * invocation of reclaim_pv_chunk().
5213 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
5214 MPASS(pc->pc_pmap != NULL);
5215 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5216 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5220 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5221 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
5222 pvc->active_reclaims--;
5223 mtx_unlock(&pvc->pvc_lock);
5224 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
5225 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
5226 m_pc = SLIST_FIRST(&free);
5227 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
5228 /* Recycle a freed page table page. */
5229 m_pc->ref_count = 1;
5231 vm_page_free_pages_toq(&free, true);
5236 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
5241 domain = PCPU_GET(domain);
5242 for (i = 0; i < vm_ndomains; i++) {
5243 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
5246 domain = (domain + 1) % vm_ndomains;
5253 * free the pv_entry back to the free list
5256 free_pv_entry(pmap_t pmap, pv_entry_t pv)
5258 struct pv_chunk *pc;
5259 int idx, field, bit;
5261 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5262 PV_STAT(counter_u64_add(pv_entry_frees, 1));
5263 PV_STAT(counter_u64_add(pv_entry_spare, 1));
5264 PV_STAT(counter_u64_add(pv_entry_count, -1));
5265 pc = pv_to_chunk(pv);
5266 idx = pv - &pc->pc_pventry[0];
5269 pc->pc_map[field] |= 1ul << bit;
5270 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5271 pc->pc_map[2] != PC_FREE2) {
5272 /* 98% of the time, pc is already at the head of the list. */
5273 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5274 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5275 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5279 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5284 free_pv_chunk_dequeued(struct pv_chunk *pc)
5288 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5289 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5290 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5291 counter_u64_add(pv_page_count, -1);
5292 /* entire chunk is free, return it */
5293 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5294 dump_drop_page(m->phys_addr);
5295 vm_page_unwire_noq(m);
5300 free_pv_chunk(struct pv_chunk *pc)
5302 struct pv_chunks_list *pvc;
5304 pvc = &pv_chunks[pc_to_domain(pc)];
5305 mtx_lock(&pvc->pvc_lock);
5306 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5307 mtx_unlock(&pvc->pvc_lock);
5308 free_pv_chunk_dequeued(pc);
5312 free_pv_chunk_batch(struct pv_chunklist *batch)
5314 struct pv_chunks_list *pvc;
5315 struct pv_chunk *pc, *npc;
5318 for (i = 0; i < vm_ndomains; i++) {
5319 if (TAILQ_EMPTY(&batch[i]))
5321 pvc = &pv_chunks[i];
5322 mtx_lock(&pvc->pvc_lock);
5323 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5324 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5326 mtx_unlock(&pvc->pvc_lock);
5329 for (i = 0; i < vm_ndomains; i++) {
5330 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5331 free_pv_chunk_dequeued(pc);
5337 * Returns a new PV entry, allocating a new PV chunk from the system when
5338 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5339 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5342 * The given PV list lock may be released.
5345 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5347 struct pv_chunks_list *pvc;
5350 struct pv_chunk *pc;
5353 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5354 PV_STAT(counter_u64_add(pv_entry_allocs, 1));
5356 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5358 for (field = 0; field < _NPCM; field++) {
5359 if (pc->pc_map[field]) {
5360 bit = bsfq(pc->pc_map[field]);
5364 if (field < _NPCM) {
5365 pv = &pc->pc_pventry[field * 64 + bit];
5366 pc->pc_map[field] &= ~(1ul << bit);
5367 /* If this was the last item, move it to tail */
5368 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5369 pc->pc_map[2] == 0) {
5370 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5371 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5374 PV_STAT(counter_u64_add(pv_entry_count, 1));
5375 PV_STAT(counter_u64_add(pv_entry_spare, -1));
5379 /* No free items, allocate another chunk */
5380 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
5382 if (lockp == NULL) {
5383 PV_STAT(counter_u64_add(pc_chunk_tryfail, 1));
5386 m = reclaim_pv_chunk(pmap, lockp);
5390 counter_u64_add(pv_page_count, 1);
5391 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5392 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5393 dump_add_page(m->phys_addr);
5394 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5396 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5397 pc->pc_map[1] = PC_FREE1;
5398 pc->pc_map[2] = PC_FREE2;
5399 pvc = &pv_chunks[vm_page_domain(m)];
5400 mtx_lock(&pvc->pvc_lock);
5401 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5402 mtx_unlock(&pvc->pvc_lock);
5403 pv = &pc->pc_pventry[0];
5404 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5405 PV_STAT(counter_u64_add(pv_entry_count, 1));
5406 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV - 1));
5411 * Returns the number of one bits within the given PV chunk map.
5413 * The erratas for Intel processors state that "POPCNT Instruction May
5414 * Take Longer to Execute Than Expected". It is believed that the
5415 * issue is the spurious dependency on the destination register.
5416 * Provide a hint to the register rename logic that the destination
5417 * value is overwritten, by clearing it, as suggested in the
5418 * optimization manual. It should be cheap for unaffected processors
5421 * Reference numbers for erratas are
5422 * 4th Gen Core: HSD146
5423 * 5th Gen Core: BDM85
5424 * 6th Gen Core: SKL029
5427 popcnt_pc_map_pq(uint64_t *map)
5431 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5432 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5433 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5434 : "=&r" (result), "=&r" (tmp)
5435 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5440 * Ensure that the number of spare PV entries in the specified pmap meets or
5441 * exceeds the given count, "needed".
5443 * The given PV list lock may be released.
5446 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5448 struct pv_chunks_list *pvc;
5449 struct pch new_tail[PMAP_MEMDOM];
5450 struct pv_chunk *pc;
5455 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5456 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5459 * Newly allocated PV chunks must be stored in a private list until
5460 * the required number of PV chunks have been allocated. Otherwise,
5461 * reclaim_pv_chunk() could recycle one of these chunks. In
5462 * contrast, these chunks must be added to the pmap upon allocation.
5464 for (i = 0; i < PMAP_MEMDOM; i++)
5465 TAILQ_INIT(&new_tail[i]);
5468 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5470 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5471 bit_count((bitstr_t *)pc->pc_map, 0,
5472 sizeof(pc->pc_map) * NBBY, &free);
5475 free = popcnt_pc_map_pq(pc->pc_map);
5479 if (avail >= needed)
5482 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5483 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
5485 m = reclaim_pv_chunk(pmap, lockp);
5490 counter_u64_add(pv_page_count, 1);
5491 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5492 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5493 dump_add_page(m->phys_addr);
5494 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5496 pc->pc_map[0] = PC_FREE0;
5497 pc->pc_map[1] = PC_FREE1;
5498 pc->pc_map[2] = PC_FREE2;
5499 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5500 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
5501 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV));
5504 * The reclaim might have freed a chunk from the current pmap.
5505 * If that chunk contained available entries, we need to
5506 * re-count the number of available entries.
5511 for (i = 0; i < vm_ndomains; i++) {
5512 if (TAILQ_EMPTY(&new_tail[i]))
5514 pvc = &pv_chunks[i];
5515 mtx_lock(&pvc->pvc_lock);
5516 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5517 mtx_unlock(&pvc->pvc_lock);
5522 * First find and then remove the pv entry for the specified pmap and virtual
5523 * address from the specified pv list. Returns the pv entry if found and NULL
5524 * otherwise. This operation can be performed on pv lists for either 4KB or
5525 * 2MB page mappings.
5527 static __inline pv_entry_t
5528 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5532 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5533 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5534 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5543 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5544 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5545 * entries for each of the 4KB page mappings.
5548 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5549 struct rwlock **lockp)
5551 struct md_page *pvh;
5552 struct pv_chunk *pc;
5554 vm_offset_t va_last;
5558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5559 KASSERT((pa & PDRMASK) == 0,
5560 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5561 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5564 * Transfer the 2mpage's pv entry for this mapping to the first
5565 * page's pv list. Once this transfer begins, the pv list lock
5566 * must not be released until the last pv entry is reinstantiated.
5568 pvh = pa_to_pvh(pa);
5569 va = trunc_2mpage(va);
5570 pv = pmap_pvh_remove(pvh, pmap, va);
5571 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5572 m = PHYS_TO_VM_PAGE(pa);
5573 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5575 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5576 PV_STAT(counter_u64_add(pv_entry_allocs, NPTEPG - 1));
5577 va_last = va + NBPDR - PAGE_SIZE;
5579 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5580 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5581 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5582 for (field = 0; field < _NPCM; field++) {
5583 while (pc->pc_map[field]) {
5584 bit = bsfq(pc->pc_map[field]);
5585 pc->pc_map[field] &= ~(1ul << bit);
5586 pv = &pc->pc_pventry[field * 64 + bit];
5590 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5591 ("pmap_pv_demote_pde: page %p is not managed", m));
5592 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5598 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5599 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5602 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5603 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5604 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5606 PV_STAT(counter_u64_add(pv_entry_count, NPTEPG - 1));
5607 PV_STAT(counter_u64_add(pv_entry_spare, -(NPTEPG - 1)));
5610 #if VM_NRESERVLEVEL > 0
5612 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5613 * replace the many pv entries for the 4KB page mappings by a single pv entry
5614 * for the 2MB page mapping.
5617 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5618 struct rwlock **lockp)
5620 struct md_page *pvh;
5622 vm_offset_t va_last;
5625 KASSERT((pa & PDRMASK) == 0,
5626 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5627 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5630 * Transfer the first page's pv entry for this mapping to the 2mpage's
5631 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5632 * a transfer avoids the possibility that get_pv_entry() calls
5633 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5634 * mappings that is being promoted.
5636 m = PHYS_TO_VM_PAGE(pa);
5637 va = trunc_2mpage(va);
5638 pv = pmap_pvh_remove(&m->md, pmap, va);
5639 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5640 pvh = pa_to_pvh(pa);
5641 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5643 /* Free the remaining NPTEPG - 1 pv entries. */
5644 va_last = va + NBPDR - PAGE_SIZE;
5648 pmap_pvh_free(&m->md, pmap, va);
5649 } while (va < va_last);
5651 #endif /* VM_NRESERVLEVEL > 0 */
5654 * First find and then destroy the pv entry for the specified pmap and virtual
5655 * address. This operation can be performed on pv lists for either 4KB or 2MB
5659 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5663 pv = pmap_pvh_remove(pvh, pmap, va);
5664 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5665 free_pv_entry(pmap, pv);
5669 * Conditionally create the PV entry for a 4KB page mapping if the required
5670 * memory can be allocated without resorting to reclamation.
5673 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5674 struct rwlock **lockp)
5678 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5679 /* Pass NULL instead of the lock pointer to disable reclamation. */
5680 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5682 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5683 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5691 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5692 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5693 * false if the PV entry cannot be allocated without resorting to reclamation.
5696 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5697 struct rwlock **lockp)
5699 struct md_page *pvh;
5703 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5704 /* Pass NULL instead of the lock pointer to disable reclamation. */
5705 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5706 NULL : lockp)) == NULL)
5709 pa = pde & PG_PS_FRAME;
5710 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5711 pvh = pa_to_pvh(pa);
5712 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5718 * Fills a page table page with mappings to consecutive physical pages.
5721 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5725 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5727 newpte += PAGE_SIZE;
5732 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5733 * mapping is invalidated.
5736 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5738 struct rwlock *lock;
5742 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5749 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5753 pt_entry_t *xpte, *ypte;
5755 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5756 xpte++, newpte += PAGE_SIZE) {
5757 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5758 printf("pmap_demote_pde: xpte %zd and newpte map "
5759 "different pages: found %#lx, expected %#lx\n",
5760 xpte - firstpte, *xpte, newpte);
5761 printf("page table dump\n");
5762 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5763 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5768 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5769 ("pmap_demote_pde: firstpte and newpte map different physical"
5776 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5777 pd_entry_t oldpde, struct rwlock **lockp)
5779 struct spglist free;
5783 sva = trunc_2mpage(va);
5784 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5785 if ((oldpde & pmap_global_bit(pmap)) == 0)
5786 pmap_invalidate_pde_page(pmap, sva, oldpde);
5787 vm_page_free_pages_toq(&free, true);
5788 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5793 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5794 struct rwlock **lockp)
5796 pd_entry_t newpde, oldpde;
5797 pt_entry_t *firstpte, newpte;
5798 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5804 PG_A = pmap_accessed_bit(pmap);
5805 PG_G = pmap_global_bit(pmap);
5806 PG_M = pmap_modified_bit(pmap);
5807 PG_RW = pmap_rw_bit(pmap);
5808 PG_V = pmap_valid_bit(pmap);
5809 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5810 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5813 in_kernel = va >= VM_MAXUSER_ADDRESS;
5815 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5816 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5819 * Invalidate the 2MB page mapping and return "failure" if the
5820 * mapping was never accessed.
5822 if ((oldpde & PG_A) == 0) {
5823 KASSERT((oldpde & PG_W) == 0,
5824 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5825 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5829 mpte = pmap_remove_pt_page(pmap, va);
5831 KASSERT((oldpde & PG_W) == 0,
5832 ("pmap_demote_pde: page table page for a wired mapping"
5836 * If the page table page is missing and the mapping
5837 * is for a kernel address, the mapping must belong to
5838 * the direct map. Page table pages are preallocated
5839 * for every other part of the kernel address space,
5840 * so the direct map region is the only part of the
5841 * kernel address space that must be handled here.
5843 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5844 va < DMAP_MAX_ADDRESS),
5845 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5848 * If the 2MB page mapping belongs to the direct map
5849 * region of the kernel's address space, then the page
5850 * allocation request specifies the highest possible
5851 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5852 * priority is normal.
5854 mpte = pmap_alloc_pt_page(pmap, pmap_pde_pindex(va),
5855 (in_kernel ? VM_ALLOC_INTERRUPT : 0) | VM_ALLOC_WIRED);
5858 * If the allocation of the new page table page fails,
5859 * invalidate the 2MB page mapping and return "failure".
5862 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5867 mpte->ref_count = NPTEPG;
5869 mptepa = VM_PAGE_TO_PHYS(mpte);
5870 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5871 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5872 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5873 ("pmap_demote_pde: oldpde is missing PG_M"));
5874 newpte = oldpde & ~PG_PS;
5875 newpte = pmap_swap_pat(pmap, newpte);
5878 * If the page table page is not leftover from an earlier promotion,
5881 if (mpte->valid == 0)
5882 pmap_fill_ptp(firstpte, newpte);
5884 pmap_demote_pde_check(firstpte, newpte);
5887 * If the mapping has changed attributes, update the page table
5890 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5891 pmap_fill_ptp(firstpte, newpte);
5894 * The spare PV entries must be reserved prior to demoting the
5895 * mapping, that is, prior to changing the PDE. Otherwise, the state
5896 * of the PDE and the PV lists will be inconsistent, which can result
5897 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5898 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5899 * PV entry for the 2MB page mapping that is being demoted.
5901 if ((oldpde & PG_MANAGED) != 0)
5902 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5905 * Demote the mapping. This pmap is locked. The old PDE has
5906 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5907 * set. Thus, there is no danger of a race with another
5908 * processor changing the setting of PG_A and/or PG_M between
5909 * the read above and the store below.
5911 if (workaround_erratum383)
5912 pmap_update_pde(pmap, va, pde, newpde);
5914 pde_store(pde, newpde);
5917 * Invalidate a stale recursive mapping of the page table page.
5920 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5923 * Demote the PV entry.
5925 if ((oldpde & PG_MANAGED) != 0)
5926 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5928 counter_u64_add(pmap_pde_demotions, 1);
5929 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5935 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5938 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5944 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5945 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5946 mpte = pmap_remove_pt_page(pmap, va);
5948 panic("pmap_remove_kernel_pde: Missing pt page.");
5950 mptepa = VM_PAGE_TO_PHYS(mpte);
5951 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5954 * If this page table page was unmapped by a promotion, then it
5955 * contains valid mappings. Zero it to invalidate those mappings.
5957 if (mpte->valid != 0)
5958 pagezero((void *)PHYS_TO_DMAP(mptepa));
5961 * Demote the mapping.
5963 if (workaround_erratum383)
5964 pmap_update_pde(pmap, va, pde, newpde);
5966 pde_store(pde, newpde);
5969 * Invalidate a stale recursive mapping of the page table page.
5971 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5975 * pmap_remove_pde: do the things to unmap a superpage in a process
5978 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5979 struct spglist *free, struct rwlock **lockp)
5981 struct md_page *pvh;
5983 vm_offset_t eva, va;
5985 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5987 PG_G = pmap_global_bit(pmap);
5988 PG_A = pmap_accessed_bit(pmap);
5989 PG_M = pmap_modified_bit(pmap);
5990 PG_RW = pmap_rw_bit(pmap);
5992 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5993 KASSERT((sva & PDRMASK) == 0,
5994 ("pmap_remove_pde: sva is not 2mpage aligned"));
5995 oldpde = pte_load_clear(pdq);
5997 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5998 if ((oldpde & PG_G) != 0)
5999 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6000 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
6001 if (oldpde & PG_MANAGED) {
6002 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
6003 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
6004 pmap_pvh_free(pvh, pmap, sva);
6006 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6007 va < eva; va += PAGE_SIZE, m++) {
6008 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
6011 vm_page_aflag_set(m, PGA_REFERENCED);
6012 if (TAILQ_EMPTY(&m->md.pv_list) &&
6013 TAILQ_EMPTY(&pvh->pv_list))
6014 vm_page_aflag_clear(m, PGA_WRITEABLE);
6015 pmap_delayed_invl_page(m);
6018 if (pmap == kernel_pmap) {
6019 pmap_remove_kernel_pde(pmap, pdq, sva);
6021 mpte = pmap_remove_pt_page(pmap, sva);
6023 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6024 ("pmap_remove_pde: pte page not promoted"));
6025 pmap_resident_count_adj(pmap, -1);
6026 KASSERT(mpte->ref_count == NPTEPG,
6027 ("pmap_remove_pde: pte page ref count error"));
6028 mpte->ref_count = 0;
6029 pmap_add_delayed_free_list(mpte, free, FALSE);
6032 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
6036 * pmap_remove_pte: do the things to unmap a page in a process
6039 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
6040 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
6042 struct md_page *pvh;
6043 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
6046 PG_A = pmap_accessed_bit(pmap);
6047 PG_M = pmap_modified_bit(pmap);
6048 PG_RW = pmap_rw_bit(pmap);
6050 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6051 oldpte = pte_load_clear(ptq);
6053 pmap->pm_stats.wired_count -= 1;
6054 pmap_resident_count_adj(pmap, -1);
6055 if (oldpte & PG_MANAGED) {
6056 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
6057 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6060 vm_page_aflag_set(m, PGA_REFERENCED);
6061 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
6062 pmap_pvh_free(&m->md, pmap, va);
6063 if (TAILQ_EMPTY(&m->md.pv_list) &&
6064 (m->flags & PG_FICTITIOUS) == 0) {
6065 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6066 if (TAILQ_EMPTY(&pvh->pv_list))
6067 vm_page_aflag_clear(m, PGA_WRITEABLE);
6069 pmap_delayed_invl_page(m);
6071 return (pmap_unuse_pt(pmap, va, ptepde, free));
6075 * Remove a single page from a process address space
6078 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
6079 struct spglist *free)
6081 struct rwlock *lock;
6082 pt_entry_t *pte, PG_V;
6084 PG_V = pmap_valid_bit(pmap);
6085 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6086 if ((*pde & PG_V) == 0)
6088 pte = pmap_pde_to_pte(pde, va);
6089 if ((*pte & PG_V) == 0)
6092 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
6095 pmap_invalidate_page(pmap, va);
6099 * Removes the specified range of addresses from the page table page.
6102 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
6103 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
6105 pt_entry_t PG_G, *pte;
6109 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6110 PG_G = pmap_global_bit(pmap);
6113 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
6117 pmap_invalidate_range(pmap, va, sva);
6122 if ((*pte & PG_G) == 0)
6126 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
6132 pmap_invalidate_range(pmap, va, sva);
6137 * Remove the given range of addresses from the specified map.
6139 * It is assumed that the start and end are properly
6140 * rounded to the page size.
6143 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6145 struct rwlock *lock;
6147 vm_offset_t va_next;
6148 pml5_entry_t *pml5e;
6149 pml4_entry_t *pml4e;
6151 pd_entry_t ptpaddr, *pde;
6152 pt_entry_t PG_G, PG_V;
6153 struct spglist free;
6156 PG_G = pmap_global_bit(pmap);
6157 PG_V = pmap_valid_bit(pmap);
6160 * If there are no resident pages besides the top level page
6161 * table page(s), there is nothing to do. Kernel pmap always
6162 * accounts whole preloaded area as resident, which makes its
6163 * resident count > 2.
6164 * Perform an unsynchronized read. This is, however, safe.
6166 if (pmap->pm_stats.resident_count <= 1 + (pmap->pm_pmltopu != NULL ?
6173 pmap_delayed_invl_start();
6175 pmap_pkru_on_remove(pmap, sva, eva);
6178 * special handling of removing one page. a very
6179 * common operation and easy to short circuit some
6182 if (sva + PAGE_SIZE == eva) {
6183 pde = pmap_pde(pmap, sva);
6184 if (pde && (*pde & PG_PS) == 0) {
6185 pmap_remove_page(pmap, sva, pde, &free);
6191 for (; sva < eva; sva = va_next) {
6192 if (pmap->pm_stats.resident_count == 0)
6195 if (pmap_is_la57(pmap)) {
6196 pml5e = pmap_pml5e(pmap, sva);
6197 if ((*pml5e & PG_V) == 0) {
6198 va_next = (sva + NBPML5) & ~PML5MASK;
6203 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
6205 pml4e = pmap_pml4e(pmap, sva);
6207 if ((*pml4e & PG_V) == 0) {
6208 va_next = (sva + NBPML4) & ~PML4MASK;
6214 va_next = (sva + NBPDP) & ~PDPMASK;
6217 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6218 if ((*pdpe & PG_V) == 0)
6220 if ((*pdpe & PG_PS) != 0) {
6221 KASSERT(va_next <= eva,
6222 ("partial update of non-transparent 1G mapping "
6223 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6224 *pdpe, sva, eva, va_next));
6225 MPASS(pmap != kernel_pmap); /* XXXKIB */
6226 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
6229 pmap_resident_count_adj(pmap, -NBPDP / PAGE_SIZE);
6230 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
6231 pmap_unwire_ptp(pmap, sva, mt, &free);
6236 * Calculate index for next page table.
6238 va_next = (sva + NBPDR) & ~PDRMASK;
6242 pde = pmap_pdpe_to_pde(pdpe, sva);
6246 * Weed out invalid mappings.
6252 * Check for large page.
6254 if ((ptpaddr & PG_PS) != 0) {
6256 * Are we removing the entire large page? If not,
6257 * demote the mapping and fall through.
6259 if (sva + NBPDR == va_next && eva >= va_next) {
6261 * The TLB entry for a PG_G mapping is
6262 * invalidated by pmap_remove_pde().
6264 if ((ptpaddr & PG_G) == 0)
6266 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6268 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6270 /* The large page mapping was destroyed. */
6277 * Limit our scan to either the end of the va represented
6278 * by the current page table page, or to the end of the
6279 * range being removed.
6284 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6291 pmap_invalidate_all(pmap);
6293 pmap_delayed_invl_finish();
6294 vm_page_free_pages_toq(&free, true);
6298 * Routine: pmap_remove_all
6300 * Removes this physical page from
6301 * all physical maps in which it resides.
6302 * Reflects back modify bits to the pager.
6305 * Original versions of this routine were very
6306 * inefficient because they iteratively called
6307 * pmap_remove (slow...)
6311 pmap_remove_all(vm_page_t m)
6313 struct md_page *pvh;
6316 struct rwlock *lock;
6317 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6320 struct spglist free;
6321 int pvh_gen, md_gen;
6323 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6324 ("pmap_remove_all: page %p is not managed", m));
6326 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6327 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6328 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6331 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6333 if (!PMAP_TRYLOCK(pmap)) {
6334 pvh_gen = pvh->pv_gen;
6338 if (pvh_gen != pvh->pv_gen) {
6344 pde = pmap_pde(pmap, va);
6345 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6348 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6350 if (!PMAP_TRYLOCK(pmap)) {
6351 pvh_gen = pvh->pv_gen;
6352 md_gen = m->md.pv_gen;
6356 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6361 PG_A = pmap_accessed_bit(pmap);
6362 PG_M = pmap_modified_bit(pmap);
6363 PG_RW = pmap_rw_bit(pmap);
6364 pmap_resident_count_adj(pmap, -1);
6365 pde = pmap_pde(pmap, pv->pv_va);
6366 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6367 " a 2mpage in page %p's pv list", m));
6368 pte = pmap_pde_to_pte(pde, pv->pv_va);
6369 tpte = pte_load_clear(pte);
6371 pmap->pm_stats.wired_count--;
6373 vm_page_aflag_set(m, PGA_REFERENCED);
6376 * Update the vm_page_t clean and reference bits.
6378 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6380 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6381 pmap_invalidate_page(pmap, pv->pv_va);
6382 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6384 free_pv_entry(pmap, pv);
6387 vm_page_aflag_clear(m, PGA_WRITEABLE);
6389 pmap_delayed_invl_wait(m);
6390 vm_page_free_pages_toq(&free, true);
6394 * pmap_protect_pde: do the things to protect a 2mpage in a process
6397 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6399 pd_entry_t newpde, oldpde;
6401 boolean_t anychanged;
6402 pt_entry_t PG_G, PG_M, PG_RW;
6404 PG_G = pmap_global_bit(pmap);
6405 PG_M = pmap_modified_bit(pmap);
6406 PG_RW = pmap_rw_bit(pmap);
6408 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6409 KASSERT((sva & PDRMASK) == 0,
6410 ("pmap_protect_pde: sva is not 2mpage aligned"));
6413 oldpde = newpde = *pde;
6414 if ((prot & VM_PROT_WRITE) == 0) {
6415 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6416 (PG_MANAGED | PG_M | PG_RW)) {
6417 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6418 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6421 newpde &= ~(PG_RW | PG_M);
6423 if ((prot & VM_PROT_EXECUTE) == 0)
6425 if (newpde != oldpde) {
6427 * As an optimization to future operations on this PDE, clear
6428 * PG_PROMOTED. The impending invalidation will remove any
6429 * lingering 4KB page mappings from the TLB.
6431 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6433 if ((oldpde & PG_G) != 0)
6434 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6438 return (anychanged);
6442 * Set the physical protection on the
6443 * specified range of this map as requested.
6446 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6449 vm_offset_t va_next;
6450 pml4_entry_t *pml4e;
6452 pd_entry_t ptpaddr, *pde;
6453 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6454 pt_entry_t obits, pbits;
6455 boolean_t anychanged;
6457 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6458 if (prot == VM_PROT_NONE) {
6459 pmap_remove(pmap, sva, eva);
6463 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6464 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6467 PG_G = pmap_global_bit(pmap);
6468 PG_M = pmap_modified_bit(pmap);
6469 PG_V = pmap_valid_bit(pmap);
6470 PG_RW = pmap_rw_bit(pmap);
6474 * Although this function delays and batches the invalidation
6475 * of stale TLB entries, it does not need to call
6476 * pmap_delayed_invl_start() and
6477 * pmap_delayed_invl_finish(), because it does not
6478 * ordinarily destroy mappings. Stale TLB entries from
6479 * protection-only changes need only be invalidated before the
6480 * pmap lock is released, because protection-only changes do
6481 * not destroy PV entries. Even operations that iterate over
6482 * a physical page's PV list of mappings, like
6483 * pmap_remove_write(), acquire the pmap lock for each
6484 * mapping. Consequently, for protection-only changes, the
6485 * pmap lock suffices to synchronize both page table and TLB
6488 * This function only destroys a mapping if pmap_demote_pde()
6489 * fails. In that case, stale TLB entries are immediately
6494 for (; sva < eva; sva = va_next) {
6495 pml4e = pmap_pml4e(pmap, sva);
6496 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6497 va_next = (sva + NBPML4) & ~PML4MASK;
6503 va_next = (sva + NBPDP) & ~PDPMASK;
6506 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6507 if ((*pdpe & PG_V) == 0)
6509 if ((*pdpe & PG_PS) != 0) {
6510 KASSERT(va_next <= eva,
6511 ("partial update of non-transparent 1G mapping "
6512 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6513 *pdpe, sva, eva, va_next));
6515 obits = pbits = *pdpe;
6516 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6517 MPASS(pmap != kernel_pmap); /* XXXKIB */
6518 if ((prot & VM_PROT_WRITE) == 0)
6519 pbits &= ~(PG_RW | PG_M);
6520 if ((prot & VM_PROT_EXECUTE) == 0)
6523 if (pbits != obits) {
6524 if (!atomic_cmpset_long(pdpe, obits, pbits))
6525 /* PG_PS cannot be cleared under us, */
6532 va_next = (sva + NBPDR) & ~PDRMASK;
6536 pde = pmap_pdpe_to_pde(pdpe, sva);
6540 * Weed out invalid mappings.
6546 * Check for large page.
6548 if ((ptpaddr & PG_PS) != 0) {
6550 * Are we protecting the entire large page? If not,
6551 * demote the mapping and fall through.
6553 if (sva + NBPDR == va_next && eva >= va_next) {
6555 * The TLB entry for a PG_G mapping is
6556 * invalidated by pmap_protect_pde().
6558 if (pmap_protect_pde(pmap, pde, sva, prot))
6561 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6563 * The large page mapping was destroyed.
6572 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6575 obits = pbits = *pte;
6576 if ((pbits & PG_V) == 0)
6579 if ((prot & VM_PROT_WRITE) == 0) {
6580 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6581 (PG_MANAGED | PG_M | PG_RW)) {
6582 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6585 pbits &= ~(PG_RW | PG_M);
6587 if ((prot & VM_PROT_EXECUTE) == 0)
6590 if (pbits != obits) {
6591 if (!atomic_cmpset_long(pte, obits, pbits))
6594 pmap_invalidate_page(pmap, sva);
6601 pmap_invalidate_all(pmap);
6605 #if VM_NRESERVLEVEL > 0
6607 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6610 if (pmap->pm_type != PT_EPT)
6612 return ((pde & EPT_PG_EXECUTE) != 0);
6616 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6617 * single page table page (PTP) to a single 2MB page mapping. For promotion
6618 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6619 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6620 * identical characteristics.
6623 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6624 struct rwlock **lockp)
6627 pt_entry_t *firstpte, oldpte, pa, *pte;
6628 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6632 PG_A = pmap_accessed_bit(pmap);
6633 PG_G = pmap_global_bit(pmap);
6634 PG_M = pmap_modified_bit(pmap);
6635 PG_V = pmap_valid_bit(pmap);
6636 PG_RW = pmap_rw_bit(pmap);
6637 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6638 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6640 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6643 * Examine the first PTE in the specified PTP. Abort if this PTE is
6644 * either invalid, unused, or does not map the first 4KB physical page
6645 * within a 2MB page.
6647 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6649 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6650 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6652 counter_u64_add(pmap_pde_p_failures, 1);
6653 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6654 " in pmap %p", va, pmap);
6658 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6660 * When PG_M is already clear, PG_RW can be cleared without
6661 * a TLB invalidation.
6663 if (!atomic_fcmpset_long(firstpte, &newpde, newpde & ~PG_RW))
6669 * Examine each of the other PTEs in the specified PTP. Abort if this
6670 * PTE maps an unexpected 4KB physical page or does not have identical
6671 * characteristics to the first PTE.
6673 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6674 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6676 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6677 counter_u64_add(pmap_pde_p_failures, 1);
6678 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6679 " in pmap %p", va, pmap);
6683 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6685 * When PG_M is already clear, PG_RW can be cleared
6686 * without a TLB invalidation.
6688 if (!atomic_fcmpset_long(pte, &oldpte, oldpte & ~PG_RW))
6691 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6692 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6693 (va & ~PDRMASK), pmap);
6695 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6696 counter_u64_add(pmap_pde_p_failures, 1);
6697 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6698 " in pmap %p", va, pmap);
6705 * Save the page table page in its current state until the PDE
6706 * mapping the superpage is demoted by pmap_demote_pde() or
6707 * destroyed by pmap_remove_pde().
6709 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6710 KASSERT(mpte >= vm_page_array &&
6711 mpte < &vm_page_array[vm_page_array_size],
6712 ("pmap_promote_pde: page table page is out of range"));
6713 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6714 ("pmap_promote_pde: page table page's pindex is wrong "
6715 "mpte %p pidx %#lx va %#lx va pde pidx %#lx",
6716 mpte, mpte->pindex, va, pmap_pde_pindex(va)));
6717 if (pmap_insert_pt_page(pmap, mpte, true)) {
6718 counter_u64_add(pmap_pde_p_failures, 1);
6720 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6726 * Promote the pv entries.
6728 if ((newpde & PG_MANAGED) != 0)
6729 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6732 * Propagate the PAT index to its proper position.
6734 newpde = pmap_swap_pat(pmap, newpde);
6737 * Map the superpage.
6739 if (workaround_erratum383)
6740 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6742 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6744 counter_u64_add(pmap_pde_promotions, 1);
6745 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6746 " in pmap %p", va, pmap);
6748 #endif /* VM_NRESERVLEVEL > 0 */
6751 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6755 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6757 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6758 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6759 ("psind %d unexpected", psind));
6760 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6761 ("unaligned phys address %#lx newpte %#lx psind %d",
6762 newpte & PG_FRAME, newpte, psind));
6763 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6764 ("unaligned va %#lx psind %d", va, psind));
6765 KASSERT(va < VM_MAXUSER_ADDRESS,
6766 ("kernel mode non-transparent superpage")); /* XXXKIB */
6767 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6768 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6770 PG_V = pmap_valid_bit(pmap);
6773 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6774 return (KERN_PROTECTION_FAILURE);
6776 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6777 pten |= pmap_pkru_get(pmap, va);
6779 if (psind == 2) { /* 1G */
6780 pml4e = pmap_pml4e(pmap, va);
6781 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6782 mp = pmap_allocpte_alloc(pmap, pmap_pml4e_pindex(va),
6786 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6787 pdpe = &pdpe[pmap_pdpe_index(va)];
6789 MPASS(origpte == 0);
6791 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6792 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6794 if ((origpte & PG_V) == 0) {
6795 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6800 } else /* (psind == 1) */ { /* 2M */
6801 pde = pmap_pde(pmap, va);
6803 mp = pmap_allocpte_alloc(pmap, pmap_pdpe_pindex(va),
6807 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6808 pde = &pde[pmap_pde_index(va)];
6810 MPASS(origpte == 0);
6813 if ((origpte & PG_V) == 0) {
6814 pdpe = pmap_pdpe(pmap, va);
6815 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6816 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6822 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6823 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6824 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6825 va, psind == 2 ? "1G" : "2M", origpte, pten));
6826 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6827 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6828 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6829 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6830 if ((origpte & PG_V) == 0)
6831 pmap_resident_count_adj(pmap, pagesizes[psind] / PAGE_SIZE);
6833 return (KERN_SUCCESS);
6836 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6837 return (KERN_RESOURCE_SHORTAGE);
6845 * Insert the given physical page (p) at
6846 * the specified virtual address (v) in the
6847 * target physical map with the protection requested.
6849 * If specified, the page will be wired down, meaning
6850 * that the related pte can not be reclaimed.
6852 * NB: This is the only routine which MAY NOT lazy-evaluate
6853 * or lose information. That is, this routine must actually
6854 * insert this page into the given map NOW.
6856 * When destroying both a page table and PV entry, this function
6857 * performs the TLB invalidation before releasing the PV list
6858 * lock, so we do not need pmap_delayed_invl_page() calls here.
6861 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6862 u_int flags, int8_t psind)
6864 struct rwlock *lock;
6866 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6867 pt_entry_t newpte, origpte;
6874 PG_A = pmap_accessed_bit(pmap);
6875 PG_G = pmap_global_bit(pmap);
6876 PG_M = pmap_modified_bit(pmap);
6877 PG_V = pmap_valid_bit(pmap);
6878 PG_RW = pmap_rw_bit(pmap);
6880 va = trunc_page(va);
6881 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6882 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6883 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6885 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6886 va >= kmi.clean_eva,
6887 ("pmap_enter: managed mapping within the clean submap"));
6888 if ((m->oflags & VPO_UNMANAGED) == 0)
6889 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6890 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6891 ("pmap_enter: flags %u has reserved bits set", flags));
6892 pa = VM_PAGE_TO_PHYS(m);
6893 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6894 if ((flags & VM_PROT_WRITE) != 0)
6896 if ((prot & VM_PROT_WRITE) != 0)
6898 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6899 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6900 if ((prot & VM_PROT_EXECUTE) == 0)
6902 if ((flags & PMAP_ENTER_WIRED) != 0)
6904 if (va < VM_MAXUSER_ADDRESS)
6906 if (pmap == kernel_pmap)
6908 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6911 * Set modified bit gratuitously for writeable mappings if
6912 * the page is unmanaged. We do not want to take a fault
6913 * to do the dirty bit accounting for these mappings.
6915 if ((m->oflags & VPO_UNMANAGED) != 0) {
6916 if ((newpte & PG_RW) != 0)
6919 newpte |= PG_MANAGED;
6923 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6924 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6925 ("managed largepage va %#lx flags %#x", va, flags));
6926 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6931 /* Assert the required virtual and physical alignment. */
6932 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6933 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6934 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6940 * In the case that a page table page is not
6941 * resident, we are creating it here.
6944 pde = pmap_pde(pmap, va);
6945 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6946 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6947 pte = pmap_pde_to_pte(pde, va);
6948 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6949 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6952 } else if (va < VM_MAXUSER_ADDRESS) {
6954 * Here if the pte page isn't mapped, or if it has been
6957 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6958 mpte = pmap_allocpte_alloc(pmap, pmap_pde_pindex(va),
6959 nosleep ? NULL : &lock, va);
6960 if (mpte == NULL && nosleep) {
6961 rv = KERN_RESOURCE_SHORTAGE;
6966 panic("pmap_enter: invalid page directory va=%#lx", va);
6970 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6971 newpte |= pmap_pkru_get(pmap, va);
6974 * Is the specified virtual address already mapped?
6976 if ((origpte & PG_V) != 0) {
6978 * Wiring change, just update stats. We don't worry about
6979 * wiring PT pages as they remain resident as long as there
6980 * are valid mappings in them. Hence, if a user page is wired,
6981 * the PT page will be also.
6983 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6984 pmap->pm_stats.wired_count++;
6985 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6986 pmap->pm_stats.wired_count--;
6989 * Remove the extra PT page reference.
6993 KASSERT(mpte->ref_count > 0,
6994 ("pmap_enter: missing reference to page table page,"
6999 * Has the physical page changed?
7001 opa = origpte & PG_FRAME;
7004 * No, might be a protection or wiring change.
7006 if ((origpte & PG_MANAGED) != 0 &&
7007 (newpte & PG_RW) != 0)
7008 vm_page_aflag_set(m, PGA_WRITEABLE);
7009 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
7015 * The physical page has changed. Temporarily invalidate
7016 * the mapping. This ensures that all threads sharing the
7017 * pmap keep a consistent view of the mapping, which is
7018 * necessary for the correct handling of COW faults. It
7019 * also permits reuse of the old mapping's PV entry,
7020 * avoiding an allocation.
7022 * For consistency, handle unmanaged mappings the same way.
7024 origpte = pte_load_clear(pte);
7025 KASSERT((origpte & PG_FRAME) == opa,
7026 ("pmap_enter: unexpected pa update for %#lx", va));
7027 if ((origpte & PG_MANAGED) != 0) {
7028 om = PHYS_TO_VM_PAGE(opa);
7031 * The pmap lock is sufficient to synchronize with
7032 * concurrent calls to pmap_page_test_mappings() and
7033 * pmap_ts_referenced().
7035 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7037 if ((origpte & PG_A) != 0) {
7038 pmap_invalidate_page(pmap, va);
7039 vm_page_aflag_set(om, PGA_REFERENCED);
7041 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
7042 pv = pmap_pvh_remove(&om->md, pmap, va);
7044 ("pmap_enter: no PV entry for %#lx", va));
7045 if ((newpte & PG_MANAGED) == 0)
7046 free_pv_entry(pmap, pv);
7047 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
7048 TAILQ_EMPTY(&om->md.pv_list) &&
7049 ((om->flags & PG_FICTITIOUS) != 0 ||
7050 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
7051 vm_page_aflag_clear(om, PGA_WRITEABLE);
7054 * Since this mapping is unmanaged, assume that PG_A
7057 pmap_invalidate_page(pmap, va);
7062 * Increment the counters.
7064 if ((newpte & PG_W) != 0)
7065 pmap->pm_stats.wired_count++;
7066 pmap_resident_count_adj(pmap, 1);
7070 * Enter on the PV list if part of our managed memory.
7072 if ((newpte & PG_MANAGED) != 0) {
7074 pv = get_pv_entry(pmap, &lock);
7077 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
7078 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7080 if ((newpte & PG_RW) != 0)
7081 vm_page_aflag_set(m, PGA_WRITEABLE);
7087 if ((origpte & PG_V) != 0) {
7089 origpte = pte_load_store(pte, newpte);
7090 KASSERT((origpte & PG_FRAME) == pa,
7091 ("pmap_enter: unexpected pa update for %#lx", va));
7092 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
7094 if ((origpte & PG_MANAGED) != 0)
7098 * Although the PTE may still have PG_RW set, TLB
7099 * invalidation may nonetheless be required because
7100 * the PTE no longer has PG_M set.
7102 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
7104 * This PTE change does not require TLB invalidation.
7108 if ((origpte & PG_A) != 0)
7109 pmap_invalidate_page(pmap, va);
7111 pte_store(pte, newpte);
7115 #if VM_NRESERVLEVEL > 0
7117 * If both the page table page and the reservation are fully
7118 * populated, then attempt promotion.
7120 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
7121 pmap_ps_enabled(pmap) &&
7122 (m->flags & PG_FICTITIOUS) == 0 &&
7123 vm_reserv_level_iffullpop(m) == 0)
7124 pmap_promote_pde(pmap, pde, va, &lock);
7136 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
7137 * if successful. Returns false if (1) a page table page cannot be allocated
7138 * without sleeping, (2) a mapping already exists at the specified virtual
7139 * address, or (3) a PV entry cannot be allocated without reclaiming another
7143 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
7144 struct rwlock **lockp)
7149 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7150 PG_V = pmap_valid_bit(pmap);
7151 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
7153 if ((m->oflags & VPO_UNMANAGED) == 0)
7154 newpde |= PG_MANAGED;
7155 if ((prot & VM_PROT_EXECUTE) == 0)
7157 if (va < VM_MAXUSER_ADDRESS)
7159 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
7160 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
7165 * Returns true if every page table entry in the specified page table page is
7169 pmap_every_pte_zero(vm_paddr_t pa)
7171 pt_entry_t *pt_end, *pte;
7173 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
7174 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
7175 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
7183 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
7184 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
7185 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
7186 * a mapping already exists at the specified virtual address. Returns
7187 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
7188 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
7189 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
7191 * The parameter "m" is only used when creating a managed, writeable mapping.
7194 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
7195 vm_page_t m, struct rwlock **lockp)
7197 struct spglist free;
7198 pd_entry_t oldpde, *pde;
7199 pt_entry_t PG_G, PG_RW, PG_V;
7202 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
7203 ("pmap_enter_pde: cannot create wired user mapping"));
7204 PG_G = pmap_global_bit(pmap);
7205 PG_RW = pmap_rw_bit(pmap);
7206 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
7207 ("pmap_enter_pde: newpde is missing PG_M"));
7208 PG_V = pmap_valid_bit(pmap);
7209 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7211 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
7213 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
7214 " in pmap %p", va, pmap);
7215 return (KERN_FAILURE);
7217 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
7218 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
7219 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7220 " in pmap %p", va, pmap);
7221 return (KERN_RESOURCE_SHORTAGE);
7225 * If pkru is not same for the whole pde range, return failure
7226 * and let vm_fault() cope. Check after pde allocation, since
7229 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
7230 pmap_abort_ptp(pmap, va, pdpg);
7231 return (KERN_FAILURE);
7233 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
7234 newpde &= ~X86_PG_PKU_MASK;
7235 newpde |= pmap_pkru_get(pmap, va);
7239 * If there are existing mappings, either abort or remove them.
7242 if ((oldpde & PG_V) != 0) {
7243 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
7244 ("pmap_enter_pde: pdpg's reference count is too low"));
7245 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
7246 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
7247 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
7250 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7251 " in pmap %p", va, pmap);
7252 return (KERN_FAILURE);
7254 /* Break the existing mapping(s). */
7256 if ((oldpde & PG_PS) != 0) {
7258 * The reference to the PD page that was acquired by
7259 * pmap_alloc_pde() ensures that it won't be freed.
7260 * However, if the PDE resulted from a promotion, then
7261 * a reserved PT page could be freed.
7263 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
7264 if ((oldpde & PG_G) == 0)
7265 pmap_invalidate_pde_page(pmap, va, oldpde);
7267 pmap_delayed_invl_start();
7268 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7270 pmap_invalidate_all(pmap);
7271 pmap_delayed_invl_finish();
7273 if (va < VM_MAXUSER_ADDRESS) {
7274 vm_page_free_pages_toq(&free, true);
7275 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7278 KASSERT(SLIST_EMPTY(&free),
7279 ("pmap_enter_pde: freed kernel page table page"));
7282 * Both pmap_remove_pde() and pmap_remove_ptes() will
7283 * leave the kernel page table page zero filled.
7285 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7286 if (pmap_insert_pt_page(pmap, mt, false))
7287 panic("pmap_enter_pde: trie insert failed");
7291 if ((newpde & PG_MANAGED) != 0) {
7293 * Abort this mapping if its PV entry could not be created.
7295 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7297 pmap_abort_ptp(pmap, va, pdpg);
7298 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7299 " in pmap %p", va, pmap);
7300 return (KERN_RESOURCE_SHORTAGE);
7302 if ((newpde & PG_RW) != 0) {
7303 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7304 vm_page_aflag_set(mt, PGA_WRITEABLE);
7309 * Increment counters.
7311 if ((newpde & PG_W) != 0)
7312 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7313 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7316 * Map the superpage. (This is not a promoted mapping; there will not
7317 * be any lingering 4KB page mappings in the TLB.)
7319 pde_store(pde, newpde);
7321 counter_u64_add(pmap_pde_mappings, 1);
7322 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7324 return (KERN_SUCCESS);
7328 * Maps a sequence of resident pages belonging to the same object.
7329 * The sequence begins with the given page m_start. This page is
7330 * mapped at the given virtual address start. Each subsequent page is
7331 * mapped at a virtual address that is offset from start by the same
7332 * amount as the page is offset from m_start within the object. The
7333 * last page in the sequence is the page with the largest offset from
7334 * m_start that can be mapped at a virtual address less than the given
7335 * virtual address end. Not every virtual page between start and end
7336 * is mapped; only those for which a resident page exists with the
7337 * corresponding offset from m_start are mapped.
7340 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7341 vm_page_t m_start, vm_prot_t prot)
7343 struct rwlock *lock;
7346 vm_pindex_t diff, psize;
7348 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7350 psize = atop(end - start);
7355 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7356 va = start + ptoa(diff);
7357 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7358 m->psind == 1 && pmap_ps_enabled(pmap) &&
7359 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7360 m = &m[NBPDR / PAGE_SIZE - 1];
7362 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7364 m = TAILQ_NEXT(m, listq);
7372 * this code makes some *MAJOR* assumptions:
7373 * 1. Current pmap & pmap exists.
7376 * 4. No page table pages.
7377 * but is *MUCH* faster than pmap_enter...
7381 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7383 struct rwlock *lock;
7387 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7394 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7395 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7397 pt_entry_t newpte, *pte, PG_V;
7399 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7400 (m->oflags & VPO_UNMANAGED) != 0,
7401 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7402 PG_V = pmap_valid_bit(pmap);
7403 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7406 * In the case that a page table page is not
7407 * resident, we are creating it here.
7409 if (va < VM_MAXUSER_ADDRESS) {
7410 vm_pindex_t ptepindex;
7414 * Calculate pagetable page index
7416 ptepindex = pmap_pde_pindex(va);
7417 if (mpte && (mpte->pindex == ptepindex)) {
7421 * Get the page directory entry
7423 ptepa = pmap_pde(pmap, va);
7426 * If the page table page is mapped, we just increment
7427 * the hold count, and activate it. Otherwise, we
7428 * attempt to allocate a page table page. If this
7429 * attempt fails, we don't retry. Instead, we give up.
7431 if (ptepa && (*ptepa & PG_V) != 0) {
7434 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7438 * Pass NULL instead of the PV list lock
7439 * pointer, because we don't intend to sleep.
7441 mpte = pmap_allocpte_alloc(pmap, ptepindex,
7447 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7448 pte = &pte[pmap_pte_index(va)];
7460 * Enter on the PV list if part of our managed memory.
7462 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7463 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7465 pmap_abort_ptp(pmap, va, mpte);
7470 * Increment counters
7472 pmap_resident_count_adj(pmap, 1);
7474 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7475 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7476 if ((m->oflags & VPO_UNMANAGED) == 0)
7477 newpte |= PG_MANAGED;
7478 if ((prot & VM_PROT_EXECUTE) == 0)
7480 if (va < VM_MAXUSER_ADDRESS)
7481 newpte |= PG_U | pmap_pkru_get(pmap, va);
7482 pte_store(pte, newpte);
7487 * Make a temporary mapping for a physical address. This is only intended
7488 * to be used for panic dumps.
7491 pmap_kenter_temporary(vm_paddr_t pa, int i)
7495 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7496 pmap_kenter(va, pa);
7498 return ((void *)crashdumpmap);
7502 * This code maps large physical mmap regions into the
7503 * processor address space. Note that some shortcuts
7504 * are taken, but the code works.
7507 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7508 vm_pindex_t pindex, vm_size_t size)
7511 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7512 vm_paddr_t pa, ptepa;
7516 PG_A = pmap_accessed_bit(pmap);
7517 PG_M = pmap_modified_bit(pmap);
7518 PG_V = pmap_valid_bit(pmap);
7519 PG_RW = pmap_rw_bit(pmap);
7521 VM_OBJECT_ASSERT_WLOCKED(object);
7522 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7523 ("pmap_object_init_pt: non-device object"));
7524 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7525 if (!pmap_ps_enabled(pmap))
7527 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7529 p = vm_page_lookup(object, pindex);
7530 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7531 ("pmap_object_init_pt: invalid page %p", p));
7532 pat_mode = p->md.pat_mode;
7535 * Abort the mapping if the first page is not physically
7536 * aligned to a 2MB page boundary.
7538 ptepa = VM_PAGE_TO_PHYS(p);
7539 if (ptepa & (NBPDR - 1))
7543 * Skip the first page. Abort the mapping if the rest of
7544 * the pages are not physically contiguous or have differing
7545 * memory attributes.
7547 p = TAILQ_NEXT(p, listq);
7548 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7550 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7551 ("pmap_object_init_pt: invalid page %p", p));
7552 if (pa != VM_PAGE_TO_PHYS(p) ||
7553 pat_mode != p->md.pat_mode)
7555 p = TAILQ_NEXT(p, listq);
7559 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7560 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7561 * will not affect the termination of this loop.
7564 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7565 pa < ptepa + size; pa += NBPDR) {
7566 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7569 * The creation of mappings below is only an
7570 * optimization. If a page directory page
7571 * cannot be allocated without blocking,
7572 * continue on to the next mapping rather than
7578 if ((*pde & PG_V) == 0) {
7579 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7580 PG_U | PG_RW | PG_V);
7581 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7582 counter_u64_add(pmap_pde_mappings, 1);
7584 /* Continue on if the PDE is already valid. */
7586 KASSERT(pdpg->ref_count > 0,
7587 ("pmap_object_init_pt: missing reference "
7588 "to page directory page, va: 0x%lx", addr));
7597 * Clear the wired attribute from the mappings for the specified range of
7598 * addresses in the given pmap. Every valid mapping within that range
7599 * must have the wired attribute set. In contrast, invalid mappings
7600 * cannot have the wired attribute set, so they are ignored.
7602 * The wired attribute of the page table entry is not a hardware
7603 * feature, so there is no need to invalidate any TLB entries.
7604 * Since pmap_demote_pde() for the wired entry must never fail,
7605 * pmap_delayed_invl_start()/finish() calls around the
7606 * function are not needed.
7609 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7611 vm_offset_t va_next;
7612 pml4_entry_t *pml4e;
7615 pt_entry_t *pte, PG_V, PG_G;
7617 PG_V = pmap_valid_bit(pmap);
7618 PG_G = pmap_global_bit(pmap);
7620 for (; sva < eva; sva = va_next) {
7621 pml4e = pmap_pml4e(pmap, sva);
7622 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7623 va_next = (sva + NBPML4) & ~PML4MASK;
7629 va_next = (sva + NBPDP) & ~PDPMASK;
7632 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7633 if ((*pdpe & PG_V) == 0)
7635 if ((*pdpe & PG_PS) != 0) {
7636 KASSERT(va_next <= eva,
7637 ("partial update of non-transparent 1G mapping "
7638 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7639 *pdpe, sva, eva, va_next));
7640 MPASS(pmap != kernel_pmap); /* XXXKIB */
7641 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7642 atomic_clear_long(pdpe, PG_W);
7643 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7647 va_next = (sva + NBPDR) & ~PDRMASK;
7650 pde = pmap_pdpe_to_pde(pdpe, sva);
7651 if ((*pde & PG_V) == 0)
7653 if ((*pde & PG_PS) != 0) {
7654 if ((*pde & PG_W) == 0)
7655 panic("pmap_unwire: pde %#jx is missing PG_W",
7659 * Are we unwiring the entire large page? If not,
7660 * demote the mapping and fall through.
7662 if (sva + NBPDR == va_next && eva >= va_next) {
7663 atomic_clear_long(pde, PG_W);
7664 pmap->pm_stats.wired_count -= NBPDR /
7667 } else if (!pmap_demote_pde(pmap, pde, sva))
7668 panic("pmap_unwire: demotion failed");
7672 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7674 if ((*pte & PG_V) == 0)
7676 if ((*pte & PG_W) == 0)
7677 panic("pmap_unwire: pte %#jx is missing PG_W",
7681 * PG_W must be cleared atomically. Although the pmap
7682 * lock synchronizes access to PG_W, another processor
7683 * could be setting PG_M and/or PG_A concurrently.
7685 atomic_clear_long(pte, PG_W);
7686 pmap->pm_stats.wired_count--;
7693 * Copy the range specified by src_addr/len
7694 * from the source map to the range dst_addr/len
7695 * in the destination map.
7697 * This routine is only advisory and need not do anything.
7700 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7701 vm_offset_t src_addr)
7703 struct rwlock *lock;
7704 pml4_entry_t *pml4e;
7706 pd_entry_t *pde, srcptepaddr;
7707 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7708 vm_offset_t addr, end_addr, va_next;
7709 vm_page_t dst_pdpg, dstmpte, srcmpte;
7711 if (dst_addr != src_addr)
7714 if (dst_pmap->pm_type != src_pmap->pm_type)
7718 * EPT page table entries that require emulation of A/D bits are
7719 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7720 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7721 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7722 * implementations flag an EPT misconfiguration for exec-only
7723 * mappings we skip this function entirely for emulated pmaps.
7725 if (pmap_emulate_ad_bits(dst_pmap))
7728 end_addr = src_addr + len;
7730 if (dst_pmap < src_pmap) {
7731 PMAP_LOCK(dst_pmap);
7732 PMAP_LOCK(src_pmap);
7734 PMAP_LOCK(src_pmap);
7735 PMAP_LOCK(dst_pmap);
7738 PG_A = pmap_accessed_bit(dst_pmap);
7739 PG_M = pmap_modified_bit(dst_pmap);
7740 PG_V = pmap_valid_bit(dst_pmap);
7742 for (addr = src_addr; addr < end_addr; addr = va_next) {
7743 KASSERT(addr < UPT_MIN_ADDRESS,
7744 ("pmap_copy: invalid to pmap_copy page tables"));
7746 pml4e = pmap_pml4e(src_pmap, addr);
7747 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7748 va_next = (addr + NBPML4) & ~PML4MASK;
7754 va_next = (addr + NBPDP) & ~PDPMASK;
7757 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7758 if ((*pdpe & PG_V) == 0)
7760 if ((*pdpe & PG_PS) != 0) {
7761 KASSERT(va_next <= end_addr,
7762 ("partial update of non-transparent 1G mapping "
7763 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7764 *pdpe, addr, end_addr, va_next));
7765 MPASS((addr & PDPMASK) == 0);
7766 MPASS((*pdpe & PG_MANAGED) == 0);
7767 srcptepaddr = *pdpe;
7768 pdpe = pmap_pdpe(dst_pmap, addr);
7770 if (pmap_allocpte_alloc(dst_pmap,
7771 pmap_pml4e_pindex(addr), NULL, addr) ==
7774 pdpe = pmap_pdpe(dst_pmap, addr);
7776 pml4e = pmap_pml4e(dst_pmap, addr);
7777 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7778 dst_pdpg->ref_count++;
7781 ("1G mapping present in dst pmap "
7782 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7783 *pdpe, addr, end_addr, va_next));
7784 *pdpe = srcptepaddr & ~PG_W;
7785 pmap_resident_count_adj(dst_pmap, NBPDP / PAGE_SIZE);
7789 va_next = (addr + NBPDR) & ~PDRMASK;
7793 pde = pmap_pdpe_to_pde(pdpe, addr);
7795 if (srcptepaddr == 0)
7798 if (srcptepaddr & PG_PS) {
7800 * We can only virtual copy whole superpages.
7802 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7804 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7807 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7808 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7809 PMAP_ENTER_NORECLAIM, &lock))) {
7811 * We leave the dirty bit unchanged because
7812 * managed read/write superpage mappings are
7813 * required to be dirty. However, managed
7814 * superpage mappings are not required to
7815 * have their accessed bit set, so we clear
7816 * it because we don't know if this mapping
7819 srcptepaddr &= ~PG_W;
7820 if ((srcptepaddr & PG_MANAGED) != 0)
7821 srcptepaddr &= ~PG_A;
7823 pmap_resident_count_adj(dst_pmap, NBPDR /
7825 counter_u64_add(pmap_pde_mappings, 1);
7827 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7831 srcptepaddr &= PG_FRAME;
7832 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7833 KASSERT(srcmpte->ref_count > 0,
7834 ("pmap_copy: source page table page is unused"));
7836 if (va_next > end_addr)
7839 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7840 src_pte = &src_pte[pmap_pte_index(addr)];
7842 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7846 * We only virtual copy managed pages.
7848 if ((ptetemp & PG_MANAGED) == 0)
7851 if (dstmpte != NULL) {
7852 KASSERT(dstmpte->pindex ==
7853 pmap_pde_pindex(addr),
7854 ("dstmpte pindex/addr mismatch"));
7855 dstmpte->ref_count++;
7856 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7859 dst_pte = (pt_entry_t *)
7860 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7861 dst_pte = &dst_pte[pmap_pte_index(addr)];
7862 if (*dst_pte == 0 &&
7863 pmap_try_insert_pv_entry(dst_pmap, addr,
7864 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7866 * Clear the wired, modified, and accessed
7867 * (referenced) bits during the copy.
7869 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7870 pmap_resident_count_adj(dst_pmap, 1);
7872 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7875 /* Have we copied all of the valid mappings? */
7876 if (dstmpte->ref_count >= srcmpte->ref_count)
7883 PMAP_UNLOCK(src_pmap);
7884 PMAP_UNLOCK(dst_pmap);
7888 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7892 if (dst_pmap->pm_type != src_pmap->pm_type ||
7893 dst_pmap->pm_type != PT_X86 ||
7894 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7897 if (dst_pmap < src_pmap) {
7898 PMAP_LOCK(dst_pmap);
7899 PMAP_LOCK(src_pmap);
7901 PMAP_LOCK(src_pmap);
7902 PMAP_LOCK(dst_pmap);
7904 error = pmap_pkru_copy(dst_pmap, src_pmap);
7905 /* Clean up partial copy on failure due to no memory. */
7906 if (error == ENOMEM)
7907 pmap_pkru_deassign_all(dst_pmap);
7908 PMAP_UNLOCK(src_pmap);
7909 PMAP_UNLOCK(dst_pmap);
7910 if (error != ENOMEM)
7918 * Zero the specified hardware page.
7921 pmap_zero_page(vm_page_t m)
7923 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7925 pagezero((void *)va);
7929 * Zero an an area within a single hardware page. off and size must not
7930 * cover an area beyond a single hardware page.
7933 pmap_zero_page_area(vm_page_t m, int off, int size)
7935 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7937 if (off == 0 && size == PAGE_SIZE)
7938 pagezero((void *)va);
7940 bzero((char *)va + off, size);
7944 * Copy 1 specified hardware page to another.
7947 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7949 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7950 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7952 pagecopy((void *)src, (void *)dst);
7955 int unmapped_buf_allowed = 1;
7958 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7959 vm_offset_t b_offset, int xfersize)
7963 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7967 while (xfersize > 0) {
7968 a_pg_offset = a_offset & PAGE_MASK;
7969 pages[0] = ma[a_offset >> PAGE_SHIFT];
7970 b_pg_offset = b_offset & PAGE_MASK;
7971 pages[1] = mb[b_offset >> PAGE_SHIFT];
7972 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7973 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7974 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7975 a_cp = (char *)vaddr[0] + a_pg_offset;
7976 b_cp = (char *)vaddr[1] + b_pg_offset;
7977 bcopy(a_cp, b_cp, cnt);
7978 if (__predict_false(mapped))
7979 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7987 * Returns true if the pmap's pv is one of the first
7988 * 16 pvs linked to from this page. This count may
7989 * be changed upwards or downwards in the future; it
7990 * is only necessary that true be returned for a small
7991 * subset of pmaps for proper page aging.
7994 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7996 struct md_page *pvh;
7997 struct rwlock *lock;
8002 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8003 ("pmap_page_exists_quick: page %p is not managed", m));
8005 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8007 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8008 if (PV_PMAP(pv) == pmap) {
8016 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
8017 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8018 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8019 if (PV_PMAP(pv) == pmap) {
8033 * pmap_page_wired_mappings:
8035 * Return the number of managed mappings to the given physical page
8039 pmap_page_wired_mappings(vm_page_t m)
8041 struct rwlock *lock;
8042 struct md_page *pvh;
8046 int count, md_gen, pvh_gen;
8048 if ((m->oflags & VPO_UNMANAGED) != 0)
8050 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8054 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8056 if (!PMAP_TRYLOCK(pmap)) {
8057 md_gen = m->md.pv_gen;
8061 if (md_gen != m->md.pv_gen) {
8066 pte = pmap_pte(pmap, pv->pv_va);
8067 if ((*pte & PG_W) != 0)
8071 if ((m->flags & PG_FICTITIOUS) == 0) {
8072 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8073 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8075 if (!PMAP_TRYLOCK(pmap)) {
8076 md_gen = m->md.pv_gen;
8077 pvh_gen = pvh->pv_gen;
8081 if (md_gen != m->md.pv_gen ||
8082 pvh_gen != pvh->pv_gen) {
8087 pte = pmap_pde(pmap, pv->pv_va);
8088 if ((*pte & PG_W) != 0)
8098 * Returns TRUE if the given page is mapped individually or as part of
8099 * a 2mpage. Otherwise, returns FALSE.
8102 pmap_page_is_mapped(vm_page_t m)
8104 struct rwlock *lock;
8107 if ((m->oflags & VPO_UNMANAGED) != 0)
8109 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8111 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
8112 ((m->flags & PG_FICTITIOUS) == 0 &&
8113 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
8119 * Destroy all managed, non-wired mappings in the given user-space
8120 * pmap. This pmap cannot be active on any processor besides the
8123 * This function cannot be applied to the kernel pmap. Moreover, it
8124 * is not intended for general use. It is only to be used during
8125 * process termination. Consequently, it can be implemented in ways
8126 * that make it faster than pmap_remove(). First, it can more quickly
8127 * destroy mappings by iterating over the pmap's collection of PV
8128 * entries, rather than searching the page table. Second, it doesn't
8129 * have to test and clear the page table entries atomically, because
8130 * no processor is currently accessing the user address space. In
8131 * particular, a page table entry's dirty bit won't change state once
8132 * this function starts.
8134 * Although this function destroys all of the pmap's managed,
8135 * non-wired mappings, it can delay and batch the invalidation of TLB
8136 * entries without calling pmap_delayed_invl_start() and
8137 * pmap_delayed_invl_finish(). Because the pmap is not active on
8138 * any other processor, none of these TLB entries will ever be used
8139 * before their eventual invalidation. Consequently, there is no need
8140 * for either pmap_remove_all() or pmap_remove_write() to wait for
8141 * that eventual TLB invalidation.
8144 pmap_remove_pages(pmap_t pmap)
8147 pt_entry_t *pte, tpte;
8148 pt_entry_t PG_M, PG_RW, PG_V;
8149 struct spglist free;
8150 struct pv_chunklist free_chunks[PMAP_MEMDOM];
8151 vm_page_t m, mpte, mt;
8153 struct md_page *pvh;
8154 struct pv_chunk *pc, *npc;
8155 struct rwlock *lock;
8157 uint64_t inuse, bitmask;
8158 int allfree, field, freed, i, idx;
8159 boolean_t superpage;
8163 * Assert that the given pmap is only active on the current
8164 * CPU. Unfortunately, we cannot block another CPU from
8165 * activating the pmap while this function is executing.
8167 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
8170 cpuset_t other_cpus;
8172 other_cpus = all_cpus;
8174 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
8175 CPU_AND(&other_cpus, &pmap->pm_active);
8177 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
8182 PG_M = pmap_modified_bit(pmap);
8183 PG_V = pmap_valid_bit(pmap);
8184 PG_RW = pmap_rw_bit(pmap);
8186 for (i = 0; i < PMAP_MEMDOM; i++)
8187 TAILQ_INIT(&free_chunks[i]);
8190 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
8193 for (field = 0; field < _NPCM; field++) {
8194 inuse = ~pc->pc_map[field] & pc_freemask[field];
8195 while (inuse != 0) {
8197 bitmask = 1UL << bit;
8198 idx = field * 64 + bit;
8199 pv = &pc->pc_pventry[idx];
8202 pte = pmap_pdpe(pmap, pv->pv_va);
8204 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
8206 if ((tpte & (PG_PS | PG_V)) == PG_V) {
8209 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
8211 pte = &pte[pmap_pte_index(pv->pv_va)];
8215 * Keep track whether 'tpte' is a
8216 * superpage explicitly instead of
8217 * relying on PG_PS being set.
8219 * This is because PG_PS is numerically
8220 * identical to PG_PTE_PAT and thus a
8221 * regular page could be mistaken for
8227 if ((tpte & PG_V) == 0) {
8228 panic("bad pte va %lx pte %lx",
8233 * We cannot remove wired pages from a process' mapping at this time
8241 pc->pc_map[field] |= bitmask;
8244 * Because this pmap is not active on other
8245 * processors, the dirty bit cannot have
8246 * changed state since we last loaded pte.
8251 pa = tpte & PG_PS_FRAME;
8253 pa = tpte & PG_FRAME;
8255 m = PHYS_TO_VM_PAGE(pa);
8256 KASSERT(m->phys_addr == pa,
8257 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
8258 m, (uintmax_t)m->phys_addr,
8261 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
8262 m < &vm_page_array[vm_page_array_size],
8263 ("pmap_remove_pages: bad tpte %#jx",
8267 * Update the vm_page_t clean/reference bits.
8269 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8271 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8277 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
8280 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
8281 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
8282 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8284 if (TAILQ_EMPTY(&pvh->pv_list)) {
8285 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8286 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8287 TAILQ_EMPTY(&mt->md.pv_list))
8288 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8290 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8292 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8293 ("pmap_remove_pages: pte page not promoted"));
8294 pmap_resident_count_adj(pmap, -1);
8295 KASSERT(mpte->ref_count == NPTEPG,
8296 ("pmap_remove_pages: pte page reference count error"));
8297 mpte->ref_count = 0;
8298 pmap_add_delayed_free_list(mpte, &free, FALSE);
8301 pmap_resident_count_adj(pmap, -1);
8302 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8304 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8305 TAILQ_EMPTY(&m->md.pv_list) &&
8306 (m->flags & PG_FICTITIOUS) == 0) {
8307 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8308 if (TAILQ_EMPTY(&pvh->pv_list))
8309 vm_page_aflag_clear(m, PGA_WRITEABLE);
8312 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8316 PV_STAT(counter_u64_add(pv_entry_frees, freed));
8317 PV_STAT(counter_u64_add(pv_entry_spare, freed));
8318 PV_STAT(counter_u64_add(pv_entry_count, -freed));
8320 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8321 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8326 pmap_invalidate_all(pmap);
8327 pmap_pkru_deassign_all(pmap);
8328 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8330 vm_page_free_pages_toq(&free, true);
8334 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8336 struct rwlock *lock;
8338 struct md_page *pvh;
8339 pt_entry_t *pte, mask;
8340 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8342 int md_gen, pvh_gen;
8346 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8349 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8351 if (!PMAP_TRYLOCK(pmap)) {
8352 md_gen = m->md.pv_gen;
8356 if (md_gen != m->md.pv_gen) {
8361 pte = pmap_pte(pmap, pv->pv_va);
8364 PG_M = pmap_modified_bit(pmap);
8365 PG_RW = pmap_rw_bit(pmap);
8366 mask |= PG_RW | PG_M;
8369 PG_A = pmap_accessed_bit(pmap);
8370 PG_V = pmap_valid_bit(pmap);
8371 mask |= PG_V | PG_A;
8373 rv = (*pte & mask) == mask;
8378 if ((m->flags & PG_FICTITIOUS) == 0) {
8379 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8380 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8382 if (!PMAP_TRYLOCK(pmap)) {
8383 md_gen = m->md.pv_gen;
8384 pvh_gen = pvh->pv_gen;
8388 if (md_gen != m->md.pv_gen ||
8389 pvh_gen != pvh->pv_gen) {
8394 pte = pmap_pde(pmap, pv->pv_va);
8397 PG_M = pmap_modified_bit(pmap);
8398 PG_RW = pmap_rw_bit(pmap);
8399 mask |= PG_RW | PG_M;
8402 PG_A = pmap_accessed_bit(pmap);
8403 PG_V = pmap_valid_bit(pmap);
8404 mask |= PG_V | PG_A;
8406 rv = (*pte & mask) == mask;
8420 * Return whether or not the specified physical page was modified
8421 * in any physical maps.
8424 pmap_is_modified(vm_page_t m)
8427 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8428 ("pmap_is_modified: page %p is not managed", m));
8431 * If the page is not busied then this check is racy.
8433 if (!pmap_page_is_write_mapped(m))
8435 return (pmap_page_test_mappings(m, FALSE, TRUE));
8439 * pmap_is_prefaultable:
8441 * Return whether or not the specified virtual address is eligible
8445 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8448 pt_entry_t *pte, PG_V;
8451 PG_V = pmap_valid_bit(pmap);
8454 pde = pmap_pde(pmap, addr);
8455 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8456 pte = pmap_pde_to_pte(pde, addr);
8457 rv = (*pte & PG_V) == 0;
8464 * pmap_is_referenced:
8466 * Return whether or not the specified physical page was referenced
8467 * in any physical maps.
8470 pmap_is_referenced(vm_page_t m)
8473 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8474 ("pmap_is_referenced: page %p is not managed", m));
8475 return (pmap_page_test_mappings(m, TRUE, FALSE));
8479 * Clear the write and modified bits in each of the given page's mappings.
8482 pmap_remove_write(vm_page_t m)
8484 struct md_page *pvh;
8486 struct rwlock *lock;
8487 pv_entry_t next_pv, pv;
8489 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8491 int pvh_gen, md_gen;
8493 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8494 ("pmap_remove_write: page %p is not managed", m));
8496 vm_page_assert_busied(m);
8497 if (!pmap_page_is_write_mapped(m))
8500 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8501 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8502 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8505 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8507 if (!PMAP_TRYLOCK(pmap)) {
8508 pvh_gen = pvh->pv_gen;
8512 if (pvh_gen != pvh->pv_gen) {
8517 PG_RW = pmap_rw_bit(pmap);
8519 pde = pmap_pde(pmap, va);
8520 if ((*pde & PG_RW) != 0)
8521 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8522 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8523 ("inconsistent pv lock %p %p for page %p",
8524 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8527 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8529 if (!PMAP_TRYLOCK(pmap)) {
8530 pvh_gen = pvh->pv_gen;
8531 md_gen = m->md.pv_gen;
8535 if (pvh_gen != pvh->pv_gen ||
8536 md_gen != m->md.pv_gen) {
8541 PG_M = pmap_modified_bit(pmap);
8542 PG_RW = pmap_rw_bit(pmap);
8543 pde = pmap_pde(pmap, pv->pv_va);
8544 KASSERT((*pde & PG_PS) == 0,
8545 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8547 pte = pmap_pde_to_pte(pde, pv->pv_va);
8549 if (oldpte & PG_RW) {
8550 while (!atomic_fcmpset_long(pte, &oldpte, oldpte &
8553 if ((oldpte & PG_M) != 0)
8555 pmap_invalidate_page(pmap, pv->pv_va);
8560 vm_page_aflag_clear(m, PGA_WRITEABLE);
8561 pmap_delayed_invl_wait(m);
8564 static __inline boolean_t
8565 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8568 if (!pmap_emulate_ad_bits(pmap))
8571 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8574 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8575 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8576 * if the EPT_PG_WRITE bit is set.
8578 if ((pte & EPT_PG_WRITE) != 0)
8582 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8584 if ((pte & EPT_PG_EXECUTE) == 0 ||
8585 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8592 * pmap_ts_referenced:
8594 * Return a count of reference bits for a page, clearing those bits.
8595 * It is not necessary for every reference bit to be cleared, but it
8596 * is necessary that 0 only be returned when there are truly no
8597 * reference bits set.
8599 * As an optimization, update the page's dirty field if a modified bit is
8600 * found while counting reference bits. This opportunistic update can be
8601 * performed at low cost and can eliminate the need for some future calls
8602 * to pmap_is_modified(). However, since this function stops after
8603 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8604 * dirty pages. Those dirty pages will only be detected by a future call
8605 * to pmap_is_modified().
8607 * A DI block is not needed within this function, because
8608 * invalidations are performed before the PV list lock is
8612 pmap_ts_referenced(vm_page_t m)
8614 struct md_page *pvh;
8617 struct rwlock *lock;
8618 pd_entry_t oldpde, *pde;
8619 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8622 int cleared, md_gen, not_cleared, pvh_gen;
8623 struct spglist free;
8626 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8627 ("pmap_ts_referenced: page %p is not managed", m));
8630 pa = VM_PAGE_TO_PHYS(m);
8631 lock = PHYS_TO_PV_LIST_LOCK(pa);
8632 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8636 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8637 goto small_mappings;
8643 if (!PMAP_TRYLOCK(pmap)) {
8644 pvh_gen = pvh->pv_gen;
8648 if (pvh_gen != pvh->pv_gen) {
8653 PG_A = pmap_accessed_bit(pmap);
8654 PG_M = pmap_modified_bit(pmap);
8655 PG_RW = pmap_rw_bit(pmap);
8657 pde = pmap_pde(pmap, pv->pv_va);
8659 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8661 * Although "oldpde" is mapping a 2MB page, because
8662 * this function is called at a 4KB page granularity,
8663 * we only update the 4KB page under test.
8667 if ((oldpde & PG_A) != 0) {
8669 * Since this reference bit is shared by 512 4KB
8670 * pages, it should not be cleared every time it is
8671 * tested. Apply a simple "hash" function on the
8672 * physical page number, the virtual superpage number,
8673 * and the pmap address to select one 4KB page out of
8674 * the 512 on which testing the reference bit will
8675 * result in clearing that reference bit. This
8676 * function is designed to avoid the selection of the
8677 * same 4KB page for every 2MB page mapping.
8679 * On demotion, a mapping that hasn't been referenced
8680 * is simply destroyed. To avoid the possibility of a
8681 * subsequent page fault on a demoted wired mapping,
8682 * always leave its reference bit set. Moreover,
8683 * since the superpage is wired, the current state of
8684 * its reference bit won't affect page replacement.
8686 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8687 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8688 (oldpde & PG_W) == 0) {
8689 if (safe_to_clear_referenced(pmap, oldpde)) {
8690 atomic_clear_long(pde, PG_A);
8691 pmap_invalidate_page(pmap, pv->pv_va);
8693 } else if (pmap_demote_pde_locked(pmap, pde,
8694 pv->pv_va, &lock)) {
8696 * Remove the mapping to a single page
8697 * so that a subsequent access may
8698 * repromote. Since the underlying
8699 * page table page is fully populated,
8700 * this removal never frees a page
8704 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8706 pte = pmap_pde_to_pte(pde, va);
8707 pmap_remove_pte(pmap, pte, va, *pde,
8709 pmap_invalidate_page(pmap, va);
8715 * The superpage mapping was removed
8716 * entirely and therefore 'pv' is no
8724 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8725 ("inconsistent pv lock %p %p for page %p",
8726 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8731 /* Rotate the PV list if it has more than one entry. */
8732 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8733 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8734 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8737 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8739 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8741 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8748 if (!PMAP_TRYLOCK(pmap)) {
8749 pvh_gen = pvh->pv_gen;
8750 md_gen = m->md.pv_gen;
8754 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8759 PG_A = pmap_accessed_bit(pmap);
8760 PG_M = pmap_modified_bit(pmap);
8761 PG_RW = pmap_rw_bit(pmap);
8762 pde = pmap_pde(pmap, pv->pv_va);
8763 KASSERT((*pde & PG_PS) == 0,
8764 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8766 pte = pmap_pde_to_pte(pde, pv->pv_va);
8767 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8769 if ((*pte & PG_A) != 0) {
8770 if (safe_to_clear_referenced(pmap, *pte)) {
8771 atomic_clear_long(pte, PG_A);
8772 pmap_invalidate_page(pmap, pv->pv_va);
8774 } else if ((*pte & PG_W) == 0) {
8776 * Wired pages cannot be paged out so
8777 * doing accessed bit emulation for
8778 * them is wasted effort. We do the
8779 * hard work for unwired pages only.
8781 pmap_remove_pte(pmap, pte, pv->pv_va,
8782 *pde, &free, &lock);
8783 pmap_invalidate_page(pmap, pv->pv_va);
8788 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8789 ("inconsistent pv lock %p %p for page %p",
8790 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8795 /* Rotate the PV list if it has more than one entry. */
8796 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8797 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8798 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8801 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8802 not_cleared < PMAP_TS_REFERENCED_MAX);
8805 vm_page_free_pages_toq(&free, true);
8806 return (cleared + not_cleared);
8810 * Apply the given advice to the specified range of addresses within the
8811 * given pmap. Depending on the advice, clear the referenced and/or
8812 * modified flags in each mapping and set the mapped page's dirty field.
8815 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8817 struct rwlock *lock;
8818 pml4_entry_t *pml4e;
8820 pd_entry_t oldpde, *pde;
8821 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8822 vm_offset_t va, va_next;
8826 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8830 * A/D bit emulation requires an alternate code path when clearing
8831 * the modified and accessed bits below. Since this function is
8832 * advisory in nature we skip it entirely for pmaps that require
8833 * A/D bit emulation.
8835 if (pmap_emulate_ad_bits(pmap))
8838 PG_A = pmap_accessed_bit(pmap);
8839 PG_G = pmap_global_bit(pmap);
8840 PG_M = pmap_modified_bit(pmap);
8841 PG_V = pmap_valid_bit(pmap);
8842 PG_RW = pmap_rw_bit(pmap);
8844 pmap_delayed_invl_start();
8846 for (; sva < eva; sva = va_next) {
8847 pml4e = pmap_pml4e(pmap, sva);
8848 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8849 va_next = (sva + NBPML4) & ~PML4MASK;
8855 va_next = (sva + NBPDP) & ~PDPMASK;
8858 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8859 if ((*pdpe & PG_V) == 0)
8861 if ((*pdpe & PG_PS) != 0) {
8862 KASSERT(va_next <= eva,
8863 ("partial update of non-transparent 1G mapping "
8864 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8865 *pdpe, sva, eva, va_next));
8869 va_next = (sva + NBPDR) & ~PDRMASK;
8872 pde = pmap_pdpe_to_pde(pdpe, sva);
8874 if ((oldpde & PG_V) == 0)
8876 else if ((oldpde & PG_PS) != 0) {
8877 if ((oldpde & PG_MANAGED) == 0)
8880 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8885 * The large page mapping was destroyed.
8891 * Unless the page mappings are wired, remove the
8892 * mapping to a single page so that a subsequent
8893 * access may repromote. Choosing the last page
8894 * within the address range [sva, min(va_next, eva))
8895 * generally results in more repromotions. Since the
8896 * underlying page table page is fully populated, this
8897 * removal never frees a page table page.
8899 if ((oldpde & PG_W) == 0) {
8905 ("pmap_advise: no address gap"));
8906 pte = pmap_pde_to_pte(pde, va);
8907 KASSERT((*pte & PG_V) != 0,
8908 ("pmap_advise: invalid PTE"));
8909 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8919 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8921 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8923 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8924 if (advice == MADV_DONTNEED) {
8926 * Future calls to pmap_is_modified()
8927 * can be avoided by making the page
8930 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8933 atomic_clear_long(pte, PG_M | PG_A);
8934 } else if ((*pte & PG_A) != 0)
8935 atomic_clear_long(pte, PG_A);
8939 if ((*pte & PG_G) != 0) {
8946 if (va != va_next) {
8947 pmap_invalidate_range(pmap, va, sva);
8952 pmap_invalidate_range(pmap, va, sva);
8955 pmap_invalidate_all(pmap);
8957 pmap_delayed_invl_finish();
8961 * Clear the modify bits on the specified physical page.
8964 pmap_clear_modify(vm_page_t m)
8966 struct md_page *pvh;
8968 pv_entry_t next_pv, pv;
8969 pd_entry_t oldpde, *pde;
8970 pt_entry_t *pte, PG_M, PG_RW;
8971 struct rwlock *lock;
8973 int md_gen, pvh_gen;
8975 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8976 ("pmap_clear_modify: page %p is not managed", m));
8977 vm_page_assert_busied(m);
8979 if (!pmap_page_is_write_mapped(m))
8981 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8982 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8983 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8986 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8988 if (!PMAP_TRYLOCK(pmap)) {
8989 pvh_gen = pvh->pv_gen;
8993 if (pvh_gen != pvh->pv_gen) {
8998 PG_M = pmap_modified_bit(pmap);
8999 PG_RW = pmap_rw_bit(pmap);
9001 pde = pmap_pde(pmap, va);
9003 /* If oldpde has PG_RW set, then it also has PG_M set. */
9004 if ((oldpde & PG_RW) != 0 &&
9005 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
9006 (oldpde & PG_W) == 0) {
9008 * Write protect the mapping to a single page so that
9009 * a subsequent write access may repromote.
9011 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
9012 pte = pmap_pde_to_pte(pde, va);
9013 atomic_clear_long(pte, PG_M | PG_RW);
9015 pmap_invalidate_page(pmap, va);
9019 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
9021 if (!PMAP_TRYLOCK(pmap)) {
9022 md_gen = m->md.pv_gen;
9023 pvh_gen = pvh->pv_gen;
9027 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
9032 PG_M = pmap_modified_bit(pmap);
9033 PG_RW = pmap_rw_bit(pmap);
9034 pde = pmap_pde(pmap, pv->pv_va);
9035 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
9036 " a 2mpage in page %p's pv list", m));
9037 pte = pmap_pde_to_pte(pde, pv->pv_va);
9038 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
9039 atomic_clear_long(pte, PG_M);
9040 pmap_invalidate_page(pmap, pv->pv_va);
9048 * Miscellaneous support routines follow
9051 /* Adjust the properties for a leaf page table entry. */
9052 static __inline void
9053 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
9057 opte = *(u_long *)pte;
9059 npte = opte & ~mask;
9061 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
9066 * Map a set of physical memory pages into the kernel virtual
9067 * address space. Return a pointer to where it is mapped. This
9068 * routine is intended to be used for mapping device memory,
9072 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
9074 struct pmap_preinit_mapping *ppim;
9075 vm_offset_t va, offset;
9079 offset = pa & PAGE_MASK;
9080 size = round_page(offset + size);
9081 pa = trunc_page(pa);
9083 if (!pmap_initialized) {
9085 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9086 ppim = pmap_preinit_mapping + i;
9087 if (ppim->va == 0) {
9091 ppim->va = virtual_avail;
9092 virtual_avail += size;
9098 panic("%s: too many preinit mappings", __func__);
9101 * If we have a preinit mapping, re-use it.
9103 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9104 ppim = pmap_preinit_mapping + i;
9105 if (ppim->pa == pa && ppim->sz == size &&
9106 (ppim->mode == mode ||
9107 (flags & MAPDEV_SETATTR) == 0))
9108 return ((void *)(ppim->va + offset));
9111 * If the specified range of physical addresses fits within
9112 * the direct map window, use the direct map.
9114 if (pa < dmaplimit && pa + size <= dmaplimit) {
9115 va = PHYS_TO_DMAP(pa);
9116 if ((flags & MAPDEV_SETATTR) != 0) {
9117 PMAP_LOCK(kernel_pmap);
9118 i = pmap_change_props_locked(va, size,
9119 PROT_NONE, mode, flags);
9120 PMAP_UNLOCK(kernel_pmap);
9124 return ((void *)(va + offset));
9126 va = kva_alloc(size);
9128 panic("%s: Couldn't allocate KVA", __func__);
9130 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
9131 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
9132 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
9133 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9134 pmap_invalidate_cache_range(va, va + tmpsize);
9135 return ((void *)(va + offset));
9139 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
9142 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
9147 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
9150 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
9154 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
9157 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
9162 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
9165 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
9166 MAPDEV_FLUSHCACHE));
9170 pmap_unmapdev(vm_offset_t va, vm_size_t size)
9172 struct pmap_preinit_mapping *ppim;
9176 /* If we gave a direct map region in pmap_mapdev, do nothing */
9177 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
9179 offset = va & PAGE_MASK;
9180 size = round_page(offset + size);
9181 va = trunc_page(va);
9182 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9183 ppim = pmap_preinit_mapping + i;
9184 if (ppim->va == va && ppim->sz == size) {
9185 if (pmap_initialized)
9191 if (va + size == virtual_avail)
9196 if (pmap_initialized) {
9197 pmap_qremove(va, atop(size));
9203 * Tries to demote a 1GB page mapping.
9206 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
9208 pdp_entry_t newpdpe, oldpdpe;
9209 pd_entry_t *firstpde, newpde, *pde;
9210 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
9214 PG_A = pmap_accessed_bit(pmap);
9215 PG_M = pmap_modified_bit(pmap);
9216 PG_V = pmap_valid_bit(pmap);
9217 PG_RW = pmap_rw_bit(pmap);
9219 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9221 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
9222 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
9223 pdpg = pmap_alloc_pt_page(pmap, va >> PDPSHIFT,
9224 VM_ALLOC_WIRED | VM_ALLOC_INTERRUPT);
9226 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
9227 " in pmap %p", va, pmap);
9230 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
9231 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
9232 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
9233 KASSERT((oldpdpe & PG_A) != 0,
9234 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
9235 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
9236 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
9240 * Initialize the page directory page.
9242 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
9248 * Demote the mapping.
9253 * Invalidate a stale recursive mapping of the page directory page.
9255 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
9257 counter_u64_add(pmap_pdpe_demotions, 1);
9258 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
9259 " in pmap %p", va, pmap);
9264 * Sets the memory attribute for the specified page.
9267 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
9270 m->md.pat_mode = ma;
9273 * If "m" is a normal page, update its direct mapping. This update
9274 * can be relied upon to perform any cache operations that are
9275 * required for data coherence.
9277 if ((m->flags & PG_FICTITIOUS) == 0 &&
9278 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
9280 panic("memory attribute change on the direct map failed");
9284 pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma)
9288 m->md.pat_mode = ma;
9290 if ((m->flags & PG_FICTITIOUS) != 0)
9292 PMAP_LOCK(kernel_pmap);
9293 error = pmap_change_props_locked(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)),
9294 PAGE_SIZE, PROT_NONE, m->md.pat_mode, 0);
9295 PMAP_UNLOCK(kernel_pmap);
9297 panic("memory attribute change on the direct map failed");
9301 * Changes the specified virtual address range's memory type to that given by
9302 * the parameter "mode". The specified virtual address range must be
9303 * completely contained within either the direct map or the kernel map. If
9304 * the virtual address range is contained within the kernel map, then the
9305 * memory type for each of the corresponding ranges of the direct map is also
9306 * changed. (The corresponding ranges of the direct map are those ranges that
9307 * map the same physical pages as the specified virtual address range.) These
9308 * changes to the direct map are necessary because Intel describes the
9309 * behavior of their processors as "undefined" if two or more mappings to the
9310 * same physical page have different memory types.
9312 * Returns zero if the change completed successfully, and either EINVAL or
9313 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9314 * of the virtual address range was not mapped, and ENOMEM is returned if
9315 * there was insufficient memory available to complete the change. In the
9316 * latter case, the memory type may have been changed on some part of the
9317 * virtual address range or the direct map.
9320 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9324 PMAP_LOCK(kernel_pmap);
9325 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9327 PMAP_UNLOCK(kernel_pmap);
9332 * Changes the specified virtual address range's protections to those
9333 * specified by "prot". Like pmap_change_attr(), protections for aliases
9334 * in the direct map are updated as well. Protections on aliasing mappings may
9335 * be a subset of the requested protections; for example, mappings in the direct
9336 * map are never executable.
9339 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9343 /* Only supported within the kernel map. */
9344 if (va < VM_MIN_KERNEL_ADDRESS)
9347 PMAP_LOCK(kernel_pmap);
9348 error = pmap_change_props_locked(va, size, prot, -1,
9349 MAPDEV_ASSERTVALID);
9350 PMAP_UNLOCK(kernel_pmap);
9355 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9356 int mode, int flags)
9358 vm_offset_t base, offset, tmpva;
9359 vm_paddr_t pa_start, pa_end, pa_end1;
9361 pd_entry_t *pde, pde_bits, pde_mask;
9362 pt_entry_t *pte, pte_bits, pte_mask;
9366 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9367 base = trunc_page(va);
9368 offset = va & PAGE_MASK;
9369 size = round_page(offset + size);
9372 * Only supported on kernel virtual addresses, including the direct
9373 * map but excluding the recursive map.
9375 if (base < DMAP_MIN_ADDRESS)
9379 * Construct our flag sets and masks. "bits" is the subset of
9380 * "mask" that will be set in each modified PTE.
9382 * Mappings in the direct map are never allowed to be executable.
9384 pde_bits = pte_bits = 0;
9385 pde_mask = pte_mask = 0;
9387 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9388 pde_mask |= X86_PG_PDE_CACHE;
9389 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9390 pte_mask |= X86_PG_PTE_CACHE;
9392 if (prot != VM_PROT_NONE) {
9393 if ((prot & VM_PROT_WRITE) != 0) {
9394 pde_bits |= X86_PG_RW;
9395 pte_bits |= X86_PG_RW;
9397 if ((prot & VM_PROT_EXECUTE) == 0 ||
9398 va < VM_MIN_KERNEL_ADDRESS) {
9402 pde_mask |= X86_PG_RW | pg_nx;
9403 pte_mask |= X86_PG_RW | pg_nx;
9407 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9408 * into 4KB pages if required.
9410 for (tmpva = base; tmpva < base + size; ) {
9411 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9412 if (pdpe == NULL || *pdpe == 0) {
9413 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9414 ("%s: addr %#lx is not mapped", __func__, tmpva));
9417 if (*pdpe & PG_PS) {
9419 * If the current 1GB page already has the required
9420 * properties, then we need not demote this page. Just
9421 * increment tmpva to the next 1GB page frame.
9423 if ((*pdpe & pde_mask) == pde_bits) {
9424 tmpva = trunc_1gpage(tmpva) + NBPDP;
9429 * If the current offset aligns with a 1GB page frame
9430 * and there is at least 1GB left within the range, then
9431 * we need not break down this page into 2MB pages.
9433 if ((tmpva & PDPMASK) == 0 &&
9434 tmpva + PDPMASK < base + size) {
9438 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9441 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9443 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9444 ("%s: addr %#lx is not mapped", __func__, tmpva));
9449 * If the current 2MB page already has the required
9450 * properties, then we need not demote this page. Just
9451 * increment tmpva to the next 2MB page frame.
9453 if ((*pde & pde_mask) == pde_bits) {
9454 tmpva = trunc_2mpage(tmpva) + NBPDR;
9459 * If the current offset aligns with a 2MB page frame
9460 * and there is at least 2MB left within the range, then
9461 * we need not break down this page into 4KB pages.
9463 if ((tmpva & PDRMASK) == 0 &&
9464 tmpva + PDRMASK < base + size) {
9468 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9471 pte = pmap_pde_to_pte(pde, tmpva);
9473 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9474 ("%s: addr %#lx is not mapped", __func__, tmpva));
9482 * Ok, all the pages exist, so run through them updating their
9483 * properties if required.
9486 pa_start = pa_end = 0;
9487 for (tmpva = base; tmpva < base + size; ) {
9488 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9489 if (*pdpe & PG_PS) {
9490 if ((*pdpe & pde_mask) != pde_bits) {
9491 pmap_pte_props(pdpe, pde_bits, pde_mask);
9494 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9495 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9496 if (pa_start == pa_end) {
9497 /* Start physical address run. */
9498 pa_start = *pdpe & PG_PS_FRAME;
9499 pa_end = pa_start + NBPDP;
9500 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9503 /* Run ended, update direct map. */
9504 error = pmap_change_props_locked(
9505 PHYS_TO_DMAP(pa_start),
9506 pa_end - pa_start, prot, mode,
9510 /* Start physical address run. */
9511 pa_start = *pdpe & PG_PS_FRAME;
9512 pa_end = pa_start + NBPDP;
9515 tmpva = trunc_1gpage(tmpva) + NBPDP;
9518 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9520 if ((*pde & pde_mask) != pde_bits) {
9521 pmap_pte_props(pde, pde_bits, pde_mask);
9524 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9525 (*pde & PG_PS_FRAME) < dmaplimit) {
9526 if (pa_start == pa_end) {
9527 /* Start physical address run. */
9528 pa_start = *pde & PG_PS_FRAME;
9529 pa_end = pa_start + NBPDR;
9530 } else if (pa_end == (*pde & PG_PS_FRAME))
9533 /* Run ended, update direct map. */
9534 error = pmap_change_props_locked(
9535 PHYS_TO_DMAP(pa_start),
9536 pa_end - pa_start, prot, mode,
9540 /* Start physical address run. */
9541 pa_start = *pde & PG_PS_FRAME;
9542 pa_end = pa_start + NBPDR;
9545 tmpva = trunc_2mpage(tmpva) + NBPDR;
9547 pte = pmap_pde_to_pte(pde, tmpva);
9548 if ((*pte & pte_mask) != pte_bits) {
9549 pmap_pte_props(pte, pte_bits, pte_mask);
9552 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9553 (*pte & PG_FRAME) < dmaplimit) {
9554 if (pa_start == pa_end) {
9555 /* Start physical address run. */
9556 pa_start = *pte & PG_FRAME;
9557 pa_end = pa_start + PAGE_SIZE;
9558 } else if (pa_end == (*pte & PG_FRAME))
9559 pa_end += PAGE_SIZE;
9561 /* Run ended, update direct map. */
9562 error = pmap_change_props_locked(
9563 PHYS_TO_DMAP(pa_start),
9564 pa_end - pa_start, prot, mode,
9568 /* Start physical address run. */
9569 pa_start = *pte & PG_FRAME;
9570 pa_end = pa_start + PAGE_SIZE;
9576 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9577 pa_end1 = MIN(pa_end, dmaplimit);
9578 if (pa_start != pa_end1)
9579 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9580 pa_end1 - pa_start, prot, mode, flags);
9584 * Flush CPU caches if required to make sure any data isn't cached that
9585 * shouldn't be, etc.
9588 pmap_invalidate_range(kernel_pmap, base, tmpva);
9589 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9590 pmap_invalidate_cache_range(base, tmpva);
9596 * Demotes any mapping within the direct map region that covers more than the
9597 * specified range of physical addresses. This range's size must be a power
9598 * of two and its starting address must be a multiple of its size. Since the
9599 * demotion does not change any attributes of the mapping, a TLB invalidation
9600 * is not mandatory. The caller may, however, request a TLB invalidation.
9603 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9612 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9613 KASSERT((base & (len - 1)) == 0,
9614 ("pmap_demote_DMAP: base is not a multiple of len"));
9615 if (len < NBPDP && base < dmaplimit) {
9616 va = PHYS_TO_DMAP(base);
9618 PMAP_LOCK(kernel_pmap);
9619 pdpe = pmap_pdpe(kernel_pmap, va);
9620 if ((*pdpe & X86_PG_V) == 0)
9621 panic("pmap_demote_DMAP: invalid PDPE");
9622 if ((*pdpe & PG_PS) != 0) {
9623 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9624 panic("pmap_demote_DMAP: PDPE failed");
9628 pde = pmap_pdpe_to_pde(pdpe, va);
9629 if ((*pde & X86_PG_V) == 0)
9630 panic("pmap_demote_DMAP: invalid PDE");
9631 if ((*pde & PG_PS) != 0) {
9632 if (!pmap_demote_pde(kernel_pmap, pde, va))
9633 panic("pmap_demote_DMAP: PDE failed");
9637 if (changed && invalidate)
9638 pmap_invalidate_page(kernel_pmap, va);
9639 PMAP_UNLOCK(kernel_pmap);
9644 * Perform the pmap work for mincore(2). If the page is not both referenced and
9645 * modified by this pmap, returns its physical address so that the caller can
9646 * find other mappings.
9649 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9653 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9657 PG_A = pmap_accessed_bit(pmap);
9658 PG_M = pmap_modified_bit(pmap);
9659 PG_V = pmap_valid_bit(pmap);
9660 PG_RW = pmap_rw_bit(pmap);
9666 pdpe = pmap_pdpe(pmap, addr);
9669 if ((*pdpe & PG_V) != 0) {
9670 if ((*pdpe & PG_PS) != 0) {
9672 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9674 val = MINCORE_PSIND(2);
9676 pdep = pmap_pde(pmap, addr);
9677 if (pdep != NULL && (*pdep & PG_V) != 0) {
9678 if ((*pdep & PG_PS) != 0) {
9680 /* Compute the physical address of the 4KB page. */
9681 pa = ((pte & PG_PS_FRAME) | (addr &
9682 PDRMASK)) & PG_FRAME;
9683 val = MINCORE_PSIND(1);
9685 pte = *pmap_pde_to_pte(pdep, addr);
9686 pa = pte & PG_FRAME;
9692 if ((pte & PG_V) != 0) {
9693 val |= MINCORE_INCORE;
9694 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9695 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9696 if ((pte & PG_A) != 0)
9697 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9699 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9700 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9701 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9710 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9712 uint32_t gen, new_gen, pcid_next;
9714 CRITICAL_ASSERT(curthread);
9715 gen = PCPU_GET(pcid_gen);
9716 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9717 return (pti ? 0 : CR3_PCID_SAVE);
9718 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9719 return (CR3_PCID_SAVE);
9720 pcid_next = PCPU_GET(pcid_next);
9721 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9722 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9723 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9724 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9725 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9729 PCPU_SET(pcid_gen, new_gen);
9730 pcid_next = PMAP_PCID_KERN + 1;
9734 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9735 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9736 PCPU_SET(pcid_next, pcid_next + 1);
9741 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9745 cached = pmap_pcid_alloc(pmap, cpuid);
9746 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9747 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9748 pmap->pm_pcids[cpuid].pm_pcid));
9749 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9750 pmap == kernel_pmap,
9751 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9752 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9757 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9760 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9761 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9765 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9768 uint64_t cached, cr3, kcr3, ucr3;
9770 KASSERT((read_rflags() & PSL_I) == 0,
9771 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9773 /* See the comment in pmap_invalidate_page_pcid(). */
9774 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9775 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9776 old_pmap = PCPU_GET(curpmap);
9777 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9778 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9781 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9783 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9784 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9785 PCPU_SET(curpmap, pmap);
9786 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9787 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9790 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9791 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9793 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9794 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9796 counter_u64_add(pcid_save_cnt, 1);
9798 pmap_activate_sw_pti_post(td, pmap);
9802 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9805 uint64_t cached, cr3;
9807 KASSERT((read_rflags() & PSL_I) == 0,
9808 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9810 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9812 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9813 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9815 PCPU_SET(curpmap, pmap);
9817 counter_u64_add(pcid_save_cnt, 1);
9821 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9822 u_int cpuid __unused)
9825 load_cr3(pmap->pm_cr3);
9826 PCPU_SET(curpmap, pmap);
9830 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9831 u_int cpuid __unused)
9834 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9835 PCPU_SET(kcr3, pmap->pm_cr3);
9836 PCPU_SET(ucr3, pmap->pm_ucr3);
9837 pmap_activate_sw_pti_post(td, pmap);
9840 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9844 if (pmap_pcid_enabled && pti)
9845 return (pmap_activate_sw_pcid_pti);
9846 else if (pmap_pcid_enabled && !pti)
9847 return (pmap_activate_sw_pcid_nopti);
9848 else if (!pmap_pcid_enabled && pti)
9849 return (pmap_activate_sw_nopcid_pti);
9850 else /* if (!pmap_pcid_enabled && !pti) */
9851 return (pmap_activate_sw_nopcid_nopti);
9855 pmap_activate_sw(struct thread *td)
9857 pmap_t oldpmap, pmap;
9860 oldpmap = PCPU_GET(curpmap);
9861 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9862 if (oldpmap == pmap) {
9863 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9867 cpuid = PCPU_GET(cpuid);
9869 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9871 CPU_SET(cpuid, &pmap->pm_active);
9873 pmap_activate_sw_mode(td, pmap, cpuid);
9875 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9877 CPU_CLR(cpuid, &oldpmap->pm_active);
9882 pmap_activate(struct thread *td)
9885 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9886 * invalidate_all IPI, which checks for curpmap ==
9887 * smp_tlb_pmap. The below sequence of operations has a
9888 * window where %CR3 is loaded with the new pmap's PML4
9889 * address, but the curpmap value has not yet been updated.
9890 * This causes the invltlb IPI handler, which is called
9891 * between the updates, to execute as a NOP, which leaves
9892 * stale TLB entries.
9894 * Note that the most common use of pmap_activate_sw(), from
9895 * a context switch, is immune to this race, because
9896 * interrupts are disabled (while the thread lock is owned),
9897 * so the IPI is delayed until after curpmap is updated. Protect
9898 * other callers in a similar way, by disabling interrupts
9899 * around the %cr3 register reload and curpmap assignment.
9902 pmap_activate_sw(td);
9907 pmap_activate_boot(pmap_t pmap)
9913 * kernel_pmap must be never deactivated, and we ensure that
9914 * by never activating it at all.
9916 MPASS(pmap != kernel_pmap);
9918 cpuid = PCPU_GET(cpuid);
9920 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9922 CPU_SET(cpuid, &pmap->pm_active);
9924 PCPU_SET(curpmap, pmap);
9926 kcr3 = pmap->pm_cr3;
9927 if (pmap_pcid_enabled)
9928 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9932 PCPU_SET(kcr3, kcr3);
9933 PCPU_SET(ucr3, PMAP_NO_CR3);
9937 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9942 * Increase the starting virtual address of the given mapping if a
9943 * different alignment might result in more superpage mappings.
9946 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9947 vm_offset_t *addr, vm_size_t size)
9949 vm_offset_t superpage_offset;
9953 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9954 offset += ptoa(object->pg_color);
9955 superpage_offset = offset & PDRMASK;
9956 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9957 (*addr & PDRMASK) == superpage_offset)
9959 if ((*addr & PDRMASK) < superpage_offset)
9960 *addr = (*addr & ~PDRMASK) + superpage_offset;
9962 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9966 static unsigned long num_dirty_emulations;
9967 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9968 &num_dirty_emulations, 0, NULL);
9970 static unsigned long num_accessed_emulations;
9971 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9972 &num_accessed_emulations, 0, NULL);
9974 static unsigned long num_superpage_accessed_emulations;
9975 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9976 &num_superpage_accessed_emulations, 0, NULL);
9978 static unsigned long ad_emulation_superpage_promotions;
9979 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9980 &ad_emulation_superpage_promotions, 0, NULL);
9981 #endif /* INVARIANTS */
9984 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9987 struct rwlock *lock;
9988 #if VM_NRESERVLEVEL > 0
9992 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9994 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9995 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9997 if (!pmap_emulate_ad_bits(pmap))
10000 PG_A = pmap_accessed_bit(pmap);
10001 PG_M = pmap_modified_bit(pmap);
10002 PG_V = pmap_valid_bit(pmap);
10003 PG_RW = pmap_rw_bit(pmap);
10009 pde = pmap_pde(pmap, va);
10010 if (pde == NULL || (*pde & PG_V) == 0)
10013 if ((*pde & PG_PS) != 0) {
10014 if (ftype == VM_PROT_READ) {
10016 atomic_add_long(&num_superpage_accessed_emulations, 1);
10024 pte = pmap_pde_to_pte(pde, va);
10025 if ((*pte & PG_V) == 0)
10028 if (ftype == VM_PROT_WRITE) {
10029 if ((*pte & PG_RW) == 0)
10032 * Set the modified and accessed bits simultaneously.
10034 * Intel EPT PTEs that do software emulation of A/D bits map
10035 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
10036 * An EPT misconfiguration is triggered if the PTE is writable
10037 * but not readable (WR=10). This is avoided by setting PG_A
10038 * and PG_M simultaneously.
10040 *pte |= PG_M | PG_A;
10045 #if VM_NRESERVLEVEL > 0
10046 /* try to promote the mapping */
10047 if (va < VM_MAXUSER_ADDRESS)
10048 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
10052 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
10054 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
10055 pmap_ps_enabled(pmap) &&
10056 (m->flags & PG_FICTITIOUS) == 0 &&
10057 vm_reserv_level_iffullpop(m) == 0) {
10058 pmap_promote_pde(pmap, pde, va, &lock);
10060 atomic_add_long(&ad_emulation_superpage_promotions, 1);
10066 if (ftype == VM_PROT_WRITE)
10067 atomic_add_long(&num_dirty_emulations, 1);
10069 atomic_add_long(&num_accessed_emulations, 1);
10071 rv = 0; /* success */
10080 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
10082 pml4_entry_t *pml4;
10085 pt_entry_t *pte, PG_V;
10089 PG_V = pmap_valid_bit(pmap);
10092 pml4 = pmap_pml4e(pmap, va);
10095 ptr[idx++] = *pml4;
10096 if ((*pml4 & PG_V) == 0)
10099 pdp = pmap_pml4e_to_pdpe(pml4, va);
10101 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
10104 pde = pmap_pdpe_to_pde(pdp, va);
10106 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
10109 pte = pmap_pde_to_pte(pde, va);
10118 * Get the kernel virtual address of a set of physical pages. If there are
10119 * physical addresses not covered by the DMAP perform a transient mapping
10120 * that will be removed when calling pmap_unmap_io_transient.
10122 * \param page The pages the caller wishes to obtain the virtual
10123 * address on the kernel memory map.
10124 * \param vaddr On return contains the kernel virtual memory address
10125 * of the pages passed in the page parameter.
10126 * \param count Number of pages passed in.
10127 * \param can_fault TRUE if the thread using the mapped pages can take
10128 * page faults, FALSE otherwise.
10130 * \returns TRUE if the caller must call pmap_unmap_io_transient when
10131 * finished or FALSE otherwise.
10135 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10136 boolean_t can_fault)
10139 boolean_t needs_mapping;
10141 int cache_bits, error __unused, i;
10144 * Allocate any KVA space that we need, this is done in a separate
10145 * loop to prevent calling vmem_alloc while pinned.
10147 needs_mapping = FALSE;
10148 for (i = 0; i < count; i++) {
10149 paddr = VM_PAGE_TO_PHYS(page[i]);
10150 if (__predict_false(paddr >= dmaplimit)) {
10151 error = vmem_alloc(kernel_arena, PAGE_SIZE,
10152 M_BESTFIT | M_WAITOK, &vaddr[i]);
10153 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
10154 needs_mapping = TRUE;
10156 vaddr[i] = PHYS_TO_DMAP(paddr);
10160 /* Exit early if everything is covered by the DMAP */
10161 if (!needs_mapping)
10165 * NB: The sequence of updating a page table followed by accesses
10166 * to the corresponding pages used in the !DMAP case is subject to
10167 * the situation described in the "AMD64 Architecture Programmer's
10168 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
10169 * Coherency Considerations". Therefore, issuing the INVLPG right
10170 * after modifying the PTE bits is crucial.
10174 for (i = 0; i < count; i++) {
10175 paddr = VM_PAGE_TO_PHYS(page[i]);
10176 if (paddr >= dmaplimit) {
10179 * Slow path, since we can get page faults
10180 * while mappings are active don't pin the
10181 * thread to the CPU and instead add a global
10182 * mapping visible to all CPUs.
10184 pmap_qenter(vaddr[i], &page[i], 1);
10186 pte = vtopte(vaddr[i]);
10187 cache_bits = pmap_cache_bits(kernel_pmap,
10188 page[i]->md.pat_mode, 0);
10189 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
10196 return (needs_mapping);
10200 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10201 boolean_t can_fault)
10208 for (i = 0; i < count; i++) {
10209 paddr = VM_PAGE_TO_PHYS(page[i]);
10210 if (paddr >= dmaplimit) {
10212 pmap_qremove(vaddr[i], 1);
10213 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
10219 pmap_quick_enter_page(vm_page_t m)
10223 paddr = VM_PAGE_TO_PHYS(m);
10224 if (paddr < dmaplimit)
10225 return (PHYS_TO_DMAP(paddr));
10226 mtx_lock_spin(&qframe_mtx);
10227 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
10228 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
10229 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
10234 pmap_quick_remove_page(vm_offset_t addr)
10237 if (addr != qframe)
10239 pte_store(vtopte(qframe), 0);
10241 mtx_unlock_spin(&qframe_mtx);
10245 * Pdp pages from the large map are managed differently from either
10246 * kernel or user page table pages. They are permanently allocated at
10247 * initialization time, and their reference count is permanently set to
10248 * zero. The pml4 entries pointing to those pages are copied into
10249 * each allocated pmap.
10251 * In contrast, pd and pt pages are managed like user page table
10252 * pages. They are dynamically allocated, and their reference count
10253 * represents the number of valid entries within the page.
10256 pmap_large_map_getptp_unlocked(void)
10258 return (pmap_alloc_pt_page(kernel_pmap, 0, VM_ALLOC_ZERO));
10262 pmap_large_map_getptp(void)
10266 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
10267 m = pmap_large_map_getptp_unlocked();
10269 PMAP_UNLOCK(kernel_pmap);
10271 PMAP_LOCK(kernel_pmap);
10272 /* Callers retry. */
10277 static pdp_entry_t *
10278 pmap_large_map_pdpe(vm_offset_t va)
10280 vm_pindex_t pml4_idx;
10283 pml4_idx = pmap_pml4e_index(va);
10284 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
10285 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
10287 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10288 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
10289 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
10290 "LMSPML4I %#jx lm_ents %d",
10291 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10292 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
10293 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
10296 static pd_entry_t *
10297 pmap_large_map_pde(vm_offset_t va)
10304 pdpe = pmap_large_map_pdpe(va);
10306 m = pmap_large_map_getptp();
10309 mphys = VM_PAGE_TO_PHYS(m);
10310 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10312 MPASS((*pdpe & X86_PG_PS) == 0);
10313 mphys = *pdpe & PG_FRAME;
10315 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10318 static pt_entry_t *
10319 pmap_large_map_pte(vm_offset_t va)
10326 pde = pmap_large_map_pde(va);
10328 m = pmap_large_map_getptp();
10331 mphys = VM_PAGE_TO_PHYS(m);
10332 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10333 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10335 MPASS((*pde & X86_PG_PS) == 0);
10336 mphys = *pde & PG_FRAME;
10338 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10342 pmap_large_map_kextract(vm_offset_t va)
10344 pdp_entry_t *pdpe, pdp;
10345 pd_entry_t *pde, pd;
10346 pt_entry_t *pte, pt;
10348 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10349 ("not largemap range %#lx", (u_long)va));
10350 pdpe = pmap_large_map_pdpe(va);
10352 KASSERT((pdp & X86_PG_V) != 0,
10353 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10354 (u_long)pdpe, pdp));
10355 if ((pdp & X86_PG_PS) != 0) {
10356 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10357 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10358 (u_long)pdpe, pdp));
10359 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10361 pde = pmap_pdpe_to_pde(pdpe, va);
10363 KASSERT((pd & X86_PG_V) != 0,
10364 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10365 if ((pd & X86_PG_PS) != 0)
10366 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10367 pte = pmap_pde_to_pte(pde, va);
10369 KASSERT((pt & X86_PG_V) != 0,
10370 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10371 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10375 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10376 vmem_addr_t *vmem_res)
10380 * Large mappings are all but static. Consequently, there
10381 * is no point in waiting for an earlier allocation to be
10384 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10385 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10389 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10390 vm_memattr_t mattr)
10395 vm_offset_t va, inc;
10396 vmem_addr_t vmem_res;
10400 if (len == 0 || spa + len < spa)
10403 /* See if DMAP can serve. */
10404 if (spa + len <= dmaplimit) {
10405 va = PHYS_TO_DMAP(spa);
10406 *addr = (void *)va;
10407 return (pmap_change_attr(va, len, mattr));
10411 * No, allocate KVA. Fit the address with best possible
10412 * alignment for superpages. Fall back to worse align if
10416 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10417 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10418 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10420 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10422 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10425 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10430 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10431 * in the pagetable to minimize flushing. No need to
10432 * invalidate TLB, since we only update invalid entries.
10434 PMAP_LOCK(kernel_pmap);
10435 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10437 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10438 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10439 pdpe = pmap_large_map_pdpe(va);
10441 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10442 X86_PG_V | X86_PG_A | pg_nx |
10443 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10445 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10446 (va & PDRMASK) == 0) {
10447 pde = pmap_large_map_pde(va);
10449 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10450 X86_PG_V | X86_PG_A | pg_nx |
10451 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10452 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10456 pte = pmap_large_map_pte(va);
10458 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10459 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10461 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10466 PMAP_UNLOCK(kernel_pmap);
10469 *addr = (void *)vmem_res;
10474 pmap_large_unmap(void *svaa, vm_size_t len)
10476 vm_offset_t sva, va;
10478 pdp_entry_t *pdpe, pdp;
10479 pd_entry_t *pde, pd;
10482 struct spglist spgf;
10484 sva = (vm_offset_t)svaa;
10485 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10486 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10490 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10491 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10492 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10493 PMAP_LOCK(kernel_pmap);
10494 for (va = sva; va < sva + len; va += inc) {
10495 pdpe = pmap_large_map_pdpe(va);
10497 KASSERT((pdp & X86_PG_V) != 0,
10498 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10499 (u_long)pdpe, pdp));
10500 if ((pdp & X86_PG_PS) != 0) {
10501 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10502 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10503 (u_long)pdpe, pdp));
10504 KASSERT((va & PDPMASK) == 0,
10505 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10506 (u_long)pdpe, pdp));
10507 KASSERT(va + NBPDP <= sva + len,
10508 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10509 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10510 (u_long)pdpe, pdp, len));
10515 pde = pmap_pdpe_to_pde(pdpe, va);
10517 KASSERT((pd & X86_PG_V) != 0,
10518 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10520 if ((pd & X86_PG_PS) != 0) {
10521 KASSERT((va & PDRMASK) == 0,
10522 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10524 KASSERT(va + NBPDR <= sva + len,
10525 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10526 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10530 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10532 if (m->ref_count == 0) {
10534 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10538 pte = pmap_pde_to_pte(pde, va);
10539 KASSERT((*pte & X86_PG_V) != 0,
10540 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10541 (u_long)pte, *pte));
10544 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10546 if (m->ref_count == 0) {
10548 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10549 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10551 if (m->ref_count == 0) {
10553 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10557 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10558 PMAP_UNLOCK(kernel_pmap);
10559 vm_page_free_pages_toq(&spgf, false);
10560 vmem_free(large_vmem, sva, len);
10564 pmap_large_map_wb_fence_mfence(void)
10571 pmap_large_map_wb_fence_atomic(void)
10574 atomic_thread_fence_seq_cst();
10578 pmap_large_map_wb_fence_nop(void)
10582 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10585 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10586 return (pmap_large_map_wb_fence_mfence);
10587 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10588 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10589 return (pmap_large_map_wb_fence_atomic);
10591 /* clflush is strongly enough ordered */
10592 return (pmap_large_map_wb_fence_nop);
10596 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10599 for (; len > 0; len -= cpu_clflush_line_size,
10600 va += cpu_clflush_line_size)
10605 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10608 for (; len > 0; len -= cpu_clflush_line_size,
10609 va += cpu_clflush_line_size)
10614 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10617 for (; len > 0; len -= cpu_clflush_line_size,
10618 va += cpu_clflush_line_size)
10623 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10627 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10630 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10631 return (pmap_large_map_flush_range_clwb);
10632 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10633 return (pmap_large_map_flush_range_clflushopt);
10634 else if ((cpu_feature & CPUID_CLFSH) != 0)
10635 return (pmap_large_map_flush_range_clflush);
10637 return (pmap_large_map_flush_range_nop);
10641 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10643 volatile u_long *pe;
10649 for (va = sva; va < eva; va += inc) {
10651 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10652 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10654 if ((p & X86_PG_PS) != 0)
10658 pe = (volatile u_long *)pmap_large_map_pde(va);
10660 if ((p & X86_PG_PS) != 0)
10664 pe = (volatile u_long *)pmap_large_map_pte(va);
10668 seen_other = false;
10670 if ((p & X86_PG_AVAIL1) != 0) {
10672 * Spin-wait for the end of a parallel
10679 * If we saw other write-back
10680 * occuring, we cannot rely on PG_M to
10681 * indicate state of the cache. The
10682 * PG_M bit is cleared before the
10683 * flush to avoid ignoring new writes,
10684 * and writes which are relevant for
10685 * us might happen after.
10691 if ((p & X86_PG_M) != 0 || seen_other) {
10692 if (!atomic_fcmpset_long(pe, &p,
10693 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10695 * If we saw PG_M without
10696 * PG_AVAIL1, and then on the
10697 * next attempt we do not
10698 * observe either PG_M or
10699 * PG_AVAIL1, the other
10700 * write-back started after us
10701 * and finished before us. We
10702 * can rely on it doing our
10706 pmap_large_map_flush_range(va, inc);
10707 atomic_clear_long(pe, X86_PG_AVAIL1);
10716 * Write-back cache lines for the given address range.
10718 * Must be called only on the range or sub-range returned from
10719 * pmap_large_map(). Must not be called on the coalesced ranges.
10721 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10722 * instructions support.
10725 pmap_large_map_wb(void *svap, vm_size_t len)
10727 vm_offset_t eva, sva;
10729 sva = (vm_offset_t)svap;
10731 pmap_large_map_wb_fence();
10732 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10733 pmap_large_map_flush_range(sva, len);
10735 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10736 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10737 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10738 pmap_large_map_wb_large(sva, eva);
10740 pmap_large_map_wb_fence();
10744 pmap_pti_alloc_page(void)
10748 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10749 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10750 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10755 pmap_pti_free_page(vm_page_t m)
10758 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10759 if (!vm_page_unwire_noq(m))
10761 vm_page_free_zero(m);
10766 pmap_pti_init(void)
10775 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10776 VM_OBJECT_WLOCK(pti_obj);
10777 pml4_pg = pmap_pti_alloc_page();
10778 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10779 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10780 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10781 pdpe = pmap_pti_pdpe(va);
10782 pmap_pti_wire_pte(pdpe);
10784 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10785 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10786 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10787 sizeof(struct gate_descriptor) * NIDT, false);
10789 /* Doublefault stack IST 1 */
10790 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10791 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10792 /* NMI stack IST 2 */
10793 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10794 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10795 /* MC# stack IST 3 */
10796 va = __pcpu[i].pc_common_tss.tss_ist3 +
10797 sizeof(struct nmi_pcpu);
10798 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10799 /* DB# stack IST 4 */
10800 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10801 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10803 pmap_pti_add_kva_locked((vm_offset_t)KERNSTART, (vm_offset_t)etext,
10805 pti_finalized = true;
10806 VM_OBJECT_WUNLOCK(pti_obj);
10810 pmap_cpu_init(void *arg __unused)
10812 CPU_COPY(&all_cpus, &kernel_pmap->pm_active);
10815 SYSINIT(pmap_cpu, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_cpu_init, NULL);
10817 static pdp_entry_t *
10818 pmap_pti_pdpe(vm_offset_t va)
10820 pml4_entry_t *pml4e;
10823 vm_pindex_t pml4_idx;
10826 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10828 pml4_idx = pmap_pml4e_index(va);
10829 pml4e = &pti_pml4[pml4_idx];
10833 panic("pml4 alloc after finalization\n");
10834 m = pmap_pti_alloc_page();
10836 pmap_pti_free_page(m);
10837 mphys = *pml4e & ~PAGE_MASK;
10839 mphys = VM_PAGE_TO_PHYS(m);
10840 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10843 mphys = *pml4e & ~PAGE_MASK;
10845 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10850 pmap_pti_wire_pte(void *pte)
10854 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10855 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10860 pmap_pti_unwire_pde(void *pde, bool only_ref)
10864 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10865 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10866 MPASS(m->ref_count > 0);
10867 MPASS(only_ref || m->ref_count > 1);
10868 pmap_pti_free_page(m);
10872 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10877 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10878 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10879 MPASS(m->ref_count > 0);
10880 if (pmap_pti_free_page(m)) {
10881 pde = pmap_pti_pde(va);
10882 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10884 pmap_pti_unwire_pde(pde, false);
10888 static pd_entry_t *
10889 pmap_pti_pde(vm_offset_t va)
10894 vm_pindex_t pd_idx;
10897 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10899 pdpe = pmap_pti_pdpe(va);
10901 m = pmap_pti_alloc_page();
10903 pmap_pti_free_page(m);
10904 MPASS((*pdpe & X86_PG_PS) == 0);
10905 mphys = *pdpe & ~PAGE_MASK;
10907 mphys = VM_PAGE_TO_PHYS(m);
10908 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10911 MPASS((*pdpe & X86_PG_PS) == 0);
10912 mphys = *pdpe & ~PAGE_MASK;
10915 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10916 pd_idx = pmap_pde_index(va);
10921 static pt_entry_t *
10922 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10929 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10931 pde = pmap_pti_pde(va);
10932 if (unwire_pde != NULL) {
10933 *unwire_pde = true;
10934 pmap_pti_wire_pte(pde);
10937 m = pmap_pti_alloc_page();
10939 pmap_pti_free_page(m);
10940 MPASS((*pde & X86_PG_PS) == 0);
10941 mphys = *pde & ~(PAGE_MASK | pg_nx);
10943 mphys = VM_PAGE_TO_PHYS(m);
10944 *pde = mphys | X86_PG_RW | X86_PG_V;
10945 if (unwire_pde != NULL)
10946 *unwire_pde = false;
10949 MPASS((*pde & X86_PG_PS) == 0);
10950 mphys = *pde & ~(PAGE_MASK | pg_nx);
10953 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10954 pte += pmap_pte_index(va);
10960 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10964 pt_entry_t *pte, ptev;
10967 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10969 sva = trunc_page(sva);
10970 MPASS(sva > VM_MAXUSER_ADDRESS);
10971 eva = round_page(eva);
10973 for (; sva < eva; sva += PAGE_SIZE) {
10974 pte = pmap_pti_pte(sva, &unwire_pde);
10975 pa = pmap_kextract(sva);
10976 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10977 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10978 VM_MEMATTR_DEFAULT, FALSE);
10980 pte_store(pte, ptev);
10981 pmap_pti_wire_pte(pte);
10983 KASSERT(!pti_finalized,
10984 ("pti overlap after fin %#lx %#lx %#lx",
10986 KASSERT(*pte == ptev,
10987 ("pti non-identical pte after fin %#lx %#lx %#lx",
10991 pde = pmap_pti_pde(sva);
10992 pmap_pti_unwire_pde(pde, true);
10998 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
11003 VM_OBJECT_WLOCK(pti_obj);
11004 pmap_pti_add_kva_locked(sva, eva, exec);
11005 VM_OBJECT_WUNLOCK(pti_obj);
11009 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
11016 sva = rounddown2(sva, PAGE_SIZE);
11017 MPASS(sva > VM_MAXUSER_ADDRESS);
11018 eva = roundup2(eva, PAGE_SIZE);
11020 VM_OBJECT_WLOCK(pti_obj);
11021 for (va = sva; va < eva; va += PAGE_SIZE) {
11022 pte = pmap_pti_pte(va, NULL);
11023 KASSERT((*pte & X86_PG_V) != 0,
11024 ("invalid pte va %#lx pte %#lx pt %#lx", va,
11025 (u_long)pte, *pte));
11027 pmap_pti_unwire_pte(pte, va);
11029 pmap_invalidate_range(kernel_pmap, sva, eva);
11030 VM_OBJECT_WUNLOCK(pti_obj);
11034 pkru_dup_range(void *ctx __unused, void *data)
11036 struct pmap_pkru_range *node, *new_node;
11038 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11039 if (new_node == NULL)
11042 memcpy(new_node, node, sizeof(*node));
11047 pkru_free_range(void *ctx __unused, void *node)
11050 uma_zfree(pmap_pkru_ranges_zone, node);
11054 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11057 struct pmap_pkru_range *ppr;
11060 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11061 MPASS(pmap->pm_type == PT_X86);
11062 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11063 if ((flags & AMD64_PKRU_EXCL) != 0 &&
11064 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
11066 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11069 ppr->pkru_keyidx = keyidx;
11070 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
11071 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
11073 uma_zfree(pmap_pkru_ranges_zone, ppr);
11078 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11081 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11082 MPASS(pmap->pm_type == PT_X86);
11083 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11084 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
11088 pmap_pkru_deassign_all(pmap_t pmap)
11091 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11092 if (pmap->pm_type == PT_X86 &&
11093 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
11094 rangeset_remove_all(&pmap->pm_pkru);
11098 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11100 struct pmap_pkru_range *ppr, *prev_ppr;
11103 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11104 if (pmap->pm_type != PT_X86 ||
11105 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11106 sva >= VM_MAXUSER_ADDRESS)
11108 MPASS(eva <= VM_MAXUSER_ADDRESS);
11109 for (va = sva; va < eva; prev_ppr = ppr) {
11110 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11113 else if ((ppr == NULL) ^ (prev_ppr == NULL))
11119 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
11121 va = ppr->pkru_rs_el.re_end;
11127 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
11129 struct pmap_pkru_range *ppr;
11131 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11132 if (pmap->pm_type != PT_X86 ||
11133 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11134 va >= VM_MAXUSER_ADDRESS)
11136 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11138 return (X86_PG_PKU(ppr->pkru_keyidx));
11143 pred_pkru_on_remove(void *ctx __unused, void *r)
11145 struct pmap_pkru_range *ppr;
11148 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
11152 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11155 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11156 if (pmap->pm_type == PT_X86 &&
11157 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
11158 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
11159 pred_pkru_on_remove);
11164 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
11167 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
11168 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
11169 MPASS(dst_pmap->pm_type == PT_X86);
11170 MPASS(src_pmap->pm_type == PT_X86);
11171 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11172 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
11174 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
11178 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11181 pml4_entry_t *pml4e;
11183 pd_entry_t newpde, ptpaddr, *pde;
11184 pt_entry_t newpte, *ptep, pte;
11185 vm_offset_t va, va_next;
11188 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11189 MPASS(pmap->pm_type == PT_X86);
11190 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
11192 for (changed = false, va = sva; va < eva; va = va_next) {
11193 pml4e = pmap_pml4e(pmap, va);
11194 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
11195 va_next = (va + NBPML4) & ~PML4MASK;
11201 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
11202 if ((*pdpe & X86_PG_V) == 0) {
11203 va_next = (va + NBPDP) & ~PDPMASK;
11209 va_next = (va + NBPDR) & ~PDRMASK;
11213 pde = pmap_pdpe_to_pde(pdpe, va);
11218 MPASS((ptpaddr & X86_PG_V) != 0);
11219 if ((ptpaddr & PG_PS) != 0) {
11220 if (va + NBPDR == va_next && eva >= va_next) {
11221 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
11222 X86_PG_PKU(keyidx);
11223 if (newpde != ptpaddr) {
11228 } else if (!pmap_demote_pde(pmap, pde, va)) {
11236 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
11237 ptep++, va += PAGE_SIZE) {
11239 if ((pte & X86_PG_V) == 0)
11241 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
11242 if (newpte != pte) {
11249 pmap_invalidate_range(pmap, sva, eva);
11253 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11254 u_int keyidx, int flags)
11257 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
11258 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
11260 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
11262 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
11268 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11273 sva = trunc_page(sva);
11274 eva = round_page(eva);
11275 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
11280 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
11282 pmap_pkru_update_range(pmap, sva, eva, keyidx);
11284 if (error != ENOMEM)
11292 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11296 sva = trunc_page(sva);
11297 eva = round_page(eva);
11298 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
11303 error = pmap_pkru_deassign(pmap, sva, eva);
11305 pmap_pkru_update_range(pmap, sva, eva, 0);
11307 if (error != ENOMEM)
11316 pmap_kasan_enter_alloc_4k(void)
11320 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
11323 panic("%s: no memory to grow shadow map", __func__);
11328 pmap_kasan_enter_alloc_2m(void)
11330 return (vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO,
11331 NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT));
11335 * Grow the shadow map by at least one 4KB page at the specified address. Use
11336 * 2MB pages when possible.
11339 pmap_kasan_enter(vm_offset_t va)
11346 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11348 pdpe = pmap_pdpe(kernel_pmap, va);
11349 if ((*pdpe & X86_PG_V) == 0) {
11350 m = pmap_kasan_enter_alloc_4k();
11351 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11354 pde = pmap_pdpe_to_pde(pdpe, va);
11355 if ((*pde & X86_PG_V) == 0) {
11356 m = pmap_kasan_enter_alloc_2m();
11358 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11359 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx);
11361 m = pmap_kasan_enter_alloc_4k();
11362 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11366 if ((*pde & X86_PG_PS) != 0)
11368 pte = pmap_pde_to_pte(pde, va);
11369 if ((*pte & X86_PG_V) != 0)
11371 m = pmap_kasan_enter_alloc_4k();
11372 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11373 X86_PG_M | X86_PG_A | pg_nx);
11379 pmap_kmsan_enter_alloc_4k(void)
11383 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
11386 panic("%s: no memory to grow shadow map", __func__);
11391 pmap_kmsan_enter_alloc_2m(void)
11393 return (vm_page_alloc_noobj_contig(VM_ALLOC_ZERO | VM_ALLOC_WIRED,
11394 NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT));
11398 * Grow the shadow or origin maps by at least one 4KB page at the specified
11399 * address. Use 2MB pages when possible.
11402 pmap_kmsan_enter(vm_offset_t va)
11409 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11411 pdpe = pmap_pdpe(kernel_pmap, va);
11412 if ((*pdpe & X86_PG_V) == 0) {
11413 m = pmap_kmsan_enter_alloc_4k();
11414 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11417 pde = pmap_pdpe_to_pde(pdpe, va);
11418 if ((*pde & X86_PG_V) == 0) {
11419 m = pmap_kmsan_enter_alloc_2m();
11421 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11422 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx);
11424 m = pmap_kmsan_enter_alloc_4k();
11425 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11429 if ((*pde & X86_PG_PS) != 0)
11431 pte = pmap_pde_to_pte(pde, va);
11432 if ((*pte & X86_PG_V) != 0)
11434 m = pmap_kmsan_enter_alloc_4k();
11435 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11436 X86_PG_M | X86_PG_A | pg_nx);
11441 * Track a range of the kernel's virtual address space that is contiguous
11442 * in various mapping attributes.
11444 struct pmap_kernel_map_range {
11453 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11459 if (eva <= range->sva)
11462 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11463 for (i = 0; i < PAT_INDEX_SIZE; i++)
11464 if (pat_index[i] == pat_idx)
11468 case PAT_WRITE_BACK:
11471 case PAT_WRITE_THROUGH:
11474 case PAT_UNCACHEABLE:
11480 case PAT_WRITE_PROTECTED:
11483 case PAT_WRITE_COMBINING:
11487 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11488 __func__, pat_idx, range->sva, eva);
11493 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11495 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11496 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11497 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11498 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11499 mode, range->pdpes, range->pdes, range->ptes);
11501 /* Reset to sentinel value. */
11502 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11503 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11504 NPDEPG - 1, NPTEPG - 1);
11508 * Determine whether the attributes specified by a page table entry match those
11509 * being tracked by the current range. This is not quite as simple as a direct
11510 * flag comparison since some PAT modes have multiple representations.
11513 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11515 pt_entry_t diff, mask;
11517 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11518 diff = (range->attrs ^ attrs) & mask;
11521 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11522 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11523 pmap_pat_index(kernel_pmap, attrs, true))
11529 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11533 memset(range, 0, sizeof(*range));
11535 range->attrs = attrs;
11539 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11540 * those of the current run, dump the address range and its attributes, and
11544 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11545 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11550 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11552 attrs |= pdpe & pg_nx;
11553 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11554 if ((pdpe & PG_PS) != 0) {
11555 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11556 } else if (pde != 0) {
11557 attrs |= pde & pg_nx;
11558 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11560 if ((pde & PG_PS) != 0) {
11561 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11562 } else if (pte != 0) {
11563 attrs |= pte & pg_nx;
11564 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11565 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11567 /* Canonicalize by always using the PDE PAT bit. */
11568 if ((attrs & X86_PG_PTE_PAT) != 0)
11569 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11572 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11573 sysctl_kmaps_dump(sb, range, va);
11574 sysctl_kmaps_reinit(range, va, attrs);
11579 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11581 struct pmap_kernel_map_range range;
11582 struct sbuf sbuf, *sb;
11583 pml4_entry_t pml4e;
11584 pdp_entry_t *pdp, pdpe;
11585 pd_entry_t *pd, pde;
11586 pt_entry_t *pt, pte;
11589 int error, i, j, k, l;
11591 error = sysctl_wire_old_buffer(req, 0);
11595 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11597 /* Sentinel value. */
11598 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11599 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11600 NPDEPG - 1, NPTEPG - 1);
11603 * Iterate over the kernel page tables without holding the kernel pmap
11604 * lock. Outside of the large map, kernel page table pages are never
11605 * freed, so at worst we will observe inconsistencies in the output.
11606 * Within the large map, ensure that PDP and PD page addresses are
11607 * valid before descending.
11609 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11612 sbuf_printf(sb, "\nRecursive map:\n");
11615 sbuf_printf(sb, "\nDirect map:\n");
11619 sbuf_printf(sb, "\nKASAN shadow map:\n");
11623 case KMSANSHADPML4I:
11624 sbuf_printf(sb, "\nKMSAN shadow map:\n");
11626 case KMSANORIGPML4I:
11627 sbuf_printf(sb, "\nKMSAN origin map:\n");
11631 sbuf_printf(sb, "\nKernel map:\n");
11634 sbuf_printf(sb, "\nLarge map:\n");
11638 /* Convert to canonical form. */
11639 if (sva == 1ul << 47)
11643 pml4e = kernel_pml4[i];
11644 if ((pml4e & X86_PG_V) == 0) {
11645 sva = rounddown2(sva, NBPML4);
11646 sysctl_kmaps_dump(sb, &range, sva);
11650 pa = pml4e & PG_FRAME;
11651 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11653 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11655 if ((pdpe & X86_PG_V) == 0) {
11656 sva = rounddown2(sva, NBPDP);
11657 sysctl_kmaps_dump(sb, &range, sva);
11661 pa = pdpe & PG_FRAME;
11662 if ((pdpe & PG_PS) != 0) {
11663 sva = rounddown2(sva, NBPDP);
11664 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11670 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11671 vm_phys_paddr_to_vm_page(pa) == NULL) {
11673 * Page table pages for the large map may be
11674 * freed. Validate the next-level address
11675 * before descending.
11679 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11681 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11683 if ((pde & X86_PG_V) == 0) {
11684 sva = rounddown2(sva, NBPDR);
11685 sysctl_kmaps_dump(sb, &range, sva);
11689 pa = pde & PG_FRAME;
11690 if ((pde & PG_PS) != 0) {
11691 sva = rounddown2(sva, NBPDR);
11692 sysctl_kmaps_check(sb, &range, sva,
11693 pml4e, pdpe, pde, 0);
11698 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11699 vm_phys_paddr_to_vm_page(pa) == NULL) {
11701 * Page table pages for the large map
11702 * may be freed. Validate the
11703 * next-level address before descending.
11707 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11709 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11710 sva += PAGE_SIZE) {
11712 if ((pte & X86_PG_V) == 0) {
11713 sysctl_kmaps_dump(sb, &range,
11717 sysctl_kmaps_check(sb, &range, sva,
11718 pml4e, pdpe, pde, pte);
11725 error = sbuf_finish(sb);
11729 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11730 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
11731 NULL, 0, sysctl_kmaps, "A",
11732 "Dump kernel address layout");
11735 DB_SHOW_COMMAND(pte, pmap_print_pte)
11738 pml5_entry_t *pml5;
11739 pml4_entry_t *pml4;
11742 pt_entry_t *pte, PG_V;
11746 db_printf("show pte addr\n");
11749 va = (vm_offset_t)addr;
11751 if (kdb_thread != NULL)
11752 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11754 pmap = PCPU_GET(curpmap);
11756 PG_V = pmap_valid_bit(pmap);
11757 db_printf("VA 0x%016lx", va);
11759 if (pmap_is_la57(pmap)) {
11760 pml5 = pmap_pml5e(pmap, va);
11761 db_printf(" pml5e 0x%016lx", *pml5);
11762 if ((*pml5 & PG_V) == 0) {
11766 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11768 pml4 = pmap_pml4e(pmap, va);
11770 db_printf(" pml4e 0x%016lx", *pml4);
11771 if ((*pml4 & PG_V) == 0) {
11775 pdp = pmap_pml4e_to_pdpe(pml4, va);
11776 db_printf(" pdpe 0x%016lx", *pdp);
11777 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11781 pde = pmap_pdpe_to_pde(pdp, va);
11782 db_printf(" pde 0x%016lx", *pde);
11783 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11787 pte = pmap_pde_to_pte(pde, va);
11788 db_printf(" pte 0x%016lx\n", *pte);
11791 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11796 a = (vm_paddr_t)addr;
11797 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11799 db_printf("show phys2dmap addr\n");
11804 ptpages_show_page(int level, int idx, vm_page_t pg)
11806 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11807 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11811 ptpages_show_complain(int level, int idx, uint64_t pte)
11813 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11817 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11819 vm_page_t pg3, pg2, pg1;
11820 pml4_entry_t *pml4;
11825 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11826 for (i4 = 0; i4 < num_entries; i4++) {
11827 if ((pml4[i4] & PG_V) == 0)
11829 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11831 ptpages_show_complain(3, i4, pml4[i4]);
11834 ptpages_show_page(3, i4, pg3);
11835 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11836 for (i3 = 0; i3 < NPDPEPG; i3++) {
11837 if ((pdp[i3] & PG_V) == 0)
11839 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11841 ptpages_show_complain(2, i3, pdp[i3]);
11844 ptpages_show_page(2, i3, pg2);
11845 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11846 for (i2 = 0; i2 < NPDEPG; i2++) {
11847 if ((pd[i2] & PG_V) == 0)
11849 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11851 ptpages_show_complain(1, i2, pd[i2]);
11854 ptpages_show_page(1, i2, pg1);
11860 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11864 pml5_entry_t *pml5;
11869 pmap = (pmap_t)addr;
11871 pmap = PCPU_GET(curpmap);
11873 PG_V = pmap_valid_bit(pmap);
11875 if (pmap_is_la57(pmap)) {
11876 pml5 = pmap->pm_pmltop;
11877 for (i5 = 0; i5 < NUPML5E; i5++) {
11878 if ((pml5[i5] & PG_V) == 0)
11880 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11882 ptpages_show_complain(4, i5, pml5[i5]);
11885 ptpages_show_page(4, i5, pg);
11886 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11889 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11890 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);