2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
168 static __inline boolean_t
169 pmap_type_guest(pmap_t pmap)
172 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
175 static __inline boolean_t
176 pmap_emulate_ad_bits(pmap_t pmap)
179 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
182 static __inline pt_entry_t
183 pmap_valid_bit(pmap_t pmap)
187 switch (pmap->pm_type) {
193 if (pmap_emulate_ad_bits(pmap))
194 mask = EPT_PG_EMUL_V;
199 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
205 static __inline pt_entry_t
206 pmap_rw_bit(pmap_t pmap)
210 switch (pmap->pm_type) {
216 if (pmap_emulate_ad_bits(pmap))
217 mask = EPT_PG_EMUL_RW;
222 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
228 static pt_entry_t pg_g;
230 static __inline pt_entry_t
231 pmap_global_bit(pmap_t pmap)
235 switch (pmap->pm_type) {
244 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
250 static __inline pt_entry_t
251 pmap_accessed_bit(pmap_t pmap)
255 switch (pmap->pm_type) {
261 if (pmap_emulate_ad_bits(pmap))
267 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
273 static __inline pt_entry_t
274 pmap_modified_bit(pmap_t pmap)
278 switch (pmap->pm_type) {
284 if (pmap_emulate_ad_bits(pmap))
290 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
296 static __inline pt_entry_t
297 pmap_pku_mask_bit(pmap_t pmap)
300 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
303 #if !defined(DIAGNOSTIC)
304 #ifdef __GNUC_GNU_INLINE__
305 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
307 #define PMAP_INLINE extern inline
314 #define PV_STAT(x) do { x ; } while (0)
316 #define PV_STAT(x) do { } while (0)
319 #define pa_index(pa) ((pa) >> PDRSHIFT)
320 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
322 #define NPV_LIST_LOCKS MAXCPU
324 #define PHYS_TO_PV_LIST_LOCK(pa) \
325 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
327 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
328 struct rwlock **_lockp = (lockp); \
329 struct rwlock *_new_lock; \
331 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
332 if (_new_lock != *_lockp) { \
333 if (*_lockp != NULL) \
334 rw_wunlock(*_lockp); \
335 *_lockp = _new_lock; \
340 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
341 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
343 #define RELEASE_PV_LIST_LOCK(lockp) do { \
344 struct rwlock **_lockp = (lockp); \
346 if (*_lockp != NULL) { \
347 rw_wunlock(*_lockp); \
352 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
353 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
355 struct pmap kernel_pmap_store;
357 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
358 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
361 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
362 "Number of kernel page table pages allocated on bootup");
365 vm_paddr_t dmaplimit;
366 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
369 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
371 static int pg_ps_enabled = 1;
372 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
373 &pg_ps_enabled, 0, "Are large page mappings enabled?");
375 #define PAT_INDEX_SIZE 8
376 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
378 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
379 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
380 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
381 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
383 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
384 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
385 static int ndmpdpphys; /* number of DMPDPphys pages */
387 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
390 * pmap_mapdev support pre initialization (i.e. console)
392 #define PMAP_PREINIT_MAPPING_COUNT 8
393 static struct pmap_preinit_mapping {
398 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
399 static int pmap_initialized;
402 * Data for the pv entry allocation mechanism.
403 * Updates to pv_invl_gen are protected by the pv_list_locks[]
404 * elements, but reads are not.
406 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
407 static struct mtx __exclusive_cache_line pv_chunks_mutex;
408 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
409 static u_long pv_invl_gen[NPV_LIST_LOCKS];
410 static struct md_page *pv_table;
411 static struct md_page pv_dummy;
414 * All those kernel PT submaps that BSD is so fond of
416 pt_entry_t *CMAP1 = NULL;
418 static vm_offset_t qframe = 0;
419 static struct mtx qframe_mtx;
421 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
423 static vmem_t *large_vmem;
424 static u_int lm_ents;
425 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
426 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
428 int pmap_pcid_enabled = 1;
429 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
430 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
431 int invpcid_works = 0;
432 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
433 "Is the invpcid instruction available ?");
435 int __read_frequently pti = 0;
436 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
438 "Page Table Isolation enabled");
439 static vm_object_t pti_obj;
440 static pml4_entry_t *pti_pml4;
441 static vm_pindex_t pti_pg_idx;
442 static bool pti_finalized;
444 struct pmap_pkru_range {
445 struct rs_el pkru_rs_el;
450 static uma_zone_t pmap_pkru_ranges_zone;
451 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
452 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
453 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
454 static void *pkru_dup_range(void *ctx, void *data);
455 static void pkru_free_range(void *ctx, void *node);
456 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
457 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
458 static void pmap_pkru_deassign_all(pmap_t pmap);
461 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
468 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
470 return (sysctl_handle_64(oidp, &res, 0, req));
472 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
473 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
474 "Count of saved TLB context on switch");
476 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
477 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
478 static struct mtx invl_gen_mtx;
479 /* Fake lock object to satisfy turnstiles interface. */
480 static struct lock_object invl_gen_ts = {
483 static struct pmap_invl_gen pmap_invl_gen_head = {
487 static u_long pmap_invl_gen = 1;
488 static int pmap_invl_waiters;
489 static struct callout pmap_invl_callout;
490 static bool pmap_invl_callout_inited;
492 #define PMAP_ASSERT_NOT_IN_DI() \
493 KASSERT(pmap_not_in_di(), ("DI already started"))
500 if ((cpu_feature2 & CPUID2_CX16) == 0)
503 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
508 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
512 locked = pmap_di_locked();
513 return (sysctl_handle_int(oidp, &locked, 0, req));
515 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
516 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
517 "Locked delayed invalidation");
519 static bool pmap_not_in_di_l(void);
520 static bool pmap_not_in_di_u(void);
521 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
524 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
528 pmap_not_in_di_l(void)
530 struct pmap_invl_gen *invl_gen;
532 invl_gen = &curthread->td_md.md_invl_gen;
533 return (invl_gen->gen == 0);
537 pmap_thread_init_invl_gen_l(struct thread *td)
539 struct pmap_invl_gen *invl_gen;
541 invl_gen = &td->td_md.md_invl_gen;
546 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
548 struct turnstile *ts;
550 ts = turnstile_trywait(&invl_gen_ts);
551 if (*m_gen > atomic_load_long(invl_gen))
552 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
554 turnstile_cancel(ts);
558 pmap_delayed_invl_finish_unblock(u_long new_gen)
560 struct turnstile *ts;
562 turnstile_chain_lock(&invl_gen_ts);
563 ts = turnstile_lookup(&invl_gen_ts);
565 pmap_invl_gen = new_gen;
567 turnstile_broadcast(ts, TS_SHARED_QUEUE);
568 turnstile_unpend(ts);
570 turnstile_chain_unlock(&invl_gen_ts);
574 * Start a new Delayed Invalidation (DI) block of code, executed by
575 * the current thread. Within a DI block, the current thread may
576 * destroy both the page table and PV list entries for a mapping and
577 * then release the corresponding PV list lock before ensuring that
578 * the mapping is flushed from the TLBs of any processors with the
582 pmap_delayed_invl_start_l(void)
584 struct pmap_invl_gen *invl_gen;
587 invl_gen = &curthread->td_md.md_invl_gen;
588 PMAP_ASSERT_NOT_IN_DI();
589 mtx_lock(&invl_gen_mtx);
590 if (LIST_EMPTY(&pmap_invl_gen_tracker))
591 currgen = pmap_invl_gen;
593 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
594 invl_gen->gen = currgen + 1;
595 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
596 mtx_unlock(&invl_gen_mtx);
600 * Finish the DI block, previously started by the current thread. All
601 * required TLB flushes for the pages marked by
602 * pmap_delayed_invl_page() must be finished before this function is
605 * This function works by bumping the global DI generation number to
606 * the generation number of the current thread's DI, unless there is a
607 * pending DI that started earlier. In the latter case, bumping the
608 * global DI generation number would incorrectly signal that the
609 * earlier DI had finished. Instead, this function bumps the earlier
610 * DI's generation number to match the generation number of the
611 * current thread's DI.
614 pmap_delayed_invl_finish_l(void)
616 struct pmap_invl_gen *invl_gen, *next;
618 invl_gen = &curthread->td_md.md_invl_gen;
619 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
620 mtx_lock(&invl_gen_mtx);
621 next = LIST_NEXT(invl_gen, link);
623 pmap_delayed_invl_finish_unblock(invl_gen->gen);
625 next->gen = invl_gen->gen;
626 LIST_REMOVE(invl_gen, link);
627 mtx_unlock(&invl_gen_mtx);
632 pmap_not_in_di_u(void)
634 struct pmap_invl_gen *invl_gen;
636 invl_gen = &curthread->td_md.md_invl_gen;
637 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
641 pmap_thread_init_invl_gen_u(struct thread *td)
643 struct pmap_invl_gen *invl_gen;
645 invl_gen = &td->td_md.md_invl_gen;
647 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
651 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
653 uint64_t new_high, new_low, old_high, old_low;
656 old_low = new_low = 0;
657 old_high = new_high = (uintptr_t)0;
659 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
660 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
661 : "b"(new_low), "c" (new_high)
664 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
667 out->next = (void *)old_high;
670 out->next = (void *)new_high;
676 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
677 struct pmap_invl_gen *new_val)
679 uint64_t new_high, new_low, old_high, old_low;
682 new_low = new_val->gen;
683 new_high = (uintptr_t)new_val->next;
684 old_low = old_val->gen;
685 old_high = (uintptr_t)old_val->next;
687 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
688 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
689 : "b"(new_low), "c" (new_high)
695 static long invl_start_restart;
696 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
697 &invl_start_restart, 0,
699 static long invl_finish_restart;
700 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
701 &invl_finish_restart, 0,
703 static int invl_max_qlen;
704 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
709 static struct lock_delay_config __read_frequently di_delay;
710 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
713 pmap_delayed_invl_start_u(void)
715 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
717 struct lock_delay_arg lda;
725 invl_gen = &td->td_md.md_invl_gen;
726 PMAP_ASSERT_NOT_IN_DI();
727 lock_delay_arg_init(&lda, &di_delay);
728 invl_gen->saved_pri = 0;
729 pri = td->td_base_pri;
732 pri = td->td_base_pri;
734 invl_gen->saved_pri = pri;
741 for (p = &pmap_invl_gen_head;; p = prev.next) {
743 prevl = atomic_load_ptr(&p->next);
744 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
745 PV_STAT(atomic_add_long(&invl_start_restart, 1));
751 prev.next = (void *)prevl;
754 if ((ii = invl_max_qlen) < i)
755 atomic_cmpset_int(&invl_max_qlen, ii, i);
758 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
759 PV_STAT(atomic_add_long(&invl_start_restart, 1));
764 new_prev.gen = prev.gen;
765 new_prev.next = invl_gen;
766 invl_gen->gen = prev.gen + 1;
768 /* Formal fence between store to invl->gen and updating *p. */
769 atomic_thread_fence_rel();
772 * After inserting an invl_gen element with invalid bit set,
773 * this thread blocks any other thread trying to enter the
774 * delayed invalidation block. Do not allow to remove us from
775 * the CPU, because it causes starvation for other threads.
780 * ABA for *p is not possible there, since p->gen can only
781 * increase. So if the *p thread finished its di, then
782 * started a new one and got inserted into the list at the
783 * same place, its gen will appear greater than the previously
786 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
788 PV_STAT(atomic_add_long(&invl_start_restart, 1));
794 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
795 * invl_gen->next, allowing other threads to iterate past us.
796 * pmap_di_store_invl() provides fence between the generation
797 * write and the update of next.
799 invl_gen->next = NULL;
804 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
805 struct pmap_invl_gen *p)
807 struct pmap_invl_gen prev, new_prev;
811 * Load invl_gen->gen after setting invl_gen->next
812 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
813 * generations to propagate to our invl_gen->gen. Lock prefix
814 * in atomic_set_ptr() worked as seq_cst fence.
816 mygen = atomic_load_long(&invl_gen->gen);
818 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
821 KASSERT(prev.gen < mygen,
822 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
823 new_prev.gen = mygen;
824 new_prev.next = (void *)((uintptr_t)invl_gen->next &
825 ~PMAP_INVL_GEN_NEXT_INVALID);
827 /* Formal fence between load of prev and storing update to it. */
828 atomic_thread_fence_rel();
830 return (pmap_di_store_invl(p, &prev, &new_prev));
834 pmap_delayed_invl_finish_u(void)
836 struct pmap_invl_gen *invl_gen, *p;
838 struct lock_delay_arg lda;
842 invl_gen = &td->td_md.md_invl_gen;
843 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
844 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
845 ("missed invl_start: INVALID"));
846 lock_delay_arg_init(&lda, &di_delay);
849 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
850 prevl = atomic_load_ptr(&p->next);
851 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
852 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
856 if ((void *)prevl == invl_gen)
861 * It is legitimate to not find ourself on the list if a
862 * thread before us finished its DI and started it again.
864 if (__predict_false(p == NULL)) {
865 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
871 atomic_set_ptr((uintptr_t *)&invl_gen->next,
872 PMAP_INVL_GEN_NEXT_INVALID);
873 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
874 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
875 PMAP_INVL_GEN_NEXT_INVALID);
877 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
882 if (atomic_load_int(&pmap_invl_waiters) > 0)
883 pmap_delayed_invl_finish_unblock(0);
884 if (invl_gen->saved_pri != 0) {
886 sched_prio(td, invl_gen->saved_pri);
892 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
894 struct pmap_invl_gen *p, *pn;
899 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
901 nextl = atomic_load_ptr(&p->next);
902 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
903 td = first ? NULL : __containerof(p, struct thread,
905 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
906 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
907 td != NULL ? td->td_tid : -1);
913 static long invl_wait;
914 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
915 "Number of times DI invalidation blocked pmap_remove_all/write");
916 static long invl_wait_slow;
917 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
918 "Number of slow invalidation waits for lockless DI");
922 pmap_delayed_invl_genp(vm_page_t m)
925 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
929 pmap_delayed_invl_callout_func(void *arg __unused)
932 if (atomic_load_int(&pmap_invl_waiters) == 0)
934 pmap_delayed_invl_finish_unblock(0);
938 pmap_delayed_invl_callout_init(void *arg __unused)
941 if (pmap_di_locked())
943 callout_init(&pmap_invl_callout, 1);
944 pmap_invl_callout_inited = true;
946 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
947 pmap_delayed_invl_callout_init, NULL);
950 * Ensure that all currently executing DI blocks, that need to flush
951 * TLB for the given page m, actually flushed the TLB at the time the
952 * function returned. If the page m has an empty PV list and we call
953 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
954 * valid mapping for the page m in either its page table or TLB.
956 * This function works by blocking until the global DI generation
957 * number catches up with the generation number associated with the
958 * given page m and its PV list. Since this function's callers
959 * typically own an object lock and sometimes own a page lock, it
960 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
964 pmap_delayed_invl_wait_l(vm_page_t m)
968 bool accounted = false;
971 m_gen = pmap_delayed_invl_genp(m);
972 while (*m_gen > pmap_invl_gen) {
975 atomic_add_long(&invl_wait, 1);
979 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
984 pmap_delayed_invl_wait_u(vm_page_t m)
987 struct lock_delay_arg lda;
991 m_gen = pmap_delayed_invl_genp(m);
992 lock_delay_arg_init(&lda, &di_delay);
993 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
994 if (fast || !pmap_invl_callout_inited) {
995 PV_STAT(atomic_add_long(&invl_wait, 1));
1000 * The page's invalidation generation number
1001 * is still below the current thread's number.
1002 * Prepare to block so that we do not waste
1003 * CPU cycles or worse, suffer livelock.
1005 * Since it is impossible to block without
1006 * racing with pmap_delayed_invl_finish_u(),
1007 * prepare for the race by incrementing
1008 * pmap_invl_waiters and arming a 1-tick
1009 * callout which will unblock us if we lose
1012 atomic_add_int(&pmap_invl_waiters, 1);
1015 * Re-check the current thread's invalidation
1016 * generation after incrementing
1017 * pmap_invl_waiters, so that there is no race
1018 * with pmap_delayed_invl_finish_u() setting
1019 * the page generation and checking
1020 * pmap_invl_waiters. The only race allowed
1021 * is for a missed unblock, which is handled
1025 atomic_load_long(&pmap_invl_gen_head.gen)) {
1026 callout_reset(&pmap_invl_callout, 1,
1027 pmap_delayed_invl_callout_func, NULL);
1028 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1029 pmap_delayed_invl_wait_block(m_gen,
1030 &pmap_invl_gen_head.gen);
1032 atomic_add_int(&pmap_invl_waiters, -1);
1037 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1040 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1041 pmap_thread_init_invl_gen_u);
1044 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1047 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1048 pmap_delayed_invl_start_u);
1051 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1054 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1055 pmap_delayed_invl_finish_u);
1058 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1061 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1062 pmap_delayed_invl_wait_u);
1066 * Mark the page m's PV list as participating in the current thread's
1067 * DI block. Any threads concurrently using m's PV list to remove or
1068 * restrict all mappings to m will wait for the current thread's DI
1069 * block to complete before proceeding.
1071 * The function works by setting the DI generation number for m's PV
1072 * list to at least the DI generation number of the current thread.
1073 * This forces a caller of pmap_delayed_invl_wait() to block until
1074 * current thread calls pmap_delayed_invl_finish().
1077 pmap_delayed_invl_page(vm_page_t m)
1081 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1082 gen = curthread->td_md.md_invl_gen.gen;
1085 m_gen = pmap_delayed_invl_genp(m);
1093 static caddr_t crashdumpmap;
1096 * Internal flags for pmap_enter()'s helper functions.
1098 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1099 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1102 * Internal flags for pmap_mapdev_internal() and
1103 * pmap_change_attr_locked().
1105 #define MAPDEV_FLUSHCACHE 0x0000001 /* Flush cache after mapping. */
1106 #define MAPDEV_SETATTR 0x0000002 /* Modify existing attrs. */
1108 static void free_pv_chunk(struct pv_chunk *pc);
1109 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1110 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1111 static int popcnt_pc_map_pq(uint64_t *map);
1112 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1113 static void reserve_pv_entries(pmap_t pmap, int needed,
1114 struct rwlock **lockp);
1115 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1116 struct rwlock **lockp);
1117 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1118 u_int flags, struct rwlock **lockp);
1119 #if VM_NRESERVLEVEL > 0
1120 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1121 struct rwlock **lockp);
1123 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1124 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1127 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
1129 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1130 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1131 vm_offset_t va, struct rwlock **lockp);
1132 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1134 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1135 vm_prot_t prot, struct rwlock **lockp);
1136 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1137 u_int flags, vm_page_t m, struct rwlock **lockp);
1138 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1139 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1140 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1141 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1142 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1144 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1146 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1148 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1149 static vm_page_t pmap_large_map_getptp_unlocked(void);
1150 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1151 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
1152 #if VM_NRESERVLEVEL > 0
1153 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1154 struct rwlock **lockp);
1156 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1158 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
1159 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1161 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1162 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1163 static void pmap_pti_wire_pte(void *pte);
1164 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1165 struct spglist *free, struct rwlock **lockp);
1166 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1167 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1168 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1169 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1170 struct spglist *free);
1171 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1172 pd_entry_t *pde, struct spglist *free,
1173 struct rwlock **lockp);
1174 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1175 vm_page_t m, struct rwlock **lockp);
1176 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1178 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1180 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1181 struct rwlock **lockp);
1182 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1183 struct rwlock **lockp);
1184 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1185 struct rwlock **lockp);
1187 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1188 struct spglist *free);
1189 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1191 /********************/
1192 /* Inline functions */
1193 /********************/
1195 /* Return a non-clipped PD index for a given VA */
1196 static __inline vm_pindex_t
1197 pmap_pde_pindex(vm_offset_t va)
1199 return (va >> PDRSHIFT);
1203 /* Return a pointer to the PML4 slot that corresponds to a VA */
1204 static __inline pml4_entry_t *
1205 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1208 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1211 /* Return a pointer to the PDP slot that corresponds to a VA */
1212 static __inline pdp_entry_t *
1213 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1217 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1218 return (&pdpe[pmap_pdpe_index(va)]);
1221 /* Return a pointer to the PDP slot that corresponds to a VA */
1222 static __inline pdp_entry_t *
1223 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1225 pml4_entry_t *pml4e;
1228 PG_V = pmap_valid_bit(pmap);
1229 pml4e = pmap_pml4e(pmap, va);
1230 if ((*pml4e & PG_V) == 0)
1232 return (pmap_pml4e_to_pdpe(pml4e, va));
1235 /* Return a pointer to the PD slot that corresponds to a VA */
1236 static __inline pd_entry_t *
1237 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1241 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1242 return (&pde[pmap_pde_index(va)]);
1245 /* Return a pointer to the PD slot that corresponds to a VA */
1246 static __inline pd_entry_t *
1247 pmap_pde(pmap_t pmap, vm_offset_t va)
1252 PG_V = pmap_valid_bit(pmap);
1253 pdpe = pmap_pdpe(pmap, va);
1254 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1256 return (pmap_pdpe_to_pde(pdpe, va));
1259 /* Return a pointer to the PT slot that corresponds to a VA */
1260 static __inline pt_entry_t *
1261 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1265 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1266 return (&pte[pmap_pte_index(va)]);
1269 /* Return a pointer to the PT slot that corresponds to a VA */
1270 static __inline pt_entry_t *
1271 pmap_pte(pmap_t pmap, vm_offset_t va)
1276 PG_V = pmap_valid_bit(pmap);
1277 pde = pmap_pde(pmap, va);
1278 if (pde == NULL || (*pde & PG_V) == 0)
1280 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1281 return ((pt_entry_t *)pde);
1282 return (pmap_pde_to_pte(pde, va));
1285 static __inline void
1286 pmap_resident_count_inc(pmap_t pmap, int count)
1289 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1290 pmap->pm_stats.resident_count += count;
1293 static __inline void
1294 pmap_resident_count_dec(pmap_t pmap, int count)
1297 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1298 KASSERT(pmap->pm_stats.resident_count >= count,
1299 ("pmap %p resident count underflow %ld %d", pmap,
1300 pmap->pm_stats.resident_count, count));
1301 pmap->pm_stats.resident_count -= count;
1304 PMAP_INLINE pt_entry_t *
1305 vtopte(vm_offset_t va)
1307 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1309 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1311 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1314 static __inline pd_entry_t *
1315 vtopde(vm_offset_t va)
1317 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1319 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1321 return (PDmap + ((va >> PDRSHIFT) & mask));
1325 allocpages(vm_paddr_t *firstaddr, int n)
1330 bzero((void *)ret, n * PAGE_SIZE);
1331 *firstaddr += n * PAGE_SIZE;
1335 CTASSERT(powerof2(NDMPML4E));
1337 /* number of kernel PDP slots */
1338 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1341 nkpt_init(vm_paddr_t addr)
1348 pt_pages = howmany(addr, 1 << PDRSHIFT);
1349 pt_pages += NKPDPE(pt_pages);
1352 * Add some slop beyond the bare minimum required for bootstrapping
1355 * This is quite important when allocating KVA for kernel modules.
1356 * The modules are required to be linked in the negative 2GB of
1357 * the address space. If we run out of KVA in this region then
1358 * pmap_growkernel() will need to allocate page table pages to map
1359 * the entire 512GB of KVA space which is an unnecessary tax on
1362 * Secondly, device memory mapped as part of setting up the low-
1363 * level console(s) is taken from KVA, starting at virtual_avail.
1364 * This is because cninit() is called after pmap_bootstrap() but
1365 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1368 pt_pages += 32; /* 64MB additional slop. */
1374 * Returns the proper write/execute permission for a physical page that is
1375 * part of the initial boot allocations.
1377 * If the page has kernel text, it is marked as read-only. If the page has
1378 * kernel read-only data, it is marked as read-only/not-executable. If the
1379 * page has only read-write data, it is marked as read-write/not-executable.
1380 * If the page is below/above the kernel range, it is marked as read-write.
1382 * This function operates on 2M pages, since we map the kernel space that
1385 * Note that this doesn't currently provide any protection for modules.
1387 static inline pt_entry_t
1388 bootaddr_rwx(vm_paddr_t pa)
1392 * Everything in the same 2M page as the start of the kernel
1393 * should be static. On the other hand, things in the same 2M
1394 * page as the end of the kernel could be read-write/executable,
1395 * as the kernel image is not guaranteed to end on a 2M boundary.
1397 if (pa < trunc_2mpage(btext - KERNBASE) ||
1398 pa >= trunc_2mpage(_end - KERNBASE))
1401 * The linker should ensure that the read-only and read-write
1402 * portions don't share the same 2M page, so this shouldn't
1403 * impact read-only data. However, in any case, any page with
1404 * read-write data needs to be read-write.
1406 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1407 return (X86_PG_RW | pg_nx);
1409 * Mark any 2M page containing kernel text as read-only. Mark
1410 * other pages with read-only data as read-only and not executable.
1411 * (It is likely a small portion of the read-only data section will
1412 * be marked as read-only, but executable. This should be acceptable
1413 * since the read-only protection will keep the data from changing.)
1414 * Note that fixups to the .text section will still work until we
1417 if (pa < round_2mpage(etext - KERNBASE))
1423 create_pagetables(vm_paddr_t *firstaddr)
1425 int i, j, ndm1g, nkpdpe, nkdmpde;
1429 uint64_t DMPDkernphys;
1431 /* Allocate page table pages for the direct map */
1432 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1433 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1435 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1436 if (ndmpdpphys > NDMPML4E) {
1438 * Each NDMPML4E allows 512 GB, so limit to that,
1439 * and then readjust ndmpdp and ndmpdpphys.
1441 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1442 Maxmem = atop(NDMPML4E * NBPML4);
1443 ndmpdpphys = NDMPML4E;
1444 ndmpdp = NDMPML4E * NPDEPG;
1446 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1448 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1450 * Calculate the number of 1G pages that will fully fit in
1453 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1456 * Allocate 2M pages for the kernel. These will be used in
1457 * place of the first one or more 1G pages from ndm1g.
1459 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1460 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1463 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1464 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1466 /* Allocate pages */
1467 KPML4phys = allocpages(firstaddr, 1);
1468 KPDPphys = allocpages(firstaddr, NKPML4E);
1471 * Allocate the initial number of kernel page table pages required to
1472 * bootstrap. We defer this until after all memory-size dependent
1473 * allocations are done (e.g. direct map), so that we don't have to
1474 * build in too much slop in our estimate.
1476 * Note that when NKPML4E > 1, we have an empty page underneath
1477 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1478 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1480 nkpt_init(*firstaddr);
1481 nkpdpe = NKPDPE(nkpt);
1483 KPTphys = allocpages(firstaddr, nkpt);
1484 KPDphys = allocpages(firstaddr, nkpdpe);
1487 * Connect the zero-filled PT pages to their PD entries. This
1488 * implicitly maps the PT pages at their correct locations within
1491 pd_p = (pd_entry_t *)KPDphys;
1492 for (i = 0; i < nkpt; i++)
1493 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1496 * Map from physical address zero to the end of loader preallocated
1497 * memory using 2MB pages. This replaces some of the PD entries
1500 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1501 /* Preset PG_M and PG_A because demotion expects it. */
1502 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1503 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1506 * Because we map the physical blocks in 2M pages, adjust firstaddr
1507 * to record the physical blocks we've actually mapped into kernel
1508 * virtual address space.
1510 if (*firstaddr < round_2mpage(KERNend))
1511 *firstaddr = round_2mpage(KERNend);
1513 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1514 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1515 for (i = 0; i < nkpdpe; i++)
1516 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1519 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1520 * the end of physical memory is not aligned to a 1GB page boundary,
1521 * then the residual physical memory is mapped with 2MB pages. Later,
1522 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1523 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1524 * that are partially used.
1526 pd_p = (pd_entry_t *)DMPDphys;
1527 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1528 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1529 /* Preset PG_M and PG_A because demotion expects it. */
1530 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1531 X86_PG_M | X86_PG_A | pg_nx;
1533 pdp_p = (pdp_entry_t *)DMPDPphys;
1534 for (i = 0; i < ndm1g; i++) {
1535 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1536 /* Preset PG_M and PG_A because demotion expects it. */
1537 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1538 X86_PG_M | X86_PG_A | pg_nx;
1540 for (j = 0; i < ndmpdp; i++, j++) {
1541 pdp_p[i] = DMPDphys + ptoa(j);
1542 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1546 * Instead of using a 1G page for the memory containing the kernel,
1547 * use 2M pages with read-only and no-execute permissions. (If using 1G
1548 * pages, this will partially overwrite the PDPEs above.)
1551 pd_p = (pd_entry_t *)DMPDkernphys;
1552 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1553 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1554 X86_PG_M | X86_PG_A | pg_nx |
1555 bootaddr_rwx(i << PDRSHIFT);
1556 for (i = 0; i < nkdmpde; i++)
1557 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1561 /* And recursively map PML4 to itself in order to get PTmap */
1562 p4_p = (pml4_entry_t *)KPML4phys;
1563 p4_p[PML4PML4I] = KPML4phys;
1564 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1566 /* Connect the Direct Map slot(s) up to the PML4. */
1567 for (i = 0; i < ndmpdpphys; i++) {
1568 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1569 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1572 /* Connect the KVA slots up to the PML4 */
1573 for (i = 0; i < NKPML4E; i++) {
1574 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1575 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1580 * Bootstrap the system enough to run with virtual memory.
1582 * On amd64 this is called after mapping has already been enabled
1583 * and just syncs the pmap module with what has already been done.
1584 * [We can't call it easily with mapping off since the kernel is not
1585 * mapped with PA == VA, hence we would have to relocate every address
1586 * from the linked base (virtual) address "KERNBASE" to the actual
1587 * (physical) address starting relative to 0]
1590 pmap_bootstrap(vm_paddr_t *firstaddr)
1593 pt_entry_t *pte, *pcpu_pte;
1594 uint64_t cr4, pcpu_phys;
1598 KERNend = *firstaddr;
1599 res = atop(KERNend - (vm_paddr_t)kernphys);
1605 * Create an initial set of page tables to run the kernel in.
1607 create_pagetables(firstaddr);
1609 pcpu_phys = allocpages(firstaddr, MAXCPU);
1612 * Add a physical memory segment (vm_phys_seg) corresponding to the
1613 * preallocated kernel page table pages so that vm_page structures
1614 * representing these pages will be created. The vm_page structures
1615 * are required for promotion of the corresponding kernel virtual
1616 * addresses to superpage mappings.
1618 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1621 * Account for the virtual addresses mapped by create_pagetables().
1623 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1624 virtual_end = VM_MAX_KERNEL_ADDRESS;
1627 * Enable PG_G global pages, then switch to the kernel page
1628 * table from the bootstrap page table. After the switch, it
1629 * is possible to enable SMEP and SMAP since PG_U bits are
1635 load_cr3(KPML4phys);
1636 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1638 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1643 * Initialize the kernel pmap (which is statically allocated).
1644 * Count bootstrap data as being resident in case any of this data is
1645 * later unmapped (using pmap_remove()) and freed.
1647 PMAP_LOCK_INIT(kernel_pmap);
1648 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1649 kernel_pmap->pm_cr3 = KPML4phys;
1650 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1651 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1652 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1653 kernel_pmap->pm_stats.resident_count = res;
1654 kernel_pmap->pm_flags = pmap_flags;
1657 * Initialize the TLB invalidations generation number lock.
1659 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1662 * Reserve some special page table entries/VA space for temporary
1665 #define SYSMAP(c, p, v, n) \
1666 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1672 * Crashdump maps. The first page is reused as CMAP1 for the
1675 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1676 CADDR1 = crashdumpmap;
1678 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1681 for (i = 0; i < MAXCPU; i++) {
1682 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1683 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1685 STAILQ_INIT(&cpuhead);
1686 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1687 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1688 amd64_bsp_pcpu_init1(&__pcpu[0]);
1689 amd64_bsp_ist_init(&__pcpu[0]);
1690 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1691 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1694 * Initialize the PAT MSR.
1695 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1696 * side-effect, invalidates stale PG_G TLB entries that might
1697 * have been created in our pre-boot environment.
1701 /* Initialize TLB Context Id. */
1702 if (pmap_pcid_enabled) {
1703 for (i = 0; i < MAXCPU; i++) {
1704 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1705 kernel_pmap->pm_pcids[i].pm_gen = 1;
1709 * PMAP_PCID_KERN + 1 is used for initialization of
1710 * proc0 pmap. The pmap' pcid state might be used by
1711 * EFIRT entry before first context switch, so it
1712 * needs to be valid.
1714 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1715 PCPU_SET(pcid_gen, 1);
1718 * pcpu area for APs is zeroed during AP startup.
1719 * pc_pcid_next and pc_pcid_gen are initialized by AP
1720 * during pcpu setup.
1722 load_cr4(rcr4() | CR4_PCIDE);
1727 * Setup the PAT MSR.
1736 /* Bail if this CPU doesn't implement PAT. */
1737 if ((cpu_feature & CPUID_PAT) == 0)
1740 /* Set default PAT index table. */
1741 for (i = 0; i < PAT_INDEX_SIZE; i++)
1743 pat_index[PAT_WRITE_BACK] = 0;
1744 pat_index[PAT_WRITE_THROUGH] = 1;
1745 pat_index[PAT_UNCACHEABLE] = 3;
1746 pat_index[PAT_WRITE_COMBINING] = 6;
1747 pat_index[PAT_WRITE_PROTECTED] = 5;
1748 pat_index[PAT_UNCACHED] = 2;
1751 * Initialize default PAT entries.
1752 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1753 * Program 5 and 6 as WP and WC.
1755 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1756 * mapping for a 2M page uses a PAT value with the bit 3 set due
1757 * to its overload with PG_PS.
1759 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1760 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1761 PAT_VALUE(2, PAT_UNCACHED) |
1762 PAT_VALUE(3, PAT_UNCACHEABLE) |
1763 PAT_VALUE(4, PAT_WRITE_BACK) |
1764 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1765 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1766 PAT_VALUE(7, PAT_UNCACHEABLE);
1770 load_cr4(cr4 & ~CR4_PGE);
1772 /* Disable caches (CD = 1, NW = 0). */
1774 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1776 /* Flushes caches and TLBs. */
1780 /* Update PAT and index table. */
1781 wrmsr(MSR_PAT, pat_msr);
1783 /* Flush caches and TLBs again. */
1787 /* Restore caches and PGE. */
1793 * Initialize a vm_page's machine-dependent fields.
1796 pmap_page_init(vm_page_t m)
1799 TAILQ_INIT(&m->md.pv_list);
1800 m->md.pat_mode = PAT_WRITE_BACK;
1804 * Initialize the pmap module.
1805 * Called by vm_init, to initialize any structures that the pmap
1806 * system needs to map virtual memory.
1811 struct pmap_preinit_mapping *ppim;
1814 int error, i, pv_npg, ret, skz63;
1816 /* L1TF, reserve page @0 unconditionally */
1817 vm_page_blacklist_add(0, bootverbose);
1819 /* Detect bare-metal Skylake Server and Skylake-X. */
1820 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1821 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1823 * Skylake-X errata SKZ63. Processor May Hang When
1824 * Executing Code In an HLE Transaction Region between
1825 * 40000000H and 403FFFFFH.
1827 * Mark the pages in the range as preallocated. It
1828 * seems to be impossible to distinguish between
1829 * Skylake Server and Skylake X.
1832 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1835 printf("SKZ63: skipping 4M RAM starting "
1836 "at physical 1G\n");
1837 for (i = 0; i < atop(0x400000); i++) {
1838 ret = vm_page_blacklist_add(0x40000000 +
1840 if (!ret && bootverbose)
1841 printf("page at %#lx already used\n",
1842 0x40000000 + ptoa(i));
1848 * Initialize the vm page array entries for the kernel pmap's
1851 PMAP_LOCK(kernel_pmap);
1852 for (i = 0; i < nkpt; i++) {
1853 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1854 KASSERT(mpte >= vm_page_array &&
1855 mpte < &vm_page_array[vm_page_array_size],
1856 ("pmap_init: page table page is out of range"));
1857 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1858 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1859 mpte->ref_count = 1;
1862 * Collect the page table pages that were replaced by a 2MB
1863 * page in create_pagetables(). They are zero filled.
1865 if (i << PDRSHIFT < KERNend &&
1866 pmap_insert_pt_page(kernel_pmap, mpte, false))
1867 panic("pmap_init: pmap_insert_pt_page failed");
1869 PMAP_UNLOCK(kernel_pmap);
1873 * If the kernel is running on a virtual machine, then it must assume
1874 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1875 * be prepared for the hypervisor changing the vendor and family that
1876 * are reported by CPUID. Consequently, the workaround for AMD Family
1877 * 10h Erratum 383 is enabled if the processor's feature set does not
1878 * include at least one feature that is only supported by older Intel
1879 * or newer AMD processors.
1881 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1882 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1883 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1885 workaround_erratum383 = 1;
1888 * Are large page mappings enabled?
1890 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1891 if (pg_ps_enabled) {
1892 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1893 ("pmap_init: can't assign to pagesizes[1]"));
1894 pagesizes[1] = NBPDR;
1898 * Initialize the pv chunk list mutex.
1900 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1903 * Initialize the pool of pv list locks.
1905 for (i = 0; i < NPV_LIST_LOCKS; i++)
1906 rw_init(&pv_list_locks[i], "pmap pv list");
1909 * Calculate the size of the pv head table for superpages.
1911 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1914 * Allocate memory for the pv head table for superpages.
1916 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1918 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1919 for (i = 0; i < pv_npg; i++)
1920 TAILQ_INIT(&pv_table[i].pv_list);
1921 TAILQ_INIT(&pv_dummy.pv_list);
1923 pmap_initialized = 1;
1924 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1925 ppim = pmap_preinit_mapping + i;
1928 /* Make the direct map consistent */
1929 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1930 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1931 ppim->sz, ppim->mode);
1935 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1936 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1939 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1940 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1941 (vmem_addr_t *)&qframe);
1943 panic("qframe allocation failed");
1946 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1947 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1948 lm_ents = LMEPML4I - LMSPML4I + 1;
1950 printf("pmap: large map %u PML4 slots (%lu GB)\n",
1951 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1953 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1954 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1955 if (large_vmem == NULL) {
1956 printf("pmap: cannot create large map\n");
1959 for (i = 0; i < lm_ents; i++) {
1960 m = pmap_large_map_getptp_unlocked();
1961 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1962 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1968 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
1969 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
1970 "Maximum number of PML4 entries for use by large map (tunable). "
1971 "Each entry corresponds to 512GB of address space.");
1973 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1974 "2MB page mapping counters");
1976 static u_long pmap_pde_demotions;
1977 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1978 &pmap_pde_demotions, 0, "2MB page demotions");
1980 static u_long pmap_pde_mappings;
1981 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1982 &pmap_pde_mappings, 0, "2MB page mappings");
1984 static u_long pmap_pde_p_failures;
1985 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1986 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1988 static u_long pmap_pde_promotions;
1989 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1990 &pmap_pde_promotions, 0, "2MB page promotions");
1992 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1993 "1GB page mapping counters");
1995 static u_long pmap_pdpe_demotions;
1996 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1997 &pmap_pdpe_demotions, 0, "1GB page demotions");
1999 /***************************************************
2000 * Low level helper routines.....
2001 ***************************************************/
2004 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2006 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2008 switch (pmap->pm_type) {
2011 /* Verify that both PAT bits are not set at the same time */
2012 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2013 ("Invalid PAT bits in entry %#lx", entry));
2015 /* Swap the PAT bits if one of them is set */
2016 if ((entry & x86_pat_bits) != 0)
2017 entry ^= x86_pat_bits;
2021 * Nothing to do - the memory attributes are represented
2022 * the same way for regular pages and superpages.
2026 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2033 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2036 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2037 pat_index[(int)mode] >= 0);
2041 * Determine the appropriate bits to set in a PTE or PDE for a specified
2045 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2047 int cache_bits, pat_flag, pat_idx;
2049 if (!pmap_is_valid_memattr(pmap, mode))
2050 panic("Unknown caching mode %d\n", mode);
2052 switch (pmap->pm_type) {
2055 /* The PAT bit is different for PTE's and PDE's. */
2056 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2058 /* Map the caching mode to a PAT index. */
2059 pat_idx = pat_index[mode];
2061 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2064 cache_bits |= pat_flag;
2066 cache_bits |= PG_NC_PCD;
2068 cache_bits |= PG_NC_PWT;
2072 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2076 panic("unsupported pmap type %d", pmap->pm_type);
2079 return (cache_bits);
2083 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2087 switch (pmap->pm_type) {
2090 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2093 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2096 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2103 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2105 int pat_flag, pat_idx;
2108 switch (pmap->pm_type) {
2111 /* The PAT bit is different for PTE's and PDE's. */
2112 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2114 if ((pte & pat_flag) != 0)
2116 if ((pte & PG_NC_PCD) != 0)
2118 if ((pte & PG_NC_PWT) != 0)
2122 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2123 panic("EPT PTE %#lx has no PAT memory type", pte);
2124 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2128 /* See pmap_init_pat(). */
2138 pmap_ps_enabled(pmap_t pmap)
2141 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2145 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2148 switch (pmap->pm_type) {
2155 * This is a little bogus since the generation number is
2156 * supposed to be bumped up when a region of the address
2157 * space is invalidated in the page tables.
2159 * In this case the old PDE entry is valid but yet we want
2160 * to make sure that any mappings using the old entry are
2161 * invalidated in the TLB.
2163 * The reason this works as expected is because we rendezvous
2164 * "all" host cpus and force any vcpu context to exit as a
2167 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2170 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2172 pde_store(pde, newpde);
2176 * After changing the page size for the specified virtual address in the page
2177 * table, flush the corresponding entries from the processor's TLB. Only the
2178 * calling processor's TLB is affected.
2180 * The calling thread must be pinned to a processor.
2183 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2187 if (pmap_type_guest(pmap))
2190 KASSERT(pmap->pm_type == PT_X86,
2191 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2193 PG_G = pmap_global_bit(pmap);
2195 if ((newpde & PG_PS) == 0)
2196 /* Demotion: flush a specific 2MB page mapping. */
2198 else if ((newpde & PG_G) == 0)
2200 * Promotion: flush every 4KB page mapping from the TLB
2201 * because there are too many to flush individually.
2206 * Promotion: flush every 4KB page mapping from the TLB,
2207 * including any global (PG_G) mappings.
2215 * For SMP, these functions have to use the IPI mechanism for coherence.
2217 * N.B.: Before calling any of the following TLB invalidation functions,
2218 * the calling processor must ensure that all stores updating a non-
2219 * kernel page table are globally performed. Otherwise, another
2220 * processor could cache an old, pre-update entry without being
2221 * invalidated. This can happen one of two ways: (1) The pmap becomes
2222 * active on another processor after its pm_active field is checked by
2223 * one of the following functions but before a store updating the page
2224 * table is globally performed. (2) The pmap becomes active on another
2225 * processor before its pm_active field is checked but due to
2226 * speculative loads one of the following functions stills reads the
2227 * pmap as inactive on the other processor.
2229 * The kernel page table is exempt because its pm_active field is
2230 * immutable. The kernel page table is always active on every
2235 * Interrupt the cpus that are executing in the guest context.
2236 * This will force the vcpu to exit and the cached EPT mappings
2237 * will be invalidated by the host before the next vmresume.
2239 static __inline void
2240 pmap_invalidate_ept(pmap_t pmap)
2245 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2246 ("pmap_invalidate_ept: absurd pm_active"));
2249 * The TLB mappings associated with a vcpu context are not
2250 * flushed each time a different vcpu is chosen to execute.
2252 * This is in contrast with a process's vtop mappings that
2253 * are flushed from the TLB on each context switch.
2255 * Therefore we need to do more than just a TLB shootdown on
2256 * the active cpus in 'pmap->pm_active'. To do this we keep
2257 * track of the number of invalidations performed on this pmap.
2259 * Each vcpu keeps a cache of this counter and compares it
2260 * just before a vmresume. If the counter is out-of-date an
2261 * invept will be done to flush stale mappings from the TLB.
2263 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2266 * Force the vcpu to exit and trap back into the hypervisor.
2268 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2269 ipi_selected(pmap->pm_active, ipinum);
2274 pmap_invalidate_cpu_mask(pmap_t pmap)
2277 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2281 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2282 const bool invpcid_works1)
2284 struct invpcid_descr d;
2285 uint64_t kcr3, ucr3;
2289 cpuid = PCPU_GET(cpuid);
2290 if (pmap == PCPU_GET(curpmap)) {
2291 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2293 * Because pm_pcid is recalculated on a
2294 * context switch, we must disable switching.
2295 * Otherwise, we might use a stale value
2299 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2300 if (invpcid_works1) {
2301 d.pcid = pcid | PMAP_PCID_USER_PT;
2304 invpcid(&d, INVPCID_ADDR);
2306 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2307 ucr3 = pmap->pm_ucr3 | pcid |
2308 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2309 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2314 pmap->pm_pcids[cpuid].pm_gen = 0;
2318 pmap->pm_pcids[i].pm_gen = 0;
2322 * The fence is between stores to pm_gen and the read of the
2323 * pm_active mask. We need to ensure that it is impossible
2324 * for us to miss the bit update in pm_active and
2325 * simultaneously observe a non-zero pm_gen in
2326 * pmap_activate_sw(), otherwise TLB update is missed.
2327 * Without the fence, IA32 allows such an outcome. Note that
2328 * pm_active is updated by a locked operation, which provides
2329 * the reciprocal fence.
2331 atomic_thread_fence_seq_cst();
2335 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2338 pmap_invalidate_page_pcid(pmap, va, true);
2342 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2345 pmap_invalidate_page_pcid(pmap, va, false);
2349 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2353 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2356 if (pmap_pcid_enabled)
2357 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2358 pmap_invalidate_page_pcid_noinvpcid);
2359 return (pmap_invalidate_page_nopcid);
2363 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2366 if (pmap_type_guest(pmap)) {
2367 pmap_invalidate_ept(pmap);
2371 KASSERT(pmap->pm_type == PT_X86,
2372 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2375 if (pmap == kernel_pmap) {
2378 if (pmap == PCPU_GET(curpmap))
2380 pmap_invalidate_page_mode(pmap, va);
2382 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2386 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2387 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2390 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2391 const bool invpcid_works1)
2393 struct invpcid_descr d;
2394 uint64_t kcr3, ucr3;
2398 cpuid = PCPU_GET(cpuid);
2399 if (pmap == PCPU_GET(curpmap)) {
2400 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2402 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2403 if (invpcid_works1) {
2404 d.pcid = pcid | PMAP_PCID_USER_PT;
2407 for (; d.addr < eva; d.addr += PAGE_SIZE)
2408 invpcid(&d, INVPCID_ADDR);
2410 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2411 ucr3 = pmap->pm_ucr3 | pcid |
2412 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2413 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2418 pmap->pm_pcids[cpuid].pm_gen = 0;
2422 pmap->pm_pcids[i].pm_gen = 0;
2424 /* See the comment in pmap_invalidate_page_pcid(). */
2425 atomic_thread_fence_seq_cst();
2429 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2433 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2437 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2441 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2445 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2449 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2453 if (pmap_pcid_enabled)
2454 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2455 pmap_invalidate_range_pcid_noinvpcid);
2456 return (pmap_invalidate_range_nopcid);
2460 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2464 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2465 pmap_invalidate_all(pmap);
2469 if (pmap_type_guest(pmap)) {
2470 pmap_invalidate_ept(pmap);
2474 KASSERT(pmap->pm_type == PT_X86,
2475 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2478 if (pmap == kernel_pmap) {
2479 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2482 if (pmap == PCPU_GET(curpmap)) {
2483 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2486 pmap_invalidate_range_mode(pmap, sva, eva);
2488 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2493 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2495 struct invpcid_descr d;
2496 uint64_t kcr3, ucr3;
2500 if (pmap == kernel_pmap) {
2501 if (invpcid_works1) {
2502 bzero(&d, sizeof(d));
2503 invpcid(&d, INVPCID_CTXGLOB);
2508 cpuid = PCPU_GET(cpuid);
2509 if (pmap == PCPU_GET(curpmap)) {
2511 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2512 if (invpcid_works1) {
2516 invpcid(&d, INVPCID_CTX);
2517 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2518 d.pcid |= PMAP_PCID_USER_PT;
2519 invpcid(&d, INVPCID_CTX);
2522 kcr3 = pmap->pm_cr3 | pcid;
2523 ucr3 = pmap->pm_ucr3;
2524 if (ucr3 != PMAP_NO_CR3) {
2525 ucr3 |= pcid | PMAP_PCID_USER_PT;
2526 pmap_pti_pcid_invalidate(ucr3, kcr3);
2533 pmap->pm_pcids[cpuid].pm_gen = 0;
2536 pmap->pm_pcids[i].pm_gen = 0;
2539 /* See the comment in pmap_invalidate_page_pcid(). */
2540 atomic_thread_fence_seq_cst();
2544 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2547 pmap_invalidate_all_pcid(pmap, true);
2551 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2554 pmap_invalidate_all_pcid(pmap, false);
2558 pmap_invalidate_all_nopcid(pmap_t pmap)
2561 if (pmap == kernel_pmap)
2563 else if (pmap == PCPU_GET(curpmap))
2567 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2570 if (pmap_pcid_enabled)
2571 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2572 pmap_invalidate_all_pcid_noinvpcid);
2573 return (pmap_invalidate_all_nopcid);
2577 pmap_invalidate_all(pmap_t pmap)
2580 if (pmap_type_guest(pmap)) {
2581 pmap_invalidate_ept(pmap);
2585 KASSERT(pmap->pm_type == PT_X86,
2586 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2589 pmap_invalidate_all_mode(pmap);
2590 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2595 pmap_invalidate_cache(void)
2605 cpuset_t invalidate; /* processors that invalidate their TLB */
2610 u_int store; /* processor that updates the PDE */
2614 pmap_update_pde_action(void *arg)
2616 struct pde_action *act = arg;
2618 if (act->store == PCPU_GET(cpuid))
2619 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2623 pmap_update_pde_teardown(void *arg)
2625 struct pde_action *act = arg;
2627 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2628 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2632 * Change the page size for the specified virtual address in a way that
2633 * prevents any possibility of the TLB ever having two entries that map the
2634 * same virtual address using different page sizes. This is the recommended
2635 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2636 * machine check exception for a TLB state that is improperly diagnosed as a
2640 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2642 struct pde_action act;
2643 cpuset_t active, other_cpus;
2647 cpuid = PCPU_GET(cpuid);
2648 other_cpus = all_cpus;
2649 CPU_CLR(cpuid, &other_cpus);
2650 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2653 active = pmap->pm_active;
2655 if (CPU_OVERLAP(&active, &other_cpus)) {
2657 act.invalidate = active;
2661 act.newpde = newpde;
2662 CPU_SET(cpuid, &active);
2663 smp_rendezvous_cpus(active,
2664 smp_no_rendezvous_barrier, pmap_update_pde_action,
2665 pmap_update_pde_teardown, &act);
2667 pmap_update_pde_store(pmap, pde, newpde);
2668 if (CPU_ISSET(cpuid, &active))
2669 pmap_update_pde_invalidate(pmap, va, newpde);
2675 * Normal, non-SMP, invalidation functions.
2678 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2680 struct invpcid_descr d;
2681 uint64_t kcr3, ucr3;
2684 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2688 KASSERT(pmap->pm_type == PT_X86,
2689 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2691 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2693 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2694 pmap->pm_ucr3 != PMAP_NO_CR3) {
2696 pcid = pmap->pm_pcids[0].pm_pcid;
2697 if (invpcid_works) {
2698 d.pcid = pcid | PMAP_PCID_USER_PT;
2701 invpcid(&d, INVPCID_ADDR);
2703 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2704 ucr3 = pmap->pm_ucr3 | pcid |
2705 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2706 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2710 } else if (pmap_pcid_enabled)
2711 pmap->pm_pcids[0].pm_gen = 0;
2715 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2717 struct invpcid_descr d;
2719 uint64_t kcr3, ucr3;
2721 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2725 KASSERT(pmap->pm_type == PT_X86,
2726 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2728 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2729 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2731 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2732 pmap->pm_ucr3 != PMAP_NO_CR3) {
2734 if (invpcid_works) {
2735 d.pcid = pmap->pm_pcids[0].pm_pcid |
2739 for (; d.addr < eva; d.addr += PAGE_SIZE)
2740 invpcid(&d, INVPCID_ADDR);
2742 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2743 pm_pcid | CR3_PCID_SAVE;
2744 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2745 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2746 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2750 } else if (pmap_pcid_enabled) {
2751 pmap->pm_pcids[0].pm_gen = 0;
2756 pmap_invalidate_all(pmap_t pmap)
2758 struct invpcid_descr d;
2759 uint64_t kcr3, ucr3;
2761 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2765 KASSERT(pmap->pm_type == PT_X86,
2766 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2768 if (pmap == kernel_pmap) {
2769 if (pmap_pcid_enabled && invpcid_works) {
2770 bzero(&d, sizeof(d));
2771 invpcid(&d, INVPCID_CTXGLOB);
2775 } else if (pmap == PCPU_GET(curpmap)) {
2776 if (pmap_pcid_enabled) {
2778 if (invpcid_works) {
2779 d.pcid = pmap->pm_pcids[0].pm_pcid;
2782 invpcid(&d, INVPCID_CTX);
2783 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2784 d.pcid |= PMAP_PCID_USER_PT;
2785 invpcid(&d, INVPCID_CTX);
2788 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2789 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2790 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2791 0].pm_pcid | PMAP_PCID_USER_PT;
2792 pmap_pti_pcid_invalidate(ucr3, kcr3);
2800 } else if (pmap_pcid_enabled) {
2801 pmap->pm_pcids[0].pm_gen = 0;
2806 pmap_invalidate_cache(void)
2813 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2816 pmap_update_pde_store(pmap, pde, newpde);
2817 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2818 pmap_update_pde_invalidate(pmap, va, newpde);
2820 pmap->pm_pcids[0].pm_gen = 0;
2825 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2829 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2830 * by a promotion that did not invalidate the 512 4KB page mappings
2831 * that might exist in the TLB. Consequently, at this point, the TLB
2832 * may hold both 4KB and 2MB page mappings for the address range [va,
2833 * va + NBPDR). Therefore, the entire range must be invalidated here.
2834 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2835 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2836 * single INVLPG suffices to invalidate the 2MB page mapping from the
2839 if ((pde & PG_PROMOTED) != 0)
2840 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2842 pmap_invalidate_page(pmap, va);
2845 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2846 (vm_offset_t sva, vm_offset_t eva))
2849 if ((cpu_feature & CPUID_SS) != 0)
2850 return (pmap_invalidate_cache_range_selfsnoop);
2851 if ((cpu_feature & CPUID_CLFSH) != 0)
2852 return (pmap_force_invalidate_cache_range);
2853 return (pmap_invalidate_cache_range_all);
2856 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2859 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2862 KASSERT((sva & PAGE_MASK) == 0,
2863 ("pmap_invalidate_cache_range: sva not page-aligned"));
2864 KASSERT((eva & PAGE_MASK) == 0,
2865 ("pmap_invalidate_cache_range: eva not page-aligned"));
2869 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2872 pmap_invalidate_cache_range_check_align(sva, eva);
2876 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2879 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2882 * XXX: Some CPUs fault, hang, or trash the local APIC
2883 * registers if we use CLFLUSH on the local APIC range. The
2884 * local APIC is always uncached, so we don't need to flush
2885 * for that range anyway.
2887 if (pmap_kextract(sva) == lapic_paddr)
2890 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2892 * Do per-cache line flush. Use the sfence
2893 * instruction to insure that previous stores are
2894 * included in the write-back. The processor
2895 * propagates flush to other processors in the cache
2899 for (; sva < eva; sva += cpu_clflush_line_size)
2904 * Writes are ordered by CLFLUSH on Intel CPUs.
2906 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2908 for (; sva < eva; sva += cpu_clflush_line_size)
2910 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2916 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2919 pmap_invalidate_cache_range_check_align(sva, eva);
2920 pmap_invalidate_cache();
2924 * Remove the specified set of pages from the data and instruction caches.
2926 * In contrast to pmap_invalidate_cache_range(), this function does not
2927 * rely on the CPU's self-snoop feature, because it is intended for use
2928 * when moving pages into a different cache domain.
2931 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2933 vm_offset_t daddr, eva;
2937 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2938 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2939 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2940 pmap_invalidate_cache();
2944 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2946 for (i = 0; i < count; i++) {
2947 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2948 eva = daddr + PAGE_SIZE;
2949 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2958 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2964 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2967 pmap_invalidate_cache_range_check_align(sva, eva);
2969 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2970 pmap_force_invalidate_cache_range(sva, eva);
2974 /* See comment in pmap_force_invalidate_cache_range(). */
2975 if (pmap_kextract(sva) == lapic_paddr)
2979 for (; sva < eva; sva += cpu_clflush_line_size)
2985 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2989 int error, pte_bits;
2991 KASSERT((spa & PAGE_MASK) == 0,
2992 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2993 KASSERT((epa & PAGE_MASK) == 0,
2994 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2996 if (spa < dmaplimit) {
2997 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2999 if (dmaplimit >= epa)
3004 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3006 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3008 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3009 pte = vtopte(vaddr);
3010 for (; spa < epa; spa += PAGE_SIZE) {
3012 pte_store(pte, spa | pte_bits);
3014 /* XXXKIB sfences inside flush_cache_range are excessive */
3015 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3018 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3022 * Routine: pmap_extract
3024 * Extract the physical page address associated
3025 * with the given map/virtual_address pair.
3028 pmap_extract(pmap_t pmap, vm_offset_t va)
3032 pt_entry_t *pte, PG_V;
3036 PG_V = pmap_valid_bit(pmap);
3038 pdpe = pmap_pdpe(pmap, va);
3039 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3040 if ((*pdpe & PG_PS) != 0)
3041 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3043 pde = pmap_pdpe_to_pde(pdpe, va);
3044 if ((*pde & PG_V) != 0) {
3045 if ((*pde & PG_PS) != 0) {
3046 pa = (*pde & PG_PS_FRAME) |
3049 pte = pmap_pde_to_pte(pde, va);
3050 pa = (*pte & PG_FRAME) |
3061 * Routine: pmap_extract_and_hold
3063 * Atomically extract and hold the physical page
3064 * with the given pmap and virtual address pair
3065 * if that mapping permits the given protection.
3068 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3070 pd_entry_t pde, *pdep;
3071 pt_entry_t pte, PG_RW, PG_V;
3075 PG_RW = pmap_rw_bit(pmap);
3076 PG_V = pmap_valid_bit(pmap);
3079 pdep = pmap_pde(pmap, va);
3080 if (pdep != NULL && (pde = *pdep)) {
3082 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3083 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3086 pte = *pmap_pde_to_pte(pdep, va);
3087 if ((pte & PG_V) != 0 &&
3088 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3089 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3091 if (m != NULL && !vm_page_wire_mapped(m))
3099 pmap_kextract(vm_offset_t va)
3104 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3105 pa = DMAP_TO_PHYS(va);
3106 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3107 pa = pmap_large_map_kextract(va);
3111 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3114 * Beware of a concurrent promotion that changes the
3115 * PDE at this point! For example, vtopte() must not
3116 * be used to access the PTE because it would use the
3117 * new PDE. It is, however, safe to use the old PDE
3118 * because the page table page is preserved by the
3121 pa = *pmap_pde_to_pte(&pde, va);
3122 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3128 /***************************************************
3129 * Low level mapping routines.....
3130 ***************************************************/
3133 * Add a wired page to the kva.
3134 * Note: not SMP coherent.
3137 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3142 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3145 static __inline void
3146 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3152 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3153 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3157 * Remove a page from the kernel pagetables.
3158 * Note: not SMP coherent.
3161 pmap_kremove(vm_offset_t va)
3170 * Used to map a range of physical addresses into kernel
3171 * virtual address space.
3173 * The value passed in '*virt' is a suggested virtual address for
3174 * the mapping. Architectures which can support a direct-mapped
3175 * physical to virtual region can return the appropriate address
3176 * within that region, leaving '*virt' unchanged. Other
3177 * architectures should map the pages starting at '*virt' and
3178 * update '*virt' with the first usable address after the mapped
3182 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3184 return PHYS_TO_DMAP(start);
3189 * Add a list of wired pages to the kva
3190 * this routine is only used for temporary
3191 * kernel mappings that do not need to have
3192 * page modification or references recorded.
3193 * Note that old mappings are simply written
3194 * over. The page *must* be wired.
3195 * Note: SMP coherent. Uses a ranged shootdown IPI.
3198 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3200 pt_entry_t *endpte, oldpte, pa, *pte;
3206 endpte = pte + count;
3207 while (pte < endpte) {
3209 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3210 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3211 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3213 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3217 if (__predict_false((oldpte & X86_PG_V) != 0))
3218 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3223 * This routine tears out page mappings from the
3224 * kernel -- it is meant only for temporary mappings.
3225 * Note: SMP coherent. Uses a ranged shootdown IPI.
3228 pmap_qremove(vm_offset_t sva, int count)
3233 while (count-- > 0) {
3234 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3238 pmap_invalidate_range(kernel_pmap, sva, va);
3241 /***************************************************
3242 * Page table page management routines.....
3243 ***************************************************/
3245 * Schedule the specified unused page table page to be freed. Specifically,
3246 * add the page to the specified list of pages that will be released to the
3247 * physical memory manager after the TLB has been updated.
3249 static __inline void
3250 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3251 boolean_t set_PG_ZERO)
3255 m->flags |= PG_ZERO;
3257 m->flags &= ~PG_ZERO;
3258 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3262 * Inserts the specified page table page into the specified pmap's collection
3263 * of idle page table pages. Each of a pmap's page table pages is responsible
3264 * for mapping a distinct range of virtual addresses. The pmap's collection is
3265 * ordered by this virtual address range.
3267 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3270 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3273 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3274 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3275 return (vm_radix_insert(&pmap->pm_root, mpte));
3279 * Removes the page table page mapping the specified virtual address from the
3280 * specified pmap's collection of idle page table pages, and returns it.
3281 * Otherwise, returns NULL if there is no page table page corresponding to the
3282 * specified virtual address.
3284 static __inline vm_page_t
3285 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3288 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3289 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3293 * Decrements a page table page's reference count, which is used to record the
3294 * number of valid page table entries within the page. If the reference count
3295 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3296 * page table page was unmapped and FALSE otherwise.
3298 static inline boolean_t
3299 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3303 if (m->ref_count == 0) {
3304 _pmap_unwire_ptp(pmap, va, m, free);
3311 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3314 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3316 * unmap the page table page
3318 if (m->pindex >= (NUPDE + NUPDPE)) {
3321 pml4 = pmap_pml4e(pmap, va);
3323 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3324 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3327 } else if (m->pindex >= NUPDE) {
3330 pdp = pmap_pdpe(pmap, va);
3335 pd = pmap_pde(pmap, va);
3338 pmap_resident_count_dec(pmap, 1);
3339 if (m->pindex < NUPDE) {
3340 /* We just released a PT, unhold the matching PD */
3343 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3344 pmap_unwire_ptp(pmap, va, pdpg, free);
3346 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3347 /* We just released a PD, unhold the matching PDP */
3350 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3351 pmap_unwire_ptp(pmap, va, pdppg, free);
3355 * Put page on a list so that it is released after
3356 * *ALL* TLB shootdown is done
3358 pmap_add_delayed_free_list(m, free, TRUE);
3362 * After removing a page table entry, this routine is used to
3363 * conditionally free the page, and manage the reference count.
3366 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3367 struct spglist *free)
3371 if (va >= VM_MAXUSER_ADDRESS)
3373 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3374 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3375 return (pmap_unwire_ptp(pmap, va, mpte, free));
3379 pmap_pinit0(pmap_t pmap)
3385 PMAP_LOCK_INIT(pmap);
3386 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3387 pmap->pm_pml4u = NULL;
3388 pmap->pm_cr3 = KPML4phys;
3389 /* hack to keep pmap_pti_pcid_invalidate() alive */
3390 pmap->pm_ucr3 = PMAP_NO_CR3;
3391 pmap->pm_root.rt_root = 0;
3392 CPU_ZERO(&pmap->pm_active);
3393 TAILQ_INIT(&pmap->pm_pvchunk);
3394 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3395 pmap->pm_flags = pmap_flags;
3397 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3398 pmap->pm_pcids[i].pm_gen = 1;
3400 pmap_activate_boot(pmap);
3405 p->p_md.md_flags |= P_MD_KPTI;
3408 pmap_thread_init_invl_gen(td);
3410 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3411 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3412 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3418 pmap_pinit_pml4(vm_page_t pml4pg)
3420 pml4_entry_t *pm_pml4;
3423 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3425 /* Wire in kernel global address entries. */
3426 for (i = 0; i < NKPML4E; i++) {
3427 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3430 for (i = 0; i < ndmpdpphys; i++) {
3431 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3435 /* install self-referential address mapping entry(s) */
3436 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3437 X86_PG_A | X86_PG_M;
3439 /* install large map entries if configured */
3440 for (i = 0; i < lm_ents; i++)
3441 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3445 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3447 pml4_entry_t *pm_pml4;
3450 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3451 for (i = 0; i < NPML4EPG; i++)
3452 pm_pml4[i] = pti_pml4[i];
3456 * Initialize a preallocated and zeroed pmap structure,
3457 * such as one in a vmspace structure.
3460 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3462 vm_page_t pml4pg, pml4pgu;
3463 vm_paddr_t pml4phys;
3467 * allocate the page directory page
3469 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3470 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3472 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3473 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3475 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3476 pmap->pm_pcids[i].pm_gen = 0;
3478 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3479 pmap->pm_ucr3 = PMAP_NO_CR3;
3480 pmap->pm_pml4u = NULL;
3482 pmap->pm_type = pm_type;
3483 if ((pml4pg->flags & PG_ZERO) == 0)
3484 pagezero(pmap->pm_pml4);
3487 * Do not install the host kernel mappings in the nested page
3488 * tables. These mappings are meaningless in the guest physical
3490 * Install minimal kernel mappings in PTI case.
3492 if (pm_type == PT_X86) {
3493 pmap->pm_cr3 = pml4phys;
3494 pmap_pinit_pml4(pml4pg);
3495 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3496 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3497 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3498 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3499 VM_PAGE_TO_PHYS(pml4pgu));
3500 pmap_pinit_pml4_pti(pml4pgu);
3501 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3503 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3504 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3505 pkru_free_range, pmap, M_NOWAIT);
3509 pmap->pm_root.rt_root = 0;
3510 CPU_ZERO(&pmap->pm_active);
3511 TAILQ_INIT(&pmap->pm_pvchunk);
3512 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3513 pmap->pm_flags = flags;
3514 pmap->pm_eptgen = 0;
3520 pmap_pinit(pmap_t pmap)
3523 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3527 * This routine is called if the desired page table page does not exist.
3529 * If page table page allocation fails, this routine may sleep before
3530 * returning NULL. It sleeps only if a lock pointer was given.
3532 * Note: If a page allocation fails at page table level two or three,
3533 * one or two pages may be held during the wait, only to be released
3534 * afterwards. This conservative approach is easily argued to avoid
3538 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3540 vm_page_t m, pdppg, pdpg;
3541 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3543 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3545 PG_A = pmap_accessed_bit(pmap);
3546 PG_M = pmap_modified_bit(pmap);
3547 PG_V = pmap_valid_bit(pmap);
3548 PG_RW = pmap_rw_bit(pmap);
3551 * Allocate a page table page.
3553 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3554 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3555 if (lockp != NULL) {
3556 RELEASE_PV_LIST_LOCK(lockp);
3558 PMAP_ASSERT_NOT_IN_DI();
3564 * Indicate the need to retry. While waiting, the page table
3565 * page may have been allocated.
3569 if ((m->flags & PG_ZERO) == 0)
3573 * Map the pagetable page into the process address space, if
3574 * it isn't already there.
3577 if (ptepindex >= (NUPDE + NUPDPE)) {
3578 pml4_entry_t *pml4, *pml4u;
3579 vm_pindex_t pml4index;
3581 /* Wire up a new PDPE page */
3582 pml4index = ptepindex - (NUPDE + NUPDPE);
3583 pml4 = &pmap->pm_pml4[pml4index];
3584 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3585 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3587 * PTI: Make all user-space mappings in the
3588 * kernel-mode page table no-execute so that
3589 * we detect any programming errors that leave
3590 * the kernel-mode page table active on return
3593 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3596 pml4u = &pmap->pm_pml4u[pml4index];
3597 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3601 } else if (ptepindex >= NUPDE) {
3602 vm_pindex_t pml4index;
3603 vm_pindex_t pdpindex;
3607 /* Wire up a new PDE page */
3608 pdpindex = ptepindex - NUPDE;
3609 pml4index = pdpindex >> NPML4EPGSHIFT;
3611 pml4 = &pmap->pm_pml4[pml4index];
3612 if ((*pml4 & PG_V) == 0) {
3613 /* Have to allocate a new pdp, recurse */
3614 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3616 vm_page_unwire_noq(m);
3617 vm_page_free_zero(m);
3621 /* Add reference to pdp page */
3622 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3625 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3627 /* Now find the pdp page */
3628 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3629 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3632 vm_pindex_t pml4index;
3633 vm_pindex_t pdpindex;
3638 /* Wire up a new PTE page */
3639 pdpindex = ptepindex >> NPDPEPGSHIFT;
3640 pml4index = pdpindex >> NPML4EPGSHIFT;
3642 /* First, find the pdp and check that its valid. */
3643 pml4 = &pmap->pm_pml4[pml4index];
3644 if ((*pml4 & PG_V) == 0) {
3645 /* Have to allocate a new pd, recurse */
3646 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3648 vm_page_unwire_noq(m);
3649 vm_page_free_zero(m);
3652 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3653 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3655 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3656 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3657 if ((*pdp & PG_V) == 0) {
3658 /* Have to allocate a new pd, recurse */
3659 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3661 vm_page_unwire_noq(m);
3662 vm_page_free_zero(m);
3666 /* Add reference to the pd page */
3667 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3671 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3673 /* Now we know where the page directory page is */
3674 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3675 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3678 pmap_resident_count_inc(pmap, 1);
3684 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3686 vm_pindex_t pdpindex, ptepindex;
3687 pdp_entry_t *pdpe, PG_V;
3690 PG_V = pmap_valid_bit(pmap);
3693 pdpe = pmap_pdpe(pmap, va);
3694 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3695 /* Add a reference to the pd page. */
3696 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3699 /* Allocate a pd page. */
3700 ptepindex = pmap_pde_pindex(va);
3701 pdpindex = ptepindex >> NPDPEPGSHIFT;
3702 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3703 if (pdpg == NULL && lockp != NULL)
3710 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3712 vm_pindex_t ptepindex;
3713 pd_entry_t *pd, PG_V;
3716 PG_V = pmap_valid_bit(pmap);
3719 * Calculate pagetable page index
3721 ptepindex = pmap_pde_pindex(va);
3724 * Get the page directory entry
3726 pd = pmap_pde(pmap, va);
3729 * This supports switching from a 2MB page to a
3732 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3733 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3735 * Invalidation of the 2MB page mapping may have caused
3736 * the deallocation of the underlying PD page.
3743 * If the page table page is mapped, we just increment the
3744 * hold count, and activate it.
3746 if (pd != NULL && (*pd & PG_V) != 0) {
3747 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3751 * Here if the pte page isn't mapped, or if it has been
3754 m = _pmap_allocpte(pmap, ptepindex, lockp);
3755 if (m == NULL && lockp != NULL)
3762 /***************************************************
3763 * Pmap allocation/deallocation routines.
3764 ***************************************************/
3767 * Release any resources held by the given physical map.
3768 * Called when a pmap initialized by pmap_pinit is being released.
3769 * Should only be called if the map contains no valid mappings.
3772 pmap_release(pmap_t pmap)
3777 KASSERT(pmap->pm_stats.resident_count == 0,
3778 ("pmap_release: pmap resident count %ld != 0",
3779 pmap->pm_stats.resident_count));
3780 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3781 ("pmap_release: pmap has reserved page table page(s)"));
3782 KASSERT(CPU_EMPTY(&pmap->pm_active),
3783 ("releasing active pmap %p", pmap));
3785 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3787 for (i = 0; i < NKPML4E; i++) /* KVA */
3788 pmap->pm_pml4[KPML4BASE + i] = 0;
3789 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3790 pmap->pm_pml4[DMPML4I + i] = 0;
3791 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3792 for (i = 0; i < lm_ents; i++) /* Large Map */
3793 pmap->pm_pml4[LMSPML4I + i] = 0;
3795 vm_page_unwire_noq(m);
3796 vm_page_free_zero(m);
3798 if (pmap->pm_pml4u != NULL) {
3799 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3800 vm_page_unwire_noq(m);
3803 if (pmap->pm_type == PT_X86 &&
3804 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3805 rangeset_fini(&pmap->pm_pkru);
3809 kvm_size(SYSCTL_HANDLER_ARGS)
3811 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3813 return sysctl_handle_long(oidp, &ksize, 0, req);
3815 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3816 0, 0, kvm_size, "LU", "Size of KVM");
3819 kvm_free(SYSCTL_HANDLER_ARGS)
3821 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3823 return sysctl_handle_long(oidp, &kfree, 0, req);
3825 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3826 0, 0, kvm_free, "LU", "Amount of KVM free");
3829 * Allocate physical memory for the vm_page array and map it into KVA,
3830 * attempting to back the vm_pages with domain-local memory.
3833 pmap_page_array_startup(long pages)
3836 pd_entry_t *pde, newpdir;
3837 vm_offset_t va, start, end;
3842 vm_page_array_size = pages;
3844 start = va = VM_MIN_KERNEL_ADDRESS;
3845 end = va + pages * sizeof(struct vm_page);
3847 pfn = first_page + (va - start) / sizeof(struct vm_page);
3848 domain = _vm_phys_domain(ptoa(pfn));
3849 pdpe = pmap_pdpe(kernel_pmap, va);
3850 if ((*pdpe & X86_PG_V) == 0) {
3851 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
3853 pagezero((void *)PHYS_TO_DMAP(pa));
3854 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
3855 X86_PG_A | X86_PG_M);
3857 pde = pmap_pdpe_to_pde(pdpe, va);
3858 if ((*pde & X86_PG_V) != 0)
3859 panic("Unexpected pde");
3860 pa = vm_phys_early_alloc(domain, NBPDR);
3861 for (i = 0; i < NPDEPG; i++)
3862 dump_add_page(pa + i * PAGE_SIZE);
3863 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
3864 X86_PG_M | PG_PS | pg_g | pg_nx);
3865 pde_store(pde, newpdir);
3868 vm_page_array = (vm_page_t)start;
3872 * grow the number of kernel page table entries, if needed
3875 pmap_growkernel(vm_offset_t addr)
3879 pd_entry_t *pde, newpdir;
3882 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3885 * Return if "addr" is within the range of kernel page table pages
3886 * that were preallocated during pmap bootstrap. Moreover, leave
3887 * "kernel_vm_end" and the kernel page table as they were.
3889 * The correctness of this action is based on the following
3890 * argument: vm_map_insert() allocates contiguous ranges of the
3891 * kernel virtual address space. It calls this function if a range
3892 * ends after "kernel_vm_end". If the kernel is mapped between
3893 * "kernel_vm_end" and "addr", then the range cannot begin at
3894 * "kernel_vm_end". In fact, its beginning address cannot be less
3895 * than the kernel. Thus, there is no immediate need to allocate
3896 * any new kernel page table pages between "kernel_vm_end" and
3899 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3902 addr = roundup2(addr, NBPDR);
3903 if (addr - 1 >= vm_map_max(kernel_map))
3904 addr = vm_map_max(kernel_map);
3905 while (kernel_vm_end < addr) {
3906 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3907 if ((*pdpe & X86_PG_V) == 0) {
3908 /* We need a new PDP entry */
3909 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3910 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3911 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3913 panic("pmap_growkernel: no memory to grow kernel");
3914 if ((nkpg->flags & PG_ZERO) == 0)
3915 pmap_zero_page(nkpg);
3916 paddr = VM_PAGE_TO_PHYS(nkpg);
3917 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3918 X86_PG_A | X86_PG_M);
3919 continue; /* try again */
3921 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3922 if ((*pde & X86_PG_V) != 0) {
3923 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3924 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3925 kernel_vm_end = vm_map_max(kernel_map);
3931 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3932 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3935 panic("pmap_growkernel: no memory to grow kernel");
3936 if ((nkpg->flags & PG_ZERO) == 0)
3937 pmap_zero_page(nkpg);
3938 paddr = VM_PAGE_TO_PHYS(nkpg);
3939 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3940 pde_store(pde, newpdir);
3942 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3943 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3944 kernel_vm_end = vm_map_max(kernel_map);
3951 /***************************************************
3952 * page management routines.
3953 ***************************************************/
3955 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3956 CTASSERT(_NPCM == 3);
3957 CTASSERT(_NPCPV == 168);
3959 static __inline struct pv_chunk *
3960 pv_to_chunk(pv_entry_t pv)
3963 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3966 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3968 #define PC_FREE0 0xfffffffffffffffful
3969 #define PC_FREE1 0xfffffffffffffffful
3970 #define PC_FREE2 0x000000fffffffffful
3972 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3975 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3977 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3978 "Current number of pv entry chunks");
3979 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3980 "Current number of pv entry chunks allocated");
3981 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3982 "Current number of pv entry chunks frees");
3983 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3984 "Number of times tried to get a chunk page but failed.");
3986 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3987 static int pv_entry_spare;
3989 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3990 "Current number of pv entry frees");
3991 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3992 "Current number of pv entry allocs");
3993 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3994 "Current number of pv entries");
3995 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3996 "Current number of spare pv entries");
4000 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4005 pmap_invalidate_all(pmap);
4006 if (pmap != locked_pmap)
4009 pmap_delayed_invl_finish();
4013 * We are in a serious low memory condition. Resort to
4014 * drastic measures to free some pages so we can allocate
4015 * another pv entry chunk.
4017 * Returns NULL if PV entries were reclaimed from the specified pmap.
4019 * We do not, however, unmap 2mpages because subsequent accesses will
4020 * allocate per-page pv entries until repromotion occurs, thereby
4021 * exacerbating the shortage of free pv entries.
4024 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4026 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4027 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4028 struct md_page *pvh;
4030 pmap_t next_pmap, pmap;
4031 pt_entry_t *pte, tpte;
4032 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4036 struct spglist free;
4038 int bit, field, freed;
4040 static int active_reclaims = 0;
4042 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4043 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4046 PG_G = PG_A = PG_M = PG_RW = 0;
4048 bzero(&pc_marker_b, sizeof(pc_marker_b));
4049 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4050 pc_marker = (struct pv_chunk *)&pc_marker_b;
4051 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4054 * A delayed invalidation block should already be active if
4055 * pmap_advise() or pmap_remove() called this function by way
4056 * of pmap_demote_pde_locked().
4058 start_di = pmap_not_in_di();
4060 mtx_lock(&pv_chunks_mutex);
4062 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
4063 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
4064 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4065 SLIST_EMPTY(&free)) {
4066 next_pmap = pc->pc_pmap;
4067 if (next_pmap == NULL) {
4069 * The next chunk is a marker. However, it is
4070 * not our marker, so active_reclaims must be
4071 * > 1. Consequently, the next_chunk code
4072 * will not rotate the pv_chunks list.
4076 mtx_unlock(&pv_chunks_mutex);
4079 * A pv_chunk can only be removed from the pc_lru list
4080 * when both pc_chunks_mutex is owned and the
4081 * corresponding pmap is locked.
4083 if (pmap != next_pmap) {
4084 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4087 /* Avoid deadlock and lock recursion. */
4088 if (pmap > locked_pmap) {
4089 RELEASE_PV_LIST_LOCK(lockp);
4092 pmap_delayed_invl_start();
4093 mtx_lock(&pv_chunks_mutex);
4095 } else if (pmap != locked_pmap) {
4096 if (PMAP_TRYLOCK(pmap)) {
4098 pmap_delayed_invl_start();
4099 mtx_lock(&pv_chunks_mutex);
4102 pmap = NULL; /* pmap is not locked */
4103 mtx_lock(&pv_chunks_mutex);
4104 pc = TAILQ_NEXT(pc_marker, pc_lru);
4106 pc->pc_pmap != next_pmap)
4110 } else if (start_di)
4111 pmap_delayed_invl_start();
4112 PG_G = pmap_global_bit(pmap);
4113 PG_A = pmap_accessed_bit(pmap);
4114 PG_M = pmap_modified_bit(pmap);
4115 PG_RW = pmap_rw_bit(pmap);
4119 * Destroy every non-wired, 4 KB page mapping in the chunk.
4122 for (field = 0; field < _NPCM; field++) {
4123 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4124 inuse != 0; inuse &= ~(1UL << bit)) {
4126 pv = &pc->pc_pventry[field * 64 + bit];
4128 pde = pmap_pde(pmap, va);
4129 if ((*pde & PG_PS) != 0)
4131 pte = pmap_pde_to_pte(pde, va);
4132 if ((*pte & PG_W) != 0)
4134 tpte = pte_load_clear(pte);
4135 if ((tpte & PG_G) != 0)
4136 pmap_invalidate_page(pmap, va);
4137 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4138 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4140 if ((tpte & PG_A) != 0)
4141 vm_page_aflag_set(m, PGA_REFERENCED);
4142 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4143 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4145 if (TAILQ_EMPTY(&m->md.pv_list) &&
4146 (m->flags & PG_FICTITIOUS) == 0) {
4147 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4148 if (TAILQ_EMPTY(&pvh->pv_list)) {
4149 vm_page_aflag_clear(m,
4153 pmap_delayed_invl_page(m);
4154 pc->pc_map[field] |= 1UL << bit;
4155 pmap_unuse_pt(pmap, va, *pde, &free);
4160 mtx_lock(&pv_chunks_mutex);
4163 /* Every freed mapping is for a 4 KB page. */
4164 pmap_resident_count_dec(pmap, freed);
4165 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4166 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4167 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4168 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4169 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4170 pc->pc_map[2] == PC_FREE2) {
4171 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4172 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4173 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4174 /* Entire chunk is free; return it. */
4175 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4176 dump_drop_page(m_pc->phys_addr);
4177 mtx_lock(&pv_chunks_mutex);
4178 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4181 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4182 mtx_lock(&pv_chunks_mutex);
4183 /* One freed pv entry in locked_pmap is sufficient. */
4184 if (pmap == locked_pmap)
4187 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4188 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
4189 if (active_reclaims == 1 && pmap != NULL) {
4191 * Rotate the pv chunks list so that we do not
4192 * scan the same pv chunks that could not be
4193 * freed (because they contained a wired
4194 * and/or superpage mapping) on every
4195 * invocation of reclaim_pv_chunk().
4197 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4198 MPASS(pc->pc_pmap != NULL);
4199 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4200 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4204 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4205 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4207 mtx_unlock(&pv_chunks_mutex);
4208 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4209 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4210 m_pc = SLIST_FIRST(&free);
4211 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4212 /* Recycle a freed page table page. */
4213 m_pc->ref_count = 1;
4215 vm_page_free_pages_toq(&free, true);
4220 * free the pv_entry back to the free list
4223 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4225 struct pv_chunk *pc;
4226 int idx, field, bit;
4228 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4229 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4230 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4231 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4232 pc = pv_to_chunk(pv);
4233 idx = pv - &pc->pc_pventry[0];
4236 pc->pc_map[field] |= 1ul << bit;
4237 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4238 pc->pc_map[2] != PC_FREE2) {
4239 /* 98% of the time, pc is already at the head of the list. */
4240 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4241 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4242 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4246 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4251 free_pv_chunk(struct pv_chunk *pc)
4255 mtx_lock(&pv_chunks_mutex);
4256 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4257 mtx_unlock(&pv_chunks_mutex);
4258 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4259 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4260 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4261 /* entire chunk is free, return it */
4262 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4263 dump_drop_page(m->phys_addr);
4264 vm_page_unwire_noq(m);
4269 * Returns a new PV entry, allocating a new PV chunk from the system when
4270 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4271 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4274 * The given PV list lock may be released.
4277 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4281 struct pv_chunk *pc;
4284 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4285 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4287 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4289 for (field = 0; field < _NPCM; field++) {
4290 if (pc->pc_map[field]) {
4291 bit = bsfq(pc->pc_map[field]);
4295 if (field < _NPCM) {
4296 pv = &pc->pc_pventry[field * 64 + bit];
4297 pc->pc_map[field] &= ~(1ul << bit);
4298 /* If this was the last item, move it to tail */
4299 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4300 pc->pc_map[2] == 0) {
4301 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4302 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4305 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4306 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4310 /* No free items, allocate another chunk */
4311 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4314 if (lockp == NULL) {
4315 PV_STAT(pc_chunk_tryfail++);
4318 m = reclaim_pv_chunk(pmap, lockp);
4322 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4323 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4324 dump_add_page(m->phys_addr);
4325 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4327 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4328 pc->pc_map[1] = PC_FREE1;
4329 pc->pc_map[2] = PC_FREE2;
4330 mtx_lock(&pv_chunks_mutex);
4331 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4332 mtx_unlock(&pv_chunks_mutex);
4333 pv = &pc->pc_pventry[0];
4334 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4335 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4336 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4341 * Returns the number of one bits within the given PV chunk map.
4343 * The erratas for Intel processors state that "POPCNT Instruction May
4344 * Take Longer to Execute Than Expected". It is believed that the
4345 * issue is the spurious dependency on the destination register.
4346 * Provide a hint to the register rename logic that the destination
4347 * value is overwritten, by clearing it, as suggested in the
4348 * optimization manual. It should be cheap for unaffected processors
4351 * Reference numbers for erratas are
4352 * 4th Gen Core: HSD146
4353 * 5th Gen Core: BDM85
4354 * 6th Gen Core: SKL029
4357 popcnt_pc_map_pq(uint64_t *map)
4361 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4362 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4363 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4364 : "=&r" (result), "=&r" (tmp)
4365 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4370 * Ensure that the number of spare PV entries in the specified pmap meets or
4371 * exceeds the given count, "needed".
4373 * The given PV list lock may be released.
4376 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4378 struct pch new_tail;
4379 struct pv_chunk *pc;
4384 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4385 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4388 * Newly allocated PV chunks must be stored in a private list until
4389 * the required number of PV chunks have been allocated. Otherwise,
4390 * reclaim_pv_chunk() could recycle one of these chunks. In
4391 * contrast, these chunks must be added to the pmap upon allocation.
4393 TAILQ_INIT(&new_tail);
4396 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4398 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4399 bit_count((bitstr_t *)pc->pc_map, 0,
4400 sizeof(pc->pc_map) * NBBY, &free);
4403 free = popcnt_pc_map_pq(pc->pc_map);
4407 if (avail >= needed)
4410 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4411 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4414 m = reclaim_pv_chunk(pmap, lockp);
4419 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4420 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4421 dump_add_page(m->phys_addr);
4422 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4424 pc->pc_map[0] = PC_FREE0;
4425 pc->pc_map[1] = PC_FREE1;
4426 pc->pc_map[2] = PC_FREE2;
4427 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4428 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4429 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4432 * The reclaim might have freed a chunk from the current pmap.
4433 * If that chunk contained available entries, we need to
4434 * re-count the number of available entries.
4439 if (!TAILQ_EMPTY(&new_tail)) {
4440 mtx_lock(&pv_chunks_mutex);
4441 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4442 mtx_unlock(&pv_chunks_mutex);
4447 * First find and then remove the pv entry for the specified pmap and virtual
4448 * address from the specified pv list. Returns the pv entry if found and NULL
4449 * otherwise. This operation can be performed on pv lists for either 4KB or
4450 * 2MB page mappings.
4452 static __inline pv_entry_t
4453 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4457 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4458 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4459 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4468 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4469 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4470 * entries for each of the 4KB page mappings.
4473 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4474 struct rwlock **lockp)
4476 struct md_page *pvh;
4477 struct pv_chunk *pc;
4479 vm_offset_t va_last;
4483 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4484 KASSERT((pa & PDRMASK) == 0,
4485 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4486 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4489 * Transfer the 2mpage's pv entry for this mapping to the first
4490 * page's pv list. Once this transfer begins, the pv list lock
4491 * must not be released until the last pv entry is reinstantiated.
4493 pvh = pa_to_pvh(pa);
4494 va = trunc_2mpage(va);
4495 pv = pmap_pvh_remove(pvh, pmap, va);
4496 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4497 m = PHYS_TO_VM_PAGE(pa);
4498 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4500 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4501 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4502 va_last = va + NBPDR - PAGE_SIZE;
4504 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4505 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4506 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4507 for (field = 0; field < _NPCM; field++) {
4508 while (pc->pc_map[field]) {
4509 bit = bsfq(pc->pc_map[field]);
4510 pc->pc_map[field] &= ~(1ul << bit);
4511 pv = &pc->pc_pventry[field * 64 + bit];
4515 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4516 ("pmap_pv_demote_pde: page %p is not managed", m));
4517 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4523 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4524 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4527 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4528 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4529 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4531 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4532 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4535 #if VM_NRESERVLEVEL > 0
4537 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4538 * replace the many pv entries for the 4KB page mappings by a single pv entry
4539 * for the 2MB page mapping.
4542 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4543 struct rwlock **lockp)
4545 struct md_page *pvh;
4547 vm_offset_t va_last;
4550 KASSERT((pa & PDRMASK) == 0,
4551 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4552 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4555 * Transfer the first page's pv entry for this mapping to the 2mpage's
4556 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4557 * a transfer avoids the possibility that get_pv_entry() calls
4558 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4559 * mappings that is being promoted.
4561 m = PHYS_TO_VM_PAGE(pa);
4562 va = trunc_2mpage(va);
4563 pv = pmap_pvh_remove(&m->md, pmap, va);
4564 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4565 pvh = pa_to_pvh(pa);
4566 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4568 /* Free the remaining NPTEPG - 1 pv entries. */
4569 va_last = va + NBPDR - PAGE_SIZE;
4573 pmap_pvh_free(&m->md, pmap, va);
4574 } while (va < va_last);
4576 #endif /* VM_NRESERVLEVEL > 0 */
4579 * First find and then destroy the pv entry for the specified pmap and virtual
4580 * address. This operation can be performed on pv lists for either 4KB or 2MB
4584 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4588 pv = pmap_pvh_remove(pvh, pmap, va);
4589 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4590 free_pv_entry(pmap, pv);
4594 * Conditionally create the PV entry for a 4KB page mapping if the required
4595 * memory can be allocated without resorting to reclamation.
4598 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4599 struct rwlock **lockp)
4603 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4604 /* Pass NULL instead of the lock pointer to disable reclamation. */
4605 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4607 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4608 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4616 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4617 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4618 * false if the PV entry cannot be allocated without resorting to reclamation.
4621 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4622 struct rwlock **lockp)
4624 struct md_page *pvh;
4628 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4629 /* Pass NULL instead of the lock pointer to disable reclamation. */
4630 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4631 NULL : lockp)) == NULL)
4634 pa = pde & PG_PS_FRAME;
4635 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4636 pvh = pa_to_pvh(pa);
4637 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4643 * Fills a page table page with mappings to consecutive physical pages.
4646 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4650 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4652 newpte += PAGE_SIZE;
4657 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4658 * mapping is invalidated.
4661 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4663 struct rwlock *lock;
4667 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4674 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4678 pt_entry_t *xpte, *ypte;
4680 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4681 xpte++, newpte += PAGE_SIZE) {
4682 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4683 printf("pmap_demote_pde: xpte %zd and newpte map "
4684 "different pages: found %#lx, expected %#lx\n",
4685 xpte - firstpte, *xpte, newpte);
4686 printf("page table dump\n");
4687 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4688 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4693 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4694 ("pmap_demote_pde: firstpte and newpte map different physical"
4701 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4702 pd_entry_t oldpde, struct rwlock **lockp)
4704 struct spglist free;
4708 sva = trunc_2mpage(va);
4709 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4710 if ((oldpde & pmap_global_bit(pmap)) == 0)
4711 pmap_invalidate_pde_page(pmap, sva, oldpde);
4712 vm_page_free_pages_toq(&free, true);
4713 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
4718 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4719 struct rwlock **lockp)
4721 pd_entry_t newpde, oldpde;
4722 pt_entry_t *firstpte, newpte;
4723 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4729 PG_A = pmap_accessed_bit(pmap);
4730 PG_G = pmap_global_bit(pmap);
4731 PG_M = pmap_modified_bit(pmap);
4732 PG_RW = pmap_rw_bit(pmap);
4733 PG_V = pmap_valid_bit(pmap);
4734 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4735 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4737 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4738 in_kernel = va >= VM_MAXUSER_ADDRESS;
4740 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4741 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4744 * Invalidate the 2MB page mapping and return "failure" if the
4745 * mapping was never accessed.
4747 if ((oldpde & PG_A) == 0) {
4748 KASSERT((oldpde & PG_W) == 0,
4749 ("pmap_demote_pde: a wired mapping is missing PG_A"));
4750 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4754 mpte = pmap_remove_pt_page(pmap, va);
4756 KASSERT((oldpde & PG_W) == 0,
4757 ("pmap_demote_pde: page table page for a wired mapping"
4761 * If the page table page is missing and the mapping
4762 * is for a kernel address, the mapping must belong to
4763 * the direct map. Page table pages are preallocated
4764 * for every other part of the kernel address space,
4765 * so the direct map region is the only part of the
4766 * kernel address space that must be handled here.
4768 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
4769 va < DMAP_MAX_ADDRESS),
4770 ("pmap_demote_pde: No saved mpte for va %#lx", va));
4773 * If the 2MB page mapping belongs to the direct map
4774 * region of the kernel's address space, then the page
4775 * allocation request specifies the highest possible
4776 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
4777 * priority is normal.
4779 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
4780 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4781 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4784 * If the allocation of the new page table page fails,
4785 * invalidate the 2MB page mapping and return "failure".
4788 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4793 mpte->ref_count = NPTEPG;
4794 pmap_resident_count_inc(pmap, 1);
4797 mptepa = VM_PAGE_TO_PHYS(mpte);
4798 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4799 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4800 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4801 ("pmap_demote_pde: oldpde is missing PG_M"));
4802 newpte = oldpde & ~PG_PS;
4803 newpte = pmap_swap_pat(pmap, newpte);
4806 * If the page table page is not leftover from an earlier promotion,
4809 if (mpte->valid == 0)
4810 pmap_fill_ptp(firstpte, newpte);
4812 pmap_demote_pde_check(firstpte, newpte);
4815 * If the mapping has changed attributes, update the page table
4818 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4819 pmap_fill_ptp(firstpte, newpte);
4822 * The spare PV entries must be reserved prior to demoting the
4823 * mapping, that is, prior to changing the PDE. Otherwise, the state
4824 * of the PDE and the PV lists will be inconsistent, which can result
4825 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4826 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4827 * PV entry for the 2MB page mapping that is being demoted.
4829 if ((oldpde & PG_MANAGED) != 0)
4830 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4833 * Demote the mapping. This pmap is locked. The old PDE has
4834 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4835 * set. Thus, there is no danger of a race with another
4836 * processor changing the setting of PG_A and/or PG_M between
4837 * the read above and the store below.
4839 if (workaround_erratum383)
4840 pmap_update_pde(pmap, va, pde, newpde);
4842 pde_store(pde, newpde);
4845 * Invalidate a stale recursive mapping of the page table page.
4848 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4851 * Demote the PV entry.
4853 if ((oldpde & PG_MANAGED) != 0)
4854 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4856 atomic_add_long(&pmap_pde_demotions, 1);
4857 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
4863 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4866 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4872 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4873 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4874 mpte = pmap_remove_pt_page(pmap, va);
4876 panic("pmap_remove_kernel_pde: Missing pt page.");
4878 mptepa = VM_PAGE_TO_PHYS(mpte);
4879 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4882 * If this page table page was unmapped by a promotion, then it
4883 * contains valid mappings. Zero it to invalidate those mappings.
4885 if (mpte->valid != 0)
4886 pagezero((void *)PHYS_TO_DMAP(mptepa));
4889 * Demote the mapping.
4891 if (workaround_erratum383)
4892 pmap_update_pde(pmap, va, pde, newpde);
4894 pde_store(pde, newpde);
4897 * Invalidate a stale recursive mapping of the page table page.
4899 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4903 * pmap_remove_pde: do the things to unmap a superpage in a process
4906 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4907 struct spglist *free, struct rwlock **lockp)
4909 struct md_page *pvh;
4911 vm_offset_t eva, va;
4913 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4915 PG_G = pmap_global_bit(pmap);
4916 PG_A = pmap_accessed_bit(pmap);
4917 PG_M = pmap_modified_bit(pmap);
4918 PG_RW = pmap_rw_bit(pmap);
4920 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4921 KASSERT((sva & PDRMASK) == 0,
4922 ("pmap_remove_pde: sva is not 2mpage aligned"));
4923 oldpde = pte_load_clear(pdq);
4925 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4926 if ((oldpde & PG_G) != 0)
4927 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4928 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4929 if (oldpde & PG_MANAGED) {
4930 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4931 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4932 pmap_pvh_free(pvh, pmap, sva);
4934 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4935 va < eva; va += PAGE_SIZE, m++) {
4936 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4939 vm_page_aflag_set(m, PGA_REFERENCED);
4940 if (TAILQ_EMPTY(&m->md.pv_list) &&
4941 TAILQ_EMPTY(&pvh->pv_list))
4942 vm_page_aflag_clear(m, PGA_WRITEABLE);
4943 pmap_delayed_invl_page(m);
4946 if (pmap == kernel_pmap) {
4947 pmap_remove_kernel_pde(pmap, pdq, sva);
4949 mpte = pmap_remove_pt_page(pmap, sva);
4951 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4952 ("pmap_remove_pde: pte page not promoted"));
4953 pmap_resident_count_dec(pmap, 1);
4954 KASSERT(mpte->ref_count == NPTEPG,
4955 ("pmap_remove_pde: pte page ref count error"));
4956 mpte->ref_count = 0;
4957 pmap_add_delayed_free_list(mpte, free, FALSE);
4960 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4964 * pmap_remove_pte: do the things to unmap a page in a process
4967 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4968 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4970 struct md_page *pvh;
4971 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4974 PG_A = pmap_accessed_bit(pmap);
4975 PG_M = pmap_modified_bit(pmap);
4976 PG_RW = pmap_rw_bit(pmap);
4978 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4979 oldpte = pte_load_clear(ptq);
4981 pmap->pm_stats.wired_count -= 1;
4982 pmap_resident_count_dec(pmap, 1);
4983 if (oldpte & PG_MANAGED) {
4984 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4985 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4988 vm_page_aflag_set(m, PGA_REFERENCED);
4989 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4990 pmap_pvh_free(&m->md, pmap, va);
4991 if (TAILQ_EMPTY(&m->md.pv_list) &&
4992 (m->flags & PG_FICTITIOUS) == 0) {
4993 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4994 if (TAILQ_EMPTY(&pvh->pv_list))
4995 vm_page_aflag_clear(m, PGA_WRITEABLE);
4997 pmap_delayed_invl_page(m);
4999 return (pmap_unuse_pt(pmap, va, ptepde, free));
5003 * Remove a single page from a process address space
5006 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5007 struct spglist *free)
5009 struct rwlock *lock;
5010 pt_entry_t *pte, PG_V;
5012 PG_V = pmap_valid_bit(pmap);
5013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5014 if ((*pde & PG_V) == 0)
5016 pte = pmap_pde_to_pte(pde, va);
5017 if ((*pte & PG_V) == 0)
5020 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5023 pmap_invalidate_page(pmap, va);
5027 * Removes the specified range of addresses from the page table page.
5030 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5031 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5033 pt_entry_t PG_G, *pte;
5037 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5038 PG_G = pmap_global_bit(pmap);
5041 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5045 pmap_invalidate_range(pmap, va, sva);
5050 if ((*pte & PG_G) == 0)
5054 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5060 pmap_invalidate_range(pmap, va, sva);
5065 * Remove the given range of addresses from the specified map.
5067 * It is assumed that the start and end are properly
5068 * rounded to the page size.
5071 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5073 struct rwlock *lock;
5074 vm_offset_t va_next;
5075 pml4_entry_t *pml4e;
5077 pd_entry_t ptpaddr, *pde;
5078 pt_entry_t PG_G, PG_V;
5079 struct spglist free;
5082 PG_G = pmap_global_bit(pmap);
5083 PG_V = pmap_valid_bit(pmap);
5086 * Perform an unsynchronized read. This is, however, safe.
5088 if (pmap->pm_stats.resident_count == 0)
5094 pmap_delayed_invl_start();
5096 pmap_pkru_on_remove(pmap, sva, eva);
5099 * special handling of removing one page. a very
5100 * common operation and easy to short circuit some
5103 if (sva + PAGE_SIZE == eva) {
5104 pde = pmap_pde(pmap, sva);
5105 if (pde && (*pde & PG_PS) == 0) {
5106 pmap_remove_page(pmap, sva, pde, &free);
5112 for (; sva < eva; sva = va_next) {
5114 if (pmap->pm_stats.resident_count == 0)
5117 pml4e = pmap_pml4e(pmap, sva);
5118 if ((*pml4e & PG_V) == 0) {
5119 va_next = (sva + NBPML4) & ~PML4MASK;
5125 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5126 if ((*pdpe & PG_V) == 0) {
5127 va_next = (sva + NBPDP) & ~PDPMASK;
5134 * Calculate index for next page table.
5136 va_next = (sva + NBPDR) & ~PDRMASK;
5140 pde = pmap_pdpe_to_pde(pdpe, sva);
5144 * Weed out invalid mappings.
5150 * Check for large page.
5152 if ((ptpaddr & PG_PS) != 0) {
5154 * Are we removing the entire large page? If not,
5155 * demote the mapping and fall through.
5157 if (sva + NBPDR == va_next && eva >= va_next) {
5159 * The TLB entry for a PG_G mapping is
5160 * invalidated by pmap_remove_pde().
5162 if ((ptpaddr & PG_G) == 0)
5164 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5166 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5168 /* The large page mapping was destroyed. */
5175 * Limit our scan to either the end of the va represented
5176 * by the current page table page, or to the end of the
5177 * range being removed.
5182 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5189 pmap_invalidate_all(pmap);
5191 pmap_delayed_invl_finish();
5192 vm_page_free_pages_toq(&free, true);
5196 * Routine: pmap_remove_all
5198 * Removes this physical page from
5199 * all physical maps in which it resides.
5200 * Reflects back modify bits to the pager.
5203 * Original versions of this routine were very
5204 * inefficient because they iteratively called
5205 * pmap_remove (slow...)
5209 pmap_remove_all(vm_page_t m)
5211 struct md_page *pvh;
5214 struct rwlock *lock;
5215 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5218 struct spglist free;
5219 int pvh_gen, md_gen;
5221 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5222 ("pmap_remove_all: page %p is not managed", m));
5224 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5225 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5226 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5229 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5231 if (!PMAP_TRYLOCK(pmap)) {
5232 pvh_gen = pvh->pv_gen;
5236 if (pvh_gen != pvh->pv_gen) {
5243 pde = pmap_pde(pmap, va);
5244 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5247 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5249 if (!PMAP_TRYLOCK(pmap)) {
5250 pvh_gen = pvh->pv_gen;
5251 md_gen = m->md.pv_gen;
5255 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5261 PG_A = pmap_accessed_bit(pmap);
5262 PG_M = pmap_modified_bit(pmap);
5263 PG_RW = pmap_rw_bit(pmap);
5264 pmap_resident_count_dec(pmap, 1);
5265 pde = pmap_pde(pmap, pv->pv_va);
5266 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5267 " a 2mpage in page %p's pv list", m));
5268 pte = pmap_pde_to_pte(pde, pv->pv_va);
5269 tpte = pte_load_clear(pte);
5271 pmap->pm_stats.wired_count--;
5273 vm_page_aflag_set(m, PGA_REFERENCED);
5276 * Update the vm_page_t clean and reference bits.
5278 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5280 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5281 pmap_invalidate_page(pmap, pv->pv_va);
5282 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5284 free_pv_entry(pmap, pv);
5287 vm_page_aflag_clear(m, PGA_WRITEABLE);
5289 pmap_delayed_invl_wait(m);
5290 vm_page_free_pages_toq(&free, true);
5294 * pmap_protect_pde: do the things to protect a 2mpage in a process
5297 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5299 pd_entry_t newpde, oldpde;
5301 boolean_t anychanged;
5302 pt_entry_t PG_G, PG_M, PG_RW;
5304 PG_G = pmap_global_bit(pmap);
5305 PG_M = pmap_modified_bit(pmap);
5306 PG_RW = pmap_rw_bit(pmap);
5308 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5309 KASSERT((sva & PDRMASK) == 0,
5310 ("pmap_protect_pde: sva is not 2mpage aligned"));
5313 oldpde = newpde = *pde;
5314 if ((prot & VM_PROT_WRITE) == 0) {
5315 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5316 (PG_MANAGED | PG_M | PG_RW)) {
5317 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5318 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5321 newpde &= ~(PG_RW | PG_M);
5323 if ((prot & VM_PROT_EXECUTE) == 0)
5325 if (newpde != oldpde) {
5327 * As an optimization to future operations on this PDE, clear
5328 * PG_PROMOTED. The impending invalidation will remove any
5329 * lingering 4KB page mappings from the TLB.
5331 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5333 if ((oldpde & PG_G) != 0)
5334 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5338 return (anychanged);
5342 * Set the physical protection on the
5343 * specified range of this map as requested.
5346 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5348 vm_offset_t va_next;
5349 pml4_entry_t *pml4e;
5351 pd_entry_t ptpaddr, *pde;
5352 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5353 boolean_t anychanged;
5355 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5356 if (prot == VM_PROT_NONE) {
5357 pmap_remove(pmap, sva, eva);
5361 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5362 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5365 PG_G = pmap_global_bit(pmap);
5366 PG_M = pmap_modified_bit(pmap);
5367 PG_V = pmap_valid_bit(pmap);
5368 PG_RW = pmap_rw_bit(pmap);
5372 * Although this function delays and batches the invalidation
5373 * of stale TLB entries, it does not need to call
5374 * pmap_delayed_invl_start() and
5375 * pmap_delayed_invl_finish(), because it does not
5376 * ordinarily destroy mappings. Stale TLB entries from
5377 * protection-only changes need only be invalidated before the
5378 * pmap lock is released, because protection-only changes do
5379 * not destroy PV entries. Even operations that iterate over
5380 * a physical page's PV list of mappings, like
5381 * pmap_remove_write(), acquire the pmap lock for each
5382 * mapping. Consequently, for protection-only changes, the
5383 * pmap lock suffices to synchronize both page table and TLB
5386 * This function only destroys a mapping if pmap_demote_pde()
5387 * fails. In that case, stale TLB entries are immediately
5392 for (; sva < eva; sva = va_next) {
5394 pml4e = pmap_pml4e(pmap, sva);
5395 if ((*pml4e & PG_V) == 0) {
5396 va_next = (sva + NBPML4) & ~PML4MASK;
5402 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5403 if ((*pdpe & PG_V) == 0) {
5404 va_next = (sva + NBPDP) & ~PDPMASK;
5410 va_next = (sva + NBPDR) & ~PDRMASK;
5414 pde = pmap_pdpe_to_pde(pdpe, sva);
5418 * Weed out invalid mappings.
5424 * Check for large page.
5426 if ((ptpaddr & PG_PS) != 0) {
5428 * Are we protecting the entire large page? If not,
5429 * demote the mapping and fall through.
5431 if (sva + NBPDR == va_next && eva >= va_next) {
5433 * The TLB entry for a PG_G mapping is
5434 * invalidated by pmap_protect_pde().
5436 if (pmap_protect_pde(pmap, pde, sva, prot))
5439 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5441 * The large page mapping was destroyed.
5450 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5452 pt_entry_t obits, pbits;
5456 obits = pbits = *pte;
5457 if ((pbits & PG_V) == 0)
5460 if ((prot & VM_PROT_WRITE) == 0) {
5461 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5462 (PG_MANAGED | PG_M | PG_RW)) {
5463 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5466 pbits &= ~(PG_RW | PG_M);
5468 if ((prot & VM_PROT_EXECUTE) == 0)
5471 if (pbits != obits) {
5472 if (!atomic_cmpset_long(pte, obits, pbits))
5475 pmap_invalidate_page(pmap, sva);
5482 pmap_invalidate_all(pmap);
5486 #if VM_NRESERVLEVEL > 0
5488 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5489 * single page table page (PTP) to a single 2MB page mapping. For promotion
5490 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5491 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5492 * identical characteristics.
5495 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5496 struct rwlock **lockp)
5499 pt_entry_t *firstpte, oldpte, pa, *pte;
5500 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5504 PG_A = pmap_accessed_bit(pmap);
5505 PG_G = pmap_global_bit(pmap);
5506 PG_M = pmap_modified_bit(pmap);
5507 PG_V = pmap_valid_bit(pmap);
5508 PG_RW = pmap_rw_bit(pmap);
5509 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5510 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5512 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5515 * Examine the first PTE in the specified PTP. Abort if this PTE is
5516 * either invalid, unused, or does not map the first 4KB physical page
5517 * within a 2MB page.
5519 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5522 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
5523 atomic_add_long(&pmap_pde_p_failures, 1);
5524 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5525 " in pmap %p", va, pmap);
5528 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5530 * When PG_M is already clear, PG_RW can be cleared without
5531 * a TLB invalidation.
5533 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5539 * Examine each of the other PTEs in the specified PTP. Abort if this
5540 * PTE maps an unexpected 4KB physical page or does not have identical
5541 * characteristics to the first PTE.
5543 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5544 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5547 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5548 atomic_add_long(&pmap_pde_p_failures, 1);
5549 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5550 " in pmap %p", va, pmap);
5553 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5555 * When PG_M is already clear, PG_RW can be cleared
5556 * without a TLB invalidation.
5558 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5561 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5562 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5563 (va & ~PDRMASK), pmap);
5565 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5566 atomic_add_long(&pmap_pde_p_failures, 1);
5567 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5568 " in pmap %p", va, pmap);
5575 * Save the page table page in its current state until the PDE
5576 * mapping the superpage is demoted by pmap_demote_pde() or
5577 * destroyed by pmap_remove_pde().
5579 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5580 KASSERT(mpte >= vm_page_array &&
5581 mpte < &vm_page_array[vm_page_array_size],
5582 ("pmap_promote_pde: page table page is out of range"));
5583 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5584 ("pmap_promote_pde: page table page's pindex is wrong"));
5585 if (pmap_insert_pt_page(pmap, mpte, true)) {
5586 atomic_add_long(&pmap_pde_p_failures, 1);
5588 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5594 * Promote the pv entries.
5596 if ((newpde & PG_MANAGED) != 0)
5597 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5600 * Propagate the PAT index to its proper position.
5602 newpde = pmap_swap_pat(pmap, newpde);
5605 * Map the superpage.
5607 if (workaround_erratum383)
5608 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5610 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5612 atomic_add_long(&pmap_pde_promotions, 1);
5613 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5614 " in pmap %p", va, pmap);
5616 #endif /* VM_NRESERVLEVEL > 0 */
5619 * Insert the given physical page (p) at
5620 * the specified virtual address (v) in the
5621 * target physical map with the protection requested.
5623 * If specified, the page will be wired down, meaning
5624 * that the related pte can not be reclaimed.
5626 * NB: This is the only routine which MAY NOT lazy-evaluate
5627 * or lose information. That is, this routine must actually
5628 * insert this page into the given map NOW.
5630 * When destroying both a page table and PV entry, this function
5631 * performs the TLB invalidation before releasing the PV list
5632 * lock, so we do not need pmap_delayed_invl_page() calls here.
5635 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5636 u_int flags, int8_t psind)
5638 struct rwlock *lock;
5640 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5641 pt_entry_t newpte, origpte;
5648 PG_A = pmap_accessed_bit(pmap);
5649 PG_G = pmap_global_bit(pmap);
5650 PG_M = pmap_modified_bit(pmap);
5651 PG_V = pmap_valid_bit(pmap);
5652 PG_RW = pmap_rw_bit(pmap);
5654 va = trunc_page(va);
5655 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5656 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5657 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5659 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5660 va >= kmi.clean_eva,
5661 ("pmap_enter: managed mapping within the clean submap"));
5662 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5663 VM_OBJECT_ASSERT_LOCKED(m->object);
5664 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5665 ("pmap_enter: flags %u has reserved bits set", flags));
5666 pa = VM_PAGE_TO_PHYS(m);
5667 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5668 if ((flags & VM_PROT_WRITE) != 0)
5670 if ((prot & VM_PROT_WRITE) != 0)
5672 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5673 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5674 if ((prot & VM_PROT_EXECUTE) == 0)
5676 if ((flags & PMAP_ENTER_WIRED) != 0)
5678 if (va < VM_MAXUSER_ADDRESS)
5680 if (pmap == kernel_pmap)
5682 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5685 * Set modified bit gratuitously for writeable mappings if
5686 * the page is unmanaged. We do not want to take a fault
5687 * to do the dirty bit accounting for these mappings.
5689 if ((m->oflags & VPO_UNMANAGED) != 0) {
5690 if ((newpte & PG_RW) != 0)
5693 newpte |= PG_MANAGED;
5698 /* Assert the required virtual and physical alignment. */
5699 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5700 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5701 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5707 * In the case that a page table page is not
5708 * resident, we are creating it here.
5711 pde = pmap_pde(pmap, va);
5712 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5713 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5714 pte = pmap_pde_to_pte(pde, va);
5715 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5716 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5719 } else if (va < VM_MAXUSER_ADDRESS) {
5721 * Here if the pte page isn't mapped, or if it has been
5724 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5725 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5726 nosleep ? NULL : &lock);
5727 if (mpte == NULL && nosleep) {
5728 rv = KERN_RESOURCE_SHORTAGE;
5733 panic("pmap_enter: invalid page directory va=%#lx", va);
5737 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5738 newpte |= pmap_pkru_get(pmap, va);
5741 * Is the specified virtual address already mapped?
5743 if ((origpte & PG_V) != 0) {
5745 * Wiring change, just update stats. We don't worry about
5746 * wiring PT pages as they remain resident as long as there
5747 * are valid mappings in them. Hence, if a user page is wired,
5748 * the PT page will be also.
5750 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5751 pmap->pm_stats.wired_count++;
5752 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5753 pmap->pm_stats.wired_count--;
5756 * Remove the extra PT page reference.
5760 KASSERT(mpte->ref_count > 0,
5761 ("pmap_enter: missing reference to page table page,"
5766 * Has the physical page changed?
5768 opa = origpte & PG_FRAME;
5771 * No, might be a protection or wiring change.
5773 if ((origpte & PG_MANAGED) != 0 &&
5774 (newpte & PG_RW) != 0)
5775 vm_page_aflag_set(m, PGA_WRITEABLE);
5776 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5782 * The physical page has changed. Temporarily invalidate
5783 * the mapping. This ensures that all threads sharing the
5784 * pmap keep a consistent view of the mapping, which is
5785 * necessary for the correct handling of COW faults. It
5786 * also permits reuse of the old mapping's PV entry,
5787 * avoiding an allocation.
5789 * For consistency, handle unmanaged mappings the same way.
5791 origpte = pte_load_clear(pte);
5792 KASSERT((origpte & PG_FRAME) == opa,
5793 ("pmap_enter: unexpected pa update for %#lx", va));
5794 if ((origpte & PG_MANAGED) != 0) {
5795 om = PHYS_TO_VM_PAGE(opa);
5798 * The pmap lock is sufficient to synchronize with
5799 * concurrent calls to pmap_page_test_mappings() and
5800 * pmap_ts_referenced().
5802 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5804 if ((origpte & PG_A) != 0)
5805 vm_page_aflag_set(om, PGA_REFERENCED);
5806 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5807 pv = pmap_pvh_remove(&om->md, pmap, va);
5809 ("pmap_enter: no PV entry for %#lx", va));
5810 if ((newpte & PG_MANAGED) == 0)
5811 free_pv_entry(pmap, pv);
5812 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5813 TAILQ_EMPTY(&om->md.pv_list) &&
5814 ((om->flags & PG_FICTITIOUS) != 0 ||
5815 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5816 vm_page_aflag_clear(om, PGA_WRITEABLE);
5818 if ((origpte & PG_A) != 0)
5819 pmap_invalidate_page(pmap, va);
5823 * Increment the counters.
5825 if ((newpte & PG_W) != 0)
5826 pmap->pm_stats.wired_count++;
5827 pmap_resident_count_inc(pmap, 1);
5831 * Enter on the PV list if part of our managed memory.
5833 if ((newpte & PG_MANAGED) != 0) {
5835 pv = get_pv_entry(pmap, &lock);
5838 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5839 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5841 if ((newpte & PG_RW) != 0)
5842 vm_page_aflag_set(m, PGA_WRITEABLE);
5848 if ((origpte & PG_V) != 0) {
5850 origpte = pte_load_store(pte, newpte);
5851 KASSERT((origpte & PG_FRAME) == pa,
5852 ("pmap_enter: unexpected pa update for %#lx", va));
5853 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5855 if ((origpte & PG_MANAGED) != 0)
5859 * Although the PTE may still have PG_RW set, TLB
5860 * invalidation may nonetheless be required because
5861 * the PTE no longer has PG_M set.
5863 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5865 * This PTE change does not require TLB invalidation.
5869 if ((origpte & PG_A) != 0)
5870 pmap_invalidate_page(pmap, va);
5872 pte_store(pte, newpte);
5876 #if VM_NRESERVLEVEL > 0
5878 * If both the page table page and the reservation are fully
5879 * populated, then attempt promotion.
5881 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
5882 pmap_ps_enabled(pmap) &&
5883 (m->flags & PG_FICTITIOUS) == 0 &&
5884 vm_reserv_level_iffullpop(m) == 0)
5885 pmap_promote_pde(pmap, pde, va, &lock);
5897 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5898 * if successful. Returns false if (1) a page table page cannot be allocated
5899 * without sleeping, (2) a mapping already exists at the specified virtual
5900 * address, or (3) a PV entry cannot be allocated without reclaiming another
5904 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5905 struct rwlock **lockp)
5910 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5911 PG_V = pmap_valid_bit(pmap);
5912 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5914 if ((m->oflags & VPO_UNMANAGED) == 0)
5915 newpde |= PG_MANAGED;
5916 if ((prot & VM_PROT_EXECUTE) == 0)
5918 if (va < VM_MAXUSER_ADDRESS)
5920 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5921 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5926 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5927 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5928 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5929 * a mapping already exists at the specified virtual address. Returns
5930 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5931 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5932 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5934 * The parameter "m" is only used when creating a managed, writeable mapping.
5937 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5938 vm_page_t m, struct rwlock **lockp)
5940 struct spglist free;
5941 pd_entry_t oldpde, *pde;
5942 pt_entry_t PG_G, PG_RW, PG_V;
5945 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
5946 ("pmap_enter_pde: cannot create wired user mapping"));
5947 PG_G = pmap_global_bit(pmap);
5948 PG_RW = pmap_rw_bit(pmap);
5949 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5950 ("pmap_enter_pde: newpde is missing PG_M"));
5951 PG_V = pmap_valid_bit(pmap);
5952 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5954 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5955 NULL : lockp)) == NULL) {
5956 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5957 " in pmap %p", va, pmap);
5958 return (KERN_RESOURCE_SHORTAGE);
5962 * If pkru is not same for the whole pde range, return failure
5963 * and let vm_fault() cope. Check after pde allocation, since
5966 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5968 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5969 pmap_invalidate_page(pmap, va);
5970 vm_page_free_pages_toq(&free, true);
5972 return (KERN_FAILURE);
5974 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5975 newpde &= ~X86_PG_PKU_MASK;
5976 newpde |= pmap_pkru_get(pmap, va);
5979 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5980 pde = &pde[pmap_pde_index(va)];
5982 if ((oldpde & PG_V) != 0) {
5983 KASSERT(pdpg->ref_count > 1,
5984 ("pmap_enter_pde: pdpg's reference count is too low"));
5985 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5987 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5988 " in pmap %p", va, pmap);
5989 return (KERN_FAILURE);
5991 /* Break the existing mapping(s). */
5993 if ((oldpde & PG_PS) != 0) {
5995 * The reference to the PD page that was acquired by
5996 * pmap_allocpde() ensures that it won't be freed.
5997 * However, if the PDE resulted from a promotion, then
5998 * a reserved PT page could be freed.
6000 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6001 if ((oldpde & PG_G) == 0)
6002 pmap_invalidate_pde_page(pmap, va, oldpde);
6004 pmap_delayed_invl_start();
6005 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6007 pmap_invalidate_all(pmap);
6008 pmap_delayed_invl_finish();
6010 vm_page_free_pages_toq(&free, true);
6011 if (va >= VM_MAXUSER_ADDRESS) {
6013 * Both pmap_remove_pde() and pmap_remove_ptes() will
6014 * leave the kernel page table page zero filled.
6016 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6017 if (pmap_insert_pt_page(pmap, mt, false))
6018 panic("pmap_enter_pde: trie insert failed");
6020 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6023 if ((newpde & PG_MANAGED) != 0) {
6025 * Abort this mapping if its PV entry could not be created.
6027 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6029 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6031 * Although "va" is not mapped, paging-
6032 * structure caches could nonetheless have
6033 * entries that refer to the freed page table
6034 * pages. Invalidate those entries.
6036 pmap_invalidate_page(pmap, va);
6037 vm_page_free_pages_toq(&free, true);
6039 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6040 " in pmap %p", va, pmap);
6041 return (KERN_RESOURCE_SHORTAGE);
6043 if ((newpde & PG_RW) != 0) {
6044 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6045 vm_page_aflag_set(mt, PGA_WRITEABLE);
6050 * Increment counters.
6052 if ((newpde & PG_W) != 0)
6053 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6054 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6057 * Map the superpage. (This is not a promoted mapping; there will not
6058 * be any lingering 4KB page mappings in the TLB.)
6060 pde_store(pde, newpde);
6062 atomic_add_long(&pmap_pde_mappings, 1);
6063 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
6064 " in pmap %p", va, pmap);
6065 return (KERN_SUCCESS);
6069 * Maps a sequence of resident pages belonging to the same object.
6070 * The sequence begins with the given page m_start. This page is
6071 * mapped at the given virtual address start. Each subsequent page is
6072 * mapped at a virtual address that is offset from start by the same
6073 * amount as the page is offset from m_start within the object. The
6074 * last page in the sequence is the page with the largest offset from
6075 * m_start that can be mapped at a virtual address less than the given
6076 * virtual address end. Not every virtual page between start and end
6077 * is mapped; only those for which a resident page exists with the
6078 * corresponding offset from m_start are mapped.
6081 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6082 vm_page_t m_start, vm_prot_t prot)
6084 struct rwlock *lock;
6087 vm_pindex_t diff, psize;
6089 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6091 psize = atop(end - start);
6096 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6097 va = start + ptoa(diff);
6098 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6099 m->psind == 1 && pmap_ps_enabled(pmap) &&
6100 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6101 m = &m[NBPDR / PAGE_SIZE - 1];
6103 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6105 m = TAILQ_NEXT(m, listq);
6113 * this code makes some *MAJOR* assumptions:
6114 * 1. Current pmap & pmap exists.
6117 * 4. No page table pages.
6118 * but is *MUCH* faster than pmap_enter...
6122 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6124 struct rwlock *lock;
6128 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6135 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6136 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6138 struct spglist free;
6139 pt_entry_t newpte, *pte, PG_V;
6141 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6142 (m->oflags & VPO_UNMANAGED) != 0,
6143 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6144 PG_V = pmap_valid_bit(pmap);
6145 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6148 * In the case that a page table page is not
6149 * resident, we are creating it here.
6151 if (va < VM_MAXUSER_ADDRESS) {
6152 vm_pindex_t ptepindex;
6156 * Calculate pagetable page index
6158 ptepindex = pmap_pde_pindex(va);
6159 if (mpte && (mpte->pindex == ptepindex)) {
6163 * Get the page directory entry
6165 ptepa = pmap_pde(pmap, va);
6168 * If the page table page is mapped, we just increment
6169 * the hold count, and activate it. Otherwise, we
6170 * attempt to allocate a page table page. If this
6171 * attempt fails, we don't retry. Instead, we give up.
6173 if (ptepa && (*ptepa & PG_V) != 0) {
6176 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6180 * Pass NULL instead of the PV list lock
6181 * pointer, because we don't intend to sleep.
6183 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6188 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6189 pte = &pte[pmap_pte_index(va)];
6203 * Enter on the PV list if part of our managed memory.
6205 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6206 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6209 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6211 * Although "va" is not mapped, paging-
6212 * structure caches could nonetheless have
6213 * entries that refer to the freed page table
6214 * pages. Invalidate those entries.
6216 pmap_invalidate_page(pmap, va);
6217 vm_page_free_pages_toq(&free, true);
6225 * Increment counters
6227 pmap_resident_count_inc(pmap, 1);
6229 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6230 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6231 if ((m->oflags & VPO_UNMANAGED) == 0)
6232 newpte |= PG_MANAGED;
6233 if ((prot & VM_PROT_EXECUTE) == 0)
6235 if (va < VM_MAXUSER_ADDRESS)
6236 newpte |= PG_U | pmap_pkru_get(pmap, va);
6237 pte_store(pte, newpte);
6242 * Make a temporary mapping for a physical address. This is only intended
6243 * to be used for panic dumps.
6246 pmap_kenter_temporary(vm_paddr_t pa, int i)
6250 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6251 pmap_kenter(va, pa);
6253 return ((void *)crashdumpmap);
6257 * This code maps large physical mmap regions into the
6258 * processor address space. Note that some shortcuts
6259 * are taken, but the code works.
6262 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6263 vm_pindex_t pindex, vm_size_t size)
6266 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6267 vm_paddr_t pa, ptepa;
6271 PG_A = pmap_accessed_bit(pmap);
6272 PG_M = pmap_modified_bit(pmap);
6273 PG_V = pmap_valid_bit(pmap);
6274 PG_RW = pmap_rw_bit(pmap);
6276 VM_OBJECT_ASSERT_WLOCKED(object);
6277 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6278 ("pmap_object_init_pt: non-device object"));
6279 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6280 if (!pmap_ps_enabled(pmap))
6282 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6284 p = vm_page_lookup(object, pindex);
6285 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6286 ("pmap_object_init_pt: invalid page %p", p));
6287 pat_mode = p->md.pat_mode;
6290 * Abort the mapping if the first page is not physically
6291 * aligned to a 2MB page boundary.
6293 ptepa = VM_PAGE_TO_PHYS(p);
6294 if (ptepa & (NBPDR - 1))
6298 * Skip the first page. Abort the mapping if the rest of
6299 * the pages are not physically contiguous or have differing
6300 * memory attributes.
6302 p = TAILQ_NEXT(p, listq);
6303 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6305 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6306 ("pmap_object_init_pt: invalid page %p", p));
6307 if (pa != VM_PAGE_TO_PHYS(p) ||
6308 pat_mode != p->md.pat_mode)
6310 p = TAILQ_NEXT(p, listq);
6314 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6315 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6316 * will not affect the termination of this loop.
6319 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6320 pa < ptepa + size; pa += NBPDR) {
6321 pdpg = pmap_allocpde(pmap, addr, NULL);
6324 * The creation of mappings below is only an
6325 * optimization. If a page directory page
6326 * cannot be allocated without blocking,
6327 * continue on to the next mapping rather than
6333 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6334 pde = &pde[pmap_pde_index(addr)];
6335 if ((*pde & PG_V) == 0) {
6336 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6337 PG_U | PG_RW | PG_V);
6338 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6339 atomic_add_long(&pmap_pde_mappings, 1);
6341 /* Continue on if the PDE is already valid. */
6343 KASSERT(pdpg->ref_count > 0,
6344 ("pmap_object_init_pt: missing reference "
6345 "to page directory page, va: 0x%lx", addr));
6354 * Clear the wired attribute from the mappings for the specified range of
6355 * addresses in the given pmap. Every valid mapping within that range
6356 * must have the wired attribute set. In contrast, invalid mappings
6357 * cannot have the wired attribute set, so they are ignored.
6359 * The wired attribute of the page table entry is not a hardware
6360 * feature, so there is no need to invalidate any TLB entries.
6361 * Since pmap_demote_pde() for the wired entry must never fail,
6362 * pmap_delayed_invl_start()/finish() calls around the
6363 * function are not needed.
6366 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6368 vm_offset_t va_next;
6369 pml4_entry_t *pml4e;
6372 pt_entry_t *pte, PG_V;
6374 PG_V = pmap_valid_bit(pmap);
6376 for (; sva < eva; sva = va_next) {
6377 pml4e = pmap_pml4e(pmap, sva);
6378 if ((*pml4e & PG_V) == 0) {
6379 va_next = (sva + NBPML4) & ~PML4MASK;
6384 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6385 if ((*pdpe & PG_V) == 0) {
6386 va_next = (sva + NBPDP) & ~PDPMASK;
6391 va_next = (sva + NBPDR) & ~PDRMASK;
6394 pde = pmap_pdpe_to_pde(pdpe, sva);
6395 if ((*pde & PG_V) == 0)
6397 if ((*pde & PG_PS) != 0) {
6398 if ((*pde & PG_W) == 0)
6399 panic("pmap_unwire: pde %#jx is missing PG_W",
6403 * Are we unwiring the entire large page? If not,
6404 * demote the mapping and fall through.
6406 if (sva + NBPDR == va_next && eva >= va_next) {
6407 atomic_clear_long(pde, PG_W);
6408 pmap->pm_stats.wired_count -= NBPDR /
6411 } else if (!pmap_demote_pde(pmap, pde, sva))
6412 panic("pmap_unwire: demotion failed");
6416 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6418 if ((*pte & PG_V) == 0)
6420 if ((*pte & PG_W) == 0)
6421 panic("pmap_unwire: pte %#jx is missing PG_W",
6425 * PG_W must be cleared atomically. Although the pmap
6426 * lock synchronizes access to PG_W, another processor
6427 * could be setting PG_M and/or PG_A concurrently.
6429 atomic_clear_long(pte, PG_W);
6430 pmap->pm_stats.wired_count--;
6437 * Copy the range specified by src_addr/len
6438 * from the source map to the range dst_addr/len
6439 * in the destination map.
6441 * This routine is only advisory and need not do anything.
6444 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6445 vm_offset_t src_addr)
6447 struct rwlock *lock;
6448 struct spglist free;
6449 pml4_entry_t *pml4e;
6451 pd_entry_t *pde, srcptepaddr;
6452 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6453 vm_offset_t addr, end_addr, va_next;
6454 vm_page_t dst_pdpg, dstmpte, srcmpte;
6456 if (dst_addr != src_addr)
6459 if (dst_pmap->pm_type != src_pmap->pm_type)
6463 * EPT page table entries that require emulation of A/D bits are
6464 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6465 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6466 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6467 * implementations flag an EPT misconfiguration for exec-only
6468 * mappings we skip this function entirely for emulated pmaps.
6470 if (pmap_emulate_ad_bits(dst_pmap))
6473 end_addr = src_addr + len;
6475 if (dst_pmap < src_pmap) {
6476 PMAP_LOCK(dst_pmap);
6477 PMAP_LOCK(src_pmap);
6479 PMAP_LOCK(src_pmap);
6480 PMAP_LOCK(dst_pmap);
6483 PG_A = pmap_accessed_bit(dst_pmap);
6484 PG_M = pmap_modified_bit(dst_pmap);
6485 PG_V = pmap_valid_bit(dst_pmap);
6487 for (addr = src_addr; addr < end_addr; addr = va_next) {
6488 KASSERT(addr < UPT_MIN_ADDRESS,
6489 ("pmap_copy: invalid to pmap_copy page tables"));
6491 pml4e = pmap_pml4e(src_pmap, addr);
6492 if ((*pml4e & PG_V) == 0) {
6493 va_next = (addr + NBPML4) & ~PML4MASK;
6499 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6500 if ((*pdpe & PG_V) == 0) {
6501 va_next = (addr + NBPDP) & ~PDPMASK;
6507 va_next = (addr + NBPDR) & ~PDRMASK;
6511 pde = pmap_pdpe_to_pde(pdpe, addr);
6513 if (srcptepaddr == 0)
6516 if (srcptepaddr & PG_PS) {
6517 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6519 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6520 if (dst_pdpg == NULL)
6522 pde = (pd_entry_t *)
6523 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6524 pde = &pde[pmap_pde_index(addr)];
6525 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6526 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6527 PMAP_ENTER_NORECLAIM, &lock))) {
6528 *pde = srcptepaddr & ~PG_W;
6529 pmap_resident_count_inc(dst_pmap, NBPDR /
6531 atomic_add_long(&pmap_pde_mappings, 1);
6533 dst_pdpg->ref_count--;
6537 srcptepaddr &= PG_FRAME;
6538 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6539 KASSERT(srcmpte->ref_count > 0,
6540 ("pmap_copy: source page table page is unused"));
6542 if (va_next > end_addr)
6545 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6546 src_pte = &src_pte[pmap_pte_index(addr)];
6548 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6552 * We only virtual copy managed pages.
6554 if ((ptetemp & PG_MANAGED) == 0)
6557 if (dstmpte != NULL) {
6558 KASSERT(dstmpte->pindex ==
6559 pmap_pde_pindex(addr),
6560 ("dstmpte pindex/addr mismatch"));
6561 dstmpte->ref_count++;
6562 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6565 dst_pte = (pt_entry_t *)
6566 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6567 dst_pte = &dst_pte[pmap_pte_index(addr)];
6568 if (*dst_pte == 0 &&
6569 pmap_try_insert_pv_entry(dst_pmap, addr,
6570 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6572 * Clear the wired, modified, and accessed
6573 * (referenced) bits during the copy.
6575 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6576 pmap_resident_count_inc(dst_pmap, 1);
6579 if (pmap_unwire_ptp(dst_pmap, addr, dstmpte,
6582 * Although "addr" is not mapped,
6583 * paging-structure caches could
6584 * nonetheless have entries that refer
6585 * to the freed page table pages.
6586 * Invalidate those entries.
6588 pmap_invalidate_page(dst_pmap, addr);
6589 vm_page_free_pages_toq(&free, true);
6593 /* Have we copied all of the valid mappings? */
6594 if (dstmpte->ref_count >= srcmpte->ref_count)
6601 PMAP_UNLOCK(src_pmap);
6602 PMAP_UNLOCK(dst_pmap);
6606 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6610 if (dst_pmap->pm_type != src_pmap->pm_type ||
6611 dst_pmap->pm_type != PT_X86 ||
6612 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6615 if (dst_pmap < src_pmap) {
6616 PMAP_LOCK(dst_pmap);
6617 PMAP_LOCK(src_pmap);
6619 PMAP_LOCK(src_pmap);
6620 PMAP_LOCK(dst_pmap);
6622 error = pmap_pkru_copy(dst_pmap, src_pmap);
6623 /* Clean up partial copy on failure due to no memory. */
6624 if (error == ENOMEM)
6625 pmap_pkru_deassign_all(dst_pmap);
6626 PMAP_UNLOCK(src_pmap);
6627 PMAP_UNLOCK(dst_pmap);
6628 if (error != ENOMEM)
6636 * Zero the specified hardware page.
6639 pmap_zero_page(vm_page_t m)
6641 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6643 pagezero((void *)va);
6647 * Zero an an area within a single hardware page. off and size must not
6648 * cover an area beyond a single hardware page.
6651 pmap_zero_page_area(vm_page_t m, int off, int size)
6653 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6655 if (off == 0 && size == PAGE_SIZE)
6656 pagezero((void *)va);
6658 bzero((char *)va + off, size);
6662 * Copy 1 specified hardware page to another.
6665 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6667 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6668 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6670 pagecopy((void *)src, (void *)dst);
6673 int unmapped_buf_allowed = 1;
6676 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6677 vm_offset_t b_offset, int xfersize)
6681 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6685 while (xfersize > 0) {
6686 a_pg_offset = a_offset & PAGE_MASK;
6687 pages[0] = ma[a_offset >> PAGE_SHIFT];
6688 b_pg_offset = b_offset & PAGE_MASK;
6689 pages[1] = mb[b_offset >> PAGE_SHIFT];
6690 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6691 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6692 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6693 a_cp = (char *)vaddr[0] + a_pg_offset;
6694 b_cp = (char *)vaddr[1] + b_pg_offset;
6695 bcopy(a_cp, b_cp, cnt);
6696 if (__predict_false(mapped))
6697 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6705 * Returns true if the pmap's pv is one of the first
6706 * 16 pvs linked to from this page. This count may
6707 * be changed upwards or downwards in the future; it
6708 * is only necessary that true be returned for a small
6709 * subset of pmaps for proper page aging.
6712 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6714 struct md_page *pvh;
6715 struct rwlock *lock;
6720 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6721 ("pmap_page_exists_quick: page %p is not managed", m));
6723 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6725 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6726 if (PV_PMAP(pv) == pmap) {
6734 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6735 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6736 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6737 if (PV_PMAP(pv) == pmap) {
6751 * pmap_page_wired_mappings:
6753 * Return the number of managed mappings to the given physical page
6757 pmap_page_wired_mappings(vm_page_t m)
6759 struct rwlock *lock;
6760 struct md_page *pvh;
6764 int count, md_gen, pvh_gen;
6766 if ((m->oflags & VPO_UNMANAGED) != 0)
6768 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6772 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6774 if (!PMAP_TRYLOCK(pmap)) {
6775 md_gen = m->md.pv_gen;
6779 if (md_gen != m->md.pv_gen) {
6784 pte = pmap_pte(pmap, pv->pv_va);
6785 if ((*pte & PG_W) != 0)
6789 if ((m->flags & PG_FICTITIOUS) == 0) {
6790 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6791 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6793 if (!PMAP_TRYLOCK(pmap)) {
6794 md_gen = m->md.pv_gen;
6795 pvh_gen = pvh->pv_gen;
6799 if (md_gen != m->md.pv_gen ||
6800 pvh_gen != pvh->pv_gen) {
6805 pte = pmap_pde(pmap, pv->pv_va);
6806 if ((*pte & PG_W) != 0)
6816 * Returns TRUE if the given page is mapped individually or as part of
6817 * a 2mpage. Otherwise, returns FALSE.
6820 pmap_page_is_mapped(vm_page_t m)
6822 struct rwlock *lock;
6825 if ((m->oflags & VPO_UNMANAGED) != 0)
6827 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6829 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6830 ((m->flags & PG_FICTITIOUS) == 0 &&
6831 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6837 * Destroy all managed, non-wired mappings in the given user-space
6838 * pmap. This pmap cannot be active on any processor besides the
6841 * This function cannot be applied to the kernel pmap. Moreover, it
6842 * is not intended for general use. It is only to be used during
6843 * process termination. Consequently, it can be implemented in ways
6844 * that make it faster than pmap_remove(). First, it can more quickly
6845 * destroy mappings by iterating over the pmap's collection of PV
6846 * entries, rather than searching the page table. Second, it doesn't
6847 * have to test and clear the page table entries atomically, because
6848 * no processor is currently accessing the user address space. In
6849 * particular, a page table entry's dirty bit won't change state once
6850 * this function starts.
6852 * Although this function destroys all of the pmap's managed,
6853 * non-wired mappings, it can delay and batch the invalidation of TLB
6854 * entries without calling pmap_delayed_invl_start() and
6855 * pmap_delayed_invl_finish(). Because the pmap is not active on
6856 * any other processor, none of these TLB entries will ever be used
6857 * before their eventual invalidation. Consequently, there is no need
6858 * for either pmap_remove_all() or pmap_remove_write() to wait for
6859 * that eventual TLB invalidation.
6862 pmap_remove_pages(pmap_t pmap)
6865 pt_entry_t *pte, tpte;
6866 pt_entry_t PG_M, PG_RW, PG_V;
6867 struct spglist free;
6868 vm_page_t m, mpte, mt;
6870 struct md_page *pvh;
6871 struct pv_chunk *pc, *npc;
6872 struct rwlock *lock;
6874 uint64_t inuse, bitmask;
6875 int allfree, field, freed, idx;
6876 boolean_t superpage;
6880 * Assert that the given pmap is only active on the current
6881 * CPU. Unfortunately, we cannot block another CPU from
6882 * activating the pmap while this function is executing.
6884 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6887 cpuset_t other_cpus;
6889 other_cpus = all_cpus;
6891 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6892 CPU_AND(&other_cpus, &pmap->pm_active);
6894 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6899 PG_M = pmap_modified_bit(pmap);
6900 PG_V = pmap_valid_bit(pmap);
6901 PG_RW = pmap_rw_bit(pmap);
6905 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6908 for (field = 0; field < _NPCM; field++) {
6909 inuse = ~pc->pc_map[field] & pc_freemask[field];
6910 while (inuse != 0) {
6912 bitmask = 1UL << bit;
6913 idx = field * 64 + bit;
6914 pv = &pc->pc_pventry[idx];
6917 pte = pmap_pdpe(pmap, pv->pv_va);
6919 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6921 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6924 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6926 pte = &pte[pmap_pte_index(pv->pv_va)];
6930 * Keep track whether 'tpte' is a
6931 * superpage explicitly instead of
6932 * relying on PG_PS being set.
6934 * This is because PG_PS is numerically
6935 * identical to PG_PTE_PAT and thus a
6936 * regular page could be mistaken for
6942 if ((tpte & PG_V) == 0) {
6943 panic("bad pte va %lx pte %lx",
6948 * We cannot remove wired pages from a process' mapping at this time
6956 pa = tpte & PG_PS_FRAME;
6958 pa = tpte & PG_FRAME;
6960 m = PHYS_TO_VM_PAGE(pa);
6961 KASSERT(m->phys_addr == pa,
6962 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6963 m, (uintmax_t)m->phys_addr,
6966 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6967 m < &vm_page_array[vm_page_array_size],
6968 ("pmap_remove_pages: bad tpte %#jx",
6974 * Update the vm_page_t clean/reference bits.
6976 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6978 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6984 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6987 pc->pc_map[field] |= bitmask;
6989 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6990 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6991 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6993 if (TAILQ_EMPTY(&pvh->pv_list)) {
6994 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6995 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6996 TAILQ_EMPTY(&mt->md.pv_list))
6997 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6999 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7001 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7002 ("pmap_remove_pages: pte page not promoted"));
7003 pmap_resident_count_dec(pmap, 1);
7004 KASSERT(mpte->ref_count == NPTEPG,
7005 ("pmap_remove_pages: pte page reference count error"));
7006 mpte->ref_count = 0;
7007 pmap_add_delayed_free_list(mpte, &free, FALSE);
7010 pmap_resident_count_dec(pmap, 1);
7011 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7013 if ((m->aflags & PGA_WRITEABLE) != 0 &&
7014 TAILQ_EMPTY(&m->md.pv_list) &&
7015 (m->flags & PG_FICTITIOUS) == 0) {
7016 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7017 if (TAILQ_EMPTY(&pvh->pv_list))
7018 vm_page_aflag_clear(m, PGA_WRITEABLE);
7021 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7025 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7026 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7027 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7029 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7035 pmap_invalidate_all(pmap);
7036 pmap_pkru_deassign_all(pmap);
7038 vm_page_free_pages_toq(&free, true);
7042 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7044 struct rwlock *lock;
7046 struct md_page *pvh;
7047 pt_entry_t *pte, mask;
7048 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7050 int md_gen, pvh_gen;
7054 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7057 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7059 if (!PMAP_TRYLOCK(pmap)) {
7060 md_gen = m->md.pv_gen;
7064 if (md_gen != m->md.pv_gen) {
7069 pte = pmap_pte(pmap, pv->pv_va);
7072 PG_M = pmap_modified_bit(pmap);
7073 PG_RW = pmap_rw_bit(pmap);
7074 mask |= PG_RW | PG_M;
7077 PG_A = pmap_accessed_bit(pmap);
7078 PG_V = pmap_valid_bit(pmap);
7079 mask |= PG_V | PG_A;
7081 rv = (*pte & mask) == mask;
7086 if ((m->flags & PG_FICTITIOUS) == 0) {
7087 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7088 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7090 if (!PMAP_TRYLOCK(pmap)) {
7091 md_gen = m->md.pv_gen;
7092 pvh_gen = pvh->pv_gen;
7096 if (md_gen != m->md.pv_gen ||
7097 pvh_gen != pvh->pv_gen) {
7102 pte = pmap_pde(pmap, pv->pv_va);
7105 PG_M = pmap_modified_bit(pmap);
7106 PG_RW = pmap_rw_bit(pmap);
7107 mask |= PG_RW | PG_M;
7110 PG_A = pmap_accessed_bit(pmap);
7111 PG_V = pmap_valid_bit(pmap);
7112 mask |= PG_V | PG_A;
7114 rv = (*pte & mask) == mask;
7128 * Return whether or not the specified physical page was modified
7129 * in any physical maps.
7132 pmap_is_modified(vm_page_t m)
7135 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7136 ("pmap_is_modified: page %p is not managed", m));
7139 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7140 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
7141 * is clear, no PTEs can have PG_M set.
7143 VM_OBJECT_ASSERT_WLOCKED(m->object);
7144 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7146 return (pmap_page_test_mappings(m, FALSE, TRUE));
7150 * pmap_is_prefaultable:
7152 * Return whether or not the specified virtual address is eligible
7156 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7159 pt_entry_t *pte, PG_V;
7162 PG_V = pmap_valid_bit(pmap);
7165 pde = pmap_pde(pmap, addr);
7166 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7167 pte = pmap_pde_to_pte(pde, addr);
7168 rv = (*pte & PG_V) == 0;
7175 * pmap_is_referenced:
7177 * Return whether or not the specified physical page was referenced
7178 * in any physical maps.
7181 pmap_is_referenced(vm_page_t m)
7184 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7185 ("pmap_is_referenced: page %p is not managed", m));
7186 return (pmap_page_test_mappings(m, TRUE, FALSE));
7190 * Clear the write and modified bits in each of the given page's mappings.
7193 pmap_remove_write(vm_page_t m)
7195 struct md_page *pvh;
7197 struct rwlock *lock;
7198 pv_entry_t next_pv, pv;
7200 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7202 int pvh_gen, md_gen;
7204 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7205 ("pmap_remove_write: page %p is not managed", m));
7208 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7209 * set by another thread while the object is locked. Thus,
7210 * if PGA_WRITEABLE is clear, no page table entries need updating.
7212 VM_OBJECT_ASSERT_WLOCKED(m->object);
7213 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7215 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7216 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7217 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7220 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7222 if (!PMAP_TRYLOCK(pmap)) {
7223 pvh_gen = pvh->pv_gen;
7227 if (pvh_gen != pvh->pv_gen) {
7233 PG_RW = pmap_rw_bit(pmap);
7235 pde = pmap_pde(pmap, va);
7236 if ((*pde & PG_RW) != 0)
7237 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7238 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7239 ("inconsistent pv lock %p %p for page %p",
7240 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7243 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7245 if (!PMAP_TRYLOCK(pmap)) {
7246 pvh_gen = pvh->pv_gen;
7247 md_gen = m->md.pv_gen;
7251 if (pvh_gen != pvh->pv_gen ||
7252 md_gen != m->md.pv_gen) {
7258 PG_M = pmap_modified_bit(pmap);
7259 PG_RW = pmap_rw_bit(pmap);
7260 pde = pmap_pde(pmap, pv->pv_va);
7261 KASSERT((*pde & PG_PS) == 0,
7262 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7264 pte = pmap_pde_to_pte(pde, pv->pv_va);
7267 if (oldpte & PG_RW) {
7268 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7271 if ((oldpte & PG_M) != 0)
7273 pmap_invalidate_page(pmap, pv->pv_va);
7278 vm_page_aflag_clear(m, PGA_WRITEABLE);
7279 pmap_delayed_invl_wait(m);
7282 static __inline boolean_t
7283 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7286 if (!pmap_emulate_ad_bits(pmap))
7289 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7292 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7293 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7294 * if the EPT_PG_WRITE bit is set.
7296 if ((pte & EPT_PG_WRITE) != 0)
7300 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7302 if ((pte & EPT_PG_EXECUTE) == 0 ||
7303 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7310 * pmap_ts_referenced:
7312 * Return a count of reference bits for a page, clearing those bits.
7313 * It is not necessary for every reference bit to be cleared, but it
7314 * is necessary that 0 only be returned when there are truly no
7315 * reference bits set.
7317 * As an optimization, update the page's dirty field if a modified bit is
7318 * found while counting reference bits. This opportunistic update can be
7319 * performed at low cost and can eliminate the need for some future calls
7320 * to pmap_is_modified(). However, since this function stops after
7321 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7322 * dirty pages. Those dirty pages will only be detected by a future call
7323 * to pmap_is_modified().
7325 * A DI block is not needed within this function, because
7326 * invalidations are performed before the PV list lock is
7330 pmap_ts_referenced(vm_page_t m)
7332 struct md_page *pvh;
7335 struct rwlock *lock;
7336 pd_entry_t oldpde, *pde;
7337 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7340 int cleared, md_gen, not_cleared, pvh_gen;
7341 struct spglist free;
7344 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7345 ("pmap_ts_referenced: page %p is not managed", m));
7348 pa = VM_PAGE_TO_PHYS(m);
7349 lock = PHYS_TO_PV_LIST_LOCK(pa);
7350 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7354 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7355 goto small_mappings;
7361 if (!PMAP_TRYLOCK(pmap)) {
7362 pvh_gen = pvh->pv_gen;
7366 if (pvh_gen != pvh->pv_gen) {
7371 PG_A = pmap_accessed_bit(pmap);
7372 PG_M = pmap_modified_bit(pmap);
7373 PG_RW = pmap_rw_bit(pmap);
7375 pde = pmap_pde(pmap, pv->pv_va);
7377 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7379 * Although "oldpde" is mapping a 2MB page, because
7380 * this function is called at a 4KB page granularity,
7381 * we only update the 4KB page under test.
7385 if ((oldpde & PG_A) != 0) {
7387 * Since this reference bit is shared by 512 4KB
7388 * pages, it should not be cleared every time it is
7389 * tested. Apply a simple "hash" function on the
7390 * physical page number, the virtual superpage number,
7391 * and the pmap address to select one 4KB page out of
7392 * the 512 on which testing the reference bit will
7393 * result in clearing that reference bit. This
7394 * function is designed to avoid the selection of the
7395 * same 4KB page for every 2MB page mapping.
7397 * On demotion, a mapping that hasn't been referenced
7398 * is simply destroyed. To avoid the possibility of a
7399 * subsequent page fault on a demoted wired mapping,
7400 * always leave its reference bit set. Moreover,
7401 * since the superpage is wired, the current state of
7402 * its reference bit won't affect page replacement.
7404 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7405 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7406 (oldpde & PG_W) == 0) {
7407 if (safe_to_clear_referenced(pmap, oldpde)) {
7408 atomic_clear_long(pde, PG_A);
7409 pmap_invalidate_page(pmap, pv->pv_va);
7411 } else if (pmap_demote_pde_locked(pmap, pde,
7412 pv->pv_va, &lock)) {
7414 * Remove the mapping to a single page
7415 * so that a subsequent access may
7416 * repromote. Since the underlying
7417 * page table page is fully populated,
7418 * this removal never frees a page
7422 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7424 pte = pmap_pde_to_pte(pde, va);
7425 pmap_remove_pte(pmap, pte, va, *pde,
7427 pmap_invalidate_page(pmap, va);
7433 * The superpage mapping was removed
7434 * entirely and therefore 'pv' is no
7442 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7443 ("inconsistent pv lock %p %p for page %p",
7444 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7449 /* Rotate the PV list if it has more than one entry. */
7450 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7451 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7452 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7455 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7457 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7459 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7466 if (!PMAP_TRYLOCK(pmap)) {
7467 pvh_gen = pvh->pv_gen;
7468 md_gen = m->md.pv_gen;
7472 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7477 PG_A = pmap_accessed_bit(pmap);
7478 PG_M = pmap_modified_bit(pmap);
7479 PG_RW = pmap_rw_bit(pmap);
7480 pde = pmap_pde(pmap, pv->pv_va);
7481 KASSERT((*pde & PG_PS) == 0,
7482 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7484 pte = pmap_pde_to_pte(pde, pv->pv_va);
7485 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7487 if ((*pte & PG_A) != 0) {
7488 if (safe_to_clear_referenced(pmap, *pte)) {
7489 atomic_clear_long(pte, PG_A);
7490 pmap_invalidate_page(pmap, pv->pv_va);
7492 } else if ((*pte & PG_W) == 0) {
7494 * Wired pages cannot be paged out so
7495 * doing accessed bit emulation for
7496 * them is wasted effort. We do the
7497 * hard work for unwired pages only.
7499 pmap_remove_pte(pmap, pte, pv->pv_va,
7500 *pde, &free, &lock);
7501 pmap_invalidate_page(pmap, pv->pv_va);
7506 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7507 ("inconsistent pv lock %p %p for page %p",
7508 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7513 /* Rotate the PV list if it has more than one entry. */
7514 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7515 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7516 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7519 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7520 not_cleared < PMAP_TS_REFERENCED_MAX);
7523 vm_page_free_pages_toq(&free, true);
7524 return (cleared + not_cleared);
7528 * Apply the given advice to the specified range of addresses within the
7529 * given pmap. Depending on the advice, clear the referenced and/or
7530 * modified flags in each mapping and set the mapped page's dirty field.
7533 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7535 struct rwlock *lock;
7536 pml4_entry_t *pml4e;
7538 pd_entry_t oldpde, *pde;
7539 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7540 vm_offset_t va, va_next;
7544 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7548 * A/D bit emulation requires an alternate code path when clearing
7549 * the modified and accessed bits below. Since this function is
7550 * advisory in nature we skip it entirely for pmaps that require
7551 * A/D bit emulation.
7553 if (pmap_emulate_ad_bits(pmap))
7556 PG_A = pmap_accessed_bit(pmap);
7557 PG_G = pmap_global_bit(pmap);
7558 PG_M = pmap_modified_bit(pmap);
7559 PG_V = pmap_valid_bit(pmap);
7560 PG_RW = pmap_rw_bit(pmap);
7562 pmap_delayed_invl_start();
7564 for (; sva < eva; sva = va_next) {
7565 pml4e = pmap_pml4e(pmap, sva);
7566 if ((*pml4e & PG_V) == 0) {
7567 va_next = (sva + NBPML4) & ~PML4MASK;
7572 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7573 if ((*pdpe & PG_V) == 0) {
7574 va_next = (sva + NBPDP) & ~PDPMASK;
7579 va_next = (sva + NBPDR) & ~PDRMASK;
7582 pde = pmap_pdpe_to_pde(pdpe, sva);
7584 if ((oldpde & PG_V) == 0)
7586 else if ((oldpde & PG_PS) != 0) {
7587 if ((oldpde & PG_MANAGED) == 0)
7590 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7595 * The large page mapping was destroyed.
7601 * Unless the page mappings are wired, remove the
7602 * mapping to a single page so that a subsequent
7603 * access may repromote. Choosing the last page
7604 * within the address range [sva, min(va_next, eva))
7605 * generally results in more repromotions. Since the
7606 * underlying page table page is fully populated, this
7607 * removal never frees a page table page.
7609 if ((oldpde & PG_W) == 0) {
7615 ("pmap_advise: no address gap"));
7616 pte = pmap_pde_to_pte(pde, va);
7617 KASSERT((*pte & PG_V) != 0,
7618 ("pmap_advise: invalid PTE"));
7619 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7629 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7631 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7633 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7634 if (advice == MADV_DONTNEED) {
7636 * Future calls to pmap_is_modified()
7637 * can be avoided by making the page
7640 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7643 atomic_clear_long(pte, PG_M | PG_A);
7644 } else if ((*pte & PG_A) != 0)
7645 atomic_clear_long(pte, PG_A);
7649 if ((*pte & PG_G) != 0) {
7656 if (va != va_next) {
7657 pmap_invalidate_range(pmap, va, sva);
7662 pmap_invalidate_range(pmap, va, sva);
7665 pmap_invalidate_all(pmap);
7667 pmap_delayed_invl_finish();
7671 * Clear the modify bits on the specified physical page.
7674 pmap_clear_modify(vm_page_t m)
7676 struct md_page *pvh;
7678 pv_entry_t next_pv, pv;
7679 pd_entry_t oldpde, *pde;
7680 pt_entry_t *pte, PG_M, PG_RW;
7681 struct rwlock *lock;
7683 int md_gen, pvh_gen;
7685 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7686 ("pmap_clear_modify: page %p is not managed", m));
7687 VM_OBJECT_ASSERT_WLOCKED(m->object);
7688 KASSERT(!vm_page_xbusied(m),
7689 ("pmap_clear_modify: page %p is exclusive busied", m));
7692 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7693 * If the object containing the page is locked and the page is not
7694 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7696 if ((m->aflags & PGA_WRITEABLE) == 0)
7698 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7699 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7700 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7703 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7705 if (!PMAP_TRYLOCK(pmap)) {
7706 pvh_gen = pvh->pv_gen;
7710 if (pvh_gen != pvh->pv_gen) {
7715 PG_M = pmap_modified_bit(pmap);
7716 PG_RW = pmap_rw_bit(pmap);
7718 pde = pmap_pde(pmap, va);
7720 /* If oldpde has PG_RW set, then it also has PG_M set. */
7721 if ((oldpde & PG_RW) != 0 &&
7722 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
7723 (oldpde & PG_W) == 0) {
7725 * Write protect the mapping to a single page so that
7726 * a subsequent write access may repromote.
7728 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
7729 pte = pmap_pde_to_pte(pde, va);
7730 atomic_clear_long(pte, PG_M | PG_RW);
7732 pmap_invalidate_page(pmap, va);
7736 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7738 if (!PMAP_TRYLOCK(pmap)) {
7739 md_gen = m->md.pv_gen;
7740 pvh_gen = pvh->pv_gen;
7744 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7749 PG_M = pmap_modified_bit(pmap);
7750 PG_RW = pmap_rw_bit(pmap);
7751 pde = pmap_pde(pmap, pv->pv_va);
7752 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7753 " a 2mpage in page %p's pv list", m));
7754 pte = pmap_pde_to_pte(pde, pv->pv_va);
7755 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7756 atomic_clear_long(pte, PG_M);
7757 pmap_invalidate_page(pmap, pv->pv_va);
7765 * Miscellaneous support routines follow
7768 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7769 static __inline void
7770 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7775 * The cache mode bits are all in the low 32-bits of the
7776 * PTE, so we can just spin on updating the low 32-bits.
7779 opte = *(u_int *)pte;
7780 npte = opte & ~mask;
7782 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7785 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7786 static __inline void
7787 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7792 * The cache mode bits are all in the low 32-bits of the
7793 * PDE, so we can just spin on updating the low 32-bits.
7796 opde = *(u_int *)pde;
7797 npde = opde & ~mask;
7799 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7803 * Map a set of physical memory pages into the kernel virtual
7804 * address space. Return a pointer to where it is mapped. This
7805 * routine is intended to be used for mapping device memory,
7809 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
7811 struct pmap_preinit_mapping *ppim;
7812 vm_offset_t va, offset;
7816 offset = pa & PAGE_MASK;
7817 size = round_page(offset + size);
7818 pa = trunc_page(pa);
7820 if (!pmap_initialized) {
7822 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7823 ppim = pmap_preinit_mapping + i;
7824 if (ppim->va == 0) {
7828 ppim->va = virtual_avail;
7829 virtual_avail += size;
7835 panic("%s: too many preinit mappings", __func__);
7838 * If we have a preinit mapping, re-use it.
7840 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7841 ppim = pmap_preinit_mapping + i;
7842 if (ppim->pa == pa && ppim->sz == size &&
7843 (ppim->mode == mode ||
7844 (flags & MAPDEV_SETATTR) == 0))
7845 return ((void *)(ppim->va + offset));
7848 * If the specified range of physical addresses fits within
7849 * the direct map window, use the direct map.
7851 if (pa < dmaplimit && pa + size <= dmaplimit) {
7852 va = PHYS_TO_DMAP(pa);
7853 if ((flags & MAPDEV_SETATTR) != 0) {
7854 PMAP_LOCK(kernel_pmap);
7855 i = pmap_change_attr_locked(va, size, mode, flags);
7856 PMAP_UNLOCK(kernel_pmap);
7860 return ((void *)(va + offset));
7862 va = kva_alloc(size);
7864 panic("%s: Couldn't allocate KVA", __func__);
7866 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7867 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7868 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7869 if ((flags & MAPDEV_FLUSHCACHE) != 0)
7870 pmap_invalidate_cache_range(va, va + tmpsize);
7871 return ((void *)(va + offset));
7875 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7878 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
7883 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7886 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
7890 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7893 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
7898 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7901 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
7902 MAPDEV_FLUSHCACHE));
7906 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7908 struct pmap_preinit_mapping *ppim;
7912 /* If we gave a direct map region in pmap_mapdev, do nothing */
7913 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7915 offset = va & PAGE_MASK;
7916 size = round_page(offset + size);
7917 va = trunc_page(va);
7918 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7919 ppim = pmap_preinit_mapping + i;
7920 if (ppim->va == va && ppim->sz == size) {
7921 if (pmap_initialized)
7927 if (va + size == virtual_avail)
7932 if (pmap_initialized)
7937 * Tries to demote a 1GB page mapping.
7940 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7942 pdp_entry_t newpdpe, oldpdpe;
7943 pd_entry_t *firstpde, newpde, *pde;
7944 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7948 PG_A = pmap_accessed_bit(pmap);
7949 PG_M = pmap_modified_bit(pmap);
7950 PG_V = pmap_valid_bit(pmap);
7951 PG_RW = pmap_rw_bit(pmap);
7953 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7955 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7956 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7957 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7958 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7959 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7960 " in pmap %p", va, pmap);
7963 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7964 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7965 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7966 KASSERT((oldpdpe & PG_A) != 0,
7967 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7968 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7969 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7973 * Initialize the page directory page.
7975 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7981 * Demote the mapping.
7986 * Invalidate a stale recursive mapping of the page directory page.
7988 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7990 pmap_pdpe_demotions++;
7991 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7992 " in pmap %p", va, pmap);
7997 * Sets the memory attribute for the specified page.
8000 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8003 m->md.pat_mode = ma;
8006 * If "m" is a normal page, update its direct mapping. This update
8007 * can be relied upon to perform any cache operations that are
8008 * required for data coherence.
8010 if ((m->flags & PG_FICTITIOUS) == 0 &&
8011 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8013 panic("memory attribute change on the direct map failed");
8017 * Changes the specified virtual address range's memory type to that given by
8018 * the parameter "mode". The specified virtual address range must be
8019 * completely contained within either the direct map or the kernel map. If
8020 * the virtual address range is contained within the kernel map, then the
8021 * memory type for each of the corresponding ranges of the direct map is also
8022 * changed. (The corresponding ranges of the direct map are those ranges that
8023 * map the same physical pages as the specified virtual address range.) These
8024 * changes to the direct map are necessary because Intel describes the
8025 * behavior of their processors as "undefined" if two or more mappings to the
8026 * same physical page have different memory types.
8028 * Returns zero if the change completed successfully, and either EINVAL or
8029 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8030 * of the virtual address range was not mapped, and ENOMEM is returned if
8031 * there was insufficient memory available to complete the change. In the
8032 * latter case, the memory type may have been changed on some part of the
8033 * virtual address range or the direct map.
8036 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8040 PMAP_LOCK(kernel_pmap);
8041 error = pmap_change_attr_locked(va, size, mode, MAPDEV_FLUSHCACHE);
8042 PMAP_UNLOCK(kernel_pmap);
8047 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, int flags)
8049 vm_offset_t base, offset, tmpva;
8050 vm_paddr_t pa_start, pa_end, pa_end1;
8054 int cache_bits_pte, cache_bits_pde, error;
8057 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8058 base = trunc_page(va);
8059 offset = va & PAGE_MASK;
8060 size = round_page(offset + size);
8063 * Only supported on kernel virtual addresses, including the direct
8064 * map but excluding the recursive map.
8066 if (base < DMAP_MIN_ADDRESS)
8069 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
8070 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
8074 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8075 * into 4KB pages if required.
8077 for (tmpva = base; tmpva < base + size; ) {
8078 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8079 if (pdpe == NULL || *pdpe == 0)
8081 if (*pdpe & PG_PS) {
8083 * If the current 1GB page already has the required
8084 * memory type, then we need not demote this page. Just
8085 * increment tmpva to the next 1GB page frame.
8087 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
8088 tmpva = trunc_1gpage(tmpva) + NBPDP;
8093 * If the current offset aligns with a 1GB page frame
8094 * and there is at least 1GB left within the range, then
8095 * we need not break down this page into 2MB pages.
8097 if ((tmpva & PDPMASK) == 0 &&
8098 tmpva + PDPMASK < base + size) {
8102 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8105 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8110 * If the current 2MB page already has the required
8111 * memory type, then we need not demote this page. Just
8112 * increment tmpva to the next 2MB page frame.
8114 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
8115 tmpva = trunc_2mpage(tmpva) + NBPDR;
8120 * If the current offset aligns with a 2MB page frame
8121 * and there is at least 2MB left within the range, then
8122 * we need not break down this page into 4KB pages.
8124 if ((tmpva & PDRMASK) == 0 &&
8125 tmpva + PDRMASK < base + size) {
8129 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8132 pte = pmap_pde_to_pte(pde, tmpva);
8140 * Ok, all the pages exist, so run through them updating their
8141 * cache mode if required.
8143 pa_start = pa_end = 0;
8144 for (tmpva = base; tmpva < base + size; ) {
8145 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8146 if (*pdpe & PG_PS) {
8147 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
8148 pmap_pde_attr(pdpe, cache_bits_pde,
8152 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8153 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8154 if (pa_start == pa_end) {
8155 /* Start physical address run. */
8156 pa_start = *pdpe & PG_PS_FRAME;
8157 pa_end = pa_start + NBPDP;
8158 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8161 /* Run ended, update direct map. */
8162 error = pmap_change_attr_locked(
8163 PHYS_TO_DMAP(pa_start),
8164 pa_end - pa_start, mode, flags);
8167 /* Start physical address run. */
8168 pa_start = *pdpe & PG_PS_FRAME;
8169 pa_end = pa_start + NBPDP;
8172 tmpva = trunc_1gpage(tmpva) + NBPDP;
8175 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8177 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
8178 pmap_pde_attr(pde, cache_bits_pde,
8182 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8183 (*pde & PG_PS_FRAME) < dmaplimit) {
8184 if (pa_start == pa_end) {
8185 /* Start physical address run. */
8186 pa_start = *pde & PG_PS_FRAME;
8187 pa_end = pa_start + NBPDR;
8188 } else if (pa_end == (*pde & PG_PS_FRAME))
8191 /* Run ended, update direct map. */
8192 error = pmap_change_attr_locked(
8193 PHYS_TO_DMAP(pa_start),
8194 pa_end - pa_start, mode, flags);
8197 /* Start physical address run. */
8198 pa_start = *pde & PG_PS_FRAME;
8199 pa_end = pa_start + NBPDR;
8202 tmpva = trunc_2mpage(tmpva) + NBPDR;
8204 pte = pmap_pde_to_pte(pde, tmpva);
8205 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
8206 pmap_pte_attr(pte, cache_bits_pte,
8210 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8211 (*pte & PG_FRAME) < dmaplimit) {
8212 if (pa_start == pa_end) {
8213 /* Start physical address run. */
8214 pa_start = *pte & PG_FRAME;
8215 pa_end = pa_start + PAGE_SIZE;
8216 } else if (pa_end == (*pte & PG_FRAME))
8217 pa_end += PAGE_SIZE;
8219 /* Run ended, update direct map. */
8220 error = pmap_change_attr_locked(
8221 PHYS_TO_DMAP(pa_start),
8222 pa_end - pa_start, mode, flags);
8225 /* Start physical address run. */
8226 pa_start = *pte & PG_FRAME;
8227 pa_end = pa_start + PAGE_SIZE;
8233 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8234 pa_end1 = MIN(pa_end, dmaplimit);
8235 if (pa_start != pa_end1)
8236 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
8237 pa_end1 - pa_start, mode, flags);
8241 * Flush CPU caches if required to make sure any data isn't cached that
8242 * shouldn't be, etc.
8245 pmap_invalidate_range(kernel_pmap, base, tmpva);
8246 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8247 pmap_invalidate_cache_range(base, tmpva);
8253 * Demotes any mapping within the direct map region that covers more than the
8254 * specified range of physical addresses. This range's size must be a power
8255 * of two and its starting address must be a multiple of its size. Since the
8256 * demotion does not change any attributes of the mapping, a TLB invalidation
8257 * is not mandatory. The caller may, however, request a TLB invalidation.
8260 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8269 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8270 KASSERT((base & (len - 1)) == 0,
8271 ("pmap_demote_DMAP: base is not a multiple of len"));
8272 if (len < NBPDP && base < dmaplimit) {
8273 va = PHYS_TO_DMAP(base);
8275 PMAP_LOCK(kernel_pmap);
8276 pdpe = pmap_pdpe(kernel_pmap, va);
8277 if ((*pdpe & X86_PG_V) == 0)
8278 panic("pmap_demote_DMAP: invalid PDPE");
8279 if ((*pdpe & PG_PS) != 0) {
8280 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8281 panic("pmap_demote_DMAP: PDPE failed");
8285 pde = pmap_pdpe_to_pde(pdpe, va);
8286 if ((*pde & X86_PG_V) == 0)
8287 panic("pmap_demote_DMAP: invalid PDE");
8288 if ((*pde & PG_PS) != 0) {
8289 if (!pmap_demote_pde(kernel_pmap, pde, va))
8290 panic("pmap_demote_DMAP: PDE failed");
8294 if (changed && invalidate)
8295 pmap_invalidate_page(kernel_pmap, va);
8296 PMAP_UNLOCK(kernel_pmap);
8301 * perform the pmap work for mincore
8304 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8307 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8311 PG_A = pmap_accessed_bit(pmap);
8312 PG_M = pmap_modified_bit(pmap);
8313 PG_V = pmap_valid_bit(pmap);
8314 PG_RW = pmap_rw_bit(pmap);
8318 pdep = pmap_pde(pmap, addr);
8319 if (pdep != NULL && (*pdep & PG_V)) {
8320 if (*pdep & PG_PS) {
8322 /* Compute the physical address of the 4KB page. */
8323 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8325 val = MINCORE_SUPER;
8327 pte = *pmap_pde_to_pte(pdep, addr);
8328 pa = pte & PG_FRAME;
8336 if ((pte & PG_V) != 0) {
8337 val |= MINCORE_INCORE;
8338 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8339 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8340 if ((pte & PG_A) != 0)
8341 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8343 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8344 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8345 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8346 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8347 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8350 PA_UNLOCK_COND(*locked_pa);
8356 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8358 uint32_t gen, new_gen, pcid_next;
8360 CRITICAL_ASSERT(curthread);
8361 gen = PCPU_GET(pcid_gen);
8362 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8363 return (pti ? 0 : CR3_PCID_SAVE);
8364 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8365 return (CR3_PCID_SAVE);
8366 pcid_next = PCPU_GET(pcid_next);
8367 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8368 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8369 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8370 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8371 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8375 PCPU_SET(pcid_gen, new_gen);
8376 pcid_next = PMAP_PCID_KERN + 1;
8380 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8381 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8382 PCPU_SET(pcid_next, pcid_next + 1);
8387 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8391 cached = pmap_pcid_alloc(pmap, cpuid);
8392 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8393 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8394 pmap->pm_pcids[cpuid].pm_pcid));
8395 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8396 pmap == kernel_pmap,
8397 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8398 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8403 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8406 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8407 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
8411 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8413 struct invpcid_descr d;
8414 uint64_t cached, cr3, kcr3, ucr3;
8416 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8418 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8419 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8420 PCPU_SET(curpmap, pmap);
8421 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8422 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8425 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8427 * Explicitly invalidate translations cached from the
8428 * user page table. They are not automatically
8429 * flushed by reload of cr3 with the kernel page table
8432 * Note that the if() condition is resolved statically
8433 * by using the function argument instead of
8434 * runtime-evaluated invpcid_works value.
8436 if (invpcid_works1) {
8437 d.pcid = PMAP_PCID_USER_PT |
8438 pmap->pm_pcids[cpuid].pm_pcid;
8441 invpcid(&d, INVPCID_CTX);
8443 pmap_pti_pcid_invalidate(ucr3, kcr3);
8447 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8448 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8450 PCPU_INC(pm_save_cnt);
8454 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8457 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8458 pmap_activate_sw_pti_post(td, pmap);
8462 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8468 * If the INVPCID instruction is not available,
8469 * invltlb_pcid_handler() is used to handle an invalidate_all
8470 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8471 * sequence of operations has a window where %CR3 is loaded
8472 * with the new pmap's PML4 address, but the curpmap value has
8473 * not yet been updated. This causes the invltlb IPI handler,
8474 * which is called between the updates, to execute as a NOP,
8475 * which leaves stale TLB entries.
8477 * Note that the most typical use of pmap_activate_sw(), from
8478 * the context switch, is immune to this race, because
8479 * interrupts are disabled (while the thread lock is owned),
8480 * and the IPI happens after curpmap is updated. Protect
8481 * other callers in a similar way, by disabling interrupts
8482 * around the %cr3 register reload and curpmap assignment.
8484 rflags = intr_disable();
8485 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8486 intr_restore(rflags);
8487 pmap_activate_sw_pti_post(td, pmap);
8491 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8494 uint64_t cached, cr3;
8496 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8498 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8499 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8501 PCPU_SET(curpmap, pmap);
8503 PCPU_INC(pm_save_cnt);
8507 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8512 rflags = intr_disable();
8513 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8514 intr_restore(rflags);
8518 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8519 u_int cpuid __unused)
8522 load_cr3(pmap->pm_cr3);
8523 PCPU_SET(curpmap, pmap);
8527 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8528 u_int cpuid __unused)
8531 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8532 PCPU_SET(kcr3, pmap->pm_cr3);
8533 PCPU_SET(ucr3, pmap->pm_ucr3);
8534 pmap_activate_sw_pti_post(td, pmap);
8537 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8541 if (pmap_pcid_enabled && pti && invpcid_works)
8542 return (pmap_activate_sw_pcid_invpcid_pti);
8543 else if (pmap_pcid_enabled && pti && !invpcid_works)
8544 return (pmap_activate_sw_pcid_noinvpcid_pti);
8545 else if (pmap_pcid_enabled && !pti && invpcid_works)
8546 return (pmap_activate_sw_pcid_nopti);
8547 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8548 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8549 else if (!pmap_pcid_enabled && pti)
8550 return (pmap_activate_sw_nopcid_pti);
8551 else /* if (!pmap_pcid_enabled && !pti) */
8552 return (pmap_activate_sw_nopcid_nopti);
8556 pmap_activate_sw(struct thread *td)
8558 pmap_t oldpmap, pmap;
8561 oldpmap = PCPU_GET(curpmap);
8562 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8563 if (oldpmap == pmap)
8565 cpuid = PCPU_GET(cpuid);
8567 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8569 CPU_SET(cpuid, &pmap->pm_active);
8571 pmap_activate_sw_mode(td, pmap, cpuid);
8573 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8575 CPU_CLR(cpuid, &oldpmap->pm_active);
8580 pmap_activate(struct thread *td)
8584 pmap_activate_sw(td);
8589 pmap_activate_boot(pmap_t pmap)
8595 * kernel_pmap must be never deactivated, and we ensure that
8596 * by never activating it at all.
8598 MPASS(pmap != kernel_pmap);
8600 cpuid = PCPU_GET(cpuid);
8602 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8604 CPU_SET(cpuid, &pmap->pm_active);
8606 PCPU_SET(curpmap, pmap);
8608 kcr3 = pmap->pm_cr3;
8609 if (pmap_pcid_enabled)
8610 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8614 PCPU_SET(kcr3, kcr3);
8615 PCPU_SET(ucr3, PMAP_NO_CR3);
8619 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8624 * Increase the starting virtual address of the given mapping if a
8625 * different alignment might result in more superpage mappings.
8628 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8629 vm_offset_t *addr, vm_size_t size)
8631 vm_offset_t superpage_offset;
8635 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8636 offset += ptoa(object->pg_color);
8637 superpage_offset = offset & PDRMASK;
8638 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8639 (*addr & PDRMASK) == superpage_offset)
8641 if ((*addr & PDRMASK) < superpage_offset)
8642 *addr = (*addr & ~PDRMASK) + superpage_offset;
8644 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8648 static unsigned long num_dirty_emulations;
8649 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8650 &num_dirty_emulations, 0, NULL);
8652 static unsigned long num_accessed_emulations;
8653 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8654 &num_accessed_emulations, 0, NULL);
8656 static unsigned long num_superpage_accessed_emulations;
8657 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8658 &num_superpage_accessed_emulations, 0, NULL);
8660 static unsigned long ad_emulation_superpage_promotions;
8661 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8662 &ad_emulation_superpage_promotions, 0, NULL);
8663 #endif /* INVARIANTS */
8666 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8669 struct rwlock *lock;
8670 #if VM_NRESERVLEVEL > 0
8674 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8676 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8677 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8679 if (!pmap_emulate_ad_bits(pmap))
8682 PG_A = pmap_accessed_bit(pmap);
8683 PG_M = pmap_modified_bit(pmap);
8684 PG_V = pmap_valid_bit(pmap);
8685 PG_RW = pmap_rw_bit(pmap);
8691 pde = pmap_pde(pmap, va);
8692 if (pde == NULL || (*pde & PG_V) == 0)
8695 if ((*pde & PG_PS) != 0) {
8696 if (ftype == VM_PROT_READ) {
8698 atomic_add_long(&num_superpage_accessed_emulations, 1);
8706 pte = pmap_pde_to_pte(pde, va);
8707 if ((*pte & PG_V) == 0)
8710 if (ftype == VM_PROT_WRITE) {
8711 if ((*pte & PG_RW) == 0)
8714 * Set the modified and accessed bits simultaneously.
8716 * Intel EPT PTEs that do software emulation of A/D bits map
8717 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8718 * An EPT misconfiguration is triggered if the PTE is writable
8719 * but not readable (WR=10). This is avoided by setting PG_A
8720 * and PG_M simultaneously.
8722 *pte |= PG_M | PG_A;
8727 #if VM_NRESERVLEVEL > 0
8728 /* try to promote the mapping */
8729 if (va < VM_MAXUSER_ADDRESS)
8730 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8734 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8736 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
8737 pmap_ps_enabled(pmap) &&
8738 (m->flags & PG_FICTITIOUS) == 0 &&
8739 vm_reserv_level_iffullpop(m) == 0) {
8740 pmap_promote_pde(pmap, pde, va, &lock);
8742 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8748 if (ftype == VM_PROT_WRITE)
8749 atomic_add_long(&num_dirty_emulations, 1);
8751 atomic_add_long(&num_accessed_emulations, 1);
8753 rv = 0; /* success */
8762 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8767 pt_entry_t *pte, PG_V;
8771 PG_V = pmap_valid_bit(pmap);
8774 pml4 = pmap_pml4e(pmap, va);
8776 if ((*pml4 & PG_V) == 0)
8779 pdp = pmap_pml4e_to_pdpe(pml4, va);
8781 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8784 pde = pmap_pdpe_to_pde(pdp, va);
8786 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8789 pte = pmap_pde_to_pte(pde, va);
8798 * Get the kernel virtual address of a set of physical pages. If there are
8799 * physical addresses not covered by the DMAP perform a transient mapping
8800 * that will be removed when calling pmap_unmap_io_transient.
8802 * \param page The pages the caller wishes to obtain the virtual
8803 * address on the kernel memory map.
8804 * \param vaddr On return contains the kernel virtual memory address
8805 * of the pages passed in the page parameter.
8806 * \param count Number of pages passed in.
8807 * \param can_fault TRUE if the thread using the mapped pages can take
8808 * page faults, FALSE otherwise.
8810 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8811 * finished or FALSE otherwise.
8815 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8816 boolean_t can_fault)
8819 boolean_t needs_mapping;
8821 int cache_bits, error __unused, i;
8824 * Allocate any KVA space that we need, this is done in a separate
8825 * loop to prevent calling vmem_alloc while pinned.
8827 needs_mapping = FALSE;
8828 for (i = 0; i < count; i++) {
8829 paddr = VM_PAGE_TO_PHYS(page[i]);
8830 if (__predict_false(paddr >= dmaplimit)) {
8831 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8832 M_BESTFIT | M_WAITOK, &vaddr[i]);
8833 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8834 needs_mapping = TRUE;
8836 vaddr[i] = PHYS_TO_DMAP(paddr);
8840 /* Exit early if everything is covered by the DMAP */
8845 * NB: The sequence of updating a page table followed by accesses
8846 * to the corresponding pages used in the !DMAP case is subject to
8847 * the situation described in the "AMD64 Architecture Programmer's
8848 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8849 * Coherency Considerations". Therefore, issuing the INVLPG right
8850 * after modifying the PTE bits is crucial.
8854 for (i = 0; i < count; i++) {
8855 paddr = VM_PAGE_TO_PHYS(page[i]);
8856 if (paddr >= dmaplimit) {
8859 * Slow path, since we can get page faults
8860 * while mappings are active don't pin the
8861 * thread to the CPU and instead add a global
8862 * mapping visible to all CPUs.
8864 pmap_qenter(vaddr[i], &page[i], 1);
8866 pte = vtopte(vaddr[i]);
8867 cache_bits = pmap_cache_bits(kernel_pmap,
8868 page[i]->md.pat_mode, 0);
8869 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8876 return (needs_mapping);
8880 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8881 boolean_t can_fault)
8888 for (i = 0; i < count; i++) {
8889 paddr = VM_PAGE_TO_PHYS(page[i]);
8890 if (paddr >= dmaplimit) {
8892 pmap_qremove(vaddr[i], 1);
8893 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8899 pmap_quick_enter_page(vm_page_t m)
8903 paddr = VM_PAGE_TO_PHYS(m);
8904 if (paddr < dmaplimit)
8905 return (PHYS_TO_DMAP(paddr));
8906 mtx_lock_spin(&qframe_mtx);
8907 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8908 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8909 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8914 pmap_quick_remove_page(vm_offset_t addr)
8919 pte_store(vtopte(qframe), 0);
8921 mtx_unlock_spin(&qframe_mtx);
8925 * Pdp pages from the large map are managed differently from either
8926 * kernel or user page table pages. They are permanently allocated at
8927 * initialization time, and their reference count is permanently set to
8928 * zero. The pml4 entries pointing to those pages are copied into
8929 * each allocated pmap.
8931 * In contrast, pd and pt pages are managed like user page table
8932 * pages. They are dynamically allocated, and their reference count
8933 * represents the number of valid entries within the page.
8936 pmap_large_map_getptp_unlocked(void)
8940 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8942 if (m != NULL && (m->flags & PG_ZERO) == 0)
8948 pmap_large_map_getptp(void)
8952 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8953 m = pmap_large_map_getptp_unlocked();
8955 PMAP_UNLOCK(kernel_pmap);
8957 PMAP_LOCK(kernel_pmap);
8958 /* Callers retry. */
8963 static pdp_entry_t *
8964 pmap_large_map_pdpe(vm_offset_t va)
8966 vm_pindex_t pml4_idx;
8969 pml4_idx = pmap_pml4e_index(va);
8970 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8971 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8973 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8974 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8975 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8976 "LMSPML4I %#jx lm_ents %d",
8977 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8978 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8979 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8983 pmap_large_map_pde(vm_offset_t va)
8990 pdpe = pmap_large_map_pdpe(va);
8992 m = pmap_large_map_getptp();
8995 mphys = VM_PAGE_TO_PHYS(m);
8996 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8998 MPASS((*pdpe & X86_PG_PS) == 0);
8999 mphys = *pdpe & PG_FRAME;
9001 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9005 pmap_large_map_pte(vm_offset_t va)
9012 pde = pmap_large_map_pde(va);
9014 m = pmap_large_map_getptp();
9017 mphys = VM_PAGE_TO_PHYS(m);
9018 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9019 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9021 MPASS((*pde & X86_PG_PS) == 0);
9022 mphys = *pde & PG_FRAME;
9024 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9028 pmap_large_map_kextract(vm_offset_t va)
9030 pdp_entry_t *pdpe, pdp;
9031 pd_entry_t *pde, pd;
9032 pt_entry_t *pte, pt;
9034 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9035 ("not largemap range %#lx", (u_long)va));
9036 pdpe = pmap_large_map_pdpe(va);
9038 KASSERT((pdp & X86_PG_V) != 0,
9039 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9040 (u_long)pdpe, pdp));
9041 if ((pdp & X86_PG_PS) != 0) {
9042 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9043 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9044 (u_long)pdpe, pdp));
9045 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9047 pde = pmap_pdpe_to_pde(pdpe, va);
9049 KASSERT((pd & X86_PG_V) != 0,
9050 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9051 if ((pd & X86_PG_PS) != 0)
9052 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9053 pte = pmap_pde_to_pte(pde, va);
9055 KASSERT((pt & X86_PG_V) != 0,
9056 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9057 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9061 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9062 vmem_addr_t *vmem_res)
9066 * Large mappings are all but static. Consequently, there
9067 * is no point in waiting for an earlier allocation to be
9070 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9071 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9075 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9081 vm_offset_t va, inc;
9082 vmem_addr_t vmem_res;
9086 if (len == 0 || spa + len < spa)
9089 /* See if DMAP can serve. */
9090 if (spa + len <= dmaplimit) {
9091 va = PHYS_TO_DMAP(spa);
9093 return (pmap_change_attr(va, len, mattr));
9097 * No, allocate KVA. Fit the address with best possible
9098 * alignment for superpages. Fall back to worse align if
9102 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9103 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9104 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9106 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9108 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9111 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9116 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9117 * in the pagetable to minimize flushing. No need to
9118 * invalidate TLB, since we only update invalid entries.
9120 PMAP_LOCK(kernel_pmap);
9121 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9123 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9124 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9125 pdpe = pmap_large_map_pdpe(va);
9127 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9128 X86_PG_V | X86_PG_A | pg_nx |
9129 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9131 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9132 (va & PDRMASK) == 0) {
9133 pde = pmap_large_map_pde(va);
9135 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9136 X86_PG_V | X86_PG_A | pg_nx |
9137 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9138 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9142 pte = pmap_large_map_pte(va);
9144 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9145 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9147 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9152 PMAP_UNLOCK(kernel_pmap);
9155 *addr = (void *)vmem_res;
9160 pmap_large_unmap(void *svaa, vm_size_t len)
9162 vm_offset_t sva, va;
9164 pdp_entry_t *pdpe, pdp;
9165 pd_entry_t *pde, pd;
9168 struct spglist spgf;
9170 sva = (vm_offset_t)svaa;
9171 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9172 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9176 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9177 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9178 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9179 PMAP_LOCK(kernel_pmap);
9180 for (va = sva; va < sva + len; va += inc) {
9181 pdpe = pmap_large_map_pdpe(va);
9183 KASSERT((pdp & X86_PG_V) != 0,
9184 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9185 (u_long)pdpe, pdp));
9186 if ((pdp & X86_PG_PS) != 0) {
9187 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9188 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9189 (u_long)pdpe, pdp));
9190 KASSERT((va & PDPMASK) == 0,
9191 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9192 (u_long)pdpe, pdp));
9193 KASSERT(va + NBPDP <= sva + len,
9194 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9195 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9196 (u_long)pdpe, pdp, len));
9201 pde = pmap_pdpe_to_pde(pdpe, va);
9203 KASSERT((pd & X86_PG_V) != 0,
9204 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9206 if ((pd & X86_PG_PS) != 0) {
9207 KASSERT((va & PDRMASK) == 0,
9208 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9210 KASSERT(va + NBPDR <= sva + len,
9211 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9212 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9216 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9218 if (m->ref_count == 0) {
9220 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9224 pte = pmap_pde_to_pte(pde, va);
9225 KASSERT((*pte & X86_PG_V) != 0,
9226 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9227 (u_long)pte, *pte));
9230 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9232 if (m->ref_count == 0) {
9234 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9235 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9237 if (m->ref_count == 0) {
9239 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9243 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9244 PMAP_UNLOCK(kernel_pmap);
9245 vm_page_free_pages_toq(&spgf, false);
9246 vmem_free(large_vmem, sva, len);
9250 pmap_large_map_wb_fence_mfence(void)
9257 pmap_large_map_wb_fence_sfence(void)
9264 pmap_large_map_wb_fence_nop(void)
9268 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9271 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9272 return (pmap_large_map_wb_fence_mfence);
9273 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9274 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9275 return (pmap_large_map_wb_fence_sfence);
9277 /* clflush is strongly enough ordered */
9278 return (pmap_large_map_wb_fence_nop);
9282 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9285 for (; len > 0; len -= cpu_clflush_line_size,
9286 va += cpu_clflush_line_size)
9291 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9294 for (; len > 0; len -= cpu_clflush_line_size,
9295 va += cpu_clflush_line_size)
9300 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9303 for (; len > 0; len -= cpu_clflush_line_size,
9304 va += cpu_clflush_line_size)
9309 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9313 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9316 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9317 return (pmap_large_map_flush_range_clwb);
9318 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9319 return (pmap_large_map_flush_range_clflushopt);
9320 else if ((cpu_feature & CPUID_CLFSH) != 0)
9321 return (pmap_large_map_flush_range_clflush);
9323 return (pmap_large_map_flush_range_nop);
9327 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9329 volatile u_long *pe;
9335 for (va = sva; va < eva; va += inc) {
9337 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9338 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9340 if ((p & X86_PG_PS) != 0)
9344 pe = (volatile u_long *)pmap_large_map_pde(va);
9346 if ((p & X86_PG_PS) != 0)
9350 pe = (volatile u_long *)pmap_large_map_pte(va);
9356 if ((p & X86_PG_AVAIL1) != 0) {
9358 * Spin-wait for the end of a parallel
9365 * If we saw other write-back
9366 * occuring, we cannot rely on PG_M to
9367 * indicate state of the cache. The
9368 * PG_M bit is cleared before the
9369 * flush to avoid ignoring new writes,
9370 * and writes which are relevant for
9371 * us might happen after.
9377 if ((p & X86_PG_M) != 0 || seen_other) {
9378 if (!atomic_fcmpset_long(pe, &p,
9379 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9381 * If we saw PG_M without
9382 * PG_AVAIL1, and then on the
9383 * next attempt we do not
9384 * observe either PG_M or
9385 * PG_AVAIL1, the other
9386 * write-back started after us
9387 * and finished before us. We
9388 * can rely on it doing our
9392 pmap_large_map_flush_range(va, inc);
9393 atomic_clear_long(pe, X86_PG_AVAIL1);
9402 * Write-back cache lines for the given address range.
9404 * Must be called only on the range or sub-range returned from
9405 * pmap_large_map(). Must not be called on the coalesced ranges.
9407 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9408 * instructions support.
9411 pmap_large_map_wb(void *svap, vm_size_t len)
9413 vm_offset_t eva, sva;
9415 sva = (vm_offset_t)svap;
9417 pmap_large_map_wb_fence();
9418 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9419 pmap_large_map_flush_range(sva, len);
9421 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9422 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9423 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9424 pmap_large_map_wb_large(sva, eva);
9426 pmap_large_map_wb_fence();
9430 pmap_pti_alloc_page(void)
9434 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9435 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9436 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9441 pmap_pti_free_page(vm_page_t m)
9444 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
9445 if (!vm_page_unwire_noq(m))
9447 vm_page_free_zero(m);
9461 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9462 VM_OBJECT_WLOCK(pti_obj);
9463 pml4_pg = pmap_pti_alloc_page();
9464 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9465 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9466 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9467 pdpe = pmap_pti_pdpe(va);
9468 pmap_pti_wire_pte(pdpe);
9470 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9471 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9472 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9473 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9474 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9475 sizeof(struct gate_descriptor) * NIDT, false);
9476 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9477 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9479 /* Doublefault stack IST 1 */
9480 va = common_tss[i].tss_ist1;
9481 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9482 /* NMI stack IST 2 */
9483 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9484 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9485 /* MC# stack IST 3 */
9486 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9487 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9488 /* DB# stack IST 4 */
9489 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9490 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9492 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9493 (vm_offset_t)etext, true);
9494 pti_finalized = true;
9495 VM_OBJECT_WUNLOCK(pti_obj);
9497 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9499 static pdp_entry_t *
9500 pmap_pti_pdpe(vm_offset_t va)
9502 pml4_entry_t *pml4e;
9505 vm_pindex_t pml4_idx;
9508 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9510 pml4_idx = pmap_pml4e_index(va);
9511 pml4e = &pti_pml4[pml4_idx];
9515 panic("pml4 alloc after finalization\n");
9516 m = pmap_pti_alloc_page();
9518 pmap_pti_free_page(m);
9519 mphys = *pml4e & ~PAGE_MASK;
9521 mphys = VM_PAGE_TO_PHYS(m);
9522 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9525 mphys = *pml4e & ~PAGE_MASK;
9527 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9532 pmap_pti_wire_pte(void *pte)
9536 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9537 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9542 pmap_pti_unwire_pde(void *pde, bool only_ref)
9546 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9547 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9548 MPASS(m->ref_count > 0);
9549 MPASS(only_ref || m->ref_count > 1);
9550 pmap_pti_free_page(m);
9554 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9559 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9560 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9561 MPASS(m->ref_count > 0);
9562 if (pmap_pti_free_page(m)) {
9563 pde = pmap_pti_pde(va);
9564 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9566 pmap_pti_unwire_pde(pde, false);
9571 pmap_pti_pde(vm_offset_t va)
9579 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9581 pdpe = pmap_pti_pdpe(va);
9583 m = pmap_pti_alloc_page();
9585 pmap_pti_free_page(m);
9586 MPASS((*pdpe & X86_PG_PS) == 0);
9587 mphys = *pdpe & ~PAGE_MASK;
9589 mphys = VM_PAGE_TO_PHYS(m);
9590 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9593 MPASS((*pdpe & X86_PG_PS) == 0);
9594 mphys = *pdpe & ~PAGE_MASK;
9597 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9598 pd_idx = pmap_pde_index(va);
9604 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9611 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9613 pde = pmap_pti_pde(va);
9614 if (unwire_pde != NULL) {
9616 pmap_pti_wire_pte(pde);
9619 m = pmap_pti_alloc_page();
9621 pmap_pti_free_page(m);
9622 MPASS((*pde & X86_PG_PS) == 0);
9623 mphys = *pde & ~(PAGE_MASK | pg_nx);
9625 mphys = VM_PAGE_TO_PHYS(m);
9626 *pde = mphys | X86_PG_RW | X86_PG_V;
9627 if (unwire_pde != NULL)
9628 *unwire_pde = false;
9631 MPASS((*pde & X86_PG_PS) == 0);
9632 mphys = *pde & ~(PAGE_MASK | pg_nx);
9635 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9636 pte += pmap_pte_index(va);
9642 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9646 pt_entry_t *pte, ptev;
9649 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9651 sva = trunc_page(sva);
9652 MPASS(sva > VM_MAXUSER_ADDRESS);
9653 eva = round_page(eva);
9655 for (; sva < eva; sva += PAGE_SIZE) {
9656 pte = pmap_pti_pte(sva, &unwire_pde);
9657 pa = pmap_kextract(sva);
9658 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9659 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9660 VM_MEMATTR_DEFAULT, FALSE);
9662 pte_store(pte, ptev);
9663 pmap_pti_wire_pte(pte);
9665 KASSERT(!pti_finalized,
9666 ("pti overlap after fin %#lx %#lx %#lx",
9668 KASSERT(*pte == ptev,
9669 ("pti non-identical pte after fin %#lx %#lx %#lx",
9673 pde = pmap_pti_pde(sva);
9674 pmap_pti_unwire_pde(pde, true);
9680 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9685 VM_OBJECT_WLOCK(pti_obj);
9686 pmap_pti_add_kva_locked(sva, eva, exec);
9687 VM_OBJECT_WUNLOCK(pti_obj);
9691 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9698 sva = rounddown2(sva, PAGE_SIZE);
9699 MPASS(sva > VM_MAXUSER_ADDRESS);
9700 eva = roundup2(eva, PAGE_SIZE);
9702 VM_OBJECT_WLOCK(pti_obj);
9703 for (va = sva; va < eva; va += PAGE_SIZE) {
9704 pte = pmap_pti_pte(va, NULL);
9705 KASSERT((*pte & X86_PG_V) != 0,
9706 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9707 (u_long)pte, *pte));
9709 pmap_pti_unwire_pte(pte, va);
9711 pmap_invalidate_range(kernel_pmap, sva, eva);
9712 VM_OBJECT_WUNLOCK(pti_obj);
9716 pkru_dup_range(void *ctx __unused, void *data)
9718 struct pmap_pkru_range *node, *new_node;
9720 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9721 if (new_node == NULL)
9724 memcpy(new_node, node, sizeof(*node));
9729 pkru_free_range(void *ctx __unused, void *node)
9732 uma_zfree(pmap_pkru_ranges_zone, node);
9736 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9739 struct pmap_pkru_range *ppr;
9742 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9743 MPASS(pmap->pm_type == PT_X86);
9744 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9745 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9746 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9748 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9751 ppr->pkru_keyidx = keyidx;
9752 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9753 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9755 uma_zfree(pmap_pkru_ranges_zone, ppr);
9760 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9764 MPASS(pmap->pm_type == PT_X86);
9765 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9766 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9770 pmap_pkru_deassign_all(pmap_t pmap)
9773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9774 if (pmap->pm_type == PT_X86 &&
9775 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9776 rangeset_remove_all(&pmap->pm_pkru);
9780 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9782 struct pmap_pkru_range *ppr, *prev_ppr;
9785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9786 if (pmap->pm_type != PT_X86 ||
9787 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9788 sva >= VM_MAXUSER_ADDRESS)
9790 MPASS(eva <= VM_MAXUSER_ADDRESS);
9791 for (va = sva, prev_ppr = NULL; va < eva;) {
9792 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9793 if ((ppr == NULL) ^ (prev_ppr == NULL))
9799 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9801 va = ppr->pkru_rs_el.re_end;
9807 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9809 struct pmap_pkru_range *ppr;
9811 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9812 if (pmap->pm_type != PT_X86 ||
9813 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9814 va >= VM_MAXUSER_ADDRESS)
9816 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9818 return (X86_PG_PKU(ppr->pkru_keyidx));
9823 pred_pkru_on_remove(void *ctx __unused, void *r)
9825 struct pmap_pkru_range *ppr;
9828 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9832 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9835 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9836 if (pmap->pm_type == PT_X86 &&
9837 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9838 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9839 pred_pkru_on_remove);
9844 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9847 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9848 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9849 MPASS(dst_pmap->pm_type == PT_X86);
9850 MPASS(src_pmap->pm_type == PT_X86);
9851 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9852 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9854 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9858 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9861 pml4_entry_t *pml4e;
9863 pd_entry_t newpde, ptpaddr, *pde;
9864 pt_entry_t newpte, *ptep, pte;
9865 vm_offset_t va, va_next;
9868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9869 MPASS(pmap->pm_type == PT_X86);
9870 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9872 for (changed = false, va = sva; va < eva; va = va_next) {
9873 pml4e = pmap_pml4e(pmap, va);
9874 if ((*pml4e & X86_PG_V) == 0) {
9875 va_next = (va + NBPML4) & ~PML4MASK;
9881 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9882 if ((*pdpe & X86_PG_V) == 0) {
9883 va_next = (va + NBPDP) & ~PDPMASK;
9889 va_next = (va + NBPDR) & ~PDRMASK;
9893 pde = pmap_pdpe_to_pde(pdpe, va);
9898 MPASS((ptpaddr & X86_PG_V) != 0);
9899 if ((ptpaddr & PG_PS) != 0) {
9900 if (va + NBPDR == va_next && eva >= va_next) {
9901 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9903 if (newpde != ptpaddr) {
9908 } else if (!pmap_demote_pde(pmap, pde, va)) {
9916 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9917 ptep++, va += PAGE_SIZE) {
9919 if ((pte & X86_PG_V) == 0)
9921 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9922 if (newpte != pte) {
9929 pmap_invalidate_range(pmap, sva, eva);
9933 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9934 u_int keyidx, int flags)
9937 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9938 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9940 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9942 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9948 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9953 sva = trunc_page(sva);
9954 eva = round_page(eva);
9955 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9960 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9962 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9964 if (error != ENOMEM)
9972 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9976 sva = trunc_page(sva);
9977 eva = round_page(eva);
9978 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9983 error = pmap_pkru_deassign(pmap, sva, eva);
9985 pmap_pkru_update_range(pmap, sva, eva, 0);
9987 if (error != ENOMEM)
9995 * Track a range of the kernel's virtual address space that is contiguous
9996 * in various mapping attributes.
9998 struct pmap_kernel_map_range {
10007 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10013 if (eva <= range->sva)
10016 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10017 for (i = 0; i < PAT_INDEX_SIZE; i++)
10018 if (pat_index[i] == pat_idx)
10022 case PAT_WRITE_BACK:
10025 case PAT_WRITE_THROUGH:
10028 case PAT_UNCACHEABLE:
10034 case PAT_WRITE_PROTECTED:
10037 case PAT_WRITE_COMBINING:
10041 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10042 __func__, pat_idx, range->sva, eva);
10047 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10049 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10050 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10051 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10052 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10053 mode, range->pdpes, range->pdes, range->ptes);
10055 /* Reset to sentinel value. */
10056 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10060 * Determine whether the attributes specified by a page table entry match those
10061 * being tracked by the current range. This is not quite as simple as a direct
10062 * flag comparison since some PAT modes have multiple representations.
10065 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10067 pt_entry_t diff, mask;
10069 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10070 diff = (range->attrs ^ attrs) & mask;
10073 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10074 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10075 pmap_pat_index(kernel_pmap, attrs, true))
10081 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10085 memset(range, 0, sizeof(*range));
10087 range->attrs = attrs;
10091 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10092 * those of the current run, dump the address range and its attributes, and
10096 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10097 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10102 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10104 attrs |= pdpe & pg_nx;
10105 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10106 if ((pdpe & PG_PS) != 0) {
10107 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10108 } else if (pde != 0) {
10109 attrs |= pde & pg_nx;
10110 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10112 if ((pde & PG_PS) != 0) {
10113 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10114 } else if (pte != 0) {
10115 attrs |= pte & pg_nx;
10116 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10117 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10119 /* Canonicalize by always using the PDE PAT bit. */
10120 if ((attrs & X86_PG_PTE_PAT) != 0)
10121 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10124 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10125 sysctl_kmaps_dump(sb, range, va);
10126 sysctl_kmaps_reinit(range, va, attrs);
10131 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10133 struct pmap_kernel_map_range range;
10134 struct sbuf sbuf, *sb;
10135 pml4_entry_t pml4e;
10136 pdp_entry_t *pdp, pdpe;
10137 pd_entry_t *pd, pde;
10138 pt_entry_t *pt, pte;
10141 int error, i, j, k, l;
10143 error = sysctl_wire_old_buffer(req, 0);
10147 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10149 /* Sentinel value. */
10150 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10153 * Iterate over the kernel page tables without holding the kernel pmap
10154 * lock. Outside of the large map, kernel page table pages are never
10155 * freed, so at worst we will observe inconsistencies in the output.
10156 * Within the large map, ensure that PDP and PD page addresses are
10157 * valid before descending.
10159 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10162 sbuf_printf(sb, "\nRecursive map:\n");
10165 sbuf_printf(sb, "\nDirect map:\n");
10168 sbuf_printf(sb, "\nKernel map:\n");
10171 sbuf_printf(sb, "\nLarge map:\n");
10175 /* Convert to canonical form. */
10176 if (sva == 1ul << 47)
10180 pml4e = kernel_pmap->pm_pml4[i];
10181 if ((pml4e & X86_PG_V) == 0) {
10182 sva = rounddown2(sva, NBPML4);
10183 sysctl_kmaps_dump(sb, &range, sva);
10187 pa = pml4e & PG_FRAME;
10188 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10190 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10192 if ((pdpe & X86_PG_V) == 0) {
10193 sva = rounddown2(sva, NBPDP);
10194 sysctl_kmaps_dump(sb, &range, sva);
10198 pa = pdpe & PG_FRAME;
10199 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10200 vm_phys_paddr_to_vm_page(pa) == NULL)
10202 if ((pdpe & PG_PS) != 0) {
10203 sva = rounddown2(sva, NBPDP);
10204 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10210 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10212 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10214 if ((pde & X86_PG_V) == 0) {
10215 sva = rounddown2(sva, NBPDR);
10216 sysctl_kmaps_dump(sb, &range, sva);
10220 pa = pde & PG_FRAME;
10221 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10222 vm_phys_paddr_to_vm_page(pa) == NULL)
10224 if ((pde & PG_PS) != 0) {
10225 sva = rounddown2(sva, NBPDR);
10226 sysctl_kmaps_check(sb, &range, sva,
10227 pml4e, pdpe, pde, 0);
10232 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10234 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10235 sva += PAGE_SIZE) {
10237 if ((pte & X86_PG_V) == 0) {
10238 sysctl_kmaps_dump(sb, &range,
10242 sysctl_kmaps_check(sb, &range, sva,
10243 pml4e, pdpe, pde, pte);
10250 error = sbuf_finish(sb);
10254 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10255 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10256 NULL, 0, sysctl_kmaps, "A",
10257 "Dump kernel address layout");
10260 DB_SHOW_COMMAND(pte, pmap_print_pte)
10263 pml4_entry_t *pml4;
10266 pt_entry_t *pte, PG_V;
10270 db_printf("show pte addr\n");
10273 va = (vm_offset_t)addr;
10275 if (kdb_thread != NULL)
10276 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10278 pmap = PCPU_GET(curpmap);
10280 PG_V = pmap_valid_bit(pmap);
10281 pml4 = pmap_pml4e(pmap, va);
10282 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10283 if ((*pml4 & PG_V) == 0) {
10287 pdp = pmap_pml4e_to_pdpe(pml4, va);
10288 db_printf(" pdpe 0x%016lx", *pdp);
10289 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10293 pde = pmap_pdpe_to_pde(pdp, va);
10294 db_printf(" pde 0x%016lx", *pde);
10295 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10299 pte = pmap_pde_to_pte(pde, va);
10300 db_printf(" pte 0x%016lx\n", *pte);
10303 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10308 a = (vm_paddr_t)addr;
10309 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10311 db_printf("show phys2dmap addr\n");