2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
128 #include <sys/turnstile.h>
129 #include <sys/vmem.h>
130 #include <sys/vmmeter.h>
131 #include <sys/sched.h>
132 #include <sys/sysctl.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
148 #include <vm/vm_phys.h>
149 #include <vm/vm_radix.h>
150 #include <vm/vm_reserv.h>
153 #include <machine/intr_machdep.h>
154 #include <x86/apicvar.h>
155 #include <x86/ifunc.h>
156 #include <machine/cpu.h>
157 #include <machine/cputypes.h>
158 #include <machine/md_var.h>
159 #include <machine/pcb.h>
160 #include <machine/specialreg.h>
162 #include <machine/smp.h>
164 #include <machine/sysarch.h>
165 #include <machine/tss.h>
167 static __inline boolean_t
168 pmap_type_guest(pmap_t pmap)
171 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
174 static __inline boolean_t
175 pmap_emulate_ad_bits(pmap_t pmap)
178 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
181 static __inline pt_entry_t
182 pmap_valid_bit(pmap_t pmap)
186 switch (pmap->pm_type) {
192 if (pmap_emulate_ad_bits(pmap))
193 mask = EPT_PG_EMUL_V;
198 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
204 static __inline pt_entry_t
205 pmap_rw_bit(pmap_t pmap)
209 switch (pmap->pm_type) {
215 if (pmap_emulate_ad_bits(pmap))
216 mask = EPT_PG_EMUL_RW;
221 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
227 static pt_entry_t pg_g;
229 static __inline pt_entry_t
230 pmap_global_bit(pmap_t pmap)
234 switch (pmap->pm_type) {
243 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
249 static __inline pt_entry_t
250 pmap_accessed_bit(pmap_t pmap)
254 switch (pmap->pm_type) {
260 if (pmap_emulate_ad_bits(pmap))
266 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
272 static __inline pt_entry_t
273 pmap_modified_bit(pmap_t pmap)
277 switch (pmap->pm_type) {
283 if (pmap_emulate_ad_bits(pmap))
289 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
295 static __inline pt_entry_t
296 pmap_pku_mask_bit(pmap_t pmap)
299 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
302 #if !defined(DIAGNOSTIC)
303 #ifdef __GNUC_GNU_INLINE__
304 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
306 #define PMAP_INLINE extern inline
313 #define PV_STAT(x) do { x ; } while (0)
315 #define PV_STAT(x) do { } while (0)
318 #define pa_index(pa) ((pa) >> PDRSHIFT)
319 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
321 #define NPV_LIST_LOCKS MAXCPU
323 #define PHYS_TO_PV_LIST_LOCK(pa) \
324 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
326 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
327 struct rwlock **_lockp = (lockp); \
328 struct rwlock *_new_lock; \
330 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
331 if (_new_lock != *_lockp) { \
332 if (*_lockp != NULL) \
333 rw_wunlock(*_lockp); \
334 *_lockp = _new_lock; \
339 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
340 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
342 #define RELEASE_PV_LIST_LOCK(lockp) do { \
343 struct rwlock **_lockp = (lockp); \
345 if (*_lockp != NULL) { \
346 rw_wunlock(*_lockp); \
351 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
352 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
354 struct pmap kernel_pmap_store;
356 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
357 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
360 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
361 "Number of kernel page table pages allocated on bootup");
364 vm_paddr_t dmaplimit;
365 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
368 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
370 static int pg_ps_enabled = 1;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
372 &pg_ps_enabled, 0, "Are large page mappings enabled?");
374 #define PAT_INDEX_SIZE 8
375 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
377 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
378 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
379 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
380 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
382 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
383 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
384 static int ndmpdpphys; /* number of DMPDPphys pages */
386 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
389 * pmap_mapdev support pre initialization (i.e. console)
391 #define PMAP_PREINIT_MAPPING_COUNT 8
392 static struct pmap_preinit_mapping {
397 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
398 static int pmap_initialized;
401 * Data for the pv entry allocation mechanism.
402 * Updates to pv_invl_gen are protected by the pv_list_locks[]
403 * elements, but reads are not.
405 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
406 static struct mtx __exclusive_cache_line pv_chunks_mutex;
407 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
408 static u_long pv_invl_gen[NPV_LIST_LOCKS];
409 static struct md_page *pv_table;
410 static struct md_page pv_dummy;
413 * All those kernel PT submaps that BSD is so fond of
415 pt_entry_t *CMAP1 = NULL;
417 static vm_offset_t qframe = 0;
418 static struct mtx qframe_mtx;
420 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
422 static vmem_t *large_vmem;
423 static u_int lm_ents;
424 #define PMAP_LARGEMAP_MAX_ADDRESS() \
425 (LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
427 int pmap_pcid_enabled = 1;
428 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
429 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
430 int invpcid_works = 0;
431 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
432 "Is the invpcid instruction available ?");
434 int __read_frequently pti = 0;
435 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
437 "Page Table Isolation enabled");
438 static vm_object_t pti_obj;
439 static pml4_entry_t *pti_pml4;
440 static vm_pindex_t pti_pg_idx;
441 static bool pti_finalized;
443 struct pmap_pkru_range {
444 struct rs_el pkru_rs_el;
449 static uma_zone_t pmap_pkru_ranges_zone;
450 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
451 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
452 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
453 static void *pkru_dup_range(void *ctx, void *data);
454 static void pkru_free_range(void *ctx, void *node);
455 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
456 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
457 static void pmap_pkru_deassign_all(pmap_t pmap);
460 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
467 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
469 return (sysctl_handle_64(oidp, &res, 0, req));
471 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
472 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
473 "Count of saved TLB context on switch");
475 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
476 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
477 static struct mtx invl_gen_mtx;
478 /* Fake lock object to satisfy turnstiles interface. */
479 static struct lock_object invl_gen_ts = {
482 static struct pmap_invl_gen pmap_invl_gen_head = {
486 static u_long pmap_invl_gen = 1;
487 static int pmap_invl_waiters;
488 static struct callout pmap_invl_callout;
489 static bool pmap_invl_callout_inited;
491 #define PMAP_ASSERT_NOT_IN_DI() \
492 KASSERT(pmap_not_in_di(), ("DI already started"))
499 if ((cpu_feature2 & CPUID2_CX16) == 0)
502 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
507 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
511 locked = pmap_di_locked();
512 return (sysctl_handle_int(oidp, &locked, 0, req));
514 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
515 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
516 "Locked delayed invalidation");
518 static bool pmap_not_in_di_l(void);
519 static bool pmap_not_in_di_u(void);
520 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
523 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
527 pmap_not_in_di_l(void)
529 struct pmap_invl_gen *invl_gen;
531 invl_gen = &curthread->td_md.md_invl_gen;
532 return (invl_gen->gen == 0);
536 pmap_thread_init_invl_gen_l(struct thread *td)
538 struct pmap_invl_gen *invl_gen;
540 invl_gen = &td->td_md.md_invl_gen;
545 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
547 struct turnstile *ts;
549 ts = turnstile_trywait(&invl_gen_ts);
550 if (*m_gen > atomic_load_long(invl_gen))
551 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
553 turnstile_cancel(ts);
557 pmap_delayed_invl_finish_unblock(u_long new_gen)
559 struct turnstile *ts;
561 turnstile_chain_lock(&invl_gen_ts);
562 ts = turnstile_lookup(&invl_gen_ts);
564 pmap_invl_gen = new_gen;
566 turnstile_broadcast(ts, TS_SHARED_QUEUE);
567 turnstile_unpend(ts);
569 turnstile_chain_unlock(&invl_gen_ts);
573 * Start a new Delayed Invalidation (DI) block of code, executed by
574 * the current thread. Within a DI block, the current thread may
575 * destroy both the page table and PV list entries for a mapping and
576 * then release the corresponding PV list lock before ensuring that
577 * the mapping is flushed from the TLBs of any processors with the
581 pmap_delayed_invl_start_l(void)
583 struct pmap_invl_gen *invl_gen;
586 invl_gen = &curthread->td_md.md_invl_gen;
587 PMAP_ASSERT_NOT_IN_DI();
588 mtx_lock(&invl_gen_mtx);
589 if (LIST_EMPTY(&pmap_invl_gen_tracker))
590 currgen = pmap_invl_gen;
592 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
593 invl_gen->gen = currgen + 1;
594 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
595 mtx_unlock(&invl_gen_mtx);
599 * Finish the DI block, previously started by the current thread. All
600 * required TLB flushes for the pages marked by
601 * pmap_delayed_invl_page() must be finished before this function is
604 * This function works by bumping the global DI generation number to
605 * the generation number of the current thread's DI, unless there is a
606 * pending DI that started earlier. In the latter case, bumping the
607 * global DI generation number would incorrectly signal that the
608 * earlier DI had finished. Instead, this function bumps the earlier
609 * DI's generation number to match the generation number of the
610 * current thread's DI.
613 pmap_delayed_invl_finish_l(void)
615 struct pmap_invl_gen *invl_gen, *next;
617 invl_gen = &curthread->td_md.md_invl_gen;
618 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
619 mtx_lock(&invl_gen_mtx);
620 next = LIST_NEXT(invl_gen, link);
622 pmap_delayed_invl_finish_unblock(invl_gen->gen);
624 next->gen = invl_gen->gen;
625 LIST_REMOVE(invl_gen, link);
626 mtx_unlock(&invl_gen_mtx);
631 pmap_not_in_di_u(void)
633 struct pmap_invl_gen *invl_gen;
635 invl_gen = &curthread->td_md.md_invl_gen;
636 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
640 pmap_thread_init_invl_gen_u(struct thread *td)
642 struct pmap_invl_gen *invl_gen;
644 invl_gen = &td->td_md.md_invl_gen;
646 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
650 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
652 uint64_t new_high, new_low, old_high, old_low;
655 old_low = new_low = 0;
656 old_high = new_high = (uintptr_t)0;
658 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
659 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
660 : "b"(new_low), "c" (new_high)
663 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
666 out->next = (void *)old_high;
669 out->next = (void *)new_high;
675 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
676 struct pmap_invl_gen *new_val)
678 uint64_t new_high, new_low, old_high, old_low;
681 new_low = new_val->gen;
682 new_high = (uintptr_t)new_val->next;
683 old_low = old_val->gen;
684 old_high = (uintptr_t)old_val->next;
686 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
687 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
688 : "b"(new_low), "c" (new_high)
694 static long invl_start_restart;
695 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
696 &invl_start_restart, 0,
698 static long invl_finish_restart;
699 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
700 &invl_finish_restart, 0,
702 static int invl_max_qlen;
703 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
708 static struct lock_delay_config __read_frequently di_delay;
709 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
712 pmap_delayed_invl_start_u(void)
714 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
716 struct lock_delay_arg lda;
724 invl_gen = &td->td_md.md_invl_gen;
725 PMAP_ASSERT_NOT_IN_DI();
726 lock_delay_arg_init(&lda, &di_delay);
727 invl_gen->saved_pri = 0;
728 pri = td->td_base_pri;
731 pri = td->td_base_pri;
733 invl_gen->saved_pri = pri;
740 for (p = &pmap_invl_gen_head;; p = prev.next) {
742 prevl = atomic_load_ptr(&p->next);
743 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
744 PV_STAT(atomic_add_long(&invl_start_restart, 1));
750 prev.next = (void *)prevl;
753 if ((ii = invl_max_qlen) < i)
754 atomic_cmpset_int(&invl_max_qlen, ii, i);
757 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
758 PV_STAT(atomic_add_long(&invl_start_restart, 1));
763 new_prev.gen = prev.gen;
764 new_prev.next = invl_gen;
765 invl_gen->gen = prev.gen + 1;
767 /* Formal fence between store to invl->gen and updating *p. */
768 atomic_thread_fence_rel();
771 * After inserting an invl_gen element with invalid bit set,
772 * this thread blocks any other thread trying to enter the
773 * delayed invalidation block. Do not allow to remove us from
774 * the CPU, because it causes starvation for other threads.
779 * ABA for *p is not possible there, since p->gen can only
780 * increase. So if the *p thread finished its di, then
781 * started a new one and got inserted into the list at the
782 * same place, its gen will appear greater than the previously
785 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
787 PV_STAT(atomic_add_long(&invl_start_restart, 1));
793 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
794 * invl_gen->next, allowing other threads to iterate past us.
795 * pmap_di_store_invl() provides fence between the generation
796 * write and the update of next.
798 invl_gen->next = NULL;
803 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
804 struct pmap_invl_gen *p)
806 struct pmap_invl_gen prev, new_prev;
810 * Load invl_gen->gen after setting invl_gen->next
811 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
812 * generations to propagate to our invl_gen->gen. Lock prefix
813 * in atomic_set_ptr() worked as seq_cst fence.
815 mygen = atomic_load_long(&invl_gen->gen);
817 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
820 KASSERT(prev.gen < mygen,
821 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
822 new_prev.gen = mygen;
823 new_prev.next = (void *)((uintptr_t)invl_gen->next &
824 ~PMAP_INVL_GEN_NEXT_INVALID);
826 /* Formal fence between load of prev and storing update to it. */
827 atomic_thread_fence_rel();
829 return (pmap_di_store_invl(p, &prev, &new_prev));
833 pmap_delayed_invl_finish_u(void)
835 struct pmap_invl_gen *invl_gen, *p;
837 struct lock_delay_arg lda;
841 invl_gen = &td->td_md.md_invl_gen;
842 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
843 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
844 ("missed invl_start: INVALID"));
845 lock_delay_arg_init(&lda, &di_delay);
848 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
849 prevl = atomic_load_ptr(&p->next);
850 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
851 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
855 if ((void *)prevl == invl_gen)
860 * It is legitimate to not find ourself on the list if a
861 * thread before us finished its DI and started it again.
863 if (__predict_false(p == NULL)) {
864 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
870 atomic_set_ptr((uintptr_t *)&invl_gen->next,
871 PMAP_INVL_GEN_NEXT_INVALID);
872 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
873 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
874 PMAP_INVL_GEN_NEXT_INVALID);
876 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
881 if (atomic_load_int(&pmap_invl_waiters) > 0)
882 pmap_delayed_invl_finish_unblock(0);
883 if (invl_gen->saved_pri != 0) {
885 sched_prio(td, invl_gen->saved_pri);
891 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
893 struct pmap_invl_gen *p, *pn;
898 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
900 nextl = atomic_load_ptr(&p->next);
901 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
902 td = first ? NULL : __containerof(p, struct thread,
904 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
905 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
906 td != NULL ? td->td_tid : -1);
912 static long invl_wait;
913 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
914 "Number of times DI invalidation blocked pmap_remove_all/write");
915 static long invl_wait_slow;
916 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
917 "Number of slow invalidation waits for lockless DI");
921 pmap_delayed_invl_genp(vm_page_t m)
924 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
928 pmap_delayed_invl_callout_func(void *arg __unused)
931 if (atomic_load_int(&pmap_invl_waiters) == 0)
933 pmap_delayed_invl_finish_unblock(0);
937 pmap_delayed_invl_callout_init(void *arg __unused)
940 if (pmap_di_locked())
942 callout_init(&pmap_invl_callout, 1);
943 pmap_invl_callout_inited = true;
945 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
946 pmap_delayed_invl_callout_init, NULL);
949 * Ensure that all currently executing DI blocks, that need to flush
950 * TLB for the given page m, actually flushed the TLB at the time the
951 * function returned. If the page m has an empty PV list and we call
952 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
953 * valid mapping for the page m in either its page table or TLB.
955 * This function works by blocking until the global DI generation
956 * number catches up with the generation number associated with the
957 * given page m and its PV list. Since this function's callers
958 * typically own an object lock and sometimes own a page lock, it
959 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
963 pmap_delayed_invl_wait_l(vm_page_t m)
967 bool accounted = false;
970 m_gen = pmap_delayed_invl_genp(m);
971 while (*m_gen > pmap_invl_gen) {
974 atomic_add_long(&invl_wait, 1);
978 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
983 pmap_delayed_invl_wait_u(vm_page_t m)
986 struct lock_delay_arg lda;
990 m_gen = pmap_delayed_invl_genp(m);
991 lock_delay_arg_init(&lda, &di_delay);
992 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
993 if (fast || !pmap_invl_callout_inited) {
994 PV_STAT(atomic_add_long(&invl_wait, 1));
999 * The page's invalidation generation number
1000 * is still below the current thread's number.
1001 * Prepare to block so that we do not waste
1002 * CPU cycles or worse, suffer livelock.
1004 * Since it is impossible to block without
1005 * racing with pmap_delayed_invl_finish_u(),
1006 * prepare for the race by incrementing
1007 * pmap_invl_waiters and arming a 1-tick
1008 * callout which will unblock us if we lose
1011 atomic_add_int(&pmap_invl_waiters, 1);
1014 * Re-check the current thread's invalidation
1015 * generation after incrementing
1016 * pmap_invl_waiters, so that there is no race
1017 * with pmap_delayed_invl_finish_u() setting
1018 * the page generation and checking
1019 * pmap_invl_waiters. The only race allowed
1020 * is for a missed unblock, which is handled
1024 atomic_load_long(&pmap_invl_gen_head.gen)) {
1025 callout_reset(&pmap_invl_callout, 1,
1026 pmap_delayed_invl_callout_func, NULL);
1027 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1028 pmap_delayed_invl_wait_block(m_gen,
1029 &pmap_invl_gen_head.gen);
1031 atomic_add_int(&pmap_invl_waiters, -1);
1036 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1039 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1040 pmap_thread_init_invl_gen_u);
1043 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1046 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1047 pmap_delayed_invl_start_u);
1050 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1053 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1054 pmap_delayed_invl_finish_u);
1057 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1060 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1061 pmap_delayed_invl_wait_u);
1065 * Mark the page m's PV list as participating in the current thread's
1066 * DI block. Any threads concurrently using m's PV list to remove or
1067 * restrict all mappings to m will wait for the current thread's DI
1068 * block to complete before proceeding.
1070 * The function works by setting the DI generation number for m's PV
1071 * list to at least the DI generation number of the current thread.
1072 * This forces a caller of pmap_delayed_invl_wait() to block until
1073 * current thread calls pmap_delayed_invl_finish().
1076 pmap_delayed_invl_page(vm_page_t m)
1080 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1081 gen = curthread->td_md.md_invl_gen.gen;
1084 m_gen = pmap_delayed_invl_genp(m);
1092 static caddr_t crashdumpmap;
1095 * Internal flags for pmap_enter()'s helper functions.
1097 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1098 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1101 * Internal flags for pmap_mapdev_internal() and
1102 * pmap_change_attr_locked().
1104 #define MAPDEV_FLUSHCACHE 0x0000001 /* Flush cache after mapping. */
1105 #define MAPDEV_SETATTR 0x0000002 /* Modify existing attrs. */
1107 static void free_pv_chunk(struct pv_chunk *pc);
1108 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1109 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1110 static int popcnt_pc_map_pq(uint64_t *map);
1111 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1112 static void reserve_pv_entries(pmap_t pmap, int needed,
1113 struct rwlock **lockp);
1114 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1115 struct rwlock **lockp);
1116 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1117 u_int flags, struct rwlock **lockp);
1118 #if VM_NRESERVLEVEL > 0
1119 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1120 struct rwlock **lockp);
1122 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1123 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1126 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
1128 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1129 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1130 vm_offset_t va, struct rwlock **lockp);
1131 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1133 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1134 vm_prot_t prot, struct rwlock **lockp);
1135 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1136 u_int flags, vm_page_t m, struct rwlock **lockp);
1137 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1138 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1139 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1140 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1141 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1143 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1145 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1147 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1148 static vm_page_t pmap_large_map_getptp_unlocked(void);
1149 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1150 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
1151 #if VM_NRESERVLEVEL > 0
1152 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1153 struct rwlock **lockp);
1155 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1157 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
1158 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1160 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1161 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1162 static void pmap_pti_wire_pte(void *pte);
1163 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1164 struct spglist *free, struct rwlock **lockp);
1165 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1166 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1167 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1168 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1169 struct spglist *free);
1170 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1171 pd_entry_t *pde, struct spglist *free,
1172 struct rwlock **lockp);
1173 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1174 vm_page_t m, struct rwlock **lockp);
1175 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1177 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1179 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1180 struct rwlock **lockp);
1181 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1182 struct rwlock **lockp);
1183 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1184 struct rwlock **lockp);
1186 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1187 struct spglist *free);
1188 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1190 /********************/
1191 /* Inline functions */
1192 /********************/
1194 /* Return a non-clipped PD index for a given VA */
1195 static __inline vm_pindex_t
1196 pmap_pde_pindex(vm_offset_t va)
1198 return (va >> PDRSHIFT);
1202 /* Return a pointer to the PML4 slot that corresponds to a VA */
1203 static __inline pml4_entry_t *
1204 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1207 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1210 /* Return a pointer to the PDP slot that corresponds to a VA */
1211 static __inline pdp_entry_t *
1212 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1216 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1217 return (&pdpe[pmap_pdpe_index(va)]);
1220 /* Return a pointer to the PDP slot that corresponds to a VA */
1221 static __inline pdp_entry_t *
1222 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1224 pml4_entry_t *pml4e;
1227 PG_V = pmap_valid_bit(pmap);
1228 pml4e = pmap_pml4e(pmap, va);
1229 if ((*pml4e & PG_V) == 0)
1231 return (pmap_pml4e_to_pdpe(pml4e, va));
1234 /* Return a pointer to the PD slot that corresponds to a VA */
1235 static __inline pd_entry_t *
1236 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1240 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1241 return (&pde[pmap_pde_index(va)]);
1244 /* Return a pointer to the PD slot that corresponds to a VA */
1245 static __inline pd_entry_t *
1246 pmap_pde(pmap_t pmap, vm_offset_t va)
1251 PG_V = pmap_valid_bit(pmap);
1252 pdpe = pmap_pdpe(pmap, va);
1253 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1255 return (pmap_pdpe_to_pde(pdpe, va));
1258 /* Return a pointer to the PT slot that corresponds to a VA */
1259 static __inline pt_entry_t *
1260 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1264 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1265 return (&pte[pmap_pte_index(va)]);
1268 /* Return a pointer to the PT slot that corresponds to a VA */
1269 static __inline pt_entry_t *
1270 pmap_pte(pmap_t pmap, vm_offset_t va)
1275 PG_V = pmap_valid_bit(pmap);
1276 pde = pmap_pde(pmap, va);
1277 if (pde == NULL || (*pde & PG_V) == 0)
1279 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1280 return ((pt_entry_t *)pde);
1281 return (pmap_pde_to_pte(pde, va));
1284 static __inline void
1285 pmap_resident_count_inc(pmap_t pmap, int count)
1288 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1289 pmap->pm_stats.resident_count += count;
1292 static __inline void
1293 pmap_resident_count_dec(pmap_t pmap, int count)
1296 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1297 KASSERT(pmap->pm_stats.resident_count >= count,
1298 ("pmap %p resident count underflow %ld %d", pmap,
1299 pmap->pm_stats.resident_count, count));
1300 pmap->pm_stats.resident_count -= count;
1303 PMAP_INLINE pt_entry_t *
1304 vtopte(vm_offset_t va)
1306 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1308 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1310 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1313 static __inline pd_entry_t *
1314 vtopde(vm_offset_t va)
1316 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1318 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1320 return (PDmap + ((va >> PDRSHIFT) & mask));
1324 allocpages(vm_paddr_t *firstaddr, int n)
1329 bzero((void *)ret, n * PAGE_SIZE);
1330 *firstaddr += n * PAGE_SIZE;
1334 CTASSERT(powerof2(NDMPML4E));
1336 /* number of kernel PDP slots */
1337 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1340 nkpt_init(vm_paddr_t addr)
1347 pt_pages = howmany(addr, 1 << PDRSHIFT);
1348 pt_pages += NKPDPE(pt_pages);
1351 * Add some slop beyond the bare minimum required for bootstrapping
1354 * This is quite important when allocating KVA for kernel modules.
1355 * The modules are required to be linked in the negative 2GB of
1356 * the address space. If we run out of KVA in this region then
1357 * pmap_growkernel() will need to allocate page table pages to map
1358 * the entire 512GB of KVA space which is an unnecessary tax on
1361 * Secondly, device memory mapped as part of setting up the low-
1362 * level console(s) is taken from KVA, starting at virtual_avail.
1363 * This is because cninit() is called after pmap_bootstrap() but
1364 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1367 pt_pages += 32; /* 64MB additional slop. */
1373 * Returns the proper write/execute permission for a physical page that is
1374 * part of the initial boot allocations.
1376 * If the page has kernel text, it is marked as read-only. If the page has
1377 * kernel read-only data, it is marked as read-only/not-executable. If the
1378 * page has only read-write data, it is marked as read-write/not-executable.
1379 * If the page is below/above the kernel range, it is marked as read-write.
1381 * This function operates on 2M pages, since we map the kernel space that
1384 * Note that this doesn't currently provide any protection for modules.
1386 static inline pt_entry_t
1387 bootaddr_rwx(vm_paddr_t pa)
1391 * Everything in the same 2M page as the start of the kernel
1392 * should be static. On the other hand, things in the same 2M
1393 * page as the end of the kernel could be read-write/executable,
1394 * as the kernel image is not guaranteed to end on a 2M boundary.
1396 if (pa < trunc_2mpage(btext - KERNBASE) ||
1397 pa >= trunc_2mpage(_end - KERNBASE))
1400 * The linker should ensure that the read-only and read-write
1401 * portions don't share the same 2M page, so this shouldn't
1402 * impact read-only data. However, in any case, any page with
1403 * read-write data needs to be read-write.
1405 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1406 return (X86_PG_RW | pg_nx);
1408 * Mark any 2M page containing kernel text as read-only. Mark
1409 * other pages with read-only data as read-only and not executable.
1410 * (It is likely a small portion of the read-only data section will
1411 * be marked as read-only, but executable. This should be acceptable
1412 * since the read-only protection will keep the data from changing.)
1413 * Note that fixups to the .text section will still work until we
1416 if (pa < round_2mpage(etext - KERNBASE))
1422 create_pagetables(vm_paddr_t *firstaddr)
1424 int i, j, ndm1g, nkpdpe, nkdmpde;
1428 uint64_t DMPDkernphys;
1430 /* Allocate page table pages for the direct map */
1431 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1432 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1434 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1435 if (ndmpdpphys > NDMPML4E) {
1437 * Each NDMPML4E allows 512 GB, so limit to that,
1438 * and then readjust ndmpdp and ndmpdpphys.
1440 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1441 Maxmem = atop(NDMPML4E * NBPML4);
1442 ndmpdpphys = NDMPML4E;
1443 ndmpdp = NDMPML4E * NPDEPG;
1445 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1447 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1449 * Calculate the number of 1G pages that will fully fit in
1452 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1455 * Allocate 2M pages for the kernel. These will be used in
1456 * place of the first one or more 1G pages from ndm1g.
1458 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1459 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1462 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1463 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1465 /* Allocate pages */
1466 KPML4phys = allocpages(firstaddr, 1);
1467 KPDPphys = allocpages(firstaddr, NKPML4E);
1470 * Allocate the initial number of kernel page table pages required to
1471 * bootstrap. We defer this until after all memory-size dependent
1472 * allocations are done (e.g. direct map), so that we don't have to
1473 * build in too much slop in our estimate.
1475 * Note that when NKPML4E > 1, we have an empty page underneath
1476 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1477 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1479 nkpt_init(*firstaddr);
1480 nkpdpe = NKPDPE(nkpt);
1482 KPTphys = allocpages(firstaddr, nkpt);
1483 KPDphys = allocpages(firstaddr, nkpdpe);
1486 * Connect the zero-filled PT pages to their PD entries. This
1487 * implicitly maps the PT pages at their correct locations within
1490 pd_p = (pd_entry_t *)KPDphys;
1491 for (i = 0; i < nkpt; i++)
1492 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1495 * Map from physical address zero to the end of loader preallocated
1496 * memory using 2MB pages. This replaces some of the PD entries
1499 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1500 /* Preset PG_M and PG_A because demotion expects it. */
1501 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1502 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1505 * Because we map the physical blocks in 2M pages, adjust firstaddr
1506 * to record the physical blocks we've actually mapped into kernel
1507 * virtual address space.
1509 if (*firstaddr < round_2mpage(KERNend))
1510 *firstaddr = round_2mpage(KERNend);
1512 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1513 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1514 for (i = 0; i < nkpdpe; i++)
1515 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1518 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1519 * the end of physical memory is not aligned to a 1GB page boundary,
1520 * then the residual physical memory is mapped with 2MB pages. Later,
1521 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1522 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1523 * that are partially used.
1525 pd_p = (pd_entry_t *)DMPDphys;
1526 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1527 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1528 /* Preset PG_M and PG_A because demotion expects it. */
1529 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1530 X86_PG_M | X86_PG_A | pg_nx;
1532 pdp_p = (pdp_entry_t *)DMPDPphys;
1533 for (i = 0; i < ndm1g; i++) {
1534 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1535 /* Preset PG_M and PG_A because demotion expects it. */
1536 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1537 X86_PG_M | X86_PG_A | pg_nx;
1539 for (j = 0; i < ndmpdp; i++, j++) {
1540 pdp_p[i] = DMPDphys + ptoa(j);
1541 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1545 * Instead of using a 1G page for the memory containing the kernel,
1546 * use 2M pages with appropriate permissions. (If using 1G pages,
1547 * this will partially overwrite the PDPEs above.)
1550 pd_p = (pd_entry_t *)DMPDkernphys;
1551 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1552 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1553 X86_PG_M | X86_PG_A | pg_nx |
1554 bootaddr_rwx(i << PDRSHIFT);
1555 for (i = 0; i < nkdmpde; i++)
1556 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1560 /* And recursively map PML4 to itself in order to get PTmap */
1561 p4_p = (pml4_entry_t *)KPML4phys;
1562 p4_p[PML4PML4I] = KPML4phys;
1563 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1565 /* Connect the Direct Map slot(s) up to the PML4. */
1566 for (i = 0; i < ndmpdpphys; i++) {
1567 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1568 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1571 /* Connect the KVA slots up to the PML4 */
1572 for (i = 0; i < NKPML4E; i++) {
1573 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1574 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1579 * Bootstrap the system enough to run with virtual memory.
1581 * On amd64 this is called after mapping has already been enabled
1582 * and just syncs the pmap module with what has already been done.
1583 * [We can't call it easily with mapping off since the kernel is not
1584 * mapped with PA == VA, hence we would have to relocate every address
1585 * from the linked base (virtual) address "KERNBASE" to the actual
1586 * (physical) address starting relative to 0]
1589 pmap_bootstrap(vm_paddr_t *firstaddr)
1597 KERNend = *firstaddr;
1598 res = atop(KERNend - (vm_paddr_t)kernphys);
1604 * Create an initial set of page tables to run the kernel in.
1606 create_pagetables(firstaddr);
1609 * Add a physical memory segment (vm_phys_seg) corresponding to the
1610 * preallocated kernel page table pages so that vm_page structures
1611 * representing these pages will be created. The vm_page structures
1612 * are required for promotion of the corresponding kernel virtual
1613 * addresses to superpage mappings.
1615 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1618 * Account for the virtual addresses mapped by create_pagetables().
1620 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1621 virtual_end = VM_MAX_KERNEL_ADDRESS;
1624 * Enable PG_G global pages, then switch to the kernel page
1625 * table from the bootstrap page table. After the switch, it
1626 * is possible to enable SMEP and SMAP since PG_U bits are
1632 load_cr3(KPML4phys);
1633 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1635 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1640 * Initialize the kernel pmap (which is statically allocated).
1641 * Count bootstrap data as being resident in case any of this data is
1642 * later unmapped (using pmap_remove()) and freed.
1644 PMAP_LOCK_INIT(kernel_pmap);
1645 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1646 kernel_pmap->pm_cr3 = KPML4phys;
1647 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1648 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1649 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1650 kernel_pmap->pm_stats.resident_count = res;
1651 kernel_pmap->pm_flags = pmap_flags;
1654 * Initialize the TLB invalidations generation number lock.
1656 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1659 * Reserve some special page table entries/VA space for temporary
1662 #define SYSMAP(c, p, v, n) \
1663 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1669 * Crashdump maps. The first page is reused as CMAP1 for the
1672 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1673 CADDR1 = crashdumpmap;
1678 * Initialize the PAT MSR.
1679 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1680 * side-effect, invalidates stale PG_G TLB entries that might
1681 * have been created in our pre-boot environment.
1685 /* Initialize TLB Context Id. */
1686 if (pmap_pcid_enabled) {
1687 for (i = 0; i < MAXCPU; i++) {
1688 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1689 kernel_pmap->pm_pcids[i].pm_gen = 1;
1693 * PMAP_PCID_KERN + 1 is used for initialization of
1694 * proc0 pmap. The pmap' pcid state might be used by
1695 * EFIRT entry before first context switch, so it
1696 * needs to be valid.
1698 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1699 PCPU_SET(pcid_gen, 1);
1702 * pcpu area for APs is zeroed during AP startup.
1703 * pc_pcid_next and pc_pcid_gen are initialized by AP
1704 * during pcpu setup.
1706 load_cr4(rcr4() | CR4_PCIDE);
1711 * Setup the PAT MSR.
1720 /* Bail if this CPU doesn't implement PAT. */
1721 if ((cpu_feature & CPUID_PAT) == 0)
1724 /* Set default PAT index table. */
1725 for (i = 0; i < PAT_INDEX_SIZE; i++)
1727 pat_index[PAT_WRITE_BACK] = 0;
1728 pat_index[PAT_WRITE_THROUGH] = 1;
1729 pat_index[PAT_UNCACHEABLE] = 3;
1730 pat_index[PAT_WRITE_COMBINING] = 6;
1731 pat_index[PAT_WRITE_PROTECTED] = 5;
1732 pat_index[PAT_UNCACHED] = 2;
1735 * Initialize default PAT entries.
1736 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1737 * Program 5 and 6 as WP and WC.
1739 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1740 * mapping for a 2M page uses a PAT value with the bit 3 set due
1741 * to its overload with PG_PS.
1743 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1744 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1745 PAT_VALUE(2, PAT_UNCACHED) |
1746 PAT_VALUE(3, PAT_UNCACHEABLE) |
1747 PAT_VALUE(4, PAT_WRITE_BACK) |
1748 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1749 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1750 PAT_VALUE(7, PAT_UNCACHEABLE);
1754 load_cr4(cr4 & ~CR4_PGE);
1756 /* Disable caches (CD = 1, NW = 0). */
1758 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1760 /* Flushes caches and TLBs. */
1764 /* Update PAT and index table. */
1765 wrmsr(MSR_PAT, pat_msr);
1767 /* Flush caches and TLBs again. */
1771 /* Restore caches and PGE. */
1777 * Initialize a vm_page's machine-dependent fields.
1780 pmap_page_init(vm_page_t m)
1783 TAILQ_INIT(&m->md.pv_list);
1784 m->md.pat_mode = PAT_WRITE_BACK;
1788 * Initialize the pmap module.
1789 * Called by vm_init, to initialize any structures that the pmap
1790 * system needs to map virtual memory.
1795 struct pmap_preinit_mapping *ppim;
1798 int error, i, pv_npg, ret, skz63;
1800 /* L1TF, reserve page @0 unconditionally */
1801 vm_page_blacklist_add(0, bootverbose);
1803 /* Detect bare-metal Skylake Server and Skylake-X. */
1804 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1805 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1807 * Skylake-X errata SKZ63. Processor May Hang When
1808 * Executing Code In an HLE Transaction Region between
1809 * 40000000H and 403FFFFFH.
1811 * Mark the pages in the range as preallocated. It
1812 * seems to be impossible to distinguish between
1813 * Skylake Server and Skylake X.
1816 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1819 printf("SKZ63: skipping 4M RAM starting "
1820 "at physical 1G\n");
1821 for (i = 0; i < atop(0x400000); i++) {
1822 ret = vm_page_blacklist_add(0x40000000 +
1824 if (!ret && bootverbose)
1825 printf("page at %#lx already used\n",
1826 0x40000000 + ptoa(i));
1832 * Initialize the vm page array entries for the kernel pmap's
1835 PMAP_LOCK(kernel_pmap);
1836 for (i = 0; i < nkpt; i++) {
1837 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1838 KASSERT(mpte >= vm_page_array &&
1839 mpte < &vm_page_array[vm_page_array_size],
1840 ("pmap_init: page table page is out of range"));
1841 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1842 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1843 mpte->wire_count = 1;
1846 * Collect the page table pages that were replaced by a 2MB
1847 * page in create_pagetables(). They are zero filled.
1849 if (i << PDRSHIFT < KERNend &&
1850 pmap_insert_pt_page(kernel_pmap, mpte, false))
1851 panic("pmap_init: pmap_insert_pt_page failed");
1853 PMAP_UNLOCK(kernel_pmap);
1857 * If the kernel is running on a virtual machine, then it must assume
1858 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1859 * be prepared for the hypervisor changing the vendor and family that
1860 * are reported by CPUID. Consequently, the workaround for AMD Family
1861 * 10h Erratum 383 is enabled if the processor's feature set does not
1862 * include at least one feature that is only supported by older Intel
1863 * or newer AMD processors.
1865 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1866 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1867 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1869 workaround_erratum383 = 1;
1872 * Are large page mappings enabled?
1874 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1875 if (pg_ps_enabled) {
1876 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1877 ("pmap_init: can't assign to pagesizes[1]"));
1878 pagesizes[1] = NBPDR;
1882 * Initialize the pv chunk list mutex.
1884 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1887 * Initialize the pool of pv list locks.
1889 for (i = 0; i < NPV_LIST_LOCKS; i++)
1890 rw_init(&pv_list_locks[i], "pmap pv list");
1893 * Calculate the size of the pv head table for superpages.
1895 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1898 * Allocate memory for the pv head table for superpages.
1900 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1902 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1903 for (i = 0; i < pv_npg; i++)
1904 TAILQ_INIT(&pv_table[i].pv_list);
1905 TAILQ_INIT(&pv_dummy.pv_list);
1907 pmap_initialized = 1;
1908 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1909 ppim = pmap_preinit_mapping + i;
1912 /* Make the direct map consistent */
1913 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1914 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1915 ppim->sz, ppim->mode);
1919 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1920 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1923 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1924 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1925 (vmem_addr_t *)&qframe);
1927 panic("qframe allocation failed");
1930 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1931 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1932 lm_ents = LMEPML4I - LMSPML4I + 1;
1934 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1935 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1937 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1938 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1939 if (large_vmem == NULL) {
1940 printf("pmap: cannot create large map\n");
1943 for (i = 0; i < lm_ents; i++) {
1944 m = pmap_large_map_getptp_unlocked();
1945 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1946 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1952 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1953 "2MB page mapping counters");
1955 static u_long pmap_pde_demotions;
1956 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1957 &pmap_pde_demotions, 0, "2MB page demotions");
1959 static u_long pmap_pde_mappings;
1960 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1961 &pmap_pde_mappings, 0, "2MB page mappings");
1963 static u_long pmap_pde_p_failures;
1964 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1965 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1967 static u_long pmap_pde_promotions;
1968 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1969 &pmap_pde_promotions, 0, "2MB page promotions");
1971 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1972 "1GB page mapping counters");
1974 static u_long pmap_pdpe_demotions;
1975 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1976 &pmap_pdpe_demotions, 0, "1GB page demotions");
1978 /***************************************************
1979 * Low level helper routines.....
1980 ***************************************************/
1983 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1985 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1987 switch (pmap->pm_type) {
1990 /* Verify that both PAT bits are not set at the same time */
1991 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1992 ("Invalid PAT bits in entry %#lx", entry));
1994 /* Swap the PAT bits if one of them is set */
1995 if ((entry & x86_pat_bits) != 0)
1996 entry ^= x86_pat_bits;
2000 * Nothing to do - the memory attributes are represented
2001 * the same way for regular pages and superpages.
2005 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2012 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2015 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2016 pat_index[(int)mode] >= 0);
2020 * Determine the appropriate bits to set in a PTE or PDE for a specified
2024 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2026 int cache_bits, pat_flag, pat_idx;
2028 if (!pmap_is_valid_memattr(pmap, mode))
2029 panic("Unknown caching mode %d\n", mode);
2031 switch (pmap->pm_type) {
2034 /* The PAT bit is different for PTE's and PDE's. */
2035 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2037 /* Map the caching mode to a PAT index. */
2038 pat_idx = pat_index[mode];
2040 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2043 cache_bits |= pat_flag;
2045 cache_bits |= PG_NC_PCD;
2047 cache_bits |= PG_NC_PWT;
2051 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2055 panic("unsupported pmap type %d", pmap->pm_type);
2058 return (cache_bits);
2062 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2066 switch (pmap->pm_type) {
2069 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2072 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2075 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2082 pmap_ps_enabled(pmap_t pmap)
2085 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2089 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2092 switch (pmap->pm_type) {
2099 * This is a little bogus since the generation number is
2100 * supposed to be bumped up when a region of the address
2101 * space is invalidated in the page tables.
2103 * In this case the old PDE entry is valid but yet we want
2104 * to make sure that any mappings using the old entry are
2105 * invalidated in the TLB.
2107 * The reason this works as expected is because we rendezvous
2108 * "all" host cpus and force any vcpu context to exit as a
2111 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2114 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2116 pde_store(pde, newpde);
2120 * After changing the page size for the specified virtual address in the page
2121 * table, flush the corresponding entries from the processor's TLB. Only the
2122 * calling processor's TLB is affected.
2124 * The calling thread must be pinned to a processor.
2127 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2131 if (pmap_type_guest(pmap))
2134 KASSERT(pmap->pm_type == PT_X86,
2135 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2137 PG_G = pmap_global_bit(pmap);
2139 if ((newpde & PG_PS) == 0)
2140 /* Demotion: flush a specific 2MB page mapping. */
2142 else if ((newpde & PG_G) == 0)
2144 * Promotion: flush every 4KB page mapping from the TLB
2145 * because there are too many to flush individually.
2150 * Promotion: flush every 4KB page mapping from the TLB,
2151 * including any global (PG_G) mappings.
2159 * For SMP, these functions have to use the IPI mechanism for coherence.
2161 * N.B.: Before calling any of the following TLB invalidation functions,
2162 * the calling processor must ensure that all stores updating a non-
2163 * kernel page table are globally performed. Otherwise, another
2164 * processor could cache an old, pre-update entry without being
2165 * invalidated. This can happen one of two ways: (1) The pmap becomes
2166 * active on another processor after its pm_active field is checked by
2167 * one of the following functions but before a store updating the page
2168 * table is globally performed. (2) The pmap becomes active on another
2169 * processor before its pm_active field is checked but due to
2170 * speculative loads one of the following functions stills reads the
2171 * pmap as inactive on the other processor.
2173 * The kernel page table is exempt because its pm_active field is
2174 * immutable. The kernel page table is always active on every
2179 * Interrupt the cpus that are executing in the guest context.
2180 * This will force the vcpu to exit and the cached EPT mappings
2181 * will be invalidated by the host before the next vmresume.
2183 static __inline void
2184 pmap_invalidate_ept(pmap_t pmap)
2189 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2190 ("pmap_invalidate_ept: absurd pm_active"));
2193 * The TLB mappings associated with a vcpu context are not
2194 * flushed each time a different vcpu is chosen to execute.
2196 * This is in contrast with a process's vtop mappings that
2197 * are flushed from the TLB on each context switch.
2199 * Therefore we need to do more than just a TLB shootdown on
2200 * the active cpus in 'pmap->pm_active'. To do this we keep
2201 * track of the number of invalidations performed on this pmap.
2203 * Each vcpu keeps a cache of this counter and compares it
2204 * just before a vmresume. If the counter is out-of-date an
2205 * invept will be done to flush stale mappings from the TLB.
2207 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2210 * Force the vcpu to exit and trap back into the hypervisor.
2212 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2213 ipi_selected(pmap->pm_active, ipinum);
2218 pmap_invalidate_cpu_mask(pmap_t pmap)
2221 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2225 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2226 const bool invpcid_works1)
2228 struct invpcid_descr d;
2229 uint64_t kcr3, ucr3;
2233 cpuid = PCPU_GET(cpuid);
2234 if (pmap == PCPU_GET(curpmap)) {
2235 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2237 * Because pm_pcid is recalculated on a
2238 * context switch, we must disable switching.
2239 * Otherwise, we might use a stale value
2243 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2244 if (invpcid_works1) {
2245 d.pcid = pcid | PMAP_PCID_USER_PT;
2248 invpcid(&d, INVPCID_ADDR);
2250 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2251 ucr3 = pmap->pm_ucr3 | pcid |
2252 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2253 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2258 pmap->pm_pcids[cpuid].pm_gen = 0;
2262 pmap->pm_pcids[i].pm_gen = 0;
2266 * The fence is between stores to pm_gen and the read of the
2267 * pm_active mask. We need to ensure that it is impossible
2268 * for us to miss the bit update in pm_active and
2269 * simultaneously observe a non-zero pm_gen in
2270 * pmap_activate_sw(), otherwise TLB update is missed.
2271 * Without the fence, IA32 allows such an outcome. Note that
2272 * pm_active is updated by a locked operation, which provides
2273 * the reciprocal fence.
2275 atomic_thread_fence_seq_cst();
2279 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2282 pmap_invalidate_page_pcid(pmap, va, true);
2286 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2289 pmap_invalidate_page_pcid(pmap, va, false);
2293 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2297 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2300 if (pmap_pcid_enabled)
2301 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2302 pmap_invalidate_page_pcid_noinvpcid);
2303 return (pmap_invalidate_page_nopcid);
2307 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2310 if (pmap_type_guest(pmap)) {
2311 pmap_invalidate_ept(pmap);
2315 KASSERT(pmap->pm_type == PT_X86,
2316 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2319 if (pmap == kernel_pmap) {
2322 if (pmap == PCPU_GET(curpmap))
2324 pmap_invalidate_page_mode(pmap, va);
2326 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2330 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2331 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2334 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2335 const bool invpcid_works1)
2337 struct invpcid_descr d;
2338 uint64_t kcr3, ucr3;
2342 cpuid = PCPU_GET(cpuid);
2343 if (pmap == PCPU_GET(curpmap)) {
2344 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2346 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2347 if (invpcid_works1) {
2348 d.pcid = pcid | PMAP_PCID_USER_PT;
2351 for (; d.addr < eva; d.addr += PAGE_SIZE)
2352 invpcid(&d, INVPCID_ADDR);
2354 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2355 ucr3 = pmap->pm_ucr3 | pcid |
2356 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2357 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2362 pmap->pm_pcids[cpuid].pm_gen = 0;
2366 pmap->pm_pcids[i].pm_gen = 0;
2368 /* See the comment in pmap_invalidate_page_pcid(). */
2369 atomic_thread_fence_seq_cst();
2373 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2377 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2381 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2385 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2389 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2393 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2397 if (pmap_pcid_enabled)
2398 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2399 pmap_invalidate_range_pcid_noinvpcid);
2400 return (pmap_invalidate_range_nopcid);
2404 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2408 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2409 pmap_invalidate_all(pmap);
2413 if (pmap_type_guest(pmap)) {
2414 pmap_invalidate_ept(pmap);
2418 KASSERT(pmap->pm_type == PT_X86,
2419 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2422 if (pmap == kernel_pmap) {
2423 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2426 if (pmap == PCPU_GET(curpmap)) {
2427 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2430 pmap_invalidate_range_mode(pmap, sva, eva);
2432 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2437 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2439 struct invpcid_descr d;
2440 uint64_t kcr3, ucr3;
2444 if (pmap == kernel_pmap) {
2445 if (invpcid_works1) {
2446 bzero(&d, sizeof(d));
2447 invpcid(&d, INVPCID_CTXGLOB);
2452 cpuid = PCPU_GET(cpuid);
2453 if (pmap == PCPU_GET(curpmap)) {
2455 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2456 if (invpcid_works1) {
2460 invpcid(&d, INVPCID_CTX);
2461 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2462 d.pcid |= PMAP_PCID_USER_PT;
2463 invpcid(&d, INVPCID_CTX);
2466 kcr3 = pmap->pm_cr3 | pcid;
2467 ucr3 = pmap->pm_ucr3;
2468 if (ucr3 != PMAP_NO_CR3) {
2469 ucr3 |= pcid | PMAP_PCID_USER_PT;
2470 pmap_pti_pcid_invalidate(ucr3, kcr3);
2477 pmap->pm_pcids[cpuid].pm_gen = 0;
2480 pmap->pm_pcids[i].pm_gen = 0;
2483 /* See the comment in pmap_invalidate_page_pcid(). */
2484 atomic_thread_fence_seq_cst();
2488 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2491 pmap_invalidate_all_pcid(pmap, true);
2495 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2498 pmap_invalidate_all_pcid(pmap, false);
2502 pmap_invalidate_all_nopcid(pmap_t pmap)
2505 if (pmap == kernel_pmap)
2507 else if (pmap == PCPU_GET(curpmap))
2511 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2514 if (pmap_pcid_enabled)
2515 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2516 pmap_invalidate_all_pcid_noinvpcid);
2517 return (pmap_invalidate_all_nopcid);
2521 pmap_invalidate_all(pmap_t pmap)
2524 if (pmap_type_guest(pmap)) {
2525 pmap_invalidate_ept(pmap);
2529 KASSERT(pmap->pm_type == PT_X86,
2530 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2533 pmap_invalidate_all_mode(pmap);
2534 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2539 pmap_invalidate_cache(void)
2549 cpuset_t invalidate; /* processors that invalidate their TLB */
2554 u_int store; /* processor that updates the PDE */
2558 pmap_update_pde_action(void *arg)
2560 struct pde_action *act = arg;
2562 if (act->store == PCPU_GET(cpuid))
2563 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2567 pmap_update_pde_teardown(void *arg)
2569 struct pde_action *act = arg;
2571 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2572 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2576 * Change the page size for the specified virtual address in a way that
2577 * prevents any possibility of the TLB ever having two entries that map the
2578 * same virtual address using different page sizes. This is the recommended
2579 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2580 * machine check exception for a TLB state that is improperly diagnosed as a
2584 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2586 struct pde_action act;
2587 cpuset_t active, other_cpus;
2591 cpuid = PCPU_GET(cpuid);
2592 other_cpus = all_cpus;
2593 CPU_CLR(cpuid, &other_cpus);
2594 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2597 active = pmap->pm_active;
2599 if (CPU_OVERLAP(&active, &other_cpus)) {
2601 act.invalidate = active;
2605 act.newpde = newpde;
2606 CPU_SET(cpuid, &active);
2607 smp_rendezvous_cpus(active,
2608 smp_no_rendezvous_barrier, pmap_update_pde_action,
2609 pmap_update_pde_teardown, &act);
2611 pmap_update_pde_store(pmap, pde, newpde);
2612 if (CPU_ISSET(cpuid, &active))
2613 pmap_update_pde_invalidate(pmap, va, newpde);
2619 * Normal, non-SMP, invalidation functions.
2622 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2624 struct invpcid_descr d;
2625 uint64_t kcr3, ucr3;
2628 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2632 KASSERT(pmap->pm_type == PT_X86,
2633 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2635 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2637 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2638 pmap->pm_ucr3 != PMAP_NO_CR3) {
2640 pcid = pmap->pm_pcids[0].pm_pcid;
2641 if (invpcid_works) {
2642 d.pcid = pcid | PMAP_PCID_USER_PT;
2645 invpcid(&d, INVPCID_ADDR);
2647 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2648 ucr3 = pmap->pm_ucr3 | pcid |
2649 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2650 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2654 } else if (pmap_pcid_enabled)
2655 pmap->pm_pcids[0].pm_gen = 0;
2659 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2661 struct invpcid_descr d;
2663 uint64_t kcr3, ucr3;
2665 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2669 KASSERT(pmap->pm_type == PT_X86,
2670 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2672 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2673 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2675 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2676 pmap->pm_ucr3 != PMAP_NO_CR3) {
2678 if (invpcid_works) {
2679 d.pcid = pmap->pm_pcids[0].pm_pcid |
2683 for (; d.addr < eva; d.addr += PAGE_SIZE)
2684 invpcid(&d, INVPCID_ADDR);
2686 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2687 pm_pcid | CR3_PCID_SAVE;
2688 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2689 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2690 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2694 } else if (pmap_pcid_enabled) {
2695 pmap->pm_pcids[0].pm_gen = 0;
2700 pmap_invalidate_all(pmap_t pmap)
2702 struct invpcid_descr d;
2703 uint64_t kcr3, ucr3;
2705 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2709 KASSERT(pmap->pm_type == PT_X86,
2710 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2712 if (pmap == kernel_pmap) {
2713 if (pmap_pcid_enabled && invpcid_works) {
2714 bzero(&d, sizeof(d));
2715 invpcid(&d, INVPCID_CTXGLOB);
2719 } else if (pmap == PCPU_GET(curpmap)) {
2720 if (pmap_pcid_enabled) {
2722 if (invpcid_works) {
2723 d.pcid = pmap->pm_pcids[0].pm_pcid;
2726 invpcid(&d, INVPCID_CTX);
2727 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2728 d.pcid |= PMAP_PCID_USER_PT;
2729 invpcid(&d, INVPCID_CTX);
2732 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2733 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2734 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2735 0].pm_pcid | PMAP_PCID_USER_PT;
2736 pmap_pti_pcid_invalidate(ucr3, kcr3);
2744 } else if (pmap_pcid_enabled) {
2745 pmap->pm_pcids[0].pm_gen = 0;
2750 pmap_invalidate_cache(void)
2757 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2760 pmap_update_pde_store(pmap, pde, newpde);
2761 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2762 pmap_update_pde_invalidate(pmap, va, newpde);
2764 pmap->pm_pcids[0].pm_gen = 0;
2769 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2773 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2774 * by a promotion that did not invalidate the 512 4KB page mappings
2775 * that might exist in the TLB. Consequently, at this point, the TLB
2776 * may hold both 4KB and 2MB page mappings for the address range [va,
2777 * va + NBPDR). Therefore, the entire range must be invalidated here.
2778 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2779 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2780 * single INVLPG suffices to invalidate the 2MB page mapping from the
2783 if ((pde & PG_PROMOTED) != 0)
2784 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2786 pmap_invalidate_page(pmap, va);
2789 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2790 (vm_offset_t sva, vm_offset_t eva))
2793 if ((cpu_feature & CPUID_SS) != 0)
2794 return (pmap_invalidate_cache_range_selfsnoop);
2795 if ((cpu_feature & CPUID_CLFSH) != 0)
2796 return (pmap_force_invalidate_cache_range);
2797 return (pmap_invalidate_cache_range_all);
2800 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2803 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2806 KASSERT((sva & PAGE_MASK) == 0,
2807 ("pmap_invalidate_cache_range: sva not page-aligned"));
2808 KASSERT((eva & PAGE_MASK) == 0,
2809 ("pmap_invalidate_cache_range: eva not page-aligned"));
2813 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2816 pmap_invalidate_cache_range_check_align(sva, eva);
2820 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2823 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2826 * XXX: Some CPUs fault, hang, or trash the local APIC
2827 * registers if we use CLFLUSH on the local APIC range. The
2828 * local APIC is always uncached, so we don't need to flush
2829 * for that range anyway.
2831 if (pmap_kextract(sva) == lapic_paddr)
2834 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2836 * Do per-cache line flush. Use the sfence
2837 * instruction to insure that previous stores are
2838 * included in the write-back. The processor
2839 * propagates flush to other processors in the cache
2843 for (; sva < eva; sva += cpu_clflush_line_size)
2848 * Writes are ordered by CLFLUSH on Intel CPUs.
2850 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2852 for (; sva < eva; sva += cpu_clflush_line_size)
2854 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2860 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2863 pmap_invalidate_cache_range_check_align(sva, eva);
2864 pmap_invalidate_cache();
2868 * Remove the specified set of pages from the data and instruction caches.
2870 * In contrast to pmap_invalidate_cache_range(), this function does not
2871 * rely on the CPU's self-snoop feature, because it is intended for use
2872 * when moving pages into a different cache domain.
2875 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2877 vm_offset_t daddr, eva;
2881 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2882 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2883 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2884 pmap_invalidate_cache();
2888 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2890 for (i = 0; i < count; i++) {
2891 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2892 eva = daddr + PAGE_SIZE;
2893 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2902 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2908 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2911 pmap_invalidate_cache_range_check_align(sva, eva);
2913 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2914 pmap_force_invalidate_cache_range(sva, eva);
2918 /* See comment in pmap_force_invalidate_cache_range(). */
2919 if (pmap_kextract(sva) == lapic_paddr)
2923 for (; sva < eva; sva += cpu_clflush_line_size)
2929 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2933 int error, pte_bits;
2935 KASSERT((spa & PAGE_MASK) == 0,
2936 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2937 KASSERT((epa & PAGE_MASK) == 0,
2938 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2940 if (spa < dmaplimit) {
2941 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2943 if (dmaplimit >= epa)
2948 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
2950 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2952 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
2953 pte = vtopte(vaddr);
2954 for (; spa < epa; spa += PAGE_SIZE) {
2956 pte_store(pte, spa | pte_bits);
2958 /* XXXKIB sfences inside flush_cache_range are excessive */
2959 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
2962 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
2966 * Routine: pmap_extract
2968 * Extract the physical page address associated
2969 * with the given map/virtual_address pair.
2972 pmap_extract(pmap_t pmap, vm_offset_t va)
2976 pt_entry_t *pte, PG_V;
2980 PG_V = pmap_valid_bit(pmap);
2982 pdpe = pmap_pdpe(pmap, va);
2983 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2984 if ((*pdpe & PG_PS) != 0)
2985 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2987 pde = pmap_pdpe_to_pde(pdpe, va);
2988 if ((*pde & PG_V) != 0) {
2989 if ((*pde & PG_PS) != 0) {
2990 pa = (*pde & PG_PS_FRAME) |
2993 pte = pmap_pde_to_pte(pde, va);
2994 pa = (*pte & PG_FRAME) |
3005 * Routine: pmap_extract_and_hold
3007 * Atomically extract and hold the physical page
3008 * with the given pmap and virtual address pair
3009 * if that mapping permits the given protection.
3012 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3014 pd_entry_t pde, *pdep;
3015 pt_entry_t pte, PG_RW, PG_V;
3021 PG_RW = pmap_rw_bit(pmap);
3022 PG_V = pmap_valid_bit(pmap);
3025 pdep = pmap_pde(pmap, va);
3026 if (pdep != NULL && (pde = *pdep)) {
3028 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
3029 if (vm_page_pa_tryrelock(pmap, (pde &
3030 PG_PS_FRAME) | (va & PDRMASK), &pa))
3032 m = PHYS_TO_VM_PAGE(pa);
3035 pte = *pmap_pde_to_pte(pdep, va);
3037 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
3038 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
3041 m = PHYS_TO_VM_PAGE(pa);
3053 pmap_kextract(vm_offset_t va)
3058 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3059 pa = DMAP_TO_PHYS(va);
3060 } else if (LARGEMAP_MIN_ADDRESS <= va &&
3061 va < PMAP_LARGEMAP_MAX_ADDRESS()) {
3062 pa = pmap_large_map_kextract(va);
3066 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3069 * Beware of a concurrent promotion that changes the
3070 * PDE at this point! For example, vtopte() must not
3071 * be used to access the PTE because it would use the
3072 * new PDE. It is, however, safe to use the old PDE
3073 * because the page table page is preserved by the
3076 pa = *pmap_pde_to_pte(&pde, va);
3077 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3083 /***************************************************
3084 * Low level mapping routines.....
3085 ***************************************************/
3088 * Add a wired page to the kva.
3089 * Note: not SMP coherent.
3092 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3097 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
3100 static __inline void
3101 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3107 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3108 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
3112 * Remove a page from the kernel pagetables.
3113 * Note: not SMP coherent.
3116 pmap_kremove(vm_offset_t va)
3125 * Used to map a range of physical addresses into kernel
3126 * virtual address space.
3128 * The value passed in '*virt' is a suggested virtual address for
3129 * the mapping. Architectures which can support a direct-mapped
3130 * physical to virtual region can return the appropriate address
3131 * within that region, leaving '*virt' unchanged. Other
3132 * architectures should map the pages starting at '*virt' and
3133 * update '*virt' with the first usable address after the mapped
3137 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3139 return PHYS_TO_DMAP(start);
3144 * Add a list of wired pages to the kva
3145 * this routine is only used for temporary
3146 * kernel mappings that do not need to have
3147 * page modification or references recorded.
3148 * Note that old mappings are simply written
3149 * over. The page *must* be wired.
3150 * Note: SMP coherent. Uses a ranged shootdown IPI.
3153 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3155 pt_entry_t *endpte, oldpte, pa, *pte;
3161 endpte = pte + count;
3162 while (pte < endpte) {
3164 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3165 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3166 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3168 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3172 if (__predict_false((oldpte & X86_PG_V) != 0))
3173 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3178 * This routine tears out page mappings from the
3179 * kernel -- it is meant only for temporary mappings.
3180 * Note: SMP coherent. Uses a ranged shootdown IPI.
3183 pmap_qremove(vm_offset_t sva, int count)
3188 while (count-- > 0) {
3189 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3193 pmap_invalidate_range(kernel_pmap, sva, va);
3196 /***************************************************
3197 * Page table page management routines.....
3198 ***************************************************/
3200 * Schedule the specified unused page table page to be freed. Specifically,
3201 * add the page to the specified list of pages that will be released to the
3202 * physical memory manager after the TLB has been updated.
3204 static __inline void
3205 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3206 boolean_t set_PG_ZERO)
3210 m->flags |= PG_ZERO;
3212 m->flags &= ~PG_ZERO;
3213 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3217 * Inserts the specified page table page into the specified pmap's collection
3218 * of idle page table pages. Each of a pmap's page table pages is responsible
3219 * for mapping a distinct range of virtual addresses. The pmap's collection is
3220 * ordered by this virtual address range.
3222 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3225 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3228 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3229 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3230 return (vm_radix_insert(&pmap->pm_root, mpte));
3234 * Removes the page table page mapping the specified virtual address from the
3235 * specified pmap's collection of idle page table pages, and returns it.
3236 * Otherwise, returns NULL if there is no page table page corresponding to the
3237 * specified virtual address.
3239 static __inline vm_page_t
3240 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3243 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3244 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3248 * Decrements a page table page's wire count, which is used to record the
3249 * number of valid page table entries within the page. If the wire count
3250 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3251 * page table page was unmapped and FALSE otherwise.
3253 static inline boolean_t
3254 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3258 if (m->wire_count == 0) {
3259 _pmap_unwire_ptp(pmap, va, m, free);
3266 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3269 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3271 * unmap the page table page
3273 if (m->pindex >= (NUPDE + NUPDPE)) {
3276 pml4 = pmap_pml4e(pmap, va);
3278 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3279 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3282 } else if (m->pindex >= NUPDE) {
3285 pdp = pmap_pdpe(pmap, va);
3290 pd = pmap_pde(pmap, va);
3293 pmap_resident_count_dec(pmap, 1);
3294 if (m->pindex < NUPDE) {
3295 /* We just released a PT, unhold the matching PD */
3298 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3299 pmap_unwire_ptp(pmap, va, pdpg, free);
3301 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3302 /* We just released a PD, unhold the matching PDP */
3305 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3306 pmap_unwire_ptp(pmap, va, pdppg, free);
3310 * Put page on a list so that it is released after
3311 * *ALL* TLB shootdown is done
3313 pmap_add_delayed_free_list(m, free, TRUE);
3317 * After removing a page table entry, this routine is used to
3318 * conditionally free the page, and manage the hold/wire counts.
3321 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3322 struct spglist *free)
3326 if (va >= VM_MAXUSER_ADDRESS)
3328 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3329 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3330 return (pmap_unwire_ptp(pmap, va, mpte, free));
3334 pmap_pinit0(pmap_t pmap)
3340 PMAP_LOCK_INIT(pmap);
3341 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3342 pmap->pm_pml4u = NULL;
3343 pmap->pm_cr3 = KPML4phys;
3344 /* hack to keep pmap_pti_pcid_invalidate() alive */
3345 pmap->pm_ucr3 = PMAP_NO_CR3;
3346 pmap->pm_root.rt_root = 0;
3347 CPU_ZERO(&pmap->pm_active);
3348 TAILQ_INIT(&pmap->pm_pvchunk);
3349 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3350 pmap->pm_flags = pmap_flags;
3352 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3353 pmap->pm_pcids[i].pm_gen = 1;
3355 pmap_activate_boot(pmap);
3360 p->p_md.md_flags |= P_MD_KPTI;
3363 pmap_thread_init_invl_gen(td);
3365 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3366 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3367 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3373 pmap_pinit_pml4(vm_page_t pml4pg)
3375 pml4_entry_t *pm_pml4;
3378 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3380 /* Wire in kernel global address entries. */
3381 for (i = 0; i < NKPML4E; i++) {
3382 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3385 for (i = 0; i < ndmpdpphys; i++) {
3386 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3390 /* install self-referential address mapping entry(s) */
3391 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3392 X86_PG_A | X86_PG_M;
3394 /* install large map entries if configured */
3395 for (i = 0; i < lm_ents; i++)
3396 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3400 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3402 pml4_entry_t *pm_pml4;
3405 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3406 for (i = 0; i < NPML4EPG; i++)
3407 pm_pml4[i] = pti_pml4[i];
3411 * Initialize a preallocated and zeroed pmap structure,
3412 * such as one in a vmspace structure.
3415 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3417 vm_page_t pml4pg, pml4pgu;
3418 vm_paddr_t pml4phys;
3422 * allocate the page directory page
3424 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3425 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3427 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3428 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3430 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3431 pmap->pm_pcids[i].pm_gen = 0;
3433 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3434 pmap->pm_ucr3 = PMAP_NO_CR3;
3435 pmap->pm_pml4u = NULL;
3437 pmap->pm_type = pm_type;
3438 if ((pml4pg->flags & PG_ZERO) == 0)
3439 pagezero(pmap->pm_pml4);
3442 * Do not install the host kernel mappings in the nested page
3443 * tables. These mappings are meaningless in the guest physical
3445 * Install minimal kernel mappings in PTI case.
3447 if (pm_type == PT_X86) {
3448 pmap->pm_cr3 = pml4phys;
3449 pmap_pinit_pml4(pml4pg);
3450 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3451 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3452 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3453 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3454 VM_PAGE_TO_PHYS(pml4pgu));
3455 pmap_pinit_pml4_pti(pml4pgu);
3456 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3458 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3459 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3460 pkru_free_range, pmap, M_NOWAIT);
3464 pmap->pm_root.rt_root = 0;
3465 CPU_ZERO(&pmap->pm_active);
3466 TAILQ_INIT(&pmap->pm_pvchunk);
3467 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3468 pmap->pm_flags = flags;
3469 pmap->pm_eptgen = 0;
3475 pmap_pinit(pmap_t pmap)
3478 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3482 * This routine is called if the desired page table page does not exist.
3484 * If page table page allocation fails, this routine may sleep before
3485 * returning NULL. It sleeps only if a lock pointer was given.
3487 * Note: If a page allocation fails at page table level two or three,
3488 * one or two pages may be held during the wait, only to be released
3489 * afterwards. This conservative approach is easily argued to avoid
3493 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3495 vm_page_t m, pdppg, pdpg;
3496 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3498 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3500 PG_A = pmap_accessed_bit(pmap);
3501 PG_M = pmap_modified_bit(pmap);
3502 PG_V = pmap_valid_bit(pmap);
3503 PG_RW = pmap_rw_bit(pmap);
3506 * Allocate a page table page.
3508 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3509 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3510 if (lockp != NULL) {
3511 RELEASE_PV_LIST_LOCK(lockp);
3513 PMAP_ASSERT_NOT_IN_DI();
3519 * Indicate the need to retry. While waiting, the page table
3520 * page may have been allocated.
3524 if ((m->flags & PG_ZERO) == 0)
3528 * Map the pagetable page into the process address space, if
3529 * it isn't already there.
3532 if (ptepindex >= (NUPDE + NUPDPE)) {
3533 pml4_entry_t *pml4, *pml4u;
3534 vm_pindex_t pml4index;
3536 /* Wire up a new PDPE page */
3537 pml4index = ptepindex - (NUPDE + NUPDPE);
3538 pml4 = &pmap->pm_pml4[pml4index];
3539 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3540 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3542 * PTI: Make all user-space mappings in the
3543 * kernel-mode page table no-execute so that
3544 * we detect any programming errors that leave
3545 * the kernel-mode page table active on return
3548 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3551 pml4u = &pmap->pm_pml4u[pml4index];
3552 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3556 } else if (ptepindex >= NUPDE) {
3557 vm_pindex_t pml4index;
3558 vm_pindex_t pdpindex;
3562 /* Wire up a new PDE page */
3563 pdpindex = ptepindex - NUPDE;
3564 pml4index = pdpindex >> NPML4EPGSHIFT;
3566 pml4 = &pmap->pm_pml4[pml4index];
3567 if ((*pml4 & PG_V) == 0) {
3568 /* Have to allocate a new pdp, recurse */
3569 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3571 vm_page_unwire_noq(m);
3572 vm_page_free_zero(m);
3576 /* Add reference to pdp page */
3577 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3578 pdppg->wire_count++;
3580 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3582 /* Now find the pdp page */
3583 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3584 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3587 vm_pindex_t pml4index;
3588 vm_pindex_t pdpindex;
3593 /* Wire up a new PTE page */
3594 pdpindex = ptepindex >> NPDPEPGSHIFT;
3595 pml4index = pdpindex >> NPML4EPGSHIFT;
3597 /* First, find the pdp and check that its valid. */
3598 pml4 = &pmap->pm_pml4[pml4index];
3599 if ((*pml4 & PG_V) == 0) {
3600 /* Have to allocate a new pd, recurse */
3601 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3603 vm_page_unwire_noq(m);
3604 vm_page_free_zero(m);
3607 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3608 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3610 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3611 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3612 if ((*pdp & PG_V) == 0) {
3613 /* Have to allocate a new pd, recurse */
3614 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3616 vm_page_unwire_noq(m);
3617 vm_page_free_zero(m);
3621 /* Add reference to the pd page */
3622 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3626 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3628 /* Now we know where the page directory page is */
3629 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3630 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3633 pmap_resident_count_inc(pmap, 1);
3639 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3641 vm_pindex_t pdpindex, ptepindex;
3642 pdp_entry_t *pdpe, PG_V;
3645 PG_V = pmap_valid_bit(pmap);
3648 pdpe = pmap_pdpe(pmap, va);
3649 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3650 /* Add a reference to the pd page. */
3651 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3654 /* Allocate a pd page. */
3655 ptepindex = pmap_pde_pindex(va);
3656 pdpindex = ptepindex >> NPDPEPGSHIFT;
3657 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3658 if (pdpg == NULL && lockp != NULL)
3665 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3667 vm_pindex_t ptepindex;
3668 pd_entry_t *pd, PG_V;
3671 PG_V = pmap_valid_bit(pmap);
3674 * Calculate pagetable page index
3676 ptepindex = pmap_pde_pindex(va);
3679 * Get the page directory entry
3681 pd = pmap_pde(pmap, va);
3684 * This supports switching from a 2MB page to a
3687 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3688 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3690 * Invalidation of the 2MB page mapping may have caused
3691 * the deallocation of the underlying PD page.
3698 * If the page table page is mapped, we just increment the
3699 * hold count, and activate it.
3701 if (pd != NULL && (*pd & PG_V) != 0) {
3702 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3706 * Here if the pte page isn't mapped, or if it has been
3709 m = _pmap_allocpte(pmap, ptepindex, lockp);
3710 if (m == NULL && lockp != NULL)
3717 /***************************************************
3718 * Pmap allocation/deallocation routines.
3719 ***************************************************/
3722 * Release any resources held by the given physical map.
3723 * Called when a pmap initialized by pmap_pinit is being released.
3724 * Should only be called if the map contains no valid mappings.
3727 pmap_release(pmap_t pmap)
3732 KASSERT(pmap->pm_stats.resident_count == 0,
3733 ("pmap_release: pmap resident count %ld != 0",
3734 pmap->pm_stats.resident_count));
3735 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3736 ("pmap_release: pmap has reserved page table page(s)"));
3737 KASSERT(CPU_EMPTY(&pmap->pm_active),
3738 ("releasing active pmap %p", pmap));
3740 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3742 for (i = 0; i < NKPML4E; i++) /* KVA */
3743 pmap->pm_pml4[KPML4BASE + i] = 0;
3744 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3745 pmap->pm_pml4[DMPML4I + i] = 0;
3746 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3747 for (i = 0; i < lm_ents; i++) /* Large Map */
3748 pmap->pm_pml4[LMSPML4I + i] = 0;
3750 vm_page_unwire_noq(m);
3751 vm_page_free_zero(m);
3753 if (pmap->pm_pml4u != NULL) {
3754 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3755 vm_page_unwire_noq(m);
3758 if (pmap->pm_type == PT_X86 &&
3759 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3760 rangeset_fini(&pmap->pm_pkru);
3764 kvm_size(SYSCTL_HANDLER_ARGS)
3766 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3768 return sysctl_handle_long(oidp, &ksize, 0, req);
3770 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3771 0, 0, kvm_size, "LU", "Size of KVM");
3774 kvm_free(SYSCTL_HANDLER_ARGS)
3776 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3778 return sysctl_handle_long(oidp, &kfree, 0, req);
3780 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3781 0, 0, kvm_free, "LU", "Amount of KVM free");
3784 * grow the number of kernel page table entries, if needed
3787 pmap_growkernel(vm_offset_t addr)
3791 pd_entry_t *pde, newpdir;
3794 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3797 * Return if "addr" is within the range of kernel page table pages
3798 * that were preallocated during pmap bootstrap. Moreover, leave
3799 * "kernel_vm_end" and the kernel page table as they were.
3801 * The correctness of this action is based on the following
3802 * argument: vm_map_insert() allocates contiguous ranges of the
3803 * kernel virtual address space. It calls this function if a range
3804 * ends after "kernel_vm_end". If the kernel is mapped between
3805 * "kernel_vm_end" and "addr", then the range cannot begin at
3806 * "kernel_vm_end". In fact, its beginning address cannot be less
3807 * than the kernel. Thus, there is no immediate need to allocate
3808 * any new kernel page table pages between "kernel_vm_end" and
3811 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3814 addr = roundup2(addr, NBPDR);
3815 if (addr - 1 >= vm_map_max(kernel_map))
3816 addr = vm_map_max(kernel_map);
3817 while (kernel_vm_end < addr) {
3818 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3819 if ((*pdpe & X86_PG_V) == 0) {
3820 /* We need a new PDP entry */
3821 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3822 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3823 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3825 panic("pmap_growkernel: no memory to grow kernel");
3826 if ((nkpg->flags & PG_ZERO) == 0)
3827 pmap_zero_page(nkpg);
3828 paddr = VM_PAGE_TO_PHYS(nkpg);
3829 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3830 X86_PG_A | X86_PG_M);
3831 continue; /* try again */
3833 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3834 if ((*pde & X86_PG_V) != 0) {
3835 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3836 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3837 kernel_vm_end = vm_map_max(kernel_map);
3843 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3844 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3847 panic("pmap_growkernel: no memory to grow kernel");
3848 if ((nkpg->flags & PG_ZERO) == 0)
3849 pmap_zero_page(nkpg);
3850 paddr = VM_PAGE_TO_PHYS(nkpg);
3851 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3852 pde_store(pde, newpdir);
3854 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3855 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3856 kernel_vm_end = vm_map_max(kernel_map);
3863 /***************************************************
3864 * page management routines.
3865 ***************************************************/
3867 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3868 CTASSERT(_NPCM == 3);
3869 CTASSERT(_NPCPV == 168);
3871 static __inline struct pv_chunk *
3872 pv_to_chunk(pv_entry_t pv)
3875 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3878 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3880 #define PC_FREE0 0xfffffffffffffffful
3881 #define PC_FREE1 0xfffffffffffffffful
3882 #define PC_FREE2 0x000000fffffffffful
3884 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3887 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3889 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3890 "Current number of pv entry chunks");
3891 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3892 "Current number of pv entry chunks allocated");
3893 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3894 "Current number of pv entry chunks frees");
3895 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3896 "Number of times tried to get a chunk page but failed.");
3898 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3899 static int pv_entry_spare;
3901 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3902 "Current number of pv entry frees");
3903 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3904 "Current number of pv entry allocs");
3905 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3906 "Current number of pv entries");
3907 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3908 "Current number of spare pv entries");
3912 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3917 pmap_invalidate_all(pmap);
3918 if (pmap != locked_pmap)
3921 pmap_delayed_invl_finish();
3925 * We are in a serious low memory condition. Resort to
3926 * drastic measures to free some pages so we can allocate
3927 * another pv entry chunk.
3929 * Returns NULL if PV entries were reclaimed from the specified pmap.
3931 * We do not, however, unmap 2mpages because subsequent accesses will
3932 * allocate per-page pv entries until repromotion occurs, thereby
3933 * exacerbating the shortage of free pv entries.
3936 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3938 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3939 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3940 struct md_page *pvh;
3942 pmap_t next_pmap, pmap;
3943 pt_entry_t *pte, tpte;
3944 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3948 struct spglist free;
3950 int bit, field, freed;
3952 static int active_reclaims = 0;
3954 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3955 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3958 PG_G = PG_A = PG_M = PG_RW = 0;
3960 bzero(&pc_marker_b, sizeof(pc_marker_b));
3961 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3962 pc_marker = (struct pv_chunk *)&pc_marker_b;
3963 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3966 * A delayed invalidation block should already be active if
3967 * pmap_advise() or pmap_remove() called this function by way
3968 * of pmap_demote_pde_locked().
3970 start_di = pmap_not_in_di();
3972 mtx_lock(&pv_chunks_mutex);
3974 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3975 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3976 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3977 SLIST_EMPTY(&free)) {
3978 next_pmap = pc->pc_pmap;
3979 if (next_pmap == NULL) {
3981 * The next chunk is a marker. However, it is
3982 * not our marker, so active_reclaims must be
3983 * > 1. Consequently, the next_chunk code
3984 * will not rotate the pv_chunks list.
3988 mtx_unlock(&pv_chunks_mutex);
3991 * A pv_chunk can only be removed from the pc_lru list
3992 * when both pc_chunks_mutex is owned and the
3993 * corresponding pmap is locked.
3995 if (pmap != next_pmap) {
3996 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3999 /* Avoid deadlock and lock recursion. */
4000 if (pmap > locked_pmap) {
4001 RELEASE_PV_LIST_LOCK(lockp);
4004 pmap_delayed_invl_start();
4005 mtx_lock(&pv_chunks_mutex);
4007 } else if (pmap != locked_pmap) {
4008 if (PMAP_TRYLOCK(pmap)) {
4010 pmap_delayed_invl_start();
4011 mtx_lock(&pv_chunks_mutex);
4014 pmap = NULL; /* pmap is not locked */
4015 mtx_lock(&pv_chunks_mutex);
4016 pc = TAILQ_NEXT(pc_marker, pc_lru);
4018 pc->pc_pmap != next_pmap)
4022 } else if (start_di)
4023 pmap_delayed_invl_start();
4024 PG_G = pmap_global_bit(pmap);
4025 PG_A = pmap_accessed_bit(pmap);
4026 PG_M = pmap_modified_bit(pmap);
4027 PG_RW = pmap_rw_bit(pmap);
4031 * Destroy every non-wired, 4 KB page mapping in the chunk.
4034 for (field = 0; field < _NPCM; field++) {
4035 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4036 inuse != 0; inuse &= ~(1UL << bit)) {
4038 pv = &pc->pc_pventry[field * 64 + bit];
4040 pde = pmap_pde(pmap, va);
4041 if ((*pde & PG_PS) != 0)
4043 pte = pmap_pde_to_pte(pde, va);
4044 if ((*pte & PG_W) != 0)
4046 tpte = pte_load_clear(pte);
4047 if ((tpte & PG_G) != 0)
4048 pmap_invalidate_page(pmap, va);
4049 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4050 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4052 if ((tpte & PG_A) != 0)
4053 vm_page_aflag_set(m, PGA_REFERENCED);
4054 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4055 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4057 if (TAILQ_EMPTY(&m->md.pv_list) &&
4058 (m->flags & PG_FICTITIOUS) == 0) {
4059 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4060 if (TAILQ_EMPTY(&pvh->pv_list)) {
4061 vm_page_aflag_clear(m,
4065 pmap_delayed_invl_page(m);
4066 pc->pc_map[field] |= 1UL << bit;
4067 pmap_unuse_pt(pmap, va, *pde, &free);
4072 mtx_lock(&pv_chunks_mutex);
4075 /* Every freed mapping is for a 4 KB page. */
4076 pmap_resident_count_dec(pmap, freed);
4077 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4078 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4079 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4080 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4081 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4082 pc->pc_map[2] == PC_FREE2) {
4083 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4084 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4085 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4086 /* Entire chunk is free; return it. */
4087 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4088 dump_drop_page(m_pc->phys_addr);
4089 mtx_lock(&pv_chunks_mutex);
4090 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4093 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4094 mtx_lock(&pv_chunks_mutex);
4095 /* One freed pv entry in locked_pmap is sufficient. */
4096 if (pmap == locked_pmap)
4099 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4100 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
4101 if (active_reclaims == 1 && pmap != NULL) {
4103 * Rotate the pv chunks list so that we do not
4104 * scan the same pv chunks that could not be
4105 * freed (because they contained a wired
4106 * and/or superpage mapping) on every
4107 * invocation of reclaim_pv_chunk().
4109 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4110 MPASS(pc->pc_pmap != NULL);
4111 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4112 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4116 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4117 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4119 mtx_unlock(&pv_chunks_mutex);
4120 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4121 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4122 m_pc = SLIST_FIRST(&free);
4123 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4124 /* Recycle a freed page table page. */
4125 m_pc->wire_count = 1;
4127 vm_page_free_pages_toq(&free, true);
4132 * free the pv_entry back to the free list
4135 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4137 struct pv_chunk *pc;
4138 int idx, field, bit;
4140 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4141 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4142 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4143 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4144 pc = pv_to_chunk(pv);
4145 idx = pv - &pc->pc_pventry[0];
4148 pc->pc_map[field] |= 1ul << bit;
4149 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4150 pc->pc_map[2] != PC_FREE2) {
4151 /* 98% of the time, pc is already at the head of the list. */
4152 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4153 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4154 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4158 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4163 free_pv_chunk(struct pv_chunk *pc)
4167 mtx_lock(&pv_chunks_mutex);
4168 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4169 mtx_unlock(&pv_chunks_mutex);
4170 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4171 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4172 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4173 /* entire chunk is free, return it */
4174 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4175 dump_drop_page(m->phys_addr);
4176 vm_page_unwire_noq(m);
4181 * Returns a new PV entry, allocating a new PV chunk from the system when
4182 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4183 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4186 * The given PV list lock may be released.
4189 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4193 struct pv_chunk *pc;
4196 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4197 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4199 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4201 for (field = 0; field < _NPCM; field++) {
4202 if (pc->pc_map[field]) {
4203 bit = bsfq(pc->pc_map[field]);
4207 if (field < _NPCM) {
4208 pv = &pc->pc_pventry[field * 64 + bit];
4209 pc->pc_map[field] &= ~(1ul << bit);
4210 /* If this was the last item, move it to tail */
4211 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4212 pc->pc_map[2] == 0) {
4213 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4214 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4217 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4218 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4222 /* No free items, allocate another chunk */
4223 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4226 if (lockp == NULL) {
4227 PV_STAT(pc_chunk_tryfail++);
4230 m = reclaim_pv_chunk(pmap, lockp);
4234 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4235 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4236 dump_add_page(m->phys_addr);
4237 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4239 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4240 pc->pc_map[1] = PC_FREE1;
4241 pc->pc_map[2] = PC_FREE2;
4242 mtx_lock(&pv_chunks_mutex);
4243 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4244 mtx_unlock(&pv_chunks_mutex);
4245 pv = &pc->pc_pventry[0];
4246 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4247 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4248 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4253 * Returns the number of one bits within the given PV chunk map.
4255 * The erratas for Intel processors state that "POPCNT Instruction May
4256 * Take Longer to Execute Than Expected". It is believed that the
4257 * issue is the spurious dependency on the destination register.
4258 * Provide a hint to the register rename logic that the destination
4259 * value is overwritten, by clearing it, as suggested in the
4260 * optimization manual. It should be cheap for unaffected processors
4263 * Reference numbers for erratas are
4264 * 4th Gen Core: HSD146
4265 * 5th Gen Core: BDM85
4266 * 6th Gen Core: SKL029
4269 popcnt_pc_map_pq(uint64_t *map)
4273 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4274 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4275 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4276 : "=&r" (result), "=&r" (tmp)
4277 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4282 * Ensure that the number of spare PV entries in the specified pmap meets or
4283 * exceeds the given count, "needed".
4285 * The given PV list lock may be released.
4288 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4290 struct pch new_tail;
4291 struct pv_chunk *pc;
4296 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4297 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4300 * Newly allocated PV chunks must be stored in a private list until
4301 * the required number of PV chunks have been allocated. Otherwise,
4302 * reclaim_pv_chunk() could recycle one of these chunks. In
4303 * contrast, these chunks must be added to the pmap upon allocation.
4305 TAILQ_INIT(&new_tail);
4308 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4310 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4311 bit_count((bitstr_t *)pc->pc_map, 0,
4312 sizeof(pc->pc_map) * NBBY, &free);
4315 free = popcnt_pc_map_pq(pc->pc_map);
4319 if (avail >= needed)
4322 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4323 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4326 m = reclaim_pv_chunk(pmap, lockp);
4331 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4332 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4333 dump_add_page(m->phys_addr);
4334 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4336 pc->pc_map[0] = PC_FREE0;
4337 pc->pc_map[1] = PC_FREE1;
4338 pc->pc_map[2] = PC_FREE2;
4339 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4340 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4341 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4344 * The reclaim might have freed a chunk from the current pmap.
4345 * If that chunk contained available entries, we need to
4346 * re-count the number of available entries.
4351 if (!TAILQ_EMPTY(&new_tail)) {
4352 mtx_lock(&pv_chunks_mutex);
4353 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4354 mtx_unlock(&pv_chunks_mutex);
4359 * First find and then remove the pv entry for the specified pmap and virtual
4360 * address from the specified pv list. Returns the pv entry if found and NULL
4361 * otherwise. This operation can be performed on pv lists for either 4KB or
4362 * 2MB page mappings.
4364 static __inline pv_entry_t
4365 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4369 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4370 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4371 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4380 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4381 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4382 * entries for each of the 4KB page mappings.
4385 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4386 struct rwlock **lockp)
4388 struct md_page *pvh;
4389 struct pv_chunk *pc;
4391 vm_offset_t va_last;
4395 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4396 KASSERT((pa & PDRMASK) == 0,
4397 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4398 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4401 * Transfer the 2mpage's pv entry for this mapping to the first
4402 * page's pv list. Once this transfer begins, the pv list lock
4403 * must not be released until the last pv entry is reinstantiated.
4405 pvh = pa_to_pvh(pa);
4406 va = trunc_2mpage(va);
4407 pv = pmap_pvh_remove(pvh, pmap, va);
4408 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4409 m = PHYS_TO_VM_PAGE(pa);
4410 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4412 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4413 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4414 va_last = va + NBPDR - PAGE_SIZE;
4416 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4417 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4418 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4419 for (field = 0; field < _NPCM; field++) {
4420 while (pc->pc_map[field]) {
4421 bit = bsfq(pc->pc_map[field]);
4422 pc->pc_map[field] &= ~(1ul << bit);
4423 pv = &pc->pc_pventry[field * 64 + bit];
4427 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4428 ("pmap_pv_demote_pde: page %p is not managed", m));
4429 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4435 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4436 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4439 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4440 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4441 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4443 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4444 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4447 #if VM_NRESERVLEVEL > 0
4449 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4450 * replace the many pv entries for the 4KB page mappings by a single pv entry
4451 * for the 2MB page mapping.
4454 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4455 struct rwlock **lockp)
4457 struct md_page *pvh;
4459 vm_offset_t va_last;
4462 KASSERT((pa & PDRMASK) == 0,
4463 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4464 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4467 * Transfer the first page's pv entry for this mapping to the 2mpage's
4468 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4469 * a transfer avoids the possibility that get_pv_entry() calls
4470 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4471 * mappings that is being promoted.
4473 m = PHYS_TO_VM_PAGE(pa);
4474 va = trunc_2mpage(va);
4475 pv = pmap_pvh_remove(&m->md, pmap, va);
4476 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4477 pvh = pa_to_pvh(pa);
4478 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4480 /* Free the remaining NPTEPG - 1 pv entries. */
4481 va_last = va + NBPDR - PAGE_SIZE;
4485 pmap_pvh_free(&m->md, pmap, va);
4486 } while (va < va_last);
4488 #endif /* VM_NRESERVLEVEL > 0 */
4491 * First find and then destroy the pv entry for the specified pmap and virtual
4492 * address. This operation can be performed on pv lists for either 4KB or 2MB
4496 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4500 pv = pmap_pvh_remove(pvh, pmap, va);
4501 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4502 free_pv_entry(pmap, pv);
4506 * Conditionally create the PV entry for a 4KB page mapping if the required
4507 * memory can be allocated without resorting to reclamation.
4510 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4511 struct rwlock **lockp)
4515 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4516 /* Pass NULL instead of the lock pointer to disable reclamation. */
4517 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4519 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4520 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4528 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4529 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4530 * false if the PV entry cannot be allocated without resorting to reclamation.
4533 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4534 struct rwlock **lockp)
4536 struct md_page *pvh;
4540 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4541 /* Pass NULL instead of the lock pointer to disable reclamation. */
4542 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4543 NULL : lockp)) == NULL)
4546 pa = pde & PG_PS_FRAME;
4547 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4548 pvh = pa_to_pvh(pa);
4549 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4555 * Fills a page table page with mappings to consecutive physical pages.
4558 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4562 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4564 newpte += PAGE_SIZE;
4569 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4570 * mapping is invalidated.
4573 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4575 struct rwlock *lock;
4579 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4586 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4590 pt_entry_t *xpte, *ypte;
4592 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4593 xpte++, newpte += PAGE_SIZE) {
4594 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4595 printf("pmap_demote_pde: xpte %zd and newpte map "
4596 "different pages: found %#lx, expected %#lx\n",
4597 xpte - firstpte, *xpte, newpte);
4598 printf("page table dump\n");
4599 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4600 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4605 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4606 ("pmap_demote_pde: firstpte and newpte map different physical"
4613 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4614 pd_entry_t oldpde, struct rwlock **lockp)
4616 struct spglist free;
4620 sva = trunc_2mpage(va);
4621 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4622 if ((oldpde & pmap_global_bit(pmap)) == 0)
4623 pmap_invalidate_pde_page(pmap, sva, oldpde);
4624 vm_page_free_pages_toq(&free, true);
4625 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
4630 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4631 struct rwlock **lockp)
4633 pd_entry_t newpde, oldpde;
4634 pt_entry_t *firstpte, newpte;
4635 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4641 PG_A = pmap_accessed_bit(pmap);
4642 PG_G = pmap_global_bit(pmap);
4643 PG_M = pmap_modified_bit(pmap);
4644 PG_RW = pmap_rw_bit(pmap);
4645 PG_V = pmap_valid_bit(pmap);
4646 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4647 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4649 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4650 in_kernel = va >= VM_MAXUSER_ADDRESS;
4652 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4653 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4656 * Invalidate the 2MB page mapping and return "failure" if the
4657 * mapping was never accessed.
4659 if ((oldpde & PG_A) == 0) {
4660 KASSERT((oldpde & PG_W) == 0,
4661 ("pmap_demote_pde: a wired mapping is missing PG_A"));
4662 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4666 mpte = pmap_remove_pt_page(pmap, va);
4668 KASSERT((oldpde & PG_W) == 0,
4669 ("pmap_demote_pde: page table page for a wired mapping"
4673 * If the page table page is missing and the mapping
4674 * is for a kernel address, the mapping must belong to
4675 * the direct map. Page table pages are preallocated
4676 * for every other part of the kernel address space,
4677 * so the direct map region is the only part of the
4678 * kernel address space that must be handled here.
4680 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
4681 va < DMAP_MAX_ADDRESS),
4682 ("pmap_demote_pde: No saved mpte for va %#lx", va));
4685 * If the 2MB page mapping belongs to the direct map
4686 * region of the kernel's address space, then the page
4687 * allocation request specifies the highest possible
4688 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
4689 * priority is normal.
4691 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
4692 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4693 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4696 * If the allocation of the new page table page fails,
4697 * invalidate the 2MB page mapping and return "failure".
4700 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4705 mpte->wire_count = NPTEPG;
4706 pmap_resident_count_inc(pmap, 1);
4709 mptepa = VM_PAGE_TO_PHYS(mpte);
4710 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4711 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4712 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4713 ("pmap_demote_pde: oldpde is missing PG_M"));
4714 newpte = oldpde & ~PG_PS;
4715 newpte = pmap_swap_pat(pmap, newpte);
4718 * If the page table page is not leftover from an earlier promotion,
4721 if (mpte->valid == 0)
4722 pmap_fill_ptp(firstpte, newpte);
4724 pmap_demote_pde_check(firstpte, newpte);
4727 * If the mapping has changed attributes, update the page table
4730 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4731 pmap_fill_ptp(firstpte, newpte);
4734 * The spare PV entries must be reserved prior to demoting the
4735 * mapping, that is, prior to changing the PDE. Otherwise, the state
4736 * of the PDE and the PV lists will be inconsistent, which can result
4737 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4738 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4739 * PV entry for the 2MB page mapping that is being demoted.
4741 if ((oldpde & PG_MANAGED) != 0)
4742 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4745 * Demote the mapping. This pmap is locked. The old PDE has
4746 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4747 * set. Thus, there is no danger of a race with another
4748 * processor changing the setting of PG_A and/or PG_M between
4749 * the read above and the store below.
4751 if (workaround_erratum383)
4752 pmap_update_pde(pmap, va, pde, newpde);
4754 pde_store(pde, newpde);
4757 * Invalidate a stale recursive mapping of the page table page.
4760 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4763 * Demote the PV entry.
4765 if ((oldpde & PG_MANAGED) != 0)
4766 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4768 atomic_add_long(&pmap_pde_demotions, 1);
4769 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
4775 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4778 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4784 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4786 mpte = pmap_remove_pt_page(pmap, va);
4788 panic("pmap_remove_kernel_pde: Missing pt page.");
4790 mptepa = VM_PAGE_TO_PHYS(mpte);
4791 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4794 * If this page table page was unmapped by a promotion, then it
4795 * contains valid mappings. Zero it to invalidate those mappings.
4797 if (mpte->valid != 0)
4798 pagezero((void *)PHYS_TO_DMAP(mptepa));
4801 * Demote the mapping.
4803 if (workaround_erratum383)
4804 pmap_update_pde(pmap, va, pde, newpde);
4806 pde_store(pde, newpde);
4809 * Invalidate a stale recursive mapping of the page table page.
4811 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4815 * pmap_remove_pde: do the things to unmap a superpage in a process
4818 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4819 struct spglist *free, struct rwlock **lockp)
4821 struct md_page *pvh;
4823 vm_offset_t eva, va;
4825 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4827 PG_G = pmap_global_bit(pmap);
4828 PG_A = pmap_accessed_bit(pmap);
4829 PG_M = pmap_modified_bit(pmap);
4830 PG_RW = pmap_rw_bit(pmap);
4832 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4833 KASSERT((sva & PDRMASK) == 0,
4834 ("pmap_remove_pde: sva is not 2mpage aligned"));
4835 oldpde = pte_load_clear(pdq);
4837 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4838 if ((oldpde & PG_G) != 0)
4839 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4840 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4841 if (oldpde & PG_MANAGED) {
4842 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4843 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4844 pmap_pvh_free(pvh, pmap, sva);
4846 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4847 va < eva; va += PAGE_SIZE, m++) {
4848 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4851 vm_page_aflag_set(m, PGA_REFERENCED);
4852 if (TAILQ_EMPTY(&m->md.pv_list) &&
4853 TAILQ_EMPTY(&pvh->pv_list))
4854 vm_page_aflag_clear(m, PGA_WRITEABLE);
4855 pmap_delayed_invl_page(m);
4858 if (pmap == kernel_pmap) {
4859 pmap_remove_kernel_pde(pmap, pdq, sva);
4861 mpte = pmap_remove_pt_page(pmap, sva);
4863 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4864 ("pmap_remove_pde: pte page not promoted"));
4865 pmap_resident_count_dec(pmap, 1);
4866 KASSERT(mpte->wire_count == NPTEPG,
4867 ("pmap_remove_pde: pte page wire count error"));
4868 mpte->wire_count = 0;
4869 pmap_add_delayed_free_list(mpte, free, FALSE);
4872 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4876 * pmap_remove_pte: do the things to unmap a page in a process
4879 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4880 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4882 struct md_page *pvh;
4883 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4886 PG_A = pmap_accessed_bit(pmap);
4887 PG_M = pmap_modified_bit(pmap);
4888 PG_RW = pmap_rw_bit(pmap);
4890 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4891 oldpte = pte_load_clear(ptq);
4893 pmap->pm_stats.wired_count -= 1;
4894 pmap_resident_count_dec(pmap, 1);
4895 if (oldpte & PG_MANAGED) {
4896 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4897 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4900 vm_page_aflag_set(m, PGA_REFERENCED);
4901 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4902 pmap_pvh_free(&m->md, pmap, va);
4903 if (TAILQ_EMPTY(&m->md.pv_list) &&
4904 (m->flags & PG_FICTITIOUS) == 0) {
4905 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4906 if (TAILQ_EMPTY(&pvh->pv_list))
4907 vm_page_aflag_clear(m, PGA_WRITEABLE);
4909 pmap_delayed_invl_page(m);
4911 return (pmap_unuse_pt(pmap, va, ptepde, free));
4915 * Remove a single page from a process address space
4918 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4919 struct spglist *free)
4921 struct rwlock *lock;
4922 pt_entry_t *pte, PG_V;
4924 PG_V = pmap_valid_bit(pmap);
4925 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4926 if ((*pde & PG_V) == 0)
4928 pte = pmap_pde_to_pte(pde, va);
4929 if ((*pte & PG_V) == 0)
4932 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4935 pmap_invalidate_page(pmap, va);
4939 * Removes the specified range of addresses from the page table page.
4942 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4943 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4945 pt_entry_t PG_G, *pte;
4949 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4950 PG_G = pmap_global_bit(pmap);
4953 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4957 pmap_invalidate_range(pmap, va, sva);
4962 if ((*pte & PG_G) == 0)
4966 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4972 pmap_invalidate_range(pmap, va, sva);
4977 * Remove the given range of addresses from the specified map.
4979 * It is assumed that the start and end are properly
4980 * rounded to the page size.
4983 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4985 struct rwlock *lock;
4986 vm_offset_t va_next;
4987 pml4_entry_t *pml4e;
4989 pd_entry_t ptpaddr, *pde;
4990 pt_entry_t PG_G, PG_V;
4991 struct spglist free;
4994 PG_G = pmap_global_bit(pmap);
4995 PG_V = pmap_valid_bit(pmap);
4998 * Perform an unsynchronized read. This is, however, safe.
5000 if (pmap->pm_stats.resident_count == 0)
5006 pmap_delayed_invl_start();
5008 pmap_pkru_on_remove(pmap, sva, eva);
5011 * special handling of removing one page. a very
5012 * common operation and easy to short circuit some
5015 if (sva + PAGE_SIZE == eva) {
5016 pde = pmap_pde(pmap, sva);
5017 if (pde && (*pde & PG_PS) == 0) {
5018 pmap_remove_page(pmap, sva, pde, &free);
5024 for (; sva < eva; sva = va_next) {
5026 if (pmap->pm_stats.resident_count == 0)
5029 pml4e = pmap_pml4e(pmap, sva);
5030 if ((*pml4e & PG_V) == 0) {
5031 va_next = (sva + NBPML4) & ~PML4MASK;
5037 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5038 if ((*pdpe & PG_V) == 0) {
5039 va_next = (sva + NBPDP) & ~PDPMASK;
5046 * Calculate index for next page table.
5048 va_next = (sva + NBPDR) & ~PDRMASK;
5052 pde = pmap_pdpe_to_pde(pdpe, sva);
5056 * Weed out invalid mappings.
5062 * Check for large page.
5064 if ((ptpaddr & PG_PS) != 0) {
5066 * Are we removing the entire large page? If not,
5067 * demote the mapping and fall through.
5069 if (sva + NBPDR == va_next && eva >= va_next) {
5071 * The TLB entry for a PG_G mapping is
5072 * invalidated by pmap_remove_pde().
5074 if ((ptpaddr & PG_G) == 0)
5076 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5078 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5080 /* The large page mapping was destroyed. */
5087 * Limit our scan to either the end of the va represented
5088 * by the current page table page, or to the end of the
5089 * range being removed.
5094 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5101 pmap_invalidate_all(pmap);
5103 pmap_delayed_invl_finish();
5104 vm_page_free_pages_toq(&free, true);
5108 * Routine: pmap_remove_all
5110 * Removes this physical page from
5111 * all physical maps in which it resides.
5112 * Reflects back modify bits to the pager.
5115 * Original versions of this routine were very
5116 * inefficient because they iteratively called
5117 * pmap_remove (slow...)
5121 pmap_remove_all(vm_page_t m)
5123 struct md_page *pvh;
5126 struct rwlock *lock;
5127 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5130 struct spglist free;
5131 int pvh_gen, md_gen;
5133 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5134 ("pmap_remove_all: page %p is not managed", m));
5136 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5137 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5138 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5141 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5143 if (!PMAP_TRYLOCK(pmap)) {
5144 pvh_gen = pvh->pv_gen;
5148 if (pvh_gen != pvh->pv_gen) {
5155 pde = pmap_pde(pmap, va);
5156 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5159 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5161 if (!PMAP_TRYLOCK(pmap)) {
5162 pvh_gen = pvh->pv_gen;
5163 md_gen = m->md.pv_gen;
5167 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5173 PG_A = pmap_accessed_bit(pmap);
5174 PG_M = pmap_modified_bit(pmap);
5175 PG_RW = pmap_rw_bit(pmap);
5176 pmap_resident_count_dec(pmap, 1);
5177 pde = pmap_pde(pmap, pv->pv_va);
5178 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5179 " a 2mpage in page %p's pv list", m));
5180 pte = pmap_pde_to_pte(pde, pv->pv_va);
5181 tpte = pte_load_clear(pte);
5183 pmap->pm_stats.wired_count--;
5185 vm_page_aflag_set(m, PGA_REFERENCED);
5188 * Update the vm_page_t clean and reference bits.
5190 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5192 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5193 pmap_invalidate_page(pmap, pv->pv_va);
5194 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5196 free_pv_entry(pmap, pv);
5199 vm_page_aflag_clear(m, PGA_WRITEABLE);
5201 pmap_delayed_invl_wait(m);
5202 vm_page_free_pages_toq(&free, true);
5206 * pmap_protect_pde: do the things to protect a 2mpage in a process
5209 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5211 pd_entry_t newpde, oldpde;
5213 boolean_t anychanged;
5214 pt_entry_t PG_G, PG_M, PG_RW;
5216 PG_G = pmap_global_bit(pmap);
5217 PG_M = pmap_modified_bit(pmap);
5218 PG_RW = pmap_rw_bit(pmap);
5220 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5221 KASSERT((sva & PDRMASK) == 0,
5222 ("pmap_protect_pde: sva is not 2mpage aligned"));
5225 oldpde = newpde = *pde;
5226 if ((prot & VM_PROT_WRITE) == 0) {
5227 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5228 (PG_MANAGED | PG_M | PG_RW)) {
5229 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5230 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5233 newpde &= ~(PG_RW | PG_M);
5235 if ((prot & VM_PROT_EXECUTE) == 0)
5237 if (newpde != oldpde) {
5239 * As an optimization to future operations on this PDE, clear
5240 * PG_PROMOTED. The impending invalidation will remove any
5241 * lingering 4KB page mappings from the TLB.
5243 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5245 if ((oldpde & PG_G) != 0)
5246 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5250 return (anychanged);
5254 * Set the physical protection on the
5255 * specified range of this map as requested.
5258 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5260 vm_offset_t va_next;
5261 pml4_entry_t *pml4e;
5263 pd_entry_t ptpaddr, *pde;
5264 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5265 boolean_t anychanged;
5267 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5268 if (prot == VM_PROT_NONE) {
5269 pmap_remove(pmap, sva, eva);
5273 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5274 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5277 PG_G = pmap_global_bit(pmap);
5278 PG_M = pmap_modified_bit(pmap);
5279 PG_V = pmap_valid_bit(pmap);
5280 PG_RW = pmap_rw_bit(pmap);
5284 * Although this function delays and batches the invalidation
5285 * of stale TLB entries, it does not need to call
5286 * pmap_delayed_invl_start() and
5287 * pmap_delayed_invl_finish(), because it does not
5288 * ordinarily destroy mappings. Stale TLB entries from
5289 * protection-only changes need only be invalidated before the
5290 * pmap lock is released, because protection-only changes do
5291 * not destroy PV entries. Even operations that iterate over
5292 * a physical page's PV list of mappings, like
5293 * pmap_remove_write(), acquire the pmap lock for each
5294 * mapping. Consequently, for protection-only changes, the
5295 * pmap lock suffices to synchronize both page table and TLB
5298 * This function only destroys a mapping if pmap_demote_pde()
5299 * fails. In that case, stale TLB entries are immediately
5304 for (; sva < eva; sva = va_next) {
5306 pml4e = pmap_pml4e(pmap, sva);
5307 if ((*pml4e & PG_V) == 0) {
5308 va_next = (sva + NBPML4) & ~PML4MASK;
5314 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5315 if ((*pdpe & PG_V) == 0) {
5316 va_next = (sva + NBPDP) & ~PDPMASK;
5322 va_next = (sva + NBPDR) & ~PDRMASK;
5326 pde = pmap_pdpe_to_pde(pdpe, sva);
5330 * Weed out invalid mappings.
5336 * Check for large page.
5338 if ((ptpaddr & PG_PS) != 0) {
5340 * Are we protecting the entire large page? If not,
5341 * demote the mapping and fall through.
5343 if (sva + NBPDR == va_next && eva >= va_next) {
5345 * The TLB entry for a PG_G mapping is
5346 * invalidated by pmap_protect_pde().
5348 if (pmap_protect_pde(pmap, pde, sva, prot))
5351 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5353 * The large page mapping was destroyed.
5362 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5364 pt_entry_t obits, pbits;
5368 obits = pbits = *pte;
5369 if ((pbits & PG_V) == 0)
5372 if ((prot & VM_PROT_WRITE) == 0) {
5373 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5374 (PG_MANAGED | PG_M | PG_RW)) {
5375 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5378 pbits &= ~(PG_RW | PG_M);
5380 if ((prot & VM_PROT_EXECUTE) == 0)
5383 if (pbits != obits) {
5384 if (!atomic_cmpset_long(pte, obits, pbits))
5387 pmap_invalidate_page(pmap, sva);
5394 pmap_invalidate_all(pmap);
5398 #if VM_NRESERVLEVEL > 0
5400 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5401 * single page table page (PTP) to a single 2MB page mapping. For promotion
5402 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5403 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5404 * identical characteristics.
5407 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5408 struct rwlock **lockp)
5411 pt_entry_t *firstpte, oldpte, pa, *pte;
5412 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5416 PG_A = pmap_accessed_bit(pmap);
5417 PG_G = pmap_global_bit(pmap);
5418 PG_M = pmap_modified_bit(pmap);
5419 PG_V = pmap_valid_bit(pmap);
5420 PG_RW = pmap_rw_bit(pmap);
5421 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5422 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5424 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5427 * Examine the first PTE in the specified PTP. Abort if this PTE is
5428 * either invalid, unused, or does not map the first 4KB physical page
5429 * within a 2MB page.
5431 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5434 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
5435 atomic_add_long(&pmap_pde_p_failures, 1);
5436 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5437 " in pmap %p", va, pmap);
5440 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5442 * When PG_M is already clear, PG_RW can be cleared without
5443 * a TLB invalidation.
5445 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5451 * Examine each of the other PTEs in the specified PTP. Abort if this
5452 * PTE maps an unexpected 4KB physical page or does not have identical
5453 * characteristics to the first PTE.
5455 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5456 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5459 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5460 atomic_add_long(&pmap_pde_p_failures, 1);
5461 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5462 " in pmap %p", va, pmap);
5465 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5467 * When PG_M is already clear, PG_RW can be cleared
5468 * without a TLB invalidation.
5470 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5473 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5474 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5475 (va & ~PDRMASK), pmap);
5477 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5478 atomic_add_long(&pmap_pde_p_failures, 1);
5479 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5480 " in pmap %p", va, pmap);
5487 * Save the page table page in its current state until the PDE
5488 * mapping the superpage is demoted by pmap_demote_pde() or
5489 * destroyed by pmap_remove_pde().
5491 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5492 KASSERT(mpte >= vm_page_array &&
5493 mpte < &vm_page_array[vm_page_array_size],
5494 ("pmap_promote_pde: page table page is out of range"));
5495 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5496 ("pmap_promote_pde: page table page's pindex is wrong"));
5497 if (pmap_insert_pt_page(pmap, mpte, true)) {
5498 atomic_add_long(&pmap_pde_p_failures, 1);
5500 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5506 * Promote the pv entries.
5508 if ((newpde & PG_MANAGED) != 0)
5509 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5512 * Propagate the PAT index to its proper position.
5514 newpde = pmap_swap_pat(pmap, newpde);
5517 * Map the superpage.
5519 if (workaround_erratum383)
5520 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5522 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5524 atomic_add_long(&pmap_pde_promotions, 1);
5525 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5526 " in pmap %p", va, pmap);
5528 #endif /* VM_NRESERVLEVEL > 0 */
5531 * Insert the given physical page (p) at
5532 * the specified virtual address (v) in the
5533 * target physical map with the protection requested.
5535 * If specified, the page will be wired down, meaning
5536 * that the related pte can not be reclaimed.
5538 * NB: This is the only routine which MAY NOT lazy-evaluate
5539 * or lose information. That is, this routine must actually
5540 * insert this page into the given map NOW.
5542 * When destroying both a page table and PV entry, this function
5543 * performs the TLB invalidation before releasing the PV list
5544 * lock, so we do not need pmap_delayed_invl_page() calls here.
5547 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5548 u_int flags, int8_t psind)
5550 struct rwlock *lock;
5552 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5553 pt_entry_t newpte, origpte;
5560 PG_A = pmap_accessed_bit(pmap);
5561 PG_G = pmap_global_bit(pmap);
5562 PG_M = pmap_modified_bit(pmap);
5563 PG_V = pmap_valid_bit(pmap);
5564 PG_RW = pmap_rw_bit(pmap);
5566 va = trunc_page(va);
5567 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5568 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5569 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5571 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5572 va >= kmi.clean_eva,
5573 ("pmap_enter: managed mapping within the clean submap"));
5574 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5575 VM_OBJECT_ASSERT_LOCKED(m->object);
5576 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5577 ("pmap_enter: flags %u has reserved bits set", flags));
5578 pa = VM_PAGE_TO_PHYS(m);
5579 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5580 if ((flags & VM_PROT_WRITE) != 0)
5582 if ((prot & VM_PROT_WRITE) != 0)
5584 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5585 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5586 if ((prot & VM_PROT_EXECUTE) == 0)
5588 if ((flags & PMAP_ENTER_WIRED) != 0)
5590 if (va < VM_MAXUSER_ADDRESS)
5592 if (pmap == kernel_pmap)
5594 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5597 * Set modified bit gratuitously for writeable mappings if
5598 * the page is unmanaged. We do not want to take a fault
5599 * to do the dirty bit accounting for these mappings.
5601 if ((m->oflags & VPO_UNMANAGED) != 0) {
5602 if ((newpte & PG_RW) != 0)
5605 newpte |= PG_MANAGED;
5610 /* Assert the required virtual and physical alignment. */
5611 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5612 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5613 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5619 * In the case that a page table page is not
5620 * resident, we are creating it here.
5623 pde = pmap_pde(pmap, va);
5624 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5625 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5626 pte = pmap_pde_to_pte(pde, va);
5627 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5628 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5631 } else if (va < VM_MAXUSER_ADDRESS) {
5633 * Here if the pte page isn't mapped, or if it has been
5636 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5637 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5638 nosleep ? NULL : &lock);
5639 if (mpte == NULL && nosleep) {
5640 rv = KERN_RESOURCE_SHORTAGE;
5645 panic("pmap_enter: invalid page directory va=%#lx", va);
5649 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5650 newpte |= pmap_pkru_get(pmap, va);
5653 * Is the specified virtual address already mapped?
5655 if ((origpte & PG_V) != 0) {
5657 * Wiring change, just update stats. We don't worry about
5658 * wiring PT pages as they remain resident as long as there
5659 * are valid mappings in them. Hence, if a user page is wired,
5660 * the PT page will be also.
5662 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5663 pmap->pm_stats.wired_count++;
5664 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5665 pmap->pm_stats.wired_count--;
5668 * Remove the extra PT page reference.
5672 KASSERT(mpte->wire_count > 0,
5673 ("pmap_enter: missing reference to page table page,"
5678 * Has the physical page changed?
5680 opa = origpte & PG_FRAME;
5683 * No, might be a protection or wiring change.
5685 if ((origpte & PG_MANAGED) != 0 &&
5686 (newpte & PG_RW) != 0)
5687 vm_page_aflag_set(m, PGA_WRITEABLE);
5688 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5694 * The physical page has changed. Temporarily invalidate
5695 * the mapping. This ensures that all threads sharing the
5696 * pmap keep a consistent view of the mapping, which is
5697 * necessary for the correct handling of COW faults. It
5698 * also permits reuse of the old mapping's PV entry,
5699 * avoiding an allocation.
5701 * For consistency, handle unmanaged mappings the same way.
5703 origpte = pte_load_clear(pte);
5704 KASSERT((origpte & PG_FRAME) == opa,
5705 ("pmap_enter: unexpected pa update for %#lx", va));
5706 if ((origpte & PG_MANAGED) != 0) {
5707 om = PHYS_TO_VM_PAGE(opa);
5710 * The pmap lock is sufficient to synchronize with
5711 * concurrent calls to pmap_page_test_mappings() and
5712 * pmap_ts_referenced().
5714 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5716 if ((origpte & PG_A) != 0)
5717 vm_page_aflag_set(om, PGA_REFERENCED);
5718 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5719 pv = pmap_pvh_remove(&om->md, pmap, va);
5721 ("pmap_enter: no PV entry for %#lx", va));
5722 if ((newpte & PG_MANAGED) == 0)
5723 free_pv_entry(pmap, pv);
5724 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5725 TAILQ_EMPTY(&om->md.pv_list) &&
5726 ((om->flags & PG_FICTITIOUS) != 0 ||
5727 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5728 vm_page_aflag_clear(om, PGA_WRITEABLE);
5730 if ((origpte & PG_A) != 0)
5731 pmap_invalidate_page(pmap, va);
5735 * Increment the counters.
5737 if ((newpte & PG_W) != 0)
5738 pmap->pm_stats.wired_count++;
5739 pmap_resident_count_inc(pmap, 1);
5743 * Enter on the PV list if part of our managed memory.
5745 if ((newpte & PG_MANAGED) != 0) {
5747 pv = get_pv_entry(pmap, &lock);
5750 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5751 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5753 if ((newpte & PG_RW) != 0)
5754 vm_page_aflag_set(m, PGA_WRITEABLE);
5760 if ((origpte & PG_V) != 0) {
5762 origpte = pte_load_store(pte, newpte);
5763 KASSERT((origpte & PG_FRAME) == pa,
5764 ("pmap_enter: unexpected pa update for %#lx", va));
5765 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5767 if ((origpte & PG_MANAGED) != 0)
5771 * Although the PTE may still have PG_RW set, TLB
5772 * invalidation may nonetheless be required because
5773 * the PTE no longer has PG_M set.
5775 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5777 * This PTE change does not require TLB invalidation.
5781 if ((origpte & PG_A) != 0)
5782 pmap_invalidate_page(pmap, va);
5784 pte_store(pte, newpte);
5788 #if VM_NRESERVLEVEL > 0
5790 * If both the page table page and the reservation are fully
5791 * populated, then attempt promotion.
5793 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5794 pmap_ps_enabled(pmap) &&
5795 (m->flags & PG_FICTITIOUS) == 0 &&
5796 vm_reserv_level_iffullpop(m) == 0)
5797 pmap_promote_pde(pmap, pde, va, &lock);
5809 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5810 * if successful. Returns false if (1) a page table page cannot be allocated
5811 * without sleeping, (2) a mapping already exists at the specified virtual
5812 * address, or (3) a PV entry cannot be allocated without reclaiming another
5816 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5817 struct rwlock **lockp)
5822 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5823 PG_V = pmap_valid_bit(pmap);
5824 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5826 if ((m->oflags & VPO_UNMANAGED) == 0)
5827 newpde |= PG_MANAGED;
5828 if ((prot & VM_PROT_EXECUTE) == 0)
5830 if (va < VM_MAXUSER_ADDRESS)
5832 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5833 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5838 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5839 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5840 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5841 * a mapping already exists at the specified virtual address. Returns
5842 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5843 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5844 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5846 * The parameter "m" is only used when creating a managed, writeable mapping.
5849 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5850 vm_page_t m, struct rwlock **lockp)
5852 struct spglist free;
5853 pd_entry_t oldpde, *pde;
5854 pt_entry_t PG_G, PG_RW, PG_V;
5857 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
5858 ("pmap_enter_pde: cannot create wired user mapping"));
5859 PG_G = pmap_global_bit(pmap);
5860 PG_RW = pmap_rw_bit(pmap);
5861 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5862 ("pmap_enter_pde: newpde is missing PG_M"));
5863 PG_V = pmap_valid_bit(pmap);
5864 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5866 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5867 NULL : lockp)) == NULL) {
5868 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5869 " in pmap %p", va, pmap);
5870 return (KERN_RESOURCE_SHORTAGE);
5874 * If pkru is not same for the whole pde range, return failure
5875 * and let vm_fault() cope. Check after pde allocation, since
5878 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5880 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5881 pmap_invalidate_page(pmap, va);
5882 vm_page_free_pages_toq(&free, true);
5884 return (KERN_FAILURE);
5886 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5887 newpde &= ~X86_PG_PKU_MASK;
5888 newpde |= pmap_pkru_get(pmap, va);
5891 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5892 pde = &pde[pmap_pde_index(va)];
5894 if ((oldpde & PG_V) != 0) {
5895 KASSERT(pdpg->wire_count > 1,
5896 ("pmap_enter_pde: pdpg's wire count is too low"));
5897 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5899 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5900 " in pmap %p", va, pmap);
5901 return (KERN_FAILURE);
5903 /* Break the existing mapping(s). */
5905 if ((oldpde & PG_PS) != 0) {
5907 * The reference to the PD page that was acquired by
5908 * pmap_allocpde() ensures that it won't be freed.
5909 * However, if the PDE resulted from a promotion, then
5910 * a reserved PT page could be freed.
5912 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5913 if ((oldpde & PG_G) == 0)
5914 pmap_invalidate_pde_page(pmap, va, oldpde);
5916 pmap_delayed_invl_start();
5917 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5919 pmap_invalidate_all(pmap);
5920 pmap_delayed_invl_finish();
5922 vm_page_free_pages_toq(&free, true);
5923 if (va >= VM_MAXUSER_ADDRESS) {
5925 * Both pmap_remove_pde() and pmap_remove_ptes() will
5926 * leave the kernel page table page zero filled.
5928 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5929 if (pmap_insert_pt_page(pmap, mt, false))
5930 panic("pmap_enter_pde: trie insert failed");
5932 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5935 if ((newpde & PG_MANAGED) != 0) {
5937 * Abort this mapping if its PV entry could not be created.
5939 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5941 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5943 * Although "va" is not mapped, paging-
5944 * structure caches could nonetheless have
5945 * entries that refer to the freed page table
5946 * pages. Invalidate those entries.
5948 pmap_invalidate_page(pmap, va);
5949 vm_page_free_pages_toq(&free, true);
5951 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5952 " in pmap %p", va, pmap);
5953 return (KERN_RESOURCE_SHORTAGE);
5955 if ((newpde & PG_RW) != 0) {
5956 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5957 vm_page_aflag_set(mt, PGA_WRITEABLE);
5962 * Increment counters.
5964 if ((newpde & PG_W) != 0)
5965 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5966 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5969 * Map the superpage. (This is not a promoted mapping; there will not
5970 * be any lingering 4KB page mappings in the TLB.)
5972 pde_store(pde, newpde);
5974 atomic_add_long(&pmap_pde_mappings, 1);
5975 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5976 " in pmap %p", va, pmap);
5977 return (KERN_SUCCESS);
5981 * Maps a sequence of resident pages belonging to the same object.
5982 * The sequence begins with the given page m_start. This page is
5983 * mapped at the given virtual address start. Each subsequent page is
5984 * mapped at a virtual address that is offset from start by the same
5985 * amount as the page is offset from m_start within the object. The
5986 * last page in the sequence is the page with the largest offset from
5987 * m_start that can be mapped at a virtual address less than the given
5988 * virtual address end. Not every virtual page between start and end
5989 * is mapped; only those for which a resident page exists with the
5990 * corresponding offset from m_start are mapped.
5993 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5994 vm_page_t m_start, vm_prot_t prot)
5996 struct rwlock *lock;
5999 vm_pindex_t diff, psize;
6001 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6003 psize = atop(end - start);
6008 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6009 va = start + ptoa(diff);
6010 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6011 m->psind == 1 && pmap_ps_enabled(pmap) &&
6012 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6013 m = &m[NBPDR / PAGE_SIZE - 1];
6015 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6017 m = TAILQ_NEXT(m, listq);
6025 * this code makes some *MAJOR* assumptions:
6026 * 1. Current pmap & pmap exists.
6029 * 4. No page table pages.
6030 * but is *MUCH* faster than pmap_enter...
6034 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6036 struct rwlock *lock;
6040 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6047 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6048 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6050 struct spglist free;
6051 pt_entry_t newpte, *pte, PG_V;
6053 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6054 (m->oflags & VPO_UNMANAGED) != 0,
6055 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6056 PG_V = pmap_valid_bit(pmap);
6057 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6060 * In the case that a page table page is not
6061 * resident, we are creating it here.
6063 if (va < VM_MAXUSER_ADDRESS) {
6064 vm_pindex_t ptepindex;
6068 * Calculate pagetable page index
6070 ptepindex = pmap_pde_pindex(va);
6071 if (mpte && (mpte->pindex == ptepindex)) {
6075 * Get the page directory entry
6077 ptepa = pmap_pde(pmap, va);
6080 * If the page table page is mapped, we just increment
6081 * the hold count, and activate it. Otherwise, we
6082 * attempt to allocate a page table page. If this
6083 * attempt fails, we don't retry. Instead, we give up.
6085 if (ptepa && (*ptepa & PG_V) != 0) {
6088 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6092 * Pass NULL instead of the PV list lock
6093 * pointer, because we don't intend to sleep.
6095 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6100 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6101 pte = &pte[pmap_pte_index(va)];
6115 * Enter on the PV list if part of our managed memory.
6117 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6118 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6121 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6123 * Although "va" is not mapped, paging-
6124 * structure caches could nonetheless have
6125 * entries that refer to the freed page table
6126 * pages. Invalidate those entries.
6128 pmap_invalidate_page(pmap, va);
6129 vm_page_free_pages_toq(&free, true);
6137 * Increment counters
6139 pmap_resident_count_inc(pmap, 1);
6141 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6142 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6143 if ((m->oflags & VPO_UNMANAGED) == 0)
6144 newpte |= PG_MANAGED;
6145 if ((prot & VM_PROT_EXECUTE) == 0)
6147 if (va < VM_MAXUSER_ADDRESS)
6148 newpte |= PG_U | pmap_pkru_get(pmap, va);
6149 pte_store(pte, newpte);
6154 * Make a temporary mapping for a physical address. This is only intended
6155 * to be used for panic dumps.
6158 pmap_kenter_temporary(vm_paddr_t pa, int i)
6162 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6163 pmap_kenter(va, pa);
6165 return ((void *)crashdumpmap);
6169 * This code maps large physical mmap regions into the
6170 * processor address space. Note that some shortcuts
6171 * are taken, but the code works.
6174 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6175 vm_pindex_t pindex, vm_size_t size)
6178 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6179 vm_paddr_t pa, ptepa;
6183 PG_A = pmap_accessed_bit(pmap);
6184 PG_M = pmap_modified_bit(pmap);
6185 PG_V = pmap_valid_bit(pmap);
6186 PG_RW = pmap_rw_bit(pmap);
6188 VM_OBJECT_ASSERT_WLOCKED(object);
6189 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6190 ("pmap_object_init_pt: non-device object"));
6191 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6192 if (!pmap_ps_enabled(pmap))
6194 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6196 p = vm_page_lookup(object, pindex);
6197 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6198 ("pmap_object_init_pt: invalid page %p", p));
6199 pat_mode = p->md.pat_mode;
6202 * Abort the mapping if the first page is not physically
6203 * aligned to a 2MB page boundary.
6205 ptepa = VM_PAGE_TO_PHYS(p);
6206 if (ptepa & (NBPDR - 1))
6210 * Skip the first page. Abort the mapping if the rest of
6211 * the pages are not physically contiguous or have differing
6212 * memory attributes.
6214 p = TAILQ_NEXT(p, listq);
6215 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6217 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6218 ("pmap_object_init_pt: invalid page %p", p));
6219 if (pa != VM_PAGE_TO_PHYS(p) ||
6220 pat_mode != p->md.pat_mode)
6222 p = TAILQ_NEXT(p, listq);
6226 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6227 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6228 * will not affect the termination of this loop.
6231 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6232 pa < ptepa + size; pa += NBPDR) {
6233 pdpg = pmap_allocpde(pmap, addr, NULL);
6236 * The creation of mappings below is only an
6237 * optimization. If a page directory page
6238 * cannot be allocated without blocking,
6239 * continue on to the next mapping rather than
6245 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6246 pde = &pde[pmap_pde_index(addr)];
6247 if ((*pde & PG_V) == 0) {
6248 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6249 PG_U | PG_RW | PG_V);
6250 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6251 atomic_add_long(&pmap_pde_mappings, 1);
6253 /* Continue on if the PDE is already valid. */
6255 KASSERT(pdpg->wire_count > 0,
6256 ("pmap_object_init_pt: missing reference "
6257 "to page directory page, va: 0x%lx", addr));
6266 * Clear the wired attribute from the mappings for the specified range of
6267 * addresses in the given pmap. Every valid mapping within that range
6268 * must have the wired attribute set. In contrast, invalid mappings
6269 * cannot have the wired attribute set, so they are ignored.
6271 * The wired attribute of the page table entry is not a hardware
6272 * feature, so there is no need to invalidate any TLB entries.
6273 * Since pmap_demote_pde() for the wired entry must never fail,
6274 * pmap_delayed_invl_start()/finish() calls around the
6275 * function are not needed.
6278 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6280 vm_offset_t va_next;
6281 pml4_entry_t *pml4e;
6284 pt_entry_t *pte, PG_V;
6286 PG_V = pmap_valid_bit(pmap);
6288 for (; sva < eva; sva = va_next) {
6289 pml4e = pmap_pml4e(pmap, sva);
6290 if ((*pml4e & PG_V) == 0) {
6291 va_next = (sva + NBPML4) & ~PML4MASK;
6296 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6297 if ((*pdpe & PG_V) == 0) {
6298 va_next = (sva + NBPDP) & ~PDPMASK;
6303 va_next = (sva + NBPDR) & ~PDRMASK;
6306 pde = pmap_pdpe_to_pde(pdpe, sva);
6307 if ((*pde & PG_V) == 0)
6309 if ((*pde & PG_PS) != 0) {
6310 if ((*pde & PG_W) == 0)
6311 panic("pmap_unwire: pde %#jx is missing PG_W",
6315 * Are we unwiring the entire large page? If not,
6316 * demote the mapping and fall through.
6318 if (sva + NBPDR == va_next && eva >= va_next) {
6319 atomic_clear_long(pde, PG_W);
6320 pmap->pm_stats.wired_count -= NBPDR /
6323 } else if (!pmap_demote_pde(pmap, pde, sva))
6324 panic("pmap_unwire: demotion failed");
6328 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6330 if ((*pte & PG_V) == 0)
6332 if ((*pte & PG_W) == 0)
6333 panic("pmap_unwire: pte %#jx is missing PG_W",
6337 * PG_W must be cleared atomically. Although the pmap
6338 * lock synchronizes access to PG_W, another processor
6339 * could be setting PG_M and/or PG_A concurrently.
6341 atomic_clear_long(pte, PG_W);
6342 pmap->pm_stats.wired_count--;
6349 * Copy the range specified by src_addr/len
6350 * from the source map to the range dst_addr/len
6351 * in the destination map.
6353 * This routine is only advisory and need not do anything.
6356 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6357 vm_offset_t src_addr)
6359 struct rwlock *lock;
6360 struct spglist free;
6361 pml4_entry_t *pml4e;
6363 pd_entry_t *pde, srcptepaddr;
6364 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6365 vm_offset_t addr, end_addr, va_next;
6366 vm_page_t dst_pdpg, dstmpte, srcmpte;
6368 if (dst_addr != src_addr)
6371 if (dst_pmap->pm_type != src_pmap->pm_type)
6375 * EPT page table entries that require emulation of A/D bits are
6376 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6377 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6378 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6379 * implementations flag an EPT misconfiguration for exec-only
6380 * mappings we skip this function entirely for emulated pmaps.
6382 if (pmap_emulate_ad_bits(dst_pmap))
6385 end_addr = src_addr + len;
6387 if (dst_pmap < src_pmap) {
6388 PMAP_LOCK(dst_pmap);
6389 PMAP_LOCK(src_pmap);
6391 PMAP_LOCK(src_pmap);
6392 PMAP_LOCK(dst_pmap);
6395 PG_A = pmap_accessed_bit(dst_pmap);
6396 PG_M = pmap_modified_bit(dst_pmap);
6397 PG_V = pmap_valid_bit(dst_pmap);
6399 for (addr = src_addr; addr < end_addr; addr = va_next) {
6400 KASSERT(addr < UPT_MIN_ADDRESS,
6401 ("pmap_copy: invalid to pmap_copy page tables"));
6403 pml4e = pmap_pml4e(src_pmap, addr);
6404 if ((*pml4e & PG_V) == 0) {
6405 va_next = (addr + NBPML4) & ~PML4MASK;
6411 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6412 if ((*pdpe & PG_V) == 0) {
6413 va_next = (addr + NBPDP) & ~PDPMASK;
6419 va_next = (addr + NBPDR) & ~PDRMASK;
6423 pde = pmap_pdpe_to_pde(pdpe, addr);
6425 if (srcptepaddr == 0)
6428 if (srcptepaddr & PG_PS) {
6429 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6431 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6432 if (dst_pdpg == NULL)
6434 pde = (pd_entry_t *)
6435 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6436 pde = &pde[pmap_pde_index(addr)];
6437 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6438 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6439 PMAP_ENTER_NORECLAIM, &lock))) {
6440 *pde = srcptepaddr & ~PG_W;
6441 pmap_resident_count_inc(dst_pmap, NBPDR /
6443 atomic_add_long(&pmap_pde_mappings, 1);
6445 dst_pdpg->wire_count--;
6449 srcptepaddr &= PG_FRAME;
6450 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6451 KASSERT(srcmpte->wire_count > 0,
6452 ("pmap_copy: source page table page is unused"));
6454 if (va_next > end_addr)
6457 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6458 src_pte = &src_pte[pmap_pte_index(addr)];
6460 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6464 * We only virtual copy managed pages.
6466 if ((ptetemp & PG_MANAGED) == 0)
6469 if (dstmpte != NULL) {
6470 KASSERT(dstmpte->pindex ==
6471 pmap_pde_pindex(addr),
6472 ("dstmpte pindex/addr mismatch"));
6473 dstmpte->wire_count++;
6474 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6477 dst_pte = (pt_entry_t *)
6478 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6479 dst_pte = &dst_pte[pmap_pte_index(addr)];
6480 if (*dst_pte == 0 &&
6481 pmap_try_insert_pv_entry(dst_pmap, addr,
6482 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6484 * Clear the wired, modified, and accessed
6485 * (referenced) bits during the copy.
6487 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6488 pmap_resident_count_inc(dst_pmap, 1);
6491 if (pmap_unwire_ptp(dst_pmap, addr, dstmpte,
6494 * Although "addr" is not mapped,
6495 * paging-structure caches could
6496 * nonetheless have entries that refer
6497 * to the freed page table pages.
6498 * Invalidate those entries.
6500 pmap_invalidate_page(dst_pmap, addr);
6501 vm_page_free_pages_toq(&free, true);
6505 /* Have we copied all of the valid mappings? */
6506 if (dstmpte->wire_count >= srcmpte->wire_count)
6513 PMAP_UNLOCK(src_pmap);
6514 PMAP_UNLOCK(dst_pmap);
6518 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6522 if (dst_pmap->pm_type != src_pmap->pm_type ||
6523 dst_pmap->pm_type != PT_X86 ||
6524 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6527 if (dst_pmap < src_pmap) {
6528 PMAP_LOCK(dst_pmap);
6529 PMAP_LOCK(src_pmap);
6531 PMAP_LOCK(src_pmap);
6532 PMAP_LOCK(dst_pmap);
6534 error = pmap_pkru_copy(dst_pmap, src_pmap);
6535 /* Clean up partial copy on failure due to no memory. */
6536 if (error == ENOMEM)
6537 pmap_pkru_deassign_all(dst_pmap);
6538 PMAP_UNLOCK(src_pmap);
6539 PMAP_UNLOCK(dst_pmap);
6540 if (error != ENOMEM)
6548 * Zero the specified hardware page.
6551 pmap_zero_page(vm_page_t m)
6553 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6555 pagezero((void *)va);
6559 * Zero an an area within a single hardware page. off and size must not
6560 * cover an area beyond a single hardware page.
6563 pmap_zero_page_area(vm_page_t m, int off, int size)
6565 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6567 if (off == 0 && size == PAGE_SIZE)
6568 pagezero((void *)va);
6570 bzero((char *)va + off, size);
6574 * Copy 1 specified hardware page to another.
6577 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6579 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6580 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6582 pagecopy((void *)src, (void *)dst);
6585 int unmapped_buf_allowed = 1;
6588 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6589 vm_offset_t b_offset, int xfersize)
6593 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6597 while (xfersize > 0) {
6598 a_pg_offset = a_offset & PAGE_MASK;
6599 pages[0] = ma[a_offset >> PAGE_SHIFT];
6600 b_pg_offset = b_offset & PAGE_MASK;
6601 pages[1] = mb[b_offset >> PAGE_SHIFT];
6602 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6603 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6604 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6605 a_cp = (char *)vaddr[0] + a_pg_offset;
6606 b_cp = (char *)vaddr[1] + b_pg_offset;
6607 bcopy(a_cp, b_cp, cnt);
6608 if (__predict_false(mapped))
6609 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6617 * Returns true if the pmap's pv is one of the first
6618 * 16 pvs linked to from this page. This count may
6619 * be changed upwards or downwards in the future; it
6620 * is only necessary that true be returned for a small
6621 * subset of pmaps for proper page aging.
6624 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6626 struct md_page *pvh;
6627 struct rwlock *lock;
6632 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6633 ("pmap_page_exists_quick: page %p is not managed", m));
6635 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6637 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6638 if (PV_PMAP(pv) == pmap) {
6646 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6647 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6648 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6649 if (PV_PMAP(pv) == pmap) {
6663 * pmap_page_wired_mappings:
6665 * Return the number of managed mappings to the given physical page
6669 pmap_page_wired_mappings(vm_page_t m)
6671 struct rwlock *lock;
6672 struct md_page *pvh;
6676 int count, md_gen, pvh_gen;
6678 if ((m->oflags & VPO_UNMANAGED) != 0)
6680 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6684 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6686 if (!PMAP_TRYLOCK(pmap)) {
6687 md_gen = m->md.pv_gen;
6691 if (md_gen != m->md.pv_gen) {
6696 pte = pmap_pte(pmap, pv->pv_va);
6697 if ((*pte & PG_W) != 0)
6701 if ((m->flags & PG_FICTITIOUS) == 0) {
6702 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6703 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6705 if (!PMAP_TRYLOCK(pmap)) {
6706 md_gen = m->md.pv_gen;
6707 pvh_gen = pvh->pv_gen;
6711 if (md_gen != m->md.pv_gen ||
6712 pvh_gen != pvh->pv_gen) {
6717 pte = pmap_pde(pmap, pv->pv_va);
6718 if ((*pte & PG_W) != 0)
6728 * Returns TRUE if the given page is mapped individually or as part of
6729 * a 2mpage. Otherwise, returns FALSE.
6732 pmap_page_is_mapped(vm_page_t m)
6734 struct rwlock *lock;
6737 if ((m->oflags & VPO_UNMANAGED) != 0)
6739 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6741 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6742 ((m->flags & PG_FICTITIOUS) == 0 &&
6743 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6749 * Destroy all managed, non-wired mappings in the given user-space
6750 * pmap. This pmap cannot be active on any processor besides the
6753 * This function cannot be applied to the kernel pmap. Moreover, it
6754 * is not intended for general use. It is only to be used during
6755 * process termination. Consequently, it can be implemented in ways
6756 * that make it faster than pmap_remove(). First, it can more quickly
6757 * destroy mappings by iterating over the pmap's collection of PV
6758 * entries, rather than searching the page table. Second, it doesn't
6759 * have to test and clear the page table entries atomically, because
6760 * no processor is currently accessing the user address space. In
6761 * particular, a page table entry's dirty bit won't change state once
6762 * this function starts.
6764 * Although this function destroys all of the pmap's managed,
6765 * non-wired mappings, it can delay and batch the invalidation of TLB
6766 * entries without calling pmap_delayed_invl_start() and
6767 * pmap_delayed_invl_finish(). Because the pmap is not active on
6768 * any other processor, none of these TLB entries will ever be used
6769 * before their eventual invalidation. Consequently, there is no need
6770 * for either pmap_remove_all() or pmap_remove_write() to wait for
6771 * that eventual TLB invalidation.
6774 pmap_remove_pages(pmap_t pmap)
6777 pt_entry_t *pte, tpte;
6778 pt_entry_t PG_M, PG_RW, PG_V;
6779 struct spglist free;
6780 vm_page_t m, mpte, mt;
6782 struct md_page *pvh;
6783 struct pv_chunk *pc, *npc;
6784 struct rwlock *lock;
6786 uint64_t inuse, bitmask;
6787 int allfree, field, freed, idx;
6788 boolean_t superpage;
6792 * Assert that the given pmap is only active on the current
6793 * CPU. Unfortunately, we cannot block another CPU from
6794 * activating the pmap while this function is executing.
6796 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6799 cpuset_t other_cpus;
6801 other_cpus = all_cpus;
6803 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6804 CPU_AND(&other_cpus, &pmap->pm_active);
6806 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6811 PG_M = pmap_modified_bit(pmap);
6812 PG_V = pmap_valid_bit(pmap);
6813 PG_RW = pmap_rw_bit(pmap);
6817 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6820 for (field = 0; field < _NPCM; field++) {
6821 inuse = ~pc->pc_map[field] & pc_freemask[field];
6822 while (inuse != 0) {
6824 bitmask = 1UL << bit;
6825 idx = field * 64 + bit;
6826 pv = &pc->pc_pventry[idx];
6829 pte = pmap_pdpe(pmap, pv->pv_va);
6831 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6833 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6836 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6838 pte = &pte[pmap_pte_index(pv->pv_va)];
6842 * Keep track whether 'tpte' is a
6843 * superpage explicitly instead of
6844 * relying on PG_PS being set.
6846 * This is because PG_PS is numerically
6847 * identical to PG_PTE_PAT and thus a
6848 * regular page could be mistaken for
6854 if ((tpte & PG_V) == 0) {
6855 panic("bad pte va %lx pte %lx",
6860 * We cannot remove wired pages from a process' mapping at this time
6868 pa = tpte & PG_PS_FRAME;
6870 pa = tpte & PG_FRAME;
6872 m = PHYS_TO_VM_PAGE(pa);
6873 KASSERT(m->phys_addr == pa,
6874 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6875 m, (uintmax_t)m->phys_addr,
6878 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6879 m < &vm_page_array[vm_page_array_size],
6880 ("pmap_remove_pages: bad tpte %#jx",
6886 * Update the vm_page_t clean/reference bits.
6888 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6890 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6896 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6899 pc->pc_map[field] |= bitmask;
6901 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6902 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6903 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6905 if (TAILQ_EMPTY(&pvh->pv_list)) {
6906 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6907 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6908 TAILQ_EMPTY(&mt->md.pv_list))
6909 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6911 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6913 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6914 ("pmap_remove_pages: pte page not promoted"));
6915 pmap_resident_count_dec(pmap, 1);
6916 KASSERT(mpte->wire_count == NPTEPG,
6917 ("pmap_remove_pages: pte page wire count error"));
6918 mpte->wire_count = 0;
6919 pmap_add_delayed_free_list(mpte, &free, FALSE);
6922 pmap_resident_count_dec(pmap, 1);
6923 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6925 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6926 TAILQ_EMPTY(&m->md.pv_list) &&
6927 (m->flags & PG_FICTITIOUS) == 0) {
6928 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6929 if (TAILQ_EMPTY(&pvh->pv_list))
6930 vm_page_aflag_clear(m, PGA_WRITEABLE);
6933 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6937 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6938 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6939 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6941 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6947 pmap_invalidate_all(pmap);
6948 pmap_pkru_deassign_all(pmap);
6950 vm_page_free_pages_toq(&free, true);
6954 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6956 struct rwlock *lock;
6958 struct md_page *pvh;
6959 pt_entry_t *pte, mask;
6960 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6962 int md_gen, pvh_gen;
6966 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6969 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6971 if (!PMAP_TRYLOCK(pmap)) {
6972 md_gen = m->md.pv_gen;
6976 if (md_gen != m->md.pv_gen) {
6981 pte = pmap_pte(pmap, pv->pv_va);
6984 PG_M = pmap_modified_bit(pmap);
6985 PG_RW = pmap_rw_bit(pmap);
6986 mask |= PG_RW | PG_M;
6989 PG_A = pmap_accessed_bit(pmap);
6990 PG_V = pmap_valid_bit(pmap);
6991 mask |= PG_V | PG_A;
6993 rv = (*pte & mask) == mask;
6998 if ((m->flags & PG_FICTITIOUS) == 0) {
6999 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7000 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7002 if (!PMAP_TRYLOCK(pmap)) {
7003 md_gen = m->md.pv_gen;
7004 pvh_gen = pvh->pv_gen;
7008 if (md_gen != m->md.pv_gen ||
7009 pvh_gen != pvh->pv_gen) {
7014 pte = pmap_pde(pmap, pv->pv_va);
7017 PG_M = pmap_modified_bit(pmap);
7018 PG_RW = pmap_rw_bit(pmap);
7019 mask |= PG_RW | PG_M;
7022 PG_A = pmap_accessed_bit(pmap);
7023 PG_V = pmap_valid_bit(pmap);
7024 mask |= PG_V | PG_A;
7026 rv = (*pte & mask) == mask;
7040 * Return whether or not the specified physical page was modified
7041 * in any physical maps.
7044 pmap_is_modified(vm_page_t m)
7047 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7048 ("pmap_is_modified: page %p is not managed", m));
7051 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7052 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
7053 * is clear, no PTEs can have PG_M set.
7055 VM_OBJECT_ASSERT_WLOCKED(m->object);
7056 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7058 return (pmap_page_test_mappings(m, FALSE, TRUE));
7062 * pmap_is_prefaultable:
7064 * Return whether or not the specified virtual address is eligible
7068 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7071 pt_entry_t *pte, PG_V;
7074 PG_V = pmap_valid_bit(pmap);
7077 pde = pmap_pde(pmap, addr);
7078 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7079 pte = pmap_pde_to_pte(pde, addr);
7080 rv = (*pte & PG_V) == 0;
7087 * pmap_is_referenced:
7089 * Return whether or not the specified physical page was referenced
7090 * in any physical maps.
7093 pmap_is_referenced(vm_page_t m)
7096 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7097 ("pmap_is_referenced: page %p is not managed", m));
7098 return (pmap_page_test_mappings(m, TRUE, FALSE));
7102 * Clear the write and modified bits in each of the given page's mappings.
7105 pmap_remove_write(vm_page_t m)
7107 struct md_page *pvh;
7109 struct rwlock *lock;
7110 pv_entry_t next_pv, pv;
7112 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7114 int pvh_gen, md_gen;
7116 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7117 ("pmap_remove_write: page %p is not managed", m));
7120 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7121 * set by another thread while the object is locked. Thus,
7122 * if PGA_WRITEABLE is clear, no page table entries need updating.
7124 VM_OBJECT_ASSERT_WLOCKED(m->object);
7125 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7127 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7128 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7129 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7132 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7134 if (!PMAP_TRYLOCK(pmap)) {
7135 pvh_gen = pvh->pv_gen;
7139 if (pvh_gen != pvh->pv_gen) {
7145 PG_RW = pmap_rw_bit(pmap);
7147 pde = pmap_pde(pmap, va);
7148 if ((*pde & PG_RW) != 0)
7149 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7150 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7151 ("inconsistent pv lock %p %p for page %p",
7152 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7155 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7157 if (!PMAP_TRYLOCK(pmap)) {
7158 pvh_gen = pvh->pv_gen;
7159 md_gen = m->md.pv_gen;
7163 if (pvh_gen != pvh->pv_gen ||
7164 md_gen != m->md.pv_gen) {
7170 PG_M = pmap_modified_bit(pmap);
7171 PG_RW = pmap_rw_bit(pmap);
7172 pde = pmap_pde(pmap, pv->pv_va);
7173 KASSERT((*pde & PG_PS) == 0,
7174 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7176 pte = pmap_pde_to_pte(pde, pv->pv_va);
7179 if (oldpte & PG_RW) {
7180 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7183 if ((oldpte & PG_M) != 0)
7185 pmap_invalidate_page(pmap, pv->pv_va);
7190 vm_page_aflag_clear(m, PGA_WRITEABLE);
7191 pmap_delayed_invl_wait(m);
7194 static __inline boolean_t
7195 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7198 if (!pmap_emulate_ad_bits(pmap))
7201 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7204 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7205 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7206 * if the EPT_PG_WRITE bit is set.
7208 if ((pte & EPT_PG_WRITE) != 0)
7212 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7214 if ((pte & EPT_PG_EXECUTE) == 0 ||
7215 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7222 * pmap_ts_referenced:
7224 * Return a count of reference bits for a page, clearing those bits.
7225 * It is not necessary for every reference bit to be cleared, but it
7226 * is necessary that 0 only be returned when there are truly no
7227 * reference bits set.
7229 * As an optimization, update the page's dirty field if a modified bit is
7230 * found while counting reference bits. This opportunistic update can be
7231 * performed at low cost and can eliminate the need for some future calls
7232 * to pmap_is_modified(). However, since this function stops after
7233 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7234 * dirty pages. Those dirty pages will only be detected by a future call
7235 * to pmap_is_modified().
7237 * A DI block is not needed within this function, because
7238 * invalidations are performed before the PV list lock is
7242 pmap_ts_referenced(vm_page_t m)
7244 struct md_page *pvh;
7247 struct rwlock *lock;
7248 pd_entry_t oldpde, *pde;
7249 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7252 int cleared, md_gen, not_cleared, pvh_gen;
7253 struct spglist free;
7256 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7257 ("pmap_ts_referenced: page %p is not managed", m));
7260 pa = VM_PAGE_TO_PHYS(m);
7261 lock = PHYS_TO_PV_LIST_LOCK(pa);
7262 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7266 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7267 goto small_mappings;
7273 if (!PMAP_TRYLOCK(pmap)) {
7274 pvh_gen = pvh->pv_gen;
7278 if (pvh_gen != pvh->pv_gen) {
7283 PG_A = pmap_accessed_bit(pmap);
7284 PG_M = pmap_modified_bit(pmap);
7285 PG_RW = pmap_rw_bit(pmap);
7287 pde = pmap_pde(pmap, pv->pv_va);
7289 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7291 * Although "oldpde" is mapping a 2MB page, because
7292 * this function is called at a 4KB page granularity,
7293 * we only update the 4KB page under test.
7297 if ((oldpde & PG_A) != 0) {
7299 * Since this reference bit is shared by 512 4KB
7300 * pages, it should not be cleared every time it is
7301 * tested. Apply a simple "hash" function on the
7302 * physical page number, the virtual superpage number,
7303 * and the pmap address to select one 4KB page out of
7304 * the 512 on which testing the reference bit will
7305 * result in clearing that reference bit. This
7306 * function is designed to avoid the selection of the
7307 * same 4KB page for every 2MB page mapping.
7309 * On demotion, a mapping that hasn't been referenced
7310 * is simply destroyed. To avoid the possibility of a
7311 * subsequent page fault on a demoted wired mapping,
7312 * always leave its reference bit set. Moreover,
7313 * since the superpage is wired, the current state of
7314 * its reference bit won't affect page replacement.
7316 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7317 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7318 (oldpde & PG_W) == 0) {
7319 if (safe_to_clear_referenced(pmap, oldpde)) {
7320 atomic_clear_long(pde, PG_A);
7321 pmap_invalidate_page(pmap, pv->pv_va);
7323 } else if (pmap_demote_pde_locked(pmap, pde,
7324 pv->pv_va, &lock)) {
7326 * Remove the mapping to a single page
7327 * so that a subsequent access may
7328 * repromote. Since the underlying
7329 * page table page is fully populated,
7330 * this removal never frees a page
7334 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7336 pte = pmap_pde_to_pte(pde, va);
7337 pmap_remove_pte(pmap, pte, va, *pde,
7339 pmap_invalidate_page(pmap, va);
7345 * The superpage mapping was removed
7346 * entirely and therefore 'pv' is no
7354 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7355 ("inconsistent pv lock %p %p for page %p",
7356 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7361 /* Rotate the PV list if it has more than one entry. */
7362 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7363 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7364 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7367 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7369 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7371 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7378 if (!PMAP_TRYLOCK(pmap)) {
7379 pvh_gen = pvh->pv_gen;
7380 md_gen = m->md.pv_gen;
7384 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7389 PG_A = pmap_accessed_bit(pmap);
7390 PG_M = pmap_modified_bit(pmap);
7391 PG_RW = pmap_rw_bit(pmap);
7392 pde = pmap_pde(pmap, pv->pv_va);
7393 KASSERT((*pde & PG_PS) == 0,
7394 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7396 pte = pmap_pde_to_pte(pde, pv->pv_va);
7397 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7399 if ((*pte & PG_A) != 0) {
7400 if (safe_to_clear_referenced(pmap, *pte)) {
7401 atomic_clear_long(pte, PG_A);
7402 pmap_invalidate_page(pmap, pv->pv_va);
7404 } else if ((*pte & PG_W) == 0) {
7406 * Wired pages cannot be paged out so
7407 * doing accessed bit emulation for
7408 * them is wasted effort. We do the
7409 * hard work for unwired pages only.
7411 pmap_remove_pte(pmap, pte, pv->pv_va,
7412 *pde, &free, &lock);
7413 pmap_invalidate_page(pmap, pv->pv_va);
7418 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7419 ("inconsistent pv lock %p %p for page %p",
7420 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7425 /* Rotate the PV list if it has more than one entry. */
7426 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7427 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7428 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7431 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7432 not_cleared < PMAP_TS_REFERENCED_MAX);
7435 vm_page_free_pages_toq(&free, true);
7436 return (cleared + not_cleared);
7440 * Apply the given advice to the specified range of addresses within the
7441 * given pmap. Depending on the advice, clear the referenced and/or
7442 * modified flags in each mapping and set the mapped page's dirty field.
7445 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7447 struct rwlock *lock;
7448 pml4_entry_t *pml4e;
7450 pd_entry_t oldpde, *pde;
7451 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7452 vm_offset_t va, va_next;
7456 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7460 * A/D bit emulation requires an alternate code path when clearing
7461 * the modified and accessed bits below. Since this function is
7462 * advisory in nature we skip it entirely for pmaps that require
7463 * A/D bit emulation.
7465 if (pmap_emulate_ad_bits(pmap))
7468 PG_A = pmap_accessed_bit(pmap);
7469 PG_G = pmap_global_bit(pmap);
7470 PG_M = pmap_modified_bit(pmap);
7471 PG_V = pmap_valid_bit(pmap);
7472 PG_RW = pmap_rw_bit(pmap);
7474 pmap_delayed_invl_start();
7476 for (; sva < eva; sva = va_next) {
7477 pml4e = pmap_pml4e(pmap, sva);
7478 if ((*pml4e & PG_V) == 0) {
7479 va_next = (sva + NBPML4) & ~PML4MASK;
7484 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7485 if ((*pdpe & PG_V) == 0) {
7486 va_next = (sva + NBPDP) & ~PDPMASK;
7491 va_next = (sva + NBPDR) & ~PDRMASK;
7494 pde = pmap_pdpe_to_pde(pdpe, sva);
7496 if ((oldpde & PG_V) == 0)
7498 else if ((oldpde & PG_PS) != 0) {
7499 if ((oldpde & PG_MANAGED) == 0)
7502 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7507 * The large page mapping was destroyed.
7513 * Unless the page mappings are wired, remove the
7514 * mapping to a single page so that a subsequent
7515 * access may repromote. Choosing the last page
7516 * within the address range [sva, min(va_next, eva))
7517 * generally results in more repromotions. Since the
7518 * underlying page table page is fully populated, this
7519 * removal never frees a page table page.
7521 if ((oldpde & PG_W) == 0) {
7527 ("pmap_advise: no address gap"));
7528 pte = pmap_pde_to_pte(pde, va);
7529 KASSERT((*pte & PG_V) != 0,
7530 ("pmap_advise: invalid PTE"));
7531 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7541 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7543 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7545 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7546 if (advice == MADV_DONTNEED) {
7548 * Future calls to pmap_is_modified()
7549 * can be avoided by making the page
7552 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7555 atomic_clear_long(pte, PG_M | PG_A);
7556 } else if ((*pte & PG_A) != 0)
7557 atomic_clear_long(pte, PG_A);
7561 if ((*pte & PG_G) != 0) {
7568 if (va != va_next) {
7569 pmap_invalidate_range(pmap, va, sva);
7574 pmap_invalidate_range(pmap, va, sva);
7577 pmap_invalidate_all(pmap);
7579 pmap_delayed_invl_finish();
7583 * Clear the modify bits on the specified physical page.
7586 pmap_clear_modify(vm_page_t m)
7588 struct md_page *pvh;
7590 pv_entry_t next_pv, pv;
7591 pd_entry_t oldpde, *pde;
7592 pt_entry_t *pte, PG_M, PG_RW;
7593 struct rwlock *lock;
7595 int md_gen, pvh_gen;
7597 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7598 ("pmap_clear_modify: page %p is not managed", m));
7599 VM_OBJECT_ASSERT_WLOCKED(m->object);
7600 KASSERT(!vm_page_xbusied(m),
7601 ("pmap_clear_modify: page %p is exclusive busied", m));
7604 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7605 * If the object containing the page is locked and the page is not
7606 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7608 if ((m->aflags & PGA_WRITEABLE) == 0)
7610 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7611 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7612 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7615 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7617 if (!PMAP_TRYLOCK(pmap)) {
7618 pvh_gen = pvh->pv_gen;
7622 if (pvh_gen != pvh->pv_gen) {
7627 PG_M = pmap_modified_bit(pmap);
7628 PG_RW = pmap_rw_bit(pmap);
7630 pde = pmap_pde(pmap, va);
7632 /* If oldpde has PG_RW set, then it also has PG_M set. */
7633 if ((oldpde & PG_RW) != 0 &&
7634 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
7635 (oldpde & PG_W) == 0) {
7637 * Write protect the mapping to a single page so that
7638 * a subsequent write access may repromote.
7640 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
7641 pte = pmap_pde_to_pte(pde, va);
7642 atomic_clear_long(pte, PG_M | PG_RW);
7644 pmap_invalidate_page(pmap, va);
7648 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7650 if (!PMAP_TRYLOCK(pmap)) {
7651 md_gen = m->md.pv_gen;
7652 pvh_gen = pvh->pv_gen;
7656 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7661 PG_M = pmap_modified_bit(pmap);
7662 PG_RW = pmap_rw_bit(pmap);
7663 pde = pmap_pde(pmap, pv->pv_va);
7664 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7665 " a 2mpage in page %p's pv list", m));
7666 pte = pmap_pde_to_pte(pde, pv->pv_va);
7667 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7668 atomic_clear_long(pte, PG_M);
7669 pmap_invalidate_page(pmap, pv->pv_va);
7677 * Miscellaneous support routines follow
7680 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7681 static __inline void
7682 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7687 * The cache mode bits are all in the low 32-bits of the
7688 * PTE, so we can just spin on updating the low 32-bits.
7691 opte = *(u_int *)pte;
7692 npte = opte & ~mask;
7694 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7697 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7698 static __inline void
7699 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7704 * The cache mode bits are all in the low 32-bits of the
7705 * PDE, so we can just spin on updating the low 32-bits.
7708 opde = *(u_int *)pde;
7709 npde = opde & ~mask;
7711 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7715 * Map a set of physical memory pages into the kernel virtual
7716 * address space. Return a pointer to where it is mapped. This
7717 * routine is intended to be used for mapping device memory,
7721 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
7723 struct pmap_preinit_mapping *ppim;
7724 vm_offset_t va, offset;
7728 offset = pa & PAGE_MASK;
7729 size = round_page(offset + size);
7730 pa = trunc_page(pa);
7732 if (!pmap_initialized) {
7734 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7735 ppim = pmap_preinit_mapping + i;
7736 if (ppim->va == 0) {
7740 ppim->va = virtual_avail;
7741 virtual_avail += size;
7747 panic("%s: too many preinit mappings", __func__);
7750 * If we have a preinit mapping, re-use it.
7752 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7753 ppim = pmap_preinit_mapping + i;
7754 if (ppim->pa == pa && ppim->sz == size &&
7755 (ppim->mode == mode ||
7756 (flags & MAPDEV_SETATTR) == 0))
7757 return ((void *)(ppim->va + offset));
7760 * If the specified range of physical addresses fits within
7761 * the direct map window, use the direct map.
7763 if (pa < dmaplimit && pa + size <= dmaplimit) {
7764 va = PHYS_TO_DMAP(pa);
7765 if ((flags & MAPDEV_SETATTR) != 0) {
7766 PMAP_LOCK(kernel_pmap);
7767 i = pmap_change_attr_locked(va, size, mode, flags);
7768 PMAP_UNLOCK(kernel_pmap);
7772 return ((void *)(va + offset));
7774 va = kva_alloc(size);
7776 panic("%s: Couldn't allocate KVA", __func__);
7778 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7779 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7780 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7781 if ((flags & MAPDEV_FLUSHCACHE) != 0)
7782 pmap_invalidate_cache_range(va, va + tmpsize);
7783 return ((void *)(va + offset));
7787 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7790 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
7795 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7798 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
7802 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7805 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
7810 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7813 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
7814 MAPDEV_FLUSHCACHE));
7818 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7820 struct pmap_preinit_mapping *ppim;
7824 /* If we gave a direct map region in pmap_mapdev, do nothing */
7825 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7827 offset = va & PAGE_MASK;
7828 size = round_page(offset + size);
7829 va = trunc_page(va);
7830 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7831 ppim = pmap_preinit_mapping + i;
7832 if (ppim->va == va && ppim->sz == size) {
7833 if (pmap_initialized)
7839 if (va + size == virtual_avail)
7844 if (pmap_initialized)
7849 * Tries to demote a 1GB page mapping.
7852 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7854 pdp_entry_t newpdpe, oldpdpe;
7855 pd_entry_t *firstpde, newpde, *pde;
7856 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7860 PG_A = pmap_accessed_bit(pmap);
7861 PG_M = pmap_modified_bit(pmap);
7862 PG_V = pmap_valid_bit(pmap);
7863 PG_RW = pmap_rw_bit(pmap);
7865 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7867 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7868 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7869 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7870 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7871 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7872 " in pmap %p", va, pmap);
7875 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7876 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7877 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7878 KASSERT((oldpdpe & PG_A) != 0,
7879 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7880 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7881 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7885 * Initialize the page directory page.
7887 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7893 * Demote the mapping.
7898 * Invalidate a stale recursive mapping of the page directory page.
7900 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7902 pmap_pdpe_demotions++;
7903 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7904 " in pmap %p", va, pmap);
7909 * Sets the memory attribute for the specified page.
7912 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7915 m->md.pat_mode = ma;
7918 * If "m" is a normal page, update its direct mapping. This update
7919 * can be relied upon to perform any cache operations that are
7920 * required for data coherence.
7922 if ((m->flags & PG_FICTITIOUS) == 0 &&
7923 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7925 panic("memory attribute change on the direct map failed");
7929 * Changes the specified virtual address range's memory type to that given by
7930 * the parameter "mode". The specified virtual address range must be
7931 * completely contained within either the direct map or the kernel map. If
7932 * the virtual address range is contained within the kernel map, then the
7933 * memory type for each of the corresponding ranges of the direct map is also
7934 * changed. (The corresponding ranges of the direct map are those ranges that
7935 * map the same physical pages as the specified virtual address range.) These
7936 * changes to the direct map are necessary because Intel describes the
7937 * behavior of their processors as "undefined" if two or more mappings to the
7938 * same physical page have different memory types.
7940 * Returns zero if the change completed successfully, and either EINVAL or
7941 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7942 * of the virtual address range was not mapped, and ENOMEM is returned if
7943 * there was insufficient memory available to complete the change. In the
7944 * latter case, the memory type may have been changed on some part of the
7945 * virtual address range or the direct map.
7948 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7952 PMAP_LOCK(kernel_pmap);
7953 error = pmap_change_attr_locked(va, size, mode, MAPDEV_FLUSHCACHE);
7954 PMAP_UNLOCK(kernel_pmap);
7959 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, int flags)
7961 vm_offset_t base, offset, tmpva;
7962 vm_paddr_t pa_start, pa_end, pa_end1;
7966 int cache_bits_pte, cache_bits_pde, error;
7969 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7970 base = trunc_page(va);
7971 offset = va & PAGE_MASK;
7972 size = round_page(offset + size);
7975 * Only supported on kernel virtual addresses, including the direct
7976 * map but excluding the recursive map.
7978 if (base < DMAP_MIN_ADDRESS)
7981 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7982 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7986 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7987 * into 4KB pages if required.
7989 for (tmpva = base; tmpva < base + size; ) {
7990 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7991 if (pdpe == NULL || *pdpe == 0)
7993 if (*pdpe & PG_PS) {
7995 * If the current 1GB page already has the required
7996 * memory type, then we need not demote this page. Just
7997 * increment tmpva to the next 1GB page frame.
7999 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
8000 tmpva = trunc_1gpage(tmpva) + NBPDP;
8005 * If the current offset aligns with a 1GB page frame
8006 * and there is at least 1GB left within the range, then
8007 * we need not break down this page into 2MB pages.
8009 if ((tmpva & PDPMASK) == 0 &&
8010 tmpva + PDPMASK < base + size) {
8014 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8017 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8022 * If the current 2MB page already has the required
8023 * memory type, then we need not demote this page. Just
8024 * increment tmpva to the next 2MB page frame.
8026 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
8027 tmpva = trunc_2mpage(tmpva) + NBPDR;
8032 * If the current offset aligns with a 2MB page frame
8033 * and there is at least 2MB left within the range, then
8034 * we need not break down this page into 4KB pages.
8036 if ((tmpva & PDRMASK) == 0 &&
8037 tmpva + PDRMASK < base + size) {
8041 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8044 pte = pmap_pde_to_pte(pde, tmpva);
8052 * Ok, all the pages exist, so run through them updating their
8053 * cache mode if required.
8055 pa_start = pa_end = 0;
8056 for (tmpva = base; tmpva < base + size; ) {
8057 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8058 if (*pdpe & PG_PS) {
8059 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
8060 pmap_pde_attr(pdpe, cache_bits_pde,
8064 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8065 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8066 if (pa_start == pa_end) {
8067 /* Start physical address run. */
8068 pa_start = *pdpe & PG_PS_FRAME;
8069 pa_end = pa_start + NBPDP;
8070 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8073 /* Run ended, update direct map. */
8074 error = pmap_change_attr_locked(
8075 PHYS_TO_DMAP(pa_start),
8076 pa_end - pa_start, mode, flags);
8079 /* Start physical address run. */
8080 pa_start = *pdpe & PG_PS_FRAME;
8081 pa_end = pa_start + NBPDP;
8084 tmpva = trunc_1gpage(tmpva) + NBPDP;
8087 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8089 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
8090 pmap_pde_attr(pde, cache_bits_pde,
8094 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8095 (*pde & PG_PS_FRAME) < dmaplimit) {
8096 if (pa_start == pa_end) {
8097 /* Start physical address run. */
8098 pa_start = *pde & PG_PS_FRAME;
8099 pa_end = pa_start + NBPDR;
8100 } else if (pa_end == (*pde & PG_PS_FRAME))
8103 /* Run ended, update direct map. */
8104 error = pmap_change_attr_locked(
8105 PHYS_TO_DMAP(pa_start),
8106 pa_end - pa_start, mode, flags);
8109 /* Start physical address run. */
8110 pa_start = *pde & PG_PS_FRAME;
8111 pa_end = pa_start + NBPDR;
8114 tmpva = trunc_2mpage(tmpva) + NBPDR;
8116 pte = pmap_pde_to_pte(pde, tmpva);
8117 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
8118 pmap_pte_attr(pte, cache_bits_pte,
8122 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8123 (*pte & PG_FRAME) < dmaplimit) {
8124 if (pa_start == pa_end) {
8125 /* Start physical address run. */
8126 pa_start = *pte & PG_FRAME;
8127 pa_end = pa_start + PAGE_SIZE;
8128 } else if (pa_end == (*pte & PG_FRAME))
8129 pa_end += PAGE_SIZE;
8131 /* Run ended, update direct map. */
8132 error = pmap_change_attr_locked(
8133 PHYS_TO_DMAP(pa_start),
8134 pa_end - pa_start, mode, flags);
8137 /* Start physical address run. */
8138 pa_start = *pte & PG_FRAME;
8139 pa_end = pa_start + PAGE_SIZE;
8145 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8146 pa_end1 = MIN(pa_end, dmaplimit);
8147 if (pa_start != pa_end1)
8148 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
8149 pa_end1 - pa_start, mode, flags);
8153 * Flush CPU caches if required to make sure any data isn't cached that
8154 * shouldn't be, etc.
8157 pmap_invalidate_range(kernel_pmap, base, tmpva);
8158 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8159 pmap_invalidate_cache_range(base, tmpva);
8165 * Demotes any mapping within the direct map region that covers more than the
8166 * specified range of physical addresses. This range's size must be a power
8167 * of two and its starting address must be a multiple of its size. Since the
8168 * demotion does not change any attributes of the mapping, a TLB invalidation
8169 * is not mandatory. The caller may, however, request a TLB invalidation.
8172 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8181 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8182 KASSERT((base & (len - 1)) == 0,
8183 ("pmap_demote_DMAP: base is not a multiple of len"));
8184 if (len < NBPDP && base < dmaplimit) {
8185 va = PHYS_TO_DMAP(base);
8187 PMAP_LOCK(kernel_pmap);
8188 pdpe = pmap_pdpe(kernel_pmap, va);
8189 if ((*pdpe & X86_PG_V) == 0)
8190 panic("pmap_demote_DMAP: invalid PDPE");
8191 if ((*pdpe & PG_PS) != 0) {
8192 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8193 panic("pmap_demote_DMAP: PDPE failed");
8197 pde = pmap_pdpe_to_pde(pdpe, va);
8198 if ((*pde & X86_PG_V) == 0)
8199 panic("pmap_demote_DMAP: invalid PDE");
8200 if ((*pde & PG_PS) != 0) {
8201 if (!pmap_demote_pde(kernel_pmap, pde, va))
8202 panic("pmap_demote_DMAP: PDE failed");
8206 if (changed && invalidate)
8207 pmap_invalidate_page(kernel_pmap, va);
8208 PMAP_UNLOCK(kernel_pmap);
8213 * perform the pmap work for mincore
8216 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8219 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8223 PG_A = pmap_accessed_bit(pmap);
8224 PG_M = pmap_modified_bit(pmap);
8225 PG_V = pmap_valid_bit(pmap);
8226 PG_RW = pmap_rw_bit(pmap);
8230 pdep = pmap_pde(pmap, addr);
8231 if (pdep != NULL && (*pdep & PG_V)) {
8232 if (*pdep & PG_PS) {
8234 /* Compute the physical address of the 4KB page. */
8235 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8237 val = MINCORE_SUPER;
8239 pte = *pmap_pde_to_pte(pdep, addr);
8240 pa = pte & PG_FRAME;
8248 if ((pte & PG_V) != 0) {
8249 val |= MINCORE_INCORE;
8250 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8251 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8252 if ((pte & PG_A) != 0)
8253 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8255 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8256 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8257 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8258 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8259 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8262 PA_UNLOCK_COND(*locked_pa);
8268 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8270 uint32_t gen, new_gen, pcid_next;
8272 CRITICAL_ASSERT(curthread);
8273 gen = PCPU_GET(pcid_gen);
8274 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8275 return (pti ? 0 : CR3_PCID_SAVE);
8276 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8277 return (CR3_PCID_SAVE);
8278 pcid_next = PCPU_GET(pcid_next);
8279 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8280 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8281 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8282 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8283 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8287 PCPU_SET(pcid_gen, new_gen);
8288 pcid_next = PMAP_PCID_KERN + 1;
8292 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8293 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8294 PCPU_SET(pcid_next, pcid_next + 1);
8299 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8303 cached = pmap_pcid_alloc(pmap, cpuid);
8304 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8305 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8306 pmap->pm_pcids[cpuid].pm_pcid));
8307 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8308 pmap == kernel_pmap,
8309 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8310 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8315 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8318 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8319 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
8323 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8325 struct invpcid_descr d;
8326 uint64_t cached, cr3, kcr3, ucr3;
8328 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8330 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8331 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8332 PCPU_SET(curpmap, pmap);
8333 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8334 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8337 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8339 * Explicitly invalidate translations cached from the
8340 * user page table. They are not automatically
8341 * flushed by reload of cr3 with the kernel page table
8344 * Note that the if() condition is resolved statically
8345 * by using the function argument instead of
8346 * runtime-evaluated invpcid_works value.
8348 if (invpcid_works1) {
8349 d.pcid = PMAP_PCID_USER_PT |
8350 pmap->pm_pcids[cpuid].pm_pcid;
8353 invpcid(&d, INVPCID_CTX);
8355 pmap_pti_pcid_invalidate(ucr3, kcr3);
8359 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8360 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8362 PCPU_INC(pm_save_cnt);
8366 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8369 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8370 pmap_activate_sw_pti_post(td, pmap);
8374 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8380 * If the INVPCID instruction is not available,
8381 * invltlb_pcid_handler() is used to handle an invalidate_all
8382 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8383 * sequence of operations has a window where %CR3 is loaded
8384 * with the new pmap's PML4 address, but the curpmap value has
8385 * not yet been updated. This causes the invltlb IPI handler,
8386 * which is called between the updates, to execute as a NOP,
8387 * which leaves stale TLB entries.
8389 * Note that the most typical use of pmap_activate_sw(), from
8390 * the context switch, is immune to this race, because
8391 * interrupts are disabled (while the thread lock is owned),
8392 * and the IPI happens after curpmap is updated. Protect
8393 * other callers in a similar way, by disabling interrupts
8394 * around the %cr3 register reload and curpmap assignment.
8396 rflags = intr_disable();
8397 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8398 intr_restore(rflags);
8399 pmap_activate_sw_pti_post(td, pmap);
8403 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8406 uint64_t cached, cr3;
8408 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8410 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8411 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8413 PCPU_SET(curpmap, pmap);
8415 PCPU_INC(pm_save_cnt);
8419 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8424 rflags = intr_disable();
8425 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8426 intr_restore(rflags);
8430 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8431 u_int cpuid __unused)
8434 load_cr3(pmap->pm_cr3);
8435 PCPU_SET(curpmap, pmap);
8439 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8440 u_int cpuid __unused)
8443 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8444 PCPU_SET(kcr3, pmap->pm_cr3);
8445 PCPU_SET(ucr3, pmap->pm_ucr3);
8446 pmap_activate_sw_pti_post(td, pmap);
8449 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8453 if (pmap_pcid_enabled && pti && invpcid_works)
8454 return (pmap_activate_sw_pcid_invpcid_pti);
8455 else if (pmap_pcid_enabled && pti && !invpcid_works)
8456 return (pmap_activate_sw_pcid_noinvpcid_pti);
8457 else if (pmap_pcid_enabled && !pti && invpcid_works)
8458 return (pmap_activate_sw_pcid_nopti);
8459 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8460 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8461 else if (!pmap_pcid_enabled && pti)
8462 return (pmap_activate_sw_nopcid_pti);
8463 else /* if (!pmap_pcid_enabled && !pti) */
8464 return (pmap_activate_sw_nopcid_nopti);
8468 pmap_activate_sw(struct thread *td)
8470 pmap_t oldpmap, pmap;
8473 oldpmap = PCPU_GET(curpmap);
8474 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8475 if (oldpmap == pmap)
8477 cpuid = PCPU_GET(cpuid);
8479 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8481 CPU_SET(cpuid, &pmap->pm_active);
8483 pmap_activate_sw_mode(td, pmap, cpuid);
8485 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8487 CPU_CLR(cpuid, &oldpmap->pm_active);
8492 pmap_activate(struct thread *td)
8496 pmap_activate_sw(td);
8501 pmap_activate_boot(pmap_t pmap)
8507 * kernel_pmap must be never deactivated, and we ensure that
8508 * by never activating it at all.
8510 MPASS(pmap != kernel_pmap);
8512 cpuid = PCPU_GET(cpuid);
8514 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8516 CPU_SET(cpuid, &pmap->pm_active);
8518 PCPU_SET(curpmap, pmap);
8520 kcr3 = pmap->pm_cr3;
8521 if (pmap_pcid_enabled)
8522 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8526 PCPU_SET(kcr3, kcr3);
8527 PCPU_SET(ucr3, PMAP_NO_CR3);
8531 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8536 * Increase the starting virtual address of the given mapping if a
8537 * different alignment might result in more superpage mappings.
8540 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8541 vm_offset_t *addr, vm_size_t size)
8543 vm_offset_t superpage_offset;
8547 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8548 offset += ptoa(object->pg_color);
8549 superpage_offset = offset & PDRMASK;
8550 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8551 (*addr & PDRMASK) == superpage_offset)
8553 if ((*addr & PDRMASK) < superpage_offset)
8554 *addr = (*addr & ~PDRMASK) + superpage_offset;
8556 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8560 static unsigned long num_dirty_emulations;
8561 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8562 &num_dirty_emulations, 0, NULL);
8564 static unsigned long num_accessed_emulations;
8565 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8566 &num_accessed_emulations, 0, NULL);
8568 static unsigned long num_superpage_accessed_emulations;
8569 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8570 &num_superpage_accessed_emulations, 0, NULL);
8572 static unsigned long ad_emulation_superpage_promotions;
8573 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8574 &ad_emulation_superpage_promotions, 0, NULL);
8575 #endif /* INVARIANTS */
8578 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8581 struct rwlock *lock;
8582 #if VM_NRESERVLEVEL > 0
8586 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8588 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8589 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8591 if (!pmap_emulate_ad_bits(pmap))
8594 PG_A = pmap_accessed_bit(pmap);
8595 PG_M = pmap_modified_bit(pmap);
8596 PG_V = pmap_valid_bit(pmap);
8597 PG_RW = pmap_rw_bit(pmap);
8603 pde = pmap_pde(pmap, va);
8604 if (pde == NULL || (*pde & PG_V) == 0)
8607 if ((*pde & PG_PS) != 0) {
8608 if (ftype == VM_PROT_READ) {
8610 atomic_add_long(&num_superpage_accessed_emulations, 1);
8618 pte = pmap_pde_to_pte(pde, va);
8619 if ((*pte & PG_V) == 0)
8622 if (ftype == VM_PROT_WRITE) {
8623 if ((*pte & PG_RW) == 0)
8626 * Set the modified and accessed bits simultaneously.
8628 * Intel EPT PTEs that do software emulation of A/D bits map
8629 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8630 * An EPT misconfiguration is triggered if the PTE is writable
8631 * but not readable (WR=10). This is avoided by setting PG_A
8632 * and PG_M simultaneously.
8634 *pte |= PG_M | PG_A;
8639 #if VM_NRESERVLEVEL > 0
8640 /* try to promote the mapping */
8641 if (va < VM_MAXUSER_ADDRESS)
8642 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8646 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8648 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8649 pmap_ps_enabled(pmap) &&
8650 (m->flags & PG_FICTITIOUS) == 0 &&
8651 vm_reserv_level_iffullpop(m) == 0) {
8652 pmap_promote_pde(pmap, pde, va, &lock);
8654 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8660 if (ftype == VM_PROT_WRITE)
8661 atomic_add_long(&num_dirty_emulations, 1);
8663 atomic_add_long(&num_accessed_emulations, 1);
8665 rv = 0; /* success */
8674 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8679 pt_entry_t *pte, PG_V;
8683 PG_V = pmap_valid_bit(pmap);
8686 pml4 = pmap_pml4e(pmap, va);
8688 if ((*pml4 & PG_V) == 0)
8691 pdp = pmap_pml4e_to_pdpe(pml4, va);
8693 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8696 pde = pmap_pdpe_to_pde(pdp, va);
8698 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8701 pte = pmap_pde_to_pte(pde, va);
8710 * Get the kernel virtual address of a set of physical pages. If there are
8711 * physical addresses not covered by the DMAP perform a transient mapping
8712 * that will be removed when calling pmap_unmap_io_transient.
8714 * \param page The pages the caller wishes to obtain the virtual
8715 * address on the kernel memory map.
8716 * \param vaddr On return contains the kernel virtual memory address
8717 * of the pages passed in the page parameter.
8718 * \param count Number of pages passed in.
8719 * \param can_fault TRUE if the thread using the mapped pages can take
8720 * page faults, FALSE otherwise.
8722 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8723 * finished or FALSE otherwise.
8727 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8728 boolean_t can_fault)
8731 boolean_t needs_mapping;
8733 int cache_bits, error __unused, i;
8736 * Allocate any KVA space that we need, this is done in a separate
8737 * loop to prevent calling vmem_alloc while pinned.
8739 needs_mapping = FALSE;
8740 for (i = 0; i < count; i++) {
8741 paddr = VM_PAGE_TO_PHYS(page[i]);
8742 if (__predict_false(paddr >= dmaplimit)) {
8743 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8744 M_BESTFIT | M_WAITOK, &vaddr[i]);
8745 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8746 needs_mapping = TRUE;
8748 vaddr[i] = PHYS_TO_DMAP(paddr);
8752 /* Exit early if everything is covered by the DMAP */
8757 * NB: The sequence of updating a page table followed by accesses
8758 * to the corresponding pages used in the !DMAP case is subject to
8759 * the situation described in the "AMD64 Architecture Programmer's
8760 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8761 * Coherency Considerations". Therefore, issuing the INVLPG right
8762 * after modifying the PTE bits is crucial.
8766 for (i = 0; i < count; i++) {
8767 paddr = VM_PAGE_TO_PHYS(page[i]);
8768 if (paddr >= dmaplimit) {
8771 * Slow path, since we can get page faults
8772 * while mappings are active don't pin the
8773 * thread to the CPU and instead add a global
8774 * mapping visible to all CPUs.
8776 pmap_qenter(vaddr[i], &page[i], 1);
8778 pte = vtopte(vaddr[i]);
8779 cache_bits = pmap_cache_bits(kernel_pmap,
8780 page[i]->md.pat_mode, 0);
8781 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8788 return (needs_mapping);
8792 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8793 boolean_t can_fault)
8800 for (i = 0; i < count; i++) {
8801 paddr = VM_PAGE_TO_PHYS(page[i]);
8802 if (paddr >= dmaplimit) {
8804 pmap_qremove(vaddr[i], 1);
8805 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8811 pmap_quick_enter_page(vm_page_t m)
8815 paddr = VM_PAGE_TO_PHYS(m);
8816 if (paddr < dmaplimit)
8817 return (PHYS_TO_DMAP(paddr));
8818 mtx_lock_spin(&qframe_mtx);
8819 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8820 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8821 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8826 pmap_quick_remove_page(vm_offset_t addr)
8831 pte_store(vtopte(qframe), 0);
8833 mtx_unlock_spin(&qframe_mtx);
8837 * Pdp pages from the large map are managed differently from either
8838 * kernel or user page table pages. They are permanently allocated at
8839 * initialization time, and their wire count is permanently set to
8840 * zero. The pml4 entries pointing to those pages are copied into
8841 * each allocated pmap.
8843 * In contrast, pd and pt pages are managed like user page table
8844 * pages. They are dynamically allocated, and their wire count
8845 * represents the number of valid entries within the page.
8848 pmap_large_map_getptp_unlocked(void)
8852 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8854 if (m != NULL && (m->flags & PG_ZERO) == 0)
8860 pmap_large_map_getptp(void)
8864 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8865 m = pmap_large_map_getptp_unlocked();
8867 PMAP_UNLOCK(kernel_pmap);
8869 PMAP_LOCK(kernel_pmap);
8870 /* Callers retry. */
8875 static pdp_entry_t *
8876 pmap_large_map_pdpe(vm_offset_t va)
8878 vm_pindex_t pml4_idx;
8881 pml4_idx = pmap_pml4e_index(va);
8882 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8883 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8885 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8886 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8887 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8888 "LMSPML4I %#jx lm_ents %d",
8889 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8890 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8891 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8895 pmap_large_map_pde(vm_offset_t va)
8902 pdpe = pmap_large_map_pdpe(va);
8904 m = pmap_large_map_getptp();
8907 mphys = VM_PAGE_TO_PHYS(m);
8908 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8910 MPASS((*pdpe & X86_PG_PS) == 0);
8911 mphys = *pdpe & PG_FRAME;
8913 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
8917 pmap_large_map_pte(vm_offset_t va)
8924 pde = pmap_large_map_pde(va);
8926 m = pmap_large_map_getptp();
8929 mphys = VM_PAGE_TO_PHYS(m);
8930 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8931 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
8933 MPASS((*pde & X86_PG_PS) == 0);
8934 mphys = *pde & PG_FRAME;
8936 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
8940 pmap_large_map_kextract(vm_offset_t va)
8942 pdp_entry_t *pdpe, pdp;
8943 pd_entry_t *pde, pd;
8944 pt_entry_t *pte, pt;
8946 KASSERT(LARGEMAP_MIN_ADDRESS <= va && va < PMAP_LARGEMAP_MAX_ADDRESS(),
8947 ("not largemap range %#lx", (u_long)va));
8948 pdpe = pmap_large_map_pdpe(va);
8950 KASSERT((pdp & X86_PG_V) != 0,
8951 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
8952 (u_long)pdpe, pdp));
8953 if ((pdp & X86_PG_PS) != 0) {
8954 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
8955 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
8956 (u_long)pdpe, pdp));
8957 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
8959 pde = pmap_pdpe_to_pde(pdpe, va);
8961 KASSERT((pd & X86_PG_V) != 0,
8962 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
8963 if ((pd & X86_PG_PS) != 0)
8964 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
8965 pte = pmap_pde_to_pte(pde, va);
8967 KASSERT((pt & X86_PG_V) != 0,
8968 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
8969 return ((pt & PG_FRAME) | (va & PAGE_MASK));
8973 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
8974 vmem_addr_t *vmem_res)
8978 * Large mappings are all but static. Consequently, there
8979 * is no point in waiting for an earlier allocation to be
8982 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
8983 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
8987 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
8993 vm_offset_t va, inc;
8994 vmem_addr_t vmem_res;
8998 if (len == 0 || spa + len < spa)
9001 /* See if DMAP can serve. */
9002 if (spa + len <= dmaplimit) {
9003 va = PHYS_TO_DMAP(spa);
9005 return (pmap_change_attr(va, len, mattr));
9009 * No, allocate KVA. Fit the address with best possible
9010 * alignment for superpages. Fall back to worse align if
9014 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9015 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9016 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9018 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9020 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9023 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9028 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9029 * in the pagetable to minimize flushing. No need to
9030 * invalidate TLB, since we only update invalid entries.
9032 PMAP_LOCK(kernel_pmap);
9033 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9035 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9036 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9037 pdpe = pmap_large_map_pdpe(va);
9039 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9040 X86_PG_V | X86_PG_A | pg_nx |
9041 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9043 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9044 (va & PDRMASK) == 0) {
9045 pde = pmap_large_map_pde(va);
9047 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9048 X86_PG_V | X86_PG_A | pg_nx |
9049 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9050 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9054 pte = pmap_large_map_pte(va);
9056 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9057 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9059 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9064 PMAP_UNLOCK(kernel_pmap);
9067 *addr = (void *)vmem_res;
9072 pmap_large_unmap(void *svaa, vm_size_t len)
9074 vm_offset_t sva, va;
9076 pdp_entry_t *pdpe, pdp;
9077 pd_entry_t *pde, pd;
9080 struct spglist spgf;
9082 sva = (vm_offset_t)svaa;
9083 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9084 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9088 KASSERT(LARGEMAP_MIN_ADDRESS <= sva &&
9089 sva + len <= PMAP_LARGEMAP_MAX_ADDRESS(),
9090 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9091 PMAP_LOCK(kernel_pmap);
9092 for (va = sva; va < sva + len; va += inc) {
9093 pdpe = pmap_large_map_pdpe(va);
9095 KASSERT((pdp & X86_PG_V) != 0,
9096 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9097 (u_long)pdpe, pdp));
9098 if ((pdp & X86_PG_PS) != 0) {
9099 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9100 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9101 (u_long)pdpe, pdp));
9102 KASSERT((va & PDPMASK) == 0,
9103 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9104 (u_long)pdpe, pdp));
9105 KASSERT(va + NBPDP <= sva + len,
9106 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9107 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9108 (u_long)pdpe, pdp, len));
9113 pde = pmap_pdpe_to_pde(pdpe, va);
9115 KASSERT((pd & X86_PG_V) != 0,
9116 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9118 if ((pd & X86_PG_PS) != 0) {
9119 KASSERT((va & PDRMASK) == 0,
9120 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9122 KASSERT(va + NBPDR <= sva + len,
9123 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9124 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9128 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9130 if (m->wire_count == 0) {
9132 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9136 pte = pmap_pde_to_pte(pde, va);
9137 KASSERT((*pte & X86_PG_V) != 0,
9138 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9139 (u_long)pte, *pte));
9142 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9144 if (m->wire_count == 0) {
9146 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9147 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9149 if (m->wire_count == 0) {
9151 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9155 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9156 PMAP_UNLOCK(kernel_pmap);
9157 vm_page_free_pages_toq(&spgf, false);
9158 vmem_free(large_vmem, sva, len);
9162 pmap_large_map_wb_fence_mfence(void)
9169 pmap_large_map_wb_fence_sfence(void)
9176 pmap_large_map_wb_fence_nop(void)
9180 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9183 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9184 return (pmap_large_map_wb_fence_mfence);
9185 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9186 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9187 return (pmap_large_map_wb_fence_sfence);
9189 /* clflush is strongly enough ordered */
9190 return (pmap_large_map_wb_fence_nop);
9194 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9197 for (; len > 0; len -= cpu_clflush_line_size,
9198 va += cpu_clflush_line_size)
9203 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9206 for (; len > 0; len -= cpu_clflush_line_size,
9207 va += cpu_clflush_line_size)
9212 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9215 for (; len > 0; len -= cpu_clflush_line_size,
9216 va += cpu_clflush_line_size)
9221 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9225 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9228 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9229 return (pmap_large_map_flush_range_clwb);
9230 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9231 return (pmap_large_map_flush_range_clflushopt);
9232 else if ((cpu_feature & CPUID_CLFSH) != 0)
9233 return (pmap_large_map_flush_range_clflush);
9235 return (pmap_large_map_flush_range_nop);
9239 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9241 volatile u_long *pe;
9247 for (va = sva; va < eva; va += inc) {
9249 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9250 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9252 if ((p & X86_PG_PS) != 0)
9256 pe = (volatile u_long *)pmap_large_map_pde(va);
9258 if ((p & X86_PG_PS) != 0)
9262 pe = (volatile u_long *)pmap_large_map_pte(va);
9268 if ((p & X86_PG_AVAIL1) != 0) {
9270 * Spin-wait for the end of a parallel
9277 * If we saw other write-back
9278 * occuring, we cannot rely on PG_M to
9279 * indicate state of the cache. The
9280 * PG_M bit is cleared before the
9281 * flush to avoid ignoring new writes,
9282 * and writes which are relevant for
9283 * us might happen after.
9289 if ((p & X86_PG_M) != 0 || seen_other) {
9290 if (!atomic_fcmpset_long(pe, &p,
9291 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9293 * If we saw PG_M without
9294 * PG_AVAIL1, and then on the
9295 * next attempt we do not
9296 * observe either PG_M or
9297 * PG_AVAIL1, the other
9298 * write-back started after us
9299 * and finished before us. We
9300 * can rely on it doing our
9304 pmap_large_map_flush_range(va, inc);
9305 atomic_clear_long(pe, X86_PG_AVAIL1);
9314 * Write-back cache lines for the given address range.
9316 * Must be called only on the range or sub-range returned from
9317 * pmap_large_map(). Must not be called on the coalesced ranges.
9319 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9320 * instructions support.
9323 pmap_large_map_wb(void *svap, vm_size_t len)
9325 vm_offset_t eva, sva;
9327 sva = (vm_offset_t)svap;
9329 pmap_large_map_wb_fence();
9330 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9331 pmap_large_map_flush_range(sva, len);
9333 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9334 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9335 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9336 pmap_large_map_wb_large(sva, eva);
9338 pmap_large_map_wb_fence();
9342 pmap_pti_alloc_page(void)
9346 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9347 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9348 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9353 pmap_pti_free_page(vm_page_t m)
9356 KASSERT(m->wire_count > 0, ("page %p not wired", m));
9357 if (!vm_page_unwire_noq(m))
9359 vm_page_free_zero(m);
9373 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9374 VM_OBJECT_WLOCK(pti_obj);
9375 pml4_pg = pmap_pti_alloc_page();
9376 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9377 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9378 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9379 pdpe = pmap_pti_pdpe(va);
9380 pmap_pti_wire_pte(pdpe);
9382 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9383 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9384 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9385 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9386 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9387 sizeof(struct gate_descriptor) * NIDT, false);
9388 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9389 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9391 /* Doublefault stack IST 1 */
9392 va = common_tss[i].tss_ist1;
9393 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9394 /* NMI stack IST 2 */
9395 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9396 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9397 /* MC# stack IST 3 */
9398 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9399 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9400 /* DB# stack IST 4 */
9401 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9402 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9404 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9405 (vm_offset_t)etext, true);
9406 pti_finalized = true;
9407 VM_OBJECT_WUNLOCK(pti_obj);
9409 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9411 static pdp_entry_t *
9412 pmap_pti_pdpe(vm_offset_t va)
9414 pml4_entry_t *pml4e;
9417 vm_pindex_t pml4_idx;
9420 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9422 pml4_idx = pmap_pml4e_index(va);
9423 pml4e = &pti_pml4[pml4_idx];
9427 panic("pml4 alloc after finalization\n");
9428 m = pmap_pti_alloc_page();
9430 pmap_pti_free_page(m);
9431 mphys = *pml4e & ~PAGE_MASK;
9433 mphys = VM_PAGE_TO_PHYS(m);
9434 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9437 mphys = *pml4e & ~PAGE_MASK;
9439 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9444 pmap_pti_wire_pte(void *pte)
9448 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9449 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9454 pmap_pti_unwire_pde(void *pde, bool only_ref)
9458 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9459 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9460 MPASS(m->wire_count > 0);
9461 MPASS(only_ref || m->wire_count > 1);
9462 pmap_pti_free_page(m);
9466 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9471 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9472 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9473 MPASS(m->wire_count > 0);
9474 if (pmap_pti_free_page(m)) {
9475 pde = pmap_pti_pde(va);
9476 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9478 pmap_pti_unwire_pde(pde, false);
9483 pmap_pti_pde(vm_offset_t va)
9491 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9493 pdpe = pmap_pti_pdpe(va);
9495 m = pmap_pti_alloc_page();
9497 pmap_pti_free_page(m);
9498 MPASS((*pdpe & X86_PG_PS) == 0);
9499 mphys = *pdpe & ~PAGE_MASK;
9501 mphys = VM_PAGE_TO_PHYS(m);
9502 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9505 MPASS((*pdpe & X86_PG_PS) == 0);
9506 mphys = *pdpe & ~PAGE_MASK;
9509 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9510 pd_idx = pmap_pde_index(va);
9516 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9523 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9525 pde = pmap_pti_pde(va);
9526 if (unwire_pde != NULL) {
9528 pmap_pti_wire_pte(pde);
9531 m = pmap_pti_alloc_page();
9533 pmap_pti_free_page(m);
9534 MPASS((*pde & X86_PG_PS) == 0);
9535 mphys = *pde & ~(PAGE_MASK | pg_nx);
9537 mphys = VM_PAGE_TO_PHYS(m);
9538 *pde = mphys | X86_PG_RW | X86_PG_V;
9539 if (unwire_pde != NULL)
9540 *unwire_pde = false;
9543 MPASS((*pde & X86_PG_PS) == 0);
9544 mphys = *pde & ~(PAGE_MASK | pg_nx);
9547 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9548 pte += pmap_pte_index(va);
9554 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9558 pt_entry_t *pte, ptev;
9561 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9563 sva = trunc_page(sva);
9564 MPASS(sva > VM_MAXUSER_ADDRESS);
9565 eva = round_page(eva);
9567 for (; sva < eva; sva += PAGE_SIZE) {
9568 pte = pmap_pti_pte(sva, &unwire_pde);
9569 pa = pmap_kextract(sva);
9570 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9571 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9572 VM_MEMATTR_DEFAULT, FALSE);
9574 pte_store(pte, ptev);
9575 pmap_pti_wire_pte(pte);
9577 KASSERT(!pti_finalized,
9578 ("pti overlap after fin %#lx %#lx %#lx",
9580 KASSERT(*pte == ptev,
9581 ("pti non-identical pte after fin %#lx %#lx %#lx",
9585 pde = pmap_pti_pde(sva);
9586 pmap_pti_unwire_pde(pde, true);
9592 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9597 VM_OBJECT_WLOCK(pti_obj);
9598 pmap_pti_add_kva_locked(sva, eva, exec);
9599 VM_OBJECT_WUNLOCK(pti_obj);
9603 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9610 sva = rounddown2(sva, PAGE_SIZE);
9611 MPASS(sva > VM_MAXUSER_ADDRESS);
9612 eva = roundup2(eva, PAGE_SIZE);
9614 VM_OBJECT_WLOCK(pti_obj);
9615 for (va = sva; va < eva; va += PAGE_SIZE) {
9616 pte = pmap_pti_pte(va, NULL);
9617 KASSERT((*pte & X86_PG_V) != 0,
9618 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9619 (u_long)pte, *pte));
9621 pmap_pti_unwire_pte(pte, va);
9623 pmap_invalidate_range(kernel_pmap, sva, eva);
9624 VM_OBJECT_WUNLOCK(pti_obj);
9628 pkru_dup_range(void *ctx __unused, void *data)
9630 struct pmap_pkru_range *node, *new_node;
9632 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9633 if (new_node == NULL)
9636 memcpy(new_node, node, sizeof(*node));
9641 pkru_free_range(void *ctx __unused, void *node)
9644 uma_zfree(pmap_pkru_ranges_zone, node);
9648 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9651 struct pmap_pkru_range *ppr;
9654 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9655 MPASS(pmap->pm_type == PT_X86);
9656 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9657 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9658 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9660 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9663 ppr->pkru_keyidx = keyidx;
9664 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9665 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9667 uma_zfree(pmap_pkru_ranges_zone, ppr);
9672 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9675 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9676 MPASS(pmap->pm_type == PT_X86);
9677 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9678 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9682 pmap_pkru_deassign_all(pmap_t pmap)
9685 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9686 if (pmap->pm_type == PT_X86 &&
9687 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9688 rangeset_remove_all(&pmap->pm_pkru);
9692 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9694 struct pmap_pkru_range *ppr, *prev_ppr;
9697 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9698 if (pmap->pm_type != PT_X86 ||
9699 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9700 sva >= VM_MAXUSER_ADDRESS)
9702 MPASS(eva <= VM_MAXUSER_ADDRESS);
9703 for (va = sva, prev_ppr = NULL; va < eva;) {
9704 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9705 if ((ppr == NULL) ^ (prev_ppr == NULL))
9711 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9713 va = ppr->pkru_rs_el.re_end;
9719 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9721 struct pmap_pkru_range *ppr;
9723 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9724 if (pmap->pm_type != PT_X86 ||
9725 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9726 va >= VM_MAXUSER_ADDRESS)
9728 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9730 return (X86_PG_PKU(ppr->pkru_keyidx));
9735 pred_pkru_on_remove(void *ctx __unused, void *r)
9737 struct pmap_pkru_range *ppr;
9740 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9744 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9747 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9748 if (pmap->pm_type == PT_X86 &&
9749 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9750 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9751 pred_pkru_on_remove);
9756 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9759 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9760 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9761 MPASS(dst_pmap->pm_type == PT_X86);
9762 MPASS(src_pmap->pm_type == PT_X86);
9763 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9764 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9766 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9770 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9773 pml4_entry_t *pml4e;
9775 pd_entry_t newpde, ptpaddr, *pde;
9776 pt_entry_t newpte, *ptep, pte;
9777 vm_offset_t va, va_next;
9780 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9781 MPASS(pmap->pm_type == PT_X86);
9782 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9784 for (changed = false, va = sva; va < eva; va = va_next) {
9785 pml4e = pmap_pml4e(pmap, va);
9786 if ((*pml4e & X86_PG_V) == 0) {
9787 va_next = (va + NBPML4) & ~PML4MASK;
9793 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9794 if ((*pdpe & X86_PG_V) == 0) {
9795 va_next = (va + NBPDP) & ~PDPMASK;
9801 va_next = (va + NBPDR) & ~PDRMASK;
9805 pde = pmap_pdpe_to_pde(pdpe, va);
9810 MPASS((ptpaddr & X86_PG_V) != 0);
9811 if ((ptpaddr & PG_PS) != 0) {
9812 if (va + NBPDR == va_next && eva >= va_next) {
9813 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9815 if (newpde != ptpaddr) {
9820 } else if (!pmap_demote_pde(pmap, pde, va)) {
9828 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9829 ptep++, va += PAGE_SIZE) {
9831 if ((pte & X86_PG_V) == 0)
9833 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9834 if (newpte != pte) {
9841 pmap_invalidate_range(pmap, sva, eva);
9845 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9846 u_int keyidx, int flags)
9849 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9850 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9852 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9854 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9860 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9865 sva = trunc_page(sva);
9866 eva = round_page(eva);
9867 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9872 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9874 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9876 if (error != ENOMEM)
9884 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9888 sva = trunc_page(sva);
9889 eva = round_page(eva);
9890 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9895 error = pmap_pkru_deassign(pmap, sva, eva);
9897 pmap_pkru_update_range(pmap, sva, eva, 0);
9899 if (error != ENOMEM)
9907 DB_SHOW_COMMAND(pte, pmap_print_pte)
9913 pt_entry_t *pte, PG_V;
9917 db_printf("show pte addr\n");
9920 va = (vm_offset_t)addr;
9922 if (kdb_thread != NULL)
9923 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
9925 pmap = PCPU_GET(curpmap);
9927 PG_V = pmap_valid_bit(pmap);
9928 pml4 = pmap_pml4e(pmap, va);
9929 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
9930 if ((*pml4 & PG_V) == 0) {
9934 pdp = pmap_pml4e_to_pdpe(pml4, va);
9935 db_printf(" pdpe %#016lx", *pdp);
9936 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
9940 pde = pmap_pdpe_to_pde(pdp, va);
9941 db_printf(" pde %#016lx", *pde);
9942 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
9946 pte = pmap_pde_to_pte(pde, va);
9947 db_printf(" pte %#016lx\n", *pte);
9950 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
9955 a = (vm_paddr_t)addr;
9956 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
9958 db_printf("show phys2dmap addr\n");