2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2018 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
126 #include <sys/turnstile.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/intr_machdep.h>
148 #include <x86/apicvar.h>
149 #include <x86/ifunc.h>
150 #include <machine/cpu.h>
151 #include <machine/cputypes.h>
152 #include <machine/md_var.h>
153 #include <machine/pcb.h>
154 #include <machine/specialreg.h>
156 #include <machine/smp.h>
158 #include <machine/tss.h>
160 static __inline boolean_t
161 pmap_type_guest(pmap_t pmap)
164 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
167 static __inline boolean_t
168 pmap_emulate_ad_bits(pmap_t pmap)
171 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
174 static __inline pt_entry_t
175 pmap_valid_bit(pmap_t pmap)
179 switch (pmap->pm_type) {
185 if (pmap_emulate_ad_bits(pmap))
186 mask = EPT_PG_EMUL_V;
191 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
197 static __inline pt_entry_t
198 pmap_rw_bit(pmap_t pmap)
202 switch (pmap->pm_type) {
208 if (pmap_emulate_ad_bits(pmap))
209 mask = EPT_PG_EMUL_RW;
214 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
220 static pt_entry_t pg_g;
222 static __inline pt_entry_t
223 pmap_global_bit(pmap_t pmap)
227 switch (pmap->pm_type) {
236 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
242 static __inline pt_entry_t
243 pmap_accessed_bit(pmap_t pmap)
247 switch (pmap->pm_type) {
253 if (pmap_emulate_ad_bits(pmap))
259 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
265 static __inline pt_entry_t
266 pmap_modified_bit(pmap_t pmap)
270 switch (pmap->pm_type) {
276 if (pmap_emulate_ad_bits(pmap))
282 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
288 #if !defined(DIAGNOSTIC)
289 #ifdef __GNUC_GNU_INLINE__
290 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
292 #define PMAP_INLINE extern inline
299 #define PV_STAT(x) do { x ; } while (0)
301 #define PV_STAT(x) do { } while (0)
304 #define pa_index(pa) ((pa) >> PDRSHIFT)
305 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
307 #define NPV_LIST_LOCKS MAXCPU
309 #define PHYS_TO_PV_LIST_LOCK(pa) \
310 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
312 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
313 struct rwlock **_lockp = (lockp); \
314 struct rwlock *_new_lock; \
316 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
317 if (_new_lock != *_lockp) { \
318 if (*_lockp != NULL) \
319 rw_wunlock(*_lockp); \
320 *_lockp = _new_lock; \
325 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
326 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
328 #define RELEASE_PV_LIST_LOCK(lockp) do { \
329 struct rwlock **_lockp = (lockp); \
331 if (*_lockp != NULL) { \
332 rw_wunlock(*_lockp); \
337 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
338 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
340 struct pmap kernel_pmap_store;
342 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
343 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
346 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
347 "Number of kernel page table pages allocated on bootup");
350 vm_paddr_t dmaplimit;
351 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
354 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
356 static int pat_works = 1;
357 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
358 "Is page attribute table fully functional?");
360 static int pg_ps_enabled = 1;
361 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
362 &pg_ps_enabled, 0, "Are large page mappings enabled?");
364 #define PAT_INDEX_SIZE 8
365 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
367 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
368 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
369 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
370 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
372 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
373 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
374 static int ndmpdpphys; /* number of DMPDPphys pages */
376 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
379 * pmap_mapdev support pre initialization (i.e. console)
381 #define PMAP_PREINIT_MAPPING_COUNT 8
382 static struct pmap_preinit_mapping {
387 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
388 static int pmap_initialized;
391 * Data for the pv entry allocation mechanism.
392 * Updates to pv_invl_gen are protected by the pv_list_locks[]
393 * elements, but reads are not.
395 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
396 static struct mtx __exclusive_cache_line pv_chunks_mutex;
397 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
398 static u_long pv_invl_gen[NPV_LIST_LOCKS];
399 static struct md_page *pv_table;
400 static struct md_page pv_dummy;
403 * All those kernel PT submaps that BSD is so fond of
405 pt_entry_t *CMAP1 = NULL;
407 static vm_offset_t qframe = 0;
408 static struct mtx qframe_mtx;
410 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
412 int pmap_pcid_enabled = 1;
413 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
414 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
415 int invpcid_works = 0;
416 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
417 "Is the invpcid instruction available ?");
419 int __read_frequently pti = 0;
420 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
422 "Page Table Isolation enabled");
423 static vm_object_t pti_obj;
424 static pml4_entry_t *pti_pml4;
425 static vm_pindex_t pti_pg_idx;
426 static bool pti_finalized;
429 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
436 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
438 return (sysctl_handle_64(oidp, &res, 0, req));
440 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
441 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
442 "Count of saved TLB context on switch");
444 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
445 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
446 static struct mtx invl_gen_mtx;
447 static u_long pmap_invl_gen = 0;
448 /* Fake lock object to satisfy turnstiles interface. */
449 static struct lock_object invl_gen_ts = {
457 return (curthread->td_md.md_invl_gen.gen == 0);
460 #define PMAP_ASSERT_NOT_IN_DI() \
461 KASSERT(pmap_not_in_di(), ("DI already started"))
464 * Start a new Delayed Invalidation (DI) block of code, executed by
465 * the current thread. Within a DI block, the current thread may
466 * destroy both the page table and PV list entries for a mapping and
467 * then release the corresponding PV list lock before ensuring that
468 * the mapping is flushed from the TLBs of any processors with the
472 pmap_delayed_invl_started(void)
474 struct pmap_invl_gen *invl_gen;
477 invl_gen = &curthread->td_md.md_invl_gen;
478 PMAP_ASSERT_NOT_IN_DI();
479 mtx_lock(&invl_gen_mtx);
480 if (LIST_EMPTY(&pmap_invl_gen_tracker))
481 currgen = pmap_invl_gen;
483 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
484 invl_gen->gen = currgen + 1;
485 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
486 mtx_unlock(&invl_gen_mtx);
490 * Finish the DI block, previously started by the current thread. All
491 * required TLB flushes for the pages marked by
492 * pmap_delayed_invl_page() must be finished before this function is
495 * This function works by bumping the global DI generation number to
496 * the generation number of the current thread's DI, unless there is a
497 * pending DI that started earlier. In the latter case, bumping the
498 * global DI generation number would incorrectly signal that the
499 * earlier DI had finished. Instead, this function bumps the earlier
500 * DI's generation number to match the generation number of the
501 * current thread's DI.
504 pmap_delayed_invl_finished(void)
506 struct pmap_invl_gen *invl_gen, *next;
507 struct turnstile *ts;
509 invl_gen = &curthread->td_md.md_invl_gen;
510 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
511 mtx_lock(&invl_gen_mtx);
512 next = LIST_NEXT(invl_gen, link);
514 turnstile_chain_lock(&invl_gen_ts);
515 ts = turnstile_lookup(&invl_gen_ts);
516 pmap_invl_gen = invl_gen->gen;
518 turnstile_broadcast(ts, TS_SHARED_QUEUE);
519 turnstile_unpend(ts);
521 turnstile_chain_unlock(&invl_gen_ts);
523 next->gen = invl_gen->gen;
525 LIST_REMOVE(invl_gen, link);
526 mtx_unlock(&invl_gen_mtx);
531 static long invl_wait;
532 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
533 "Number of times DI invalidation blocked pmap_remove_all/write");
537 pmap_delayed_invl_genp(vm_page_t m)
540 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
544 * Ensure that all currently executing DI blocks, that need to flush
545 * TLB for the given page m, actually flushed the TLB at the time the
546 * function returned. If the page m has an empty PV list and we call
547 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
548 * valid mapping for the page m in either its page table or TLB.
550 * This function works by blocking until the global DI generation
551 * number catches up with the generation number associated with the
552 * given page m and its PV list. Since this function's callers
553 * typically own an object lock and sometimes own a page lock, it
554 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
558 pmap_delayed_invl_wait(vm_page_t m)
560 struct turnstile *ts;
563 bool accounted = false;
566 m_gen = pmap_delayed_invl_genp(m);
567 while (*m_gen > pmap_invl_gen) {
570 atomic_add_long(&invl_wait, 1);
574 ts = turnstile_trywait(&invl_gen_ts);
575 if (*m_gen > pmap_invl_gen)
576 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
578 turnstile_cancel(ts);
583 * Mark the page m's PV list as participating in the current thread's
584 * DI block. Any threads concurrently using m's PV list to remove or
585 * restrict all mappings to m will wait for the current thread's DI
586 * block to complete before proceeding.
588 * The function works by setting the DI generation number for m's PV
589 * list to at least the DI generation number of the current thread.
590 * This forces a caller of pmap_delayed_invl_wait() to block until
591 * current thread calls pmap_delayed_invl_finished().
594 pmap_delayed_invl_page(vm_page_t m)
598 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
599 gen = curthread->td_md.md_invl_gen.gen;
602 m_gen = pmap_delayed_invl_genp(m);
610 static caddr_t crashdumpmap;
613 * Internal flags for pmap_enter()'s helper functions.
615 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
616 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
618 static void free_pv_chunk(struct pv_chunk *pc);
619 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
620 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
621 static int popcnt_pc_map_pq(uint64_t *map);
622 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
623 static void reserve_pv_entries(pmap_t pmap, int needed,
624 struct rwlock **lockp);
625 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
626 struct rwlock **lockp);
627 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
628 u_int flags, struct rwlock **lockp);
629 #if VM_NRESERVLEVEL > 0
630 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
631 struct rwlock **lockp);
633 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
634 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
637 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
638 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
639 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
640 vm_offset_t va, struct rwlock **lockp);
641 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
643 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
644 vm_prot_t prot, struct rwlock **lockp);
645 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
646 u_int flags, vm_page_t m, struct rwlock **lockp);
647 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
648 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
649 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
650 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
651 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
653 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
655 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
657 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
658 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
659 #if VM_NRESERVLEVEL > 0
660 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
661 struct rwlock **lockp);
663 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
665 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
666 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
668 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
669 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
670 static void pmap_pti_wire_pte(void *pte);
671 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
672 struct spglist *free, struct rwlock **lockp);
673 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
674 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
675 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
676 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
677 struct spglist *free);
678 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
679 pd_entry_t *pde, struct spglist *free,
680 struct rwlock **lockp);
681 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
682 vm_page_t m, struct rwlock **lockp);
683 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
685 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
687 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
688 struct rwlock **lockp);
689 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
690 struct rwlock **lockp);
691 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
692 struct rwlock **lockp);
694 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
695 struct spglist *free);
696 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
698 /********************/
699 /* Inline functions */
700 /********************/
702 /* Return a non-clipped PD index for a given VA */
703 static __inline vm_pindex_t
704 pmap_pde_pindex(vm_offset_t va)
706 return (va >> PDRSHIFT);
710 /* Return a pointer to the PML4 slot that corresponds to a VA */
711 static __inline pml4_entry_t *
712 pmap_pml4e(pmap_t pmap, vm_offset_t va)
715 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
718 /* Return a pointer to the PDP slot that corresponds to a VA */
719 static __inline pdp_entry_t *
720 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
724 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
725 return (&pdpe[pmap_pdpe_index(va)]);
728 /* Return a pointer to the PDP slot that corresponds to a VA */
729 static __inline pdp_entry_t *
730 pmap_pdpe(pmap_t pmap, vm_offset_t va)
735 PG_V = pmap_valid_bit(pmap);
736 pml4e = pmap_pml4e(pmap, va);
737 if ((*pml4e & PG_V) == 0)
739 return (pmap_pml4e_to_pdpe(pml4e, va));
742 /* Return a pointer to the PD slot that corresponds to a VA */
743 static __inline pd_entry_t *
744 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
748 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
749 return (&pde[pmap_pde_index(va)]);
752 /* Return a pointer to the PD slot that corresponds to a VA */
753 static __inline pd_entry_t *
754 pmap_pde(pmap_t pmap, vm_offset_t va)
759 PG_V = pmap_valid_bit(pmap);
760 pdpe = pmap_pdpe(pmap, va);
761 if (pdpe == NULL || (*pdpe & PG_V) == 0)
763 return (pmap_pdpe_to_pde(pdpe, va));
766 /* Return a pointer to the PT slot that corresponds to a VA */
767 static __inline pt_entry_t *
768 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
772 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
773 return (&pte[pmap_pte_index(va)]);
776 /* Return a pointer to the PT slot that corresponds to a VA */
777 static __inline pt_entry_t *
778 pmap_pte(pmap_t pmap, vm_offset_t va)
783 PG_V = pmap_valid_bit(pmap);
784 pde = pmap_pde(pmap, va);
785 if (pde == NULL || (*pde & PG_V) == 0)
787 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
788 return ((pt_entry_t *)pde);
789 return (pmap_pde_to_pte(pde, va));
793 pmap_resident_count_inc(pmap_t pmap, int count)
796 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
797 pmap->pm_stats.resident_count += count;
801 pmap_resident_count_dec(pmap_t pmap, int count)
804 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
805 KASSERT(pmap->pm_stats.resident_count >= count,
806 ("pmap %p resident count underflow %ld %d", pmap,
807 pmap->pm_stats.resident_count, count));
808 pmap->pm_stats.resident_count -= count;
811 PMAP_INLINE pt_entry_t *
812 vtopte(vm_offset_t va)
814 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
816 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
818 return (PTmap + ((va >> PAGE_SHIFT) & mask));
821 static __inline pd_entry_t *
822 vtopde(vm_offset_t va)
824 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
826 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
828 return (PDmap + ((va >> PDRSHIFT) & mask));
832 allocpages(vm_paddr_t *firstaddr, int n)
837 bzero((void *)ret, n * PAGE_SIZE);
838 *firstaddr += n * PAGE_SIZE;
842 CTASSERT(powerof2(NDMPML4E));
844 /* number of kernel PDP slots */
845 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
848 nkpt_init(vm_paddr_t addr)
855 pt_pages = howmany(addr, 1 << PDRSHIFT);
856 pt_pages += NKPDPE(pt_pages);
859 * Add some slop beyond the bare minimum required for bootstrapping
862 * This is quite important when allocating KVA for kernel modules.
863 * The modules are required to be linked in the negative 2GB of
864 * the address space. If we run out of KVA in this region then
865 * pmap_growkernel() will need to allocate page table pages to map
866 * the entire 512GB of KVA space which is an unnecessary tax on
869 * Secondly, device memory mapped as part of setting up the low-
870 * level console(s) is taken from KVA, starting at virtual_avail.
871 * This is because cninit() is called after pmap_bootstrap() but
872 * before vm_init() and pmap_init(). 20MB for a frame buffer is
875 pt_pages += 32; /* 64MB additional slop. */
881 * Returns the proper write/execute permission for a physical page that is
882 * part of the initial boot allocations.
884 * If the page has kernel text, it is marked as read-only. If the page has
885 * kernel read-only data, it is marked as read-only/not-executable. If the
886 * page has only read-write data, it is marked as read-write/not-executable.
887 * If the page is below/above the kernel range, it is marked as read-write.
889 * This function operates on 2M pages, since we map the kernel space that
892 * Note that this doesn't currently provide any protection for modules.
894 static inline pt_entry_t
895 bootaddr_rwx(vm_paddr_t pa)
899 * Everything in the same 2M page as the start of the kernel
900 * should be static. On the other hand, things in the same 2M
901 * page as the end of the kernel could be read-write/executable,
902 * as the kernel image is not guaranteed to end on a 2M boundary.
904 if (pa < trunc_2mpage(btext - KERNBASE) ||
905 pa >= trunc_2mpage(_end - KERNBASE))
908 * The linker should ensure that the read-only and read-write
909 * portions don't share the same 2M page, so this shouldn't
910 * impact read-only data. However, in any case, any page with
911 * read-write data needs to be read-write.
913 if (pa >= trunc_2mpage(brwsection - KERNBASE))
914 return (X86_PG_RW | pg_nx);
916 * Mark any 2M page containing kernel text as read-only. Mark
917 * other pages with read-only data as read-only and not executable.
918 * (It is likely a small portion of the read-only data section will
919 * be marked as read-only, but executable. This should be acceptable
920 * since the read-only protection will keep the data from changing.)
921 * Note that fixups to the .text section will still work until we
924 if (pa < round_2mpage(etext - KERNBASE))
930 create_pagetables(vm_paddr_t *firstaddr)
932 int i, j, ndm1g, nkpdpe, nkdmpde;
937 uint64_t DMPDkernphys;
939 /* Allocate page table pages for the direct map */
940 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
941 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
943 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
944 if (ndmpdpphys > NDMPML4E) {
946 * Each NDMPML4E allows 512 GB, so limit to that,
947 * and then readjust ndmpdp and ndmpdpphys.
949 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
950 Maxmem = atop(NDMPML4E * NBPML4);
951 ndmpdpphys = NDMPML4E;
952 ndmpdp = NDMPML4E * NPDEPG;
954 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
956 if ((amd_feature & AMDID_PAGE1GB) != 0) {
958 * Calculate the number of 1G pages that will fully fit in
961 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
964 * Allocate 2M pages for the kernel. These will be used in
965 * place of the first one or more 1G pages from ndm1g.
967 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
968 DMPDkernphys = allocpages(firstaddr, nkdmpde);
971 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
972 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
975 KPML4phys = allocpages(firstaddr, 1);
976 KPDPphys = allocpages(firstaddr, NKPML4E);
979 * Allocate the initial number of kernel page table pages required to
980 * bootstrap. We defer this until after all memory-size dependent
981 * allocations are done (e.g. direct map), so that we don't have to
982 * build in too much slop in our estimate.
984 * Note that when NKPML4E > 1, we have an empty page underneath
985 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
986 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
988 nkpt_init(*firstaddr);
989 nkpdpe = NKPDPE(nkpt);
991 KPTphys = allocpages(firstaddr, nkpt);
992 KPDphys = allocpages(firstaddr, nkpdpe);
994 /* Fill in the underlying page table pages */
995 /* XXX not fully used, underneath 2M pages */
996 pt_p = (pt_entry_t *)KPTphys;
997 for (i = 0; ptoa(i) < *firstaddr; i++)
998 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
1000 /* Now map the page tables at their location within PTmap */
1001 pd_p = (pd_entry_t *)KPDphys;
1002 for (i = 0; i < nkpt; i++)
1003 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1005 /* Map from zero to end of allocations under 2M pages */
1006 /* This replaces some of the KPTphys entries above */
1007 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1008 /* Preset PG_M and PG_A because demotion expects it. */
1009 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1010 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1013 * Because we map the physical blocks in 2M pages, adjust firstaddr
1014 * to record the physical blocks we've actually mapped into kernel
1015 * virtual address space.
1017 *firstaddr = round_2mpage(*firstaddr);
1019 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1020 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1021 for (i = 0; i < nkpdpe; i++)
1022 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1025 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1026 * the end of physical memory is not aligned to a 1GB page boundary,
1027 * then the residual physical memory is mapped with 2MB pages. Later,
1028 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1029 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1030 * that are partially used.
1032 pd_p = (pd_entry_t *)DMPDphys;
1033 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1034 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1035 /* Preset PG_M and PG_A because demotion expects it. */
1036 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1037 X86_PG_M | X86_PG_A | pg_nx;
1039 pdp_p = (pdp_entry_t *)DMPDPphys;
1040 for (i = 0; i < ndm1g; i++) {
1041 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1042 /* Preset PG_M and PG_A because demotion expects it. */
1043 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1044 X86_PG_M | X86_PG_A | pg_nx;
1046 for (j = 0; i < ndmpdp; i++, j++) {
1047 pdp_p[i] = DMPDphys + ptoa(j);
1048 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1052 * Instead of using a 1G page for the memory containing the kernel,
1053 * use 2M pages with appropriate permissions. (If using 1G pages,
1054 * this will partially overwrite the PDPEs above.)
1057 pd_p = (pd_entry_t *)DMPDkernphys;
1058 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1059 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1060 X86_PG_M | X86_PG_A | pg_nx |
1061 bootaddr_rwx(i << PDRSHIFT);
1062 for (i = 0; i < nkdmpde; i++)
1063 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1067 /* And recursively map PML4 to itself in order to get PTmap */
1068 p4_p = (pml4_entry_t *)KPML4phys;
1069 p4_p[PML4PML4I] = KPML4phys;
1070 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1072 /* Connect the Direct Map slot(s) up to the PML4. */
1073 for (i = 0; i < ndmpdpphys; i++) {
1074 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1075 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1078 /* Connect the KVA slots up to the PML4 */
1079 for (i = 0; i < NKPML4E; i++) {
1080 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1081 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1086 * Bootstrap the system enough to run with virtual memory.
1088 * On amd64 this is called after mapping has already been enabled
1089 * and just syncs the pmap module with what has already been done.
1090 * [We can't call it easily with mapping off since the kernel is not
1091 * mapped with PA == VA, hence we would have to relocate every address
1092 * from the linked base (virtual) address "KERNBASE" to the actual
1093 * (physical) address starting relative to 0]
1096 pmap_bootstrap(vm_paddr_t *firstaddr)
1103 KERNend = *firstaddr;
1109 * Create an initial set of page tables to run the kernel in.
1111 create_pagetables(firstaddr);
1114 * Add a physical memory segment (vm_phys_seg) corresponding to the
1115 * preallocated kernel page table pages so that vm_page structures
1116 * representing these pages will be created. The vm_page structures
1117 * are required for promotion of the corresponding kernel virtual
1118 * addresses to superpage mappings.
1120 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1122 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1124 virtual_end = VM_MAX_KERNEL_ADDRESS;
1128 * Enable PG_G global pages, then switch to the kernel page
1129 * table from the bootstrap page table. After the switch, it
1130 * is possible to enable SMEP and SMAP since PG_U bits are
1136 load_cr3(KPML4phys);
1137 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1139 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1144 * Initialize the kernel pmap (which is statically allocated).
1146 PMAP_LOCK_INIT(kernel_pmap);
1147 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1148 kernel_pmap->pm_cr3 = KPML4phys;
1149 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1150 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1151 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1152 kernel_pmap->pm_flags = pmap_flags;
1155 * Initialize the TLB invalidations generation number lock.
1157 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1160 * Reserve some special page table entries/VA space for temporary
1163 #define SYSMAP(c, p, v, n) \
1164 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1170 * Crashdump maps. The first page is reused as CMAP1 for the
1173 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1174 CADDR1 = crashdumpmap;
1179 * Initialize the PAT MSR.
1180 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1181 * side-effect, invalidates stale PG_G TLB entries that might
1182 * have been created in our pre-boot environment.
1186 /* Initialize TLB Context Id. */
1187 if (pmap_pcid_enabled) {
1188 for (i = 0; i < MAXCPU; i++) {
1189 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1190 kernel_pmap->pm_pcids[i].pm_gen = 1;
1194 * PMAP_PCID_KERN + 1 is used for initialization of
1195 * proc0 pmap. The pmap' pcid state might be used by
1196 * EFIRT entry before first context switch, so it
1197 * needs to be valid.
1199 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1200 PCPU_SET(pcid_gen, 1);
1203 * pcpu area for APs is zeroed during AP startup.
1204 * pc_pcid_next and pc_pcid_gen are initialized by AP
1205 * during pcpu setup.
1207 load_cr4(rcr4() | CR4_PCIDE);
1212 * Setup the PAT MSR.
1217 int pat_table[PAT_INDEX_SIZE];
1222 /* Bail if this CPU doesn't implement PAT. */
1223 if ((cpu_feature & CPUID_PAT) == 0)
1226 /* Set default PAT index table. */
1227 for (i = 0; i < PAT_INDEX_SIZE; i++)
1229 pat_table[PAT_WRITE_BACK] = 0;
1230 pat_table[PAT_WRITE_THROUGH] = 1;
1231 pat_table[PAT_UNCACHEABLE] = 3;
1232 pat_table[PAT_WRITE_COMBINING] = 3;
1233 pat_table[PAT_WRITE_PROTECTED] = 3;
1234 pat_table[PAT_UNCACHED] = 3;
1236 /* Initialize default PAT entries. */
1237 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1238 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1239 PAT_VALUE(2, PAT_UNCACHED) |
1240 PAT_VALUE(3, PAT_UNCACHEABLE) |
1241 PAT_VALUE(4, PAT_WRITE_BACK) |
1242 PAT_VALUE(5, PAT_WRITE_THROUGH) |
1243 PAT_VALUE(6, PAT_UNCACHED) |
1244 PAT_VALUE(7, PAT_UNCACHEABLE);
1248 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1249 * Program 5 and 6 as WP and WC.
1250 * Leave 4 and 7 as WB and UC.
1252 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
1253 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1254 PAT_VALUE(6, PAT_WRITE_COMBINING);
1255 pat_table[PAT_UNCACHED] = 2;
1256 pat_table[PAT_WRITE_PROTECTED] = 5;
1257 pat_table[PAT_WRITE_COMBINING] = 6;
1260 * Just replace PAT Index 2 with WC instead of UC-.
1262 pat_msr &= ~PAT_MASK(2);
1263 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
1264 pat_table[PAT_WRITE_COMBINING] = 2;
1269 load_cr4(cr4 & ~CR4_PGE);
1271 /* Disable caches (CD = 1, NW = 0). */
1273 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1275 /* Flushes caches and TLBs. */
1279 /* Update PAT and index table. */
1280 wrmsr(MSR_PAT, pat_msr);
1281 for (i = 0; i < PAT_INDEX_SIZE; i++)
1282 pat_index[i] = pat_table[i];
1284 /* Flush caches and TLBs again. */
1288 /* Restore caches and PGE. */
1294 * Initialize a vm_page's machine-dependent fields.
1297 pmap_page_init(vm_page_t m)
1300 TAILQ_INIT(&m->md.pv_list);
1301 m->md.pat_mode = PAT_WRITE_BACK;
1305 * Initialize the pmap module.
1306 * Called by vm_init, to initialize any structures that the pmap
1307 * system needs to map virtual memory.
1312 struct pmap_preinit_mapping *ppim;
1315 int error, i, pv_npg, ret, skz63;
1317 /* L1TF, reserve page @0 unconditionally */
1318 vm_page_blacklist_add(0, bootverbose);
1320 /* Detect bare-metal Skylake Server and Skylake-X. */
1321 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1322 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1324 * Skylake-X errata SKZ63. Processor May Hang When
1325 * Executing Code In an HLE Transaction Region between
1326 * 40000000H and 403FFFFFH.
1328 * Mark the pages in the range as preallocated. It
1329 * seems to be impossible to distinguish between
1330 * Skylake Server and Skylake X.
1333 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1336 printf("SKZ63: skipping 4M RAM starting "
1337 "at physical 1G\n");
1338 for (i = 0; i < atop(0x400000); i++) {
1339 ret = vm_page_blacklist_add(0x40000000 +
1341 if (!ret && bootverbose)
1342 printf("page at %#lx already used\n",
1343 0x40000000 + ptoa(i));
1349 * Initialize the vm page array entries for the kernel pmap's
1352 PMAP_LOCK(kernel_pmap);
1353 for (i = 0; i < nkpt; i++) {
1354 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1355 KASSERT(mpte >= vm_page_array &&
1356 mpte < &vm_page_array[vm_page_array_size],
1357 ("pmap_init: page table page is out of range"));
1358 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1359 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1360 mpte->wire_count = 1;
1361 if (i << PDRSHIFT < KERNend &&
1362 pmap_insert_pt_page(kernel_pmap, mpte))
1363 panic("pmap_init: pmap_insert_pt_page failed");
1365 PMAP_UNLOCK(kernel_pmap);
1369 * If the kernel is running on a virtual machine, then it must assume
1370 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1371 * be prepared for the hypervisor changing the vendor and family that
1372 * are reported by CPUID. Consequently, the workaround for AMD Family
1373 * 10h Erratum 383 is enabled if the processor's feature set does not
1374 * include at least one feature that is only supported by older Intel
1375 * or newer AMD processors.
1377 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1378 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1379 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1381 workaround_erratum383 = 1;
1384 * Are large page mappings enabled?
1386 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1387 if (pg_ps_enabled) {
1388 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1389 ("pmap_init: can't assign to pagesizes[1]"));
1390 pagesizes[1] = NBPDR;
1394 * Initialize the pv chunk list mutex.
1396 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1399 * Initialize the pool of pv list locks.
1401 for (i = 0; i < NPV_LIST_LOCKS; i++)
1402 rw_init(&pv_list_locks[i], "pmap pv list");
1405 * Calculate the size of the pv head table for superpages.
1407 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1410 * Allocate memory for the pv head table for superpages.
1412 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1414 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1415 for (i = 0; i < pv_npg; i++)
1416 TAILQ_INIT(&pv_table[i].pv_list);
1417 TAILQ_INIT(&pv_dummy.pv_list);
1419 pmap_initialized = 1;
1420 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1421 ppim = pmap_preinit_mapping + i;
1424 /* Make the direct map consistent */
1425 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1426 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1427 ppim->sz, ppim->mode);
1431 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1432 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1435 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1436 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1437 (vmem_addr_t *)&qframe);
1439 panic("qframe allocation failed");
1442 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1443 "2MB page mapping counters");
1445 static u_long pmap_pde_demotions;
1446 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1447 &pmap_pde_demotions, 0, "2MB page demotions");
1449 static u_long pmap_pde_mappings;
1450 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1451 &pmap_pde_mappings, 0, "2MB page mappings");
1453 static u_long pmap_pde_p_failures;
1454 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1455 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1457 static u_long pmap_pde_promotions;
1458 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1459 &pmap_pde_promotions, 0, "2MB page promotions");
1461 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1462 "1GB page mapping counters");
1464 static u_long pmap_pdpe_demotions;
1465 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1466 &pmap_pdpe_demotions, 0, "1GB page demotions");
1468 /***************************************************
1469 * Low level helper routines.....
1470 ***************************************************/
1473 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1475 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1477 switch (pmap->pm_type) {
1480 /* Verify that both PAT bits are not set at the same time */
1481 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1482 ("Invalid PAT bits in entry %#lx", entry));
1484 /* Swap the PAT bits if one of them is set */
1485 if ((entry & x86_pat_bits) != 0)
1486 entry ^= x86_pat_bits;
1490 * Nothing to do - the memory attributes are represented
1491 * the same way for regular pages and superpages.
1495 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1502 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1505 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1506 pat_index[(int)mode] >= 0);
1510 * Determine the appropriate bits to set in a PTE or PDE for a specified
1514 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1516 int cache_bits, pat_flag, pat_idx;
1518 if (!pmap_is_valid_memattr(pmap, mode))
1519 panic("Unknown caching mode %d\n", mode);
1521 switch (pmap->pm_type) {
1524 /* The PAT bit is different for PTE's and PDE's. */
1525 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1527 /* Map the caching mode to a PAT index. */
1528 pat_idx = pat_index[mode];
1530 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1533 cache_bits |= pat_flag;
1535 cache_bits |= PG_NC_PCD;
1537 cache_bits |= PG_NC_PWT;
1541 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1545 panic("unsupported pmap type %d", pmap->pm_type);
1548 return (cache_bits);
1552 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1556 switch (pmap->pm_type) {
1559 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1562 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1565 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1572 pmap_ps_enabled(pmap_t pmap)
1575 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1579 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1582 switch (pmap->pm_type) {
1589 * This is a little bogus since the generation number is
1590 * supposed to be bumped up when a region of the address
1591 * space is invalidated in the page tables.
1593 * In this case the old PDE entry is valid but yet we want
1594 * to make sure that any mappings using the old entry are
1595 * invalidated in the TLB.
1597 * The reason this works as expected is because we rendezvous
1598 * "all" host cpus and force any vcpu context to exit as a
1601 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1604 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1606 pde_store(pde, newpde);
1610 * After changing the page size for the specified virtual address in the page
1611 * table, flush the corresponding entries from the processor's TLB. Only the
1612 * calling processor's TLB is affected.
1614 * The calling thread must be pinned to a processor.
1617 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1621 if (pmap_type_guest(pmap))
1624 KASSERT(pmap->pm_type == PT_X86,
1625 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1627 PG_G = pmap_global_bit(pmap);
1629 if ((newpde & PG_PS) == 0)
1630 /* Demotion: flush a specific 2MB page mapping. */
1632 else if ((newpde & PG_G) == 0)
1634 * Promotion: flush every 4KB page mapping from the TLB
1635 * because there are too many to flush individually.
1640 * Promotion: flush every 4KB page mapping from the TLB,
1641 * including any global (PG_G) mappings.
1649 * For SMP, these functions have to use the IPI mechanism for coherence.
1651 * N.B.: Before calling any of the following TLB invalidation functions,
1652 * the calling processor must ensure that all stores updating a non-
1653 * kernel page table are globally performed. Otherwise, another
1654 * processor could cache an old, pre-update entry without being
1655 * invalidated. This can happen one of two ways: (1) The pmap becomes
1656 * active on another processor after its pm_active field is checked by
1657 * one of the following functions but before a store updating the page
1658 * table is globally performed. (2) The pmap becomes active on another
1659 * processor before its pm_active field is checked but due to
1660 * speculative loads one of the following functions stills reads the
1661 * pmap as inactive on the other processor.
1663 * The kernel page table is exempt because its pm_active field is
1664 * immutable. The kernel page table is always active on every
1669 * Interrupt the cpus that are executing in the guest context.
1670 * This will force the vcpu to exit and the cached EPT mappings
1671 * will be invalidated by the host before the next vmresume.
1673 static __inline void
1674 pmap_invalidate_ept(pmap_t pmap)
1679 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1680 ("pmap_invalidate_ept: absurd pm_active"));
1683 * The TLB mappings associated with a vcpu context are not
1684 * flushed each time a different vcpu is chosen to execute.
1686 * This is in contrast with a process's vtop mappings that
1687 * are flushed from the TLB on each context switch.
1689 * Therefore we need to do more than just a TLB shootdown on
1690 * the active cpus in 'pmap->pm_active'. To do this we keep
1691 * track of the number of invalidations performed on this pmap.
1693 * Each vcpu keeps a cache of this counter and compares it
1694 * just before a vmresume. If the counter is out-of-date an
1695 * invept will be done to flush stale mappings from the TLB.
1697 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1700 * Force the vcpu to exit and trap back into the hypervisor.
1702 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1703 ipi_selected(pmap->pm_active, ipinum);
1708 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1711 struct invpcid_descr d;
1712 uint64_t kcr3, ucr3;
1716 if (pmap_type_guest(pmap)) {
1717 pmap_invalidate_ept(pmap);
1721 KASSERT(pmap->pm_type == PT_X86,
1722 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1725 if (pmap == kernel_pmap) {
1729 cpuid = PCPU_GET(cpuid);
1730 if (pmap == PCPU_GET(curpmap)) {
1732 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1734 * Disable context switching. pm_pcid
1735 * is recalculated on switch, which
1736 * might make us use wrong pcid below.
1739 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1741 if (invpcid_works) {
1742 d.pcid = pcid | PMAP_PCID_USER_PT;
1745 invpcid(&d, INVPCID_ADDR);
1747 kcr3 = pmap->pm_cr3 | pcid |
1749 ucr3 = pmap->pm_ucr3 | pcid |
1750 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1751 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1755 } else if (pmap_pcid_enabled)
1756 pmap->pm_pcids[cpuid].pm_gen = 0;
1757 if (pmap_pcid_enabled) {
1760 pmap->pm_pcids[i].pm_gen = 0;
1764 * The fence is between stores to pm_gen and the read of
1765 * the pm_active mask. We need to ensure that it is
1766 * impossible for us to miss the bit update in pm_active
1767 * and simultaneously observe a non-zero pm_gen in
1768 * pmap_activate_sw(), otherwise TLB update is missed.
1769 * Without the fence, IA32 allows such an outcome.
1770 * Note that pm_active is updated by a locked operation,
1771 * which provides the reciprocal fence.
1773 atomic_thread_fence_seq_cst();
1775 mask = &pmap->pm_active;
1777 smp_masked_invlpg(*mask, va, pmap);
1781 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1782 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1785 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1788 struct invpcid_descr d;
1790 uint64_t kcr3, ucr3;
1794 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1795 pmap_invalidate_all(pmap);
1799 if (pmap_type_guest(pmap)) {
1800 pmap_invalidate_ept(pmap);
1804 KASSERT(pmap->pm_type == PT_X86,
1805 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1808 cpuid = PCPU_GET(cpuid);
1809 if (pmap == kernel_pmap) {
1810 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1814 if (pmap == PCPU_GET(curpmap)) {
1815 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1817 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1819 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1820 if (invpcid_works) {
1821 d.pcid = pcid | PMAP_PCID_USER_PT;
1824 for (; d.addr < eva; d.addr +=
1826 invpcid(&d, INVPCID_ADDR);
1828 kcr3 = pmap->pm_cr3 | pcid |
1830 ucr3 = pmap->pm_ucr3 | pcid |
1831 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1832 pmap_pti_pcid_invlrng(ucr3, kcr3, sva,
1837 } else if (pmap_pcid_enabled) {
1838 pmap->pm_pcids[cpuid].pm_gen = 0;
1840 if (pmap_pcid_enabled) {
1843 pmap->pm_pcids[i].pm_gen = 0;
1845 /* See the comment in pmap_invalidate_page(). */
1846 atomic_thread_fence_seq_cst();
1848 mask = &pmap->pm_active;
1850 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1855 pmap_invalidate_all(pmap_t pmap)
1858 struct invpcid_descr d;
1859 uint64_t kcr3, ucr3;
1863 if (pmap_type_guest(pmap)) {
1864 pmap_invalidate_ept(pmap);
1868 KASSERT(pmap->pm_type == PT_X86,
1869 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1872 if (pmap == kernel_pmap) {
1873 if (pmap_pcid_enabled && invpcid_works) {
1874 bzero(&d, sizeof(d));
1875 invpcid(&d, INVPCID_CTXGLOB);
1881 cpuid = PCPU_GET(cpuid);
1882 if (pmap == PCPU_GET(curpmap)) {
1883 if (pmap_pcid_enabled) {
1885 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1886 if (invpcid_works) {
1890 invpcid(&d, INVPCID_CTX);
1891 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1892 d.pcid |= PMAP_PCID_USER_PT;
1893 invpcid(&d, INVPCID_CTX);
1896 kcr3 = pmap->pm_cr3 | pcid;
1897 ucr3 = pmap->pm_ucr3;
1898 if (ucr3 != PMAP_NO_CR3) {
1899 ucr3 |= pcid | PMAP_PCID_USER_PT;
1900 pmap_pti_pcid_invalidate(ucr3,
1910 } else if (pmap_pcid_enabled) {
1911 pmap->pm_pcids[cpuid].pm_gen = 0;
1913 if (pmap_pcid_enabled) {
1916 pmap->pm_pcids[i].pm_gen = 0;
1918 /* See the comment in pmap_invalidate_page(). */
1919 atomic_thread_fence_seq_cst();
1921 mask = &pmap->pm_active;
1923 smp_masked_invltlb(*mask, pmap);
1928 pmap_invalidate_cache(void)
1938 cpuset_t invalidate; /* processors that invalidate their TLB */
1943 u_int store; /* processor that updates the PDE */
1947 pmap_update_pde_action(void *arg)
1949 struct pde_action *act = arg;
1951 if (act->store == PCPU_GET(cpuid))
1952 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1956 pmap_update_pde_teardown(void *arg)
1958 struct pde_action *act = arg;
1960 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1961 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1965 * Change the page size for the specified virtual address in a way that
1966 * prevents any possibility of the TLB ever having two entries that map the
1967 * same virtual address using different page sizes. This is the recommended
1968 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1969 * machine check exception for a TLB state that is improperly diagnosed as a
1973 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1975 struct pde_action act;
1976 cpuset_t active, other_cpus;
1980 cpuid = PCPU_GET(cpuid);
1981 other_cpus = all_cpus;
1982 CPU_CLR(cpuid, &other_cpus);
1983 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1986 active = pmap->pm_active;
1988 if (CPU_OVERLAP(&active, &other_cpus)) {
1990 act.invalidate = active;
1994 act.newpde = newpde;
1995 CPU_SET(cpuid, &active);
1996 smp_rendezvous_cpus(active,
1997 smp_no_rendezvous_barrier, pmap_update_pde_action,
1998 pmap_update_pde_teardown, &act);
2000 pmap_update_pde_store(pmap, pde, newpde);
2001 if (CPU_ISSET(cpuid, &active))
2002 pmap_update_pde_invalidate(pmap, va, newpde);
2008 * Normal, non-SMP, invalidation functions.
2011 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2013 struct invpcid_descr d;
2014 uint64_t kcr3, ucr3;
2017 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2021 KASSERT(pmap->pm_type == PT_X86,
2022 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2024 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2026 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2027 pmap->pm_ucr3 != PMAP_NO_CR3) {
2029 pcid = pmap->pm_pcids[0].pm_pcid;
2030 if (invpcid_works) {
2031 d.pcid = pcid | PMAP_PCID_USER_PT;
2034 invpcid(&d, INVPCID_ADDR);
2036 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2037 ucr3 = pmap->pm_ucr3 | pcid |
2038 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2039 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2043 } else if (pmap_pcid_enabled)
2044 pmap->pm_pcids[0].pm_gen = 0;
2048 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2050 struct invpcid_descr d;
2052 uint64_t kcr3, ucr3;
2054 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2058 KASSERT(pmap->pm_type == PT_X86,
2059 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2061 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2062 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2064 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2065 pmap->pm_ucr3 != PMAP_NO_CR3) {
2067 if (invpcid_works) {
2068 d.pcid = pmap->pm_pcids[0].pm_pcid |
2072 for (; d.addr < eva; d.addr += PAGE_SIZE)
2073 invpcid(&d, INVPCID_ADDR);
2075 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2076 pm_pcid | CR3_PCID_SAVE;
2077 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2078 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2079 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2083 } else if (pmap_pcid_enabled) {
2084 pmap->pm_pcids[0].pm_gen = 0;
2089 pmap_invalidate_all(pmap_t pmap)
2091 struct invpcid_descr d;
2092 uint64_t kcr3, ucr3;
2094 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2098 KASSERT(pmap->pm_type == PT_X86,
2099 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2101 if (pmap == kernel_pmap) {
2102 if (pmap_pcid_enabled && invpcid_works) {
2103 bzero(&d, sizeof(d));
2104 invpcid(&d, INVPCID_CTXGLOB);
2108 } else if (pmap == PCPU_GET(curpmap)) {
2109 if (pmap_pcid_enabled) {
2111 if (invpcid_works) {
2112 d.pcid = pmap->pm_pcids[0].pm_pcid;
2115 invpcid(&d, INVPCID_CTX);
2116 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2117 d.pcid |= PMAP_PCID_USER_PT;
2118 invpcid(&d, INVPCID_CTX);
2121 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2122 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2123 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2124 0].pm_pcid | PMAP_PCID_USER_PT;
2125 pmap_pti_pcid_invalidate(ucr3, kcr3);
2133 } else if (pmap_pcid_enabled) {
2134 pmap->pm_pcids[0].pm_gen = 0;
2139 pmap_invalidate_cache(void)
2146 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2149 pmap_update_pde_store(pmap, pde, newpde);
2150 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2151 pmap_update_pde_invalidate(pmap, va, newpde);
2153 pmap->pm_pcids[0].pm_gen = 0;
2158 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2162 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2163 * by a promotion that did not invalidate the 512 4KB page mappings
2164 * that might exist in the TLB. Consequently, at this point, the TLB
2165 * may hold both 4KB and 2MB page mappings for the address range [va,
2166 * va + NBPDR). Therefore, the entire range must be invalidated here.
2167 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2168 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2169 * single INVLPG suffices to invalidate the 2MB page mapping from the
2172 if ((pde & PG_PROMOTED) != 0)
2173 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2175 pmap_invalidate_page(pmap, va);
2178 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2179 (vm_offset_t sva, vm_offset_t eva), static)
2182 if ((cpu_feature & CPUID_SS) != 0)
2183 return (pmap_invalidate_cache_range_selfsnoop);
2184 if ((cpu_feature & CPUID_CLFSH) != 0)
2185 return (pmap_force_invalidate_cache_range);
2186 return (pmap_invalidate_cache_range_all);
2189 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2192 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2195 KASSERT((sva & PAGE_MASK) == 0,
2196 ("pmap_invalidate_cache_range: sva not page-aligned"));
2197 KASSERT((eva & PAGE_MASK) == 0,
2198 ("pmap_invalidate_cache_range: eva not page-aligned"));
2202 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2205 pmap_invalidate_cache_range_check_align(sva, eva);
2209 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2212 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2213 if (eva - sva >= PMAP_CLFLUSH_THRESHOLD) {
2215 * The supplied range is bigger than 2MB.
2216 * Globally invalidate cache.
2218 pmap_invalidate_cache();
2223 * XXX: Some CPUs fault, hang, or trash the local APIC
2224 * registers if we use CLFLUSH on the local APIC range. The
2225 * local APIC is always uncached, so we don't need to flush
2226 * for that range anyway.
2228 if (pmap_kextract(sva) == lapic_paddr)
2231 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2233 * Do per-cache line flush. Use the sfence
2234 * instruction to insure that previous stores are
2235 * included in the write-back. The processor
2236 * propagates flush to other processors in the cache
2240 for (; sva < eva; sva += cpu_clflush_line_size)
2245 * Writes are ordered by CLFLUSH on Intel CPUs.
2247 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2249 for (; sva < eva; sva += cpu_clflush_line_size)
2251 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2257 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2260 pmap_invalidate_cache_range_check_align(sva, eva);
2261 pmap_invalidate_cache();
2265 * Remove the specified set of pages from the data and instruction caches.
2267 * In contrast to pmap_invalidate_cache_range(), this function does not
2268 * rely on the CPU's self-snoop feature, because it is intended for use
2269 * when moving pages into a different cache domain.
2272 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2274 vm_offset_t daddr, eva;
2278 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2279 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2280 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2281 pmap_invalidate_cache();
2285 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2287 for (i = 0; i < count; i++) {
2288 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2289 eva = daddr + PAGE_SIZE;
2290 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2299 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2305 * Routine: pmap_extract
2307 * Extract the physical page address associated
2308 * with the given map/virtual_address pair.
2311 pmap_extract(pmap_t pmap, vm_offset_t va)
2315 pt_entry_t *pte, PG_V;
2319 PG_V = pmap_valid_bit(pmap);
2321 pdpe = pmap_pdpe(pmap, va);
2322 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2323 if ((*pdpe & PG_PS) != 0)
2324 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2326 pde = pmap_pdpe_to_pde(pdpe, va);
2327 if ((*pde & PG_V) != 0) {
2328 if ((*pde & PG_PS) != 0) {
2329 pa = (*pde & PG_PS_FRAME) |
2332 pte = pmap_pde_to_pte(pde, va);
2333 pa = (*pte & PG_FRAME) |
2344 * Routine: pmap_extract_and_hold
2346 * Atomically extract and hold the physical page
2347 * with the given pmap and virtual address pair
2348 * if that mapping permits the given protection.
2351 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2353 pd_entry_t pde, *pdep;
2354 pt_entry_t pte, PG_RW, PG_V;
2360 PG_RW = pmap_rw_bit(pmap);
2361 PG_V = pmap_valid_bit(pmap);
2364 pdep = pmap_pde(pmap, va);
2365 if (pdep != NULL && (pde = *pdep)) {
2367 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2368 if (vm_page_pa_tryrelock(pmap, (pde &
2369 PG_PS_FRAME) | (va & PDRMASK), &pa))
2371 m = PHYS_TO_VM_PAGE(pa);
2374 pte = *pmap_pde_to_pte(pdep, va);
2376 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2377 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2380 m = PHYS_TO_VM_PAGE(pa);
2392 pmap_kextract(vm_offset_t va)
2397 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2398 pa = DMAP_TO_PHYS(va);
2402 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2405 * Beware of a concurrent promotion that changes the
2406 * PDE at this point! For example, vtopte() must not
2407 * be used to access the PTE because it would use the
2408 * new PDE. It is, however, safe to use the old PDE
2409 * because the page table page is preserved by the
2412 pa = *pmap_pde_to_pte(&pde, va);
2413 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2419 /***************************************************
2420 * Low level mapping routines.....
2421 ***************************************************/
2424 * Add a wired page to the kva.
2425 * Note: not SMP coherent.
2428 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2433 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2436 static __inline void
2437 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2443 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2444 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2448 * Remove a page from the kernel pagetables.
2449 * Note: not SMP coherent.
2452 pmap_kremove(vm_offset_t va)
2461 * Used to map a range of physical addresses into kernel
2462 * virtual address space.
2464 * The value passed in '*virt' is a suggested virtual address for
2465 * the mapping. Architectures which can support a direct-mapped
2466 * physical to virtual region can return the appropriate address
2467 * within that region, leaving '*virt' unchanged. Other
2468 * architectures should map the pages starting at '*virt' and
2469 * update '*virt' with the first usable address after the mapped
2473 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2475 return PHYS_TO_DMAP(start);
2480 * Add a list of wired pages to the kva
2481 * this routine is only used for temporary
2482 * kernel mappings that do not need to have
2483 * page modification or references recorded.
2484 * Note that old mappings are simply written
2485 * over. The page *must* be wired.
2486 * Note: SMP coherent. Uses a ranged shootdown IPI.
2489 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2491 pt_entry_t *endpte, oldpte, pa, *pte;
2497 endpte = pte + count;
2498 while (pte < endpte) {
2500 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2501 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2502 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2504 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2508 if (__predict_false((oldpte & X86_PG_V) != 0))
2509 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2514 * This routine tears out page mappings from the
2515 * kernel -- it is meant only for temporary mappings.
2516 * Note: SMP coherent. Uses a ranged shootdown IPI.
2519 pmap_qremove(vm_offset_t sva, int count)
2524 while (count-- > 0) {
2525 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2529 pmap_invalidate_range(kernel_pmap, sva, va);
2532 /***************************************************
2533 * Page table page management routines.....
2534 ***************************************************/
2536 * Schedule the specified unused page table page to be freed. Specifically,
2537 * add the page to the specified list of pages that will be released to the
2538 * physical memory manager after the TLB has been updated.
2540 static __inline void
2541 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2542 boolean_t set_PG_ZERO)
2546 m->flags |= PG_ZERO;
2548 m->flags &= ~PG_ZERO;
2549 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2553 * Inserts the specified page table page into the specified pmap's collection
2554 * of idle page table pages. Each of a pmap's page table pages is responsible
2555 * for mapping a distinct range of virtual addresses. The pmap's collection is
2556 * ordered by this virtual address range.
2559 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2562 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2563 return (vm_radix_insert(&pmap->pm_root, mpte));
2567 * Removes the page table page mapping the specified virtual address from the
2568 * specified pmap's collection of idle page table pages, and returns it.
2569 * Otherwise, returns NULL if there is no page table page corresponding to the
2570 * specified virtual address.
2572 static __inline vm_page_t
2573 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2576 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2577 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2581 * Decrements a page table page's wire count, which is used to record the
2582 * number of valid page table entries within the page. If the wire count
2583 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2584 * page table page was unmapped and FALSE otherwise.
2586 static inline boolean_t
2587 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2591 if (m->wire_count == 0) {
2592 _pmap_unwire_ptp(pmap, va, m, free);
2599 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2602 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2604 * unmap the page table page
2606 if (m->pindex >= (NUPDE + NUPDPE)) {
2609 pml4 = pmap_pml4e(pmap, va);
2611 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2612 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2615 } else if (m->pindex >= NUPDE) {
2618 pdp = pmap_pdpe(pmap, va);
2623 pd = pmap_pde(pmap, va);
2626 pmap_resident_count_dec(pmap, 1);
2627 if (m->pindex < NUPDE) {
2628 /* We just released a PT, unhold the matching PD */
2631 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2632 pmap_unwire_ptp(pmap, va, pdpg, free);
2634 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2635 /* We just released a PD, unhold the matching PDP */
2638 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2639 pmap_unwire_ptp(pmap, va, pdppg, free);
2643 * Put page on a list so that it is released after
2644 * *ALL* TLB shootdown is done
2646 pmap_add_delayed_free_list(m, free, TRUE);
2650 * After removing a page table entry, this routine is used to
2651 * conditionally free the page, and manage the hold/wire counts.
2654 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2655 struct spglist *free)
2659 if (va >= VM_MAXUSER_ADDRESS)
2661 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2662 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2663 return (pmap_unwire_ptp(pmap, va, mpte, free));
2667 pmap_pinit0(pmap_t pmap)
2671 PMAP_LOCK_INIT(pmap);
2672 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2673 pmap->pm_pml4u = NULL;
2674 pmap->pm_cr3 = KPML4phys;
2675 /* hack to keep pmap_pti_pcid_invalidate() alive */
2676 pmap->pm_ucr3 = PMAP_NO_CR3;
2677 pmap->pm_root.rt_root = 0;
2678 CPU_ZERO(&pmap->pm_active);
2679 TAILQ_INIT(&pmap->pm_pvchunk);
2680 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2681 pmap->pm_flags = pmap_flags;
2683 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
2684 pmap->pm_pcids[i].pm_gen = 1;
2686 pmap_activate_boot(pmap);
2690 pmap_pinit_pml4(vm_page_t pml4pg)
2692 pml4_entry_t *pm_pml4;
2695 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2697 /* Wire in kernel global address entries. */
2698 for (i = 0; i < NKPML4E; i++) {
2699 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2702 for (i = 0; i < ndmpdpphys; i++) {
2703 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2707 /* install self-referential address mapping entry(s) */
2708 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2709 X86_PG_A | X86_PG_M;
2713 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2715 pml4_entry_t *pm_pml4;
2718 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2719 for (i = 0; i < NPML4EPG; i++)
2720 pm_pml4[i] = pti_pml4[i];
2724 * Initialize a preallocated and zeroed pmap structure,
2725 * such as one in a vmspace structure.
2728 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2730 vm_page_t pml4pg, pml4pgu;
2731 vm_paddr_t pml4phys;
2735 * allocate the page directory page
2737 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2738 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2740 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2741 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2743 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2744 pmap->pm_pcids[i].pm_gen = 0;
2746 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2747 pmap->pm_ucr3 = PMAP_NO_CR3;
2748 pmap->pm_pml4u = NULL;
2750 pmap->pm_type = pm_type;
2751 if ((pml4pg->flags & PG_ZERO) == 0)
2752 pagezero(pmap->pm_pml4);
2755 * Do not install the host kernel mappings in the nested page
2756 * tables. These mappings are meaningless in the guest physical
2758 * Install minimal kernel mappings in PTI case.
2760 if (pm_type == PT_X86) {
2761 pmap->pm_cr3 = pml4phys;
2762 pmap_pinit_pml4(pml4pg);
2764 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2765 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2766 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2767 VM_PAGE_TO_PHYS(pml4pgu));
2768 pmap_pinit_pml4_pti(pml4pgu);
2769 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2773 pmap->pm_root.rt_root = 0;
2774 CPU_ZERO(&pmap->pm_active);
2775 TAILQ_INIT(&pmap->pm_pvchunk);
2776 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2777 pmap->pm_flags = flags;
2778 pmap->pm_eptgen = 0;
2784 pmap_pinit(pmap_t pmap)
2787 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2791 * This routine is called if the desired page table page does not exist.
2793 * If page table page allocation fails, this routine may sleep before
2794 * returning NULL. It sleeps only if a lock pointer was given.
2796 * Note: If a page allocation fails at page table level two or three,
2797 * one or two pages may be held during the wait, only to be released
2798 * afterwards. This conservative approach is easily argued to avoid
2802 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2804 vm_page_t m, pdppg, pdpg;
2805 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2807 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2809 PG_A = pmap_accessed_bit(pmap);
2810 PG_M = pmap_modified_bit(pmap);
2811 PG_V = pmap_valid_bit(pmap);
2812 PG_RW = pmap_rw_bit(pmap);
2815 * Allocate a page table page.
2817 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2818 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2819 if (lockp != NULL) {
2820 RELEASE_PV_LIST_LOCK(lockp);
2822 PMAP_ASSERT_NOT_IN_DI();
2828 * Indicate the need to retry. While waiting, the page table
2829 * page may have been allocated.
2833 if ((m->flags & PG_ZERO) == 0)
2837 * Map the pagetable page into the process address space, if
2838 * it isn't already there.
2841 if (ptepindex >= (NUPDE + NUPDPE)) {
2842 pml4_entry_t *pml4, *pml4u;
2843 vm_pindex_t pml4index;
2845 /* Wire up a new PDPE page */
2846 pml4index = ptepindex - (NUPDE + NUPDPE);
2847 pml4 = &pmap->pm_pml4[pml4index];
2848 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2849 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
2851 * PTI: Make all user-space mappings in the
2852 * kernel-mode page table no-execute so that
2853 * we detect any programming errors that leave
2854 * the kernel-mode page table active on return
2857 if (pmap->pm_ucr3 != PMAP_NO_CR3)
2860 pml4u = &pmap->pm_pml4u[pml4index];
2861 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
2865 } else if (ptepindex >= NUPDE) {
2866 vm_pindex_t pml4index;
2867 vm_pindex_t pdpindex;
2871 /* Wire up a new PDE page */
2872 pdpindex = ptepindex - NUPDE;
2873 pml4index = pdpindex >> NPML4EPGSHIFT;
2875 pml4 = &pmap->pm_pml4[pml4index];
2876 if ((*pml4 & PG_V) == 0) {
2877 /* Have to allocate a new pdp, recurse */
2878 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2880 vm_page_unwire_noq(m);
2881 vm_page_free_zero(m);
2885 /* Add reference to pdp page */
2886 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2887 pdppg->wire_count++;
2889 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2891 /* Now find the pdp page */
2892 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2893 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2896 vm_pindex_t pml4index;
2897 vm_pindex_t pdpindex;
2902 /* Wire up a new PTE page */
2903 pdpindex = ptepindex >> NPDPEPGSHIFT;
2904 pml4index = pdpindex >> NPML4EPGSHIFT;
2906 /* First, find the pdp and check that its valid. */
2907 pml4 = &pmap->pm_pml4[pml4index];
2908 if ((*pml4 & PG_V) == 0) {
2909 /* Have to allocate a new pd, recurse */
2910 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2912 vm_page_unwire_noq(m);
2913 vm_page_free_zero(m);
2916 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2917 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2919 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2920 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2921 if ((*pdp & PG_V) == 0) {
2922 /* Have to allocate a new pd, recurse */
2923 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2925 vm_page_unwire_noq(m);
2926 vm_page_free_zero(m);
2930 /* Add reference to the pd page */
2931 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2935 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2937 /* Now we know where the page directory page is */
2938 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2939 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2942 pmap_resident_count_inc(pmap, 1);
2948 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2950 vm_pindex_t pdpindex, ptepindex;
2951 pdp_entry_t *pdpe, PG_V;
2954 PG_V = pmap_valid_bit(pmap);
2957 pdpe = pmap_pdpe(pmap, va);
2958 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2959 /* Add a reference to the pd page. */
2960 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2963 /* Allocate a pd page. */
2964 ptepindex = pmap_pde_pindex(va);
2965 pdpindex = ptepindex >> NPDPEPGSHIFT;
2966 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2967 if (pdpg == NULL && lockp != NULL)
2974 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2976 vm_pindex_t ptepindex;
2977 pd_entry_t *pd, PG_V;
2980 PG_V = pmap_valid_bit(pmap);
2983 * Calculate pagetable page index
2985 ptepindex = pmap_pde_pindex(va);
2988 * Get the page directory entry
2990 pd = pmap_pde(pmap, va);
2993 * This supports switching from a 2MB page to a
2996 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2997 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2999 * Invalidation of the 2MB page mapping may have caused
3000 * the deallocation of the underlying PD page.
3007 * If the page table page is mapped, we just increment the
3008 * hold count, and activate it.
3010 if (pd != NULL && (*pd & PG_V) != 0) {
3011 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3015 * Here if the pte page isn't mapped, or if it has been
3018 m = _pmap_allocpte(pmap, ptepindex, lockp);
3019 if (m == NULL && lockp != NULL)
3026 /***************************************************
3027 * Pmap allocation/deallocation routines.
3028 ***************************************************/
3031 * Release any resources held by the given physical map.
3032 * Called when a pmap initialized by pmap_pinit is being released.
3033 * Should only be called if the map contains no valid mappings.
3036 pmap_release(pmap_t pmap)
3041 KASSERT(pmap->pm_stats.resident_count == 0,
3042 ("pmap_release: pmap resident count %ld != 0",
3043 pmap->pm_stats.resident_count));
3044 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3045 ("pmap_release: pmap has reserved page table page(s)"));
3046 KASSERT(CPU_EMPTY(&pmap->pm_active),
3047 ("releasing active pmap %p", pmap));
3049 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3051 for (i = 0; i < NKPML4E; i++) /* KVA */
3052 pmap->pm_pml4[KPML4BASE + i] = 0;
3053 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3054 pmap->pm_pml4[DMPML4I + i] = 0;
3055 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3057 vm_page_unwire_noq(m);
3058 vm_page_free_zero(m);
3060 if (pmap->pm_pml4u != NULL) {
3061 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3062 vm_page_unwire_noq(m);
3068 kvm_size(SYSCTL_HANDLER_ARGS)
3070 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3072 return sysctl_handle_long(oidp, &ksize, 0, req);
3074 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3075 0, 0, kvm_size, "LU", "Size of KVM");
3078 kvm_free(SYSCTL_HANDLER_ARGS)
3080 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3082 return sysctl_handle_long(oidp, &kfree, 0, req);
3084 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3085 0, 0, kvm_free, "LU", "Amount of KVM free");
3088 * grow the number of kernel page table entries, if needed
3091 pmap_growkernel(vm_offset_t addr)
3095 pd_entry_t *pde, newpdir;
3098 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3101 * Return if "addr" is within the range of kernel page table pages
3102 * that were preallocated during pmap bootstrap. Moreover, leave
3103 * "kernel_vm_end" and the kernel page table as they were.
3105 * The correctness of this action is based on the following
3106 * argument: vm_map_insert() allocates contiguous ranges of the
3107 * kernel virtual address space. It calls this function if a range
3108 * ends after "kernel_vm_end". If the kernel is mapped between
3109 * "kernel_vm_end" and "addr", then the range cannot begin at
3110 * "kernel_vm_end". In fact, its beginning address cannot be less
3111 * than the kernel. Thus, there is no immediate need to allocate
3112 * any new kernel page table pages between "kernel_vm_end" and
3115 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3118 addr = roundup2(addr, NBPDR);
3119 if (addr - 1 >= vm_map_max(kernel_map))
3120 addr = vm_map_max(kernel_map);
3121 while (kernel_vm_end < addr) {
3122 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3123 if ((*pdpe & X86_PG_V) == 0) {
3124 /* We need a new PDP entry */
3125 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3126 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3127 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3129 panic("pmap_growkernel: no memory to grow kernel");
3130 if ((nkpg->flags & PG_ZERO) == 0)
3131 pmap_zero_page(nkpg);
3132 paddr = VM_PAGE_TO_PHYS(nkpg);
3133 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3134 X86_PG_A | X86_PG_M);
3135 continue; /* try again */
3137 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3138 if ((*pde & X86_PG_V) != 0) {
3139 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3140 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3141 kernel_vm_end = vm_map_max(kernel_map);
3147 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3148 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3151 panic("pmap_growkernel: no memory to grow kernel");
3152 if ((nkpg->flags & PG_ZERO) == 0)
3153 pmap_zero_page(nkpg);
3154 paddr = VM_PAGE_TO_PHYS(nkpg);
3155 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3156 pde_store(pde, newpdir);
3158 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3159 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3160 kernel_vm_end = vm_map_max(kernel_map);
3167 /***************************************************
3168 * page management routines.
3169 ***************************************************/
3171 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3172 CTASSERT(_NPCM == 3);
3173 CTASSERT(_NPCPV == 168);
3175 static __inline struct pv_chunk *
3176 pv_to_chunk(pv_entry_t pv)
3179 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3182 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3184 #define PC_FREE0 0xfffffffffffffffful
3185 #define PC_FREE1 0xfffffffffffffffful
3186 #define PC_FREE2 0x000000fffffffffful
3188 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3191 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3193 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3194 "Current number of pv entry chunks");
3195 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3196 "Current number of pv entry chunks allocated");
3197 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3198 "Current number of pv entry chunks frees");
3199 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3200 "Number of times tried to get a chunk page but failed.");
3202 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3203 static int pv_entry_spare;
3205 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3206 "Current number of pv entry frees");
3207 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3208 "Current number of pv entry allocs");
3209 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3210 "Current number of pv entries");
3211 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3212 "Current number of spare pv entries");
3216 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3221 pmap_invalidate_all(pmap);
3222 if (pmap != locked_pmap)
3225 pmap_delayed_invl_finished();
3229 * We are in a serious low memory condition. Resort to
3230 * drastic measures to free some pages so we can allocate
3231 * another pv entry chunk.
3233 * Returns NULL if PV entries were reclaimed from the specified pmap.
3235 * We do not, however, unmap 2mpages because subsequent accesses will
3236 * allocate per-page pv entries until repromotion occurs, thereby
3237 * exacerbating the shortage of free pv entries.
3240 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3242 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3243 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3244 struct md_page *pvh;
3246 pmap_t next_pmap, pmap;
3247 pt_entry_t *pte, tpte;
3248 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3252 struct spglist free;
3254 int bit, field, freed;
3256 static int active_reclaims = 0;
3258 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3259 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3262 PG_G = PG_A = PG_M = PG_RW = 0;
3264 bzero(&pc_marker_b, sizeof(pc_marker_b));
3265 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3266 pc_marker = (struct pv_chunk *)&pc_marker_b;
3267 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3270 * A delayed invalidation block should already be active if
3271 * pmap_advise() or pmap_remove() called this function by way
3272 * of pmap_demote_pde_locked().
3274 start_di = pmap_not_in_di();
3276 mtx_lock(&pv_chunks_mutex);
3278 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3279 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3280 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3281 SLIST_EMPTY(&free)) {
3282 next_pmap = pc->pc_pmap;
3283 if (next_pmap == NULL) {
3285 * The next chunk is a marker. However, it is
3286 * not our marker, so active_reclaims must be
3287 * > 1. Consequently, the next_chunk code
3288 * will not rotate the pv_chunks list.
3292 mtx_unlock(&pv_chunks_mutex);
3295 * A pv_chunk can only be removed from the pc_lru list
3296 * when both pc_chunks_mutex is owned and the
3297 * corresponding pmap is locked.
3299 if (pmap != next_pmap) {
3300 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3303 /* Avoid deadlock and lock recursion. */
3304 if (pmap > locked_pmap) {
3305 RELEASE_PV_LIST_LOCK(lockp);
3308 pmap_delayed_invl_started();
3309 mtx_lock(&pv_chunks_mutex);
3311 } else if (pmap != locked_pmap) {
3312 if (PMAP_TRYLOCK(pmap)) {
3314 pmap_delayed_invl_started();
3315 mtx_lock(&pv_chunks_mutex);
3318 pmap = NULL; /* pmap is not locked */
3319 mtx_lock(&pv_chunks_mutex);
3320 pc = TAILQ_NEXT(pc_marker, pc_lru);
3322 pc->pc_pmap != next_pmap)
3326 } else if (start_di)
3327 pmap_delayed_invl_started();
3328 PG_G = pmap_global_bit(pmap);
3329 PG_A = pmap_accessed_bit(pmap);
3330 PG_M = pmap_modified_bit(pmap);
3331 PG_RW = pmap_rw_bit(pmap);
3335 * Destroy every non-wired, 4 KB page mapping in the chunk.
3338 for (field = 0; field < _NPCM; field++) {
3339 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3340 inuse != 0; inuse &= ~(1UL << bit)) {
3342 pv = &pc->pc_pventry[field * 64 + bit];
3344 pde = pmap_pde(pmap, va);
3345 if ((*pde & PG_PS) != 0)
3347 pte = pmap_pde_to_pte(pde, va);
3348 if ((*pte & PG_W) != 0)
3350 tpte = pte_load_clear(pte);
3351 if ((tpte & PG_G) != 0)
3352 pmap_invalidate_page(pmap, va);
3353 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3354 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3356 if ((tpte & PG_A) != 0)
3357 vm_page_aflag_set(m, PGA_REFERENCED);
3358 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3359 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3361 if (TAILQ_EMPTY(&m->md.pv_list) &&
3362 (m->flags & PG_FICTITIOUS) == 0) {
3363 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3364 if (TAILQ_EMPTY(&pvh->pv_list)) {
3365 vm_page_aflag_clear(m,
3369 pmap_delayed_invl_page(m);
3370 pc->pc_map[field] |= 1UL << bit;
3371 pmap_unuse_pt(pmap, va, *pde, &free);
3376 mtx_lock(&pv_chunks_mutex);
3379 /* Every freed mapping is for a 4 KB page. */
3380 pmap_resident_count_dec(pmap, freed);
3381 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3382 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3383 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3384 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3385 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3386 pc->pc_map[2] == PC_FREE2) {
3387 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3388 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3389 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3390 /* Entire chunk is free; return it. */
3391 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3392 dump_drop_page(m_pc->phys_addr);
3393 mtx_lock(&pv_chunks_mutex);
3394 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3397 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3398 mtx_lock(&pv_chunks_mutex);
3399 /* One freed pv entry in locked_pmap is sufficient. */
3400 if (pmap == locked_pmap)
3403 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3404 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3405 if (active_reclaims == 1 && pmap != NULL) {
3407 * Rotate the pv chunks list so that we do not
3408 * scan the same pv chunks that could not be
3409 * freed (because they contained a wired
3410 * and/or superpage mapping) on every
3411 * invocation of reclaim_pv_chunk().
3413 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3414 MPASS(pc->pc_pmap != NULL);
3415 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3416 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3420 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3421 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3423 mtx_unlock(&pv_chunks_mutex);
3424 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3425 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3426 m_pc = SLIST_FIRST(&free);
3427 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3428 /* Recycle a freed page table page. */
3429 m_pc->wire_count = 1;
3431 vm_page_free_pages_toq(&free, true);
3436 * free the pv_entry back to the free list
3439 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3441 struct pv_chunk *pc;
3442 int idx, field, bit;
3444 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3445 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3446 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3447 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3448 pc = pv_to_chunk(pv);
3449 idx = pv - &pc->pc_pventry[0];
3452 pc->pc_map[field] |= 1ul << bit;
3453 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3454 pc->pc_map[2] != PC_FREE2) {
3455 /* 98% of the time, pc is already at the head of the list. */
3456 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3457 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3458 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3462 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3467 free_pv_chunk(struct pv_chunk *pc)
3471 mtx_lock(&pv_chunks_mutex);
3472 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3473 mtx_unlock(&pv_chunks_mutex);
3474 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3475 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3476 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3477 /* entire chunk is free, return it */
3478 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3479 dump_drop_page(m->phys_addr);
3480 vm_page_unwire(m, PQ_NONE);
3485 * Returns a new PV entry, allocating a new PV chunk from the system when
3486 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3487 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3490 * The given PV list lock may be released.
3493 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3497 struct pv_chunk *pc;
3500 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3501 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3503 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3505 for (field = 0; field < _NPCM; field++) {
3506 if (pc->pc_map[field]) {
3507 bit = bsfq(pc->pc_map[field]);
3511 if (field < _NPCM) {
3512 pv = &pc->pc_pventry[field * 64 + bit];
3513 pc->pc_map[field] &= ~(1ul << bit);
3514 /* If this was the last item, move it to tail */
3515 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3516 pc->pc_map[2] == 0) {
3517 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3518 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3521 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3522 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3526 /* No free items, allocate another chunk */
3527 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3530 if (lockp == NULL) {
3531 PV_STAT(pc_chunk_tryfail++);
3534 m = reclaim_pv_chunk(pmap, lockp);
3538 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3539 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3540 dump_add_page(m->phys_addr);
3541 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3543 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3544 pc->pc_map[1] = PC_FREE1;
3545 pc->pc_map[2] = PC_FREE2;
3546 mtx_lock(&pv_chunks_mutex);
3547 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3548 mtx_unlock(&pv_chunks_mutex);
3549 pv = &pc->pc_pventry[0];
3550 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3551 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3552 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3557 * Returns the number of one bits within the given PV chunk map.
3559 * The erratas for Intel processors state that "POPCNT Instruction May
3560 * Take Longer to Execute Than Expected". It is believed that the
3561 * issue is the spurious dependency on the destination register.
3562 * Provide a hint to the register rename logic that the destination
3563 * value is overwritten, by clearing it, as suggested in the
3564 * optimization manual. It should be cheap for unaffected processors
3567 * Reference numbers for erratas are
3568 * 4th Gen Core: HSD146
3569 * 5th Gen Core: BDM85
3570 * 6th Gen Core: SKL029
3573 popcnt_pc_map_pq(uint64_t *map)
3577 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3578 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3579 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3580 : "=&r" (result), "=&r" (tmp)
3581 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3586 * Ensure that the number of spare PV entries in the specified pmap meets or
3587 * exceeds the given count, "needed".
3589 * The given PV list lock may be released.
3592 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3594 struct pch new_tail;
3595 struct pv_chunk *pc;
3600 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3601 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3604 * Newly allocated PV chunks must be stored in a private list until
3605 * the required number of PV chunks have been allocated. Otherwise,
3606 * reclaim_pv_chunk() could recycle one of these chunks. In
3607 * contrast, these chunks must be added to the pmap upon allocation.
3609 TAILQ_INIT(&new_tail);
3612 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3614 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3615 bit_count((bitstr_t *)pc->pc_map, 0,
3616 sizeof(pc->pc_map) * NBBY, &free);
3619 free = popcnt_pc_map_pq(pc->pc_map);
3623 if (avail >= needed)
3626 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3627 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3630 m = reclaim_pv_chunk(pmap, lockp);
3635 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3636 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3637 dump_add_page(m->phys_addr);
3638 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3640 pc->pc_map[0] = PC_FREE0;
3641 pc->pc_map[1] = PC_FREE1;
3642 pc->pc_map[2] = PC_FREE2;
3643 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3644 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3645 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3648 * The reclaim might have freed a chunk from the current pmap.
3649 * If that chunk contained available entries, we need to
3650 * re-count the number of available entries.
3655 if (!TAILQ_EMPTY(&new_tail)) {
3656 mtx_lock(&pv_chunks_mutex);
3657 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3658 mtx_unlock(&pv_chunks_mutex);
3663 * First find and then remove the pv entry for the specified pmap and virtual
3664 * address from the specified pv list. Returns the pv entry if found and NULL
3665 * otherwise. This operation can be performed on pv lists for either 4KB or
3666 * 2MB page mappings.
3668 static __inline pv_entry_t
3669 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3673 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3674 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3675 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3684 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3685 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3686 * entries for each of the 4KB page mappings.
3689 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3690 struct rwlock **lockp)
3692 struct md_page *pvh;
3693 struct pv_chunk *pc;
3695 vm_offset_t va_last;
3699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3700 KASSERT((pa & PDRMASK) == 0,
3701 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3702 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3705 * Transfer the 2mpage's pv entry for this mapping to the first
3706 * page's pv list. Once this transfer begins, the pv list lock
3707 * must not be released until the last pv entry is reinstantiated.
3709 pvh = pa_to_pvh(pa);
3710 va = trunc_2mpage(va);
3711 pv = pmap_pvh_remove(pvh, pmap, va);
3712 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3713 m = PHYS_TO_VM_PAGE(pa);
3714 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3716 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3717 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3718 va_last = va + NBPDR - PAGE_SIZE;
3720 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3721 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3722 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3723 for (field = 0; field < _NPCM; field++) {
3724 while (pc->pc_map[field]) {
3725 bit = bsfq(pc->pc_map[field]);
3726 pc->pc_map[field] &= ~(1ul << bit);
3727 pv = &pc->pc_pventry[field * 64 + bit];
3731 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3732 ("pmap_pv_demote_pde: page %p is not managed", m));
3733 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3739 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3740 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3743 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3744 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3745 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3747 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3748 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3751 #if VM_NRESERVLEVEL > 0
3753 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3754 * replace the many pv entries for the 4KB page mappings by a single pv entry
3755 * for the 2MB page mapping.
3758 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3759 struct rwlock **lockp)
3761 struct md_page *pvh;
3763 vm_offset_t va_last;
3766 KASSERT((pa & PDRMASK) == 0,
3767 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3768 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3771 * Transfer the first page's pv entry for this mapping to the 2mpage's
3772 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3773 * a transfer avoids the possibility that get_pv_entry() calls
3774 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3775 * mappings that is being promoted.
3777 m = PHYS_TO_VM_PAGE(pa);
3778 va = trunc_2mpage(va);
3779 pv = pmap_pvh_remove(&m->md, pmap, va);
3780 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3781 pvh = pa_to_pvh(pa);
3782 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3784 /* Free the remaining NPTEPG - 1 pv entries. */
3785 va_last = va + NBPDR - PAGE_SIZE;
3789 pmap_pvh_free(&m->md, pmap, va);
3790 } while (va < va_last);
3792 #endif /* VM_NRESERVLEVEL > 0 */
3795 * First find and then destroy the pv entry for the specified pmap and virtual
3796 * address. This operation can be performed on pv lists for either 4KB or 2MB
3800 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3804 pv = pmap_pvh_remove(pvh, pmap, va);
3805 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3806 free_pv_entry(pmap, pv);
3810 * Conditionally create the PV entry for a 4KB page mapping if the required
3811 * memory can be allocated without resorting to reclamation.
3814 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3815 struct rwlock **lockp)
3819 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3820 /* Pass NULL instead of the lock pointer to disable reclamation. */
3821 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3823 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3824 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3832 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3833 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3834 * false if the PV entry cannot be allocated without resorting to reclamation.
3837 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
3838 struct rwlock **lockp)
3840 struct md_page *pvh;
3844 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3845 /* Pass NULL instead of the lock pointer to disable reclamation. */
3846 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3847 NULL : lockp)) == NULL)
3850 pa = pde & PG_PS_FRAME;
3851 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3852 pvh = pa_to_pvh(pa);
3853 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3859 * Fills a page table page with mappings to consecutive physical pages.
3862 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3866 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3868 newpte += PAGE_SIZE;
3873 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3874 * mapping is invalidated.
3877 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3879 struct rwlock *lock;
3883 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3890 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3891 struct rwlock **lockp)
3893 pd_entry_t newpde, oldpde;
3894 pt_entry_t *firstpte, newpte;
3895 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3898 struct spglist free;
3902 PG_G = pmap_global_bit(pmap);
3903 PG_A = pmap_accessed_bit(pmap);
3904 PG_M = pmap_modified_bit(pmap);
3905 PG_RW = pmap_rw_bit(pmap);
3906 PG_V = pmap_valid_bit(pmap);
3907 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3909 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3911 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3912 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3913 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
3915 KASSERT((oldpde & PG_W) == 0,
3916 ("pmap_demote_pde: page table page for a wired mapping"
3920 * Invalidate the 2MB page mapping and return "failure" if the
3921 * mapping was never accessed or the allocation of the new
3922 * page table page fails. If the 2MB page mapping belongs to
3923 * the direct map region of the kernel's address space, then
3924 * the page allocation request specifies the highest possible
3925 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3926 * normal. Page table pages are preallocated for every other
3927 * part of the kernel address space, so the direct map region
3928 * is the only part of the kernel address space that must be
3931 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3932 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3933 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3934 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3936 sva = trunc_2mpage(va);
3937 pmap_remove_pde(pmap, pde, sva, &free, lockp);
3938 if ((oldpde & PG_G) == 0)
3939 pmap_invalidate_pde_page(pmap, sva, oldpde);
3940 vm_page_free_pages_toq(&free, true);
3941 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3942 " in pmap %p", va, pmap);
3945 if (va < VM_MAXUSER_ADDRESS)
3946 pmap_resident_count_inc(pmap, 1);
3948 mptepa = VM_PAGE_TO_PHYS(mpte);
3949 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3950 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3951 KASSERT((oldpde & PG_A) != 0,
3952 ("pmap_demote_pde: oldpde is missing PG_A"));
3953 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3954 ("pmap_demote_pde: oldpde is missing PG_M"));
3955 newpte = oldpde & ~PG_PS;
3956 newpte = pmap_swap_pat(pmap, newpte);
3959 * If the page table page is new, initialize it.
3961 if (mpte->wire_count == 1) {
3962 mpte->wire_count = NPTEPG;
3963 pmap_fill_ptp(firstpte, newpte);
3965 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3966 ("pmap_demote_pde: firstpte and newpte map different physical"
3970 * If the mapping has changed attributes, update the page table
3973 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3974 pmap_fill_ptp(firstpte, newpte);
3977 * The spare PV entries must be reserved prior to demoting the
3978 * mapping, that is, prior to changing the PDE. Otherwise, the state
3979 * of the PDE and the PV lists will be inconsistent, which can result
3980 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3981 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3982 * PV entry for the 2MB page mapping that is being demoted.
3984 if ((oldpde & PG_MANAGED) != 0)
3985 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3988 * Demote the mapping. This pmap is locked. The old PDE has
3989 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3990 * set. Thus, there is no danger of a race with another
3991 * processor changing the setting of PG_A and/or PG_M between
3992 * the read above and the store below.
3994 if (workaround_erratum383)
3995 pmap_update_pde(pmap, va, pde, newpde);
3997 pde_store(pde, newpde);
4000 * Invalidate a stale recursive mapping of the page table page.
4002 if (va >= VM_MAXUSER_ADDRESS)
4003 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4006 * Demote the PV entry.
4008 if ((oldpde & PG_MANAGED) != 0)
4009 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4011 atomic_add_long(&pmap_pde_demotions, 1);
4012 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
4013 " in pmap %p", va, pmap);
4018 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4021 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4027 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4028 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4029 mpte = pmap_remove_pt_page(pmap, va);
4031 panic("pmap_remove_kernel_pde: Missing pt page.");
4033 mptepa = VM_PAGE_TO_PHYS(mpte);
4034 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4037 * Initialize the page table page.
4039 pagezero((void *)PHYS_TO_DMAP(mptepa));
4042 * Demote the mapping.
4044 if (workaround_erratum383)
4045 pmap_update_pde(pmap, va, pde, newpde);
4047 pde_store(pde, newpde);
4050 * Invalidate a stale recursive mapping of the page table page.
4052 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4056 * pmap_remove_pde: do the things to unmap a superpage in a process
4059 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4060 struct spglist *free, struct rwlock **lockp)
4062 struct md_page *pvh;
4064 vm_offset_t eva, va;
4066 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4068 PG_G = pmap_global_bit(pmap);
4069 PG_A = pmap_accessed_bit(pmap);
4070 PG_M = pmap_modified_bit(pmap);
4071 PG_RW = pmap_rw_bit(pmap);
4073 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4074 KASSERT((sva & PDRMASK) == 0,
4075 ("pmap_remove_pde: sva is not 2mpage aligned"));
4076 oldpde = pte_load_clear(pdq);
4078 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4079 if ((oldpde & PG_G) != 0)
4080 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4081 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4082 if (oldpde & PG_MANAGED) {
4083 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4084 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4085 pmap_pvh_free(pvh, pmap, sva);
4087 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4088 va < eva; va += PAGE_SIZE, m++) {
4089 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4092 vm_page_aflag_set(m, PGA_REFERENCED);
4093 if (TAILQ_EMPTY(&m->md.pv_list) &&
4094 TAILQ_EMPTY(&pvh->pv_list))
4095 vm_page_aflag_clear(m, PGA_WRITEABLE);
4096 pmap_delayed_invl_page(m);
4099 if (pmap == kernel_pmap) {
4100 pmap_remove_kernel_pde(pmap, pdq, sva);
4102 mpte = pmap_remove_pt_page(pmap, sva);
4104 pmap_resident_count_dec(pmap, 1);
4105 KASSERT(mpte->wire_count == NPTEPG,
4106 ("pmap_remove_pde: pte page wire count error"));
4107 mpte->wire_count = 0;
4108 pmap_add_delayed_free_list(mpte, free, FALSE);
4111 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4115 * pmap_remove_pte: do the things to unmap a page in a process
4118 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4119 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4121 struct md_page *pvh;
4122 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4125 PG_A = pmap_accessed_bit(pmap);
4126 PG_M = pmap_modified_bit(pmap);
4127 PG_RW = pmap_rw_bit(pmap);
4129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4130 oldpte = pte_load_clear(ptq);
4132 pmap->pm_stats.wired_count -= 1;
4133 pmap_resident_count_dec(pmap, 1);
4134 if (oldpte & PG_MANAGED) {
4135 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4136 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4139 vm_page_aflag_set(m, PGA_REFERENCED);
4140 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4141 pmap_pvh_free(&m->md, pmap, va);
4142 if (TAILQ_EMPTY(&m->md.pv_list) &&
4143 (m->flags & PG_FICTITIOUS) == 0) {
4144 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4145 if (TAILQ_EMPTY(&pvh->pv_list))
4146 vm_page_aflag_clear(m, PGA_WRITEABLE);
4148 pmap_delayed_invl_page(m);
4150 return (pmap_unuse_pt(pmap, va, ptepde, free));
4154 * Remove a single page from a process address space
4157 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4158 struct spglist *free)
4160 struct rwlock *lock;
4161 pt_entry_t *pte, PG_V;
4163 PG_V = pmap_valid_bit(pmap);
4164 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4165 if ((*pde & PG_V) == 0)
4167 pte = pmap_pde_to_pte(pde, va);
4168 if ((*pte & PG_V) == 0)
4171 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4174 pmap_invalidate_page(pmap, va);
4178 * Removes the specified range of addresses from the page table page.
4181 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4182 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4184 pt_entry_t PG_G, *pte;
4188 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4189 PG_G = pmap_global_bit(pmap);
4192 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4196 pmap_invalidate_range(pmap, va, sva);
4201 if ((*pte & PG_G) == 0)
4205 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4211 pmap_invalidate_range(pmap, va, sva);
4216 * Remove the given range of addresses from the specified map.
4218 * It is assumed that the start and end are properly
4219 * rounded to the page size.
4222 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4224 struct rwlock *lock;
4225 vm_offset_t va_next;
4226 pml4_entry_t *pml4e;
4228 pd_entry_t ptpaddr, *pde;
4229 pt_entry_t PG_G, PG_V;
4230 struct spglist free;
4233 PG_G = pmap_global_bit(pmap);
4234 PG_V = pmap_valid_bit(pmap);
4237 * Perform an unsynchronized read. This is, however, safe.
4239 if (pmap->pm_stats.resident_count == 0)
4245 pmap_delayed_invl_started();
4249 * special handling of removing one page. a very
4250 * common operation and easy to short circuit some
4253 if (sva + PAGE_SIZE == eva) {
4254 pde = pmap_pde(pmap, sva);
4255 if (pde && (*pde & PG_PS) == 0) {
4256 pmap_remove_page(pmap, sva, pde, &free);
4262 for (; sva < eva; sva = va_next) {
4264 if (pmap->pm_stats.resident_count == 0)
4267 pml4e = pmap_pml4e(pmap, sva);
4268 if ((*pml4e & PG_V) == 0) {
4269 va_next = (sva + NBPML4) & ~PML4MASK;
4275 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4276 if ((*pdpe & PG_V) == 0) {
4277 va_next = (sva + NBPDP) & ~PDPMASK;
4284 * Calculate index for next page table.
4286 va_next = (sva + NBPDR) & ~PDRMASK;
4290 pde = pmap_pdpe_to_pde(pdpe, sva);
4294 * Weed out invalid mappings.
4300 * Check for large page.
4302 if ((ptpaddr & PG_PS) != 0) {
4304 * Are we removing the entire large page? If not,
4305 * demote the mapping and fall through.
4307 if (sva + NBPDR == va_next && eva >= va_next) {
4309 * The TLB entry for a PG_G mapping is
4310 * invalidated by pmap_remove_pde().
4312 if ((ptpaddr & PG_G) == 0)
4314 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4316 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4318 /* The large page mapping was destroyed. */
4325 * Limit our scan to either the end of the va represented
4326 * by the current page table page, or to the end of the
4327 * range being removed.
4332 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4339 pmap_invalidate_all(pmap);
4341 pmap_delayed_invl_finished();
4342 vm_page_free_pages_toq(&free, true);
4346 * Routine: pmap_remove_all
4348 * Removes this physical page from
4349 * all physical maps in which it resides.
4350 * Reflects back modify bits to the pager.
4353 * Original versions of this routine were very
4354 * inefficient because they iteratively called
4355 * pmap_remove (slow...)
4359 pmap_remove_all(vm_page_t m)
4361 struct md_page *pvh;
4364 struct rwlock *lock;
4365 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4368 struct spglist free;
4369 int pvh_gen, md_gen;
4371 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4372 ("pmap_remove_all: page %p is not managed", m));
4374 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4375 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4376 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4379 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4381 if (!PMAP_TRYLOCK(pmap)) {
4382 pvh_gen = pvh->pv_gen;
4386 if (pvh_gen != pvh->pv_gen) {
4393 pde = pmap_pde(pmap, va);
4394 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4397 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4399 if (!PMAP_TRYLOCK(pmap)) {
4400 pvh_gen = pvh->pv_gen;
4401 md_gen = m->md.pv_gen;
4405 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4411 PG_A = pmap_accessed_bit(pmap);
4412 PG_M = pmap_modified_bit(pmap);
4413 PG_RW = pmap_rw_bit(pmap);
4414 pmap_resident_count_dec(pmap, 1);
4415 pde = pmap_pde(pmap, pv->pv_va);
4416 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4417 " a 2mpage in page %p's pv list", m));
4418 pte = pmap_pde_to_pte(pde, pv->pv_va);
4419 tpte = pte_load_clear(pte);
4421 pmap->pm_stats.wired_count--;
4423 vm_page_aflag_set(m, PGA_REFERENCED);
4426 * Update the vm_page_t clean and reference bits.
4428 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4430 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4431 pmap_invalidate_page(pmap, pv->pv_va);
4432 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4434 free_pv_entry(pmap, pv);
4437 vm_page_aflag_clear(m, PGA_WRITEABLE);
4439 pmap_delayed_invl_wait(m);
4440 vm_page_free_pages_toq(&free, true);
4444 * pmap_protect_pde: do the things to protect a 2mpage in a process
4447 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4449 pd_entry_t newpde, oldpde;
4450 vm_offset_t eva, va;
4452 boolean_t anychanged;
4453 pt_entry_t PG_G, PG_M, PG_RW;
4455 PG_G = pmap_global_bit(pmap);
4456 PG_M = pmap_modified_bit(pmap);
4457 PG_RW = pmap_rw_bit(pmap);
4459 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4460 KASSERT((sva & PDRMASK) == 0,
4461 ("pmap_protect_pde: sva is not 2mpage aligned"));
4464 oldpde = newpde = *pde;
4465 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4466 (PG_MANAGED | PG_M | PG_RW)) {
4468 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4469 va < eva; va += PAGE_SIZE, m++)
4472 if ((prot & VM_PROT_WRITE) == 0)
4473 newpde &= ~(PG_RW | PG_M);
4474 if ((prot & VM_PROT_EXECUTE) == 0)
4476 if (newpde != oldpde) {
4478 * As an optimization to future operations on this PDE, clear
4479 * PG_PROMOTED. The impending invalidation will remove any
4480 * lingering 4KB page mappings from the TLB.
4482 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4484 if ((oldpde & PG_G) != 0)
4485 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4489 return (anychanged);
4493 * Set the physical protection on the
4494 * specified range of this map as requested.
4497 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4499 vm_offset_t va_next;
4500 pml4_entry_t *pml4e;
4502 pd_entry_t ptpaddr, *pde;
4503 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4504 boolean_t anychanged;
4506 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4507 if (prot == VM_PROT_NONE) {
4508 pmap_remove(pmap, sva, eva);
4512 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4513 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4516 PG_G = pmap_global_bit(pmap);
4517 PG_M = pmap_modified_bit(pmap);
4518 PG_V = pmap_valid_bit(pmap);
4519 PG_RW = pmap_rw_bit(pmap);
4523 * Although this function delays and batches the invalidation
4524 * of stale TLB entries, it does not need to call
4525 * pmap_delayed_invl_started() and
4526 * pmap_delayed_invl_finished(), because it does not
4527 * ordinarily destroy mappings. Stale TLB entries from
4528 * protection-only changes need only be invalidated before the
4529 * pmap lock is released, because protection-only changes do
4530 * not destroy PV entries. Even operations that iterate over
4531 * a physical page's PV list of mappings, like
4532 * pmap_remove_write(), acquire the pmap lock for each
4533 * mapping. Consequently, for protection-only changes, the
4534 * pmap lock suffices to synchronize both page table and TLB
4537 * This function only destroys a mapping if pmap_demote_pde()
4538 * fails. In that case, stale TLB entries are immediately
4543 for (; sva < eva; sva = va_next) {
4545 pml4e = pmap_pml4e(pmap, sva);
4546 if ((*pml4e & PG_V) == 0) {
4547 va_next = (sva + NBPML4) & ~PML4MASK;
4553 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4554 if ((*pdpe & PG_V) == 0) {
4555 va_next = (sva + NBPDP) & ~PDPMASK;
4561 va_next = (sva + NBPDR) & ~PDRMASK;
4565 pde = pmap_pdpe_to_pde(pdpe, sva);
4569 * Weed out invalid mappings.
4575 * Check for large page.
4577 if ((ptpaddr & PG_PS) != 0) {
4579 * Are we protecting the entire large page? If not,
4580 * demote the mapping and fall through.
4582 if (sva + NBPDR == va_next && eva >= va_next) {
4584 * The TLB entry for a PG_G mapping is
4585 * invalidated by pmap_protect_pde().
4587 if (pmap_protect_pde(pmap, pde, sva, prot))
4590 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4592 * The large page mapping was destroyed.
4601 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4603 pt_entry_t obits, pbits;
4607 obits = pbits = *pte;
4608 if ((pbits & PG_V) == 0)
4611 if ((prot & VM_PROT_WRITE) == 0) {
4612 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4613 (PG_MANAGED | PG_M | PG_RW)) {
4614 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4617 pbits &= ~(PG_RW | PG_M);
4619 if ((prot & VM_PROT_EXECUTE) == 0)
4622 if (pbits != obits) {
4623 if (!atomic_cmpset_long(pte, obits, pbits))
4626 pmap_invalidate_page(pmap, sva);
4633 pmap_invalidate_all(pmap);
4637 #if VM_NRESERVLEVEL > 0
4639 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4640 * single page table page (PTP) to a single 2MB page mapping. For promotion
4641 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4642 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4643 * identical characteristics.
4646 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4647 struct rwlock **lockp)
4650 pt_entry_t *firstpte, oldpte, pa, *pte;
4651 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4655 PG_A = pmap_accessed_bit(pmap);
4656 PG_G = pmap_global_bit(pmap);
4657 PG_M = pmap_modified_bit(pmap);
4658 PG_V = pmap_valid_bit(pmap);
4659 PG_RW = pmap_rw_bit(pmap);
4660 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4665 * Examine the first PTE in the specified PTP. Abort if this PTE is
4666 * either invalid, unused, or does not map the first 4KB physical page
4667 * within a 2MB page.
4669 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4672 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4673 atomic_add_long(&pmap_pde_p_failures, 1);
4674 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4675 " in pmap %p", va, pmap);
4678 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4680 * When PG_M is already clear, PG_RW can be cleared without
4681 * a TLB invalidation.
4683 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4689 * Examine each of the other PTEs in the specified PTP. Abort if this
4690 * PTE maps an unexpected 4KB physical page or does not have identical
4691 * characteristics to the first PTE.
4693 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4694 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4697 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4698 atomic_add_long(&pmap_pde_p_failures, 1);
4699 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4700 " in pmap %p", va, pmap);
4703 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4705 * When PG_M is already clear, PG_RW can be cleared
4706 * without a TLB invalidation.
4708 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4711 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4712 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4713 (va & ~PDRMASK), pmap);
4715 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4716 atomic_add_long(&pmap_pde_p_failures, 1);
4717 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4718 " in pmap %p", va, pmap);
4725 * Save the page table page in its current state until the PDE
4726 * mapping the superpage is demoted by pmap_demote_pde() or
4727 * destroyed by pmap_remove_pde().
4729 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4730 KASSERT(mpte >= vm_page_array &&
4731 mpte < &vm_page_array[vm_page_array_size],
4732 ("pmap_promote_pde: page table page is out of range"));
4733 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4734 ("pmap_promote_pde: page table page's pindex is wrong"));
4735 if (pmap_insert_pt_page(pmap, mpte)) {
4736 atomic_add_long(&pmap_pde_p_failures, 1);
4738 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4744 * Promote the pv entries.
4746 if ((newpde & PG_MANAGED) != 0)
4747 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4750 * Propagate the PAT index to its proper position.
4752 newpde = pmap_swap_pat(pmap, newpde);
4755 * Map the superpage.
4757 if (workaround_erratum383)
4758 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4760 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4762 atomic_add_long(&pmap_pde_promotions, 1);
4763 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4764 " in pmap %p", va, pmap);
4766 #endif /* VM_NRESERVLEVEL > 0 */
4769 * Insert the given physical page (p) at
4770 * the specified virtual address (v) in the
4771 * target physical map with the protection requested.
4773 * If specified, the page will be wired down, meaning
4774 * that the related pte can not be reclaimed.
4776 * NB: This is the only routine which MAY NOT lazy-evaluate
4777 * or lose information. That is, this routine must actually
4778 * insert this page into the given map NOW.
4780 * When destroying both a page table and PV entry, this function
4781 * performs the TLB invalidation before releasing the PV list
4782 * lock, so we do not need pmap_delayed_invl_page() calls here.
4785 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4786 u_int flags, int8_t psind)
4788 struct rwlock *lock;
4790 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4791 pt_entry_t newpte, origpte;
4798 PG_A = pmap_accessed_bit(pmap);
4799 PG_G = pmap_global_bit(pmap);
4800 PG_M = pmap_modified_bit(pmap);
4801 PG_V = pmap_valid_bit(pmap);
4802 PG_RW = pmap_rw_bit(pmap);
4804 va = trunc_page(va);
4805 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4806 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4807 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4809 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4810 va >= kmi.clean_eva,
4811 ("pmap_enter: managed mapping within the clean submap"));
4812 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4813 VM_OBJECT_ASSERT_LOCKED(m->object);
4814 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
4815 ("pmap_enter: flags %u has reserved bits set", flags));
4816 pa = VM_PAGE_TO_PHYS(m);
4817 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4818 if ((flags & VM_PROT_WRITE) != 0)
4820 if ((prot & VM_PROT_WRITE) != 0)
4822 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4823 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4824 if ((prot & VM_PROT_EXECUTE) == 0)
4826 if ((flags & PMAP_ENTER_WIRED) != 0)
4828 if (va < VM_MAXUSER_ADDRESS)
4830 if (pmap == kernel_pmap)
4832 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
4835 * Set modified bit gratuitously for writeable mappings if
4836 * the page is unmanaged. We do not want to take a fault
4837 * to do the dirty bit accounting for these mappings.
4839 if ((m->oflags & VPO_UNMANAGED) != 0) {
4840 if ((newpte & PG_RW) != 0)
4843 newpte |= PG_MANAGED;
4848 /* Assert the required virtual and physical alignment. */
4849 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
4850 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4851 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
4857 * In the case that a page table page is not
4858 * resident, we are creating it here.
4861 pde = pmap_pde(pmap, va);
4862 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4863 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4864 pte = pmap_pde_to_pte(pde, va);
4865 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4866 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4869 } else if (va < VM_MAXUSER_ADDRESS) {
4871 * Here if the pte page isn't mapped, or if it has been
4874 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4875 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4876 nosleep ? NULL : &lock);
4877 if (mpte == NULL && nosleep) {
4878 rv = KERN_RESOURCE_SHORTAGE;
4883 panic("pmap_enter: invalid page directory va=%#lx", va);
4889 * Is the specified virtual address already mapped?
4891 if ((origpte & PG_V) != 0) {
4893 * Wiring change, just update stats. We don't worry about
4894 * wiring PT pages as they remain resident as long as there
4895 * are valid mappings in them. Hence, if a user page is wired,
4896 * the PT page will be also.
4898 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4899 pmap->pm_stats.wired_count++;
4900 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4901 pmap->pm_stats.wired_count--;
4904 * Remove the extra PT page reference.
4908 KASSERT(mpte->wire_count > 0,
4909 ("pmap_enter: missing reference to page table page,"
4914 * Has the physical page changed?
4916 opa = origpte & PG_FRAME;
4919 * No, might be a protection or wiring change.
4921 if ((origpte & PG_MANAGED) != 0 &&
4922 (newpte & PG_RW) != 0)
4923 vm_page_aflag_set(m, PGA_WRITEABLE);
4924 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4930 * The physical page has changed. Temporarily invalidate
4931 * the mapping. This ensures that all threads sharing the
4932 * pmap keep a consistent view of the mapping, which is
4933 * necessary for the correct handling of COW faults. It
4934 * also permits reuse of the old mapping's PV entry,
4935 * avoiding an allocation.
4937 * For consistency, handle unmanaged mappings the same way.
4939 origpte = pte_load_clear(pte);
4940 KASSERT((origpte & PG_FRAME) == opa,
4941 ("pmap_enter: unexpected pa update for %#lx", va));
4942 if ((origpte & PG_MANAGED) != 0) {
4943 om = PHYS_TO_VM_PAGE(opa);
4946 * The pmap lock is sufficient to synchronize with
4947 * concurrent calls to pmap_page_test_mappings() and
4948 * pmap_ts_referenced().
4950 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4952 if ((origpte & PG_A) != 0)
4953 vm_page_aflag_set(om, PGA_REFERENCED);
4954 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4955 pv = pmap_pvh_remove(&om->md, pmap, va);
4956 if ((newpte & PG_MANAGED) == 0)
4957 free_pv_entry(pmap, pv);
4958 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4959 TAILQ_EMPTY(&om->md.pv_list) &&
4960 ((om->flags & PG_FICTITIOUS) != 0 ||
4961 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4962 vm_page_aflag_clear(om, PGA_WRITEABLE);
4964 if ((origpte & PG_A) != 0)
4965 pmap_invalidate_page(pmap, va);
4969 * Increment the counters.
4971 if ((newpte & PG_W) != 0)
4972 pmap->pm_stats.wired_count++;
4973 pmap_resident_count_inc(pmap, 1);
4977 * Enter on the PV list if part of our managed memory.
4979 if ((newpte & PG_MANAGED) != 0) {
4981 pv = get_pv_entry(pmap, &lock);
4984 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4985 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4987 if ((newpte & PG_RW) != 0)
4988 vm_page_aflag_set(m, PGA_WRITEABLE);
4994 if ((origpte & PG_V) != 0) {
4996 origpte = pte_load_store(pte, newpte);
4997 KASSERT((origpte & PG_FRAME) == pa,
4998 ("pmap_enter: unexpected pa update for %#lx", va));
4999 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5001 if ((origpte & PG_MANAGED) != 0)
5005 * Although the PTE may still have PG_RW set, TLB
5006 * invalidation may nonetheless be required because
5007 * the PTE no longer has PG_M set.
5009 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5011 * This PTE change does not require TLB invalidation.
5015 if ((origpte & PG_A) != 0)
5016 pmap_invalidate_page(pmap, va);
5018 pte_store(pte, newpte);
5022 #if VM_NRESERVLEVEL > 0
5024 * If both the page table page and the reservation are fully
5025 * populated, then attempt promotion.
5027 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5028 pmap_ps_enabled(pmap) &&
5029 (m->flags & PG_FICTITIOUS) == 0 &&
5030 vm_reserv_level_iffullpop(m) == 0)
5031 pmap_promote_pde(pmap, pde, va, &lock);
5043 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5044 * if successful. Returns false if (1) a page table page cannot be allocated
5045 * without sleeping, (2) a mapping already exists at the specified virtual
5046 * address, or (3) a PV entry cannot be allocated without reclaiming another
5050 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5051 struct rwlock **lockp)
5056 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5057 PG_V = pmap_valid_bit(pmap);
5058 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5060 if ((m->oflags & VPO_UNMANAGED) == 0)
5061 newpde |= PG_MANAGED;
5062 if ((prot & VM_PROT_EXECUTE) == 0)
5064 if (va < VM_MAXUSER_ADDRESS)
5066 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5067 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5072 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5073 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5074 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5075 * a mapping already exists at the specified virtual address. Returns
5076 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5077 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5078 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5080 * The parameter "m" is only used when creating a managed, writeable mapping.
5083 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5084 vm_page_t m, struct rwlock **lockp)
5086 struct spglist free;
5087 pd_entry_t oldpde, *pde;
5088 pt_entry_t PG_G, PG_RW, PG_V;
5091 PG_G = pmap_global_bit(pmap);
5092 PG_RW = pmap_rw_bit(pmap);
5093 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5094 ("pmap_enter_pde: newpde is missing PG_M"));
5095 PG_V = pmap_valid_bit(pmap);
5096 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5098 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5099 NULL : lockp)) == NULL) {
5100 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5101 " in pmap %p", va, pmap);
5102 return (KERN_RESOURCE_SHORTAGE);
5104 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5105 pde = &pde[pmap_pde_index(va)];
5107 if ((oldpde & PG_V) != 0) {
5108 KASSERT(pdpg->wire_count > 1,
5109 ("pmap_enter_pde: pdpg's wire count is too low"));
5110 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5112 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5113 " in pmap %p", va, pmap);
5114 return (KERN_FAILURE);
5116 /* Break the existing mapping(s). */
5118 if ((oldpde & PG_PS) != 0) {
5120 * The reference to the PD page that was acquired by
5121 * pmap_allocpde() ensures that it won't be freed.
5122 * However, if the PDE resulted from a promotion, then
5123 * a reserved PT page could be freed.
5125 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5126 if ((oldpde & PG_G) == 0)
5127 pmap_invalidate_pde_page(pmap, va, oldpde);
5129 pmap_delayed_invl_started();
5130 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5132 pmap_invalidate_all(pmap);
5133 pmap_delayed_invl_finished();
5135 vm_page_free_pages_toq(&free, true);
5136 if (va >= VM_MAXUSER_ADDRESS) {
5137 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5138 if (pmap_insert_pt_page(pmap, mt)) {
5140 * XXX Currently, this can't happen because
5141 * we do not perform pmap_enter(psind == 1)
5142 * on the kernel pmap.
5144 panic("pmap_enter_pde: trie insert failed");
5147 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5150 if ((newpde & PG_MANAGED) != 0) {
5152 * Abort this mapping if its PV entry could not be created.
5154 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5156 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5158 * Although "va" is not mapped, paging-
5159 * structure caches could nonetheless have
5160 * entries that refer to the freed page table
5161 * pages. Invalidate those entries.
5163 pmap_invalidate_page(pmap, va);
5164 vm_page_free_pages_toq(&free, true);
5166 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5167 " in pmap %p", va, pmap);
5168 return (KERN_RESOURCE_SHORTAGE);
5170 if ((newpde & PG_RW) != 0) {
5171 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5172 vm_page_aflag_set(mt, PGA_WRITEABLE);
5177 * Increment counters.
5179 if ((newpde & PG_W) != 0)
5180 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5181 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5184 * Map the superpage. (This is not a promoted mapping; there will not
5185 * be any lingering 4KB page mappings in the TLB.)
5187 pde_store(pde, newpde);
5189 atomic_add_long(&pmap_pde_mappings, 1);
5190 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5191 " in pmap %p", va, pmap);
5192 return (KERN_SUCCESS);
5196 * Maps a sequence of resident pages belonging to the same object.
5197 * The sequence begins with the given page m_start. This page is
5198 * mapped at the given virtual address start. Each subsequent page is
5199 * mapped at a virtual address that is offset from start by the same
5200 * amount as the page is offset from m_start within the object. The
5201 * last page in the sequence is the page with the largest offset from
5202 * m_start that can be mapped at a virtual address less than the given
5203 * virtual address end. Not every virtual page between start and end
5204 * is mapped; only those for which a resident page exists with the
5205 * corresponding offset from m_start are mapped.
5208 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5209 vm_page_t m_start, vm_prot_t prot)
5211 struct rwlock *lock;
5214 vm_pindex_t diff, psize;
5216 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5218 psize = atop(end - start);
5223 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5224 va = start + ptoa(diff);
5225 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5226 m->psind == 1 && pmap_ps_enabled(pmap) &&
5227 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5228 m = &m[NBPDR / PAGE_SIZE - 1];
5230 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5232 m = TAILQ_NEXT(m, listq);
5240 * this code makes some *MAJOR* assumptions:
5241 * 1. Current pmap & pmap exists.
5244 * 4. No page table pages.
5245 * but is *MUCH* faster than pmap_enter...
5249 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5251 struct rwlock *lock;
5255 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5262 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5263 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5265 struct spglist free;
5266 pt_entry_t *pte, PG_V;
5269 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5270 (m->oflags & VPO_UNMANAGED) != 0,
5271 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5272 PG_V = pmap_valid_bit(pmap);
5273 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5276 * In the case that a page table page is not
5277 * resident, we are creating it here.
5279 if (va < VM_MAXUSER_ADDRESS) {
5280 vm_pindex_t ptepindex;
5284 * Calculate pagetable page index
5286 ptepindex = pmap_pde_pindex(va);
5287 if (mpte && (mpte->pindex == ptepindex)) {
5291 * Get the page directory entry
5293 ptepa = pmap_pde(pmap, va);
5296 * If the page table page is mapped, we just increment
5297 * the hold count, and activate it. Otherwise, we
5298 * attempt to allocate a page table page. If this
5299 * attempt fails, we don't retry. Instead, we give up.
5301 if (ptepa && (*ptepa & PG_V) != 0) {
5304 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5308 * Pass NULL instead of the PV list lock
5309 * pointer, because we don't intend to sleep.
5311 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5316 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5317 pte = &pte[pmap_pte_index(va)];
5331 * Enter on the PV list if part of our managed memory.
5333 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5334 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5337 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5339 * Although "va" is not mapped, paging-
5340 * structure caches could nonetheless have
5341 * entries that refer to the freed page table
5342 * pages. Invalidate those entries.
5344 pmap_invalidate_page(pmap, va);
5345 vm_page_free_pages_toq(&free, true);
5353 * Increment counters
5355 pmap_resident_count_inc(pmap, 1);
5357 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
5358 if ((prot & VM_PROT_EXECUTE) == 0)
5362 * Now validate mapping with RO protection
5364 if ((m->oflags & VPO_UNMANAGED) != 0)
5365 pte_store(pte, pa | PG_V | PG_U);
5367 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
5372 * Make a temporary mapping for a physical address. This is only intended
5373 * to be used for panic dumps.
5376 pmap_kenter_temporary(vm_paddr_t pa, int i)
5380 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5381 pmap_kenter(va, pa);
5383 return ((void *)crashdumpmap);
5387 * This code maps large physical mmap regions into the
5388 * processor address space. Note that some shortcuts
5389 * are taken, but the code works.
5392 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5393 vm_pindex_t pindex, vm_size_t size)
5396 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5397 vm_paddr_t pa, ptepa;
5401 PG_A = pmap_accessed_bit(pmap);
5402 PG_M = pmap_modified_bit(pmap);
5403 PG_V = pmap_valid_bit(pmap);
5404 PG_RW = pmap_rw_bit(pmap);
5406 VM_OBJECT_ASSERT_WLOCKED(object);
5407 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5408 ("pmap_object_init_pt: non-device object"));
5409 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5410 if (!pmap_ps_enabled(pmap))
5412 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5414 p = vm_page_lookup(object, pindex);
5415 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5416 ("pmap_object_init_pt: invalid page %p", p));
5417 pat_mode = p->md.pat_mode;
5420 * Abort the mapping if the first page is not physically
5421 * aligned to a 2MB page boundary.
5423 ptepa = VM_PAGE_TO_PHYS(p);
5424 if (ptepa & (NBPDR - 1))
5428 * Skip the first page. Abort the mapping if the rest of
5429 * the pages are not physically contiguous or have differing
5430 * memory attributes.
5432 p = TAILQ_NEXT(p, listq);
5433 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5435 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5436 ("pmap_object_init_pt: invalid page %p", p));
5437 if (pa != VM_PAGE_TO_PHYS(p) ||
5438 pat_mode != p->md.pat_mode)
5440 p = TAILQ_NEXT(p, listq);
5444 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5445 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5446 * will not affect the termination of this loop.
5449 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5450 pa < ptepa + size; pa += NBPDR) {
5451 pdpg = pmap_allocpde(pmap, addr, NULL);
5454 * The creation of mappings below is only an
5455 * optimization. If a page directory page
5456 * cannot be allocated without blocking,
5457 * continue on to the next mapping rather than
5463 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5464 pde = &pde[pmap_pde_index(addr)];
5465 if ((*pde & PG_V) == 0) {
5466 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5467 PG_U | PG_RW | PG_V);
5468 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5469 atomic_add_long(&pmap_pde_mappings, 1);
5471 /* Continue on if the PDE is already valid. */
5473 KASSERT(pdpg->wire_count > 0,
5474 ("pmap_object_init_pt: missing reference "
5475 "to page directory page, va: 0x%lx", addr));
5484 * Clear the wired attribute from the mappings for the specified range of
5485 * addresses in the given pmap. Every valid mapping within that range
5486 * must have the wired attribute set. In contrast, invalid mappings
5487 * cannot have the wired attribute set, so they are ignored.
5489 * The wired attribute of the page table entry is not a hardware
5490 * feature, so there is no need to invalidate any TLB entries.
5491 * Since pmap_demote_pde() for the wired entry must never fail,
5492 * pmap_delayed_invl_started()/finished() calls around the
5493 * function are not needed.
5496 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5498 vm_offset_t va_next;
5499 pml4_entry_t *pml4e;
5502 pt_entry_t *pte, PG_V;
5504 PG_V = pmap_valid_bit(pmap);
5506 for (; sva < eva; sva = va_next) {
5507 pml4e = pmap_pml4e(pmap, sva);
5508 if ((*pml4e & PG_V) == 0) {
5509 va_next = (sva + NBPML4) & ~PML4MASK;
5514 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5515 if ((*pdpe & PG_V) == 0) {
5516 va_next = (sva + NBPDP) & ~PDPMASK;
5521 va_next = (sva + NBPDR) & ~PDRMASK;
5524 pde = pmap_pdpe_to_pde(pdpe, sva);
5525 if ((*pde & PG_V) == 0)
5527 if ((*pde & PG_PS) != 0) {
5528 if ((*pde & PG_W) == 0)
5529 panic("pmap_unwire: pde %#jx is missing PG_W",
5533 * Are we unwiring the entire large page? If not,
5534 * demote the mapping and fall through.
5536 if (sva + NBPDR == va_next && eva >= va_next) {
5537 atomic_clear_long(pde, PG_W);
5538 pmap->pm_stats.wired_count -= NBPDR /
5541 } else if (!pmap_demote_pde(pmap, pde, sva))
5542 panic("pmap_unwire: demotion failed");
5546 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5548 if ((*pte & PG_V) == 0)
5550 if ((*pte & PG_W) == 0)
5551 panic("pmap_unwire: pte %#jx is missing PG_W",
5555 * PG_W must be cleared atomically. Although the pmap
5556 * lock synchronizes access to PG_W, another processor
5557 * could be setting PG_M and/or PG_A concurrently.
5559 atomic_clear_long(pte, PG_W);
5560 pmap->pm_stats.wired_count--;
5567 * Copy the range specified by src_addr/len
5568 * from the source map to the range dst_addr/len
5569 * in the destination map.
5571 * This routine is only advisory and need not do anything.
5575 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5576 vm_offset_t src_addr)
5578 struct rwlock *lock;
5579 struct spglist free;
5581 vm_offset_t end_addr = src_addr + len;
5582 vm_offset_t va_next;
5583 vm_page_t dst_pdpg, dstmpte, srcmpte;
5584 pt_entry_t PG_A, PG_M, PG_V;
5586 if (dst_addr != src_addr)
5589 if (dst_pmap->pm_type != src_pmap->pm_type)
5593 * EPT page table entries that require emulation of A/D bits are
5594 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5595 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5596 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5597 * implementations flag an EPT misconfiguration for exec-only
5598 * mappings we skip this function entirely for emulated pmaps.
5600 if (pmap_emulate_ad_bits(dst_pmap))
5604 if (dst_pmap < src_pmap) {
5605 PMAP_LOCK(dst_pmap);
5606 PMAP_LOCK(src_pmap);
5608 PMAP_LOCK(src_pmap);
5609 PMAP_LOCK(dst_pmap);
5612 PG_A = pmap_accessed_bit(dst_pmap);
5613 PG_M = pmap_modified_bit(dst_pmap);
5614 PG_V = pmap_valid_bit(dst_pmap);
5616 for (addr = src_addr; addr < end_addr; addr = va_next) {
5617 pt_entry_t *src_pte, *dst_pte;
5618 pml4_entry_t *pml4e;
5620 pd_entry_t srcptepaddr, *pde;
5622 KASSERT(addr < UPT_MIN_ADDRESS,
5623 ("pmap_copy: invalid to pmap_copy page tables"));
5625 pml4e = pmap_pml4e(src_pmap, addr);
5626 if ((*pml4e & PG_V) == 0) {
5627 va_next = (addr + NBPML4) & ~PML4MASK;
5633 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5634 if ((*pdpe & PG_V) == 0) {
5635 va_next = (addr + NBPDP) & ~PDPMASK;
5641 va_next = (addr + NBPDR) & ~PDRMASK;
5645 pde = pmap_pdpe_to_pde(pdpe, addr);
5647 if (srcptepaddr == 0)
5650 if (srcptepaddr & PG_PS) {
5651 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5653 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5654 if (dst_pdpg == NULL)
5656 pde = (pd_entry_t *)
5657 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5658 pde = &pde[pmap_pde_index(addr)];
5659 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5660 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5661 PMAP_ENTER_NORECLAIM, &lock))) {
5662 *pde = srcptepaddr & ~PG_W;
5663 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5664 atomic_add_long(&pmap_pde_mappings, 1);
5666 dst_pdpg->wire_count--;
5670 srcptepaddr &= PG_FRAME;
5671 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5672 KASSERT(srcmpte->wire_count > 0,
5673 ("pmap_copy: source page table page is unused"));
5675 if (va_next > end_addr)
5678 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5679 src_pte = &src_pte[pmap_pte_index(addr)];
5681 while (addr < va_next) {
5685 * we only virtual copy managed pages
5687 if ((ptetemp & PG_MANAGED) != 0) {
5688 if (dstmpte != NULL &&
5689 dstmpte->pindex == pmap_pde_pindex(addr))
5690 dstmpte->wire_count++;
5691 else if ((dstmpte = pmap_allocpte(dst_pmap,
5692 addr, NULL)) == NULL)
5694 dst_pte = (pt_entry_t *)
5695 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5696 dst_pte = &dst_pte[pmap_pte_index(addr)];
5697 if (*dst_pte == 0 &&
5698 pmap_try_insert_pv_entry(dst_pmap, addr,
5699 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5702 * Clear the wired, modified, and
5703 * accessed (referenced) bits
5706 *dst_pte = ptetemp & ~(PG_W | PG_M |
5708 pmap_resident_count_inc(dst_pmap, 1);
5711 if (pmap_unwire_ptp(dst_pmap, addr,
5714 * Although "addr" is not
5715 * mapped, paging-structure
5716 * caches could nonetheless
5717 * have entries that refer to
5718 * the freed page table pages.
5719 * Invalidate those entries.
5721 pmap_invalidate_page(dst_pmap,
5723 vm_page_free_pages_toq(&free,
5728 if (dstmpte->wire_count >= srcmpte->wire_count)
5738 PMAP_UNLOCK(src_pmap);
5739 PMAP_UNLOCK(dst_pmap);
5743 * Zero the specified hardware page.
5746 pmap_zero_page(vm_page_t m)
5748 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5750 pagezero((void *)va);
5754 * Zero an an area within a single hardware page. off and size must not
5755 * cover an area beyond a single hardware page.
5758 pmap_zero_page_area(vm_page_t m, int off, int size)
5760 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5762 if (off == 0 && size == PAGE_SIZE)
5763 pagezero((void *)va);
5765 bzero((char *)va + off, size);
5769 * Copy 1 specified hardware page to another.
5772 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5774 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5775 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5777 pagecopy((void *)src, (void *)dst);
5780 int unmapped_buf_allowed = 1;
5783 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5784 vm_offset_t b_offset, int xfersize)
5788 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5792 while (xfersize > 0) {
5793 a_pg_offset = a_offset & PAGE_MASK;
5794 pages[0] = ma[a_offset >> PAGE_SHIFT];
5795 b_pg_offset = b_offset & PAGE_MASK;
5796 pages[1] = mb[b_offset >> PAGE_SHIFT];
5797 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5798 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5799 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5800 a_cp = (char *)vaddr[0] + a_pg_offset;
5801 b_cp = (char *)vaddr[1] + b_pg_offset;
5802 bcopy(a_cp, b_cp, cnt);
5803 if (__predict_false(mapped))
5804 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5812 * Returns true if the pmap's pv is one of the first
5813 * 16 pvs linked to from this page. This count may
5814 * be changed upwards or downwards in the future; it
5815 * is only necessary that true be returned for a small
5816 * subset of pmaps for proper page aging.
5819 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5821 struct md_page *pvh;
5822 struct rwlock *lock;
5827 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5828 ("pmap_page_exists_quick: page %p is not managed", m));
5830 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5832 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5833 if (PV_PMAP(pv) == pmap) {
5841 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5842 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5843 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5844 if (PV_PMAP(pv) == pmap) {
5858 * pmap_page_wired_mappings:
5860 * Return the number of managed mappings to the given physical page
5864 pmap_page_wired_mappings(vm_page_t m)
5866 struct rwlock *lock;
5867 struct md_page *pvh;
5871 int count, md_gen, pvh_gen;
5873 if ((m->oflags & VPO_UNMANAGED) != 0)
5875 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5879 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5881 if (!PMAP_TRYLOCK(pmap)) {
5882 md_gen = m->md.pv_gen;
5886 if (md_gen != m->md.pv_gen) {
5891 pte = pmap_pte(pmap, pv->pv_va);
5892 if ((*pte & PG_W) != 0)
5896 if ((m->flags & PG_FICTITIOUS) == 0) {
5897 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5898 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5900 if (!PMAP_TRYLOCK(pmap)) {
5901 md_gen = m->md.pv_gen;
5902 pvh_gen = pvh->pv_gen;
5906 if (md_gen != m->md.pv_gen ||
5907 pvh_gen != pvh->pv_gen) {
5912 pte = pmap_pde(pmap, pv->pv_va);
5913 if ((*pte & PG_W) != 0)
5923 * Returns TRUE if the given page is mapped individually or as part of
5924 * a 2mpage. Otherwise, returns FALSE.
5927 pmap_page_is_mapped(vm_page_t m)
5929 struct rwlock *lock;
5932 if ((m->oflags & VPO_UNMANAGED) != 0)
5934 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5936 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5937 ((m->flags & PG_FICTITIOUS) == 0 &&
5938 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5944 * Destroy all managed, non-wired mappings in the given user-space
5945 * pmap. This pmap cannot be active on any processor besides the
5948 * This function cannot be applied to the kernel pmap. Moreover, it
5949 * is not intended for general use. It is only to be used during
5950 * process termination. Consequently, it can be implemented in ways
5951 * that make it faster than pmap_remove(). First, it can more quickly
5952 * destroy mappings by iterating over the pmap's collection of PV
5953 * entries, rather than searching the page table. Second, it doesn't
5954 * have to test and clear the page table entries atomically, because
5955 * no processor is currently accessing the user address space. In
5956 * particular, a page table entry's dirty bit won't change state once
5957 * this function starts.
5959 * Although this function destroys all of the pmap's managed,
5960 * non-wired mappings, it can delay and batch the invalidation of TLB
5961 * entries without calling pmap_delayed_invl_started() and
5962 * pmap_delayed_invl_finished(). Because the pmap is not active on
5963 * any other processor, none of these TLB entries will ever be used
5964 * before their eventual invalidation. Consequently, there is no need
5965 * for either pmap_remove_all() or pmap_remove_write() to wait for
5966 * that eventual TLB invalidation.
5969 pmap_remove_pages(pmap_t pmap)
5972 pt_entry_t *pte, tpte;
5973 pt_entry_t PG_M, PG_RW, PG_V;
5974 struct spglist free;
5975 vm_page_t m, mpte, mt;
5977 struct md_page *pvh;
5978 struct pv_chunk *pc, *npc;
5979 struct rwlock *lock;
5981 uint64_t inuse, bitmask;
5982 int allfree, field, freed, idx;
5983 boolean_t superpage;
5987 * Assert that the given pmap is only active on the current
5988 * CPU. Unfortunately, we cannot block another CPU from
5989 * activating the pmap while this function is executing.
5991 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5994 cpuset_t other_cpus;
5996 other_cpus = all_cpus;
5998 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5999 CPU_AND(&other_cpus, &pmap->pm_active);
6001 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6006 PG_M = pmap_modified_bit(pmap);
6007 PG_V = pmap_valid_bit(pmap);
6008 PG_RW = pmap_rw_bit(pmap);
6012 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6015 for (field = 0; field < _NPCM; field++) {
6016 inuse = ~pc->pc_map[field] & pc_freemask[field];
6017 while (inuse != 0) {
6019 bitmask = 1UL << bit;
6020 idx = field * 64 + bit;
6021 pv = &pc->pc_pventry[idx];
6024 pte = pmap_pdpe(pmap, pv->pv_va);
6026 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6028 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6031 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6033 pte = &pte[pmap_pte_index(pv->pv_va)];
6037 * Keep track whether 'tpte' is a
6038 * superpage explicitly instead of
6039 * relying on PG_PS being set.
6041 * This is because PG_PS is numerically
6042 * identical to PG_PTE_PAT and thus a
6043 * regular page could be mistaken for
6049 if ((tpte & PG_V) == 0) {
6050 panic("bad pte va %lx pte %lx",
6055 * We cannot remove wired pages from a process' mapping at this time
6063 pa = tpte & PG_PS_FRAME;
6065 pa = tpte & PG_FRAME;
6067 m = PHYS_TO_VM_PAGE(pa);
6068 KASSERT(m->phys_addr == pa,
6069 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6070 m, (uintmax_t)m->phys_addr,
6073 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6074 m < &vm_page_array[vm_page_array_size],
6075 ("pmap_remove_pages: bad tpte %#jx",
6081 * Update the vm_page_t clean/reference bits.
6083 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6085 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6091 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6094 pc->pc_map[field] |= bitmask;
6096 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6097 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6098 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6100 if (TAILQ_EMPTY(&pvh->pv_list)) {
6101 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6102 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6103 TAILQ_EMPTY(&mt->md.pv_list))
6104 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6106 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6108 pmap_resident_count_dec(pmap, 1);
6109 KASSERT(mpte->wire_count == NPTEPG,
6110 ("pmap_remove_pages: pte page wire count error"));
6111 mpte->wire_count = 0;
6112 pmap_add_delayed_free_list(mpte, &free, FALSE);
6115 pmap_resident_count_dec(pmap, 1);
6116 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6118 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6119 TAILQ_EMPTY(&m->md.pv_list) &&
6120 (m->flags & PG_FICTITIOUS) == 0) {
6121 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6122 if (TAILQ_EMPTY(&pvh->pv_list))
6123 vm_page_aflag_clear(m, PGA_WRITEABLE);
6126 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6130 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6131 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6132 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6134 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6140 pmap_invalidate_all(pmap);
6142 vm_page_free_pages_toq(&free, true);
6146 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6148 struct rwlock *lock;
6150 struct md_page *pvh;
6151 pt_entry_t *pte, mask;
6152 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6154 int md_gen, pvh_gen;
6158 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6161 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6163 if (!PMAP_TRYLOCK(pmap)) {
6164 md_gen = m->md.pv_gen;
6168 if (md_gen != m->md.pv_gen) {
6173 pte = pmap_pte(pmap, pv->pv_va);
6176 PG_M = pmap_modified_bit(pmap);
6177 PG_RW = pmap_rw_bit(pmap);
6178 mask |= PG_RW | PG_M;
6181 PG_A = pmap_accessed_bit(pmap);
6182 PG_V = pmap_valid_bit(pmap);
6183 mask |= PG_V | PG_A;
6185 rv = (*pte & mask) == mask;
6190 if ((m->flags & PG_FICTITIOUS) == 0) {
6191 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6192 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6194 if (!PMAP_TRYLOCK(pmap)) {
6195 md_gen = m->md.pv_gen;
6196 pvh_gen = pvh->pv_gen;
6200 if (md_gen != m->md.pv_gen ||
6201 pvh_gen != pvh->pv_gen) {
6206 pte = pmap_pde(pmap, pv->pv_va);
6209 PG_M = pmap_modified_bit(pmap);
6210 PG_RW = pmap_rw_bit(pmap);
6211 mask |= PG_RW | PG_M;
6214 PG_A = pmap_accessed_bit(pmap);
6215 PG_V = pmap_valid_bit(pmap);
6216 mask |= PG_V | PG_A;
6218 rv = (*pte & mask) == mask;
6232 * Return whether or not the specified physical page was modified
6233 * in any physical maps.
6236 pmap_is_modified(vm_page_t m)
6239 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6240 ("pmap_is_modified: page %p is not managed", m));
6243 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6244 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6245 * is clear, no PTEs can have PG_M set.
6247 VM_OBJECT_ASSERT_WLOCKED(m->object);
6248 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6250 return (pmap_page_test_mappings(m, FALSE, TRUE));
6254 * pmap_is_prefaultable:
6256 * Return whether or not the specified virtual address is eligible
6260 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6263 pt_entry_t *pte, PG_V;
6266 PG_V = pmap_valid_bit(pmap);
6269 pde = pmap_pde(pmap, addr);
6270 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6271 pte = pmap_pde_to_pte(pde, addr);
6272 rv = (*pte & PG_V) == 0;
6279 * pmap_is_referenced:
6281 * Return whether or not the specified physical page was referenced
6282 * in any physical maps.
6285 pmap_is_referenced(vm_page_t m)
6288 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6289 ("pmap_is_referenced: page %p is not managed", m));
6290 return (pmap_page_test_mappings(m, TRUE, FALSE));
6294 * Clear the write and modified bits in each of the given page's mappings.
6297 pmap_remove_write(vm_page_t m)
6299 struct md_page *pvh;
6301 struct rwlock *lock;
6302 pv_entry_t next_pv, pv;
6304 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6306 int pvh_gen, md_gen;
6308 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6309 ("pmap_remove_write: page %p is not managed", m));
6312 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6313 * set by another thread while the object is locked. Thus,
6314 * if PGA_WRITEABLE is clear, no page table entries need updating.
6316 VM_OBJECT_ASSERT_WLOCKED(m->object);
6317 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6319 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6320 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6321 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6324 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6326 if (!PMAP_TRYLOCK(pmap)) {
6327 pvh_gen = pvh->pv_gen;
6331 if (pvh_gen != pvh->pv_gen) {
6337 PG_RW = pmap_rw_bit(pmap);
6339 pde = pmap_pde(pmap, va);
6340 if ((*pde & PG_RW) != 0)
6341 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6342 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6343 ("inconsistent pv lock %p %p for page %p",
6344 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6347 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6349 if (!PMAP_TRYLOCK(pmap)) {
6350 pvh_gen = pvh->pv_gen;
6351 md_gen = m->md.pv_gen;
6355 if (pvh_gen != pvh->pv_gen ||
6356 md_gen != m->md.pv_gen) {
6362 PG_M = pmap_modified_bit(pmap);
6363 PG_RW = pmap_rw_bit(pmap);
6364 pde = pmap_pde(pmap, pv->pv_va);
6365 KASSERT((*pde & PG_PS) == 0,
6366 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6368 pte = pmap_pde_to_pte(pde, pv->pv_va);
6371 if (oldpte & PG_RW) {
6372 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6375 if ((oldpte & PG_M) != 0)
6377 pmap_invalidate_page(pmap, pv->pv_va);
6382 vm_page_aflag_clear(m, PGA_WRITEABLE);
6383 pmap_delayed_invl_wait(m);
6386 static __inline boolean_t
6387 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6390 if (!pmap_emulate_ad_bits(pmap))
6393 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6396 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6397 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6398 * if the EPT_PG_WRITE bit is set.
6400 if ((pte & EPT_PG_WRITE) != 0)
6404 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6406 if ((pte & EPT_PG_EXECUTE) == 0 ||
6407 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6414 * pmap_ts_referenced:
6416 * Return a count of reference bits for a page, clearing those bits.
6417 * It is not necessary for every reference bit to be cleared, but it
6418 * is necessary that 0 only be returned when there are truly no
6419 * reference bits set.
6421 * As an optimization, update the page's dirty field if a modified bit is
6422 * found while counting reference bits. This opportunistic update can be
6423 * performed at low cost and can eliminate the need for some future calls
6424 * to pmap_is_modified(). However, since this function stops after
6425 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6426 * dirty pages. Those dirty pages will only be detected by a future call
6427 * to pmap_is_modified().
6429 * A DI block is not needed within this function, because
6430 * invalidations are performed before the PV list lock is
6434 pmap_ts_referenced(vm_page_t m)
6436 struct md_page *pvh;
6439 struct rwlock *lock;
6440 pd_entry_t oldpde, *pde;
6441 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6444 int cleared, md_gen, not_cleared, pvh_gen;
6445 struct spglist free;
6448 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6449 ("pmap_ts_referenced: page %p is not managed", m));
6452 pa = VM_PAGE_TO_PHYS(m);
6453 lock = PHYS_TO_PV_LIST_LOCK(pa);
6454 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6458 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6459 goto small_mappings;
6465 if (!PMAP_TRYLOCK(pmap)) {
6466 pvh_gen = pvh->pv_gen;
6470 if (pvh_gen != pvh->pv_gen) {
6475 PG_A = pmap_accessed_bit(pmap);
6476 PG_M = pmap_modified_bit(pmap);
6477 PG_RW = pmap_rw_bit(pmap);
6479 pde = pmap_pde(pmap, pv->pv_va);
6481 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6483 * Although "oldpde" is mapping a 2MB page, because
6484 * this function is called at a 4KB page granularity,
6485 * we only update the 4KB page under test.
6489 if ((oldpde & PG_A) != 0) {
6491 * Since this reference bit is shared by 512 4KB
6492 * pages, it should not be cleared every time it is
6493 * tested. Apply a simple "hash" function on the
6494 * physical page number, the virtual superpage number,
6495 * and the pmap address to select one 4KB page out of
6496 * the 512 on which testing the reference bit will
6497 * result in clearing that reference bit. This
6498 * function is designed to avoid the selection of the
6499 * same 4KB page for every 2MB page mapping.
6501 * On demotion, a mapping that hasn't been referenced
6502 * is simply destroyed. To avoid the possibility of a
6503 * subsequent page fault on a demoted wired mapping,
6504 * always leave its reference bit set. Moreover,
6505 * since the superpage is wired, the current state of
6506 * its reference bit won't affect page replacement.
6508 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6509 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6510 (oldpde & PG_W) == 0) {
6511 if (safe_to_clear_referenced(pmap, oldpde)) {
6512 atomic_clear_long(pde, PG_A);
6513 pmap_invalidate_page(pmap, pv->pv_va);
6515 } else if (pmap_demote_pde_locked(pmap, pde,
6516 pv->pv_va, &lock)) {
6518 * Remove the mapping to a single page
6519 * so that a subsequent access may
6520 * repromote. Since the underlying
6521 * page table page is fully populated,
6522 * this removal never frees a page
6526 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6528 pte = pmap_pde_to_pte(pde, va);
6529 pmap_remove_pte(pmap, pte, va, *pde,
6531 pmap_invalidate_page(pmap, va);
6537 * The superpage mapping was removed
6538 * entirely and therefore 'pv' is no
6546 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6547 ("inconsistent pv lock %p %p for page %p",
6548 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6553 /* Rotate the PV list if it has more than one entry. */
6554 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6555 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6556 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6559 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6561 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6563 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6570 if (!PMAP_TRYLOCK(pmap)) {
6571 pvh_gen = pvh->pv_gen;
6572 md_gen = m->md.pv_gen;
6576 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6581 PG_A = pmap_accessed_bit(pmap);
6582 PG_M = pmap_modified_bit(pmap);
6583 PG_RW = pmap_rw_bit(pmap);
6584 pde = pmap_pde(pmap, pv->pv_va);
6585 KASSERT((*pde & PG_PS) == 0,
6586 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6588 pte = pmap_pde_to_pte(pde, pv->pv_va);
6589 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6591 if ((*pte & PG_A) != 0) {
6592 if (safe_to_clear_referenced(pmap, *pte)) {
6593 atomic_clear_long(pte, PG_A);
6594 pmap_invalidate_page(pmap, pv->pv_va);
6596 } else if ((*pte & PG_W) == 0) {
6598 * Wired pages cannot be paged out so
6599 * doing accessed bit emulation for
6600 * them is wasted effort. We do the
6601 * hard work for unwired pages only.
6603 pmap_remove_pte(pmap, pte, pv->pv_va,
6604 *pde, &free, &lock);
6605 pmap_invalidate_page(pmap, pv->pv_va);
6610 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6611 ("inconsistent pv lock %p %p for page %p",
6612 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6617 /* Rotate the PV list if it has more than one entry. */
6618 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6619 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6620 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6623 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6624 not_cleared < PMAP_TS_REFERENCED_MAX);
6627 vm_page_free_pages_toq(&free, true);
6628 return (cleared + not_cleared);
6632 * Apply the given advice to the specified range of addresses within the
6633 * given pmap. Depending on the advice, clear the referenced and/or
6634 * modified flags in each mapping and set the mapped page's dirty field.
6637 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6639 struct rwlock *lock;
6640 pml4_entry_t *pml4e;
6642 pd_entry_t oldpde, *pde;
6643 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6644 vm_offset_t va, va_next;
6646 boolean_t anychanged;
6648 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6652 * A/D bit emulation requires an alternate code path when clearing
6653 * the modified and accessed bits below. Since this function is
6654 * advisory in nature we skip it entirely for pmaps that require
6655 * A/D bit emulation.
6657 if (pmap_emulate_ad_bits(pmap))
6660 PG_A = pmap_accessed_bit(pmap);
6661 PG_G = pmap_global_bit(pmap);
6662 PG_M = pmap_modified_bit(pmap);
6663 PG_V = pmap_valid_bit(pmap);
6664 PG_RW = pmap_rw_bit(pmap);
6666 pmap_delayed_invl_started();
6668 for (; sva < eva; sva = va_next) {
6669 pml4e = pmap_pml4e(pmap, sva);
6670 if ((*pml4e & PG_V) == 0) {
6671 va_next = (sva + NBPML4) & ~PML4MASK;
6676 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6677 if ((*pdpe & PG_V) == 0) {
6678 va_next = (sva + NBPDP) & ~PDPMASK;
6683 va_next = (sva + NBPDR) & ~PDRMASK;
6686 pde = pmap_pdpe_to_pde(pdpe, sva);
6688 if ((oldpde & PG_V) == 0)
6690 else if ((oldpde & PG_PS) != 0) {
6691 if ((oldpde & PG_MANAGED) == 0)
6694 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6699 * The large page mapping was destroyed.
6705 * Unless the page mappings are wired, remove the
6706 * mapping to a single page so that a subsequent
6707 * access may repromote. Since the underlying page
6708 * table page is fully populated, this removal never
6709 * frees a page table page.
6711 if ((oldpde & PG_W) == 0) {
6712 pte = pmap_pde_to_pte(pde, sva);
6713 KASSERT((*pte & PG_V) != 0,
6714 ("pmap_advise: invalid PTE"));
6715 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6725 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6727 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6729 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6730 if (advice == MADV_DONTNEED) {
6732 * Future calls to pmap_is_modified()
6733 * can be avoided by making the page
6736 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6739 atomic_clear_long(pte, PG_M | PG_A);
6740 } else if ((*pte & PG_A) != 0)
6741 atomic_clear_long(pte, PG_A);
6745 if ((*pte & PG_G) != 0) {
6752 if (va != va_next) {
6753 pmap_invalidate_range(pmap, va, sva);
6758 pmap_invalidate_range(pmap, va, sva);
6761 pmap_invalidate_all(pmap);
6763 pmap_delayed_invl_finished();
6767 * Clear the modify bits on the specified physical page.
6770 pmap_clear_modify(vm_page_t m)
6772 struct md_page *pvh;
6774 pv_entry_t next_pv, pv;
6775 pd_entry_t oldpde, *pde;
6776 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6777 struct rwlock *lock;
6779 int md_gen, pvh_gen;
6781 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6782 ("pmap_clear_modify: page %p is not managed", m));
6783 VM_OBJECT_ASSERT_WLOCKED(m->object);
6784 KASSERT(!vm_page_xbusied(m),
6785 ("pmap_clear_modify: page %p is exclusive busied", m));
6788 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6789 * If the object containing the page is locked and the page is not
6790 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6792 if ((m->aflags & PGA_WRITEABLE) == 0)
6794 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6795 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6796 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6799 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6801 if (!PMAP_TRYLOCK(pmap)) {
6802 pvh_gen = pvh->pv_gen;
6806 if (pvh_gen != pvh->pv_gen) {
6811 PG_M = pmap_modified_bit(pmap);
6812 PG_V = pmap_valid_bit(pmap);
6813 PG_RW = pmap_rw_bit(pmap);
6815 pde = pmap_pde(pmap, va);
6817 if ((oldpde & PG_RW) != 0) {
6818 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6819 if ((oldpde & PG_W) == 0) {
6821 * Write protect the mapping to a
6822 * single page so that a subsequent
6823 * write access may repromote.
6825 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6827 pte = pmap_pde_to_pte(pde, va);
6829 if ((oldpte & PG_V) != 0) {
6830 while (!atomic_cmpset_long(pte,
6832 oldpte & ~(PG_M | PG_RW)))
6835 pmap_invalidate_page(pmap, va);
6842 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6844 if (!PMAP_TRYLOCK(pmap)) {
6845 md_gen = m->md.pv_gen;
6846 pvh_gen = pvh->pv_gen;
6850 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6855 PG_M = pmap_modified_bit(pmap);
6856 PG_RW = pmap_rw_bit(pmap);
6857 pde = pmap_pde(pmap, pv->pv_va);
6858 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6859 " a 2mpage in page %p's pv list", m));
6860 pte = pmap_pde_to_pte(pde, pv->pv_va);
6861 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6862 atomic_clear_long(pte, PG_M);
6863 pmap_invalidate_page(pmap, pv->pv_va);
6871 * Miscellaneous support routines follow
6874 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6875 static __inline void
6876 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6881 * The cache mode bits are all in the low 32-bits of the
6882 * PTE, so we can just spin on updating the low 32-bits.
6885 opte = *(u_int *)pte;
6886 npte = opte & ~mask;
6888 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6891 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6892 static __inline void
6893 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6898 * The cache mode bits are all in the low 32-bits of the
6899 * PDE, so we can just spin on updating the low 32-bits.
6902 opde = *(u_int *)pde;
6903 npde = opde & ~mask;
6905 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6909 * Map a set of physical memory pages into the kernel virtual
6910 * address space. Return a pointer to where it is mapped. This
6911 * routine is intended to be used for mapping device memory,
6915 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6917 struct pmap_preinit_mapping *ppim;
6918 vm_offset_t va, offset;
6922 offset = pa & PAGE_MASK;
6923 size = round_page(offset + size);
6924 pa = trunc_page(pa);
6926 if (!pmap_initialized) {
6928 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6929 ppim = pmap_preinit_mapping + i;
6930 if (ppim->va == 0) {
6934 ppim->va = virtual_avail;
6935 virtual_avail += size;
6941 panic("%s: too many preinit mappings", __func__);
6944 * If we have a preinit mapping, re-use it.
6946 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6947 ppim = pmap_preinit_mapping + i;
6948 if (ppim->pa == pa && ppim->sz == size &&
6950 return ((void *)(ppim->va + offset));
6953 * If the specified range of physical addresses fits within
6954 * the direct map window, use the direct map.
6956 if (pa < dmaplimit && pa + size < dmaplimit) {
6957 va = PHYS_TO_DMAP(pa);
6958 if (!pmap_change_attr(va, size, mode))
6959 return ((void *)(va + offset));
6961 va = kva_alloc(size);
6963 panic("%s: Couldn't allocate KVA", __func__);
6965 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6966 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6967 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6968 pmap_invalidate_cache_range(va, va + tmpsize);
6969 return ((void *)(va + offset));
6973 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6976 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6980 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6983 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6987 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6989 struct pmap_preinit_mapping *ppim;
6993 /* If we gave a direct map region in pmap_mapdev, do nothing */
6994 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6996 offset = va & PAGE_MASK;
6997 size = round_page(offset + size);
6998 va = trunc_page(va);
6999 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7000 ppim = pmap_preinit_mapping + i;
7001 if (ppim->va == va && ppim->sz == size) {
7002 if (pmap_initialized)
7008 if (va + size == virtual_avail)
7013 if (pmap_initialized)
7018 * Tries to demote a 1GB page mapping.
7021 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7023 pdp_entry_t newpdpe, oldpdpe;
7024 pd_entry_t *firstpde, newpde, *pde;
7025 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7029 PG_A = pmap_accessed_bit(pmap);
7030 PG_M = pmap_modified_bit(pmap);
7031 PG_V = pmap_valid_bit(pmap);
7032 PG_RW = pmap_rw_bit(pmap);
7034 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7036 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7037 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7038 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7039 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7040 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7041 " in pmap %p", va, pmap);
7044 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7045 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7046 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7047 KASSERT((oldpdpe & PG_A) != 0,
7048 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7049 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7050 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7054 * Initialize the page directory page.
7056 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7062 * Demote the mapping.
7067 * Invalidate a stale recursive mapping of the page directory page.
7069 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7071 pmap_pdpe_demotions++;
7072 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7073 " in pmap %p", va, pmap);
7078 * Sets the memory attribute for the specified page.
7081 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7084 m->md.pat_mode = ma;
7087 * If "m" is a normal page, update its direct mapping. This update
7088 * can be relied upon to perform any cache operations that are
7089 * required for data coherence.
7091 if ((m->flags & PG_FICTITIOUS) == 0 &&
7092 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7094 panic("memory attribute change on the direct map failed");
7098 * Changes the specified virtual address range's memory type to that given by
7099 * the parameter "mode". The specified virtual address range must be
7100 * completely contained within either the direct map or the kernel map. If
7101 * the virtual address range is contained within the kernel map, then the
7102 * memory type for each of the corresponding ranges of the direct map is also
7103 * changed. (The corresponding ranges of the direct map are those ranges that
7104 * map the same physical pages as the specified virtual address range.) These
7105 * changes to the direct map are necessary because Intel describes the
7106 * behavior of their processors as "undefined" if two or more mappings to the
7107 * same physical page have different memory types.
7109 * Returns zero if the change completed successfully, and either EINVAL or
7110 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7111 * of the virtual address range was not mapped, and ENOMEM is returned if
7112 * there was insufficient memory available to complete the change. In the
7113 * latter case, the memory type may have been changed on some part of the
7114 * virtual address range or the direct map.
7117 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7121 PMAP_LOCK(kernel_pmap);
7122 error = pmap_change_attr_locked(va, size, mode);
7123 PMAP_UNLOCK(kernel_pmap);
7128 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
7130 vm_offset_t base, offset, tmpva;
7131 vm_paddr_t pa_start, pa_end, pa_end1;
7135 int cache_bits_pte, cache_bits_pde, error;
7138 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7139 base = trunc_page(va);
7140 offset = va & PAGE_MASK;
7141 size = round_page(offset + size);
7144 * Only supported on kernel virtual addresses, including the direct
7145 * map but excluding the recursive map.
7147 if (base < DMAP_MIN_ADDRESS)
7150 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7151 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7155 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7156 * into 4KB pages if required.
7158 for (tmpva = base; tmpva < base + size; ) {
7159 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7160 if (pdpe == NULL || *pdpe == 0)
7162 if (*pdpe & PG_PS) {
7164 * If the current 1GB page already has the required
7165 * memory type, then we need not demote this page. Just
7166 * increment tmpva to the next 1GB page frame.
7168 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7169 tmpva = trunc_1gpage(tmpva) + NBPDP;
7174 * If the current offset aligns with a 1GB page frame
7175 * and there is at least 1GB left within the range, then
7176 * we need not break down this page into 2MB pages.
7178 if ((tmpva & PDPMASK) == 0 &&
7179 tmpva + PDPMASK < base + size) {
7183 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7186 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7191 * If the current 2MB page already has the required
7192 * memory type, then we need not demote this page. Just
7193 * increment tmpva to the next 2MB page frame.
7195 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7196 tmpva = trunc_2mpage(tmpva) + NBPDR;
7201 * If the current offset aligns with a 2MB page frame
7202 * and there is at least 2MB left within the range, then
7203 * we need not break down this page into 4KB pages.
7205 if ((tmpva & PDRMASK) == 0 &&
7206 tmpva + PDRMASK < base + size) {
7210 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7213 pte = pmap_pde_to_pte(pde, tmpva);
7221 * Ok, all the pages exist, so run through them updating their
7222 * cache mode if required.
7224 pa_start = pa_end = 0;
7225 for (tmpva = base; tmpva < base + size; ) {
7226 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7227 if (*pdpe & PG_PS) {
7228 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7229 pmap_pde_attr(pdpe, cache_bits_pde,
7233 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7234 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7235 if (pa_start == pa_end) {
7236 /* Start physical address run. */
7237 pa_start = *pdpe & PG_PS_FRAME;
7238 pa_end = pa_start + NBPDP;
7239 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7242 /* Run ended, update direct map. */
7243 error = pmap_change_attr_locked(
7244 PHYS_TO_DMAP(pa_start),
7245 pa_end - pa_start, mode);
7248 /* Start physical address run. */
7249 pa_start = *pdpe & PG_PS_FRAME;
7250 pa_end = pa_start + NBPDP;
7253 tmpva = trunc_1gpage(tmpva) + NBPDP;
7256 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7258 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7259 pmap_pde_attr(pde, cache_bits_pde,
7263 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7264 (*pde & PG_PS_FRAME) < dmaplimit) {
7265 if (pa_start == pa_end) {
7266 /* Start physical address run. */
7267 pa_start = *pde & PG_PS_FRAME;
7268 pa_end = pa_start + NBPDR;
7269 } else if (pa_end == (*pde & PG_PS_FRAME))
7272 /* Run ended, update direct map. */
7273 error = pmap_change_attr_locked(
7274 PHYS_TO_DMAP(pa_start),
7275 pa_end - pa_start, mode);
7278 /* Start physical address run. */
7279 pa_start = *pde & PG_PS_FRAME;
7280 pa_end = pa_start + NBPDR;
7283 tmpva = trunc_2mpage(tmpva) + NBPDR;
7285 pte = pmap_pde_to_pte(pde, tmpva);
7286 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7287 pmap_pte_attr(pte, cache_bits_pte,
7291 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7292 (*pte & PG_FRAME) < dmaplimit) {
7293 if (pa_start == pa_end) {
7294 /* Start physical address run. */
7295 pa_start = *pte & PG_FRAME;
7296 pa_end = pa_start + PAGE_SIZE;
7297 } else if (pa_end == (*pte & PG_FRAME))
7298 pa_end += PAGE_SIZE;
7300 /* Run ended, update direct map. */
7301 error = pmap_change_attr_locked(
7302 PHYS_TO_DMAP(pa_start),
7303 pa_end - pa_start, mode);
7306 /* Start physical address run. */
7307 pa_start = *pte & PG_FRAME;
7308 pa_end = pa_start + PAGE_SIZE;
7314 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7315 pa_end1 = MIN(pa_end, dmaplimit);
7316 if (pa_start != pa_end1)
7317 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7318 pa_end1 - pa_start, mode);
7322 * Flush CPU caches if required to make sure any data isn't cached that
7323 * shouldn't be, etc.
7326 pmap_invalidate_range(kernel_pmap, base, tmpva);
7327 pmap_invalidate_cache_range(base, tmpva);
7333 * Demotes any mapping within the direct map region that covers more than the
7334 * specified range of physical addresses. This range's size must be a power
7335 * of two and its starting address must be a multiple of its size. Since the
7336 * demotion does not change any attributes of the mapping, a TLB invalidation
7337 * is not mandatory. The caller may, however, request a TLB invalidation.
7340 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7349 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7350 KASSERT((base & (len - 1)) == 0,
7351 ("pmap_demote_DMAP: base is not a multiple of len"));
7352 if (len < NBPDP && base < dmaplimit) {
7353 va = PHYS_TO_DMAP(base);
7355 PMAP_LOCK(kernel_pmap);
7356 pdpe = pmap_pdpe(kernel_pmap, va);
7357 if ((*pdpe & X86_PG_V) == 0)
7358 panic("pmap_demote_DMAP: invalid PDPE");
7359 if ((*pdpe & PG_PS) != 0) {
7360 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7361 panic("pmap_demote_DMAP: PDPE failed");
7365 pde = pmap_pdpe_to_pde(pdpe, va);
7366 if ((*pde & X86_PG_V) == 0)
7367 panic("pmap_demote_DMAP: invalid PDE");
7368 if ((*pde & PG_PS) != 0) {
7369 if (!pmap_demote_pde(kernel_pmap, pde, va))
7370 panic("pmap_demote_DMAP: PDE failed");
7374 if (changed && invalidate)
7375 pmap_invalidate_page(kernel_pmap, va);
7376 PMAP_UNLOCK(kernel_pmap);
7381 * perform the pmap work for mincore
7384 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7387 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7391 PG_A = pmap_accessed_bit(pmap);
7392 PG_M = pmap_modified_bit(pmap);
7393 PG_V = pmap_valid_bit(pmap);
7394 PG_RW = pmap_rw_bit(pmap);
7398 pdep = pmap_pde(pmap, addr);
7399 if (pdep != NULL && (*pdep & PG_V)) {
7400 if (*pdep & PG_PS) {
7402 /* Compute the physical address of the 4KB page. */
7403 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7405 val = MINCORE_SUPER;
7407 pte = *pmap_pde_to_pte(pdep, addr);
7408 pa = pte & PG_FRAME;
7416 if ((pte & PG_V) != 0) {
7417 val |= MINCORE_INCORE;
7418 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7419 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7420 if ((pte & PG_A) != 0)
7421 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7423 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7424 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7425 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7426 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7427 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7430 PA_UNLOCK_COND(*locked_pa);
7436 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7438 uint32_t gen, new_gen, pcid_next;
7440 CRITICAL_ASSERT(curthread);
7441 gen = PCPU_GET(pcid_gen);
7442 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7443 return (pti ? 0 : CR3_PCID_SAVE);
7444 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7445 return (CR3_PCID_SAVE);
7446 pcid_next = PCPU_GET(pcid_next);
7447 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7448 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7449 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7450 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7451 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7455 PCPU_SET(pcid_gen, new_gen);
7456 pcid_next = PMAP_PCID_KERN + 1;
7460 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7461 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7462 PCPU_SET(pcid_next, pcid_next + 1);
7467 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
7471 cached = pmap_pcid_alloc(pmap, cpuid);
7472 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7473 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7474 pmap->pm_pcids[cpuid].pm_pcid));
7475 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7476 pmap == kernel_pmap,
7477 ("non-kernel pmap pmap %p cpu %d pcid %#x",
7478 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7483 pmap_activate_sw_pti_post(pmap_t pmap)
7486 if (pmap->pm_ucr3 != PMAP_NO_CR3)
7487 PCPU_GET(tssp)->tss_rsp0 = ((vm_offset_t)PCPU_PTR(pti_stack) +
7488 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful;
7492 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
7494 struct invpcid_descr d;
7495 uint64_t cached, cr3, kcr3, ucr3;
7497 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7499 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7500 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
7501 PCPU_SET(curpmap, pmap);
7502 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7503 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7506 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7508 * Explicitly invalidate translations cached from the
7509 * user page table. They are not automatically
7510 * flushed by reload of cr3 with the kernel page table
7513 * Note that the if() condition is resolved statically
7514 * by using the function argument instead of
7515 * runtime-evaluated invpcid_works value.
7517 if (invpcid_works1) {
7518 d.pcid = PMAP_PCID_USER_PT |
7519 pmap->pm_pcids[cpuid].pm_pcid;
7522 invpcid(&d, INVPCID_CTX);
7524 pmap_pti_pcid_invalidate(ucr3, kcr3);
7528 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7529 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7531 PCPU_INC(pm_save_cnt);
7535 pmap_activate_sw_pcid_invpcid_pti(pmap_t pmap, u_int cpuid)
7538 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
7539 pmap_activate_sw_pti_post(pmap);
7543 pmap_activate_sw_pcid_noinvpcid_pti(pmap_t pmap, u_int cpuid)
7548 * If the INVPCID instruction is not available,
7549 * invltlb_pcid_handler() is used to handle an invalidate_all
7550 * IPI, which checks for curpmap == smp_tlb_pmap. The below
7551 * sequence of operations has a window where %CR3 is loaded
7552 * with the new pmap's PML4 address, but the curpmap value has
7553 * not yet been updated. This causes the invltlb IPI handler,
7554 * which is called between the updates, to execute as a NOP,
7555 * which leaves stale TLB entries.
7557 * Note that the most typical use of pmap_activate_sw(), from
7558 * the context switch, is immune to this race, because
7559 * interrupts are disabled (while the thread lock is owned),
7560 * and the IPI happens after curpmap is updated. Protect
7561 * other callers in a similar way, by disabling interrupts
7562 * around the %cr3 register reload and curpmap assignment.
7564 rflags = intr_disable();
7565 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
7566 intr_restore(rflags);
7567 pmap_activate_sw_pti_post(pmap);
7571 pmap_activate_sw_pcid_nopti(pmap_t pmap, u_int cpuid)
7573 uint64_t cached, cr3;
7575 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7577 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7578 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7580 PCPU_SET(curpmap, pmap);
7582 PCPU_INC(pm_save_cnt);
7586 pmap_activate_sw_pcid_noinvpcid_nopti(pmap_t pmap, u_int cpuid)
7590 rflags = intr_disable();
7591 pmap_activate_sw_pcid_nopti(pmap, cpuid);
7592 intr_restore(rflags);
7596 pmap_activate_sw_nopcid_nopti(pmap_t pmap, u_int cpuid __unused)
7599 load_cr3(pmap->pm_cr3);
7600 PCPU_SET(curpmap, pmap);
7604 pmap_activate_sw_nopcid_pti(pmap_t pmap, u_int cpuid __unused)
7607 pmap_activate_sw_nopcid_nopti(pmap, cpuid);
7608 PCPU_SET(kcr3, pmap->pm_cr3);
7609 PCPU_SET(ucr3, pmap->pm_ucr3);
7610 pmap_activate_sw_pti_post(pmap);
7613 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (pmap_t, u_int), static)
7616 if (pmap_pcid_enabled && pti && invpcid_works)
7617 return (pmap_activate_sw_pcid_invpcid_pti);
7618 else if (pmap_pcid_enabled && pti && !invpcid_works)
7619 return (pmap_activate_sw_pcid_noinvpcid_pti);
7620 else if (pmap_pcid_enabled && !pti && invpcid_works)
7621 return (pmap_activate_sw_pcid_nopti);
7622 else if (pmap_pcid_enabled && !pti && !invpcid_works)
7623 return (pmap_activate_sw_pcid_noinvpcid_nopti);
7624 else if (!pmap_pcid_enabled && pti)
7625 return (pmap_activate_sw_nopcid_pti);
7626 else /* if (!pmap_pcid_enabled && !pti) */
7627 return (pmap_activate_sw_nopcid_nopti);
7631 pmap_activate_sw(struct thread *td)
7633 pmap_t oldpmap, pmap;
7636 oldpmap = PCPU_GET(curpmap);
7637 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7638 if (oldpmap == pmap)
7640 cpuid = PCPU_GET(cpuid);
7642 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7644 CPU_SET(cpuid, &pmap->pm_active);
7646 pmap_activate_sw_mode(pmap, cpuid);
7648 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7650 CPU_CLR(cpuid, &oldpmap->pm_active);
7655 pmap_activate(struct thread *td)
7659 pmap_activate_sw(td);
7664 pmap_activate_boot(pmap_t pmap)
7670 * kernel_pmap must be never deactivated, and we ensure that
7671 * by never activating it at all.
7673 MPASS(pmap != kernel_pmap);
7675 cpuid = PCPU_GET(cpuid);
7677 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7679 CPU_SET(cpuid, &pmap->pm_active);
7681 PCPU_SET(curpmap, pmap);
7683 kcr3 = pmap->pm_cr3;
7684 if (pmap_pcid_enabled)
7685 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
7689 PCPU_SET(kcr3, kcr3);
7690 PCPU_SET(ucr3, PMAP_NO_CR3);
7694 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7699 * Increase the starting virtual address of the given mapping if a
7700 * different alignment might result in more superpage mappings.
7703 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7704 vm_offset_t *addr, vm_size_t size)
7706 vm_offset_t superpage_offset;
7710 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7711 offset += ptoa(object->pg_color);
7712 superpage_offset = offset & PDRMASK;
7713 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
7714 (*addr & PDRMASK) == superpage_offset)
7716 if ((*addr & PDRMASK) < superpage_offset)
7717 *addr = (*addr & ~PDRMASK) + superpage_offset;
7719 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
7723 static unsigned long num_dirty_emulations;
7724 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
7725 &num_dirty_emulations, 0, NULL);
7727 static unsigned long num_accessed_emulations;
7728 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
7729 &num_accessed_emulations, 0, NULL);
7731 static unsigned long num_superpage_accessed_emulations;
7732 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
7733 &num_superpage_accessed_emulations, 0, NULL);
7735 static unsigned long ad_emulation_superpage_promotions;
7736 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
7737 &ad_emulation_superpage_promotions, 0, NULL);
7738 #endif /* INVARIANTS */
7741 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
7744 struct rwlock *lock;
7745 #if VM_NRESERVLEVEL > 0
7749 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
7751 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
7752 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
7754 if (!pmap_emulate_ad_bits(pmap))
7757 PG_A = pmap_accessed_bit(pmap);
7758 PG_M = pmap_modified_bit(pmap);
7759 PG_V = pmap_valid_bit(pmap);
7760 PG_RW = pmap_rw_bit(pmap);
7766 pde = pmap_pde(pmap, va);
7767 if (pde == NULL || (*pde & PG_V) == 0)
7770 if ((*pde & PG_PS) != 0) {
7771 if (ftype == VM_PROT_READ) {
7773 atomic_add_long(&num_superpage_accessed_emulations, 1);
7781 pte = pmap_pde_to_pte(pde, va);
7782 if ((*pte & PG_V) == 0)
7785 if (ftype == VM_PROT_WRITE) {
7786 if ((*pte & PG_RW) == 0)
7789 * Set the modified and accessed bits simultaneously.
7791 * Intel EPT PTEs that do software emulation of A/D bits map
7792 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
7793 * An EPT misconfiguration is triggered if the PTE is writable
7794 * but not readable (WR=10). This is avoided by setting PG_A
7795 * and PG_M simultaneously.
7797 *pte |= PG_M | PG_A;
7802 #if VM_NRESERVLEVEL > 0
7803 /* try to promote the mapping */
7804 if (va < VM_MAXUSER_ADDRESS)
7805 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7809 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7811 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
7812 pmap_ps_enabled(pmap) &&
7813 (m->flags & PG_FICTITIOUS) == 0 &&
7814 vm_reserv_level_iffullpop(m) == 0) {
7815 pmap_promote_pde(pmap, pde, va, &lock);
7817 atomic_add_long(&ad_emulation_superpage_promotions, 1);
7823 if (ftype == VM_PROT_WRITE)
7824 atomic_add_long(&num_dirty_emulations, 1);
7826 atomic_add_long(&num_accessed_emulations, 1);
7828 rv = 0; /* success */
7837 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
7842 pt_entry_t *pte, PG_V;
7846 PG_V = pmap_valid_bit(pmap);
7849 pml4 = pmap_pml4e(pmap, va);
7851 if ((*pml4 & PG_V) == 0)
7854 pdp = pmap_pml4e_to_pdpe(pml4, va);
7856 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
7859 pde = pmap_pdpe_to_pde(pdp, va);
7861 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
7864 pte = pmap_pde_to_pte(pde, va);
7873 * Get the kernel virtual address of a set of physical pages. If there are
7874 * physical addresses not covered by the DMAP perform a transient mapping
7875 * that will be removed when calling pmap_unmap_io_transient.
7877 * \param page The pages the caller wishes to obtain the virtual
7878 * address on the kernel memory map.
7879 * \param vaddr On return contains the kernel virtual memory address
7880 * of the pages passed in the page parameter.
7881 * \param count Number of pages passed in.
7882 * \param can_fault TRUE if the thread using the mapped pages can take
7883 * page faults, FALSE otherwise.
7885 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7886 * finished or FALSE otherwise.
7890 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7891 boolean_t can_fault)
7894 boolean_t needs_mapping;
7896 int cache_bits, error __unused, i;
7899 * Allocate any KVA space that we need, this is done in a separate
7900 * loop to prevent calling vmem_alloc while pinned.
7902 needs_mapping = FALSE;
7903 for (i = 0; i < count; i++) {
7904 paddr = VM_PAGE_TO_PHYS(page[i]);
7905 if (__predict_false(paddr >= dmaplimit)) {
7906 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7907 M_BESTFIT | M_WAITOK, &vaddr[i]);
7908 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7909 needs_mapping = TRUE;
7911 vaddr[i] = PHYS_TO_DMAP(paddr);
7915 /* Exit early if everything is covered by the DMAP */
7920 * NB: The sequence of updating a page table followed by accesses
7921 * to the corresponding pages used in the !DMAP case is subject to
7922 * the situation described in the "AMD64 Architecture Programmer's
7923 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7924 * Coherency Considerations". Therefore, issuing the INVLPG right
7925 * after modifying the PTE bits is crucial.
7929 for (i = 0; i < count; i++) {
7930 paddr = VM_PAGE_TO_PHYS(page[i]);
7931 if (paddr >= dmaplimit) {
7934 * Slow path, since we can get page faults
7935 * while mappings are active don't pin the
7936 * thread to the CPU and instead add a global
7937 * mapping visible to all CPUs.
7939 pmap_qenter(vaddr[i], &page[i], 1);
7941 pte = vtopte(vaddr[i]);
7942 cache_bits = pmap_cache_bits(kernel_pmap,
7943 page[i]->md.pat_mode, 0);
7944 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7951 return (needs_mapping);
7955 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7956 boolean_t can_fault)
7963 for (i = 0; i < count; i++) {
7964 paddr = VM_PAGE_TO_PHYS(page[i]);
7965 if (paddr >= dmaplimit) {
7967 pmap_qremove(vaddr[i], 1);
7968 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7974 pmap_quick_enter_page(vm_page_t m)
7978 paddr = VM_PAGE_TO_PHYS(m);
7979 if (paddr < dmaplimit)
7980 return (PHYS_TO_DMAP(paddr));
7981 mtx_lock_spin(&qframe_mtx);
7982 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7983 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7984 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7989 pmap_quick_remove_page(vm_offset_t addr)
7994 pte_store(vtopte(qframe), 0);
7996 mtx_unlock_spin(&qframe_mtx);
8000 pmap_pti_alloc_page(void)
8004 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8005 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
8006 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
8011 pmap_pti_free_page(vm_page_t m)
8014 KASSERT(m->wire_count > 0, ("page %p not wired", m));
8015 if (!vm_page_unwire_noq(m))
8017 vm_page_free_zero(m);
8031 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
8032 VM_OBJECT_WLOCK(pti_obj);
8033 pml4_pg = pmap_pti_alloc_page();
8034 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
8035 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
8036 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
8037 pdpe = pmap_pti_pdpe(va);
8038 pmap_pti_wire_pte(pdpe);
8040 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
8041 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
8042 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
8043 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
8044 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
8045 sizeof(struct gate_descriptor) * NIDT, false);
8046 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
8047 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
8049 /* Doublefault stack IST 1 */
8050 va = common_tss[i].tss_ist1;
8051 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8052 /* NMI stack IST 2 */
8053 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
8054 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8055 /* MC# stack IST 3 */
8056 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
8057 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8058 /* DB# stack IST 4 */
8059 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
8060 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8062 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
8063 (vm_offset_t)etext, true);
8064 pti_finalized = true;
8065 VM_OBJECT_WUNLOCK(pti_obj);
8067 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
8069 static pdp_entry_t *
8070 pmap_pti_pdpe(vm_offset_t va)
8072 pml4_entry_t *pml4e;
8075 vm_pindex_t pml4_idx;
8078 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8080 pml4_idx = pmap_pml4e_index(va);
8081 pml4e = &pti_pml4[pml4_idx];
8085 panic("pml4 alloc after finalization\n");
8086 m = pmap_pti_alloc_page();
8088 pmap_pti_free_page(m);
8089 mphys = *pml4e & ~PAGE_MASK;
8091 mphys = VM_PAGE_TO_PHYS(m);
8092 *pml4e = mphys | X86_PG_RW | X86_PG_V;
8095 mphys = *pml4e & ~PAGE_MASK;
8097 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
8102 pmap_pti_wire_pte(void *pte)
8106 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8107 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8112 pmap_pti_unwire_pde(void *pde, bool only_ref)
8116 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8117 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
8118 MPASS(m->wire_count > 0);
8119 MPASS(only_ref || m->wire_count > 1);
8120 pmap_pti_free_page(m);
8124 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
8129 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8130 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8131 MPASS(m->wire_count > 0);
8132 if (pmap_pti_free_page(m)) {
8133 pde = pmap_pti_pde(va);
8134 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
8136 pmap_pti_unwire_pde(pde, false);
8141 pmap_pti_pde(vm_offset_t va)
8149 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8151 pdpe = pmap_pti_pdpe(va);
8153 m = pmap_pti_alloc_page();
8155 pmap_pti_free_page(m);
8156 MPASS((*pdpe & X86_PG_PS) == 0);
8157 mphys = *pdpe & ~PAGE_MASK;
8159 mphys = VM_PAGE_TO_PHYS(m);
8160 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8163 MPASS((*pdpe & X86_PG_PS) == 0);
8164 mphys = *pdpe & ~PAGE_MASK;
8167 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8168 pd_idx = pmap_pde_index(va);
8174 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8181 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8183 pde = pmap_pti_pde(va);
8184 if (unwire_pde != NULL) {
8186 pmap_pti_wire_pte(pde);
8189 m = pmap_pti_alloc_page();
8191 pmap_pti_free_page(m);
8192 MPASS((*pde & X86_PG_PS) == 0);
8193 mphys = *pde & ~(PAGE_MASK | pg_nx);
8195 mphys = VM_PAGE_TO_PHYS(m);
8196 *pde = mphys | X86_PG_RW | X86_PG_V;
8197 if (unwire_pde != NULL)
8198 *unwire_pde = false;
8201 MPASS((*pde & X86_PG_PS) == 0);
8202 mphys = *pde & ~(PAGE_MASK | pg_nx);
8205 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8206 pte += pmap_pte_index(va);
8212 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8216 pt_entry_t *pte, ptev;
8219 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8221 sva = trunc_page(sva);
8222 MPASS(sva > VM_MAXUSER_ADDRESS);
8223 eva = round_page(eva);
8225 for (; sva < eva; sva += PAGE_SIZE) {
8226 pte = pmap_pti_pte(sva, &unwire_pde);
8227 pa = pmap_kextract(sva);
8228 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8229 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8230 VM_MEMATTR_DEFAULT, FALSE);
8232 pte_store(pte, ptev);
8233 pmap_pti_wire_pte(pte);
8235 KASSERT(!pti_finalized,
8236 ("pti overlap after fin %#lx %#lx %#lx",
8238 KASSERT(*pte == ptev,
8239 ("pti non-identical pte after fin %#lx %#lx %#lx",
8243 pde = pmap_pti_pde(sva);
8244 pmap_pti_unwire_pde(pde, true);
8250 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
8255 VM_OBJECT_WLOCK(pti_obj);
8256 pmap_pti_add_kva_locked(sva, eva, exec);
8257 VM_OBJECT_WUNLOCK(pti_obj);
8261 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
8268 sva = rounddown2(sva, PAGE_SIZE);
8269 MPASS(sva > VM_MAXUSER_ADDRESS);
8270 eva = roundup2(eva, PAGE_SIZE);
8272 VM_OBJECT_WLOCK(pti_obj);
8273 for (va = sva; va < eva; va += PAGE_SIZE) {
8274 pte = pmap_pti_pte(va, NULL);
8275 KASSERT((*pte & X86_PG_V) != 0,
8276 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8277 (u_long)pte, *pte));
8279 pmap_pti_unwire_pte(pte, va);
8281 pmap_invalidate_range(kernel_pmap, sva, eva);
8282 VM_OBJECT_WUNLOCK(pti_obj);
8285 #include "opt_ddb.h"
8287 #include <sys/kdb.h>
8288 #include <ddb/ddb.h>
8290 DB_SHOW_COMMAND(pte, pmap_print_pte)
8296 pt_entry_t *pte, PG_V;
8300 db_printf("show pte addr\n");
8303 va = (vm_offset_t)addr;
8305 if (kdb_thread != NULL)
8306 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
8308 pmap = PCPU_GET(curpmap);
8310 PG_V = pmap_valid_bit(pmap);
8311 pml4 = pmap_pml4e(pmap, va);
8312 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
8313 if ((*pml4 & PG_V) == 0) {
8317 pdp = pmap_pml4e_to_pdpe(pml4, va);
8318 db_printf(" pdpe %#016lx", *pdp);
8319 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
8323 pde = pmap_pdpe_to_pde(pdp, va);
8324 db_printf(" pde %#016lx", *pde);
8325 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
8329 pte = pmap_pde_to_pte(pde, va);
8330 db_printf(" pte %#016lx\n", *pte);
8333 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
8338 a = (vm_paddr_t)addr;
8339 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
8341 db_printf("show phys2dmap addr\n");