2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
326 #define pa_index(pa) ({ \
327 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
328 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
345 #define NPV_LIST_LOCKS MAXCPU
347 #define PHYS_TO_PV_LIST_LOCK(pa) \
348 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
351 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
352 struct rwlock **_lockp = (lockp); \
353 struct rwlock *_new_lock; \
355 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
356 if (_new_lock != *_lockp) { \
357 if (*_lockp != NULL) \
358 rw_wunlock(*_lockp); \
359 *_lockp = _new_lock; \
364 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
365 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
367 #define RELEASE_PV_LIST_LOCK(lockp) do { \
368 struct rwlock **_lockp = (lockp); \
370 if (*_lockp != NULL) { \
371 rw_wunlock(*_lockp); \
376 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
377 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
379 struct pmap kernel_pmap_store;
381 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
382 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
385 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
386 "Number of kernel page table pages allocated on bootup");
389 vm_paddr_t dmaplimit;
390 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
393 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
395 static int pg_ps_enabled = 1;
396 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
397 &pg_ps_enabled, 0, "Are large page mappings enabled?");
399 #define PAT_INDEX_SIZE 8
400 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
402 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
403 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
404 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
405 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
407 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
408 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
409 static int ndmpdpphys; /* number of DMPDPphys pages */
411 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
414 * pmap_mapdev support pre initialization (i.e. console)
416 #define PMAP_PREINIT_MAPPING_COUNT 8
417 static struct pmap_preinit_mapping {
422 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
423 static int pmap_initialized;
426 * Data for the pv entry allocation mechanism.
427 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
431 pc_to_domain(struct pv_chunk *pc)
434 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
438 pc_to_domain(struct pv_chunk *pc __unused)
445 struct pv_chunks_list {
447 TAILQ_HEAD(pch, pv_chunk) pvc_list;
449 } __aligned(CACHE_LINE_SIZE);
451 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
454 struct pmap_large_md_page {
455 struct rwlock pv_lock;
456 struct md_page pv_page;
459 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
460 #define pv_dummy pv_dummy_large.pv_page
461 __read_mostly static struct pmap_large_md_page *pv_table;
462 __read_mostly vm_paddr_t pmap_last_pa;
464 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
465 static u_long pv_invl_gen[NPV_LIST_LOCKS];
466 static struct md_page *pv_table;
467 static struct md_page pv_dummy;
471 * All those kernel PT submaps that BSD is so fond of
473 pt_entry_t *CMAP1 = NULL;
475 static vm_offset_t qframe = 0;
476 static struct mtx qframe_mtx;
478 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
480 static vmem_t *large_vmem;
481 static u_int lm_ents;
482 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
483 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
485 int pmap_pcid_enabled = 1;
486 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
487 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
488 int invpcid_works = 0;
489 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
490 "Is the invpcid instruction available ?");
492 int __read_frequently pti = 0;
493 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
495 "Page Table Isolation enabled");
496 static vm_object_t pti_obj;
497 static pml4_entry_t *pti_pml4;
498 static vm_pindex_t pti_pg_idx;
499 static bool pti_finalized;
501 struct pmap_pkru_range {
502 struct rs_el pkru_rs_el;
507 static uma_zone_t pmap_pkru_ranges_zone;
508 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
509 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
510 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
511 static void *pkru_dup_range(void *ctx, void *data);
512 static void pkru_free_range(void *ctx, void *node);
513 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
514 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
515 static void pmap_pkru_deassign_all(pmap_t pmap);
518 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
525 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
527 return (sysctl_handle_64(oidp, &res, 0, req));
529 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
530 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
531 "Count of saved TLB context on switch");
533 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
534 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
535 static struct mtx invl_gen_mtx;
536 /* Fake lock object to satisfy turnstiles interface. */
537 static struct lock_object invl_gen_ts = {
540 static struct pmap_invl_gen pmap_invl_gen_head = {
544 static u_long pmap_invl_gen = 1;
545 static int pmap_invl_waiters;
546 static struct callout pmap_invl_callout;
547 static bool pmap_invl_callout_inited;
549 #define PMAP_ASSERT_NOT_IN_DI() \
550 KASSERT(pmap_not_in_di(), ("DI already started"))
557 if ((cpu_feature2 & CPUID2_CX16) == 0)
560 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
565 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
569 locked = pmap_di_locked();
570 return (sysctl_handle_int(oidp, &locked, 0, req));
572 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
573 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
574 "Locked delayed invalidation");
576 static bool pmap_not_in_di_l(void);
577 static bool pmap_not_in_di_u(void);
578 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
581 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
585 pmap_not_in_di_l(void)
587 struct pmap_invl_gen *invl_gen;
589 invl_gen = &curthread->td_md.md_invl_gen;
590 return (invl_gen->gen == 0);
594 pmap_thread_init_invl_gen_l(struct thread *td)
596 struct pmap_invl_gen *invl_gen;
598 invl_gen = &td->td_md.md_invl_gen;
603 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
605 struct turnstile *ts;
607 ts = turnstile_trywait(&invl_gen_ts);
608 if (*m_gen > atomic_load_long(invl_gen))
609 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
611 turnstile_cancel(ts);
615 pmap_delayed_invl_finish_unblock(u_long new_gen)
617 struct turnstile *ts;
619 turnstile_chain_lock(&invl_gen_ts);
620 ts = turnstile_lookup(&invl_gen_ts);
622 pmap_invl_gen = new_gen;
624 turnstile_broadcast(ts, TS_SHARED_QUEUE);
625 turnstile_unpend(ts);
627 turnstile_chain_unlock(&invl_gen_ts);
631 * Start a new Delayed Invalidation (DI) block of code, executed by
632 * the current thread. Within a DI block, the current thread may
633 * destroy both the page table and PV list entries for a mapping and
634 * then release the corresponding PV list lock before ensuring that
635 * the mapping is flushed from the TLBs of any processors with the
639 pmap_delayed_invl_start_l(void)
641 struct pmap_invl_gen *invl_gen;
644 invl_gen = &curthread->td_md.md_invl_gen;
645 PMAP_ASSERT_NOT_IN_DI();
646 mtx_lock(&invl_gen_mtx);
647 if (LIST_EMPTY(&pmap_invl_gen_tracker))
648 currgen = pmap_invl_gen;
650 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
651 invl_gen->gen = currgen + 1;
652 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
653 mtx_unlock(&invl_gen_mtx);
657 * Finish the DI block, previously started by the current thread. All
658 * required TLB flushes for the pages marked by
659 * pmap_delayed_invl_page() must be finished before this function is
662 * This function works by bumping the global DI generation number to
663 * the generation number of the current thread's DI, unless there is a
664 * pending DI that started earlier. In the latter case, bumping the
665 * global DI generation number would incorrectly signal that the
666 * earlier DI had finished. Instead, this function bumps the earlier
667 * DI's generation number to match the generation number of the
668 * current thread's DI.
671 pmap_delayed_invl_finish_l(void)
673 struct pmap_invl_gen *invl_gen, *next;
675 invl_gen = &curthread->td_md.md_invl_gen;
676 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
677 mtx_lock(&invl_gen_mtx);
678 next = LIST_NEXT(invl_gen, link);
680 pmap_delayed_invl_finish_unblock(invl_gen->gen);
682 next->gen = invl_gen->gen;
683 LIST_REMOVE(invl_gen, link);
684 mtx_unlock(&invl_gen_mtx);
689 pmap_not_in_di_u(void)
691 struct pmap_invl_gen *invl_gen;
693 invl_gen = &curthread->td_md.md_invl_gen;
694 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
698 pmap_thread_init_invl_gen_u(struct thread *td)
700 struct pmap_invl_gen *invl_gen;
702 invl_gen = &td->td_md.md_invl_gen;
704 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
708 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
710 uint64_t new_high, new_low, old_high, old_low;
713 old_low = new_low = 0;
714 old_high = new_high = (uintptr_t)0;
716 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
717 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
718 : "b"(new_low), "c" (new_high)
721 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
724 out->next = (void *)old_high;
727 out->next = (void *)new_high;
733 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
734 struct pmap_invl_gen *new_val)
736 uint64_t new_high, new_low, old_high, old_low;
739 new_low = new_val->gen;
740 new_high = (uintptr_t)new_val->next;
741 old_low = old_val->gen;
742 old_high = (uintptr_t)old_val->next;
744 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
745 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
746 : "b"(new_low), "c" (new_high)
752 static long invl_start_restart;
753 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
754 &invl_start_restart, 0,
756 static long invl_finish_restart;
757 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
758 &invl_finish_restart, 0,
760 static int invl_max_qlen;
761 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
766 static struct lock_delay_config __read_frequently di_delay;
767 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
770 pmap_delayed_invl_start_u(void)
772 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
774 struct lock_delay_arg lda;
782 invl_gen = &td->td_md.md_invl_gen;
783 PMAP_ASSERT_NOT_IN_DI();
784 lock_delay_arg_init(&lda, &di_delay);
785 invl_gen->saved_pri = 0;
786 pri = td->td_base_pri;
789 pri = td->td_base_pri;
791 invl_gen->saved_pri = pri;
798 for (p = &pmap_invl_gen_head;; p = prev.next) {
800 prevl = atomic_load_ptr(&p->next);
801 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
802 PV_STAT(atomic_add_long(&invl_start_restart, 1));
808 prev.next = (void *)prevl;
811 if ((ii = invl_max_qlen) < i)
812 atomic_cmpset_int(&invl_max_qlen, ii, i);
815 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
816 PV_STAT(atomic_add_long(&invl_start_restart, 1));
821 new_prev.gen = prev.gen;
822 new_prev.next = invl_gen;
823 invl_gen->gen = prev.gen + 1;
825 /* Formal fence between store to invl->gen and updating *p. */
826 atomic_thread_fence_rel();
829 * After inserting an invl_gen element with invalid bit set,
830 * this thread blocks any other thread trying to enter the
831 * delayed invalidation block. Do not allow to remove us from
832 * the CPU, because it causes starvation for other threads.
837 * ABA for *p is not possible there, since p->gen can only
838 * increase. So if the *p thread finished its di, then
839 * started a new one and got inserted into the list at the
840 * same place, its gen will appear greater than the previously
843 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
845 PV_STAT(atomic_add_long(&invl_start_restart, 1));
851 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
852 * invl_gen->next, allowing other threads to iterate past us.
853 * pmap_di_store_invl() provides fence between the generation
854 * write and the update of next.
856 invl_gen->next = NULL;
861 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
862 struct pmap_invl_gen *p)
864 struct pmap_invl_gen prev, new_prev;
868 * Load invl_gen->gen after setting invl_gen->next
869 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
870 * generations to propagate to our invl_gen->gen. Lock prefix
871 * in atomic_set_ptr() worked as seq_cst fence.
873 mygen = atomic_load_long(&invl_gen->gen);
875 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
878 KASSERT(prev.gen < mygen,
879 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
880 new_prev.gen = mygen;
881 new_prev.next = (void *)((uintptr_t)invl_gen->next &
882 ~PMAP_INVL_GEN_NEXT_INVALID);
884 /* Formal fence between load of prev and storing update to it. */
885 atomic_thread_fence_rel();
887 return (pmap_di_store_invl(p, &prev, &new_prev));
891 pmap_delayed_invl_finish_u(void)
893 struct pmap_invl_gen *invl_gen, *p;
895 struct lock_delay_arg lda;
899 invl_gen = &td->td_md.md_invl_gen;
900 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
901 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
902 ("missed invl_start: INVALID"));
903 lock_delay_arg_init(&lda, &di_delay);
906 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
907 prevl = atomic_load_ptr(&p->next);
908 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
909 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
913 if ((void *)prevl == invl_gen)
918 * It is legitimate to not find ourself on the list if a
919 * thread before us finished its DI and started it again.
921 if (__predict_false(p == NULL)) {
922 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
928 atomic_set_ptr((uintptr_t *)&invl_gen->next,
929 PMAP_INVL_GEN_NEXT_INVALID);
930 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
931 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
932 PMAP_INVL_GEN_NEXT_INVALID);
934 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
939 if (atomic_load_int(&pmap_invl_waiters) > 0)
940 pmap_delayed_invl_finish_unblock(0);
941 if (invl_gen->saved_pri != 0) {
943 sched_prio(td, invl_gen->saved_pri);
949 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
951 struct pmap_invl_gen *p, *pn;
956 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
958 nextl = atomic_load_ptr(&p->next);
959 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
960 td = first ? NULL : __containerof(p, struct thread,
962 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
963 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
964 td != NULL ? td->td_tid : -1);
970 static long invl_wait;
971 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
972 "Number of times DI invalidation blocked pmap_remove_all/write");
973 static long invl_wait_slow;
974 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
975 "Number of slow invalidation waits for lockless DI");
980 pmap_delayed_invl_genp(vm_page_t m)
985 pa = VM_PAGE_TO_PHYS(m);
986 if (__predict_false((pa) > pmap_last_pa))
987 gen = &pv_dummy_large.pv_invl_gen;
989 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
995 pmap_delayed_invl_genp(vm_page_t m)
998 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1003 pmap_delayed_invl_callout_func(void *arg __unused)
1006 if (atomic_load_int(&pmap_invl_waiters) == 0)
1008 pmap_delayed_invl_finish_unblock(0);
1012 pmap_delayed_invl_callout_init(void *arg __unused)
1015 if (pmap_di_locked())
1017 callout_init(&pmap_invl_callout, 1);
1018 pmap_invl_callout_inited = true;
1020 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1021 pmap_delayed_invl_callout_init, NULL);
1024 * Ensure that all currently executing DI blocks, that need to flush
1025 * TLB for the given page m, actually flushed the TLB at the time the
1026 * function returned. If the page m has an empty PV list and we call
1027 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1028 * valid mapping for the page m in either its page table or TLB.
1030 * This function works by blocking until the global DI generation
1031 * number catches up with the generation number associated with the
1032 * given page m and its PV list. Since this function's callers
1033 * typically own an object lock and sometimes own a page lock, it
1034 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1038 pmap_delayed_invl_wait_l(vm_page_t m)
1042 bool accounted = false;
1045 m_gen = pmap_delayed_invl_genp(m);
1046 while (*m_gen > pmap_invl_gen) {
1049 atomic_add_long(&invl_wait, 1);
1053 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1058 pmap_delayed_invl_wait_u(vm_page_t m)
1061 struct lock_delay_arg lda;
1065 m_gen = pmap_delayed_invl_genp(m);
1066 lock_delay_arg_init(&lda, &di_delay);
1067 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1068 if (fast || !pmap_invl_callout_inited) {
1069 PV_STAT(atomic_add_long(&invl_wait, 1));
1074 * The page's invalidation generation number
1075 * is still below the current thread's number.
1076 * Prepare to block so that we do not waste
1077 * CPU cycles or worse, suffer livelock.
1079 * Since it is impossible to block without
1080 * racing with pmap_delayed_invl_finish_u(),
1081 * prepare for the race by incrementing
1082 * pmap_invl_waiters and arming a 1-tick
1083 * callout which will unblock us if we lose
1086 atomic_add_int(&pmap_invl_waiters, 1);
1089 * Re-check the current thread's invalidation
1090 * generation after incrementing
1091 * pmap_invl_waiters, so that there is no race
1092 * with pmap_delayed_invl_finish_u() setting
1093 * the page generation and checking
1094 * pmap_invl_waiters. The only race allowed
1095 * is for a missed unblock, which is handled
1099 atomic_load_long(&pmap_invl_gen_head.gen)) {
1100 callout_reset(&pmap_invl_callout, 1,
1101 pmap_delayed_invl_callout_func, NULL);
1102 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1103 pmap_delayed_invl_wait_block(m_gen,
1104 &pmap_invl_gen_head.gen);
1106 atomic_add_int(&pmap_invl_waiters, -1);
1111 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1114 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1115 pmap_thread_init_invl_gen_u);
1118 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1121 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1122 pmap_delayed_invl_start_u);
1125 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1128 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1129 pmap_delayed_invl_finish_u);
1132 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1135 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1136 pmap_delayed_invl_wait_u);
1140 * Mark the page m's PV list as participating in the current thread's
1141 * DI block. Any threads concurrently using m's PV list to remove or
1142 * restrict all mappings to m will wait for the current thread's DI
1143 * block to complete before proceeding.
1145 * The function works by setting the DI generation number for m's PV
1146 * list to at least the DI generation number of the current thread.
1147 * This forces a caller of pmap_delayed_invl_wait() to block until
1148 * current thread calls pmap_delayed_invl_finish().
1151 pmap_delayed_invl_page(vm_page_t m)
1155 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1156 gen = curthread->td_md.md_invl_gen.gen;
1159 m_gen = pmap_delayed_invl_genp(m);
1167 static caddr_t crashdumpmap;
1170 * Internal flags for pmap_enter()'s helper functions.
1172 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1173 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1176 * Internal flags for pmap_mapdev_internal() and
1177 * pmap_change_props_locked().
1179 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1180 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1181 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1183 TAILQ_HEAD(pv_chunklist, pv_chunk);
1185 static void free_pv_chunk(struct pv_chunk *pc);
1186 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1187 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1188 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1189 static int popcnt_pc_map_pq(uint64_t *map);
1190 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1191 static void reserve_pv_entries(pmap_t pmap, int needed,
1192 struct rwlock **lockp);
1193 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1194 struct rwlock **lockp);
1195 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1196 u_int flags, struct rwlock **lockp);
1197 #if VM_NRESERVLEVEL > 0
1198 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1199 struct rwlock **lockp);
1201 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1202 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1205 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1206 vm_prot_t prot, int mode, int flags);
1207 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1208 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1209 vm_offset_t va, struct rwlock **lockp);
1210 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1212 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1213 vm_prot_t prot, struct rwlock **lockp);
1214 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1215 u_int flags, vm_page_t m, struct rwlock **lockp);
1216 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1217 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1218 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1219 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1220 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1222 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1224 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1226 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1227 static vm_page_t pmap_large_map_getptp_unlocked(void);
1228 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1229 #if VM_NRESERVLEVEL > 0
1230 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1231 struct rwlock **lockp);
1233 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1235 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1236 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1238 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1239 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1240 static void pmap_pti_wire_pte(void *pte);
1241 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1242 struct spglist *free, struct rwlock **lockp);
1243 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1244 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1245 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1246 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1247 struct spglist *free);
1248 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1249 pd_entry_t *pde, struct spglist *free,
1250 struct rwlock **lockp);
1251 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1252 vm_page_t m, struct rwlock **lockp);
1253 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1255 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1257 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1258 struct rwlock **lockp);
1259 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1260 struct rwlock **lockp);
1261 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1262 struct rwlock **lockp);
1264 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1265 struct spglist *free);
1266 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1268 /********************/
1269 /* Inline functions */
1270 /********************/
1272 /* Return a non-clipped PD index for a given VA */
1273 static __inline vm_pindex_t
1274 pmap_pde_pindex(vm_offset_t va)
1276 return (va >> PDRSHIFT);
1280 /* Return a pointer to the PML4 slot that corresponds to a VA */
1281 static __inline pml4_entry_t *
1282 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1285 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1288 /* Return a pointer to the PDP slot that corresponds to a VA */
1289 static __inline pdp_entry_t *
1290 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1294 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1295 return (&pdpe[pmap_pdpe_index(va)]);
1298 /* Return a pointer to the PDP slot that corresponds to a VA */
1299 static __inline pdp_entry_t *
1300 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1302 pml4_entry_t *pml4e;
1305 PG_V = pmap_valid_bit(pmap);
1306 pml4e = pmap_pml4e(pmap, va);
1307 if ((*pml4e & PG_V) == 0)
1309 return (pmap_pml4e_to_pdpe(pml4e, va));
1312 /* Return a pointer to the PD slot that corresponds to a VA */
1313 static __inline pd_entry_t *
1314 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1318 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1319 return (&pde[pmap_pde_index(va)]);
1322 /* Return a pointer to the PD slot that corresponds to a VA */
1323 static __inline pd_entry_t *
1324 pmap_pde(pmap_t pmap, vm_offset_t va)
1329 PG_V = pmap_valid_bit(pmap);
1330 pdpe = pmap_pdpe(pmap, va);
1331 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1333 return (pmap_pdpe_to_pde(pdpe, va));
1336 /* Return a pointer to the PT slot that corresponds to a VA */
1337 static __inline pt_entry_t *
1338 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1342 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1343 return (&pte[pmap_pte_index(va)]);
1346 /* Return a pointer to the PT slot that corresponds to a VA */
1347 static __inline pt_entry_t *
1348 pmap_pte(pmap_t pmap, vm_offset_t va)
1353 PG_V = pmap_valid_bit(pmap);
1354 pde = pmap_pde(pmap, va);
1355 if (pde == NULL || (*pde & PG_V) == 0)
1357 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1358 return ((pt_entry_t *)pde);
1359 return (pmap_pde_to_pte(pde, va));
1362 static __inline void
1363 pmap_resident_count_inc(pmap_t pmap, int count)
1366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1367 pmap->pm_stats.resident_count += count;
1370 static __inline void
1371 pmap_resident_count_dec(pmap_t pmap, int count)
1374 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1375 KASSERT(pmap->pm_stats.resident_count >= count,
1376 ("pmap %p resident count underflow %ld %d", pmap,
1377 pmap->pm_stats.resident_count, count));
1378 pmap->pm_stats.resident_count -= count;
1381 PMAP_INLINE pt_entry_t *
1382 vtopte(vm_offset_t va)
1384 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1386 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1388 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1391 static __inline pd_entry_t *
1392 vtopde(vm_offset_t va)
1394 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1396 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1398 return (PDmap + ((va >> PDRSHIFT) & mask));
1402 allocpages(vm_paddr_t *firstaddr, int n)
1407 bzero((void *)ret, n * PAGE_SIZE);
1408 *firstaddr += n * PAGE_SIZE;
1412 CTASSERT(powerof2(NDMPML4E));
1414 /* number of kernel PDP slots */
1415 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1418 nkpt_init(vm_paddr_t addr)
1425 pt_pages = howmany(addr, 1 << PDRSHIFT);
1426 pt_pages += NKPDPE(pt_pages);
1429 * Add some slop beyond the bare minimum required for bootstrapping
1432 * This is quite important when allocating KVA for kernel modules.
1433 * The modules are required to be linked in the negative 2GB of
1434 * the address space. If we run out of KVA in this region then
1435 * pmap_growkernel() will need to allocate page table pages to map
1436 * the entire 512GB of KVA space which is an unnecessary tax on
1439 * Secondly, device memory mapped as part of setting up the low-
1440 * level console(s) is taken from KVA, starting at virtual_avail.
1441 * This is because cninit() is called after pmap_bootstrap() but
1442 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1445 pt_pages += 32; /* 64MB additional slop. */
1451 * Returns the proper write/execute permission for a physical page that is
1452 * part of the initial boot allocations.
1454 * If the page has kernel text, it is marked as read-only. If the page has
1455 * kernel read-only data, it is marked as read-only/not-executable. If the
1456 * page has only read-write data, it is marked as read-write/not-executable.
1457 * If the page is below/above the kernel range, it is marked as read-write.
1459 * This function operates on 2M pages, since we map the kernel space that
1462 static inline pt_entry_t
1463 bootaddr_rwx(vm_paddr_t pa)
1467 * The kernel is loaded at a 2MB-aligned address, and memory below that
1468 * need not be executable. The .bss section is padded to a 2MB
1469 * boundary, so memory following the kernel need not be executable
1470 * either. Preloaded kernel modules have their mapping permissions
1471 * fixed up by the linker.
1473 if (pa < trunc_2mpage(btext - KERNBASE) ||
1474 pa >= trunc_2mpage(_end - KERNBASE))
1475 return (X86_PG_RW | pg_nx);
1478 * The linker should ensure that the read-only and read-write
1479 * portions don't share the same 2M page, so this shouldn't
1480 * impact read-only data. However, in any case, any page with
1481 * read-write data needs to be read-write.
1483 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1484 return (X86_PG_RW | pg_nx);
1487 * Mark any 2M page containing kernel text as read-only. Mark
1488 * other pages with read-only data as read-only and not executable.
1489 * (It is likely a small portion of the read-only data section will
1490 * be marked as read-only, but executable. This should be acceptable
1491 * since the read-only protection will keep the data from changing.)
1492 * Note that fixups to the .text section will still work until we
1495 if (pa < round_2mpage(etext - KERNBASE))
1501 create_pagetables(vm_paddr_t *firstaddr)
1503 int i, j, ndm1g, nkpdpe, nkdmpde;
1507 uint64_t DMPDkernphys;
1509 /* Allocate page table pages for the direct map */
1510 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1511 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1513 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1514 if (ndmpdpphys > NDMPML4E) {
1516 * Each NDMPML4E allows 512 GB, so limit to that,
1517 * and then readjust ndmpdp and ndmpdpphys.
1519 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1520 Maxmem = atop(NDMPML4E * NBPML4);
1521 ndmpdpphys = NDMPML4E;
1522 ndmpdp = NDMPML4E * NPDEPG;
1524 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1526 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1528 * Calculate the number of 1G pages that will fully fit in
1531 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1534 * Allocate 2M pages for the kernel. These will be used in
1535 * place of the first one or more 1G pages from ndm1g.
1537 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1538 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1541 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1542 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1544 /* Allocate pages */
1545 KPML4phys = allocpages(firstaddr, 1);
1546 KPDPphys = allocpages(firstaddr, NKPML4E);
1549 * Allocate the initial number of kernel page table pages required to
1550 * bootstrap. We defer this until after all memory-size dependent
1551 * allocations are done (e.g. direct map), so that we don't have to
1552 * build in too much slop in our estimate.
1554 * Note that when NKPML4E > 1, we have an empty page underneath
1555 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1556 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1558 nkpt_init(*firstaddr);
1559 nkpdpe = NKPDPE(nkpt);
1561 KPTphys = allocpages(firstaddr, nkpt);
1562 KPDphys = allocpages(firstaddr, nkpdpe);
1565 * Connect the zero-filled PT pages to their PD entries. This
1566 * implicitly maps the PT pages at their correct locations within
1569 pd_p = (pd_entry_t *)KPDphys;
1570 for (i = 0; i < nkpt; i++)
1571 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1574 * Map from physical address zero to the end of loader preallocated
1575 * memory using 2MB pages. This replaces some of the PD entries
1578 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1579 /* Preset PG_M and PG_A because demotion expects it. */
1580 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1581 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1584 * Because we map the physical blocks in 2M pages, adjust firstaddr
1585 * to record the physical blocks we've actually mapped into kernel
1586 * virtual address space.
1588 if (*firstaddr < round_2mpage(KERNend))
1589 *firstaddr = round_2mpage(KERNend);
1591 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1592 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1593 for (i = 0; i < nkpdpe; i++)
1594 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1597 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1598 * the end of physical memory is not aligned to a 1GB page boundary,
1599 * then the residual physical memory is mapped with 2MB pages. Later,
1600 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1601 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1602 * that are partially used.
1604 pd_p = (pd_entry_t *)DMPDphys;
1605 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1606 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1607 /* Preset PG_M and PG_A because demotion expects it. */
1608 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1609 X86_PG_M | X86_PG_A | pg_nx;
1611 pdp_p = (pdp_entry_t *)DMPDPphys;
1612 for (i = 0; i < ndm1g; i++) {
1613 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1614 /* Preset PG_M and PG_A because demotion expects it. */
1615 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1616 X86_PG_M | X86_PG_A | pg_nx;
1618 for (j = 0; i < ndmpdp; i++, j++) {
1619 pdp_p[i] = DMPDphys + ptoa(j);
1620 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1624 * Instead of using a 1G page for the memory containing the kernel,
1625 * use 2M pages with read-only and no-execute permissions. (If using 1G
1626 * pages, this will partially overwrite the PDPEs above.)
1629 pd_p = (pd_entry_t *)DMPDkernphys;
1630 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1631 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1632 X86_PG_M | X86_PG_A | pg_nx |
1633 bootaddr_rwx(i << PDRSHIFT);
1634 for (i = 0; i < nkdmpde; i++)
1635 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1639 /* And recursively map PML4 to itself in order to get PTmap */
1640 p4_p = (pml4_entry_t *)KPML4phys;
1641 p4_p[PML4PML4I] = KPML4phys;
1642 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1644 /* Connect the Direct Map slot(s) up to the PML4. */
1645 for (i = 0; i < ndmpdpphys; i++) {
1646 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1647 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1650 /* Connect the KVA slots up to the PML4 */
1651 for (i = 0; i < NKPML4E; i++) {
1652 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1653 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1658 * Bootstrap the system enough to run with virtual memory.
1660 * On amd64 this is called after mapping has already been enabled
1661 * and just syncs the pmap module with what has already been done.
1662 * [We can't call it easily with mapping off since the kernel is not
1663 * mapped with PA == VA, hence we would have to relocate every address
1664 * from the linked base (virtual) address "KERNBASE" to the actual
1665 * (physical) address starting relative to 0]
1668 pmap_bootstrap(vm_paddr_t *firstaddr)
1671 pt_entry_t *pte, *pcpu_pte;
1672 struct region_descriptor r_gdt;
1673 uint64_t cr4, pcpu_phys;
1677 KERNend = *firstaddr;
1678 res = atop(KERNend - (vm_paddr_t)kernphys);
1684 * Create an initial set of page tables to run the kernel in.
1686 create_pagetables(firstaddr);
1688 pcpu_phys = allocpages(firstaddr, MAXCPU);
1691 * Add a physical memory segment (vm_phys_seg) corresponding to the
1692 * preallocated kernel page table pages so that vm_page structures
1693 * representing these pages will be created. The vm_page structures
1694 * are required for promotion of the corresponding kernel virtual
1695 * addresses to superpage mappings.
1697 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1700 * Account for the virtual addresses mapped by create_pagetables().
1702 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1703 virtual_end = VM_MAX_KERNEL_ADDRESS;
1706 * Enable PG_G global pages, then switch to the kernel page
1707 * table from the bootstrap page table. After the switch, it
1708 * is possible to enable SMEP and SMAP since PG_U bits are
1714 load_cr3(KPML4phys);
1715 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1717 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1722 * Initialize the kernel pmap (which is statically allocated).
1723 * Count bootstrap data as being resident in case any of this data is
1724 * later unmapped (using pmap_remove()) and freed.
1726 PMAP_LOCK_INIT(kernel_pmap);
1727 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1728 kernel_pmap->pm_cr3 = KPML4phys;
1729 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1730 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1731 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1732 kernel_pmap->pm_stats.resident_count = res;
1733 kernel_pmap->pm_flags = pmap_flags;
1736 * Initialize the TLB invalidations generation number lock.
1738 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1741 * Reserve some special page table entries/VA space for temporary
1744 #define SYSMAP(c, p, v, n) \
1745 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1751 * Crashdump maps. The first page is reused as CMAP1 for the
1754 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1755 CADDR1 = crashdumpmap;
1757 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1760 for (i = 0; i < MAXCPU; i++) {
1761 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1762 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1766 * Re-initialize PCPU area for BSP after switching.
1767 * Make hardware use gdt and common_tss from the new PCPU.
1769 STAILQ_INIT(&cpuhead);
1770 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1771 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1772 amd64_bsp_pcpu_init1(&__pcpu[0]);
1773 amd64_bsp_ist_init(&__pcpu[0]);
1774 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1776 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1777 sizeof(struct user_segment_descriptor));
1778 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1779 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1780 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1781 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1782 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1784 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1785 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1786 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1787 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1790 * Initialize the PAT MSR.
1791 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1792 * side-effect, invalidates stale PG_G TLB entries that might
1793 * have been created in our pre-boot environment.
1797 /* Initialize TLB Context Id. */
1798 if (pmap_pcid_enabled) {
1799 for (i = 0; i < MAXCPU; i++) {
1800 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1801 kernel_pmap->pm_pcids[i].pm_gen = 1;
1805 * PMAP_PCID_KERN + 1 is used for initialization of
1806 * proc0 pmap. The pmap' pcid state might be used by
1807 * EFIRT entry before first context switch, so it
1808 * needs to be valid.
1810 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1811 PCPU_SET(pcid_gen, 1);
1814 * pcpu area for APs is zeroed during AP startup.
1815 * pc_pcid_next and pc_pcid_gen are initialized by AP
1816 * during pcpu setup.
1818 load_cr4(rcr4() | CR4_PCIDE);
1823 * Setup the PAT MSR.
1832 /* Bail if this CPU doesn't implement PAT. */
1833 if ((cpu_feature & CPUID_PAT) == 0)
1836 /* Set default PAT index table. */
1837 for (i = 0; i < PAT_INDEX_SIZE; i++)
1839 pat_index[PAT_WRITE_BACK] = 0;
1840 pat_index[PAT_WRITE_THROUGH] = 1;
1841 pat_index[PAT_UNCACHEABLE] = 3;
1842 pat_index[PAT_WRITE_COMBINING] = 6;
1843 pat_index[PAT_WRITE_PROTECTED] = 5;
1844 pat_index[PAT_UNCACHED] = 2;
1847 * Initialize default PAT entries.
1848 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1849 * Program 5 and 6 as WP and WC.
1851 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1852 * mapping for a 2M page uses a PAT value with the bit 3 set due
1853 * to its overload with PG_PS.
1855 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1856 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1857 PAT_VALUE(2, PAT_UNCACHED) |
1858 PAT_VALUE(3, PAT_UNCACHEABLE) |
1859 PAT_VALUE(4, PAT_WRITE_BACK) |
1860 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1861 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1862 PAT_VALUE(7, PAT_UNCACHEABLE);
1866 load_cr4(cr4 & ~CR4_PGE);
1868 /* Disable caches (CD = 1, NW = 0). */
1870 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1872 /* Flushes caches and TLBs. */
1876 /* Update PAT and index table. */
1877 wrmsr(MSR_PAT, pat_msr);
1879 /* Flush caches and TLBs again. */
1883 /* Restore caches and PGE. */
1889 * Initialize a vm_page's machine-dependent fields.
1892 pmap_page_init(vm_page_t m)
1895 TAILQ_INIT(&m->md.pv_list);
1896 m->md.pat_mode = PAT_WRITE_BACK;
1899 static int pmap_allow_2m_x_ept;
1900 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1901 &pmap_allow_2m_x_ept, 0,
1902 "Allow executable superpage mappings in EPT");
1905 pmap_allow_2m_x_ept_recalculate(void)
1908 * SKL002, SKL012S. Since the EPT format is only used by
1909 * Intel CPUs, the vendor check is merely a formality.
1911 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1912 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1913 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1914 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1915 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1916 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1917 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1918 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1919 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1920 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1921 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1922 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1923 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1924 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1925 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1926 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1927 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1928 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1929 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1930 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1931 CPUID_TO_MODEL(cpu_id) == 0x85))))
1932 pmap_allow_2m_x_ept = 1;
1933 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1937 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1940 return (pmap->pm_type != PT_EPT || !executable ||
1941 !pmap_allow_2m_x_ept);
1946 pmap_init_pv_table(void)
1948 struct pmap_large_md_page *pvd;
1950 long start, end, highest, pv_npg;
1951 int domain, i, j, pages;
1954 * We strongly depend on the size being a power of two, so the assert
1955 * is overzealous. However, should the struct be resized to a
1956 * different power of two, the code below needs to be revisited.
1958 CTASSERT((sizeof(*pvd) == 64));
1961 * Calculate the size of the array.
1963 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
1964 pv_npg = howmany(pmap_last_pa, NBPDR);
1965 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
1967 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1968 if (pv_table == NULL)
1969 panic("%s: kva_alloc failed\n", __func__);
1972 * Iterate physical segments to allocate space for respective pages.
1976 for (i = 0; i < vm_phys_nsegs; i++) {
1977 end = vm_phys_segs[i].end / NBPDR;
1978 domain = vm_phys_segs[i].domain;
1983 start = highest + 1;
1984 pvd = &pv_table[start];
1986 pages = end - start + 1;
1987 s = round_page(pages * sizeof(*pvd));
1988 highest = start + (s / sizeof(*pvd)) - 1;
1990 for (j = 0; j < s; j += PAGE_SIZE) {
1991 vm_page_t m = vm_page_alloc_domain(NULL, 0,
1992 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
1994 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
1995 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
1998 for (j = 0; j < s / sizeof(*pvd); j++) {
1999 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2000 TAILQ_INIT(&pvd->pv_page.pv_list);
2001 pvd->pv_page.pv_gen = 0;
2002 pvd->pv_page.pat_mode = 0;
2003 pvd->pv_invl_gen = 0;
2007 pvd = &pv_dummy_large;
2008 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2009 TAILQ_INIT(&pvd->pv_page.pv_list);
2010 pvd->pv_page.pv_gen = 0;
2011 pvd->pv_page.pat_mode = 0;
2012 pvd->pv_invl_gen = 0;
2016 pmap_init_pv_table(void)
2022 * Initialize the pool of pv list locks.
2024 for (i = 0; i < NPV_LIST_LOCKS; i++)
2025 rw_init(&pv_list_locks[i], "pmap pv list");
2028 * Calculate the size of the pv head table for superpages.
2030 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2033 * Allocate memory for the pv head table for superpages.
2035 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2037 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2038 for (i = 0; i < pv_npg; i++)
2039 TAILQ_INIT(&pv_table[i].pv_list);
2040 TAILQ_INIT(&pv_dummy.pv_list);
2045 * Initialize the pmap module.
2046 * Called by vm_init, to initialize any structures that the pmap
2047 * system needs to map virtual memory.
2052 struct pmap_preinit_mapping *ppim;
2054 int error, i, ret, skz63;
2056 /* L1TF, reserve page @0 unconditionally */
2057 vm_page_blacklist_add(0, bootverbose);
2059 /* Detect bare-metal Skylake Server and Skylake-X. */
2060 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2061 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2063 * Skylake-X errata SKZ63. Processor May Hang When
2064 * Executing Code In an HLE Transaction Region between
2065 * 40000000H and 403FFFFFH.
2067 * Mark the pages in the range as preallocated. It
2068 * seems to be impossible to distinguish between
2069 * Skylake Server and Skylake X.
2072 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2075 printf("SKZ63: skipping 4M RAM starting "
2076 "at physical 1G\n");
2077 for (i = 0; i < atop(0x400000); i++) {
2078 ret = vm_page_blacklist_add(0x40000000 +
2080 if (!ret && bootverbose)
2081 printf("page at %#lx already used\n",
2082 0x40000000 + ptoa(i));
2088 pmap_allow_2m_x_ept_recalculate();
2091 * Initialize the vm page array entries for the kernel pmap's
2094 PMAP_LOCK(kernel_pmap);
2095 for (i = 0; i < nkpt; i++) {
2096 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2097 KASSERT(mpte >= vm_page_array &&
2098 mpte < &vm_page_array[vm_page_array_size],
2099 ("pmap_init: page table page is out of range"));
2100 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2101 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2102 mpte->ref_count = 1;
2105 * Collect the page table pages that were replaced by a 2MB
2106 * page in create_pagetables(). They are zero filled.
2108 if (i << PDRSHIFT < KERNend &&
2109 pmap_insert_pt_page(kernel_pmap, mpte, false))
2110 panic("pmap_init: pmap_insert_pt_page failed");
2112 PMAP_UNLOCK(kernel_pmap);
2116 * If the kernel is running on a virtual machine, then it must assume
2117 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2118 * be prepared for the hypervisor changing the vendor and family that
2119 * are reported by CPUID. Consequently, the workaround for AMD Family
2120 * 10h Erratum 383 is enabled if the processor's feature set does not
2121 * include at least one feature that is only supported by older Intel
2122 * or newer AMD processors.
2124 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2125 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2126 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2128 workaround_erratum383 = 1;
2131 * Are large page mappings enabled?
2133 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2134 if (pg_ps_enabled) {
2135 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2136 ("pmap_init: can't assign to pagesizes[1]"));
2137 pagesizes[1] = NBPDR;
2141 * Initialize pv chunk lists.
2143 for (i = 0; i < PMAP_MEMDOM; i++) {
2144 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2145 TAILQ_INIT(&pv_chunks[i].pvc_list);
2147 pmap_init_pv_table();
2149 pmap_initialized = 1;
2150 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2151 ppim = pmap_preinit_mapping + i;
2154 /* Make the direct map consistent */
2155 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2156 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2157 ppim->sz, ppim->mode);
2161 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2162 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2165 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2166 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2167 (vmem_addr_t *)&qframe);
2169 panic("qframe allocation failed");
2172 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2173 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2174 lm_ents = LMEPML4I - LMSPML4I + 1;
2176 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2177 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2179 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2180 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2181 if (large_vmem == NULL) {
2182 printf("pmap: cannot create large map\n");
2185 for (i = 0; i < lm_ents; i++) {
2186 m = pmap_large_map_getptp_unlocked();
2187 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
2188 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2194 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2195 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2196 "Maximum number of PML4 entries for use by large map (tunable). "
2197 "Each entry corresponds to 512GB of address space.");
2199 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
2200 "2MB page mapping counters");
2202 static u_long pmap_pde_demotions;
2203 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2204 &pmap_pde_demotions, 0, "2MB page demotions");
2206 static u_long pmap_pde_mappings;
2207 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2208 &pmap_pde_mappings, 0, "2MB page mappings");
2210 static u_long pmap_pde_p_failures;
2211 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2212 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2214 static u_long pmap_pde_promotions;
2215 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2216 &pmap_pde_promotions, 0, "2MB page promotions");
2218 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
2219 "1GB page mapping counters");
2221 static u_long pmap_pdpe_demotions;
2222 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2223 &pmap_pdpe_demotions, 0, "1GB page demotions");
2225 /***************************************************
2226 * Low level helper routines.....
2227 ***************************************************/
2230 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2232 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2234 switch (pmap->pm_type) {
2237 /* Verify that both PAT bits are not set at the same time */
2238 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2239 ("Invalid PAT bits in entry %#lx", entry));
2241 /* Swap the PAT bits if one of them is set */
2242 if ((entry & x86_pat_bits) != 0)
2243 entry ^= x86_pat_bits;
2247 * Nothing to do - the memory attributes are represented
2248 * the same way for regular pages and superpages.
2252 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2259 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2262 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2263 pat_index[(int)mode] >= 0);
2267 * Determine the appropriate bits to set in a PTE or PDE for a specified
2271 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2273 int cache_bits, pat_flag, pat_idx;
2275 if (!pmap_is_valid_memattr(pmap, mode))
2276 panic("Unknown caching mode %d\n", mode);
2278 switch (pmap->pm_type) {
2281 /* The PAT bit is different for PTE's and PDE's. */
2282 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2284 /* Map the caching mode to a PAT index. */
2285 pat_idx = pat_index[mode];
2287 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2290 cache_bits |= pat_flag;
2292 cache_bits |= PG_NC_PCD;
2294 cache_bits |= PG_NC_PWT;
2298 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2302 panic("unsupported pmap type %d", pmap->pm_type);
2305 return (cache_bits);
2309 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2313 switch (pmap->pm_type) {
2316 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2319 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2322 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2329 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2331 int pat_flag, pat_idx;
2334 switch (pmap->pm_type) {
2337 /* The PAT bit is different for PTE's and PDE's. */
2338 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2340 if ((pte & pat_flag) != 0)
2342 if ((pte & PG_NC_PCD) != 0)
2344 if ((pte & PG_NC_PWT) != 0)
2348 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2349 panic("EPT PTE %#lx has no PAT memory type", pte);
2350 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2354 /* See pmap_init_pat(). */
2364 pmap_ps_enabled(pmap_t pmap)
2367 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2371 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2374 switch (pmap->pm_type) {
2381 * This is a little bogus since the generation number is
2382 * supposed to be bumped up when a region of the address
2383 * space is invalidated in the page tables.
2385 * In this case the old PDE entry is valid but yet we want
2386 * to make sure that any mappings using the old entry are
2387 * invalidated in the TLB.
2389 * The reason this works as expected is because we rendezvous
2390 * "all" host cpus and force any vcpu context to exit as a
2393 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2396 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2398 pde_store(pde, newpde);
2402 * After changing the page size for the specified virtual address in the page
2403 * table, flush the corresponding entries from the processor's TLB. Only the
2404 * calling processor's TLB is affected.
2406 * The calling thread must be pinned to a processor.
2409 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2413 if (pmap_type_guest(pmap))
2416 KASSERT(pmap->pm_type == PT_X86,
2417 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2419 PG_G = pmap_global_bit(pmap);
2421 if ((newpde & PG_PS) == 0)
2422 /* Demotion: flush a specific 2MB page mapping. */
2424 else if ((newpde & PG_G) == 0)
2426 * Promotion: flush every 4KB page mapping from the TLB
2427 * because there are too many to flush individually.
2432 * Promotion: flush every 4KB page mapping from the TLB,
2433 * including any global (PG_G) mappings.
2441 * For SMP, these functions have to use the IPI mechanism for coherence.
2443 * N.B.: Before calling any of the following TLB invalidation functions,
2444 * the calling processor must ensure that all stores updating a non-
2445 * kernel page table are globally performed. Otherwise, another
2446 * processor could cache an old, pre-update entry without being
2447 * invalidated. This can happen one of two ways: (1) The pmap becomes
2448 * active on another processor after its pm_active field is checked by
2449 * one of the following functions but before a store updating the page
2450 * table is globally performed. (2) The pmap becomes active on another
2451 * processor before its pm_active field is checked but due to
2452 * speculative loads one of the following functions stills reads the
2453 * pmap as inactive on the other processor.
2455 * The kernel page table is exempt because its pm_active field is
2456 * immutable. The kernel page table is always active on every
2461 * Interrupt the cpus that are executing in the guest context.
2462 * This will force the vcpu to exit and the cached EPT mappings
2463 * will be invalidated by the host before the next vmresume.
2465 static __inline void
2466 pmap_invalidate_ept(pmap_t pmap)
2471 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2472 ("pmap_invalidate_ept: absurd pm_active"));
2475 * The TLB mappings associated with a vcpu context are not
2476 * flushed each time a different vcpu is chosen to execute.
2478 * This is in contrast with a process's vtop mappings that
2479 * are flushed from the TLB on each context switch.
2481 * Therefore we need to do more than just a TLB shootdown on
2482 * the active cpus in 'pmap->pm_active'. To do this we keep
2483 * track of the number of invalidations performed on this pmap.
2485 * Each vcpu keeps a cache of this counter and compares it
2486 * just before a vmresume. If the counter is out-of-date an
2487 * invept will be done to flush stale mappings from the TLB.
2489 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2492 * Force the vcpu to exit and trap back into the hypervisor.
2494 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2495 ipi_selected(pmap->pm_active, ipinum);
2500 pmap_invalidate_cpu_mask(pmap_t pmap)
2503 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2507 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2508 const bool invpcid_works1)
2510 struct invpcid_descr d;
2511 uint64_t kcr3, ucr3;
2515 cpuid = PCPU_GET(cpuid);
2516 if (pmap == PCPU_GET(curpmap)) {
2517 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2519 * Because pm_pcid is recalculated on a
2520 * context switch, we must disable switching.
2521 * Otherwise, we might use a stale value
2525 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2526 if (invpcid_works1) {
2527 d.pcid = pcid | PMAP_PCID_USER_PT;
2530 invpcid(&d, INVPCID_ADDR);
2532 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2533 ucr3 = pmap->pm_ucr3 | pcid |
2534 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2535 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2540 pmap->pm_pcids[cpuid].pm_gen = 0;
2544 pmap->pm_pcids[i].pm_gen = 0;
2548 * The fence is between stores to pm_gen and the read of the
2549 * pm_active mask. We need to ensure that it is impossible
2550 * for us to miss the bit update in pm_active and
2551 * simultaneously observe a non-zero pm_gen in
2552 * pmap_activate_sw(), otherwise TLB update is missed.
2553 * Without the fence, IA32 allows such an outcome. Note that
2554 * pm_active is updated by a locked operation, which provides
2555 * the reciprocal fence.
2557 atomic_thread_fence_seq_cst();
2561 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2564 pmap_invalidate_page_pcid(pmap, va, true);
2568 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2571 pmap_invalidate_page_pcid(pmap, va, false);
2575 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2579 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2582 if (pmap_pcid_enabled)
2583 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2584 pmap_invalidate_page_pcid_noinvpcid);
2585 return (pmap_invalidate_page_nopcid);
2589 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2592 if (pmap_type_guest(pmap)) {
2593 pmap_invalidate_ept(pmap);
2597 KASSERT(pmap->pm_type == PT_X86,
2598 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2601 if (pmap == kernel_pmap) {
2604 if (pmap == PCPU_GET(curpmap))
2606 pmap_invalidate_page_mode(pmap, va);
2608 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2612 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2613 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2616 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2617 const bool invpcid_works1)
2619 struct invpcid_descr d;
2620 uint64_t kcr3, ucr3;
2624 cpuid = PCPU_GET(cpuid);
2625 if (pmap == PCPU_GET(curpmap)) {
2626 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2628 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2629 if (invpcid_works1) {
2630 d.pcid = pcid | PMAP_PCID_USER_PT;
2633 for (; d.addr < eva; d.addr += PAGE_SIZE)
2634 invpcid(&d, INVPCID_ADDR);
2636 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2637 ucr3 = pmap->pm_ucr3 | pcid |
2638 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2639 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2644 pmap->pm_pcids[cpuid].pm_gen = 0;
2648 pmap->pm_pcids[i].pm_gen = 0;
2650 /* See the comment in pmap_invalidate_page_pcid(). */
2651 atomic_thread_fence_seq_cst();
2655 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2659 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2663 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2667 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2671 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2675 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2679 if (pmap_pcid_enabled)
2680 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2681 pmap_invalidate_range_pcid_noinvpcid);
2682 return (pmap_invalidate_range_nopcid);
2686 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2690 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2691 pmap_invalidate_all(pmap);
2695 if (pmap_type_guest(pmap)) {
2696 pmap_invalidate_ept(pmap);
2700 KASSERT(pmap->pm_type == PT_X86,
2701 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2704 if (pmap == kernel_pmap) {
2705 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2708 if (pmap == PCPU_GET(curpmap)) {
2709 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2712 pmap_invalidate_range_mode(pmap, sva, eva);
2714 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2719 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2721 struct invpcid_descr d;
2722 uint64_t kcr3, ucr3;
2726 if (pmap == kernel_pmap) {
2727 if (invpcid_works1) {
2728 bzero(&d, sizeof(d));
2729 invpcid(&d, INVPCID_CTXGLOB);
2734 cpuid = PCPU_GET(cpuid);
2735 if (pmap == PCPU_GET(curpmap)) {
2737 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2738 if (invpcid_works1) {
2742 invpcid(&d, INVPCID_CTX);
2743 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2744 d.pcid |= PMAP_PCID_USER_PT;
2745 invpcid(&d, INVPCID_CTX);
2748 kcr3 = pmap->pm_cr3 | pcid;
2749 ucr3 = pmap->pm_ucr3;
2750 if (ucr3 != PMAP_NO_CR3) {
2751 ucr3 |= pcid | PMAP_PCID_USER_PT;
2752 pmap_pti_pcid_invalidate(ucr3, kcr3);
2759 pmap->pm_pcids[cpuid].pm_gen = 0;
2762 pmap->pm_pcids[i].pm_gen = 0;
2765 /* See the comment in pmap_invalidate_page_pcid(). */
2766 atomic_thread_fence_seq_cst();
2770 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2773 pmap_invalidate_all_pcid(pmap, true);
2777 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2780 pmap_invalidate_all_pcid(pmap, false);
2784 pmap_invalidate_all_nopcid(pmap_t pmap)
2787 if (pmap == kernel_pmap)
2789 else if (pmap == PCPU_GET(curpmap))
2793 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2796 if (pmap_pcid_enabled)
2797 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2798 pmap_invalidate_all_pcid_noinvpcid);
2799 return (pmap_invalidate_all_nopcid);
2803 pmap_invalidate_all(pmap_t pmap)
2806 if (pmap_type_guest(pmap)) {
2807 pmap_invalidate_ept(pmap);
2811 KASSERT(pmap->pm_type == PT_X86,
2812 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2815 pmap_invalidate_all_mode(pmap);
2816 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2821 pmap_invalidate_cache(void)
2831 cpuset_t invalidate; /* processors that invalidate their TLB */
2836 u_int store; /* processor that updates the PDE */
2840 pmap_update_pde_action(void *arg)
2842 struct pde_action *act = arg;
2844 if (act->store == PCPU_GET(cpuid))
2845 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2849 pmap_update_pde_teardown(void *arg)
2851 struct pde_action *act = arg;
2853 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2854 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2858 * Change the page size for the specified virtual address in a way that
2859 * prevents any possibility of the TLB ever having two entries that map the
2860 * same virtual address using different page sizes. This is the recommended
2861 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2862 * machine check exception for a TLB state that is improperly diagnosed as a
2866 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2868 struct pde_action act;
2869 cpuset_t active, other_cpus;
2873 cpuid = PCPU_GET(cpuid);
2874 other_cpus = all_cpus;
2875 CPU_CLR(cpuid, &other_cpus);
2876 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2879 active = pmap->pm_active;
2881 if (CPU_OVERLAP(&active, &other_cpus)) {
2883 act.invalidate = active;
2887 act.newpde = newpde;
2888 CPU_SET(cpuid, &active);
2889 smp_rendezvous_cpus(active,
2890 smp_no_rendezvous_barrier, pmap_update_pde_action,
2891 pmap_update_pde_teardown, &act);
2893 pmap_update_pde_store(pmap, pde, newpde);
2894 if (CPU_ISSET(cpuid, &active))
2895 pmap_update_pde_invalidate(pmap, va, newpde);
2901 * Normal, non-SMP, invalidation functions.
2904 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2906 struct invpcid_descr d;
2907 uint64_t kcr3, ucr3;
2910 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2914 KASSERT(pmap->pm_type == PT_X86,
2915 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2917 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2919 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2920 pmap->pm_ucr3 != PMAP_NO_CR3) {
2922 pcid = pmap->pm_pcids[0].pm_pcid;
2923 if (invpcid_works) {
2924 d.pcid = pcid | PMAP_PCID_USER_PT;
2927 invpcid(&d, INVPCID_ADDR);
2929 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2930 ucr3 = pmap->pm_ucr3 | pcid |
2931 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2932 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2936 } else if (pmap_pcid_enabled)
2937 pmap->pm_pcids[0].pm_gen = 0;
2941 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2943 struct invpcid_descr d;
2945 uint64_t kcr3, ucr3;
2947 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2951 KASSERT(pmap->pm_type == PT_X86,
2952 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2954 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2955 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2957 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2958 pmap->pm_ucr3 != PMAP_NO_CR3) {
2960 if (invpcid_works) {
2961 d.pcid = pmap->pm_pcids[0].pm_pcid |
2965 for (; d.addr < eva; d.addr += PAGE_SIZE)
2966 invpcid(&d, INVPCID_ADDR);
2968 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2969 pm_pcid | CR3_PCID_SAVE;
2970 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2971 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2972 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2976 } else if (pmap_pcid_enabled) {
2977 pmap->pm_pcids[0].pm_gen = 0;
2982 pmap_invalidate_all(pmap_t pmap)
2984 struct invpcid_descr d;
2985 uint64_t kcr3, ucr3;
2987 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2991 KASSERT(pmap->pm_type == PT_X86,
2992 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2994 if (pmap == kernel_pmap) {
2995 if (pmap_pcid_enabled && invpcid_works) {
2996 bzero(&d, sizeof(d));
2997 invpcid(&d, INVPCID_CTXGLOB);
3001 } else if (pmap == PCPU_GET(curpmap)) {
3002 if (pmap_pcid_enabled) {
3004 if (invpcid_works) {
3005 d.pcid = pmap->pm_pcids[0].pm_pcid;
3008 invpcid(&d, INVPCID_CTX);
3009 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3010 d.pcid |= PMAP_PCID_USER_PT;
3011 invpcid(&d, INVPCID_CTX);
3014 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3015 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3016 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3017 0].pm_pcid | PMAP_PCID_USER_PT;
3018 pmap_pti_pcid_invalidate(ucr3, kcr3);
3026 } else if (pmap_pcid_enabled) {
3027 pmap->pm_pcids[0].pm_gen = 0;
3032 pmap_invalidate_cache(void)
3039 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3042 pmap_update_pde_store(pmap, pde, newpde);
3043 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3044 pmap_update_pde_invalidate(pmap, va, newpde);
3046 pmap->pm_pcids[0].pm_gen = 0;
3051 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3055 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3056 * by a promotion that did not invalidate the 512 4KB page mappings
3057 * that might exist in the TLB. Consequently, at this point, the TLB
3058 * may hold both 4KB and 2MB page mappings for the address range [va,
3059 * va + NBPDR). Therefore, the entire range must be invalidated here.
3060 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3061 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3062 * single INVLPG suffices to invalidate the 2MB page mapping from the
3065 if ((pde & PG_PROMOTED) != 0)
3066 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3068 pmap_invalidate_page(pmap, va);
3071 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3072 (vm_offset_t sva, vm_offset_t eva))
3075 if ((cpu_feature & CPUID_SS) != 0)
3076 return (pmap_invalidate_cache_range_selfsnoop);
3077 if ((cpu_feature & CPUID_CLFSH) != 0)
3078 return (pmap_force_invalidate_cache_range);
3079 return (pmap_invalidate_cache_range_all);
3082 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3085 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3088 KASSERT((sva & PAGE_MASK) == 0,
3089 ("pmap_invalidate_cache_range: sva not page-aligned"));
3090 KASSERT((eva & PAGE_MASK) == 0,
3091 ("pmap_invalidate_cache_range: eva not page-aligned"));
3095 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3098 pmap_invalidate_cache_range_check_align(sva, eva);
3102 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3105 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3108 * XXX: Some CPUs fault, hang, or trash the local APIC
3109 * registers if we use CLFLUSH on the local APIC range. The
3110 * local APIC is always uncached, so we don't need to flush
3111 * for that range anyway.
3113 if (pmap_kextract(sva) == lapic_paddr)
3116 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3118 * Do per-cache line flush. Use a locked
3119 * instruction to insure that previous stores are
3120 * included in the write-back. The processor
3121 * propagates flush to other processors in the cache
3124 atomic_thread_fence_seq_cst();
3125 for (; sva < eva; sva += cpu_clflush_line_size)
3127 atomic_thread_fence_seq_cst();
3130 * Writes are ordered by CLFLUSH on Intel CPUs.
3132 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3134 for (; sva < eva; sva += cpu_clflush_line_size)
3136 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3142 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3145 pmap_invalidate_cache_range_check_align(sva, eva);
3146 pmap_invalidate_cache();
3150 * Remove the specified set of pages from the data and instruction caches.
3152 * In contrast to pmap_invalidate_cache_range(), this function does not
3153 * rely on the CPU's self-snoop feature, because it is intended for use
3154 * when moving pages into a different cache domain.
3157 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3159 vm_offset_t daddr, eva;
3163 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3164 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3165 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3166 pmap_invalidate_cache();
3169 atomic_thread_fence_seq_cst();
3170 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3172 for (i = 0; i < count; i++) {
3173 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3174 eva = daddr + PAGE_SIZE;
3175 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3183 atomic_thread_fence_seq_cst();
3184 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3190 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3193 pmap_invalidate_cache_range_check_align(sva, eva);
3195 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3196 pmap_force_invalidate_cache_range(sva, eva);
3200 /* See comment in pmap_force_invalidate_cache_range(). */
3201 if (pmap_kextract(sva) == lapic_paddr)
3204 atomic_thread_fence_seq_cst();
3205 for (; sva < eva; sva += cpu_clflush_line_size)
3207 atomic_thread_fence_seq_cst();
3211 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3215 int error, pte_bits;
3217 KASSERT((spa & PAGE_MASK) == 0,
3218 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3219 KASSERT((epa & PAGE_MASK) == 0,
3220 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3222 if (spa < dmaplimit) {
3223 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3225 if (dmaplimit >= epa)
3230 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3232 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3234 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3235 pte = vtopte(vaddr);
3236 for (; spa < epa; spa += PAGE_SIZE) {
3238 pte_store(pte, spa | pte_bits);
3240 /* XXXKIB atomic inside flush_cache_range are excessive */
3241 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3244 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3248 * Routine: pmap_extract
3250 * Extract the physical page address associated
3251 * with the given map/virtual_address pair.
3254 pmap_extract(pmap_t pmap, vm_offset_t va)
3258 pt_entry_t *pte, PG_V;
3262 PG_V = pmap_valid_bit(pmap);
3264 pdpe = pmap_pdpe(pmap, va);
3265 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3266 if ((*pdpe & PG_PS) != 0)
3267 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3269 pde = pmap_pdpe_to_pde(pdpe, va);
3270 if ((*pde & PG_V) != 0) {
3271 if ((*pde & PG_PS) != 0) {
3272 pa = (*pde & PG_PS_FRAME) |
3275 pte = pmap_pde_to_pte(pde, va);
3276 pa = (*pte & PG_FRAME) |
3287 * Routine: pmap_extract_and_hold
3289 * Atomically extract and hold the physical page
3290 * with the given pmap and virtual address pair
3291 * if that mapping permits the given protection.
3294 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3296 pd_entry_t pde, *pdep;
3297 pt_entry_t pte, PG_RW, PG_V;
3301 PG_RW = pmap_rw_bit(pmap);
3302 PG_V = pmap_valid_bit(pmap);
3305 pdep = pmap_pde(pmap, va);
3306 if (pdep != NULL && (pde = *pdep)) {
3308 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3309 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3312 pte = *pmap_pde_to_pte(pdep, va);
3313 if ((pte & PG_V) != 0 &&
3314 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3315 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3317 if (m != NULL && !vm_page_wire_mapped(m))
3325 pmap_kextract(vm_offset_t va)
3330 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3331 pa = DMAP_TO_PHYS(va);
3332 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3333 pa = pmap_large_map_kextract(va);
3337 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3340 * Beware of a concurrent promotion that changes the
3341 * PDE at this point! For example, vtopte() must not
3342 * be used to access the PTE because it would use the
3343 * new PDE. It is, however, safe to use the old PDE
3344 * because the page table page is preserved by the
3347 pa = *pmap_pde_to_pte(&pde, va);
3348 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3354 /***************************************************
3355 * Low level mapping routines.....
3356 ***************************************************/
3359 * Add a wired page to the kva.
3360 * Note: not SMP coherent.
3363 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3368 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3371 static __inline void
3372 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3378 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3379 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3383 * Remove a page from the kernel pagetables.
3384 * Note: not SMP coherent.
3387 pmap_kremove(vm_offset_t va)
3396 * Used to map a range of physical addresses into kernel
3397 * virtual address space.
3399 * The value passed in '*virt' is a suggested virtual address for
3400 * the mapping. Architectures which can support a direct-mapped
3401 * physical to virtual region can return the appropriate address
3402 * within that region, leaving '*virt' unchanged. Other
3403 * architectures should map the pages starting at '*virt' and
3404 * update '*virt' with the first usable address after the mapped
3408 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3410 return PHYS_TO_DMAP(start);
3415 * Add a list of wired pages to the kva
3416 * this routine is only used for temporary
3417 * kernel mappings that do not need to have
3418 * page modification or references recorded.
3419 * Note that old mappings are simply written
3420 * over. The page *must* be wired.
3421 * Note: SMP coherent. Uses a ranged shootdown IPI.
3424 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3426 pt_entry_t *endpte, oldpte, pa, *pte;
3432 endpte = pte + count;
3433 while (pte < endpte) {
3435 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3436 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3437 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3439 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3443 if (__predict_false((oldpte & X86_PG_V) != 0))
3444 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3449 * This routine tears out page mappings from the
3450 * kernel -- it is meant only for temporary mappings.
3451 * Note: SMP coherent. Uses a ranged shootdown IPI.
3454 pmap_qremove(vm_offset_t sva, int count)
3459 while (count-- > 0) {
3460 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3464 pmap_invalidate_range(kernel_pmap, sva, va);
3467 /***************************************************
3468 * Page table page management routines.....
3469 ***************************************************/
3471 * Schedule the specified unused page table page to be freed. Specifically,
3472 * add the page to the specified list of pages that will be released to the
3473 * physical memory manager after the TLB has been updated.
3475 static __inline void
3476 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3477 boolean_t set_PG_ZERO)
3481 m->flags |= PG_ZERO;
3483 m->flags &= ~PG_ZERO;
3484 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3488 * Inserts the specified page table page into the specified pmap's collection
3489 * of idle page table pages. Each of a pmap's page table pages is responsible
3490 * for mapping a distinct range of virtual addresses. The pmap's collection is
3491 * ordered by this virtual address range.
3493 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3496 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3500 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3501 return (vm_radix_insert(&pmap->pm_root, mpte));
3505 * Removes the page table page mapping the specified virtual address from the
3506 * specified pmap's collection of idle page table pages, and returns it.
3507 * Otherwise, returns NULL if there is no page table page corresponding to the
3508 * specified virtual address.
3510 static __inline vm_page_t
3511 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3514 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3515 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3519 * Decrements a page table page's reference count, which is used to record the
3520 * number of valid page table entries within the page. If the reference count
3521 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3522 * page table page was unmapped and FALSE otherwise.
3524 static inline boolean_t
3525 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3529 if (m->ref_count == 0) {
3530 _pmap_unwire_ptp(pmap, va, m, free);
3537 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3540 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3542 * unmap the page table page
3544 if (m->pindex >= (NUPDE + NUPDPE)) {
3547 pml4 = pmap_pml4e(pmap, va);
3549 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3550 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3553 } else if (m->pindex >= NUPDE) {
3556 pdp = pmap_pdpe(pmap, va);
3561 pd = pmap_pde(pmap, va);
3564 pmap_resident_count_dec(pmap, 1);
3565 if (m->pindex < NUPDE) {
3566 /* We just released a PT, unhold the matching PD */
3569 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3570 pmap_unwire_ptp(pmap, va, pdpg, free);
3572 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3573 /* We just released a PD, unhold the matching PDP */
3576 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3577 pmap_unwire_ptp(pmap, va, pdppg, free);
3581 * Put page on a list so that it is released after
3582 * *ALL* TLB shootdown is done
3584 pmap_add_delayed_free_list(m, free, TRUE);
3588 * After removing a page table entry, this routine is used to
3589 * conditionally free the page, and manage the reference count.
3592 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3593 struct spglist *free)
3597 if (va >= VM_MAXUSER_ADDRESS)
3599 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3600 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3601 return (pmap_unwire_ptp(pmap, va, mpte, free));
3605 pmap_pinit0(pmap_t pmap)
3611 PMAP_LOCK_INIT(pmap);
3612 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3613 pmap->pm_pml4u = NULL;
3614 pmap->pm_cr3 = KPML4phys;
3615 /* hack to keep pmap_pti_pcid_invalidate() alive */
3616 pmap->pm_ucr3 = PMAP_NO_CR3;
3617 pmap->pm_root.rt_root = 0;
3618 CPU_ZERO(&pmap->pm_active);
3619 TAILQ_INIT(&pmap->pm_pvchunk);
3620 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3621 pmap->pm_flags = pmap_flags;
3623 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3624 pmap->pm_pcids[i].pm_gen = 1;
3626 pmap_activate_boot(pmap);
3631 p->p_md.md_flags |= P_MD_KPTI;
3634 pmap_thread_init_invl_gen(td);
3636 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3637 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3638 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3644 pmap_pinit_pml4(vm_page_t pml4pg)
3646 pml4_entry_t *pm_pml4;
3649 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3651 /* Wire in kernel global address entries. */
3652 for (i = 0; i < NKPML4E; i++) {
3653 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3656 for (i = 0; i < ndmpdpphys; i++) {
3657 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3661 /* install self-referential address mapping entry(s) */
3662 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3663 X86_PG_A | X86_PG_M;
3665 /* install large map entries if configured */
3666 for (i = 0; i < lm_ents; i++)
3667 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3671 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3673 pml4_entry_t *pm_pml4;
3676 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3677 for (i = 0; i < NPML4EPG; i++)
3678 pm_pml4[i] = pti_pml4[i];
3682 * Initialize a preallocated and zeroed pmap structure,
3683 * such as one in a vmspace structure.
3686 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3688 vm_page_t pml4pg, pml4pgu;
3689 vm_paddr_t pml4phys;
3693 * allocate the page directory page
3695 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3696 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3698 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3699 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3701 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3702 pmap->pm_pcids[i].pm_gen = 0;
3704 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3705 pmap->pm_ucr3 = PMAP_NO_CR3;
3706 pmap->pm_pml4u = NULL;
3708 pmap->pm_type = pm_type;
3709 if ((pml4pg->flags & PG_ZERO) == 0)
3710 pagezero(pmap->pm_pml4);
3713 * Do not install the host kernel mappings in the nested page
3714 * tables. These mappings are meaningless in the guest physical
3716 * Install minimal kernel mappings in PTI case.
3718 if (pm_type == PT_X86) {
3719 pmap->pm_cr3 = pml4phys;
3720 pmap_pinit_pml4(pml4pg);
3721 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3722 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3723 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3724 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3725 VM_PAGE_TO_PHYS(pml4pgu));
3726 pmap_pinit_pml4_pti(pml4pgu);
3727 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3729 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3730 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3731 pkru_free_range, pmap, M_NOWAIT);
3735 pmap->pm_root.rt_root = 0;
3736 CPU_ZERO(&pmap->pm_active);
3737 TAILQ_INIT(&pmap->pm_pvchunk);
3738 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3739 pmap->pm_flags = flags;
3740 pmap->pm_eptgen = 0;
3746 pmap_pinit(pmap_t pmap)
3749 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3753 * This routine is called if the desired page table page does not exist.
3755 * If page table page allocation fails, this routine may sleep before
3756 * returning NULL. It sleeps only if a lock pointer was given.
3758 * Note: If a page allocation fails at page table level two or three,
3759 * one or two pages may be held during the wait, only to be released
3760 * afterwards. This conservative approach is easily argued to avoid
3764 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3766 vm_page_t m, pdppg, pdpg;
3767 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3769 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3771 PG_A = pmap_accessed_bit(pmap);
3772 PG_M = pmap_modified_bit(pmap);
3773 PG_V = pmap_valid_bit(pmap);
3774 PG_RW = pmap_rw_bit(pmap);
3777 * Allocate a page table page.
3779 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3780 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3781 if (lockp != NULL) {
3782 RELEASE_PV_LIST_LOCK(lockp);
3784 PMAP_ASSERT_NOT_IN_DI();
3790 * Indicate the need to retry. While waiting, the page table
3791 * page may have been allocated.
3795 if ((m->flags & PG_ZERO) == 0)
3799 * Map the pagetable page into the process address space, if
3800 * it isn't already there.
3803 if (ptepindex >= (NUPDE + NUPDPE)) {
3804 pml4_entry_t *pml4, *pml4u;
3805 vm_pindex_t pml4index;
3807 /* Wire up a new PDPE page */
3808 pml4index = ptepindex - (NUPDE + NUPDPE);
3809 pml4 = &pmap->pm_pml4[pml4index];
3810 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3811 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3813 * PTI: Make all user-space mappings in the
3814 * kernel-mode page table no-execute so that
3815 * we detect any programming errors that leave
3816 * the kernel-mode page table active on return
3819 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3822 pml4u = &pmap->pm_pml4u[pml4index];
3823 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3827 } else if (ptepindex >= NUPDE) {
3828 vm_pindex_t pml4index;
3829 vm_pindex_t pdpindex;
3833 /* Wire up a new PDE page */
3834 pdpindex = ptepindex - NUPDE;
3835 pml4index = pdpindex >> NPML4EPGSHIFT;
3837 pml4 = &pmap->pm_pml4[pml4index];
3838 if ((*pml4 & PG_V) == 0) {
3839 /* Have to allocate a new pdp, recurse */
3840 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3842 vm_page_unwire_noq(m);
3843 vm_page_free_zero(m);
3847 /* Add reference to pdp page */
3848 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3851 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3853 /* Now find the pdp page */
3854 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3855 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3858 vm_pindex_t pml4index;
3859 vm_pindex_t pdpindex;
3864 /* Wire up a new PTE page */
3865 pdpindex = ptepindex >> NPDPEPGSHIFT;
3866 pml4index = pdpindex >> NPML4EPGSHIFT;
3868 /* First, find the pdp and check that its valid. */
3869 pml4 = &pmap->pm_pml4[pml4index];
3870 if ((*pml4 & PG_V) == 0) {
3871 /* Have to allocate a new pd, recurse */
3872 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3874 vm_page_unwire_noq(m);
3875 vm_page_free_zero(m);
3878 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3879 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3881 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3882 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3883 if ((*pdp & PG_V) == 0) {
3884 /* Have to allocate a new pd, recurse */
3885 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3887 vm_page_unwire_noq(m);
3888 vm_page_free_zero(m);
3892 /* Add reference to the pd page */
3893 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3897 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3899 /* Now we know where the page directory page is */
3900 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3901 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3904 pmap_resident_count_inc(pmap, 1);
3910 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3912 vm_pindex_t pdpindex, ptepindex;
3913 pdp_entry_t *pdpe, PG_V;
3916 PG_V = pmap_valid_bit(pmap);
3919 pdpe = pmap_pdpe(pmap, va);
3920 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3921 /* Add a reference to the pd page. */
3922 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3925 /* Allocate a pd page. */
3926 ptepindex = pmap_pde_pindex(va);
3927 pdpindex = ptepindex >> NPDPEPGSHIFT;
3928 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3929 if (pdpg == NULL && lockp != NULL)
3936 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3938 vm_pindex_t ptepindex;
3939 pd_entry_t *pd, PG_V;
3942 PG_V = pmap_valid_bit(pmap);
3945 * Calculate pagetable page index
3947 ptepindex = pmap_pde_pindex(va);
3950 * Get the page directory entry
3952 pd = pmap_pde(pmap, va);
3955 * This supports switching from a 2MB page to a
3958 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3959 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3961 * Invalidation of the 2MB page mapping may have caused
3962 * the deallocation of the underlying PD page.
3969 * If the page table page is mapped, we just increment the
3970 * hold count, and activate it.
3972 if (pd != NULL && (*pd & PG_V) != 0) {
3973 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3977 * Here if the pte page isn't mapped, or if it has been
3980 m = _pmap_allocpte(pmap, ptepindex, lockp);
3981 if (m == NULL && lockp != NULL)
3988 /***************************************************
3989 * Pmap allocation/deallocation routines.
3990 ***************************************************/
3993 * Release any resources held by the given physical map.
3994 * Called when a pmap initialized by pmap_pinit is being released.
3995 * Should only be called if the map contains no valid mappings.
3998 pmap_release(pmap_t pmap)
4003 KASSERT(pmap->pm_stats.resident_count == 0,
4004 ("pmap_release: pmap resident count %ld != 0",
4005 pmap->pm_stats.resident_count));
4006 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4007 ("pmap_release: pmap has reserved page table page(s)"));
4008 KASSERT(CPU_EMPTY(&pmap->pm_active),
4009 ("releasing active pmap %p", pmap));
4011 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
4013 for (i = 0; i < NKPML4E; i++) /* KVA */
4014 pmap->pm_pml4[KPML4BASE + i] = 0;
4015 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4016 pmap->pm_pml4[DMPML4I + i] = 0;
4017 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
4018 for (i = 0; i < lm_ents; i++) /* Large Map */
4019 pmap->pm_pml4[LMSPML4I + i] = 0;
4021 vm_page_unwire_noq(m);
4022 vm_page_free_zero(m);
4024 if (pmap->pm_pml4u != NULL) {
4025 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
4026 vm_page_unwire_noq(m);
4029 if (pmap->pm_type == PT_X86 &&
4030 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4031 rangeset_fini(&pmap->pm_pkru);
4035 kvm_size(SYSCTL_HANDLER_ARGS)
4037 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4039 return sysctl_handle_long(oidp, &ksize, 0, req);
4041 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
4042 0, 0, kvm_size, "LU", "Size of KVM");
4045 kvm_free(SYSCTL_HANDLER_ARGS)
4047 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4049 return sysctl_handle_long(oidp, &kfree, 0, req);
4051 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
4052 0, 0, kvm_free, "LU", "Amount of KVM free");
4055 * Allocate physical memory for the vm_page array and map it into KVA,
4056 * attempting to back the vm_pages with domain-local memory.
4059 pmap_page_array_startup(long pages)
4062 pd_entry_t *pde, newpdir;
4063 vm_offset_t va, start, end;
4068 vm_page_array_size = pages;
4070 start = VM_MIN_KERNEL_ADDRESS;
4071 end = start + pages * sizeof(struct vm_page);
4072 for (va = start; va < end; va += NBPDR) {
4073 pfn = first_page + (va - start) / sizeof(struct vm_page);
4074 domain = _vm_phys_domain(ptoa(pfn));
4075 pdpe = pmap_pdpe(kernel_pmap, va);
4076 if ((*pdpe & X86_PG_V) == 0) {
4077 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4079 pagezero((void *)PHYS_TO_DMAP(pa));
4080 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4081 X86_PG_A | X86_PG_M);
4083 pde = pmap_pdpe_to_pde(pdpe, va);
4084 if ((*pde & X86_PG_V) != 0)
4085 panic("Unexpected pde");
4086 pa = vm_phys_early_alloc(domain, NBPDR);
4087 for (i = 0; i < NPDEPG; i++)
4088 dump_add_page(pa + i * PAGE_SIZE);
4089 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4090 X86_PG_M | PG_PS | pg_g | pg_nx);
4091 pde_store(pde, newpdir);
4093 vm_page_array = (vm_page_t)start;
4097 * grow the number of kernel page table entries, if needed
4100 pmap_growkernel(vm_offset_t addr)
4104 pd_entry_t *pde, newpdir;
4107 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4110 * Return if "addr" is within the range of kernel page table pages
4111 * that were preallocated during pmap bootstrap. Moreover, leave
4112 * "kernel_vm_end" and the kernel page table as they were.
4114 * The correctness of this action is based on the following
4115 * argument: vm_map_insert() allocates contiguous ranges of the
4116 * kernel virtual address space. It calls this function if a range
4117 * ends after "kernel_vm_end". If the kernel is mapped between
4118 * "kernel_vm_end" and "addr", then the range cannot begin at
4119 * "kernel_vm_end". In fact, its beginning address cannot be less
4120 * than the kernel. Thus, there is no immediate need to allocate
4121 * any new kernel page table pages between "kernel_vm_end" and
4124 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4127 addr = roundup2(addr, NBPDR);
4128 if (addr - 1 >= vm_map_max(kernel_map))
4129 addr = vm_map_max(kernel_map);
4130 while (kernel_vm_end < addr) {
4131 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4132 if ((*pdpe & X86_PG_V) == 0) {
4133 /* We need a new PDP entry */
4134 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4135 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4136 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4138 panic("pmap_growkernel: no memory to grow kernel");
4139 if ((nkpg->flags & PG_ZERO) == 0)
4140 pmap_zero_page(nkpg);
4141 paddr = VM_PAGE_TO_PHYS(nkpg);
4142 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4143 X86_PG_A | X86_PG_M);
4144 continue; /* try again */
4146 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4147 if ((*pde & X86_PG_V) != 0) {
4148 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4149 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4150 kernel_vm_end = vm_map_max(kernel_map);
4156 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4157 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4160 panic("pmap_growkernel: no memory to grow kernel");
4161 if ((nkpg->flags & PG_ZERO) == 0)
4162 pmap_zero_page(nkpg);
4163 paddr = VM_PAGE_TO_PHYS(nkpg);
4164 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4165 pde_store(pde, newpdir);
4167 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4168 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4169 kernel_vm_end = vm_map_max(kernel_map);
4176 /***************************************************
4177 * page management routines.
4178 ***************************************************/
4180 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4181 CTASSERT(_NPCM == 3);
4182 CTASSERT(_NPCPV == 168);
4184 static __inline struct pv_chunk *
4185 pv_to_chunk(pv_entry_t pv)
4188 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4191 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4193 #define PC_FREE0 0xfffffffffffffffful
4194 #define PC_FREE1 0xfffffffffffffffful
4195 #define PC_FREE2 0x000000fffffffffful
4197 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4200 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4202 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4203 "Current number of pv entry chunks");
4204 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4205 "Current number of pv entry chunks allocated");
4206 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4207 "Current number of pv entry chunks frees");
4208 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4209 "Number of times tried to get a chunk page but failed.");
4211 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4212 static int pv_entry_spare;
4214 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4215 "Current number of pv entry frees");
4216 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4217 "Current number of pv entry allocs");
4218 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4219 "Current number of pv entries");
4220 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4221 "Current number of spare pv entries");
4225 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4230 pmap_invalidate_all(pmap);
4231 if (pmap != locked_pmap)
4234 pmap_delayed_invl_finish();
4238 * We are in a serious low memory condition. Resort to
4239 * drastic measures to free some pages so we can allocate
4240 * another pv entry chunk.
4242 * Returns NULL if PV entries were reclaimed from the specified pmap.
4244 * We do not, however, unmap 2mpages because subsequent accesses will
4245 * allocate per-page pv entries until repromotion occurs, thereby
4246 * exacerbating the shortage of free pv entries.
4249 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4251 struct pv_chunks_list *pvc;
4252 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4253 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4254 struct md_page *pvh;
4256 pmap_t next_pmap, pmap;
4257 pt_entry_t *pte, tpte;
4258 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4262 struct spglist free;
4264 int bit, field, freed;
4267 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4268 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4271 PG_G = PG_A = PG_M = PG_RW = 0;
4273 bzero(&pc_marker_b, sizeof(pc_marker_b));
4274 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4275 pc_marker = (struct pv_chunk *)&pc_marker_b;
4276 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4279 * A delayed invalidation block should already be active if
4280 * pmap_advise() or pmap_remove() called this function by way
4281 * of pmap_demote_pde_locked().
4283 start_di = pmap_not_in_di();
4285 pvc = &pv_chunks[domain];
4286 mtx_lock(&pvc->pvc_lock);
4287 pvc->active_reclaims++;
4288 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4289 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4290 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4291 SLIST_EMPTY(&free)) {
4292 next_pmap = pc->pc_pmap;
4293 if (next_pmap == NULL) {
4295 * The next chunk is a marker. However, it is
4296 * not our marker, so active_reclaims must be
4297 * > 1. Consequently, the next_chunk code
4298 * will not rotate the pv_chunks list.
4302 mtx_unlock(&pvc->pvc_lock);
4305 * A pv_chunk can only be removed from the pc_lru list
4306 * when both pc_chunks_mutex is owned and the
4307 * corresponding pmap is locked.
4309 if (pmap != next_pmap) {
4310 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4313 /* Avoid deadlock and lock recursion. */
4314 if (pmap > locked_pmap) {
4315 RELEASE_PV_LIST_LOCK(lockp);
4318 pmap_delayed_invl_start();
4319 mtx_lock(&pvc->pvc_lock);
4321 } else if (pmap != locked_pmap) {
4322 if (PMAP_TRYLOCK(pmap)) {
4324 pmap_delayed_invl_start();
4325 mtx_lock(&pvc->pvc_lock);
4328 pmap = NULL; /* pmap is not locked */
4329 mtx_lock(&pvc->pvc_lock);
4330 pc = TAILQ_NEXT(pc_marker, pc_lru);
4332 pc->pc_pmap != next_pmap)
4336 } else if (start_di)
4337 pmap_delayed_invl_start();
4338 PG_G = pmap_global_bit(pmap);
4339 PG_A = pmap_accessed_bit(pmap);
4340 PG_M = pmap_modified_bit(pmap);
4341 PG_RW = pmap_rw_bit(pmap);
4345 * Destroy every non-wired, 4 KB page mapping in the chunk.
4348 for (field = 0; field < _NPCM; field++) {
4349 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4350 inuse != 0; inuse &= ~(1UL << bit)) {
4352 pv = &pc->pc_pventry[field * 64 + bit];
4354 pde = pmap_pde(pmap, va);
4355 if ((*pde & PG_PS) != 0)
4357 pte = pmap_pde_to_pte(pde, va);
4358 if ((*pte & PG_W) != 0)
4360 tpte = pte_load_clear(pte);
4361 if ((tpte & PG_G) != 0)
4362 pmap_invalidate_page(pmap, va);
4363 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4364 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4366 if ((tpte & PG_A) != 0)
4367 vm_page_aflag_set(m, PGA_REFERENCED);
4368 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4369 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4371 if (TAILQ_EMPTY(&m->md.pv_list) &&
4372 (m->flags & PG_FICTITIOUS) == 0) {
4373 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4374 if (TAILQ_EMPTY(&pvh->pv_list)) {
4375 vm_page_aflag_clear(m,
4379 pmap_delayed_invl_page(m);
4380 pc->pc_map[field] |= 1UL << bit;
4381 pmap_unuse_pt(pmap, va, *pde, &free);
4386 mtx_lock(&pvc->pvc_lock);
4389 /* Every freed mapping is for a 4 KB page. */
4390 pmap_resident_count_dec(pmap, freed);
4391 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4392 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4393 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4394 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4395 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4396 pc->pc_map[2] == PC_FREE2) {
4397 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4398 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4399 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4400 /* Entire chunk is free; return it. */
4401 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4402 dump_drop_page(m_pc->phys_addr);
4403 mtx_lock(&pvc->pvc_lock);
4404 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4407 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4408 mtx_lock(&pvc->pvc_lock);
4409 /* One freed pv entry in locked_pmap is sufficient. */
4410 if (pmap == locked_pmap)
4413 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4414 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4415 if (pvc->active_reclaims == 1 && pmap != NULL) {
4417 * Rotate the pv chunks list so that we do not
4418 * scan the same pv chunks that could not be
4419 * freed (because they contained a wired
4420 * and/or superpage mapping) on every
4421 * invocation of reclaim_pv_chunk().
4423 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4424 MPASS(pc->pc_pmap != NULL);
4425 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4426 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4430 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4431 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4432 pvc->active_reclaims--;
4433 mtx_unlock(&pvc->pvc_lock);
4434 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4435 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4436 m_pc = SLIST_FIRST(&free);
4437 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4438 /* Recycle a freed page table page. */
4439 m_pc->ref_count = 1;
4441 vm_page_free_pages_toq(&free, true);
4446 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4451 domain = PCPU_GET(domain);
4452 for (i = 0; i < vm_ndomains; i++) {
4453 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4456 domain = (domain + 1) % vm_ndomains;
4463 * free the pv_entry back to the free list
4466 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4468 struct pv_chunk *pc;
4469 int idx, field, bit;
4471 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4472 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4473 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4474 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4475 pc = pv_to_chunk(pv);
4476 idx = pv - &pc->pc_pventry[0];
4479 pc->pc_map[field] |= 1ul << bit;
4480 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4481 pc->pc_map[2] != PC_FREE2) {
4482 /* 98% of the time, pc is already at the head of the list. */
4483 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4484 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4485 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4489 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4494 free_pv_chunk_dequeued(struct pv_chunk *pc)
4498 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4499 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4500 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4501 /* entire chunk is free, return it */
4502 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4503 dump_drop_page(m->phys_addr);
4504 vm_page_unwire_noq(m);
4509 free_pv_chunk(struct pv_chunk *pc)
4511 struct pv_chunks_list *pvc;
4513 pvc = &pv_chunks[pc_to_domain(pc)];
4514 mtx_lock(&pvc->pvc_lock);
4515 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4516 mtx_unlock(&pvc->pvc_lock);
4517 free_pv_chunk_dequeued(pc);
4521 free_pv_chunk_batch(struct pv_chunklist *batch)
4523 struct pv_chunks_list *pvc;
4524 struct pv_chunk *pc, *npc;
4527 for (i = 0; i < vm_ndomains; i++) {
4528 if (TAILQ_EMPTY(&batch[i]))
4530 pvc = &pv_chunks[i];
4531 mtx_lock(&pvc->pvc_lock);
4532 TAILQ_FOREACH(pc, &batch[i], pc_list) {
4533 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4535 mtx_unlock(&pvc->pvc_lock);
4538 for (i = 0; i < vm_ndomains; i++) {
4539 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
4540 free_pv_chunk_dequeued(pc);
4546 * Returns a new PV entry, allocating a new PV chunk from the system when
4547 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4548 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4551 * The given PV list lock may be released.
4554 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4556 struct pv_chunks_list *pvc;
4559 struct pv_chunk *pc;
4562 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4563 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4565 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4567 for (field = 0; field < _NPCM; field++) {
4568 if (pc->pc_map[field]) {
4569 bit = bsfq(pc->pc_map[field]);
4573 if (field < _NPCM) {
4574 pv = &pc->pc_pventry[field * 64 + bit];
4575 pc->pc_map[field] &= ~(1ul << bit);
4576 /* If this was the last item, move it to tail */
4577 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4578 pc->pc_map[2] == 0) {
4579 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4580 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4583 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4584 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4588 /* No free items, allocate another chunk */
4589 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4592 if (lockp == NULL) {
4593 PV_STAT(pc_chunk_tryfail++);
4596 m = reclaim_pv_chunk(pmap, lockp);
4600 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4601 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4602 dump_add_page(m->phys_addr);
4603 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4605 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4606 pc->pc_map[1] = PC_FREE1;
4607 pc->pc_map[2] = PC_FREE2;
4608 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
4609 mtx_lock(&pvc->pvc_lock);
4610 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4611 mtx_unlock(&pvc->pvc_lock);
4612 pv = &pc->pc_pventry[0];
4613 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4614 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4615 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4620 * Returns the number of one bits within the given PV chunk map.
4622 * The erratas for Intel processors state that "POPCNT Instruction May
4623 * Take Longer to Execute Than Expected". It is believed that the
4624 * issue is the spurious dependency on the destination register.
4625 * Provide a hint to the register rename logic that the destination
4626 * value is overwritten, by clearing it, as suggested in the
4627 * optimization manual. It should be cheap for unaffected processors
4630 * Reference numbers for erratas are
4631 * 4th Gen Core: HSD146
4632 * 5th Gen Core: BDM85
4633 * 6th Gen Core: SKL029
4636 popcnt_pc_map_pq(uint64_t *map)
4640 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4641 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4642 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4643 : "=&r" (result), "=&r" (tmp)
4644 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4649 * Ensure that the number of spare PV entries in the specified pmap meets or
4650 * exceeds the given count, "needed".
4652 * The given PV list lock may be released.
4655 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4657 struct pv_chunks_list *pvc;
4658 struct pch new_tail[PMAP_MEMDOM];
4659 struct pv_chunk *pc;
4664 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4665 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4668 * Newly allocated PV chunks must be stored in a private list until
4669 * the required number of PV chunks have been allocated. Otherwise,
4670 * reclaim_pv_chunk() could recycle one of these chunks. In
4671 * contrast, these chunks must be added to the pmap upon allocation.
4673 for (i = 0; i < PMAP_MEMDOM; i++)
4674 TAILQ_INIT(&new_tail[i]);
4677 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4679 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4680 bit_count((bitstr_t *)pc->pc_map, 0,
4681 sizeof(pc->pc_map) * NBBY, &free);
4684 free = popcnt_pc_map_pq(pc->pc_map);
4688 if (avail >= needed)
4691 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4692 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4695 m = reclaim_pv_chunk(pmap, lockp);
4700 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4701 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4702 dump_add_page(m->phys_addr);
4703 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4705 pc->pc_map[0] = PC_FREE0;
4706 pc->pc_map[1] = PC_FREE1;
4707 pc->pc_map[2] = PC_FREE2;
4708 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4709 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
4710 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4713 * The reclaim might have freed a chunk from the current pmap.
4714 * If that chunk contained available entries, we need to
4715 * re-count the number of available entries.
4720 for (i = 0; i < vm_ndomains; i++) {
4721 if (TAILQ_EMPTY(&new_tail[i]))
4723 pvc = &pv_chunks[i];
4724 mtx_lock(&pvc->pvc_lock);
4725 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
4726 mtx_unlock(&pvc->pvc_lock);
4731 * First find and then remove the pv entry for the specified pmap and virtual
4732 * address from the specified pv list. Returns the pv entry if found and NULL
4733 * otherwise. This operation can be performed on pv lists for either 4KB or
4734 * 2MB page mappings.
4736 static __inline pv_entry_t
4737 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4741 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4742 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4743 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4752 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4753 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4754 * entries for each of the 4KB page mappings.
4757 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4758 struct rwlock **lockp)
4760 struct md_page *pvh;
4761 struct pv_chunk *pc;
4763 vm_offset_t va_last;
4767 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4768 KASSERT((pa & PDRMASK) == 0,
4769 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4770 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4773 * Transfer the 2mpage's pv entry for this mapping to the first
4774 * page's pv list. Once this transfer begins, the pv list lock
4775 * must not be released until the last pv entry is reinstantiated.
4777 pvh = pa_to_pvh(pa);
4778 va = trunc_2mpage(va);
4779 pv = pmap_pvh_remove(pvh, pmap, va);
4780 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4781 m = PHYS_TO_VM_PAGE(pa);
4782 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4784 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4785 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4786 va_last = va + NBPDR - PAGE_SIZE;
4788 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4789 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4790 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4791 for (field = 0; field < _NPCM; field++) {
4792 while (pc->pc_map[field]) {
4793 bit = bsfq(pc->pc_map[field]);
4794 pc->pc_map[field] &= ~(1ul << bit);
4795 pv = &pc->pc_pventry[field * 64 + bit];
4799 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4800 ("pmap_pv_demote_pde: page %p is not managed", m));
4801 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4807 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4808 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4811 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4812 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4813 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4815 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4816 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4819 #if VM_NRESERVLEVEL > 0
4821 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4822 * replace the many pv entries for the 4KB page mappings by a single pv entry
4823 * for the 2MB page mapping.
4826 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4827 struct rwlock **lockp)
4829 struct md_page *pvh;
4831 vm_offset_t va_last;
4834 KASSERT((pa & PDRMASK) == 0,
4835 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4836 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4839 * Transfer the first page's pv entry for this mapping to the 2mpage's
4840 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4841 * a transfer avoids the possibility that get_pv_entry() calls
4842 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4843 * mappings that is being promoted.
4845 m = PHYS_TO_VM_PAGE(pa);
4846 va = trunc_2mpage(va);
4847 pv = pmap_pvh_remove(&m->md, pmap, va);
4848 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4849 pvh = pa_to_pvh(pa);
4850 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4852 /* Free the remaining NPTEPG - 1 pv entries. */
4853 va_last = va + NBPDR - PAGE_SIZE;
4857 pmap_pvh_free(&m->md, pmap, va);
4858 } while (va < va_last);
4860 #endif /* VM_NRESERVLEVEL > 0 */
4863 * First find and then destroy the pv entry for the specified pmap and virtual
4864 * address. This operation can be performed on pv lists for either 4KB or 2MB
4868 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4872 pv = pmap_pvh_remove(pvh, pmap, va);
4873 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4874 free_pv_entry(pmap, pv);
4878 * Conditionally create the PV entry for a 4KB page mapping if the required
4879 * memory can be allocated without resorting to reclamation.
4882 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4883 struct rwlock **lockp)
4887 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4888 /* Pass NULL instead of the lock pointer to disable reclamation. */
4889 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4891 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4892 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4900 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4901 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4902 * false if the PV entry cannot be allocated without resorting to reclamation.
4905 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4906 struct rwlock **lockp)
4908 struct md_page *pvh;
4912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4913 /* Pass NULL instead of the lock pointer to disable reclamation. */
4914 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4915 NULL : lockp)) == NULL)
4918 pa = pde & PG_PS_FRAME;
4919 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4920 pvh = pa_to_pvh(pa);
4921 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4927 * Fills a page table page with mappings to consecutive physical pages.
4930 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4934 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4936 newpte += PAGE_SIZE;
4941 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4942 * mapping is invalidated.
4945 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4947 struct rwlock *lock;
4951 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4958 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4962 pt_entry_t *xpte, *ypte;
4964 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4965 xpte++, newpte += PAGE_SIZE) {
4966 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4967 printf("pmap_demote_pde: xpte %zd and newpte map "
4968 "different pages: found %#lx, expected %#lx\n",
4969 xpte - firstpte, *xpte, newpte);
4970 printf("page table dump\n");
4971 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4972 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4977 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4978 ("pmap_demote_pde: firstpte and newpte map different physical"
4985 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4986 pd_entry_t oldpde, struct rwlock **lockp)
4988 struct spglist free;
4992 sva = trunc_2mpage(va);
4993 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4994 if ((oldpde & pmap_global_bit(pmap)) == 0)
4995 pmap_invalidate_pde_page(pmap, sva, oldpde);
4996 vm_page_free_pages_toq(&free, true);
4997 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5002 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5003 struct rwlock **lockp)
5005 pd_entry_t newpde, oldpde;
5006 pt_entry_t *firstpte, newpte;
5007 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5013 PG_A = pmap_accessed_bit(pmap);
5014 PG_G = pmap_global_bit(pmap);
5015 PG_M = pmap_modified_bit(pmap);
5016 PG_RW = pmap_rw_bit(pmap);
5017 PG_V = pmap_valid_bit(pmap);
5018 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5019 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5021 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5022 in_kernel = va >= VM_MAXUSER_ADDRESS;
5024 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5025 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5028 * Invalidate the 2MB page mapping and return "failure" if the
5029 * mapping was never accessed.
5031 if ((oldpde & PG_A) == 0) {
5032 KASSERT((oldpde & PG_W) == 0,
5033 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5034 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5038 mpte = pmap_remove_pt_page(pmap, va);
5040 KASSERT((oldpde & PG_W) == 0,
5041 ("pmap_demote_pde: page table page for a wired mapping"
5045 * If the page table page is missing and the mapping
5046 * is for a kernel address, the mapping must belong to
5047 * the direct map. Page table pages are preallocated
5048 * for every other part of the kernel address space,
5049 * so the direct map region is the only part of the
5050 * kernel address space that must be handled here.
5052 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5053 va < DMAP_MAX_ADDRESS),
5054 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5057 * If the 2MB page mapping belongs to the direct map
5058 * region of the kernel's address space, then the page
5059 * allocation request specifies the highest possible
5060 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5061 * priority is normal.
5063 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5064 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5065 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5068 * If the allocation of the new page table page fails,
5069 * invalidate the 2MB page mapping and return "failure".
5072 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5077 mpte->ref_count = NPTEPG;
5078 pmap_resident_count_inc(pmap, 1);
5081 mptepa = VM_PAGE_TO_PHYS(mpte);
5082 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5083 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5084 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5085 ("pmap_demote_pde: oldpde is missing PG_M"));
5086 newpte = oldpde & ~PG_PS;
5087 newpte = pmap_swap_pat(pmap, newpte);
5090 * If the page table page is not leftover from an earlier promotion,
5093 if (mpte->valid == 0)
5094 pmap_fill_ptp(firstpte, newpte);
5096 pmap_demote_pde_check(firstpte, newpte);
5099 * If the mapping has changed attributes, update the page table
5102 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5103 pmap_fill_ptp(firstpte, newpte);
5106 * The spare PV entries must be reserved prior to demoting the
5107 * mapping, that is, prior to changing the PDE. Otherwise, the state
5108 * of the PDE and the PV lists will be inconsistent, which can result
5109 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5110 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5111 * PV entry for the 2MB page mapping that is being demoted.
5113 if ((oldpde & PG_MANAGED) != 0)
5114 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5117 * Demote the mapping. This pmap is locked. The old PDE has
5118 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5119 * set. Thus, there is no danger of a race with another
5120 * processor changing the setting of PG_A and/or PG_M between
5121 * the read above and the store below.
5123 if (workaround_erratum383)
5124 pmap_update_pde(pmap, va, pde, newpde);
5126 pde_store(pde, newpde);
5129 * Invalidate a stale recursive mapping of the page table page.
5132 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5135 * Demote the PV entry.
5137 if ((oldpde & PG_MANAGED) != 0)
5138 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5140 atomic_add_long(&pmap_pde_demotions, 1);
5141 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5147 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5150 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5156 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5157 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5158 mpte = pmap_remove_pt_page(pmap, va);
5160 panic("pmap_remove_kernel_pde: Missing pt page.");
5162 mptepa = VM_PAGE_TO_PHYS(mpte);
5163 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5166 * If this page table page was unmapped by a promotion, then it
5167 * contains valid mappings. Zero it to invalidate those mappings.
5169 if (mpte->valid != 0)
5170 pagezero((void *)PHYS_TO_DMAP(mptepa));
5173 * Demote the mapping.
5175 if (workaround_erratum383)
5176 pmap_update_pde(pmap, va, pde, newpde);
5178 pde_store(pde, newpde);
5181 * Invalidate a stale recursive mapping of the page table page.
5183 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5187 * pmap_remove_pde: do the things to unmap a superpage in a process
5190 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5191 struct spglist *free, struct rwlock **lockp)
5193 struct md_page *pvh;
5195 vm_offset_t eva, va;
5197 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5199 PG_G = pmap_global_bit(pmap);
5200 PG_A = pmap_accessed_bit(pmap);
5201 PG_M = pmap_modified_bit(pmap);
5202 PG_RW = pmap_rw_bit(pmap);
5204 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5205 KASSERT((sva & PDRMASK) == 0,
5206 ("pmap_remove_pde: sva is not 2mpage aligned"));
5207 oldpde = pte_load_clear(pdq);
5209 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5210 if ((oldpde & PG_G) != 0)
5211 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5212 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5213 if (oldpde & PG_MANAGED) {
5214 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5215 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5216 pmap_pvh_free(pvh, pmap, sva);
5218 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5219 va < eva; va += PAGE_SIZE, m++) {
5220 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5223 vm_page_aflag_set(m, PGA_REFERENCED);
5224 if (TAILQ_EMPTY(&m->md.pv_list) &&
5225 TAILQ_EMPTY(&pvh->pv_list))
5226 vm_page_aflag_clear(m, PGA_WRITEABLE);
5227 pmap_delayed_invl_page(m);
5230 if (pmap == kernel_pmap) {
5231 pmap_remove_kernel_pde(pmap, pdq, sva);
5233 mpte = pmap_remove_pt_page(pmap, sva);
5235 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5236 ("pmap_remove_pde: pte page not promoted"));
5237 pmap_resident_count_dec(pmap, 1);
5238 KASSERT(mpte->ref_count == NPTEPG,
5239 ("pmap_remove_pde: pte page ref count error"));
5240 mpte->ref_count = 0;
5241 pmap_add_delayed_free_list(mpte, free, FALSE);
5244 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5248 * pmap_remove_pte: do the things to unmap a page in a process
5251 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5252 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5254 struct md_page *pvh;
5255 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5258 PG_A = pmap_accessed_bit(pmap);
5259 PG_M = pmap_modified_bit(pmap);
5260 PG_RW = pmap_rw_bit(pmap);
5262 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5263 oldpte = pte_load_clear(ptq);
5265 pmap->pm_stats.wired_count -= 1;
5266 pmap_resident_count_dec(pmap, 1);
5267 if (oldpte & PG_MANAGED) {
5268 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5269 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5272 vm_page_aflag_set(m, PGA_REFERENCED);
5273 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5274 pmap_pvh_free(&m->md, pmap, va);
5275 if (TAILQ_EMPTY(&m->md.pv_list) &&
5276 (m->flags & PG_FICTITIOUS) == 0) {
5277 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5278 if (TAILQ_EMPTY(&pvh->pv_list))
5279 vm_page_aflag_clear(m, PGA_WRITEABLE);
5281 pmap_delayed_invl_page(m);
5283 return (pmap_unuse_pt(pmap, va, ptepde, free));
5287 * Remove a single page from a process address space
5290 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5291 struct spglist *free)
5293 struct rwlock *lock;
5294 pt_entry_t *pte, PG_V;
5296 PG_V = pmap_valid_bit(pmap);
5297 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5298 if ((*pde & PG_V) == 0)
5300 pte = pmap_pde_to_pte(pde, va);
5301 if ((*pte & PG_V) == 0)
5304 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5307 pmap_invalidate_page(pmap, va);
5311 * Removes the specified range of addresses from the page table page.
5314 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5315 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5317 pt_entry_t PG_G, *pte;
5321 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5322 PG_G = pmap_global_bit(pmap);
5325 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5329 pmap_invalidate_range(pmap, va, sva);
5334 if ((*pte & PG_G) == 0)
5338 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5344 pmap_invalidate_range(pmap, va, sva);
5349 * Remove the given range of addresses from the specified map.
5351 * It is assumed that the start and end are properly
5352 * rounded to the page size.
5355 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5357 struct rwlock *lock;
5358 vm_offset_t va_next;
5359 pml4_entry_t *pml4e;
5361 pd_entry_t ptpaddr, *pde;
5362 pt_entry_t PG_G, PG_V;
5363 struct spglist free;
5366 PG_G = pmap_global_bit(pmap);
5367 PG_V = pmap_valid_bit(pmap);
5370 * Perform an unsynchronized read. This is, however, safe.
5372 if (pmap->pm_stats.resident_count == 0)
5378 pmap_delayed_invl_start();
5380 pmap_pkru_on_remove(pmap, sva, eva);
5383 * special handling of removing one page. a very
5384 * common operation and easy to short circuit some
5387 if (sva + PAGE_SIZE == eva) {
5388 pde = pmap_pde(pmap, sva);
5389 if (pde && (*pde & PG_PS) == 0) {
5390 pmap_remove_page(pmap, sva, pde, &free);
5396 for (; sva < eva; sva = va_next) {
5398 if (pmap->pm_stats.resident_count == 0)
5401 pml4e = pmap_pml4e(pmap, sva);
5402 if ((*pml4e & PG_V) == 0) {
5403 va_next = (sva + NBPML4) & ~PML4MASK;
5409 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5410 if ((*pdpe & PG_V) == 0) {
5411 va_next = (sva + NBPDP) & ~PDPMASK;
5418 * Calculate index for next page table.
5420 va_next = (sva + NBPDR) & ~PDRMASK;
5424 pde = pmap_pdpe_to_pde(pdpe, sva);
5428 * Weed out invalid mappings.
5434 * Check for large page.
5436 if ((ptpaddr & PG_PS) != 0) {
5438 * Are we removing the entire large page? If not,
5439 * demote the mapping and fall through.
5441 if (sva + NBPDR == va_next && eva >= va_next) {
5443 * The TLB entry for a PG_G mapping is
5444 * invalidated by pmap_remove_pde().
5446 if ((ptpaddr & PG_G) == 0)
5448 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5450 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5452 /* The large page mapping was destroyed. */
5459 * Limit our scan to either the end of the va represented
5460 * by the current page table page, or to the end of the
5461 * range being removed.
5466 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5473 pmap_invalidate_all(pmap);
5475 pmap_delayed_invl_finish();
5476 vm_page_free_pages_toq(&free, true);
5480 * Routine: pmap_remove_all
5482 * Removes this physical page from
5483 * all physical maps in which it resides.
5484 * Reflects back modify bits to the pager.
5487 * Original versions of this routine were very
5488 * inefficient because they iteratively called
5489 * pmap_remove (slow...)
5493 pmap_remove_all(vm_page_t m)
5495 struct md_page *pvh;
5498 struct rwlock *lock;
5499 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5502 struct spglist free;
5503 int pvh_gen, md_gen;
5505 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5506 ("pmap_remove_all: page %p is not managed", m));
5508 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5509 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5510 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5513 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5515 if (!PMAP_TRYLOCK(pmap)) {
5516 pvh_gen = pvh->pv_gen;
5520 if (pvh_gen != pvh->pv_gen) {
5527 pde = pmap_pde(pmap, va);
5528 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5531 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5533 if (!PMAP_TRYLOCK(pmap)) {
5534 pvh_gen = pvh->pv_gen;
5535 md_gen = m->md.pv_gen;
5539 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5545 PG_A = pmap_accessed_bit(pmap);
5546 PG_M = pmap_modified_bit(pmap);
5547 PG_RW = pmap_rw_bit(pmap);
5548 pmap_resident_count_dec(pmap, 1);
5549 pde = pmap_pde(pmap, pv->pv_va);
5550 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5551 " a 2mpage in page %p's pv list", m));
5552 pte = pmap_pde_to_pte(pde, pv->pv_va);
5553 tpte = pte_load_clear(pte);
5555 pmap->pm_stats.wired_count--;
5557 vm_page_aflag_set(m, PGA_REFERENCED);
5560 * Update the vm_page_t clean and reference bits.
5562 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5564 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5565 pmap_invalidate_page(pmap, pv->pv_va);
5566 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5568 free_pv_entry(pmap, pv);
5571 vm_page_aflag_clear(m, PGA_WRITEABLE);
5573 pmap_delayed_invl_wait(m);
5574 vm_page_free_pages_toq(&free, true);
5578 * pmap_protect_pde: do the things to protect a 2mpage in a process
5581 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5583 pd_entry_t newpde, oldpde;
5585 boolean_t anychanged;
5586 pt_entry_t PG_G, PG_M, PG_RW;
5588 PG_G = pmap_global_bit(pmap);
5589 PG_M = pmap_modified_bit(pmap);
5590 PG_RW = pmap_rw_bit(pmap);
5592 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5593 KASSERT((sva & PDRMASK) == 0,
5594 ("pmap_protect_pde: sva is not 2mpage aligned"));
5597 oldpde = newpde = *pde;
5598 if ((prot & VM_PROT_WRITE) == 0) {
5599 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5600 (PG_MANAGED | PG_M | PG_RW)) {
5601 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5602 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5605 newpde &= ~(PG_RW | PG_M);
5607 if ((prot & VM_PROT_EXECUTE) == 0)
5609 if (newpde != oldpde) {
5611 * As an optimization to future operations on this PDE, clear
5612 * PG_PROMOTED. The impending invalidation will remove any
5613 * lingering 4KB page mappings from the TLB.
5615 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5617 if ((oldpde & PG_G) != 0)
5618 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5622 return (anychanged);
5626 * Set the physical protection on the
5627 * specified range of this map as requested.
5630 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5632 vm_offset_t va_next;
5633 pml4_entry_t *pml4e;
5635 pd_entry_t ptpaddr, *pde;
5636 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5637 boolean_t anychanged;
5639 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5640 if (prot == VM_PROT_NONE) {
5641 pmap_remove(pmap, sva, eva);
5645 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5646 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5649 PG_G = pmap_global_bit(pmap);
5650 PG_M = pmap_modified_bit(pmap);
5651 PG_V = pmap_valid_bit(pmap);
5652 PG_RW = pmap_rw_bit(pmap);
5656 * Although this function delays and batches the invalidation
5657 * of stale TLB entries, it does not need to call
5658 * pmap_delayed_invl_start() and
5659 * pmap_delayed_invl_finish(), because it does not
5660 * ordinarily destroy mappings. Stale TLB entries from
5661 * protection-only changes need only be invalidated before the
5662 * pmap lock is released, because protection-only changes do
5663 * not destroy PV entries. Even operations that iterate over
5664 * a physical page's PV list of mappings, like
5665 * pmap_remove_write(), acquire the pmap lock for each
5666 * mapping. Consequently, for protection-only changes, the
5667 * pmap lock suffices to synchronize both page table and TLB
5670 * This function only destroys a mapping if pmap_demote_pde()
5671 * fails. In that case, stale TLB entries are immediately
5676 for (; sva < eva; sva = va_next) {
5678 pml4e = pmap_pml4e(pmap, sva);
5679 if ((*pml4e & PG_V) == 0) {
5680 va_next = (sva + NBPML4) & ~PML4MASK;
5686 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5687 if ((*pdpe & PG_V) == 0) {
5688 va_next = (sva + NBPDP) & ~PDPMASK;
5694 va_next = (sva + NBPDR) & ~PDRMASK;
5698 pde = pmap_pdpe_to_pde(pdpe, sva);
5702 * Weed out invalid mappings.
5708 * Check for large page.
5710 if ((ptpaddr & PG_PS) != 0) {
5712 * Are we protecting the entire large page? If not,
5713 * demote the mapping and fall through.
5715 if (sva + NBPDR == va_next && eva >= va_next) {
5717 * The TLB entry for a PG_G mapping is
5718 * invalidated by pmap_protect_pde().
5720 if (pmap_protect_pde(pmap, pde, sva, prot))
5723 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5725 * The large page mapping was destroyed.
5734 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5736 pt_entry_t obits, pbits;
5740 obits = pbits = *pte;
5741 if ((pbits & PG_V) == 0)
5744 if ((prot & VM_PROT_WRITE) == 0) {
5745 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5746 (PG_MANAGED | PG_M | PG_RW)) {
5747 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5750 pbits &= ~(PG_RW | PG_M);
5752 if ((prot & VM_PROT_EXECUTE) == 0)
5755 if (pbits != obits) {
5756 if (!atomic_cmpset_long(pte, obits, pbits))
5759 pmap_invalidate_page(pmap, sva);
5766 pmap_invalidate_all(pmap);
5770 #if VM_NRESERVLEVEL > 0
5772 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5775 if (pmap->pm_type != PT_EPT)
5777 return ((pde & EPT_PG_EXECUTE) != 0);
5781 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5782 * single page table page (PTP) to a single 2MB page mapping. For promotion
5783 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5784 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5785 * identical characteristics.
5788 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5789 struct rwlock **lockp)
5792 pt_entry_t *firstpte, oldpte, pa, *pte;
5793 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5797 PG_A = pmap_accessed_bit(pmap);
5798 PG_G = pmap_global_bit(pmap);
5799 PG_M = pmap_modified_bit(pmap);
5800 PG_V = pmap_valid_bit(pmap);
5801 PG_RW = pmap_rw_bit(pmap);
5802 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5803 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5805 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5808 * Examine the first PTE in the specified PTP. Abort if this PTE is
5809 * either invalid, unused, or does not map the first 4KB physical page
5810 * within a 2MB page.
5812 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5815 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5816 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5818 atomic_add_long(&pmap_pde_p_failures, 1);
5819 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5820 " in pmap %p", va, pmap);
5823 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5825 * When PG_M is already clear, PG_RW can be cleared without
5826 * a TLB invalidation.
5828 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5834 * Examine each of the other PTEs in the specified PTP. Abort if this
5835 * PTE maps an unexpected 4KB physical page or does not have identical
5836 * characteristics to the first PTE.
5838 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5839 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5842 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5843 atomic_add_long(&pmap_pde_p_failures, 1);
5844 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5845 " in pmap %p", va, pmap);
5848 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5850 * When PG_M is already clear, PG_RW can be cleared
5851 * without a TLB invalidation.
5853 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5856 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5857 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5858 (va & ~PDRMASK), pmap);
5860 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5861 atomic_add_long(&pmap_pde_p_failures, 1);
5862 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5863 " in pmap %p", va, pmap);
5870 * Save the page table page in its current state until the PDE
5871 * mapping the superpage is demoted by pmap_demote_pde() or
5872 * destroyed by pmap_remove_pde().
5874 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5875 KASSERT(mpte >= vm_page_array &&
5876 mpte < &vm_page_array[vm_page_array_size],
5877 ("pmap_promote_pde: page table page is out of range"));
5878 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5879 ("pmap_promote_pde: page table page's pindex is wrong"));
5880 if (pmap_insert_pt_page(pmap, mpte, true)) {
5881 atomic_add_long(&pmap_pde_p_failures, 1);
5883 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5889 * Promote the pv entries.
5891 if ((newpde & PG_MANAGED) != 0)
5892 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5895 * Propagate the PAT index to its proper position.
5897 newpde = pmap_swap_pat(pmap, newpde);
5900 * Map the superpage.
5902 if (workaround_erratum383)
5903 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5905 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5907 atomic_add_long(&pmap_pde_promotions, 1);
5908 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5909 " in pmap %p", va, pmap);
5911 #endif /* VM_NRESERVLEVEL > 0 */
5914 * Insert the given physical page (p) at
5915 * the specified virtual address (v) in the
5916 * target physical map with the protection requested.
5918 * If specified, the page will be wired down, meaning
5919 * that the related pte can not be reclaimed.
5921 * NB: This is the only routine which MAY NOT lazy-evaluate
5922 * or lose information. That is, this routine must actually
5923 * insert this page into the given map NOW.
5925 * When destroying both a page table and PV entry, this function
5926 * performs the TLB invalidation before releasing the PV list
5927 * lock, so we do not need pmap_delayed_invl_page() calls here.
5930 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5931 u_int flags, int8_t psind)
5933 struct rwlock *lock;
5935 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5936 pt_entry_t newpte, origpte;
5943 PG_A = pmap_accessed_bit(pmap);
5944 PG_G = pmap_global_bit(pmap);
5945 PG_M = pmap_modified_bit(pmap);
5946 PG_V = pmap_valid_bit(pmap);
5947 PG_RW = pmap_rw_bit(pmap);
5949 va = trunc_page(va);
5950 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5951 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5952 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5954 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5955 va >= kmi.clean_eva,
5956 ("pmap_enter: managed mapping within the clean submap"));
5957 if ((m->oflags & VPO_UNMANAGED) == 0)
5958 VM_PAGE_OBJECT_BUSY_ASSERT(m);
5959 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5960 ("pmap_enter: flags %u has reserved bits set", flags));
5961 pa = VM_PAGE_TO_PHYS(m);
5962 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5963 if ((flags & VM_PROT_WRITE) != 0)
5965 if ((prot & VM_PROT_WRITE) != 0)
5967 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5968 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5969 if ((prot & VM_PROT_EXECUTE) == 0)
5971 if ((flags & PMAP_ENTER_WIRED) != 0)
5973 if (va < VM_MAXUSER_ADDRESS)
5975 if (pmap == kernel_pmap)
5977 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5980 * Set modified bit gratuitously for writeable mappings if
5981 * the page is unmanaged. We do not want to take a fault
5982 * to do the dirty bit accounting for these mappings.
5984 if ((m->oflags & VPO_UNMANAGED) != 0) {
5985 if ((newpte & PG_RW) != 0)
5988 newpte |= PG_MANAGED;
5993 /* Assert the required virtual and physical alignment. */
5994 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5995 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5996 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6002 * In the case that a page table page is not
6003 * resident, we are creating it here.
6006 pde = pmap_pde(pmap, va);
6007 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6008 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6009 pte = pmap_pde_to_pte(pde, va);
6010 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6011 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6014 } else if (va < VM_MAXUSER_ADDRESS) {
6016 * Here if the pte page isn't mapped, or if it has been
6019 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6020 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6021 nosleep ? NULL : &lock);
6022 if (mpte == NULL && nosleep) {
6023 rv = KERN_RESOURCE_SHORTAGE;
6028 panic("pmap_enter: invalid page directory va=%#lx", va);
6032 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6033 newpte |= pmap_pkru_get(pmap, va);
6036 * Is the specified virtual address already mapped?
6038 if ((origpte & PG_V) != 0) {
6040 * Wiring change, just update stats. We don't worry about
6041 * wiring PT pages as they remain resident as long as there
6042 * are valid mappings in them. Hence, if a user page is wired,
6043 * the PT page will be also.
6045 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6046 pmap->pm_stats.wired_count++;
6047 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6048 pmap->pm_stats.wired_count--;
6051 * Remove the extra PT page reference.
6055 KASSERT(mpte->ref_count > 0,
6056 ("pmap_enter: missing reference to page table page,"
6061 * Has the physical page changed?
6063 opa = origpte & PG_FRAME;
6066 * No, might be a protection or wiring change.
6068 if ((origpte & PG_MANAGED) != 0 &&
6069 (newpte & PG_RW) != 0)
6070 vm_page_aflag_set(m, PGA_WRITEABLE);
6071 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6077 * The physical page has changed. Temporarily invalidate
6078 * the mapping. This ensures that all threads sharing the
6079 * pmap keep a consistent view of the mapping, which is
6080 * necessary for the correct handling of COW faults. It
6081 * also permits reuse of the old mapping's PV entry,
6082 * avoiding an allocation.
6084 * For consistency, handle unmanaged mappings the same way.
6086 origpte = pte_load_clear(pte);
6087 KASSERT((origpte & PG_FRAME) == opa,
6088 ("pmap_enter: unexpected pa update for %#lx", va));
6089 if ((origpte & PG_MANAGED) != 0) {
6090 om = PHYS_TO_VM_PAGE(opa);
6093 * The pmap lock is sufficient to synchronize with
6094 * concurrent calls to pmap_page_test_mappings() and
6095 * pmap_ts_referenced().
6097 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6099 if ((origpte & PG_A) != 0)
6100 vm_page_aflag_set(om, PGA_REFERENCED);
6101 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6102 pv = pmap_pvh_remove(&om->md, pmap, va);
6104 ("pmap_enter: no PV entry for %#lx", va));
6105 if ((newpte & PG_MANAGED) == 0)
6106 free_pv_entry(pmap, pv);
6107 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6108 TAILQ_EMPTY(&om->md.pv_list) &&
6109 ((om->flags & PG_FICTITIOUS) != 0 ||
6110 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6111 vm_page_aflag_clear(om, PGA_WRITEABLE);
6113 if ((origpte & PG_A) != 0)
6114 pmap_invalidate_page(pmap, va);
6118 * Increment the counters.
6120 if ((newpte & PG_W) != 0)
6121 pmap->pm_stats.wired_count++;
6122 pmap_resident_count_inc(pmap, 1);
6126 * Enter on the PV list if part of our managed memory.
6128 if ((newpte & PG_MANAGED) != 0) {
6130 pv = get_pv_entry(pmap, &lock);
6133 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6134 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6136 if ((newpte & PG_RW) != 0)
6137 vm_page_aflag_set(m, PGA_WRITEABLE);
6143 if ((origpte & PG_V) != 0) {
6145 origpte = pte_load_store(pte, newpte);
6146 KASSERT((origpte & PG_FRAME) == pa,
6147 ("pmap_enter: unexpected pa update for %#lx", va));
6148 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6150 if ((origpte & PG_MANAGED) != 0)
6154 * Although the PTE may still have PG_RW set, TLB
6155 * invalidation may nonetheless be required because
6156 * the PTE no longer has PG_M set.
6158 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6160 * This PTE change does not require TLB invalidation.
6164 if ((origpte & PG_A) != 0)
6165 pmap_invalidate_page(pmap, va);
6167 pte_store(pte, newpte);
6171 #if VM_NRESERVLEVEL > 0
6173 * If both the page table page and the reservation are fully
6174 * populated, then attempt promotion.
6176 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6177 pmap_ps_enabled(pmap) &&
6178 (m->flags & PG_FICTITIOUS) == 0 &&
6179 vm_reserv_level_iffullpop(m) == 0)
6180 pmap_promote_pde(pmap, pde, va, &lock);
6192 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6193 * if successful. Returns false if (1) a page table page cannot be allocated
6194 * without sleeping, (2) a mapping already exists at the specified virtual
6195 * address, or (3) a PV entry cannot be allocated without reclaiming another
6199 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6200 struct rwlock **lockp)
6205 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6206 PG_V = pmap_valid_bit(pmap);
6207 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6209 if ((m->oflags & VPO_UNMANAGED) == 0)
6210 newpde |= PG_MANAGED;
6211 if ((prot & VM_PROT_EXECUTE) == 0)
6213 if (va < VM_MAXUSER_ADDRESS)
6215 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6216 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6221 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6222 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6223 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6224 * a mapping already exists at the specified virtual address. Returns
6225 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6226 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6227 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6229 * The parameter "m" is only used when creating a managed, writeable mapping.
6232 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6233 vm_page_t m, struct rwlock **lockp)
6235 struct spglist free;
6236 pd_entry_t oldpde, *pde;
6237 pt_entry_t PG_G, PG_RW, PG_V;
6240 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6241 ("pmap_enter_pde: cannot create wired user mapping"));
6242 PG_G = pmap_global_bit(pmap);
6243 PG_RW = pmap_rw_bit(pmap);
6244 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6245 ("pmap_enter_pde: newpde is missing PG_M"));
6246 PG_V = pmap_valid_bit(pmap);
6247 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6249 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6251 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6252 " in pmap %p", va, pmap);
6253 return (KERN_FAILURE);
6255 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
6256 NULL : lockp)) == NULL) {
6257 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6258 " in pmap %p", va, pmap);
6259 return (KERN_RESOURCE_SHORTAGE);
6263 * If pkru is not same for the whole pde range, return failure
6264 * and let vm_fault() cope. Check after pde allocation, since
6267 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6269 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6270 pmap_invalidate_page(pmap, va);
6271 vm_page_free_pages_toq(&free, true);
6273 return (KERN_FAILURE);
6275 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6276 newpde &= ~X86_PG_PKU_MASK;
6277 newpde |= pmap_pkru_get(pmap, va);
6280 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6281 pde = &pde[pmap_pde_index(va)];
6283 if ((oldpde & PG_V) != 0) {
6284 KASSERT(pdpg->ref_count > 1,
6285 ("pmap_enter_pde: pdpg's reference count is too low"));
6286 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
6288 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6289 " in pmap %p", va, pmap);
6290 return (KERN_FAILURE);
6292 /* Break the existing mapping(s). */
6294 if ((oldpde & PG_PS) != 0) {
6296 * The reference to the PD page that was acquired by
6297 * pmap_allocpde() ensures that it won't be freed.
6298 * However, if the PDE resulted from a promotion, then
6299 * a reserved PT page could be freed.
6301 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6302 if ((oldpde & PG_G) == 0)
6303 pmap_invalidate_pde_page(pmap, va, oldpde);
6305 pmap_delayed_invl_start();
6306 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6308 pmap_invalidate_all(pmap);
6309 pmap_delayed_invl_finish();
6311 vm_page_free_pages_toq(&free, true);
6312 if (va >= VM_MAXUSER_ADDRESS) {
6314 * Both pmap_remove_pde() and pmap_remove_ptes() will
6315 * leave the kernel page table page zero filled.
6317 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6318 if (pmap_insert_pt_page(pmap, mt, false))
6319 panic("pmap_enter_pde: trie insert failed");
6321 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6324 if ((newpde & PG_MANAGED) != 0) {
6326 * Abort this mapping if its PV entry could not be created.
6328 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6330 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6332 * Although "va" is not mapped, paging-
6333 * structure caches could nonetheless have
6334 * entries that refer to the freed page table
6335 * pages. Invalidate those entries.
6337 pmap_invalidate_page(pmap, va);
6338 vm_page_free_pages_toq(&free, true);
6340 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6341 " in pmap %p", va, pmap);
6342 return (KERN_RESOURCE_SHORTAGE);
6344 if ((newpde & PG_RW) != 0) {
6345 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6346 vm_page_aflag_set(mt, PGA_WRITEABLE);
6351 * Increment counters.
6353 if ((newpde & PG_W) != 0)
6354 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6355 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6358 * Map the superpage. (This is not a promoted mapping; there will not
6359 * be any lingering 4KB page mappings in the TLB.)
6361 pde_store(pde, newpde);
6363 atomic_add_long(&pmap_pde_mappings, 1);
6364 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
6365 " in pmap %p", va, pmap);
6366 return (KERN_SUCCESS);
6370 * Maps a sequence of resident pages belonging to the same object.
6371 * The sequence begins with the given page m_start. This page is
6372 * mapped at the given virtual address start. Each subsequent page is
6373 * mapped at a virtual address that is offset from start by the same
6374 * amount as the page is offset from m_start within the object. The
6375 * last page in the sequence is the page with the largest offset from
6376 * m_start that can be mapped at a virtual address less than the given
6377 * virtual address end. Not every virtual page between start and end
6378 * is mapped; only those for which a resident page exists with the
6379 * corresponding offset from m_start are mapped.
6382 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6383 vm_page_t m_start, vm_prot_t prot)
6385 struct rwlock *lock;
6388 vm_pindex_t diff, psize;
6390 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6392 psize = atop(end - start);
6397 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6398 va = start + ptoa(diff);
6399 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6400 m->psind == 1 && pmap_ps_enabled(pmap) &&
6401 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6402 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6403 m = &m[NBPDR / PAGE_SIZE - 1];
6405 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6407 m = TAILQ_NEXT(m, listq);
6415 * this code makes some *MAJOR* assumptions:
6416 * 1. Current pmap & pmap exists.
6419 * 4. No page table pages.
6420 * but is *MUCH* faster than pmap_enter...
6424 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6426 struct rwlock *lock;
6430 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6437 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6438 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6440 struct spglist free;
6441 pt_entry_t newpte, *pte, PG_V;
6443 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6444 (m->oflags & VPO_UNMANAGED) != 0,
6445 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6446 PG_V = pmap_valid_bit(pmap);
6447 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6450 * In the case that a page table page is not
6451 * resident, we are creating it here.
6453 if (va < VM_MAXUSER_ADDRESS) {
6454 vm_pindex_t ptepindex;
6458 * Calculate pagetable page index
6460 ptepindex = pmap_pde_pindex(va);
6461 if (mpte && (mpte->pindex == ptepindex)) {
6465 * Get the page directory entry
6467 ptepa = pmap_pde(pmap, va);
6470 * If the page table page is mapped, we just increment
6471 * the hold count, and activate it. Otherwise, we
6472 * attempt to allocate a page table page. If this
6473 * attempt fails, we don't retry. Instead, we give up.
6475 if (ptepa && (*ptepa & PG_V) != 0) {
6478 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6482 * Pass NULL instead of the PV list lock
6483 * pointer, because we don't intend to sleep.
6485 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6490 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6491 pte = &pte[pmap_pte_index(va)];
6505 * Enter on the PV list if part of our managed memory.
6507 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6508 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6511 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6513 * Although "va" is not mapped, paging-
6514 * structure caches could nonetheless have
6515 * entries that refer to the freed page table
6516 * pages. Invalidate those entries.
6518 pmap_invalidate_page(pmap, va);
6519 vm_page_free_pages_toq(&free, true);
6527 * Increment counters
6529 pmap_resident_count_inc(pmap, 1);
6531 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6532 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6533 if ((m->oflags & VPO_UNMANAGED) == 0)
6534 newpte |= PG_MANAGED;
6535 if ((prot & VM_PROT_EXECUTE) == 0)
6537 if (va < VM_MAXUSER_ADDRESS)
6538 newpte |= PG_U | pmap_pkru_get(pmap, va);
6539 pte_store(pte, newpte);
6544 * Make a temporary mapping for a physical address. This is only intended
6545 * to be used for panic dumps.
6548 pmap_kenter_temporary(vm_paddr_t pa, int i)
6552 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6553 pmap_kenter(va, pa);
6555 return ((void *)crashdumpmap);
6559 * This code maps large physical mmap regions into the
6560 * processor address space. Note that some shortcuts
6561 * are taken, but the code works.
6564 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6565 vm_pindex_t pindex, vm_size_t size)
6568 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6569 vm_paddr_t pa, ptepa;
6573 PG_A = pmap_accessed_bit(pmap);
6574 PG_M = pmap_modified_bit(pmap);
6575 PG_V = pmap_valid_bit(pmap);
6576 PG_RW = pmap_rw_bit(pmap);
6578 VM_OBJECT_ASSERT_WLOCKED(object);
6579 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6580 ("pmap_object_init_pt: non-device object"));
6581 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6582 if (!pmap_ps_enabled(pmap))
6584 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6586 p = vm_page_lookup(object, pindex);
6587 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6588 ("pmap_object_init_pt: invalid page %p", p));
6589 pat_mode = p->md.pat_mode;
6592 * Abort the mapping if the first page is not physically
6593 * aligned to a 2MB page boundary.
6595 ptepa = VM_PAGE_TO_PHYS(p);
6596 if (ptepa & (NBPDR - 1))
6600 * Skip the first page. Abort the mapping if the rest of
6601 * the pages are not physically contiguous or have differing
6602 * memory attributes.
6604 p = TAILQ_NEXT(p, listq);
6605 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6607 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6608 ("pmap_object_init_pt: invalid page %p", p));
6609 if (pa != VM_PAGE_TO_PHYS(p) ||
6610 pat_mode != p->md.pat_mode)
6612 p = TAILQ_NEXT(p, listq);
6616 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6617 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6618 * will not affect the termination of this loop.
6621 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6622 pa < ptepa + size; pa += NBPDR) {
6623 pdpg = pmap_allocpde(pmap, addr, NULL);
6626 * The creation of mappings below is only an
6627 * optimization. If a page directory page
6628 * cannot be allocated without blocking,
6629 * continue on to the next mapping rather than
6635 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6636 pde = &pde[pmap_pde_index(addr)];
6637 if ((*pde & PG_V) == 0) {
6638 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6639 PG_U | PG_RW | PG_V);
6640 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6641 atomic_add_long(&pmap_pde_mappings, 1);
6643 /* Continue on if the PDE is already valid. */
6645 KASSERT(pdpg->ref_count > 0,
6646 ("pmap_object_init_pt: missing reference "
6647 "to page directory page, va: 0x%lx", addr));
6656 * Clear the wired attribute from the mappings for the specified range of
6657 * addresses in the given pmap. Every valid mapping within that range
6658 * must have the wired attribute set. In contrast, invalid mappings
6659 * cannot have the wired attribute set, so they are ignored.
6661 * The wired attribute of the page table entry is not a hardware
6662 * feature, so there is no need to invalidate any TLB entries.
6663 * Since pmap_demote_pde() for the wired entry must never fail,
6664 * pmap_delayed_invl_start()/finish() calls around the
6665 * function are not needed.
6668 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6670 vm_offset_t va_next;
6671 pml4_entry_t *pml4e;
6674 pt_entry_t *pte, PG_V;
6676 PG_V = pmap_valid_bit(pmap);
6678 for (; sva < eva; sva = va_next) {
6679 pml4e = pmap_pml4e(pmap, sva);
6680 if ((*pml4e & PG_V) == 0) {
6681 va_next = (sva + NBPML4) & ~PML4MASK;
6686 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6687 if ((*pdpe & PG_V) == 0) {
6688 va_next = (sva + NBPDP) & ~PDPMASK;
6693 va_next = (sva + NBPDR) & ~PDRMASK;
6696 pde = pmap_pdpe_to_pde(pdpe, sva);
6697 if ((*pde & PG_V) == 0)
6699 if ((*pde & PG_PS) != 0) {
6700 if ((*pde & PG_W) == 0)
6701 panic("pmap_unwire: pde %#jx is missing PG_W",
6705 * Are we unwiring the entire large page? If not,
6706 * demote the mapping and fall through.
6708 if (sva + NBPDR == va_next && eva >= va_next) {
6709 atomic_clear_long(pde, PG_W);
6710 pmap->pm_stats.wired_count -= NBPDR /
6713 } else if (!pmap_demote_pde(pmap, pde, sva))
6714 panic("pmap_unwire: demotion failed");
6718 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6720 if ((*pte & PG_V) == 0)
6722 if ((*pte & PG_W) == 0)
6723 panic("pmap_unwire: pte %#jx is missing PG_W",
6727 * PG_W must be cleared atomically. Although the pmap
6728 * lock synchronizes access to PG_W, another processor
6729 * could be setting PG_M and/or PG_A concurrently.
6731 atomic_clear_long(pte, PG_W);
6732 pmap->pm_stats.wired_count--;
6739 * Copy the range specified by src_addr/len
6740 * from the source map to the range dst_addr/len
6741 * in the destination map.
6743 * This routine is only advisory and need not do anything.
6746 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6747 vm_offset_t src_addr)
6749 struct rwlock *lock;
6750 struct spglist free;
6751 pml4_entry_t *pml4e;
6753 pd_entry_t *pde, srcptepaddr;
6754 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6755 vm_offset_t addr, end_addr, va_next;
6756 vm_page_t dst_pdpg, dstmpte, srcmpte;
6758 if (dst_addr != src_addr)
6761 if (dst_pmap->pm_type != src_pmap->pm_type)
6765 * EPT page table entries that require emulation of A/D bits are
6766 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6767 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6768 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6769 * implementations flag an EPT misconfiguration for exec-only
6770 * mappings we skip this function entirely for emulated pmaps.
6772 if (pmap_emulate_ad_bits(dst_pmap))
6775 end_addr = src_addr + len;
6777 if (dst_pmap < src_pmap) {
6778 PMAP_LOCK(dst_pmap);
6779 PMAP_LOCK(src_pmap);
6781 PMAP_LOCK(src_pmap);
6782 PMAP_LOCK(dst_pmap);
6785 PG_A = pmap_accessed_bit(dst_pmap);
6786 PG_M = pmap_modified_bit(dst_pmap);
6787 PG_V = pmap_valid_bit(dst_pmap);
6789 for (addr = src_addr; addr < end_addr; addr = va_next) {
6790 KASSERT(addr < UPT_MIN_ADDRESS,
6791 ("pmap_copy: invalid to pmap_copy page tables"));
6793 pml4e = pmap_pml4e(src_pmap, addr);
6794 if ((*pml4e & PG_V) == 0) {
6795 va_next = (addr + NBPML4) & ~PML4MASK;
6801 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6802 if ((*pdpe & PG_V) == 0) {
6803 va_next = (addr + NBPDP) & ~PDPMASK;
6809 va_next = (addr + NBPDR) & ~PDRMASK;
6813 pde = pmap_pdpe_to_pde(pdpe, addr);
6815 if (srcptepaddr == 0)
6818 if (srcptepaddr & PG_PS) {
6819 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6821 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6822 if (dst_pdpg == NULL)
6824 pde = (pd_entry_t *)
6825 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6826 pde = &pde[pmap_pde_index(addr)];
6827 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6828 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6829 PMAP_ENTER_NORECLAIM, &lock))) {
6830 *pde = srcptepaddr & ~PG_W;
6831 pmap_resident_count_inc(dst_pmap, NBPDR /
6833 atomic_add_long(&pmap_pde_mappings, 1);
6835 dst_pdpg->ref_count--;
6839 srcptepaddr &= PG_FRAME;
6840 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6841 KASSERT(srcmpte->ref_count > 0,
6842 ("pmap_copy: source page table page is unused"));
6844 if (va_next > end_addr)
6847 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6848 src_pte = &src_pte[pmap_pte_index(addr)];
6850 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6854 * We only virtual copy managed pages.
6856 if ((ptetemp & PG_MANAGED) == 0)
6859 if (dstmpte != NULL) {
6860 KASSERT(dstmpte->pindex ==
6861 pmap_pde_pindex(addr),
6862 ("dstmpte pindex/addr mismatch"));
6863 dstmpte->ref_count++;
6864 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6867 dst_pte = (pt_entry_t *)
6868 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6869 dst_pte = &dst_pte[pmap_pte_index(addr)];
6870 if (*dst_pte == 0 &&
6871 pmap_try_insert_pv_entry(dst_pmap, addr,
6872 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6874 * Clear the wired, modified, and accessed
6875 * (referenced) bits during the copy.
6877 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6878 pmap_resident_count_inc(dst_pmap, 1);
6881 if (pmap_unwire_ptp(dst_pmap, addr, dstmpte,
6884 * Although "addr" is not mapped,
6885 * paging-structure caches could
6886 * nonetheless have entries that refer
6887 * to the freed page table pages.
6888 * Invalidate those entries.
6890 pmap_invalidate_page(dst_pmap, addr);
6891 vm_page_free_pages_toq(&free, true);
6895 /* Have we copied all of the valid mappings? */
6896 if (dstmpte->ref_count >= srcmpte->ref_count)
6903 PMAP_UNLOCK(src_pmap);
6904 PMAP_UNLOCK(dst_pmap);
6908 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6912 if (dst_pmap->pm_type != src_pmap->pm_type ||
6913 dst_pmap->pm_type != PT_X86 ||
6914 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6917 if (dst_pmap < src_pmap) {
6918 PMAP_LOCK(dst_pmap);
6919 PMAP_LOCK(src_pmap);
6921 PMAP_LOCK(src_pmap);
6922 PMAP_LOCK(dst_pmap);
6924 error = pmap_pkru_copy(dst_pmap, src_pmap);
6925 /* Clean up partial copy on failure due to no memory. */
6926 if (error == ENOMEM)
6927 pmap_pkru_deassign_all(dst_pmap);
6928 PMAP_UNLOCK(src_pmap);
6929 PMAP_UNLOCK(dst_pmap);
6930 if (error != ENOMEM)
6938 * Zero the specified hardware page.
6941 pmap_zero_page(vm_page_t m)
6943 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6945 pagezero((void *)va);
6949 * Zero an an area within a single hardware page. off and size must not
6950 * cover an area beyond a single hardware page.
6953 pmap_zero_page_area(vm_page_t m, int off, int size)
6955 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6957 if (off == 0 && size == PAGE_SIZE)
6958 pagezero((void *)va);
6960 bzero((char *)va + off, size);
6964 * Copy 1 specified hardware page to another.
6967 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6969 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6970 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6972 pagecopy((void *)src, (void *)dst);
6975 int unmapped_buf_allowed = 1;
6978 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6979 vm_offset_t b_offset, int xfersize)
6983 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6987 while (xfersize > 0) {
6988 a_pg_offset = a_offset & PAGE_MASK;
6989 pages[0] = ma[a_offset >> PAGE_SHIFT];
6990 b_pg_offset = b_offset & PAGE_MASK;
6991 pages[1] = mb[b_offset >> PAGE_SHIFT];
6992 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6993 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6994 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6995 a_cp = (char *)vaddr[0] + a_pg_offset;
6996 b_cp = (char *)vaddr[1] + b_pg_offset;
6997 bcopy(a_cp, b_cp, cnt);
6998 if (__predict_false(mapped))
6999 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7007 * Returns true if the pmap's pv is one of the first
7008 * 16 pvs linked to from this page. This count may
7009 * be changed upwards or downwards in the future; it
7010 * is only necessary that true be returned for a small
7011 * subset of pmaps for proper page aging.
7014 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7016 struct md_page *pvh;
7017 struct rwlock *lock;
7022 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7023 ("pmap_page_exists_quick: page %p is not managed", m));
7025 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7027 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7028 if (PV_PMAP(pv) == pmap) {
7036 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7037 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7038 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7039 if (PV_PMAP(pv) == pmap) {
7053 * pmap_page_wired_mappings:
7055 * Return the number of managed mappings to the given physical page
7059 pmap_page_wired_mappings(vm_page_t m)
7061 struct rwlock *lock;
7062 struct md_page *pvh;
7066 int count, md_gen, pvh_gen;
7068 if ((m->oflags & VPO_UNMANAGED) != 0)
7070 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7074 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7076 if (!PMAP_TRYLOCK(pmap)) {
7077 md_gen = m->md.pv_gen;
7081 if (md_gen != m->md.pv_gen) {
7086 pte = pmap_pte(pmap, pv->pv_va);
7087 if ((*pte & PG_W) != 0)
7091 if ((m->flags & PG_FICTITIOUS) == 0) {
7092 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7093 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7095 if (!PMAP_TRYLOCK(pmap)) {
7096 md_gen = m->md.pv_gen;
7097 pvh_gen = pvh->pv_gen;
7101 if (md_gen != m->md.pv_gen ||
7102 pvh_gen != pvh->pv_gen) {
7107 pte = pmap_pde(pmap, pv->pv_va);
7108 if ((*pte & PG_W) != 0)
7118 * Returns TRUE if the given page is mapped individually or as part of
7119 * a 2mpage. Otherwise, returns FALSE.
7122 pmap_page_is_mapped(vm_page_t m)
7124 struct rwlock *lock;
7127 if ((m->oflags & VPO_UNMANAGED) != 0)
7129 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7131 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7132 ((m->flags & PG_FICTITIOUS) == 0 &&
7133 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7139 * Destroy all managed, non-wired mappings in the given user-space
7140 * pmap. This pmap cannot be active on any processor besides the
7143 * This function cannot be applied to the kernel pmap. Moreover, it
7144 * is not intended for general use. It is only to be used during
7145 * process termination. Consequently, it can be implemented in ways
7146 * that make it faster than pmap_remove(). First, it can more quickly
7147 * destroy mappings by iterating over the pmap's collection of PV
7148 * entries, rather than searching the page table. Second, it doesn't
7149 * have to test and clear the page table entries atomically, because
7150 * no processor is currently accessing the user address space. In
7151 * particular, a page table entry's dirty bit won't change state once
7152 * this function starts.
7154 * Although this function destroys all of the pmap's managed,
7155 * non-wired mappings, it can delay and batch the invalidation of TLB
7156 * entries without calling pmap_delayed_invl_start() and
7157 * pmap_delayed_invl_finish(). Because the pmap is not active on
7158 * any other processor, none of these TLB entries will ever be used
7159 * before their eventual invalidation. Consequently, there is no need
7160 * for either pmap_remove_all() or pmap_remove_write() to wait for
7161 * that eventual TLB invalidation.
7164 pmap_remove_pages(pmap_t pmap)
7167 pt_entry_t *pte, tpte;
7168 pt_entry_t PG_M, PG_RW, PG_V;
7169 struct spglist free;
7170 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7171 vm_page_t m, mpte, mt;
7173 struct md_page *pvh;
7174 struct pv_chunk *pc, *npc;
7175 struct rwlock *lock;
7177 uint64_t inuse, bitmask;
7178 int allfree, field, freed, i, idx;
7179 boolean_t superpage;
7183 * Assert that the given pmap is only active on the current
7184 * CPU. Unfortunately, we cannot block another CPU from
7185 * activating the pmap while this function is executing.
7187 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7190 cpuset_t other_cpus;
7192 other_cpus = all_cpus;
7194 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7195 CPU_AND(&other_cpus, &pmap->pm_active);
7197 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7202 PG_M = pmap_modified_bit(pmap);
7203 PG_V = pmap_valid_bit(pmap);
7204 PG_RW = pmap_rw_bit(pmap);
7206 for (i = 0; i < PMAP_MEMDOM; i++)
7207 TAILQ_INIT(&free_chunks[i]);
7210 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7213 for (field = 0; field < _NPCM; field++) {
7214 inuse = ~pc->pc_map[field] & pc_freemask[field];
7215 while (inuse != 0) {
7217 bitmask = 1UL << bit;
7218 idx = field * 64 + bit;
7219 pv = &pc->pc_pventry[idx];
7222 pte = pmap_pdpe(pmap, pv->pv_va);
7224 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7226 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7229 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7231 pte = &pte[pmap_pte_index(pv->pv_va)];
7235 * Keep track whether 'tpte' is a
7236 * superpage explicitly instead of
7237 * relying on PG_PS being set.
7239 * This is because PG_PS is numerically
7240 * identical to PG_PTE_PAT and thus a
7241 * regular page could be mistaken for
7247 if ((tpte & PG_V) == 0) {
7248 panic("bad pte va %lx pte %lx",
7253 * We cannot remove wired pages from a process' mapping at this time
7261 pa = tpte & PG_PS_FRAME;
7263 pa = tpte & PG_FRAME;
7265 m = PHYS_TO_VM_PAGE(pa);
7266 KASSERT(m->phys_addr == pa,
7267 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7268 m, (uintmax_t)m->phys_addr,
7271 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7272 m < &vm_page_array[vm_page_array_size],
7273 ("pmap_remove_pages: bad tpte %#jx",
7279 * Update the vm_page_t clean/reference bits.
7281 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7283 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7289 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7292 pc->pc_map[field] |= bitmask;
7294 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7295 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7296 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7298 if (TAILQ_EMPTY(&pvh->pv_list)) {
7299 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7300 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7301 TAILQ_EMPTY(&mt->md.pv_list))
7302 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7304 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7306 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7307 ("pmap_remove_pages: pte page not promoted"));
7308 pmap_resident_count_dec(pmap, 1);
7309 KASSERT(mpte->ref_count == NPTEPG,
7310 ("pmap_remove_pages: pte page reference count error"));
7311 mpte->ref_count = 0;
7312 pmap_add_delayed_free_list(mpte, &free, FALSE);
7315 pmap_resident_count_dec(pmap, 1);
7316 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7318 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
7319 TAILQ_EMPTY(&m->md.pv_list) &&
7320 (m->flags & PG_FICTITIOUS) == 0) {
7321 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7322 if (TAILQ_EMPTY(&pvh->pv_list))
7323 vm_page_aflag_clear(m, PGA_WRITEABLE);
7326 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7330 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7331 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7332 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7334 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7335 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7340 pmap_invalidate_all(pmap);
7341 pmap_pkru_deassign_all(pmap);
7342 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7344 vm_page_free_pages_toq(&free, true);
7348 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7350 struct rwlock *lock;
7352 struct md_page *pvh;
7353 pt_entry_t *pte, mask;
7354 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7356 int md_gen, pvh_gen;
7360 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7363 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7365 if (!PMAP_TRYLOCK(pmap)) {
7366 md_gen = m->md.pv_gen;
7370 if (md_gen != m->md.pv_gen) {
7375 pte = pmap_pte(pmap, pv->pv_va);
7378 PG_M = pmap_modified_bit(pmap);
7379 PG_RW = pmap_rw_bit(pmap);
7380 mask |= PG_RW | PG_M;
7383 PG_A = pmap_accessed_bit(pmap);
7384 PG_V = pmap_valid_bit(pmap);
7385 mask |= PG_V | PG_A;
7387 rv = (*pte & mask) == mask;
7392 if ((m->flags & PG_FICTITIOUS) == 0) {
7393 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7394 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7396 if (!PMAP_TRYLOCK(pmap)) {
7397 md_gen = m->md.pv_gen;
7398 pvh_gen = pvh->pv_gen;
7402 if (md_gen != m->md.pv_gen ||
7403 pvh_gen != pvh->pv_gen) {
7408 pte = pmap_pde(pmap, pv->pv_va);
7411 PG_M = pmap_modified_bit(pmap);
7412 PG_RW = pmap_rw_bit(pmap);
7413 mask |= PG_RW | PG_M;
7416 PG_A = pmap_accessed_bit(pmap);
7417 PG_V = pmap_valid_bit(pmap);
7418 mask |= PG_V | PG_A;
7420 rv = (*pte & mask) == mask;
7434 * Return whether or not the specified physical page was modified
7435 * in any physical maps.
7438 pmap_is_modified(vm_page_t m)
7441 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7442 ("pmap_is_modified: page %p is not managed", m));
7445 * If the page is not busied then this check is racy.
7447 if (!pmap_page_is_write_mapped(m))
7449 return (pmap_page_test_mappings(m, FALSE, TRUE));
7453 * pmap_is_prefaultable:
7455 * Return whether or not the specified virtual address is eligible
7459 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7462 pt_entry_t *pte, PG_V;
7465 PG_V = pmap_valid_bit(pmap);
7468 pde = pmap_pde(pmap, addr);
7469 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7470 pte = pmap_pde_to_pte(pde, addr);
7471 rv = (*pte & PG_V) == 0;
7478 * pmap_is_referenced:
7480 * Return whether or not the specified physical page was referenced
7481 * in any physical maps.
7484 pmap_is_referenced(vm_page_t m)
7487 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7488 ("pmap_is_referenced: page %p is not managed", m));
7489 return (pmap_page_test_mappings(m, TRUE, FALSE));
7493 * Clear the write and modified bits in each of the given page's mappings.
7496 pmap_remove_write(vm_page_t m)
7498 struct md_page *pvh;
7500 struct rwlock *lock;
7501 pv_entry_t next_pv, pv;
7503 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7505 int pvh_gen, md_gen;
7507 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7508 ("pmap_remove_write: page %p is not managed", m));
7510 vm_page_assert_busied(m);
7511 if (!pmap_page_is_write_mapped(m))
7514 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7515 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7516 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7519 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7521 if (!PMAP_TRYLOCK(pmap)) {
7522 pvh_gen = pvh->pv_gen;
7526 if (pvh_gen != pvh->pv_gen) {
7532 PG_RW = pmap_rw_bit(pmap);
7534 pde = pmap_pde(pmap, va);
7535 if ((*pde & PG_RW) != 0)
7536 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7537 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7538 ("inconsistent pv lock %p %p for page %p",
7539 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7542 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7544 if (!PMAP_TRYLOCK(pmap)) {
7545 pvh_gen = pvh->pv_gen;
7546 md_gen = m->md.pv_gen;
7550 if (pvh_gen != pvh->pv_gen ||
7551 md_gen != m->md.pv_gen) {
7557 PG_M = pmap_modified_bit(pmap);
7558 PG_RW = pmap_rw_bit(pmap);
7559 pde = pmap_pde(pmap, pv->pv_va);
7560 KASSERT((*pde & PG_PS) == 0,
7561 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7563 pte = pmap_pde_to_pte(pde, pv->pv_va);
7566 if (oldpte & PG_RW) {
7567 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7570 if ((oldpte & PG_M) != 0)
7572 pmap_invalidate_page(pmap, pv->pv_va);
7577 vm_page_aflag_clear(m, PGA_WRITEABLE);
7578 pmap_delayed_invl_wait(m);
7581 static __inline boolean_t
7582 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7585 if (!pmap_emulate_ad_bits(pmap))
7588 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7591 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7592 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7593 * if the EPT_PG_WRITE bit is set.
7595 if ((pte & EPT_PG_WRITE) != 0)
7599 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7601 if ((pte & EPT_PG_EXECUTE) == 0 ||
7602 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7609 * pmap_ts_referenced:
7611 * Return a count of reference bits for a page, clearing those bits.
7612 * It is not necessary for every reference bit to be cleared, but it
7613 * is necessary that 0 only be returned when there are truly no
7614 * reference bits set.
7616 * As an optimization, update the page's dirty field if a modified bit is
7617 * found while counting reference bits. This opportunistic update can be
7618 * performed at low cost and can eliminate the need for some future calls
7619 * to pmap_is_modified(). However, since this function stops after
7620 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7621 * dirty pages. Those dirty pages will only be detected by a future call
7622 * to pmap_is_modified().
7624 * A DI block is not needed within this function, because
7625 * invalidations are performed before the PV list lock is
7629 pmap_ts_referenced(vm_page_t m)
7631 struct md_page *pvh;
7634 struct rwlock *lock;
7635 pd_entry_t oldpde, *pde;
7636 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7639 int cleared, md_gen, not_cleared, pvh_gen;
7640 struct spglist free;
7643 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7644 ("pmap_ts_referenced: page %p is not managed", m));
7647 pa = VM_PAGE_TO_PHYS(m);
7648 lock = PHYS_TO_PV_LIST_LOCK(pa);
7649 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7653 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7654 goto small_mappings;
7660 if (!PMAP_TRYLOCK(pmap)) {
7661 pvh_gen = pvh->pv_gen;
7665 if (pvh_gen != pvh->pv_gen) {
7670 PG_A = pmap_accessed_bit(pmap);
7671 PG_M = pmap_modified_bit(pmap);
7672 PG_RW = pmap_rw_bit(pmap);
7674 pde = pmap_pde(pmap, pv->pv_va);
7676 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7678 * Although "oldpde" is mapping a 2MB page, because
7679 * this function is called at a 4KB page granularity,
7680 * we only update the 4KB page under test.
7684 if ((oldpde & PG_A) != 0) {
7686 * Since this reference bit is shared by 512 4KB
7687 * pages, it should not be cleared every time it is
7688 * tested. Apply a simple "hash" function on the
7689 * physical page number, the virtual superpage number,
7690 * and the pmap address to select one 4KB page out of
7691 * the 512 on which testing the reference bit will
7692 * result in clearing that reference bit. This
7693 * function is designed to avoid the selection of the
7694 * same 4KB page for every 2MB page mapping.
7696 * On demotion, a mapping that hasn't been referenced
7697 * is simply destroyed. To avoid the possibility of a
7698 * subsequent page fault on a demoted wired mapping,
7699 * always leave its reference bit set. Moreover,
7700 * since the superpage is wired, the current state of
7701 * its reference bit won't affect page replacement.
7703 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7704 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7705 (oldpde & PG_W) == 0) {
7706 if (safe_to_clear_referenced(pmap, oldpde)) {
7707 atomic_clear_long(pde, PG_A);
7708 pmap_invalidate_page(pmap, pv->pv_va);
7710 } else if (pmap_demote_pde_locked(pmap, pde,
7711 pv->pv_va, &lock)) {
7713 * Remove the mapping to a single page
7714 * so that a subsequent access may
7715 * repromote. Since the underlying
7716 * page table page is fully populated,
7717 * this removal never frees a page
7721 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7723 pte = pmap_pde_to_pte(pde, va);
7724 pmap_remove_pte(pmap, pte, va, *pde,
7726 pmap_invalidate_page(pmap, va);
7732 * The superpage mapping was removed
7733 * entirely and therefore 'pv' is no
7741 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7742 ("inconsistent pv lock %p %p for page %p",
7743 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7748 /* Rotate the PV list if it has more than one entry. */
7749 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7750 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7751 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7754 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7756 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7758 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7765 if (!PMAP_TRYLOCK(pmap)) {
7766 pvh_gen = pvh->pv_gen;
7767 md_gen = m->md.pv_gen;
7771 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7776 PG_A = pmap_accessed_bit(pmap);
7777 PG_M = pmap_modified_bit(pmap);
7778 PG_RW = pmap_rw_bit(pmap);
7779 pde = pmap_pde(pmap, pv->pv_va);
7780 KASSERT((*pde & PG_PS) == 0,
7781 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7783 pte = pmap_pde_to_pte(pde, pv->pv_va);
7784 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7786 if ((*pte & PG_A) != 0) {
7787 if (safe_to_clear_referenced(pmap, *pte)) {
7788 atomic_clear_long(pte, PG_A);
7789 pmap_invalidate_page(pmap, pv->pv_va);
7791 } else if ((*pte & PG_W) == 0) {
7793 * Wired pages cannot be paged out so
7794 * doing accessed bit emulation for
7795 * them is wasted effort. We do the
7796 * hard work for unwired pages only.
7798 pmap_remove_pte(pmap, pte, pv->pv_va,
7799 *pde, &free, &lock);
7800 pmap_invalidate_page(pmap, pv->pv_va);
7805 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7806 ("inconsistent pv lock %p %p for page %p",
7807 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7812 /* Rotate the PV list if it has more than one entry. */
7813 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7814 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7815 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7818 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7819 not_cleared < PMAP_TS_REFERENCED_MAX);
7822 vm_page_free_pages_toq(&free, true);
7823 return (cleared + not_cleared);
7827 * Apply the given advice to the specified range of addresses within the
7828 * given pmap. Depending on the advice, clear the referenced and/or
7829 * modified flags in each mapping and set the mapped page's dirty field.
7832 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7834 struct rwlock *lock;
7835 pml4_entry_t *pml4e;
7837 pd_entry_t oldpde, *pde;
7838 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7839 vm_offset_t va, va_next;
7843 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7847 * A/D bit emulation requires an alternate code path when clearing
7848 * the modified and accessed bits below. Since this function is
7849 * advisory in nature we skip it entirely for pmaps that require
7850 * A/D bit emulation.
7852 if (pmap_emulate_ad_bits(pmap))
7855 PG_A = pmap_accessed_bit(pmap);
7856 PG_G = pmap_global_bit(pmap);
7857 PG_M = pmap_modified_bit(pmap);
7858 PG_V = pmap_valid_bit(pmap);
7859 PG_RW = pmap_rw_bit(pmap);
7861 pmap_delayed_invl_start();
7863 for (; sva < eva; sva = va_next) {
7864 pml4e = pmap_pml4e(pmap, sva);
7865 if ((*pml4e & PG_V) == 0) {
7866 va_next = (sva + NBPML4) & ~PML4MASK;
7871 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7872 if ((*pdpe & PG_V) == 0) {
7873 va_next = (sva + NBPDP) & ~PDPMASK;
7878 va_next = (sva + NBPDR) & ~PDRMASK;
7881 pde = pmap_pdpe_to_pde(pdpe, sva);
7883 if ((oldpde & PG_V) == 0)
7885 else if ((oldpde & PG_PS) != 0) {
7886 if ((oldpde & PG_MANAGED) == 0)
7889 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7894 * The large page mapping was destroyed.
7900 * Unless the page mappings are wired, remove the
7901 * mapping to a single page so that a subsequent
7902 * access may repromote. Choosing the last page
7903 * within the address range [sva, min(va_next, eva))
7904 * generally results in more repromotions. Since the
7905 * underlying page table page is fully populated, this
7906 * removal never frees a page table page.
7908 if ((oldpde & PG_W) == 0) {
7914 ("pmap_advise: no address gap"));
7915 pte = pmap_pde_to_pte(pde, va);
7916 KASSERT((*pte & PG_V) != 0,
7917 ("pmap_advise: invalid PTE"));
7918 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7928 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7930 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7932 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7933 if (advice == MADV_DONTNEED) {
7935 * Future calls to pmap_is_modified()
7936 * can be avoided by making the page
7939 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7942 atomic_clear_long(pte, PG_M | PG_A);
7943 } else if ((*pte & PG_A) != 0)
7944 atomic_clear_long(pte, PG_A);
7948 if ((*pte & PG_G) != 0) {
7955 if (va != va_next) {
7956 pmap_invalidate_range(pmap, va, sva);
7961 pmap_invalidate_range(pmap, va, sva);
7964 pmap_invalidate_all(pmap);
7966 pmap_delayed_invl_finish();
7970 * Clear the modify bits on the specified physical page.
7973 pmap_clear_modify(vm_page_t m)
7975 struct md_page *pvh;
7977 pv_entry_t next_pv, pv;
7978 pd_entry_t oldpde, *pde;
7979 pt_entry_t *pte, PG_M, PG_RW;
7980 struct rwlock *lock;
7982 int md_gen, pvh_gen;
7984 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7985 ("pmap_clear_modify: page %p is not managed", m));
7986 vm_page_assert_busied(m);
7988 if (!pmap_page_is_write_mapped(m))
7990 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7991 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7992 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7995 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7997 if (!PMAP_TRYLOCK(pmap)) {
7998 pvh_gen = pvh->pv_gen;
8002 if (pvh_gen != pvh->pv_gen) {
8007 PG_M = pmap_modified_bit(pmap);
8008 PG_RW = pmap_rw_bit(pmap);
8010 pde = pmap_pde(pmap, va);
8012 /* If oldpde has PG_RW set, then it also has PG_M set. */
8013 if ((oldpde & PG_RW) != 0 &&
8014 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8015 (oldpde & PG_W) == 0) {
8017 * Write protect the mapping to a single page so that
8018 * a subsequent write access may repromote.
8020 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8021 pte = pmap_pde_to_pte(pde, va);
8022 atomic_clear_long(pte, PG_M | PG_RW);
8024 pmap_invalidate_page(pmap, va);
8028 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8030 if (!PMAP_TRYLOCK(pmap)) {
8031 md_gen = m->md.pv_gen;
8032 pvh_gen = pvh->pv_gen;
8036 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8041 PG_M = pmap_modified_bit(pmap);
8042 PG_RW = pmap_rw_bit(pmap);
8043 pde = pmap_pde(pmap, pv->pv_va);
8044 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8045 " a 2mpage in page %p's pv list", m));
8046 pte = pmap_pde_to_pte(pde, pv->pv_va);
8047 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8048 atomic_clear_long(pte, PG_M);
8049 pmap_invalidate_page(pmap, pv->pv_va);
8057 * Miscellaneous support routines follow
8060 /* Adjust the properties for a leaf page table entry. */
8061 static __inline void
8062 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8066 opte = *(u_long *)pte;
8068 npte = opte & ~mask;
8070 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8075 * Map a set of physical memory pages into the kernel virtual
8076 * address space. Return a pointer to where it is mapped. This
8077 * routine is intended to be used for mapping device memory,
8081 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8083 struct pmap_preinit_mapping *ppim;
8084 vm_offset_t va, offset;
8088 offset = pa & PAGE_MASK;
8089 size = round_page(offset + size);
8090 pa = trunc_page(pa);
8092 if (!pmap_initialized) {
8094 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8095 ppim = pmap_preinit_mapping + i;
8096 if (ppim->va == 0) {
8100 ppim->va = virtual_avail;
8101 virtual_avail += size;
8107 panic("%s: too many preinit mappings", __func__);
8110 * If we have a preinit mapping, re-use it.
8112 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8113 ppim = pmap_preinit_mapping + i;
8114 if (ppim->pa == pa && ppim->sz == size &&
8115 (ppim->mode == mode ||
8116 (flags & MAPDEV_SETATTR) == 0))
8117 return ((void *)(ppim->va + offset));
8120 * If the specified range of physical addresses fits within
8121 * the direct map window, use the direct map.
8123 if (pa < dmaplimit && pa + size <= dmaplimit) {
8124 va = PHYS_TO_DMAP(pa);
8125 if ((flags & MAPDEV_SETATTR) != 0) {
8126 PMAP_LOCK(kernel_pmap);
8127 i = pmap_change_props_locked(va, size,
8128 PROT_NONE, mode, flags);
8129 PMAP_UNLOCK(kernel_pmap);
8133 return ((void *)(va + offset));
8135 va = kva_alloc(size);
8137 panic("%s: Couldn't allocate KVA", __func__);
8139 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8140 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8141 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8142 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8143 pmap_invalidate_cache_range(va, va + tmpsize);
8144 return ((void *)(va + offset));
8148 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8151 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8156 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8159 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8163 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8166 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8171 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8174 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8175 MAPDEV_FLUSHCACHE));
8179 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8181 struct pmap_preinit_mapping *ppim;
8185 /* If we gave a direct map region in pmap_mapdev, do nothing */
8186 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8188 offset = va & PAGE_MASK;
8189 size = round_page(offset + size);
8190 va = trunc_page(va);
8191 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8192 ppim = pmap_preinit_mapping + i;
8193 if (ppim->va == va && ppim->sz == size) {
8194 if (pmap_initialized)
8200 if (va + size == virtual_avail)
8205 if (pmap_initialized)
8210 * Tries to demote a 1GB page mapping.
8213 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8215 pdp_entry_t newpdpe, oldpdpe;
8216 pd_entry_t *firstpde, newpde, *pde;
8217 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8221 PG_A = pmap_accessed_bit(pmap);
8222 PG_M = pmap_modified_bit(pmap);
8223 PG_V = pmap_valid_bit(pmap);
8224 PG_RW = pmap_rw_bit(pmap);
8226 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8228 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8229 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8230 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8231 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8232 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8233 " in pmap %p", va, pmap);
8236 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8237 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8238 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8239 KASSERT((oldpdpe & PG_A) != 0,
8240 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8241 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8242 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8246 * Initialize the page directory page.
8248 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8254 * Demote the mapping.
8259 * Invalidate a stale recursive mapping of the page directory page.
8261 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8263 pmap_pdpe_demotions++;
8264 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8265 " in pmap %p", va, pmap);
8270 * Sets the memory attribute for the specified page.
8273 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8276 m->md.pat_mode = ma;
8279 * If "m" is a normal page, update its direct mapping. This update
8280 * can be relied upon to perform any cache operations that are
8281 * required for data coherence.
8283 if ((m->flags & PG_FICTITIOUS) == 0 &&
8284 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8286 panic("memory attribute change on the direct map failed");
8290 * Changes the specified virtual address range's memory type to that given by
8291 * the parameter "mode". The specified virtual address range must be
8292 * completely contained within either the direct map or the kernel map. If
8293 * the virtual address range is contained within the kernel map, then the
8294 * memory type for each of the corresponding ranges of the direct map is also
8295 * changed. (The corresponding ranges of the direct map are those ranges that
8296 * map the same physical pages as the specified virtual address range.) These
8297 * changes to the direct map are necessary because Intel describes the
8298 * behavior of their processors as "undefined" if two or more mappings to the
8299 * same physical page have different memory types.
8301 * Returns zero if the change completed successfully, and either EINVAL or
8302 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8303 * of the virtual address range was not mapped, and ENOMEM is returned if
8304 * there was insufficient memory available to complete the change. In the
8305 * latter case, the memory type may have been changed on some part of the
8306 * virtual address range or the direct map.
8309 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8313 PMAP_LOCK(kernel_pmap);
8314 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8316 PMAP_UNLOCK(kernel_pmap);
8321 * Changes the specified virtual address range's protections to those
8322 * specified by "prot". Like pmap_change_attr(), protections for aliases
8323 * in the direct map are updated as well. Protections on aliasing mappings may
8324 * be a subset of the requested protections; for example, mappings in the direct
8325 * map are never executable.
8328 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8332 /* Only supported within the kernel map. */
8333 if (va < VM_MIN_KERNEL_ADDRESS)
8336 PMAP_LOCK(kernel_pmap);
8337 error = pmap_change_props_locked(va, size, prot, -1,
8338 MAPDEV_ASSERTVALID);
8339 PMAP_UNLOCK(kernel_pmap);
8344 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8345 int mode, int flags)
8347 vm_offset_t base, offset, tmpva;
8348 vm_paddr_t pa_start, pa_end, pa_end1;
8350 pd_entry_t *pde, pde_bits, pde_mask;
8351 pt_entry_t *pte, pte_bits, pte_mask;
8355 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8356 base = trunc_page(va);
8357 offset = va & PAGE_MASK;
8358 size = round_page(offset + size);
8361 * Only supported on kernel virtual addresses, including the direct
8362 * map but excluding the recursive map.
8364 if (base < DMAP_MIN_ADDRESS)
8368 * Construct our flag sets and masks. "bits" is the subset of
8369 * "mask" that will be set in each modified PTE.
8371 * Mappings in the direct map are never allowed to be executable.
8373 pde_bits = pte_bits = 0;
8374 pde_mask = pte_mask = 0;
8376 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8377 pde_mask |= X86_PG_PDE_CACHE;
8378 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8379 pte_mask |= X86_PG_PTE_CACHE;
8381 if (prot != VM_PROT_NONE) {
8382 if ((prot & VM_PROT_WRITE) != 0) {
8383 pde_bits |= X86_PG_RW;
8384 pte_bits |= X86_PG_RW;
8386 if ((prot & VM_PROT_EXECUTE) == 0 ||
8387 va < VM_MIN_KERNEL_ADDRESS) {
8391 pde_mask |= X86_PG_RW | pg_nx;
8392 pte_mask |= X86_PG_RW | pg_nx;
8396 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8397 * into 4KB pages if required.
8399 for (tmpva = base; tmpva < base + size; ) {
8400 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8401 if (pdpe == NULL || *pdpe == 0) {
8402 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8403 ("%s: addr %#lx is not mapped", __func__, tmpva));
8406 if (*pdpe & PG_PS) {
8408 * If the current 1GB page already has the required
8409 * properties, then we need not demote this page. Just
8410 * increment tmpva to the next 1GB page frame.
8412 if ((*pdpe & pde_mask) == pde_bits) {
8413 tmpva = trunc_1gpage(tmpva) + NBPDP;
8418 * If the current offset aligns with a 1GB page frame
8419 * and there is at least 1GB left within the range, then
8420 * we need not break down this page into 2MB pages.
8422 if ((tmpva & PDPMASK) == 0 &&
8423 tmpva + PDPMASK < base + size) {
8427 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8430 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8432 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8433 ("%s: addr %#lx is not mapped", __func__, tmpva));
8438 * If the current 2MB page already has the required
8439 * properties, then we need not demote this page. Just
8440 * increment tmpva to the next 2MB page frame.
8442 if ((*pde & pde_mask) == pde_bits) {
8443 tmpva = trunc_2mpage(tmpva) + NBPDR;
8448 * If the current offset aligns with a 2MB page frame
8449 * and there is at least 2MB left within the range, then
8450 * we need not break down this page into 4KB pages.
8452 if ((tmpva & PDRMASK) == 0 &&
8453 tmpva + PDRMASK < base + size) {
8457 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8460 pte = pmap_pde_to_pte(pde, tmpva);
8462 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8463 ("%s: addr %#lx is not mapped", __func__, tmpva));
8471 * Ok, all the pages exist, so run through them updating their
8472 * properties if required.
8475 pa_start = pa_end = 0;
8476 for (tmpva = base; tmpva < base + size; ) {
8477 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8478 if (*pdpe & PG_PS) {
8479 if ((*pdpe & pde_mask) != pde_bits) {
8480 pmap_pte_props(pdpe, pde_bits, pde_mask);
8483 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8484 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8485 if (pa_start == pa_end) {
8486 /* Start physical address run. */
8487 pa_start = *pdpe & PG_PS_FRAME;
8488 pa_end = pa_start + NBPDP;
8489 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8492 /* Run ended, update direct map. */
8493 error = pmap_change_props_locked(
8494 PHYS_TO_DMAP(pa_start),
8495 pa_end - pa_start, prot, mode,
8499 /* Start physical address run. */
8500 pa_start = *pdpe & PG_PS_FRAME;
8501 pa_end = pa_start + NBPDP;
8504 tmpva = trunc_1gpage(tmpva) + NBPDP;
8507 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8509 if ((*pde & pde_mask) != pde_bits) {
8510 pmap_pte_props(pde, pde_bits, pde_mask);
8513 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8514 (*pde & PG_PS_FRAME) < dmaplimit) {
8515 if (pa_start == pa_end) {
8516 /* Start physical address run. */
8517 pa_start = *pde & PG_PS_FRAME;
8518 pa_end = pa_start + NBPDR;
8519 } else if (pa_end == (*pde & PG_PS_FRAME))
8522 /* Run ended, update direct map. */
8523 error = pmap_change_props_locked(
8524 PHYS_TO_DMAP(pa_start),
8525 pa_end - pa_start, prot, mode,
8529 /* Start physical address run. */
8530 pa_start = *pde & PG_PS_FRAME;
8531 pa_end = pa_start + NBPDR;
8534 tmpva = trunc_2mpage(tmpva) + NBPDR;
8536 pte = pmap_pde_to_pte(pde, tmpva);
8537 if ((*pte & pte_mask) != pte_bits) {
8538 pmap_pte_props(pte, pte_bits, pte_mask);
8541 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8542 (*pte & PG_FRAME) < dmaplimit) {
8543 if (pa_start == pa_end) {
8544 /* Start physical address run. */
8545 pa_start = *pte & PG_FRAME;
8546 pa_end = pa_start + PAGE_SIZE;
8547 } else if (pa_end == (*pte & PG_FRAME))
8548 pa_end += PAGE_SIZE;
8550 /* Run ended, update direct map. */
8551 error = pmap_change_props_locked(
8552 PHYS_TO_DMAP(pa_start),
8553 pa_end - pa_start, prot, mode,
8557 /* Start physical address run. */
8558 pa_start = *pte & PG_FRAME;
8559 pa_end = pa_start + PAGE_SIZE;
8565 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8566 pa_end1 = MIN(pa_end, dmaplimit);
8567 if (pa_start != pa_end1)
8568 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
8569 pa_end1 - pa_start, prot, mode, flags);
8573 * Flush CPU caches if required to make sure any data isn't cached that
8574 * shouldn't be, etc.
8577 pmap_invalidate_range(kernel_pmap, base, tmpva);
8578 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8579 pmap_invalidate_cache_range(base, tmpva);
8585 * Demotes any mapping within the direct map region that covers more than the
8586 * specified range of physical addresses. This range's size must be a power
8587 * of two and its starting address must be a multiple of its size. Since the
8588 * demotion does not change any attributes of the mapping, a TLB invalidation
8589 * is not mandatory. The caller may, however, request a TLB invalidation.
8592 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8601 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8602 KASSERT((base & (len - 1)) == 0,
8603 ("pmap_demote_DMAP: base is not a multiple of len"));
8604 if (len < NBPDP && base < dmaplimit) {
8605 va = PHYS_TO_DMAP(base);
8607 PMAP_LOCK(kernel_pmap);
8608 pdpe = pmap_pdpe(kernel_pmap, va);
8609 if ((*pdpe & X86_PG_V) == 0)
8610 panic("pmap_demote_DMAP: invalid PDPE");
8611 if ((*pdpe & PG_PS) != 0) {
8612 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8613 panic("pmap_demote_DMAP: PDPE failed");
8617 pde = pmap_pdpe_to_pde(pdpe, va);
8618 if ((*pde & X86_PG_V) == 0)
8619 panic("pmap_demote_DMAP: invalid PDE");
8620 if ((*pde & PG_PS) != 0) {
8621 if (!pmap_demote_pde(kernel_pmap, pde, va))
8622 panic("pmap_demote_DMAP: PDE failed");
8626 if (changed && invalidate)
8627 pmap_invalidate_page(kernel_pmap, va);
8628 PMAP_UNLOCK(kernel_pmap);
8633 * Perform the pmap work for mincore(2). If the page is not both referenced and
8634 * modified by this pmap, returns its physical address so that the caller can
8635 * find other mappings.
8638 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
8641 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8645 PG_A = pmap_accessed_bit(pmap);
8646 PG_M = pmap_modified_bit(pmap);
8647 PG_V = pmap_valid_bit(pmap);
8648 PG_RW = pmap_rw_bit(pmap);
8651 pdep = pmap_pde(pmap, addr);
8652 if (pdep != NULL && (*pdep & PG_V)) {
8653 if (*pdep & PG_PS) {
8655 /* Compute the physical address of the 4KB page. */
8656 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8658 val = MINCORE_SUPER;
8660 pte = *pmap_pde_to_pte(pdep, addr);
8661 pa = pte & PG_FRAME;
8669 if ((pte & PG_V) != 0) {
8670 val |= MINCORE_INCORE;
8671 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8672 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8673 if ((pte & PG_A) != 0)
8674 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8676 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8677 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8678 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8686 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8688 uint32_t gen, new_gen, pcid_next;
8690 CRITICAL_ASSERT(curthread);
8691 gen = PCPU_GET(pcid_gen);
8692 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8693 return (pti ? 0 : CR3_PCID_SAVE);
8694 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8695 return (CR3_PCID_SAVE);
8696 pcid_next = PCPU_GET(pcid_next);
8697 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8698 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8699 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8700 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8701 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8705 PCPU_SET(pcid_gen, new_gen);
8706 pcid_next = PMAP_PCID_KERN + 1;
8710 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8711 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8712 PCPU_SET(pcid_next, pcid_next + 1);
8717 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8721 cached = pmap_pcid_alloc(pmap, cpuid);
8722 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8723 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8724 pmap->pm_pcids[cpuid].pm_pcid));
8725 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8726 pmap == kernel_pmap,
8727 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8728 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8733 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8736 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8737 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
8741 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8743 struct invpcid_descr d;
8744 uint64_t cached, cr3, kcr3, ucr3;
8746 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8748 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8749 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8750 PCPU_SET(curpmap, pmap);
8751 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8752 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8755 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8757 * Explicitly invalidate translations cached from the
8758 * user page table. They are not automatically
8759 * flushed by reload of cr3 with the kernel page table
8762 * Note that the if() condition is resolved statically
8763 * by using the function argument instead of
8764 * runtime-evaluated invpcid_works value.
8766 if (invpcid_works1) {
8767 d.pcid = PMAP_PCID_USER_PT |
8768 pmap->pm_pcids[cpuid].pm_pcid;
8771 invpcid(&d, INVPCID_CTX);
8773 pmap_pti_pcid_invalidate(ucr3, kcr3);
8777 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8778 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8780 PCPU_INC(pm_save_cnt);
8784 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8787 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8788 pmap_activate_sw_pti_post(td, pmap);
8792 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8798 * If the INVPCID instruction is not available,
8799 * invltlb_pcid_handler() is used to handle an invalidate_all
8800 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8801 * sequence of operations has a window where %CR3 is loaded
8802 * with the new pmap's PML4 address, but the curpmap value has
8803 * not yet been updated. This causes the invltlb IPI handler,
8804 * which is called between the updates, to execute as a NOP,
8805 * which leaves stale TLB entries.
8807 * Note that the most typical use of pmap_activate_sw(), from
8808 * the context switch, is immune to this race, because
8809 * interrupts are disabled (while the thread lock is owned),
8810 * and the IPI happens after curpmap is updated. Protect
8811 * other callers in a similar way, by disabling interrupts
8812 * around the %cr3 register reload and curpmap assignment.
8814 rflags = intr_disable();
8815 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8816 intr_restore(rflags);
8817 pmap_activate_sw_pti_post(td, pmap);
8821 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8824 uint64_t cached, cr3;
8826 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8828 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8829 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8831 PCPU_SET(curpmap, pmap);
8833 PCPU_INC(pm_save_cnt);
8837 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8842 rflags = intr_disable();
8843 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8844 intr_restore(rflags);
8848 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8849 u_int cpuid __unused)
8852 load_cr3(pmap->pm_cr3);
8853 PCPU_SET(curpmap, pmap);
8857 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8858 u_int cpuid __unused)
8861 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8862 PCPU_SET(kcr3, pmap->pm_cr3);
8863 PCPU_SET(ucr3, pmap->pm_ucr3);
8864 pmap_activate_sw_pti_post(td, pmap);
8867 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8871 if (pmap_pcid_enabled && pti && invpcid_works)
8872 return (pmap_activate_sw_pcid_invpcid_pti);
8873 else if (pmap_pcid_enabled && pti && !invpcid_works)
8874 return (pmap_activate_sw_pcid_noinvpcid_pti);
8875 else if (pmap_pcid_enabled && !pti && invpcid_works)
8876 return (pmap_activate_sw_pcid_nopti);
8877 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8878 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8879 else if (!pmap_pcid_enabled && pti)
8880 return (pmap_activate_sw_nopcid_pti);
8881 else /* if (!pmap_pcid_enabled && !pti) */
8882 return (pmap_activate_sw_nopcid_nopti);
8886 pmap_activate_sw(struct thread *td)
8888 pmap_t oldpmap, pmap;
8891 oldpmap = PCPU_GET(curpmap);
8892 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8893 if (oldpmap == pmap) {
8894 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8898 cpuid = PCPU_GET(cpuid);
8900 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8902 CPU_SET(cpuid, &pmap->pm_active);
8904 pmap_activate_sw_mode(td, pmap, cpuid);
8906 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8908 CPU_CLR(cpuid, &oldpmap->pm_active);
8913 pmap_activate(struct thread *td)
8917 pmap_activate_sw(td);
8922 pmap_activate_boot(pmap_t pmap)
8928 * kernel_pmap must be never deactivated, and we ensure that
8929 * by never activating it at all.
8931 MPASS(pmap != kernel_pmap);
8933 cpuid = PCPU_GET(cpuid);
8935 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8937 CPU_SET(cpuid, &pmap->pm_active);
8939 PCPU_SET(curpmap, pmap);
8941 kcr3 = pmap->pm_cr3;
8942 if (pmap_pcid_enabled)
8943 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8947 PCPU_SET(kcr3, kcr3);
8948 PCPU_SET(ucr3, PMAP_NO_CR3);
8952 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8957 * Increase the starting virtual address of the given mapping if a
8958 * different alignment might result in more superpage mappings.
8961 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8962 vm_offset_t *addr, vm_size_t size)
8964 vm_offset_t superpage_offset;
8968 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8969 offset += ptoa(object->pg_color);
8970 superpage_offset = offset & PDRMASK;
8971 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8972 (*addr & PDRMASK) == superpage_offset)
8974 if ((*addr & PDRMASK) < superpage_offset)
8975 *addr = (*addr & ~PDRMASK) + superpage_offset;
8977 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8981 static unsigned long num_dirty_emulations;
8982 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8983 &num_dirty_emulations, 0, NULL);
8985 static unsigned long num_accessed_emulations;
8986 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8987 &num_accessed_emulations, 0, NULL);
8989 static unsigned long num_superpage_accessed_emulations;
8990 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8991 &num_superpage_accessed_emulations, 0, NULL);
8993 static unsigned long ad_emulation_superpage_promotions;
8994 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8995 &ad_emulation_superpage_promotions, 0, NULL);
8996 #endif /* INVARIANTS */
8999 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9002 struct rwlock *lock;
9003 #if VM_NRESERVLEVEL > 0
9007 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9009 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9010 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9012 if (!pmap_emulate_ad_bits(pmap))
9015 PG_A = pmap_accessed_bit(pmap);
9016 PG_M = pmap_modified_bit(pmap);
9017 PG_V = pmap_valid_bit(pmap);
9018 PG_RW = pmap_rw_bit(pmap);
9024 pde = pmap_pde(pmap, va);
9025 if (pde == NULL || (*pde & PG_V) == 0)
9028 if ((*pde & PG_PS) != 0) {
9029 if (ftype == VM_PROT_READ) {
9031 atomic_add_long(&num_superpage_accessed_emulations, 1);
9039 pte = pmap_pde_to_pte(pde, va);
9040 if ((*pte & PG_V) == 0)
9043 if (ftype == VM_PROT_WRITE) {
9044 if ((*pte & PG_RW) == 0)
9047 * Set the modified and accessed bits simultaneously.
9049 * Intel EPT PTEs that do software emulation of A/D bits map
9050 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9051 * An EPT misconfiguration is triggered if the PTE is writable
9052 * but not readable (WR=10). This is avoided by setting PG_A
9053 * and PG_M simultaneously.
9055 *pte |= PG_M | PG_A;
9060 #if VM_NRESERVLEVEL > 0
9061 /* try to promote the mapping */
9062 if (va < VM_MAXUSER_ADDRESS)
9063 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9067 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9069 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9070 pmap_ps_enabled(pmap) &&
9071 (m->flags & PG_FICTITIOUS) == 0 &&
9072 vm_reserv_level_iffullpop(m) == 0) {
9073 pmap_promote_pde(pmap, pde, va, &lock);
9075 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9081 if (ftype == VM_PROT_WRITE)
9082 atomic_add_long(&num_dirty_emulations, 1);
9084 atomic_add_long(&num_accessed_emulations, 1);
9086 rv = 0; /* success */
9095 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9100 pt_entry_t *pte, PG_V;
9104 PG_V = pmap_valid_bit(pmap);
9107 pml4 = pmap_pml4e(pmap, va);
9109 if ((*pml4 & PG_V) == 0)
9112 pdp = pmap_pml4e_to_pdpe(pml4, va);
9114 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9117 pde = pmap_pdpe_to_pde(pdp, va);
9119 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9122 pte = pmap_pde_to_pte(pde, va);
9131 * Get the kernel virtual address of a set of physical pages. If there are
9132 * physical addresses not covered by the DMAP perform a transient mapping
9133 * that will be removed when calling pmap_unmap_io_transient.
9135 * \param page The pages the caller wishes to obtain the virtual
9136 * address on the kernel memory map.
9137 * \param vaddr On return contains the kernel virtual memory address
9138 * of the pages passed in the page parameter.
9139 * \param count Number of pages passed in.
9140 * \param can_fault TRUE if the thread using the mapped pages can take
9141 * page faults, FALSE otherwise.
9143 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9144 * finished or FALSE otherwise.
9148 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9149 boolean_t can_fault)
9152 boolean_t needs_mapping;
9154 int cache_bits, error __unused, i;
9157 * Allocate any KVA space that we need, this is done in a separate
9158 * loop to prevent calling vmem_alloc while pinned.
9160 needs_mapping = FALSE;
9161 for (i = 0; i < count; i++) {
9162 paddr = VM_PAGE_TO_PHYS(page[i]);
9163 if (__predict_false(paddr >= dmaplimit)) {
9164 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9165 M_BESTFIT | M_WAITOK, &vaddr[i]);
9166 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9167 needs_mapping = TRUE;
9169 vaddr[i] = PHYS_TO_DMAP(paddr);
9173 /* Exit early if everything is covered by the DMAP */
9178 * NB: The sequence of updating a page table followed by accesses
9179 * to the corresponding pages used in the !DMAP case is subject to
9180 * the situation described in the "AMD64 Architecture Programmer's
9181 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9182 * Coherency Considerations". Therefore, issuing the INVLPG right
9183 * after modifying the PTE bits is crucial.
9187 for (i = 0; i < count; i++) {
9188 paddr = VM_PAGE_TO_PHYS(page[i]);
9189 if (paddr >= dmaplimit) {
9192 * Slow path, since we can get page faults
9193 * while mappings are active don't pin the
9194 * thread to the CPU and instead add a global
9195 * mapping visible to all CPUs.
9197 pmap_qenter(vaddr[i], &page[i], 1);
9199 pte = vtopte(vaddr[i]);
9200 cache_bits = pmap_cache_bits(kernel_pmap,
9201 page[i]->md.pat_mode, 0);
9202 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9209 return (needs_mapping);
9213 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9214 boolean_t can_fault)
9221 for (i = 0; i < count; i++) {
9222 paddr = VM_PAGE_TO_PHYS(page[i]);
9223 if (paddr >= dmaplimit) {
9225 pmap_qremove(vaddr[i], 1);
9226 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9232 pmap_quick_enter_page(vm_page_t m)
9236 paddr = VM_PAGE_TO_PHYS(m);
9237 if (paddr < dmaplimit)
9238 return (PHYS_TO_DMAP(paddr));
9239 mtx_lock_spin(&qframe_mtx);
9240 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9241 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9242 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9247 pmap_quick_remove_page(vm_offset_t addr)
9252 pte_store(vtopte(qframe), 0);
9254 mtx_unlock_spin(&qframe_mtx);
9258 * Pdp pages from the large map are managed differently from either
9259 * kernel or user page table pages. They are permanently allocated at
9260 * initialization time, and their reference count is permanently set to
9261 * zero. The pml4 entries pointing to those pages are copied into
9262 * each allocated pmap.
9264 * In contrast, pd and pt pages are managed like user page table
9265 * pages. They are dynamically allocated, and their reference count
9266 * represents the number of valid entries within the page.
9269 pmap_large_map_getptp_unlocked(void)
9273 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9275 if (m != NULL && (m->flags & PG_ZERO) == 0)
9281 pmap_large_map_getptp(void)
9285 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9286 m = pmap_large_map_getptp_unlocked();
9288 PMAP_UNLOCK(kernel_pmap);
9290 PMAP_LOCK(kernel_pmap);
9291 /* Callers retry. */
9296 static pdp_entry_t *
9297 pmap_large_map_pdpe(vm_offset_t va)
9299 vm_pindex_t pml4_idx;
9302 pml4_idx = pmap_pml4e_index(va);
9303 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9304 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9306 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9307 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
9308 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9309 "LMSPML4I %#jx lm_ents %d",
9310 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9311 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
9312 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9316 pmap_large_map_pde(vm_offset_t va)
9323 pdpe = pmap_large_map_pdpe(va);
9325 m = pmap_large_map_getptp();
9328 mphys = VM_PAGE_TO_PHYS(m);
9329 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9331 MPASS((*pdpe & X86_PG_PS) == 0);
9332 mphys = *pdpe & PG_FRAME;
9334 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9338 pmap_large_map_pte(vm_offset_t va)
9345 pde = pmap_large_map_pde(va);
9347 m = pmap_large_map_getptp();
9350 mphys = VM_PAGE_TO_PHYS(m);
9351 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9352 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9354 MPASS((*pde & X86_PG_PS) == 0);
9355 mphys = *pde & PG_FRAME;
9357 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9361 pmap_large_map_kextract(vm_offset_t va)
9363 pdp_entry_t *pdpe, pdp;
9364 pd_entry_t *pde, pd;
9365 pt_entry_t *pte, pt;
9367 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9368 ("not largemap range %#lx", (u_long)va));
9369 pdpe = pmap_large_map_pdpe(va);
9371 KASSERT((pdp & X86_PG_V) != 0,
9372 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9373 (u_long)pdpe, pdp));
9374 if ((pdp & X86_PG_PS) != 0) {
9375 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9376 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9377 (u_long)pdpe, pdp));
9378 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9380 pde = pmap_pdpe_to_pde(pdpe, va);
9382 KASSERT((pd & X86_PG_V) != 0,
9383 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9384 if ((pd & X86_PG_PS) != 0)
9385 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9386 pte = pmap_pde_to_pte(pde, va);
9388 KASSERT((pt & X86_PG_V) != 0,
9389 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9390 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9394 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9395 vmem_addr_t *vmem_res)
9399 * Large mappings are all but static. Consequently, there
9400 * is no point in waiting for an earlier allocation to be
9403 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9404 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9408 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9414 vm_offset_t va, inc;
9415 vmem_addr_t vmem_res;
9419 if (len == 0 || spa + len < spa)
9422 /* See if DMAP can serve. */
9423 if (spa + len <= dmaplimit) {
9424 va = PHYS_TO_DMAP(spa);
9426 return (pmap_change_attr(va, len, mattr));
9430 * No, allocate KVA. Fit the address with best possible
9431 * alignment for superpages. Fall back to worse align if
9435 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9436 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9437 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9439 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9441 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9444 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9449 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9450 * in the pagetable to minimize flushing. No need to
9451 * invalidate TLB, since we only update invalid entries.
9453 PMAP_LOCK(kernel_pmap);
9454 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9456 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9457 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9458 pdpe = pmap_large_map_pdpe(va);
9460 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9461 X86_PG_V | X86_PG_A | pg_nx |
9462 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9464 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9465 (va & PDRMASK) == 0) {
9466 pde = pmap_large_map_pde(va);
9468 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9469 X86_PG_V | X86_PG_A | pg_nx |
9470 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9471 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9475 pte = pmap_large_map_pte(va);
9477 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9478 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9480 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9485 PMAP_UNLOCK(kernel_pmap);
9488 *addr = (void *)vmem_res;
9493 pmap_large_unmap(void *svaa, vm_size_t len)
9495 vm_offset_t sva, va;
9497 pdp_entry_t *pdpe, pdp;
9498 pd_entry_t *pde, pd;
9501 struct spglist spgf;
9503 sva = (vm_offset_t)svaa;
9504 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9505 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9509 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9510 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9511 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9512 PMAP_LOCK(kernel_pmap);
9513 for (va = sva; va < sva + len; va += inc) {
9514 pdpe = pmap_large_map_pdpe(va);
9516 KASSERT((pdp & X86_PG_V) != 0,
9517 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9518 (u_long)pdpe, pdp));
9519 if ((pdp & X86_PG_PS) != 0) {
9520 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9521 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9522 (u_long)pdpe, pdp));
9523 KASSERT((va & PDPMASK) == 0,
9524 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9525 (u_long)pdpe, pdp));
9526 KASSERT(va + NBPDP <= sva + len,
9527 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9528 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9529 (u_long)pdpe, pdp, len));
9534 pde = pmap_pdpe_to_pde(pdpe, va);
9536 KASSERT((pd & X86_PG_V) != 0,
9537 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9539 if ((pd & X86_PG_PS) != 0) {
9540 KASSERT((va & PDRMASK) == 0,
9541 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9543 KASSERT(va + NBPDR <= sva + len,
9544 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9545 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9549 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9551 if (m->ref_count == 0) {
9553 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9557 pte = pmap_pde_to_pte(pde, va);
9558 KASSERT((*pte & X86_PG_V) != 0,
9559 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9560 (u_long)pte, *pte));
9563 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9565 if (m->ref_count == 0) {
9567 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9568 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9570 if (m->ref_count == 0) {
9572 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9576 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9577 PMAP_UNLOCK(kernel_pmap);
9578 vm_page_free_pages_toq(&spgf, false);
9579 vmem_free(large_vmem, sva, len);
9583 pmap_large_map_wb_fence_mfence(void)
9590 pmap_large_map_wb_fence_atomic(void)
9593 atomic_thread_fence_seq_cst();
9597 pmap_large_map_wb_fence_nop(void)
9601 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9604 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9605 return (pmap_large_map_wb_fence_mfence);
9606 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9607 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9608 return (pmap_large_map_wb_fence_atomic);
9610 /* clflush is strongly enough ordered */
9611 return (pmap_large_map_wb_fence_nop);
9615 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9618 for (; len > 0; len -= cpu_clflush_line_size,
9619 va += cpu_clflush_line_size)
9624 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9627 for (; len > 0; len -= cpu_clflush_line_size,
9628 va += cpu_clflush_line_size)
9633 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9636 for (; len > 0; len -= cpu_clflush_line_size,
9637 va += cpu_clflush_line_size)
9642 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9646 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9649 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9650 return (pmap_large_map_flush_range_clwb);
9651 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9652 return (pmap_large_map_flush_range_clflushopt);
9653 else if ((cpu_feature & CPUID_CLFSH) != 0)
9654 return (pmap_large_map_flush_range_clflush);
9656 return (pmap_large_map_flush_range_nop);
9660 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9662 volatile u_long *pe;
9668 for (va = sva; va < eva; va += inc) {
9670 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9671 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9673 if ((p & X86_PG_PS) != 0)
9677 pe = (volatile u_long *)pmap_large_map_pde(va);
9679 if ((p & X86_PG_PS) != 0)
9683 pe = (volatile u_long *)pmap_large_map_pte(va);
9689 if ((p & X86_PG_AVAIL1) != 0) {
9691 * Spin-wait for the end of a parallel
9698 * If we saw other write-back
9699 * occuring, we cannot rely on PG_M to
9700 * indicate state of the cache. The
9701 * PG_M bit is cleared before the
9702 * flush to avoid ignoring new writes,
9703 * and writes which are relevant for
9704 * us might happen after.
9710 if ((p & X86_PG_M) != 0 || seen_other) {
9711 if (!atomic_fcmpset_long(pe, &p,
9712 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9714 * If we saw PG_M without
9715 * PG_AVAIL1, and then on the
9716 * next attempt we do not
9717 * observe either PG_M or
9718 * PG_AVAIL1, the other
9719 * write-back started after us
9720 * and finished before us. We
9721 * can rely on it doing our
9725 pmap_large_map_flush_range(va, inc);
9726 atomic_clear_long(pe, X86_PG_AVAIL1);
9735 * Write-back cache lines for the given address range.
9737 * Must be called only on the range or sub-range returned from
9738 * pmap_large_map(). Must not be called on the coalesced ranges.
9740 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9741 * instructions support.
9744 pmap_large_map_wb(void *svap, vm_size_t len)
9746 vm_offset_t eva, sva;
9748 sva = (vm_offset_t)svap;
9750 pmap_large_map_wb_fence();
9751 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9752 pmap_large_map_flush_range(sva, len);
9754 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9755 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9756 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9757 pmap_large_map_wb_large(sva, eva);
9759 pmap_large_map_wb_fence();
9763 pmap_pti_alloc_page(void)
9767 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9768 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9769 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9774 pmap_pti_free_page(vm_page_t m)
9777 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
9778 if (!vm_page_unwire_noq(m))
9780 vm_page_free_zero(m);
9794 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9795 VM_OBJECT_WLOCK(pti_obj);
9796 pml4_pg = pmap_pti_alloc_page();
9797 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9798 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9799 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9800 pdpe = pmap_pti_pdpe(va);
9801 pmap_pti_wire_pte(pdpe);
9803 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9804 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9805 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9806 sizeof(struct gate_descriptor) * NIDT, false);
9808 /* Doublefault stack IST 1 */
9809 va = __pcpu[i].pc_common_tss.tss_ist1;
9810 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9811 /* NMI stack IST 2 */
9812 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
9813 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9814 /* MC# stack IST 3 */
9815 va = __pcpu[i].pc_common_tss.tss_ist3 +
9816 sizeof(struct nmi_pcpu);
9817 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9818 /* DB# stack IST 4 */
9819 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
9820 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9822 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9823 (vm_offset_t)etext, true);
9824 pti_finalized = true;
9825 VM_OBJECT_WUNLOCK(pti_obj);
9827 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9829 static pdp_entry_t *
9830 pmap_pti_pdpe(vm_offset_t va)
9832 pml4_entry_t *pml4e;
9835 vm_pindex_t pml4_idx;
9838 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9840 pml4_idx = pmap_pml4e_index(va);
9841 pml4e = &pti_pml4[pml4_idx];
9845 panic("pml4 alloc after finalization\n");
9846 m = pmap_pti_alloc_page();
9848 pmap_pti_free_page(m);
9849 mphys = *pml4e & ~PAGE_MASK;
9851 mphys = VM_PAGE_TO_PHYS(m);
9852 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9855 mphys = *pml4e & ~PAGE_MASK;
9857 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9862 pmap_pti_wire_pte(void *pte)
9866 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9867 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9872 pmap_pti_unwire_pde(void *pde, bool only_ref)
9876 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9877 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9878 MPASS(m->ref_count > 0);
9879 MPASS(only_ref || m->ref_count > 1);
9880 pmap_pti_free_page(m);
9884 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9889 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9890 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9891 MPASS(m->ref_count > 0);
9892 if (pmap_pti_free_page(m)) {
9893 pde = pmap_pti_pde(va);
9894 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9896 pmap_pti_unwire_pde(pde, false);
9901 pmap_pti_pde(vm_offset_t va)
9909 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9911 pdpe = pmap_pti_pdpe(va);
9913 m = pmap_pti_alloc_page();
9915 pmap_pti_free_page(m);
9916 MPASS((*pdpe & X86_PG_PS) == 0);
9917 mphys = *pdpe & ~PAGE_MASK;
9919 mphys = VM_PAGE_TO_PHYS(m);
9920 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9923 MPASS((*pdpe & X86_PG_PS) == 0);
9924 mphys = *pdpe & ~PAGE_MASK;
9927 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9928 pd_idx = pmap_pde_index(va);
9934 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9941 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9943 pde = pmap_pti_pde(va);
9944 if (unwire_pde != NULL) {
9946 pmap_pti_wire_pte(pde);
9949 m = pmap_pti_alloc_page();
9951 pmap_pti_free_page(m);
9952 MPASS((*pde & X86_PG_PS) == 0);
9953 mphys = *pde & ~(PAGE_MASK | pg_nx);
9955 mphys = VM_PAGE_TO_PHYS(m);
9956 *pde = mphys | X86_PG_RW | X86_PG_V;
9957 if (unwire_pde != NULL)
9958 *unwire_pde = false;
9961 MPASS((*pde & X86_PG_PS) == 0);
9962 mphys = *pde & ~(PAGE_MASK | pg_nx);
9965 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9966 pte += pmap_pte_index(va);
9972 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9976 pt_entry_t *pte, ptev;
9979 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9981 sva = trunc_page(sva);
9982 MPASS(sva > VM_MAXUSER_ADDRESS);
9983 eva = round_page(eva);
9985 for (; sva < eva; sva += PAGE_SIZE) {
9986 pte = pmap_pti_pte(sva, &unwire_pde);
9987 pa = pmap_kextract(sva);
9988 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9989 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9990 VM_MEMATTR_DEFAULT, FALSE);
9992 pte_store(pte, ptev);
9993 pmap_pti_wire_pte(pte);
9995 KASSERT(!pti_finalized,
9996 ("pti overlap after fin %#lx %#lx %#lx",
9998 KASSERT(*pte == ptev,
9999 ("pti non-identical pte after fin %#lx %#lx %#lx",
10003 pde = pmap_pti_pde(sva);
10004 pmap_pti_unwire_pde(pde, true);
10010 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10015 VM_OBJECT_WLOCK(pti_obj);
10016 pmap_pti_add_kva_locked(sva, eva, exec);
10017 VM_OBJECT_WUNLOCK(pti_obj);
10021 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10028 sva = rounddown2(sva, PAGE_SIZE);
10029 MPASS(sva > VM_MAXUSER_ADDRESS);
10030 eva = roundup2(eva, PAGE_SIZE);
10032 VM_OBJECT_WLOCK(pti_obj);
10033 for (va = sva; va < eva; va += PAGE_SIZE) {
10034 pte = pmap_pti_pte(va, NULL);
10035 KASSERT((*pte & X86_PG_V) != 0,
10036 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10037 (u_long)pte, *pte));
10039 pmap_pti_unwire_pte(pte, va);
10041 pmap_invalidate_range(kernel_pmap, sva, eva);
10042 VM_OBJECT_WUNLOCK(pti_obj);
10046 pkru_dup_range(void *ctx __unused, void *data)
10048 struct pmap_pkru_range *node, *new_node;
10050 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10051 if (new_node == NULL)
10054 memcpy(new_node, node, sizeof(*node));
10059 pkru_free_range(void *ctx __unused, void *node)
10062 uma_zfree(pmap_pkru_ranges_zone, node);
10066 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10069 struct pmap_pkru_range *ppr;
10072 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10073 MPASS(pmap->pm_type == PT_X86);
10074 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10075 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10076 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10078 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10081 ppr->pkru_keyidx = keyidx;
10082 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10083 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10085 uma_zfree(pmap_pkru_ranges_zone, ppr);
10090 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10093 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10094 MPASS(pmap->pm_type == PT_X86);
10095 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10096 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10100 pmap_pkru_deassign_all(pmap_t pmap)
10103 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10104 if (pmap->pm_type == PT_X86 &&
10105 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10106 rangeset_remove_all(&pmap->pm_pkru);
10110 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10112 struct pmap_pkru_range *ppr, *prev_ppr;
10115 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10116 if (pmap->pm_type != PT_X86 ||
10117 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10118 sva >= VM_MAXUSER_ADDRESS)
10120 MPASS(eva <= VM_MAXUSER_ADDRESS);
10121 for (va = sva, prev_ppr = NULL; va < eva;) {
10122 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10123 if ((ppr == NULL) ^ (prev_ppr == NULL))
10129 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10131 va = ppr->pkru_rs_el.re_end;
10137 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10139 struct pmap_pkru_range *ppr;
10141 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10142 if (pmap->pm_type != PT_X86 ||
10143 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10144 va >= VM_MAXUSER_ADDRESS)
10146 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10148 return (X86_PG_PKU(ppr->pkru_keyidx));
10153 pred_pkru_on_remove(void *ctx __unused, void *r)
10155 struct pmap_pkru_range *ppr;
10158 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10162 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10165 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10166 if (pmap->pm_type == PT_X86 &&
10167 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10168 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10169 pred_pkru_on_remove);
10174 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10177 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10178 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10179 MPASS(dst_pmap->pm_type == PT_X86);
10180 MPASS(src_pmap->pm_type == PT_X86);
10181 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10182 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10184 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10188 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10191 pml4_entry_t *pml4e;
10193 pd_entry_t newpde, ptpaddr, *pde;
10194 pt_entry_t newpte, *ptep, pte;
10195 vm_offset_t va, va_next;
10198 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10199 MPASS(pmap->pm_type == PT_X86);
10200 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10202 for (changed = false, va = sva; va < eva; va = va_next) {
10203 pml4e = pmap_pml4e(pmap, va);
10204 if ((*pml4e & X86_PG_V) == 0) {
10205 va_next = (va + NBPML4) & ~PML4MASK;
10211 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10212 if ((*pdpe & X86_PG_V) == 0) {
10213 va_next = (va + NBPDP) & ~PDPMASK;
10219 va_next = (va + NBPDR) & ~PDRMASK;
10223 pde = pmap_pdpe_to_pde(pdpe, va);
10228 MPASS((ptpaddr & X86_PG_V) != 0);
10229 if ((ptpaddr & PG_PS) != 0) {
10230 if (va + NBPDR == va_next && eva >= va_next) {
10231 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10232 X86_PG_PKU(keyidx);
10233 if (newpde != ptpaddr) {
10238 } else if (!pmap_demote_pde(pmap, pde, va)) {
10246 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10247 ptep++, va += PAGE_SIZE) {
10249 if ((pte & X86_PG_V) == 0)
10251 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10252 if (newpte != pte) {
10259 pmap_invalidate_range(pmap, sva, eva);
10263 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10264 u_int keyidx, int flags)
10267 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10268 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10270 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10272 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10278 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10283 sva = trunc_page(sva);
10284 eva = round_page(eva);
10285 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10290 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10292 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10294 if (error != ENOMEM)
10302 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10306 sva = trunc_page(sva);
10307 eva = round_page(eva);
10308 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10313 error = pmap_pkru_deassign(pmap, sva, eva);
10315 pmap_pkru_update_range(pmap, sva, eva, 0);
10317 if (error != ENOMEM)
10325 * Track a range of the kernel's virtual address space that is contiguous
10326 * in various mapping attributes.
10328 struct pmap_kernel_map_range {
10337 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10343 if (eva <= range->sva)
10346 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10347 for (i = 0; i < PAT_INDEX_SIZE; i++)
10348 if (pat_index[i] == pat_idx)
10352 case PAT_WRITE_BACK:
10355 case PAT_WRITE_THROUGH:
10358 case PAT_UNCACHEABLE:
10364 case PAT_WRITE_PROTECTED:
10367 case PAT_WRITE_COMBINING:
10371 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10372 __func__, pat_idx, range->sva, eva);
10377 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10379 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10380 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10381 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10382 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10383 mode, range->pdpes, range->pdes, range->ptes);
10385 /* Reset to sentinel value. */
10386 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10390 * Determine whether the attributes specified by a page table entry match those
10391 * being tracked by the current range. This is not quite as simple as a direct
10392 * flag comparison since some PAT modes have multiple representations.
10395 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10397 pt_entry_t diff, mask;
10399 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10400 diff = (range->attrs ^ attrs) & mask;
10403 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10404 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10405 pmap_pat_index(kernel_pmap, attrs, true))
10411 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10415 memset(range, 0, sizeof(*range));
10417 range->attrs = attrs;
10421 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10422 * those of the current run, dump the address range and its attributes, and
10426 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10427 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10432 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10434 attrs |= pdpe & pg_nx;
10435 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10436 if ((pdpe & PG_PS) != 0) {
10437 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10438 } else if (pde != 0) {
10439 attrs |= pde & pg_nx;
10440 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10442 if ((pde & PG_PS) != 0) {
10443 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10444 } else if (pte != 0) {
10445 attrs |= pte & pg_nx;
10446 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10447 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10449 /* Canonicalize by always using the PDE PAT bit. */
10450 if ((attrs & X86_PG_PTE_PAT) != 0)
10451 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10454 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10455 sysctl_kmaps_dump(sb, range, va);
10456 sysctl_kmaps_reinit(range, va, attrs);
10461 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10463 struct pmap_kernel_map_range range;
10464 struct sbuf sbuf, *sb;
10465 pml4_entry_t pml4e;
10466 pdp_entry_t *pdp, pdpe;
10467 pd_entry_t *pd, pde;
10468 pt_entry_t *pt, pte;
10471 int error, i, j, k, l;
10473 error = sysctl_wire_old_buffer(req, 0);
10477 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10479 /* Sentinel value. */
10480 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10483 * Iterate over the kernel page tables without holding the kernel pmap
10484 * lock. Outside of the large map, kernel page table pages are never
10485 * freed, so at worst we will observe inconsistencies in the output.
10486 * Within the large map, ensure that PDP and PD page addresses are
10487 * valid before descending.
10489 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10492 sbuf_printf(sb, "\nRecursive map:\n");
10495 sbuf_printf(sb, "\nDirect map:\n");
10498 sbuf_printf(sb, "\nKernel map:\n");
10501 sbuf_printf(sb, "\nLarge map:\n");
10505 /* Convert to canonical form. */
10506 if (sva == 1ul << 47)
10510 pml4e = kernel_pmap->pm_pml4[i];
10511 if ((pml4e & X86_PG_V) == 0) {
10512 sva = rounddown2(sva, NBPML4);
10513 sysctl_kmaps_dump(sb, &range, sva);
10517 pa = pml4e & PG_FRAME;
10518 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10520 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10522 if ((pdpe & X86_PG_V) == 0) {
10523 sva = rounddown2(sva, NBPDP);
10524 sysctl_kmaps_dump(sb, &range, sva);
10528 pa = pdpe & PG_FRAME;
10529 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10530 vm_phys_paddr_to_vm_page(pa) == NULL)
10532 if ((pdpe & PG_PS) != 0) {
10533 sva = rounddown2(sva, NBPDP);
10534 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10540 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10542 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10544 if ((pde & X86_PG_V) == 0) {
10545 sva = rounddown2(sva, NBPDR);
10546 sysctl_kmaps_dump(sb, &range, sva);
10550 pa = pde & PG_FRAME;
10551 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10552 vm_phys_paddr_to_vm_page(pa) == NULL)
10554 if ((pde & PG_PS) != 0) {
10555 sva = rounddown2(sva, NBPDR);
10556 sysctl_kmaps_check(sb, &range, sva,
10557 pml4e, pdpe, pde, 0);
10562 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10564 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10565 sva += PAGE_SIZE) {
10567 if ((pte & X86_PG_V) == 0) {
10568 sysctl_kmaps_dump(sb, &range,
10572 sysctl_kmaps_check(sb, &range, sva,
10573 pml4e, pdpe, pde, pte);
10580 error = sbuf_finish(sb);
10584 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10585 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10586 NULL, 0, sysctl_kmaps, "A",
10587 "Dump kernel address layout");
10590 DB_SHOW_COMMAND(pte, pmap_print_pte)
10593 pml4_entry_t *pml4;
10596 pt_entry_t *pte, PG_V;
10600 db_printf("show pte addr\n");
10603 va = (vm_offset_t)addr;
10605 if (kdb_thread != NULL)
10606 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10608 pmap = PCPU_GET(curpmap);
10610 PG_V = pmap_valid_bit(pmap);
10611 pml4 = pmap_pml4e(pmap, va);
10612 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10613 if ((*pml4 & PG_V) == 0) {
10617 pdp = pmap_pml4e_to_pdpe(pml4, va);
10618 db_printf(" pdpe 0x%016lx", *pdp);
10619 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10623 pde = pmap_pdpe_to_pde(pdp, va);
10624 db_printf(" pde 0x%016lx", *pde);
10625 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10629 pte = pmap_pde_to_pte(pde, va);
10630 db_printf(" pte 0x%016lx\n", *pte);
10633 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10638 a = (vm_paddr_t)addr;
10639 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10641 db_printf("show phys2dmap addr\n");