2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rangeset.h>
125 #include <sys/rwlock.h>
127 #include <sys/turnstile.h>
128 #include <sys/vmem.h>
129 #include <sys/vmmeter.h>
130 #include <sys/sched.h>
131 #include <sys/sysctl.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
150 #include <x86/ifunc.h>
151 #include <machine/cpu.h>
152 #include <machine/cputypes.h>
153 #include <machine/md_var.h>
154 #include <machine/pcb.h>
155 #include <machine/specialreg.h>
157 #include <machine/smp.h>
159 #include <machine/sysarch.h>
160 #include <machine/tss.h>
162 static __inline boolean_t
163 pmap_type_guest(pmap_t pmap)
166 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
169 static __inline boolean_t
170 pmap_emulate_ad_bits(pmap_t pmap)
173 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
176 static __inline pt_entry_t
177 pmap_valid_bit(pmap_t pmap)
181 switch (pmap->pm_type) {
187 if (pmap_emulate_ad_bits(pmap))
188 mask = EPT_PG_EMUL_V;
193 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
199 static __inline pt_entry_t
200 pmap_rw_bit(pmap_t pmap)
204 switch (pmap->pm_type) {
210 if (pmap_emulate_ad_bits(pmap))
211 mask = EPT_PG_EMUL_RW;
216 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
222 static pt_entry_t pg_g;
224 static __inline pt_entry_t
225 pmap_global_bit(pmap_t pmap)
229 switch (pmap->pm_type) {
238 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
244 static __inline pt_entry_t
245 pmap_accessed_bit(pmap_t pmap)
249 switch (pmap->pm_type) {
255 if (pmap_emulate_ad_bits(pmap))
261 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
267 static __inline pt_entry_t
268 pmap_modified_bit(pmap_t pmap)
272 switch (pmap->pm_type) {
278 if (pmap_emulate_ad_bits(pmap))
284 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
290 static __inline pt_entry_t
291 pmap_pku_mask_bit(pmap_t pmap)
294 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
297 #if !defined(DIAGNOSTIC)
298 #ifdef __GNUC_GNU_INLINE__
299 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
301 #define PMAP_INLINE extern inline
308 #define PV_STAT(x) do { x ; } while (0)
310 #define PV_STAT(x) do { } while (0)
313 #define pa_index(pa) ((pa) >> PDRSHIFT)
314 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
316 #define NPV_LIST_LOCKS MAXCPU
318 #define PHYS_TO_PV_LIST_LOCK(pa) \
319 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
321 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
322 struct rwlock **_lockp = (lockp); \
323 struct rwlock *_new_lock; \
325 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
326 if (_new_lock != *_lockp) { \
327 if (*_lockp != NULL) \
328 rw_wunlock(*_lockp); \
329 *_lockp = _new_lock; \
334 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
335 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
337 #define RELEASE_PV_LIST_LOCK(lockp) do { \
338 struct rwlock **_lockp = (lockp); \
340 if (*_lockp != NULL) { \
341 rw_wunlock(*_lockp); \
346 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
347 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
349 struct pmap kernel_pmap_store;
351 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
352 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
355 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
356 "Number of kernel page table pages allocated on bootup");
359 vm_paddr_t dmaplimit;
360 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
363 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
365 static int pg_ps_enabled = 1;
366 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
367 &pg_ps_enabled, 0, "Are large page mappings enabled?");
369 #define PAT_INDEX_SIZE 8
370 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
372 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
373 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
374 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
375 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
377 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
378 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
379 static int ndmpdpphys; /* number of DMPDPphys pages */
381 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
384 * pmap_mapdev support pre initialization (i.e. console)
386 #define PMAP_PREINIT_MAPPING_COUNT 8
387 static struct pmap_preinit_mapping {
392 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
393 static int pmap_initialized;
396 * Data for the pv entry allocation mechanism.
397 * Updates to pv_invl_gen are protected by the pv_list_locks[]
398 * elements, but reads are not.
400 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
401 static struct mtx __exclusive_cache_line pv_chunks_mutex;
402 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
403 static u_long pv_invl_gen[NPV_LIST_LOCKS];
404 static struct md_page *pv_table;
405 static struct md_page pv_dummy;
408 * All those kernel PT submaps that BSD is so fond of
410 pt_entry_t *CMAP1 = NULL;
412 static vm_offset_t qframe = 0;
413 static struct mtx qframe_mtx;
415 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
417 static vmem_t *large_vmem;
418 static u_int lm_ents;
420 int pmap_pcid_enabled = 1;
421 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
422 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
423 int invpcid_works = 0;
424 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
425 "Is the invpcid instruction available ?");
427 int __read_frequently pti = 0;
428 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
430 "Page Table Isolation enabled");
431 static vm_object_t pti_obj;
432 static pml4_entry_t *pti_pml4;
433 static vm_pindex_t pti_pg_idx;
434 static bool pti_finalized;
436 struct pmap_pkru_range {
437 struct rs_el pkru_rs_el;
442 static uma_zone_t pmap_pkru_ranges_zone;
443 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
444 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
445 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
446 static void *pkru_dup_range(void *ctx, void *data);
447 static void pkru_free_range(void *ctx, void *node);
448 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
449 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
450 static void pmap_pkru_deassign_all(pmap_t pmap);
453 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
460 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
462 return (sysctl_handle_64(oidp, &res, 0, req));
464 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
465 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
466 "Count of saved TLB context on switch");
468 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
469 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
470 static struct mtx invl_gen_mtx;
471 static u_long pmap_invl_gen = 0;
472 /* Fake lock object to satisfy turnstiles interface. */
473 static struct lock_object invl_gen_ts = {
481 return (curthread->td_md.md_invl_gen.gen == 0);
484 #define PMAP_ASSERT_NOT_IN_DI() \
485 KASSERT(pmap_not_in_di(), ("DI already started"))
488 * Start a new Delayed Invalidation (DI) block of code, executed by
489 * the current thread. Within a DI block, the current thread may
490 * destroy both the page table and PV list entries for a mapping and
491 * then release the corresponding PV list lock before ensuring that
492 * the mapping is flushed from the TLBs of any processors with the
496 pmap_delayed_invl_started(void)
498 struct pmap_invl_gen *invl_gen;
501 invl_gen = &curthread->td_md.md_invl_gen;
502 PMAP_ASSERT_NOT_IN_DI();
503 mtx_lock(&invl_gen_mtx);
504 if (LIST_EMPTY(&pmap_invl_gen_tracker))
505 currgen = pmap_invl_gen;
507 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
508 invl_gen->gen = currgen + 1;
509 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
510 mtx_unlock(&invl_gen_mtx);
514 * Finish the DI block, previously started by the current thread. All
515 * required TLB flushes for the pages marked by
516 * pmap_delayed_invl_page() must be finished before this function is
519 * This function works by bumping the global DI generation number to
520 * the generation number of the current thread's DI, unless there is a
521 * pending DI that started earlier. In the latter case, bumping the
522 * global DI generation number would incorrectly signal that the
523 * earlier DI had finished. Instead, this function bumps the earlier
524 * DI's generation number to match the generation number of the
525 * current thread's DI.
528 pmap_delayed_invl_finished(void)
530 struct pmap_invl_gen *invl_gen, *next;
531 struct turnstile *ts;
533 invl_gen = &curthread->td_md.md_invl_gen;
534 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
535 mtx_lock(&invl_gen_mtx);
536 next = LIST_NEXT(invl_gen, link);
538 turnstile_chain_lock(&invl_gen_ts);
539 ts = turnstile_lookup(&invl_gen_ts);
540 pmap_invl_gen = invl_gen->gen;
542 turnstile_broadcast(ts, TS_SHARED_QUEUE);
543 turnstile_unpend(ts);
545 turnstile_chain_unlock(&invl_gen_ts);
547 next->gen = invl_gen->gen;
549 LIST_REMOVE(invl_gen, link);
550 mtx_unlock(&invl_gen_mtx);
555 static long invl_wait;
556 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
557 "Number of times DI invalidation blocked pmap_remove_all/write");
561 pmap_delayed_invl_genp(vm_page_t m)
564 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
568 * Ensure that all currently executing DI blocks, that need to flush
569 * TLB for the given page m, actually flushed the TLB at the time the
570 * function returned. If the page m has an empty PV list and we call
571 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
572 * valid mapping for the page m in either its page table or TLB.
574 * This function works by blocking until the global DI generation
575 * number catches up with the generation number associated with the
576 * given page m and its PV list. Since this function's callers
577 * typically own an object lock and sometimes own a page lock, it
578 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
582 pmap_delayed_invl_wait(vm_page_t m)
584 struct turnstile *ts;
587 bool accounted = false;
590 m_gen = pmap_delayed_invl_genp(m);
591 while (*m_gen > pmap_invl_gen) {
594 atomic_add_long(&invl_wait, 1);
598 ts = turnstile_trywait(&invl_gen_ts);
599 if (*m_gen > pmap_invl_gen)
600 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
602 turnstile_cancel(ts);
607 * Mark the page m's PV list as participating in the current thread's
608 * DI block. Any threads concurrently using m's PV list to remove or
609 * restrict all mappings to m will wait for the current thread's DI
610 * block to complete before proceeding.
612 * The function works by setting the DI generation number for m's PV
613 * list to at least the DI generation number of the current thread.
614 * This forces a caller of pmap_delayed_invl_wait() to block until
615 * current thread calls pmap_delayed_invl_finished().
618 pmap_delayed_invl_page(vm_page_t m)
622 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
623 gen = curthread->td_md.md_invl_gen.gen;
626 m_gen = pmap_delayed_invl_genp(m);
634 static caddr_t crashdumpmap;
637 * Internal flags for pmap_enter()'s helper functions.
639 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
640 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
642 static void free_pv_chunk(struct pv_chunk *pc);
643 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
644 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
645 static int popcnt_pc_map_pq(uint64_t *map);
646 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
647 static void reserve_pv_entries(pmap_t pmap, int needed,
648 struct rwlock **lockp);
649 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
650 struct rwlock **lockp);
651 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
652 u_int flags, struct rwlock **lockp);
653 #if VM_NRESERVLEVEL > 0
654 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
655 struct rwlock **lockp);
657 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
658 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
661 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
663 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
664 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
665 vm_offset_t va, struct rwlock **lockp);
666 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
668 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
669 vm_prot_t prot, struct rwlock **lockp);
670 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
671 u_int flags, vm_page_t m, struct rwlock **lockp);
672 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
673 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
674 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
675 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
676 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
678 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
680 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
682 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
683 static vm_page_t pmap_large_map_getptp_unlocked(void);
684 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
685 #if VM_NRESERVLEVEL > 0
686 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
687 struct rwlock **lockp);
689 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
691 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
692 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
694 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
695 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
696 static void pmap_pti_wire_pte(void *pte);
697 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
698 struct spglist *free, struct rwlock **lockp);
699 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
700 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
701 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
702 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
703 struct spglist *free);
704 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
705 pd_entry_t *pde, struct spglist *free,
706 struct rwlock **lockp);
707 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
708 vm_page_t m, struct rwlock **lockp);
709 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
711 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
713 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
714 struct rwlock **lockp);
715 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
716 struct rwlock **lockp);
717 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
718 struct rwlock **lockp);
720 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
721 struct spglist *free);
722 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
724 /********************/
725 /* Inline functions */
726 /********************/
728 /* Return a non-clipped PD index for a given VA */
729 static __inline vm_pindex_t
730 pmap_pde_pindex(vm_offset_t va)
732 return (va >> PDRSHIFT);
736 /* Return a pointer to the PML4 slot that corresponds to a VA */
737 static __inline pml4_entry_t *
738 pmap_pml4e(pmap_t pmap, vm_offset_t va)
741 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
744 /* Return a pointer to the PDP slot that corresponds to a VA */
745 static __inline pdp_entry_t *
746 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
750 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
751 return (&pdpe[pmap_pdpe_index(va)]);
754 /* Return a pointer to the PDP slot that corresponds to a VA */
755 static __inline pdp_entry_t *
756 pmap_pdpe(pmap_t pmap, vm_offset_t va)
761 PG_V = pmap_valid_bit(pmap);
762 pml4e = pmap_pml4e(pmap, va);
763 if ((*pml4e & PG_V) == 0)
765 return (pmap_pml4e_to_pdpe(pml4e, va));
768 /* Return a pointer to the PD slot that corresponds to a VA */
769 static __inline pd_entry_t *
770 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
774 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
775 return (&pde[pmap_pde_index(va)]);
778 /* Return a pointer to the PD slot that corresponds to a VA */
779 static __inline pd_entry_t *
780 pmap_pde(pmap_t pmap, vm_offset_t va)
785 PG_V = pmap_valid_bit(pmap);
786 pdpe = pmap_pdpe(pmap, va);
787 if (pdpe == NULL || (*pdpe & PG_V) == 0)
789 return (pmap_pdpe_to_pde(pdpe, va));
792 /* Return a pointer to the PT slot that corresponds to a VA */
793 static __inline pt_entry_t *
794 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
798 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
799 return (&pte[pmap_pte_index(va)]);
802 /* Return a pointer to the PT slot that corresponds to a VA */
803 static __inline pt_entry_t *
804 pmap_pte(pmap_t pmap, vm_offset_t va)
809 PG_V = pmap_valid_bit(pmap);
810 pde = pmap_pde(pmap, va);
811 if (pde == NULL || (*pde & PG_V) == 0)
813 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
814 return ((pt_entry_t *)pde);
815 return (pmap_pde_to_pte(pde, va));
819 pmap_resident_count_inc(pmap_t pmap, int count)
822 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
823 pmap->pm_stats.resident_count += count;
827 pmap_resident_count_dec(pmap_t pmap, int count)
830 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
831 KASSERT(pmap->pm_stats.resident_count >= count,
832 ("pmap %p resident count underflow %ld %d", pmap,
833 pmap->pm_stats.resident_count, count));
834 pmap->pm_stats.resident_count -= count;
837 PMAP_INLINE pt_entry_t *
838 vtopte(vm_offset_t va)
840 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
842 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
844 return (PTmap + ((va >> PAGE_SHIFT) & mask));
847 static __inline pd_entry_t *
848 vtopde(vm_offset_t va)
850 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
852 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
854 return (PDmap + ((va >> PDRSHIFT) & mask));
858 allocpages(vm_paddr_t *firstaddr, int n)
863 bzero((void *)ret, n * PAGE_SIZE);
864 *firstaddr += n * PAGE_SIZE;
868 CTASSERT(powerof2(NDMPML4E));
870 /* number of kernel PDP slots */
871 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
874 nkpt_init(vm_paddr_t addr)
881 pt_pages = howmany(addr, 1 << PDRSHIFT);
882 pt_pages += NKPDPE(pt_pages);
885 * Add some slop beyond the bare minimum required for bootstrapping
888 * This is quite important when allocating KVA for kernel modules.
889 * The modules are required to be linked in the negative 2GB of
890 * the address space. If we run out of KVA in this region then
891 * pmap_growkernel() will need to allocate page table pages to map
892 * the entire 512GB of KVA space which is an unnecessary tax on
895 * Secondly, device memory mapped as part of setting up the low-
896 * level console(s) is taken from KVA, starting at virtual_avail.
897 * This is because cninit() is called after pmap_bootstrap() but
898 * before vm_init() and pmap_init(). 20MB for a frame buffer is
901 pt_pages += 32; /* 64MB additional slop. */
907 * Returns the proper write/execute permission for a physical page that is
908 * part of the initial boot allocations.
910 * If the page has kernel text, it is marked as read-only. If the page has
911 * kernel read-only data, it is marked as read-only/not-executable. If the
912 * page has only read-write data, it is marked as read-write/not-executable.
913 * If the page is below/above the kernel range, it is marked as read-write.
915 * This function operates on 2M pages, since we map the kernel space that
918 * Note that this doesn't currently provide any protection for modules.
920 static inline pt_entry_t
921 bootaddr_rwx(vm_paddr_t pa)
925 * Everything in the same 2M page as the start of the kernel
926 * should be static. On the other hand, things in the same 2M
927 * page as the end of the kernel could be read-write/executable,
928 * as the kernel image is not guaranteed to end on a 2M boundary.
930 if (pa < trunc_2mpage(btext - KERNBASE) ||
931 pa >= trunc_2mpage(_end - KERNBASE))
934 * The linker should ensure that the read-only and read-write
935 * portions don't share the same 2M page, so this shouldn't
936 * impact read-only data. However, in any case, any page with
937 * read-write data needs to be read-write.
939 if (pa >= trunc_2mpage(brwsection - KERNBASE))
940 return (X86_PG_RW | pg_nx);
942 * Mark any 2M page containing kernel text as read-only. Mark
943 * other pages with read-only data as read-only and not executable.
944 * (It is likely a small portion of the read-only data section will
945 * be marked as read-only, but executable. This should be acceptable
946 * since the read-only protection will keep the data from changing.)
947 * Note that fixups to the .text section will still work until we
950 if (pa < round_2mpage(etext - KERNBASE))
956 create_pagetables(vm_paddr_t *firstaddr)
958 int i, j, ndm1g, nkpdpe, nkdmpde;
963 uint64_t DMPDkernphys;
965 /* Allocate page table pages for the direct map */
966 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
967 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
969 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
970 if (ndmpdpphys > NDMPML4E) {
972 * Each NDMPML4E allows 512 GB, so limit to that,
973 * and then readjust ndmpdp and ndmpdpphys.
975 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
976 Maxmem = atop(NDMPML4E * NBPML4);
977 ndmpdpphys = NDMPML4E;
978 ndmpdp = NDMPML4E * NPDEPG;
980 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
982 if ((amd_feature & AMDID_PAGE1GB) != 0) {
984 * Calculate the number of 1G pages that will fully fit in
987 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
990 * Allocate 2M pages for the kernel. These will be used in
991 * place of the first one or more 1G pages from ndm1g.
993 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
994 DMPDkernphys = allocpages(firstaddr, nkdmpde);
997 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
998 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1000 /* Allocate pages */
1001 KPML4phys = allocpages(firstaddr, 1);
1002 KPDPphys = allocpages(firstaddr, NKPML4E);
1005 * Allocate the initial number of kernel page table pages required to
1006 * bootstrap. We defer this until after all memory-size dependent
1007 * allocations are done (e.g. direct map), so that we don't have to
1008 * build in too much slop in our estimate.
1010 * Note that when NKPML4E > 1, we have an empty page underneath
1011 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1012 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1014 nkpt_init(*firstaddr);
1015 nkpdpe = NKPDPE(nkpt);
1017 KPTphys = allocpages(firstaddr, nkpt);
1018 KPDphys = allocpages(firstaddr, nkpdpe);
1020 /* Fill in the underlying page table pages */
1021 /* XXX not fully used, underneath 2M pages */
1022 pt_p = (pt_entry_t *)KPTphys;
1023 for (i = 0; ptoa(i) < *firstaddr; i++)
1024 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
1026 /* Now map the page tables at their location within PTmap */
1027 pd_p = (pd_entry_t *)KPDphys;
1028 for (i = 0; i < nkpt; i++)
1029 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1031 /* Map from zero to end of allocations under 2M pages */
1032 /* This replaces some of the KPTphys entries above */
1033 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1034 /* Preset PG_M and PG_A because demotion expects it. */
1035 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1036 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1039 * Because we map the physical blocks in 2M pages, adjust firstaddr
1040 * to record the physical blocks we've actually mapped into kernel
1041 * virtual address space.
1043 *firstaddr = round_2mpage(*firstaddr);
1045 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1046 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1047 for (i = 0; i < nkpdpe; i++)
1048 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1051 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1052 * the end of physical memory is not aligned to a 1GB page boundary,
1053 * then the residual physical memory is mapped with 2MB pages. Later,
1054 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1055 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1056 * that are partially used.
1058 pd_p = (pd_entry_t *)DMPDphys;
1059 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1060 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1061 /* Preset PG_M and PG_A because demotion expects it. */
1062 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1063 X86_PG_M | X86_PG_A | pg_nx;
1065 pdp_p = (pdp_entry_t *)DMPDPphys;
1066 for (i = 0; i < ndm1g; i++) {
1067 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1068 /* Preset PG_M and PG_A because demotion expects it. */
1069 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1070 X86_PG_M | X86_PG_A | pg_nx;
1072 for (j = 0; i < ndmpdp; i++, j++) {
1073 pdp_p[i] = DMPDphys + ptoa(j);
1074 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1078 * Instead of using a 1G page for the memory containing the kernel,
1079 * use 2M pages with appropriate permissions. (If using 1G pages,
1080 * this will partially overwrite the PDPEs above.)
1083 pd_p = (pd_entry_t *)DMPDkernphys;
1084 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1085 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1086 X86_PG_M | X86_PG_A | pg_nx |
1087 bootaddr_rwx(i << PDRSHIFT);
1088 for (i = 0; i < nkdmpde; i++)
1089 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1093 /* And recursively map PML4 to itself in order to get PTmap */
1094 p4_p = (pml4_entry_t *)KPML4phys;
1095 p4_p[PML4PML4I] = KPML4phys;
1096 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1098 /* Connect the Direct Map slot(s) up to the PML4. */
1099 for (i = 0; i < ndmpdpphys; i++) {
1100 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1101 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1104 /* Connect the KVA slots up to the PML4 */
1105 for (i = 0; i < NKPML4E; i++) {
1106 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1107 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1112 * Bootstrap the system enough to run with virtual memory.
1114 * On amd64 this is called after mapping has already been enabled
1115 * and just syncs the pmap module with what has already been done.
1116 * [We can't call it easily with mapping off since the kernel is not
1117 * mapped with PA == VA, hence we would have to relocate every address
1118 * from the linked base (virtual) address "KERNBASE" to the actual
1119 * (physical) address starting relative to 0]
1122 pmap_bootstrap(vm_paddr_t *firstaddr)
1130 KERNend = *firstaddr;
1131 res = atop(KERNend - (vm_paddr_t)kernphys);
1137 * Create an initial set of page tables to run the kernel in.
1139 create_pagetables(firstaddr);
1142 * Add a physical memory segment (vm_phys_seg) corresponding to the
1143 * preallocated kernel page table pages so that vm_page structures
1144 * representing these pages will be created. The vm_page structures
1145 * are required for promotion of the corresponding kernel virtual
1146 * addresses to superpage mappings.
1148 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1150 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1151 virtual_end = VM_MAX_KERNEL_ADDRESS;
1154 * Enable PG_G global pages, then switch to the kernel page
1155 * table from the bootstrap page table. After the switch, it
1156 * is possible to enable SMEP and SMAP since PG_U bits are
1162 load_cr3(KPML4phys);
1163 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1165 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1170 * Initialize the kernel pmap (which is statically allocated).
1171 * Count bootstrap data as being resident in case any of this data is
1172 * later unmapped (using pmap_remove()) and freed.
1174 PMAP_LOCK_INIT(kernel_pmap);
1175 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1176 kernel_pmap->pm_cr3 = KPML4phys;
1177 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1178 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1179 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1180 kernel_pmap->pm_stats.resident_count = res;
1181 kernel_pmap->pm_flags = pmap_flags;
1184 * Initialize the TLB invalidations generation number lock.
1186 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1189 * Reserve some special page table entries/VA space for temporary
1192 #define SYSMAP(c, p, v, n) \
1193 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1199 * Crashdump maps. The first page is reused as CMAP1 for the
1202 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1203 CADDR1 = crashdumpmap;
1208 * Initialize the PAT MSR.
1209 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1210 * side-effect, invalidates stale PG_G TLB entries that might
1211 * have been created in our pre-boot environment.
1215 /* Initialize TLB Context Id. */
1216 if (pmap_pcid_enabled) {
1217 for (i = 0; i < MAXCPU; i++) {
1218 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1219 kernel_pmap->pm_pcids[i].pm_gen = 1;
1223 * PMAP_PCID_KERN + 1 is used for initialization of
1224 * proc0 pmap. The pmap' pcid state might be used by
1225 * EFIRT entry before first context switch, so it
1226 * needs to be valid.
1228 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1229 PCPU_SET(pcid_gen, 1);
1232 * pcpu area for APs is zeroed during AP startup.
1233 * pc_pcid_next and pc_pcid_gen are initialized by AP
1234 * during pcpu setup.
1236 load_cr4(rcr4() | CR4_PCIDE);
1241 * Setup the PAT MSR.
1250 /* Bail if this CPU doesn't implement PAT. */
1251 if ((cpu_feature & CPUID_PAT) == 0)
1254 /* Set default PAT index table. */
1255 for (i = 0; i < PAT_INDEX_SIZE; i++)
1257 pat_index[PAT_WRITE_BACK] = 0;
1258 pat_index[PAT_WRITE_THROUGH] = 1;
1259 pat_index[PAT_UNCACHEABLE] = 3;
1260 pat_index[PAT_WRITE_COMBINING] = 6;
1261 pat_index[PAT_WRITE_PROTECTED] = 5;
1262 pat_index[PAT_UNCACHED] = 2;
1265 * Initialize default PAT entries.
1266 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1267 * Program 5 and 6 as WP and WC.
1269 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1270 * mapping for a 2M page uses a PAT value with the bit 3 set due
1271 * to its overload with PG_PS.
1273 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1274 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1275 PAT_VALUE(2, PAT_UNCACHED) |
1276 PAT_VALUE(3, PAT_UNCACHEABLE) |
1277 PAT_VALUE(4, PAT_WRITE_BACK) |
1278 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1279 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1280 PAT_VALUE(7, PAT_UNCACHEABLE);
1284 load_cr4(cr4 & ~CR4_PGE);
1286 /* Disable caches (CD = 1, NW = 0). */
1288 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1290 /* Flushes caches and TLBs. */
1294 /* Update PAT and index table. */
1295 wrmsr(MSR_PAT, pat_msr);
1297 /* Flush caches and TLBs again. */
1301 /* Restore caches and PGE. */
1307 * Initialize a vm_page's machine-dependent fields.
1310 pmap_page_init(vm_page_t m)
1313 TAILQ_INIT(&m->md.pv_list);
1314 m->md.pat_mode = PAT_WRITE_BACK;
1318 * Initialize the pmap module.
1319 * Called by vm_init, to initialize any structures that the pmap
1320 * system needs to map virtual memory.
1325 struct pmap_preinit_mapping *ppim;
1328 int error, i, pv_npg, ret, skz63;
1330 /* L1TF, reserve page @0 unconditionally */
1331 vm_page_blacklist_add(0, bootverbose);
1333 /* Detect bare-metal Skylake Server and Skylake-X. */
1334 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1335 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1337 * Skylake-X errata SKZ63. Processor May Hang When
1338 * Executing Code In an HLE Transaction Region between
1339 * 40000000H and 403FFFFFH.
1341 * Mark the pages in the range as preallocated. It
1342 * seems to be impossible to distinguish between
1343 * Skylake Server and Skylake X.
1346 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1349 printf("SKZ63: skipping 4M RAM starting "
1350 "at physical 1G\n");
1351 for (i = 0; i < atop(0x400000); i++) {
1352 ret = vm_page_blacklist_add(0x40000000 +
1354 if (!ret && bootverbose)
1355 printf("page at %#lx already used\n",
1356 0x40000000 + ptoa(i));
1362 * Initialize the vm page array entries for the kernel pmap's
1365 PMAP_LOCK(kernel_pmap);
1366 for (i = 0; i < nkpt; i++) {
1367 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1368 KASSERT(mpte >= vm_page_array &&
1369 mpte < &vm_page_array[vm_page_array_size],
1370 ("pmap_init: page table page is out of range"));
1371 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1372 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1373 mpte->wire_count = 1;
1374 if (i << PDRSHIFT < KERNend &&
1375 pmap_insert_pt_page(kernel_pmap, mpte))
1376 panic("pmap_init: pmap_insert_pt_page failed");
1378 PMAP_UNLOCK(kernel_pmap);
1382 * If the kernel is running on a virtual machine, then it must assume
1383 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1384 * be prepared for the hypervisor changing the vendor and family that
1385 * are reported by CPUID. Consequently, the workaround for AMD Family
1386 * 10h Erratum 383 is enabled if the processor's feature set does not
1387 * include at least one feature that is only supported by older Intel
1388 * or newer AMD processors.
1390 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1391 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1392 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1394 workaround_erratum383 = 1;
1397 * Are large page mappings enabled?
1399 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1400 if (pg_ps_enabled) {
1401 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1402 ("pmap_init: can't assign to pagesizes[1]"));
1403 pagesizes[1] = NBPDR;
1407 * Initialize the pv chunk list mutex.
1409 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1412 * Initialize the pool of pv list locks.
1414 for (i = 0; i < NPV_LIST_LOCKS; i++)
1415 rw_init(&pv_list_locks[i], "pmap pv list");
1418 * Calculate the size of the pv head table for superpages.
1420 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1423 * Allocate memory for the pv head table for superpages.
1425 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1427 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1428 for (i = 0; i < pv_npg; i++)
1429 TAILQ_INIT(&pv_table[i].pv_list);
1430 TAILQ_INIT(&pv_dummy.pv_list);
1432 pmap_initialized = 1;
1433 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1434 ppim = pmap_preinit_mapping + i;
1437 /* Make the direct map consistent */
1438 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1439 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1440 ppim->sz, ppim->mode);
1444 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1445 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1448 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1449 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1450 (vmem_addr_t *)&qframe);
1452 panic("qframe allocation failed");
1455 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1456 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1457 lm_ents = LMEPML4I - LMSPML4I + 1;
1459 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1460 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1462 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1463 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1464 if (large_vmem == NULL) {
1465 printf("pmap: cannot create large map\n");
1468 for (i = 0; i < lm_ents; i++) {
1469 m = pmap_large_map_getptp_unlocked();
1470 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1471 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1477 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1478 "2MB page mapping counters");
1480 static u_long pmap_pde_demotions;
1481 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1482 &pmap_pde_demotions, 0, "2MB page demotions");
1484 static u_long pmap_pde_mappings;
1485 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1486 &pmap_pde_mappings, 0, "2MB page mappings");
1488 static u_long pmap_pde_p_failures;
1489 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1490 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1492 static u_long pmap_pde_promotions;
1493 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1494 &pmap_pde_promotions, 0, "2MB page promotions");
1496 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1497 "1GB page mapping counters");
1499 static u_long pmap_pdpe_demotions;
1500 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1501 &pmap_pdpe_demotions, 0, "1GB page demotions");
1503 /***************************************************
1504 * Low level helper routines.....
1505 ***************************************************/
1508 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1510 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1512 switch (pmap->pm_type) {
1515 /* Verify that both PAT bits are not set at the same time */
1516 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1517 ("Invalid PAT bits in entry %#lx", entry));
1519 /* Swap the PAT bits if one of them is set */
1520 if ((entry & x86_pat_bits) != 0)
1521 entry ^= x86_pat_bits;
1525 * Nothing to do - the memory attributes are represented
1526 * the same way for regular pages and superpages.
1530 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1537 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1540 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1541 pat_index[(int)mode] >= 0);
1545 * Determine the appropriate bits to set in a PTE or PDE for a specified
1549 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1551 int cache_bits, pat_flag, pat_idx;
1553 if (!pmap_is_valid_memattr(pmap, mode))
1554 panic("Unknown caching mode %d\n", mode);
1556 switch (pmap->pm_type) {
1559 /* The PAT bit is different for PTE's and PDE's. */
1560 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1562 /* Map the caching mode to a PAT index. */
1563 pat_idx = pat_index[mode];
1565 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1568 cache_bits |= pat_flag;
1570 cache_bits |= PG_NC_PCD;
1572 cache_bits |= PG_NC_PWT;
1576 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1580 panic("unsupported pmap type %d", pmap->pm_type);
1583 return (cache_bits);
1587 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1591 switch (pmap->pm_type) {
1594 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1597 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1600 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1607 pmap_ps_enabled(pmap_t pmap)
1610 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1614 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1617 switch (pmap->pm_type) {
1624 * This is a little bogus since the generation number is
1625 * supposed to be bumped up when a region of the address
1626 * space is invalidated in the page tables.
1628 * In this case the old PDE entry is valid but yet we want
1629 * to make sure that any mappings using the old entry are
1630 * invalidated in the TLB.
1632 * The reason this works as expected is because we rendezvous
1633 * "all" host cpus and force any vcpu context to exit as a
1636 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1639 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1641 pde_store(pde, newpde);
1645 * After changing the page size for the specified virtual address in the page
1646 * table, flush the corresponding entries from the processor's TLB. Only the
1647 * calling processor's TLB is affected.
1649 * The calling thread must be pinned to a processor.
1652 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1656 if (pmap_type_guest(pmap))
1659 KASSERT(pmap->pm_type == PT_X86,
1660 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1662 PG_G = pmap_global_bit(pmap);
1664 if ((newpde & PG_PS) == 0)
1665 /* Demotion: flush a specific 2MB page mapping. */
1667 else if ((newpde & PG_G) == 0)
1669 * Promotion: flush every 4KB page mapping from the TLB
1670 * because there are too many to flush individually.
1675 * Promotion: flush every 4KB page mapping from the TLB,
1676 * including any global (PG_G) mappings.
1684 * For SMP, these functions have to use the IPI mechanism for coherence.
1686 * N.B.: Before calling any of the following TLB invalidation functions,
1687 * the calling processor must ensure that all stores updating a non-
1688 * kernel page table are globally performed. Otherwise, another
1689 * processor could cache an old, pre-update entry without being
1690 * invalidated. This can happen one of two ways: (1) The pmap becomes
1691 * active on another processor after its pm_active field is checked by
1692 * one of the following functions but before a store updating the page
1693 * table is globally performed. (2) The pmap becomes active on another
1694 * processor before its pm_active field is checked but due to
1695 * speculative loads one of the following functions stills reads the
1696 * pmap as inactive on the other processor.
1698 * The kernel page table is exempt because its pm_active field is
1699 * immutable. The kernel page table is always active on every
1704 * Interrupt the cpus that are executing in the guest context.
1705 * This will force the vcpu to exit and the cached EPT mappings
1706 * will be invalidated by the host before the next vmresume.
1708 static __inline void
1709 pmap_invalidate_ept(pmap_t pmap)
1714 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1715 ("pmap_invalidate_ept: absurd pm_active"));
1718 * The TLB mappings associated with a vcpu context are not
1719 * flushed each time a different vcpu is chosen to execute.
1721 * This is in contrast with a process's vtop mappings that
1722 * are flushed from the TLB on each context switch.
1724 * Therefore we need to do more than just a TLB shootdown on
1725 * the active cpus in 'pmap->pm_active'. To do this we keep
1726 * track of the number of invalidations performed on this pmap.
1728 * Each vcpu keeps a cache of this counter and compares it
1729 * just before a vmresume. If the counter is out-of-date an
1730 * invept will be done to flush stale mappings from the TLB.
1732 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1735 * Force the vcpu to exit and trap back into the hypervisor.
1737 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1738 ipi_selected(pmap->pm_active, ipinum);
1743 pmap_invalidate_cpu_mask(pmap_t pmap)
1746 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
1750 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
1751 const bool invpcid_works1)
1753 struct invpcid_descr d;
1754 uint64_t kcr3, ucr3;
1758 cpuid = PCPU_GET(cpuid);
1759 if (pmap == PCPU_GET(curpmap)) {
1760 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1762 * Because pm_pcid is recalculated on a
1763 * context switch, we must disable switching.
1764 * Otherwise, we might use a stale value
1768 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1769 if (invpcid_works1) {
1770 d.pcid = pcid | PMAP_PCID_USER_PT;
1773 invpcid(&d, INVPCID_ADDR);
1775 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
1776 ucr3 = pmap->pm_ucr3 | pcid |
1777 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1778 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1783 pmap->pm_pcids[cpuid].pm_gen = 0;
1787 pmap->pm_pcids[i].pm_gen = 0;
1791 * The fence is between stores to pm_gen and the read of the
1792 * pm_active mask. We need to ensure that it is impossible
1793 * for us to miss the bit update in pm_active and
1794 * simultaneously observe a non-zero pm_gen in
1795 * pmap_activate_sw(), otherwise TLB update is missed.
1796 * Without the fence, IA32 allows such an outcome. Note that
1797 * pm_active is updated by a locked operation, which provides
1798 * the reciprocal fence.
1800 atomic_thread_fence_seq_cst();
1804 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
1807 pmap_invalidate_page_pcid(pmap, va, true);
1811 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
1814 pmap_invalidate_page_pcid(pmap, va, false);
1818 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
1822 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t),
1826 if (pmap_pcid_enabled)
1827 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
1828 pmap_invalidate_page_pcid_noinvpcid);
1829 return (pmap_invalidate_page_nopcid);
1833 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1836 if (pmap_type_guest(pmap)) {
1837 pmap_invalidate_ept(pmap);
1841 KASSERT(pmap->pm_type == PT_X86,
1842 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1845 if (pmap == kernel_pmap) {
1848 if (pmap == PCPU_GET(curpmap))
1850 pmap_invalidate_page_mode(pmap, va);
1852 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
1856 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1857 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1860 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1861 const bool invpcid_works1)
1863 struct invpcid_descr d;
1864 uint64_t kcr3, ucr3;
1868 cpuid = PCPU_GET(cpuid);
1869 if (pmap == PCPU_GET(curpmap)) {
1870 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1872 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1873 if (invpcid_works1) {
1874 d.pcid = pcid | PMAP_PCID_USER_PT;
1877 for (; d.addr < eva; d.addr += PAGE_SIZE)
1878 invpcid(&d, INVPCID_ADDR);
1880 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
1881 ucr3 = pmap->pm_ucr3 | pcid |
1882 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1883 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
1888 pmap->pm_pcids[cpuid].pm_gen = 0;
1892 pmap->pm_pcids[i].pm_gen = 0;
1894 /* See the comment in pmap_invalidate_page_pcid(). */
1895 atomic_thread_fence_seq_cst();
1899 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
1903 pmap_invalidate_range_pcid(pmap, sva, eva, true);
1907 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
1911 pmap_invalidate_range_pcid(pmap, sva, eva, false);
1915 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1919 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
1920 vm_offset_t), static)
1923 if (pmap_pcid_enabled)
1924 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
1925 pmap_invalidate_range_pcid_noinvpcid);
1926 return (pmap_invalidate_range_nopcid);
1930 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1934 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1935 pmap_invalidate_all(pmap);
1939 if (pmap_type_guest(pmap)) {
1940 pmap_invalidate_ept(pmap);
1944 KASSERT(pmap->pm_type == PT_X86,
1945 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1948 if (pmap == kernel_pmap) {
1949 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1952 if (pmap == PCPU_GET(curpmap)) {
1953 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1956 pmap_invalidate_range_mode(pmap, sva, eva);
1958 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
1963 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
1965 struct invpcid_descr d;
1966 uint64_t kcr3, ucr3;
1970 if (pmap == kernel_pmap) {
1971 if (invpcid_works1) {
1972 bzero(&d, sizeof(d));
1973 invpcid(&d, INVPCID_CTXGLOB);
1978 cpuid = PCPU_GET(cpuid);
1979 if (pmap == PCPU_GET(curpmap)) {
1981 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1982 if (invpcid_works1) {
1986 invpcid(&d, INVPCID_CTX);
1987 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1988 d.pcid |= PMAP_PCID_USER_PT;
1989 invpcid(&d, INVPCID_CTX);
1992 kcr3 = pmap->pm_cr3 | pcid;
1993 ucr3 = pmap->pm_ucr3;
1994 if (ucr3 != PMAP_NO_CR3) {
1995 ucr3 |= pcid | PMAP_PCID_USER_PT;
1996 pmap_pti_pcid_invalidate(ucr3, kcr3);
2003 pmap->pm_pcids[cpuid].pm_gen = 0;
2006 pmap->pm_pcids[i].pm_gen = 0;
2009 /* See the comment in pmap_invalidate_page_pcid(). */
2010 atomic_thread_fence_seq_cst();
2014 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2017 pmap_invalidate_all_pcid(pmap, true);
2021 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2024 pmap_invalidate_all_pcid(pmap, false);
2028 pmap_invalidate_all_nopcid(pmap_t pmap)
2031 if (pmap == kernel_pmap)
2033 else if (pmap == PCPU_GET(curpmap))
2037 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t), static)
2040 if (pmap_pcid_enabled)
2041 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2042 pmap_invalidate_all_pcid_noinvpcid);
2043 return (pmap_invalidate_all_nopcid);
2047 pmap_invalidate_all(pmap_t pmap)
2050 if (pmap_type_guest(pmap)) {
2051 pmap_invalidate_ept(pmap);
2055 KASSERT(pmap->pm_type == PT_X86,
2056 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2059 pmap_invalidate_all_mode(pmap);
2060 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2065 pmap_invalidate_cache(void)
2075 cpuset_t invalidate; /* processors that invalidate their TLB */
2080 u_int store; /* processor that updates the PDE */
2084 pmap_update_pde_action(void *arg)
2086 struct pde_action *act = arg;
2088 if (act->store == PCPU_GET(cpuid))
2089 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2093 pmap_update_pde_teardown(void *arg)
2095 struct pde_action *act = arg;
2097 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2098 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2102 * Change the page size for the specified virtual address in a way that
2103 * prevents any possibility of the TLB ever having two entries that map the
2104 * same virtual address using different page sizes. This is the recommended
2105 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2106 * machine check exception for a TLB state that is improperly diagnosed as a
2110 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2112 struct pde_action act;
2113 cpuset_t active, other_cpus;
2117 cpuid = PCPU_GET(cpuid);
2118 other_cpus = all_cpus;
2119 CPU_CLR(cpuid, &other_cpus);
2120 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2123 active = pmap->pm_active;
2125 if (CPU_OVERLAP(&active, &other_cpus)) {
2127 act.invalidate = active;
2131 act.newpde = newpde;
2132 CPU_SET(cpuid, &active);
2133 smp_rendezvous_cpus(active,
2134 smp_no_rendezvous_barrier, pmap_update_pde_action,
2135 pmap_update_pde_teardown, &act);
2137 pmap_update_pde_store(pmap, pde, newpde);
2138 if (CPU_ISSET(cpuid, &active))
2139 pmap_update_pde_invalidate(pmap, va, newpde);
2145 * Normal, non-SMP, invalidation functions.
2148 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2150 struct invpcid_descr d;
2151 uint64_t kcr3, ucr3;
2154 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2158 KASSERT(pmap->pm_type == PT_X86,
2159 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2161 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2163 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2164 pmap->pm_ucr3 != PMAP_NO_CR3) {
2166 pcid = pmap->pm_pcids[0].pm_pcid;
2167 if (invpcid_works) {
2168 d.pcid = pcid | PMAP_PCID_USER_PT;
2171 invpcid(&d, INVPCID_ADDR);
2173 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2174 ucr3 = pmap->pm_ucr3 | pcid |
2175 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2176 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2180 } else if (pmap_pcid_enabled)
2181 pmap->pm_pcids[0].pm_gen = 0;
2185 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2187 struct invpcid_descr d;
2189 uint64_t kcr3, ucr3;
2191 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2195 KASSERT(pmap->pm_type == PT_X86,
2196 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2198 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2199 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2201 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2202 pmap->pm_ucr3 != PMAP_NO_CR3) {
2204 if (invpcid_works) {
2205 d.pcid = pmap->pm_pcids[0].pm_pcid |
2209 for (; d.addr < eva; d.addr += PAGE_SIZE)
2210 invpcid(&d, INVPCID_ADDR);
2212 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2213 pm_pcid | CR3_PCID_SAVE;
2214 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2215 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2216 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2220 } else if (pmap_pcid_enabled) {
2221 pmap->pm_pcids[0].pm_gen = 0;
2226 pmap_invalidate_all(pmap_t pmap)
2228 struct invpcid_descr d;
2229 uint64_t kcr3, ucr3;
2231 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2235 KASSERT(pmap->pm_type == PT_X86,
2236 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2238 if (pmap == kernel_pmap) {
2239 if (pmap_pcid_enabled && invpcid_works) {
2240 bzero(&d, sizeof(d));
2241 invpcid(&d, INVPCID_CTXGLOB);
2245 } else if (pmap == PCPU_GET(curpmap)) {
2246 if (pmap_pcid_enabled) {
2248 if (invpcid_works) {
2249 d.pcid = pmap->pm_pcids[0].pm_pcid;
2252 invpcid(&d, INVPCID_CTX);
2253 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2254 d.pcid |= PMAP_PCID_USER_PT;
2255 invpcid(&d, INVPCID_CTX);
2258 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2259 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2260 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2261 0].pm_pcid | PMAP_PCID_USER_PT;
2262 pmap_pti_pcid_invalidate(ucr3, kcr3);
2270 } else if (pmap_pcid_enabled) {
2271 pmap->pm_pcids[0].pm_gen = 0;
2276 pmap_invalidate_cache(void)
2283 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2286 pmap_update_pde_store(pmap, pde, newpde);
2287 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2288 pmap_update_pde_invalidate(pmap, va, newpde);
2290 pmap->pm_pcids[0].pm_gen = 0;
2295 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2299 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2300 * by a promotion that did not invalidate the 512 4KB page mappings
2301 * that might exist in the TLB. Consequently, at this point, the TLB
2302 * may hold both 4KB and 2MB page mappings for the address range [va,
2303 * va + NBPDR). Therefore, the entire range must be invalidated here.
2304 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2305 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2306 * single INVLPG suffices to invalidate the 2MB page mapping from the
2309 if ((pde & PG_PROMOTED) != 0)
2310 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2312 pmap_invalidate_page(pmap, va);
2315 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2316 (vm_offset_t sva, vm_offset_t eva), static)
2319 if ((cpu_feature & CPUID_SS) != 0)
2320 return (pmap_invalidate_cache_range_selfsnoop);
2321 if ((cpu_feature & CPUID_CLFSH) != 0)
2322 return (pmap_force_invalidate_cache_range);
2323 return (pmap_invalidate_cache_range_all);
2326 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2329 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2332 KASSERT((sva & PAGE_MASK) == 0,
2333 ("pmap_invalidate_cache_range: sva not page-aligned"));
2334 KASSERT((eva & PAGE_MASK) == 0,
2335 ("pmap_invalidate_cache_range: eva not page-aligned"));
2339 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2342 pmap_invalidate_cache_range_check_align(sva, eva);
2346 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2349 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2352 * XXX: Some CPUs fault, hang, or trash the local APIC
2353 * registers if we use CLFLUSH on the local APIC range. The
2354 * local APIC is always uncached, so we don't need to flush
2355 * for that range anyway.
2357 if (pmap_kextract(sva) == lapic_paddr)
2360 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2362 * Do per-cache line flush. Use the sfence
2363 * instruction to insure that previous stores are
2364 * included in the write-back. The processor
2365 * propagates flush to other processors in the cache
2369 for (; sva < eva; sva += cpu_clflush_line_size)
2374 * Writes are ordered by CLFLUSH on Intel CPUs.
2376 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2378 for (; sva < eva; sva += cpu_clflush_line_size)
2380 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2386 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2389 pmap_invalidate_cache_range_check_align(sva, eva);
2390 pmap_invalidate_cache();
2394 * Remove the specified set of pages from the data and instruction caches.
2396 * In contrast to pmap_invalidate_cache_range(), this function does not
2397 * rely on the CPU's self-snoop feature, because it is intended for use
2398 * when moving pages into a different cache domain.
2401 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2403 vm_offset_t daddr, eva;
2407 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2408 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2409 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2410 pmap_invalidate_cache();
2414 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2416 for (i = 0; i < count; i++) {
2417 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2418 eva = daddr + PAGE_SIZE;
2419 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2428 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2434 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2437 pmap_invalidate_cache_range_check_align(sva, eva);
2439 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2440 pmap_force_invalidate_cache_range(sva, eva);
2444 /* See comment in pmap_force_invalidate_cache_range(). */
2445 if (pmap_kextract(sva) == lapic_paddr)
2449 for (; sva < eva; sva += cpu_clflush_line_size)
2455 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2459 int error, pte_bits;
2461 KASSERT((spa & PAGE_MASK) == 0,
2462 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2463 KASSERT((epa & PAGE_MASK) == 0,
2464 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2466 if (spa < dmaplimit) {
2467 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2469 if (dmaplimit >= epa)
2474 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
2476 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2478 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
2479 pte = vtopte(vaddr);
2480 for (; spa < epa; spa += PAGE_SIZE) {
2482 pte_store(pte, spa | pte_bits);
2484 /* XXXKIB sfences inside flush_cache_range are excessive */
2485 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
2488 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
2492 * Routine: pmap_extract
2494 * Extract the physical page address associated
2495 * with the given map/virtual_address pair.
2498 pmap_extract(pmap_t pmap, vm_offset_t va)
2502 pt_entry_t *pte, PG_V;
2506 PG_V = pmap_valid_bit(pmap);
2508 pdpe = pmap_pdpe(pmap, va);
2509 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2510 if ((*pdpe & PG_PS) != 0)
2511 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2513 pde = pmap_pdpe_to_pde(pdpe, va);
2514 if ((*pde & PG_V) != 0) {
2515 if ((*pde & PG_PS) != 0) {
2516 pa = (*pde & PG_PS_FRAME) |
2519 pte = pmap_pde_to_pte(pde, va);
2520 pa = (*pte & PG_FRAME) |
2531 * Routine: pmap_extract_and_hold
2533 * Atomically extract and hold the physical page
2534 * with the given pmap and virtual address pair
2535 * if that mapping permits the given protection.
2538 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2540 pd_entry_t pde, *pdep;
2541 pt_entry_t pte, PG_RW, PG_V;
2547 PG_RW = pmap_rw_bit(pmap);
2548 PG_V = pmap_valid_bit(pmap);
2551 pdep = pmap_pde(pmap, va);
2552 if (pdep != NULL && (pde = *pdep)) {
2554 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2555 if (vm_page_pa_tryrelock(pmap, (pde &
2556 PG_PS_FRAME) | (va & PDRMASK), &pa))
2558 m = PHYS_TO_VM_PAGE(pa);
2561 pte = *pmap_pde_to_pte(pdep, va);
2563 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2564 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2567 m = PHYS_TO_VM_PAGE(pa);
2579 pmap_kextract(vm_offset_t va)
2584 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2585 pa = DMAP_TO_PHYS(va);
2589 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2592 * Beware of a concurrent promotion that changes the
2593 * PDE at this point! For example, vtopte() must not
2594 * be used to access the PTE because it would use the
2595 * new PDE. It is, however, safe to use the old PDE
2596 * because the page table page is preserved by the
2599 pa = *pmap_pde_to_pte(&pde, va);
2600 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2606 /***************************************************
2607 * Low level mapping routines.....
2608 ***************************************************/
2611 * Add a wired page to the kva.
2612 * Note: not SMP coherent.
2615 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2620 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2623 static __inline void
2624 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2630 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2631 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2635 * Remove a page from the kernel pagetables.
2636 * Note: not SMP coherent.
2639 pmap_kremove(vm_offset_t va)
2648 * Used to map a range of physical addresses into kernel
2649 * virtual address space.
2651 * The value passed in '*virt' is a suggested virtual address for
2652 * the mapping. Architectures which can support a direct-mapped
2653 * physical to virtual region can return the appropriate address
2654 * within that region, leaving '*virt' unchanged. Other
2655 * architectures should map the pages starting at '*virt' and
2656 * update '*virt' with the first usable address after the mapped
2660 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2662 return PHYS_TO_DMAP(start);
2667 * Add a list of wired pages to the kva
2668 * this routine is only used for temporary
2669 * kernel mappings that do not need to have
2670 * page modification or references recorded.
2671 * Note that old mappings are simply written
2672 * over. The page *must* be wired.
2673 * Note: SMP coherent. Uses a ranged shootdown IPI.
2676 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2678 pt_entry_t *endpte, oldpte, pa, *pte;
2684 endpte = pte + count;
2685 while (pte < endpte) {
2687 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2688 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2689 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2691 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2695 if (__predict_false((oldpte & X86_PG_V) != 0))
2696 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2701 * This routine tears out page mappings from the
2702 * kernel -- it is meant only for temporary mappings.
2703 * Note: SMP coherent. Uses a ranged shootdown IPI.
2706 pmap_qremove(vm_offset_t sva, int count)
2711 while (count-- > 0) {
2712 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2716 pmap_invalidate_range(kernel_pmap, sva, va);
2719 /***************************************************
2720 * Page table page management routines.....
2721 ***************************************************/
2723 * Schedule the specified unused page table page to be freed. Specifically,
2724 * add the page to the specified list of pages that will be released to the
2725 * physical memory manager after the TLB has been updated.
2727 static __inline void
2728 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2729 boolean_t set_PG_ZERO)
2733 m->flags |= PG_ZERO;
2735 m->flags &= ~PG_ZERO;
2736 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2740 * Inserts the specified page table page into the specified pmap's collection
2741 * of idle page table pages. Each of a pmap's page table pages is responsible
2742 * for mapping a distinct range of virtual addresses. The pmap's collection is
2743 * ordered by this virtual address range.
2746 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2749 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2750 return (vm_radix_insert(&pmap->pm_root, mpte));
2754 * Removes the page table page mapping the specified virtual address from the
2755 * specified pmap's collection of idle page table pages, and returns it.
2756 * Otherwise, returns NULL if there is no page table page corresponding to the
2757 * specified virtual address.
2759 static __inline vm_page_t
2760 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2764 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2768 * Decrements a page table page's wire count, which is used to record the
2769 * number of valid page table entries within the page. If the wire count
2770 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2771 * page table page was unmapped and FALSE otherwise.
2773 static inline boolean_t
2774 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2778 if (m->wire_count == 0) {
2779 _pmap_unwire_ptp(pmap, va, m, free);
2786 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2791 * unmap the page table page
2793 if (m->pindex >= (NUPDE + NUPDPE)) {
2796 pml4 = pmap_pml4e(pmap, va);
2798 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2799 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2802 } else if (m->pindex >= NUPDE) {
2805 pdp = pmap_pdpe(pmap, va);
2810 pd = pmap_pde(pmap, va);
2813 pmap_resident_count_dec(pmap, 1);
2814 if (m->pindex < NUPDE) {
2815 /* We just released a PT, unhold the matching PD */
2818 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2819 pmap_unwire_ptp(pmap, va, pdpg, free);
2821 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2822 /* We just released a PD, unhold the matching PDP */
2825 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2826 pmap_unwire_ptp(pmap, va, pdppg, free);
2830 * Put page on a list so that it is released after
2831 * *ALL* TLB shootdown is done
2833 pmap_add_delayed_free_list(m, free, TRUE);
2837 * After removing a page table entry, this routine is used to
2838 * conditionally free the page, and manage the hold/wire counts.
2841 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2842 struct spglist *free)
2846 if (va >= VM_MAXUSER_ADDRESS)
2848 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2849 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2850 return (pmap_unwire_ptp(pmap, va, mpte, free));
2854 pmap_pinit0(pmap_t pmap)
2859 PMAP_LOCK_INIT(pmap);
2860 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2861 pmap->pm_pml4u = NULL;
2862 pmap->pm_cr3 = KPML4phys;
2863 /* hack to keep pmap_pti_pcid_invalidate() alive */
2864 pmap->pm_ucr3 = PMAP_NO_CR3;
2865 pmap->pm_root.rt_root = 0;
2866 CPU_ZERO(&pmap->pm_active);
2867 TAILQ_INIT(&pmap->pm_pvchunk);
2868 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2869 pmap->pm_flags = pmap_flags;
2871 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
2872 pmap->pm_pcids[i].pm_gen = 1;
2874 pmap_activate_boot(pmap);
2878 p->p_md.md_flags |= P_MD_KPTI;
2882 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
2883 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
2884 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
2890 pmap_pinit_pml4(vm_page_t pml4pg)
2892 pml4_entry_t *pm_pml4;
2895 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2897 /* Wire in kernel global address entries. */
2898 for (i = 0; i < NKPML4E; i++) {
2899 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2902 for (i = 0; i < ndmpdpphys; i++) {
2903 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2907 /* install self-referential address mapping entry(s) */
2908 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2909 X86_PG_A | X86_PG_M;
2911 /* install large map entries if configured */
2912 for (i = 0; i < lm_ents; i++)
2913 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
2917 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2919 pml4_entry_t *pm_pml4;
2922 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2923 for (i = 0; i < NPML4EPG; i++)
2924 pm_pml4[i] = pti_pml4[i];
2928 * Initialize a preallocated and zeroed pmap structure,
2929 * such as one in a vmspace structure.
2932 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2934 vm_page_t pml4pg, pml4pgu;
2935 vm_paddr_t pml4phys;
2939 * allocate the page directory page
2941 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2942 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2944 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2945 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2947 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2948 pmap->pm_pcids[i].pm_gen = 0;
2950 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2951 pmap->pm_ucr3 = PMAP_NO_CR3;
2952 pmap->pm_pml4u = NULL;
2954 pmap->pm_type = pm_type;
2955 if ((pml4pg->flags & PG_ZERO) == 0)
2956 pagezero(pmap->pm_pml4);
2959 * Do not install the host kernel mappings in the nested page
2960 * tables. These mappings are meaningless in the guest physical
2962 * Install minimal kernel mappings in PTI case.
2964 if (pm_type == PT_X86) {
2965 pmap->pm_cr3 = pml4phys;
2966 pmap_pinit_pml4(pml4pg);
2967 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
2968 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2969 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2970 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2971 VM_PAGE_TO_PHYS(pml4pgu));
2972 pmap_pinit_pml4_pti(pml4pgu);
2973 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2975 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
2976 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
2977 pkru_free_range, pmap, M_NOWAIT);
2981 pmap->pm_root.rt_root = 0;
2982 CPU_ZERO(&pmap->pm_active);
2983 TAILQ_INIT(&pmap->pm_pvchunk);
2984 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2985 pmap->pm_flags = flags;
2986 pmap->pm_eptgen = 0;
2992 pmap_pinit(pmap_t pmap)
2995 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2999 * This routine is called if the desired page table page does not exist.
3001 * If page table page allocation fails, this routine may sleep before
3002 * returning NULL. It sleeps only if a lock pointer was given.
3004 * Note: If a page allocation fails at page table level two or three,
3005 * one or two pages may be held during the wait, only to be released
3006 * afterwards. This conservative approach is easily argued to avoid
3010 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3012 vm_page_t m, pdppg, pdpg;
3013 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3015 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3017 PG_A = pmap_accessed_bit(pmap);
3018 PG_M = pmap_modified_bit(pmap);
3019 PG_V = pmap_valid_bit(pmap);
3020 PG_RW = pmap_rw_bit(pmap);
3023 * Allocate a page table page.
3025 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3026 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3027 if (lockp != NULL) {
3028 RELEASE_PV_LIST_LOCK(lockp);
3030 PMAP_ASSERT_NOT_IN_DI();
3036 * Indicate the need to retry. While waiting, the page table
3037 * page may have been allocated.
3041 if ((m->flags & PG_ZERO) == 0)
3045 * Map the pagetable page into the process address space, if
3046 * it isn't already there.
3049 if (ptepindex >= (NUPDE + NUPDPE)) {
3050 pml4_entry_t *pml4, *pml4u;
3051 vm_pindex_t pml4index;
3053 /* Wire up a new PDPE page */
3054 pml4index = ptepindex - (NUPDE + NUPDPE);
3055 pml4 = &pmap->pm_pml4[pml4index];
3056 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3057 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3059 * PTI: Make all user-space mappings in the
3060 * kernel-mode page table no-execute so that
3061 * we detect any programming errors that leave
3062 * the kernel-mode page table active on return
3065 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3068 pml4u = &pmap->pm_pml4u[pml4index];
3069 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3073 } else if (ptepindex >= NUPDE) {
3074 vm_pindex_t pml4index;
3075 vm_pindex_t pdpindex;
3079 /* Wire up a new PDE page */
3080 pdpindex = ptepindex - NUPDE;
3081 pml4index = pdpindex >> NPML4EPGSHIFT;
3083 pml4 = &pmap->pm_pml4[pml4index];
3084 if ((*pml4 & PG_V) == 0) {
3085 /* Have to allocate a new pdp, recurse */
3086 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3088 vm_page_unwire_noq(m);
3089 vm_page_free_zero(m);
3093 /* Add reference to pdp page */
3094 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3095 pdppg->wire_count++;
3097 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3099 /* Now find the pdp page */
3100 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3101 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3104 vm_pindex_t pml4index;
3105 vm_pindex_t pdpindex;
3110 /* Wire up a new PTE page */
3111 pdpindex = ptepindex >> NPDPEPGSHIFT;
3112 pml4index = pdpindex >> NPML4EPGSHIFT;
3114 /* First, find the pdp and check that its valid. */
3115 pml4 = &pmap->pm_pml4[pml4index];
3116 if ((*pml4 & PG_V) == 0) {
3117 /* Have to allocate a new pd, recurse */
3118 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3120 vm_page_unwire_noq(m);
3121 vm_page_free_zero(m);
3124 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3125 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3127 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3128 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3129 if ((*pdp & PG_V) == 0) {
3130 /* Have to allocate a new pd, recurse */
3131 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3133 vm_page_unwire_noq(m);
3134 vm_page_free_zero(m);
3138 /* Add reference to the pd page */
3139 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3143 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3145 /* Now we know where the page directory page is */
3146 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3147 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3150 pmap_resident_count_inc(pmap, 1);
3156 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3158 vm_pindex_t pdpindex, ptepindex;
3159 pdp_entry_t *pdpe, PG_V;
3162 PG_V = pmap_valid_bit(pmap);
3165 pdpe = pmap_pdpe(pmap, va);
3166 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3167 /* Add a reference to the pd page. */
3168 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3171 /* Allocate a pd page. */
3172 ptepindex = pmap_pde_pindex(va);
3173 pdpindex = ptepindex >> NPDPEPGSHIFT;
3174 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3175 if (pdpg == NULL && lockp != NULL)
3182 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3184 vm_pindex_t ptepindex;
3185 pd_entry_t *pd, PG_V;
3188 PG_V = pmap_valid_bit(pmap);
3191 * Calculate pagetable page index
3193 ptepindex = pmap_pde_pindex(va);
3196 * Get the page directory entry
3198 pd = pmap_pde(pmap, va);
3201 * This supports switching from a 2MB page to a
3204 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3205 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3207 * Invalidation of the 2MB page mapping may have caused
3208 * the deallocation of the underlying PD page.
3215 * If the page table page is mapped, we just increment the
3216 * hold count, and activate it.
3218 if (pd != NULL && (*pd & PG_V) != 0) {
3219 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3223 * Here if the pte page isn't mapped, or if it has been
3226 m = _pmap_allocpte(pmap, ptepindex, lockp);
3227 if (m == NULL && lockp != NULL)
3234 /***************************************************
3235 * Pmap allocation/deallocation routines.
3236 ***************************************************/
3239 * Release any resources held by the given physical map.
3240 * Called when a pmap initialized by pmap_pinit is being released.
3241 * Should only be called if the map contains no valid mappings.
3244 pmap_release(pmap_t pmap)
3249 KASSERT(pmap->pm_stats.resident_count == 0,
3250 ("pmap_release: pmap resident count %ld != 0",
3251 pmap->pm_stats.resident_count));
3252 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3253 ("pmap_release: pmap has reserved page table page(s)"));
3254 KASSERT(CPU_EMPTY(&pmap->pm_active),
3255 ("releasing active pmap %p", pmap));
3257 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3259 for (i = 0; i < NKPML4E; i++) /* KVA */
3260 pmap->pm_pml4[KPML4BASE + i] = 0;
3261 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3262 pmap->pm_pml4[DMPML4I + i] = 0;
3263 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3264 for (i = 0; i < lm_ents; i++) /* Large Map */
3265 pmap->pm_pml4[LMSPML4I + i] = 0;
3267 vm_page_unwire_noq(m);
3268 vm_page_free_zero(m);
3270 if (pmap->pm_pml4u != NULL) {
3271 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3272 vm_page_unwire_noq(m);
3275 if (pmap->pm_type == PT_X86 &&
3276 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3277 rangeset_fini(&pmap->pm_pkru);
3281 kvm_size(SYSCTL_HANDLER_ARGS)
3283 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3285 return sysctl_handle_long(oidp, &ksize, 0, req);
3287 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3288 0, 0, kvm_size, "LU", "Size of KVM");
3291 kvm_free(SYSCTL_HANDLER_ARGS)
3293 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3295 return sysctl_handle_long(oidp, &kfree, 0, req);
3297 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3298 0, 0, kvm_free, "LU", "Amount of KVM free");
3301 * grow the number of kernel page table entries, if needed
3304 pmap_growkernel(vm_offset_t addr)
3308 pd_entry_t *pde, newpdir;
3311 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3314 * Return if "addr" is within the range of kernel page table pages
3315 * that were preallocated during pmap bootstrap. Moreover, leave
3316 * "kernel_vm_end" and the kernel page table as they were.
3318 * The correctness of this action is based on the following
3319 * argument: vm_map_insert() allocates contiguous ranges of the
3320 * kernel virtual address space. It calls this function if a range
3321 * ends after "kernel_vm_end". If the kernel is mapped between
3322 * "kernel_vm_end" and "addr", then the range cannot begin at
3323 * "kernel_vm_end". In fact, its beginning address cannot be less
3324 * than the kernel. Thus, there is no immediate need to allocate
3325 * any new kernel page table pages between "kernel_vm_end" and
3328 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3331 addr = roundup2(addr, NBPDR);
3332 if (addr - 1 >= vm_map_max(kernel_map))
3333 addr = vm_map_max(kernel_map);
3334 while (kernel_vm_end < addr) {
3335 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3336 if ((*pdpe & X86_PG_V) == 0) {
3337 /* We need a new PDP entry */
3338 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3339 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3340 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3342 panic("pmap_growkernel: no memory to grow kernel");
3343 if ((nkpg->flags & PG_ZERO) == 0)
3344 pmap_zero_page(nkpg);
3345 paddr = VM_PAGE_TO_PHYS(nkpg);
3346 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3347 X86_PG_A | X86_PG_M);
3348 continue; /* try again */
3350 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3351 if ((*pde & X86_PG_V) != 0) {
3352 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3353 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3354 kernel_vm_end = vm_map_max(kernel_map);
3360 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3361 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3364 panic("pmap_growkernel: no memory to grow kernel");
3365 if ((nkpg->flags & PG_ZERO) == 0)
3366 pmap_zero_page(nkpg);
3367 paddr = VM_PAGE_TO_PHYS(nkpg);
3368 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3369 pde_store(pde, newpdir);
3371 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3372 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3373 kernel_vm_end = vm_map_max(kernel_map);
3380 /***************************************************
3381 * page management routines.
3382 ***************************************************/
3384 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3385 CTASSERT(_NPCM == 3);
3386 CTASSERT(_NPCPV == 168);
3388 static __inline struct pv_chunk *
3389 pv_to_chunk(pv_entry_t pv)
3392 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3395 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3397 #define PC_FREE0 0xfffffffffffffffful
3398 #define PC_FREE1 0xfffffffffffffffful
3399 #define PC_FREE2 0x000000fffffffffful
3401 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3404 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3406 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3407 "Current number of pv entry chunks");
3408 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3409 "Current number of pv entry chunks allocated");
3410 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3411 "Current number of pv entry chunks frees");
3412 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3413 "Number of times tried to get a chunk page but failed.");
3415 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3416 static int pv_entry_spare;
3418 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3419 "Current number of pv entry frees");
3420 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3421 "Current number of pv entry allocs");
3422 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3423 "Current number of pv entries");
3424 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3425 "Current number of spare pv entries");
3429 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3434 pmap_invalidate_all(pmap);
3435 if (pmap != locked_pmap)
3438 pmap_delayed_invl_finished();
3442 * We are in a serious low memory condition. Resort to
3443 * drastic measures to free some pages so we can allocate
3444 * another pv entry chunk.
3446 * Returns NULL if PV entries were reclaimed from the specified pmap.
3448 * We do not, however, unmap 2mpages because subsequent accesses will
3449 * allocate per-page pv entries until repromotion occurs, thereby
3450 * exacerbating the shortage of free pv entries.
3453 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3455 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3456 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3457 struct md_page *pvh;
3459 pmap_t next_pmap, pmap;
3460 pt_entry_t *pte, tpte;
3461 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3465 struct spglist free;
3467 int bit, field, freed;
3469 static int active_reclaims = 0;
3471 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3472 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3475 PG_G = PG_A = PG_M = PG_RW = 0;
3477 bzero(&pc_marker_b, sizeof(pc_marker_b));
3478 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3479 pc_marker = (struct pv_chunk *)&pc_marker_b;
3480 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3483 * A delayed invalidation block should already be active if
3484 * pmap_advise() or pmap_remove() called this function by way
3485 * of pmap_demote_pde_locked().
3487 start_di = pmap_not_in_di();
3489 mtx_lock(&pv_chunks_mutex);
3491 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3492 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3493 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3494 SLIST_EMPTY(&free)) {
3495 next_pmap = pc->pc_pmap;
3496 if (next_pmap == NULL) {
3498 * The next chunk is a marker. However, it is
3499 * not our marker, so active_reclaims must be
3500 * > 1. Consequently, the next_chunk code
3501 * will not rotate the pv_chunks list.
3505 mtx_unlock(&pv_chunks_mutex);
3508 * A pv_chunk can only be removed from the pc_lru list
3509 * when both pc_chunks_mutex is owned and the
3510 * corresponding pmap is locked.
3512 if (pmap != next_pmap) {
3513 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3516 /* Avoid deadlock and lock recursion. */
3517 if (pmap > locked_pmap) {
3518 RELEASE_PV_LIST_LOCK(lockp);
3521 pmap_delayed_invl_started();
3522 mtx_lock(&pv_chunks_mutex);
3524 } else if (pmap != locked_pmap) {
3525 if (PMAP_TRYLOCK(pmap)) {
3527 pmap_delayed_invl_started();
3528 mtx_lock(&pv_chunks_mutex);
3531 pmap = NULL; /* pmap is not locked */
3532 mtx_lock(&pv_chunks_mutex);
3533 pc = TAILQ_NEXT(pc_marker, pc_lru);
3535 pc->pc_pmap != next_pmap)
3539 } else if (start_di)
3540 pmap_delayed_invl_started();
3541 PG_G = pmap_global_bit(pmap);
3542 PG_A = pmap_accessed_bit(pmap);
3543 PG_M = pmap_modified_bit(pmap);
3544 PG_RW = pmap_rw_bit(pmap);
3548 * Destroy every non-wired, 4 KB page mapping in the chunk.
3551 for (field = 0; field < _NPCM; field++) {
3552 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3553 inuse != 0; inuse &= ~(1UL << bit)) {
3555 pv = &pc->pc_pventry[field * 64 + bit];
3557 pde = pmap_pde(pmap, va);
3558 if ((*pde & PG_PS) != 0)
3560 pte = pmap_pde_to_pte(pde, va);
3561 if ((*pte & PG_W) != 0)
3563 tpte = pte_load_clear(pte);
3564 if ((tpte & PG_G) != 0)
3565 pmap_invalidate_page(pmap, va);
3566 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3567 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3569 if ((tpte & PG_A) != 0)
3570 vm_page_aflag_set(m, PGA_REFERENCED);
3571 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3572 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3574 if (TAILQ_EMPTY(&m->md.pv_list) &&
3575 (m->flags & PG_FICTITIOUS) == 0) {
3576 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3577 if (TAILQ_EMPTY(&pvh->pv_list)) {
3578 vm_page_aflag_clear(m,
3582 pmap_delayed_invl_page(m);
3583 pc->pc_map[field] |= 1UL << bit;
3584 pmap_unuse_pt(pmap, va, *pde, &free);
3589 mtx_lock(&pv_chunks_mutex);
3592 /* Every freed mapping is for a 4 KB page. */
3593 pmap_resident_count_dec(pmap, freed);
3594 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3595 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3596 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3597 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3598 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3599 pc->pc_map[2] == PC_FREE2) {
3600 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3601 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3602 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3603 /* Entire chunk is free; return it. */
3604 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3605 dump_drop_page(m_pc->phys_addr);
3606 mtx_lock(&pv_chunks_mutex);
3607 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3610 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3611 mtx_lock(&pv_chunks_mutex);
3612 /* One freed pv entry in locked_pmap is sufficient. */
3613 if (pmap == locked_pmap)
3616 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3617 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3618 if (active_reclaims == 1 && pmap != NULL) {
3620 * Rotate the pv chunks list so that we do not
3621 * scan the same pv chunks that could not be
3622 * freed (because they contained a wired
3623 * and/or superpage mapping) on every
3624 * invocation of reclaim_pv_chunk().
3626 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3627 MPASS(pc->pc_pmap != NULL);
3628 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3629 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3633 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3634 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3636 mtx_unlock(&pv_chunks_mutex);
3637 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3638 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3639 m_pc = SLIST_FIRST(&free);
3640 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3641 /* Recycle a freed page table page. */
3642 m_pc->wire_count = 1;
3644 vm_page_free_pages_toq(&free, true);
3649 * free the pv_entry back to the free list
3652 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3654 struct pv_chunk *pc;
3655 int idx, field, bit;
3657 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3658 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3659 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3660 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3661 pc = pv_to_chunk(pv);
3662 idx = pv - &pc->pc_pventry[0];
3665 pc->pc_map[field] |= 1ul << bit;
3666 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3667 pc->pc_map[2] != PC_FREE2) {
3668 /* 98% of the time, pc is already at the head of the list. */
3669 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3670 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3671 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3675 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3680 free_pv_chunk(struct pv_chunk *pc)
3684 mtx_lock(&pv_chunks_mutex);
3685 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3686 mtx_unlock(&pv_chunks_mutex);
3687 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3688 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3689 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3690 /* entire chunk is free, return it */
3691 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3692 dump_drop_page(m->phys_addr);
3693 vm_page_unwire(m, PQ_NONE);
3698 * Returns a new PV entry, allocating a new PV chunk from the system when
3699 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3700 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3703 * The given PV list lock may be released.
3706 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3710 struct pv_chunk *pc;
3713 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3714 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3716 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3718 for (field = 0; field < _NPCM; field++) {
3719 if (pc->pc_map[field]) {
3720 bit = bsfq(pc->pc_map[field]);
3724 if (field < _NPCM) {
3725 pv = &pc->pc_pventry[field * 64 + bit];
3726 pc->pc_map[field] &= ~(1ul << bit);
3727 /* If this was the last item, move it to tail */
3728 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3729 pc->pc_map[2] == 0) {
3730 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3731 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3734 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3735 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3739 /* No free items, allocate another chunk */
3740 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3743 if (lockp == NULL) {
3744 PV_STAT(pc_chunk_tryfail++);
3747 m = reclaim_pv_chunk(pmap, lockp);
3751 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3752 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3753 dump_add_page(m->phys_addr);
3754 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3756 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3757 pc->pc_map[1] = PC_FREE1;
3758 pc->pc_map[2] = PC_FREE2;
3759 mtx_lock(&pv_chunks_mutex);
3760 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3761 mtx_unlock(&pv_chunks_mutex);
3762 pv = &pc->pc_pventry[0];
3763 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3764 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3765 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3770 * Returns the number of one bits within the given PV chunk map.
3772 * The erratas for Intel processors state that "POPCNT Instruction May
3773 * Take Longer to Execute Than Expected". It is believed that the
3774 * issue is the spurious dependency on the destination register.
3775 * Provide a hint to the register rename logic that the destination
3776 * value is overwritten, by clearing it, as suggested in the
3777 * optimization manual. It should be cheap for unaffected processors
3780 * Reference numbers for erratas are
3781 * 4th Gen Core: HSD146
3782 * 5th Gen Core: BDM85
3783 * 6th Gen Core: SKL029
3786 popcnt_pc_map_pq(uint64_t *map)
3790 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3791 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3792 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3793 : "=&r" (result), "=&r" (tmp)
3794 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3799 * Ensure that the number of spare PV entries in the specified pmap meets or
3800 * exceeds the given count, "needed".
3802 * The given PV list lock may be released.
3805 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3807 struct pch new_tail;
3808 struct pv_chunk *pc;
3813 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3814 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3817 * Newly allocated PV chunks must be stored in a private list until
3818 * the required number of PV chunks have been allocated. Otherwise,
3819 * reclaim_pv_chunk() could recycle one of these chunks. In
3820 * contrast, these chunks must be added to the pmap upon allocation.
3822 TAILQ_INIT(&new_tail);
3825 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3827 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3828 bit_count((bitstr_t *)pc->pc_map, 0,
3829 sizeof(pc->pc_map) * NBBY, &free);
3832 free = popcnt_pc_map_pq(pc->pc_map);
3836 if (avail >= needed)
3839 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3840 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3843 m = reclaim_pv_chunk(pmap, lockp);
3848 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3849 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3850 dump_add_page(m->phys_addr);
3851 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3853 pc->pc_map[0] = PC_FREE0;
3854 pc->pc_map[1] = PC_FREE1;
3855 pc->pc_map[2] = PC_FREE2;
3856 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3857 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3858 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3861 * The reclaim might have freed a chunk from the current pmap.
3862 * If that chunk contained available entries, we need to
3863 * re-count the number of available entries.
3868 if (!TAILQ_EMPTY(&new_tail)) {
3869 mtx_lock(&pv_chunks_mutex);
3870 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3871 mtx_unlock(&pv_chunks_mutex);
3876 * First find and then remove the pv entry for the specified pmap and virtual
3877 * address from the specified pv list. Returns the pv entry if found and NULL
3878 * otherwise. This operation can be performed on pv lists for either 4KB or
3879 * 2MB page mappings.
3881 static __inline pv_entry_t
3882 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3886 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3887 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3888 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3897 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3898 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3899 * entries for each of the 4KB page mappings.
3902 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3903 struct rwlock **lockp)
3905 struct md_page *pvh;
3906 struct pv_chunk *pc;
3908 vm_offset_t va_last;
3912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3913 KASSERT((pa & PDRMASK) == 0,
3914 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3915 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3918 * Transfer the 2mpage's pv entry for this mapping to the first
3919 * page's pv list. Once this transfer begins, the pv list lock
3920 * must not be released until the last pv entry is reinstantiated.
3922 pvh = pa_to_pvh(pa);
3923 va = trunc_2mpage(va);
3924 pv = pmap_pvh_remove(pvh, pmap, va);
3925 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3926 m = PHYS_TO_VM_PAGE(pa);
3927 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3929 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3930 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3931 va_last = va + NBPDR - PAGE_SIZE;
3933 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3934 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3935 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3936 for (field = 0; field < _NPCM; field++) {
3937 while (pc->pc_map[field]) {
3938 bit = bsfq(pc->pc_map[field]);
3939 pc->pc_map[field] &= ~(1ul << bit);
3940 pv = &pc->pc_pventry[field * 64 + bit];
3944 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3945 ("pmap_pv_demote_pde: page %p is not managed", m));
3946 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3952 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3953 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3956 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3957 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3958 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3960 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3961 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3964 #if VM_NRESERVLEVEL > 0
3966 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3967 * replace the many pv entries for the 4KB page mappings by a single pv entry
3968 * for the 2MB page mapping.
3971 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3972 struct rwlock **lockp)
3974 struct md_page *pvh;
3976 vm_offset_t va_last;
3979 KASSERT((pa & PDRMASK) == 0,
3980 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3981 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3984 * Transfer the first page's pv entry for this mapping to the 2mpage's
3985 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3986 * a transfer avoids the possibility that get_pv_entry() calls
3987 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3988 * mappings that is being promoted.
3990 m = PHYS_TO_VM_PAGE(pa);
3991 va = trunc_2mpage(va);
3992 pv = pmap_pvh_remove(&m->md, pmap, va);
3993 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3994 pvh = pa_to_pvh(pa);
3995 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3997 /* Free the remaining NPTEPG - 1 pv entries. */
3998 va_last = va + NBPDR - PAGE_SIZE;
4002 pmap_pvh_free(&m->md, pmap, va);
4003 } while (va < va_last);
4005 #endif /* VM_NRESERVLEVEL > 0 */
4008 * First find and then destroy the pv entry for the specified pmap and virtual
4009 * address. This operation can be performed on pv lists for either 4KB or 2MB
4013 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4017 pv = pmap_pvh_remove(pvh, pmap, va);
4018 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4019 free_pv_entry(pmap, pv);
4023 * Conditionally create the PV entry for a 4KB page mapping if the required
4024 * memory can be allocated without resorting to reclamation.
4027 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4028 struct rwlock **lockp)
4032 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4033 /* Pass NULL instead of the lock pointer to disable reclamation. */
4034 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4036 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4037 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4045 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4046 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4047 * false if the PV entry cannot be allocated without resorting to reclamation.
4050 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4051 struct rwlock **lockp)
4053 struct md_page *pvh;
4057 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4058 /* Pass NULL instead of the lock pointer to disable reclamation. */
4059 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4060 NULL : lockp)) == NULL)
4063 pa = pde & PG_PS_FRAME;
4064 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4065 pvh = pa_to_pvh(pa);
4066 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4072 * Fills a page table page with mappings to consecutive physical pages.
4075 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4079 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4081 newpte += PAGE_SIZE;
4086 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4087 * mapping is invalidated.
4090 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4092 struct rwlock *lock;
4096 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4103 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4104 struct rwlock **lockp)
4106 pd_entry_t newpde, oldpde;
4107 pt_entry_t *firstpte, newpte;
4108 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4111 struct spglist free;
4115 PG_G = pmap_global_bit(pmap);
4116 PG_A = pmap_accessed_bit(pmap);
4117 PG_M = pmap_modified_bit(pmap);
4118 PG_RW = pmap_rw_bit(pmap);
4119 PG_V = pmap_valid_bit(pmap);
4120 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4121 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4123 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4125 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4126 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4127 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
4129 KASSERT((oldpde & PG_W) == 0,
4130 ("pmap_demote_pde: page table page for a wired mapping"
4134 * Invalidate the 2MB page mapping and return "failure" if the
4135 * mapping was never accessed or the allocation of the new
4136 * page table page fails. If the 2MB page mapping belongs to
4137 * the direct map region of the kernel's address space, then
4138 * the page allocation request specifies the highest possible
4139 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
4140 * normal. Page table pages are preallocated for every other
4141 * part of the kernel address space, so the direct map region
4142 * is the only part of the kernel address space that must be
4145 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
4146 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
4147 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4148 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4150 sva = trunc_2mpage(va);
4151 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4152 if ((oldpde & PG_G) == 0)
4153 pmap_invalidate_pde_page(pmap, sva, oldpde);
4154 vm_page_free_pages_toq(&free, true);
4155 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
4156 " in pmap %p", va, pmap);
4159 if (va < VM_MAXUSER_ADDRESS)
4160 pmap_resident_count_inc(pmap, 1);
4162 mptepa = VM_PAGE_TO_PHYS(mpte);
4163 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4164 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4165 KASSERT((oldpde & PG_A) != 0,
4166 ("pmap_demote_pde: oldpde is missing PG_A"));
4167 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4168 ("pmap_demote_pde: oldpde is missing PG_M"));
4169 newpte = oldpde & ~PG_PS;
4170 newpte = pmap_swap_pat(pmap, newpte);
4173 * If the page table page is new, initialize it.
4175 if (mpte->wire_count == 1) {
4176 mpte->wire_count = NPTEPG;
4177 pmap_fill_ptp(firstpte, newpte);
4179 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4180 ("pmap_demote_pde: firstpte and newpte map different physical"
4184 * If the mapping has changed attributes, update the page table
4187 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4188 pmap_fill_ptp(firstpte, newpte);
4191 * The spare PV entries must be reserved prior to demoting the
4192 * mapping, that is, prior to changing the PDE. Otherwise, the state
4193 * of the PDE and the PV lists will be inconsistent, which can result
4194 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4195 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4196 * PV entry for the 2MB page mapping that is being demoted.
4198 if ((oldpde & PG_MANAGED) != 0)
4199 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4202 * Demote the mapping. This pmap is locked. The old PDE has
4203 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4204 * set. Thus, there is no danger of a race with another
4205 * processor changing the setting of PG_A and/or PG_M between
4206 * the read above and the store below.
4208 if (workaround_erratum383)
4209 pmap_update_pde(pmap, va, pde, newpde);
4211 pde_store(pde, newpde);
4214 * Invalidate a stale recursive mapping of the page table page.
4216 if (va >= VM_MAXUSER_ADDRESS)
4217 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4220 * Demote the PV entry.
4222 if ((oldpde & PG_MANAGED) != 0)
4223 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4225 atomic_add_long(&pmap_pde_demotions, 1);
4226 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
4227 " in pmap %p", va, pmap);
4232 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4235 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4241 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4242 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4243 mpte = pmap_remove_pt_page(pmap, va);
4245 panic("pmap_remove_kernel_pde: Missing pt page.");
4247 mptepa = VM_PAGE_TO_PHYS(mpte);
4248 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4251 * Initialize the page table page.
4253 pagezero((void *)PHYS_TO_DMAP(mptepa));
4256 * Demote the mapping.
4258 if (workaround_erratum383)
4259 pmap_update_pde(pmap, va, pde, newpde);
4261 pde_store(pde, newpde);
4264 * Invalidate a stale recursive mapping of the page table page.
4266 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4270 * pmap_remove_pde: do the things to unmap a superpage in a process
4273 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4274 struct spglist *free, struct rwlock **lockp)
4276 struct md_page *pvh;
4278 vm_offset_t eva, va;
4280 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4282 PG_G = pmap_global_bit(pmap);
4283 PG_A = pmap_accessed_bit(pmap);
4284 PG_M = pmap_modified_bit(pmap);
4285 PG_RW = pmap_rw_bit(pmap);
4287 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4288 KASSERT((sva & PDRMASK) == 0,
4289 ("pmap_remove_pde: sva is not 2mpage aligned"));
4290 oldpde = pte_load_clear(pdq);
4292 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4293 if ((oldpde & PG_G) != 0)
4294 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4295 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4296 if (oldpde & PG_MANAGED) {
4297 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4298 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4299 pmap_pvh_free(pvh, pmap, sva);
4301 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4302 va < eva; va += PAGE_SIZE, m++) {
4303 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4306 vm_page_aflag_set(m, PGA_REFERENCED);
4307 if (TAILQ_EMPTY(&m->md.pv_list) &&
4308 TAILQ_EMPTY(&pvh->pv_list))
4309 vm_page_aflag_clear(m, PGA_WRITEABLE);
4310 pmap_delayed_invl_page(m);
4313 if (pmap == kernel_pmap) {
4314 pmap_remove_kernel_pde(pmap, pdq, sva);
4316 mpte = pmap_remove_pt_page(pmap, sva);
4318 pmap_resident_count_dec(pmap, 1);
4319 KASSERT(mpte->wire_count == NPTEPG,
4320 ("pmap_remove_pde: pte page wire count error"));
4321 mpte->wire_count = 0;
4322 pmap_add_delayed_free_list(mpte, free, FALSE);
4325 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4329 * pmap_remove_pte: do the things to unmap a page in a process
4332 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4333 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4335 struct md_page *pvh;
4336 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4339 PG_A = pmap_accessed_bit(pmap);
4340 PG_M = pmap_modified_bit(pmap);
4341 PG_RW = pmap_rw_bit(pmap);
4343 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4344 oldpte = pte_load_clear(ptq);
4346 pmap->pm_stats.wired_count -= 1;
4347 pmap_resident_count_dec(pmap, 1);
4348 if (oldpte & PG_MANAGED) {
4349 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4350 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4353 vm_page_aflag_set(m, PGA_REFERENCED);
4354 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4355 pmap_pvh_free(&m->md, pmap, va);
4356 if (TAILQ_EMPTY(&m->md.pv_list) &&
4357 (m->flags & PG_FICTITIOUS) == 0) {
4358 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4359 if (TAILQ_EMPTY(&pvh->pv_list))
4360 vm_page_aflag_clear(m, PGA_WRITEABLE);
4362 pmap_delayed_invl_page(m);
4364 return (pmap_unuse_pt(pmap, va, ptepde, free));
4368 * Remove a single page from a process address space
4371 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4372 struct spglist *free)
4374 struct rwlock *lock;
4375 pt_entry_t *pte, PG_V;
4377 PG_V = pmap_valid_bit(pmap);
4378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4379 if ((*pde & PG_V) == 0)
4381 pte = pmap_pde_to_pte(pde, va);
4382 if ((*pte & PG_V) == 0)
4385 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4388 pmap_invalidate_page(pmap, va);
4392 * Removes the specified range of addresses from the page table page.
4395 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4396 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4398 pt_entry_t PG_G, *pte;
4402 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4403 PG_G = pmap_global_bit(pmap);
4406 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4410 pmap_invalidate_range(pmap, va, sva);
4415 if ((*pte & PG_G) == 0)
4419 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4425 pmap_invalidate_range(pmap, va, sva);
4430 * Remove the given range of addresses from the specified map.
4432 * It is assumed that the start and end are properly
4433 * rounded to the page size.
4436 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4438 struct rwlock *lock;
4439 vm_offset_t va_next;
4440 pml4_entry_t *pml4e;
4442 pd_entry_t ptpaddr, *pde;
4443 pt_entry_t PG_G, PG_V;
4444 struct spglist free;
4447 PG_G = pmap_global_bit(pmap);
4448 PG_V = pmap_valid_bit(pmap);
4451 * Perform an unsynchronized read. This is, however, safe.
4453 if (pmap->pm_stats.resident_count == 0)
4459 pmap_delayed_invl_started();
4463 * special handling of removing one page. a very
4464 * common operation and easy to short circuit some
4467 if (sva + PAGE_SIZE == eva) {
4468 pde = pmap_pde(pmap, sva);
4469 if (pde && (*pde & PG_PS) == 0) {
4470 pmap_remove_page(pmap, sva, pde, &free);
4476 for (; sva < eva; sva = va_next) {
4478 if (pmap->pm_stats.resident_count == 0)
4481 pml4e = pmap_pml4e(pmap, sva);
4482 if ((*pml4e & PG_V) == 0) {
4483 va_next = (sva + NBPML4) & ~PML4MASK;
4489 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4490 if ((*pdpe & PG_V) == 0) {
4491 va_next = (sva + NBPDP) & ~PDPMASK;
4498 * Calculate index for next page table.
4500 va_next = (sva + NBPDR) & ~PDRMASK;
4504 pde = pmap_pdpe_to_pde(pdpe, sva);
4508 * Weed out invalid mappings.
4514 * Check for large page.
4516 if ((ptpaddr & PG_PS) != 0) {
4518 * Are we removing the entire large page? If not,
4519 * demote the mapping and fall through.
4521 if (sva + NBPDR == va_next && eva >= va_next) {
4523 * The TLB entry for a PG_G mapping is
4524 * invalidated by pmap_remove_pde().
4526 if ((ptpaddr & PG_G) == 0)
4528 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4530 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4532 /* The large page mapping was destroyed. */
4539 * Limit our scan to either the end of the va represented
4540 * by the current page table page, or to the end of the
4541 * range being removed.
4546 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4553 pmap_invalidate_all(pmap);
4554 pmap_pkru_on_remove(pmap, sva, eva);
4556 pmap_delayed_invl_finished();
4557 vm_page_free_pages_toq(&free, true);
4561 * Routine: pmap_remove_all
4563 * Removes this physical page from
4564 * all physical maps in which it resides.
4565 * Reflects back modify bits to the pager.
4568 * Original versions of this routine were very
4569 * inefficient because they iteratively called
4570 * pmap_remove (slow...)
4574 pmap_remove_all(vm_page_t m)
4576 struct md_page *pvh;
4579 struct rwlock *lock;
4580 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4583 struct spglist free;
4584 int pvh_gen, md_gen;
4586 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4587 ("pmap_remove_all: page %p is not managed", m));
4589 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4590 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4591 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4594 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4596 if (!PMAP_TRYLOCK(pmap)) {
4597 pvh_gen = pvh->pv_gen;
4601 if (pvh_gen != pvh->pv_gen) {
4608 pde = pmap_pde(pmap, va);
4609 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4612 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4614 if (!PMAP_TRYLOCK(pmap)) {
4615 pvh_gen = pvh->pv_gen;
4616 md_gen = m->md.pv_gen;
4620 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4626 PG_A = pmap_accessed_bit(pmap);
4627 PG_M = pmap_modified_bit(pmap);
4628 PG_RW = pmap_rw_bit(pmap);
4629 pmap_resident_count_dec(pmap, 1);
4630 pde = pmap_pde(pmap, pv->pv_va);
4631 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4632 " a 2mpage in page %p's pv list", m));
4633 pte = pmap_pde_to_pte(pde, pv->pv_va);
4634 tpte = pte_load_clear(pte);
4636 pmap->pm_stats.wired_count--;
4638 vm_page_aflag_set(m, PGA_REFERENCED);
4641 * Update the vm_page_t clean and reference bits.
4643 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4645 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4646 pmap_invalidate_page(pmap, pv->pv_va);
4647 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4649 free_pv_entry(pmap, pv);
4652 vm_page_aflag_clear(m, PGA_WRITEABLE);
4654 pmap_delayed_invl_wait(m);
4655 vm_page_free_pages_toq(&free, true);
4659 * pmap_protect_pde: do the things to protect a 2mpage in a process
4662 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4664 pd_entry_t newpde, oldpde;
4665 vm_offset_t eva, va;
4667 boolean_t anychanged;
4668 pt_entry_t PG_G, PG_M, PG_RW;
4670 PG_G = pmap_global_bit(pmap);
4671 PG_M = pmap_modified_bit(pmap);
4672 PG_RW = pmap_rw_bit(pmap);
4674 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4675 KASSERT((sva & PDRMASK) == 0,
4676 ("pmap_protect_pde: sva is not 2mpage aligned"));
4679 oldpde = newpde = *pde;
4680 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4681 (PG_MANAGED | PG_M | PG_RW)) {
4683 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4684 va < eva; va += PAGE_SIZE, m++)
4687 if ((prot & VM_PROT_WRITE) == 0)
4688 newpde &= ~(PG_RW | PG_M);
4689 if ((prot & VM_PROT_EXECUTE) == 0)
4691 if (newpde != oldpde) {
4693 * As an optimization to future operations on this PDE, clear
4694 * PG_PROMOTED. The impending invalidation will remove any
4695 * lingering 4KB page mappings from the TLB.
4697 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4699 if ((oldpde & PG_G) != 0)
4700 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4704 return (anychanged);
4708 * Set the physical protection on the
4709 * specified range of this map as requested.
4712 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4714 vm_offset_t va_next;
4715 pml4_entry_t *pml4e;
4717 pd_entry_t ptpaddr, *pde;
4718 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4719 boolean_t anychanged;
4721 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4722 if (prot == VM_PROT_NONE) {
4723 pmap_remove(pmap, sva, eva);
4727 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4728 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4731 PG_G = pmap_global_bit(pmap);
4732 PG_M = pmap_modified_bit(pmap);
4733 PG_V = pmap_valid_bit(pmap);
4734 PG_RW = pmap_rw_bit(pmap);
4738 * Although this function delays and batches the invalidation
4739 * of stale TLB entries, it does not need to call
4740 * pmap_delayed_invl_started() and
4741 * pmap_delayed_invl_finished(), because it does not
4742 * ordinarily destroy mappings. Stale TLB entries from
4743 * protection-only changes need only be invalidated before the
4744 * pmap lock is released, because protection-only changes do
4745 * not destroy PV entries. Even operations that iterate over
4746 * a physical page's PV list of mappings, like
4747 * pmap_remove_write(), acquire the pmap lock for each
4748 * mapping. Consequently, for protection-only changes, the
4749 * pmap lock suffices to synchronize both page table and TLB
4752 * This function only destroys a mapping if pmap_demote_pde()
4753 * fails. In that case, stale TLB entries are immediately
4758 for (; sva < eva; sva = va_next) {
4760 pml4e = pmap_pml4e(pmap, sva);
4761 if ((*pml4e & PG_V) == 0) {
4762 va_next = (sva + NBPML4) & ~PML4MASK;
4768 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4769 if ((*pdpe & PG_V) == 0) {
4770 va_next = (sva + NBPDP) & ~PDPMASK;
4776 va_next = (sva + NBPDR) & ~PDRMASK;
4780 pde = pmap_pdpe_to_pde(pdpe, sva);
4784 * Weed out invalid mappings.
4790 * Check for large page.
4792 if ((ptpaddr & PG_PS) != 0) {
4794 * Are we protecting the entire large page? If not,
4795 * demote the mapping and fall through.
4797 if (sva + NBPDR == va_next && eva >= va_next) {
4799 * The TLB entry for a PG_G mapping is
4800 * invalidated by pmap_protect_pde().
4802 if (pmap_protect_pde(pmap, pde, sva, prot))
4805 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4807 * The large page mapping was destroyed.
4816 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4818 pt_entry_t obits, pbits;
4822 obits = pbits = *pte;
4823 if ((pbits & PG_V) == 0)
4826 if ((prot & VM_PROT_WRITE) == 0) {
4827 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4828 (PG_MANAGED | PG_M | PG_RW)) {
4829 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4832 pbits &= ~(PG_RW | PG_M);
4834 if ((prot & VM_PROT_EXECUTE) == 0)
4837 if (pbits != obits) {
4838 if (!atomic_cmpset_long(pte, obits, pbits))
4841 pmap_invalidate_page(pmap, sva);
4848 pmap_invalidate_all(pmap);
4852 #if VM_NRESERVLEVEL > 0
4854 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4855 * single page table page (PTP) to a single 2MB page mapping. For promotion
4856 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4857 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4858 * identical characteristics.
4861 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4862 struct rwlock **lockp)
4865 pt_entry_t *firstpte, oldpte, pa, *pte;
4866 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
4870 PG_A = pmap_accessed_bit(pmap);
4871 PG_G = pmap_global_bit(pmap);
4872 PG_M = pmap_modified_bit(pmap);
4873 PG_V = pmap_valid_bit(pmap);
4874 PG_RW = pmap_rw_bit(pmap);
4875 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4876 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4878 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4881 * Examine the first PTE in the specified PTP. Abort if this PTE is
4882 * either invalid, unused, or does not map the first 4KB physical page
4883 * within a 2MB page.
4885 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4888 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4889 atomic_add_long(&pmap_pde_p_failures, 1);
4890 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4891 " in pmap %p", va, pmap);
4894 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4896 * When PG_M is already clear, PG_RW can be cleared without
4897 * a TLB invalidation.
4899 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4905 * Examine each of the other PTEs in the specified PTP. Abort if this
4906 * PTE maps an unexpected 4KB physical page or does not have identical
4907 * characteristics to the first PTE.
4909 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4910 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4913 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4914 atomic_add_long(&pmap_pde_p_failures, 1);
4915 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4916 " in pmap %p", va, pmap);
4919 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4921 * When PG_M is already clear, PG_RW can be cleared
4922 * without a TLB invalidation.
4924 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4927 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4928 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4929 (va & ~PDRMASK), pmap);
4931 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4932 atomic_add_long(&pmap_pde_p_failures, 1);
4933 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4934 " in pmap %p", va, pmap);
4941 * Save the page table page in its current state until the PDE
4942 * mapping the superpage is demoted by pmap_demote_pde() or
4943 * destroyed by pmap_remove_pde().
4945 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4946 KASSERT(mpte >= vm_page_array &&
4947 mpte < &vm_page_array[vm_page_array_size],
4948 ("pmap_promote_pde: page table page is out of range"));
4949 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4950 ("pmap_promote_pde: page table page's pindex is wrong"));
4951 if (pmap_insert_pt_page(pmap, mpte)) {
4952 atomic_add_long(&pmap_pde_p_failures, 1);
4954 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4960 * Promote the pv entries.
4962 if ((newpde & PG_MANAGED) != 0)
4963 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4966 * Propagate the PAT index to its proper position.
4968 newpde = pmap_swap_pat(pmap, newpde);
4971 * Map the superpage.
4973 if (workaround_erratum383)
4974 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4976 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4978 atomic_add_long(&pmap_pde_promotions, 1);
4979 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4980 " in pmap %p", va, pmap);
4982 #endif /* VM_NRESERVLEVEL > 0 */
4985 * Insert the given physical page (p) at
4986 * the specified virtual address (v) in the
4987 * target physical map with the protection requested.
4989 * If specified, the page will be wired down, meaning
4990 * that the related pte can not be reclaimed.
4992 * NB: This is the only routine which MAY NOT lazy-evaluate
4993 * or lose information. That is, this routine must actually
4994 * insert this page into the given map NOW.
4996 * When destroying both a page table and PV entry, this function
4997 * performs the TLB invalidation before releasing the PV list
4998 * lock, so we do not need pmap_delayed_invl_page() calls here.
5001 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5002 u_int flags, int8_t psind)
5004 struct rwlock *lock;
5006 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5007 pt_entry_t newpte, origpte;
5014 PG_A = pmap_accessed_bit(pmap);
5015 PG_G = pmap_global_bit(pmap);
5016 PG_M = pmap_modified_bit(pmap);
5017 PG_V = pmap_valid_bit(pmap);
5018 PG_RW = pmap_rw_bit(pmap);
5020 va = trunc_page(va);
5021 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5022 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5023 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5025 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5026 va >= kmi.clean_eva,
5027 ("pmap_enter: managed mapping within the clean submap"));
5028 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5029 VM_OBJECT_ASSERT_LOCKED(m->object);
5030 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5031 ("pmap_enter: flags %u has reserved bits set", flags));
5032 pa = VM_PAGE_TO_PHYS(m);
5033 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5034 if ((flags & VM_PROT_WRITE) != 0)
5036 if ((prot & VM_PROT_WRITE) != 0)
5038 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5039 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5040 if ((prot & VM_PROT_EXECUTE) == 0)
5042 if ((flags & PMAP_ENTER_WIRED) != 0)
5044 if (va < VM_MAXUSER_ADDRESS)
5046 if (pmap == kernel_pmap)
5048 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5051 * Set modified bit gratuitously for writeable mappings if
5052 * the page is unmanaged. We do not want to take a fault
5053 * to do the dirty bit accounting for these mappings.
5055 if ((m->oflags & VPO_UNMANAGED) != 0) {
5056 if ((newpte & PG_RW) != 0)
5059 newpte |= PG_MANAGED;
5064 /* Assert the required virtual and physical alignment. */
5065 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5066 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5067 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5073 * In the case that a page table page is not
5074 * resident, we are creating it here.
5077 pde = pmap_pde(pmap, va);
5078 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5079 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5080 pte = pmap_pde_to_pte(pde, va);
5081 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5082 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5085 } else if (va < VM_MAXUSER_ADDRESS) {
5087 * Here if the pte page isn't mapped, or if it has been
5090 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5091 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5092 nosleep ? NULL : &lock);
5093 if (mpte == NULL && nosleep) {
5094 rv = KERN_RESOURCE_SHORTAGE;
5099 panic("pmap_enter: invalid page directory va=%#lx", va);
5103 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5104 newpte |= pmap_pkru_get(pmap, va);
5107 * Is the specified virtual address already mapped?
5109 if ((origpte & PG_V) != 0) {
5111 * Wiring change, just update stats. We don't worry about
5112 * wiring PT pages as they remain resident as long as there
5113 * are valid mappings in them. Hence, if a user page is wired,
5114 * the PT page will be also.
5116 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5117 pmap->pm_stats.wired_count++;
5118 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5119 pmap->pm_stats.wired_count--;
5122 * Remove the extra PT page reference.
5126 KASSERT(mpte->wire_count > 0,
5127 ("pmap_enter: missing reference to page table page,"
5132 * Has the physical page changed?
5134 opa = origpte & PG_FRAME;
5137 * No, might be a protection or wiring change.
5139 if ((origpte & PG_MANAGED) != 0 &&
5140 (newpte & PG_RW) != 0)
5141 vm_page_aflag_set(m, PGA_WRITEABLE);
5142 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5148 * The physical page has changed. Temporarily invalidate
5149 * the mapping. This ensures that all threads sharing the
5150 * pmap keep a consistent view of the mapping, which is
5151 * necessary for the correct handling of COW faults. It
5152 * also permits reuse of the old mapping's PV entry,
5153 * avoiding an allocation.
5155 * For consistency, handle unmanaged mappings the same way.
5157 origpte = pte_load_clear(pte);
5158 KASSERT((origpte & PG_FRAME) == opa,
5159 ("pmap_enter: unexpected pa update for %#lx", va));
5160 if ((origpte & PG_MANAGED) != 0) {
5161 om = PHYS_TO_VM_PAGE(opa);
5164 * The pmap lock is sufficient to synchronize with
5165 * concurrent calls to pmap_page_test_mappings() and
5166 * pmap_ts_referenced().
5168 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5170 if ((origpte & PG_A) != 0)
5171 vm_page_aflag_set(om, PGA_REFERENCED);
5172 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5173 pv = pmap_pvh_remove(&om->md, pmap, va);
5175 ("pmap_enter: no PV entry for %#lx", va));
5176 if ((newpte & PG_MANAGED) == 0)
5177 free_pv_entry(pmap, pv);
5178 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5179 TAILQ_EMPTY(&om->md.pv_list) &&
5180 ((om->flags & PG_FICTITIOUS) != 0 ||
5181 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5182 vm_page_aflag_clear(om, PGA_WRITEABLE);
5184 if ((origpte & PG_A) != 0)
5185 pmap_invalidate_page(pmap, va);
5189 * Increment the counters.
5191 if ((newpte & PG_W) != 0)
5192 pmap->pm_stats.wired_count++;
5193 pmap_resident_count_inc(pmap, 1);
5197 * Enter on the PV list if part of our managed memory.
5199 if ((newpte & PG_MANAGED) != 0) {
5201 pv = get_pv_entry(pmap, &lock);
5204 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5205 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5207 if ((newpte & PG_RW) != 0)
5208 vm_page_aflag_set(m, PGA_WRITEABLE);
5214 if ((origpte & PG_V) != 0) {
5216 origpte = pte_load_store(pte, newpte);
5217 KASSERT((origpte & PG_FRAME) == pa,
5218 ("pmap_enter: unexpected pa update for %#lx", va));
5219 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5221 if ((origpte & PG_MANAGED) != 0)
5225 * Although the PTE may still have PG_RW set, TLB
5226 * invalidation may nonetheless be required because
5227 * the PTE no longer has PG_M set.
5229 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5231 * This PTE change does not require TLB invalidation.
5235 if ((origpte & PG_A) != 0)
5236 pmap_invalidate_page(pmap, va);
5238 pte_store(pte, newpte);
5242 #if VM_NRESERVLEVEL > 0
5244 * If both the page table page and the reservation are fully
5245 * populated, then attempt promotion.
5247 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5248 pmap_ps_enabled(pmap) &&
5249 (m->flags & PG_FICTITIOUS) == 0 &&
5250 vm_reserv_level_iffullpop(m) == 0)
5251 pmap_promote_pde(pmap, pde, va, &lock);
5263 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5264 * if successful. Returns false if (1) a page table page cannot be allocated
5265 * without sleeping, (2) a mapping already exists at the specified virtual
5266 * address, or (3) a PV entry cannot be allocated without reclaiming another
5270 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5271 struct rwlock **lockp)
5276 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5277 PG_V = pmap_valid_bit(pmap);
5278 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5280 if ((m->oflags & VPO_UNMANAGED) == 0)
5281 newpde |= PG_MANAGED;
5282 if ((prot & VM_PROT_EXECUTE) == 0)
5284 if (va < VM_MAXUSER_ADDRESS)
5286 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5287 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5292 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5293 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5294 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5295 * a mapping already exists at the specified virtual address. Returns
5296 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5297 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5298 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5300 * The parameter "m" is only used when creating a managed, writeable mapping.
5303 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5304 vm_page_t m, struct rwlock **lockp)
5306 struct spglist free;
5307 pd_entry_t oldpde, *pde;
5308 pt_entry_t PG_G, PG_RW, PG_V;
5311 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
5312 ("pmap_enter_pde: cannot create wired user mapping"));
5313 PG_G = pmap_global_bit(pmap);
5314 PG_RW = pmap_rw_bit(pmap);
5315 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5316 ("pmap_enter_pde: newpde is missing PG_M"));
5317 PG_V = pmap_valid_bit(pmap);
5318 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5320 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5321 NULL : lockp)) == NULL) {
5322 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5323 " in pmap %p", va, pmap);
5324 return (KERN_RESOURCE_SHORTAGE);
5328 * If pkru is not same for the whole pde range, return failure
5329 * and let vm_fault() cope. Check after pde allocation, since
5332 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5334 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5335 pmap_invalidate_page(pmap, va);
5336 vm_page_free_pages_toq(&free, true);
5338 return (KERN_FAILURE);
5340 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5341 newpde &= ~X86_PG_PKU_MASK;
5342 newpde |= pmap_pkru_get(pmap, va);
5345 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5346 pde = &pde[pmap_pde_index(va)];
5348 if ((oldpde & PG_V) != 0) {
5349 KASSERT(pdpg->wire_count > 1,
5350 ("pmap_enter_pde: pdpg's wire count is too low"));
5351 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5353 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5354 " in pmap %p", va, pmap);
5355 return (KERN_FAILURE);
5357 /* Break the existing mapping(s). */
5359 if ((oldpde & PG_PS) != 0) {
5361 * The reference to the PD page that was acquired by
5362 * pmap_allocpde() ensures that it won't be freed.
5363 * However, if the PDE resulted from a promotion, then
5364 * a reserved PT page could be freed.
5366 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5367 if ((oldpde & PG_G) == 0)
5368 pmap_invalidate_pde_page(pmap, va, oldpde);
5370 pmap_delayed_invl_started();
5371 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5373 pmap_invalidate_all(pmap);
5374 pmap_delayed_invl_finished();
5376 vm_page_free_pages_toq(&free, true);
5377 if (va >= VM_MAXUSER_ADDRESS) {
5378 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5379 if (pmap_insert_pt_page(pmap, mt)) {
5381 * XXX Currently, this can't happen because
5382 * we do not perform pmap_enter(psind == 1)
5383 * on the kernel pmap.
5385 panic("pmap_enter_pde: trie insert failed");
5388 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5391 if ((newpde & PG_MANAGED) != 0) {
5393 * Abort this mapping if its PV entry could not be created.
5395 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5397 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5399 * Although "va" is not mapped, paging-
5400 * structure caches could nonetheless have
5401 * entries that refer to the freed page table
5402 * pages. Invalidate those entries.
5404 pmap_invalidate_page(pmap, va);
5405 vm_page_free_pages_toq(&free, true);
5407 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5408 " in pmap %p", va, pmap);
5409 return (KERN_RESOURCE_SHORTAGE);
5411 if ((newpde & PG_RW) != 0) {
5412 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5413 vm_page_aflag_set(mt, PGA_WRITEABLE);
5418 * Increment counters.
5420 if ((newpde & PG_W) != 0)
5421 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5422 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5425 * Map the superpage. (This is not a promoted mapping; there will not
5426 * be any lingering 4KB page mappings in the TLB.)
5428 pde_store(pde, newpde);
5430 atomic_add_long(&pmap_pde_mappings, 1);
5431 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5432 " in pmap %p", va, pmap);
5433 return (KERN_SUCCESS);
5437 * Maps a sequence of resident pages belonging to the same object.
5438 * The sequence begins with the given page m_start. This page is
5439 * mapped at the given virtual address start. Each subsequent page is
5440 * mapped at a virtual address that is offset from start by the same
5441 * amount as the page is offset from m_start within the object. The
5442 * last page in the sequence is the page with the largest offset from
5443 * m_start that can be mapped at a virtual address less than the given
5444 * virtual address end. Not every virtual page between start and end
5445 * is mapped; only those for which a resident page exists with the
5446 * corresponding offset from m_start are mapped.
5449 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5450 vm_page_t m_start, vm_prot_t prot)
5452 struct rwlock *lock;
5455 vm_pindex_t diff, psize;
5457 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5459 psize = atop(end - start);
5464 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5465 va = start + ptoa(diff);
5466 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5467 m->psind == 1 && pmap_ps_enabled(pmap) &&
5468 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5469 m = &m[NBPDR / PAGE_SIZE - 1];
5471 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5473 m = TAILQ_NEXT(m, listq);
5481 * this code makes some *MAJOR* assumptions:
5482 * 1. Current pmap & pmap exists.
5485 * 4. No page table pages.
5486 * but is *MUCH* faster than pmap_enter...
5490 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5492 struct rwlock *lock;
5496 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5503 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5504 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5506 struct spglist free;
5507 pt_entry_t newpte, *pte, PG_V;
5509 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5510 (m->oflags & VPO_UNMANAGED) != 0,
5511 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5512 PG_V = pmap_valid_bit(pmap);
5513 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5516 * In the case that a page table page is not
5517 * resident, we are creating it here.
5519 if (va < VM_MAXUSER_ADDRESS) {
5520 vm_pindex_t ptepindex;
5524 * Calculate pagetable page index
5526 ptepindex = pmap_pde_pindex(va);
5527 if (mpte && (mpte->pindex == ptepindex)) {
5531 * Get the page directory entry
5533 ptepa = pmap_pde(pmap, va);
5536 * If the page table page is mapped, we just increment
5537 * the hold count, and activate it. Otherwise, we
5538 * attempt to allocate a page table page. If this
5539 * attempt fails, we don't retry. Instead, we give up.
5541 if (ptepa && (*ptepa & PG_V) != 0) {
5544 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5548 * Pass NULL instead of the PV list lock
5549 * pointer, because we don't intend to sleep.
5551 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5556 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5557 pte = &pte[pmap_pte_index(va)];
5571 * Enter on the PV list if part of our managed memory.
5573 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5574 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5577 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5579 * Although "va" is not mapped, paging-
5580 * structure caches could nonetheless have
5581 * entries that refer to the freed page table
5582 * pages. Invalidate those entries.
5584 pmap_invalidate_page(pmap, va);
5585 vm_page_free_pages_toq(&free, true);
5593 * Increment counters
5595 pmap_resident_count_inc(pmap, 1);
5597 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
5598 pmap_cache_bits(pmap, m->md.pat_mode, 0);
5599 if ((m->oflags & VPO_UNMANAGED) == 0)
5600 newpte |= PG_MANAGED;
5601 if ((prot & VM_PROT_EXECUTE) == 0)
5603 if (va < VM_MAXUSER_ADDRESS)
5604 newpte |= PG_U | pmap_pkru_get(pmap, va);
5605 pte_store(pte, newpte);
5610 * Make a temporary mapping for a physical address. This is only intended
5611 * to be used for panic dumps.
5614 pmap_kenter_temporary(vm_paddr_t pa, int i)
5618 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5619 pmap_kenter(va, pa);
5621 return ((void *)crashdumpmap);
5625 * This code maps large physical mmap regions into the
5626 * processor address space. Note that some shortcuts
5627 * are taken, but the code works.
5630 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5631 vm_pindex_t pindex, vm_size_t size)
5634 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5635 vm_paddr_t pa, ptepa;
5639 PG_A = pmap_accessed_bit(pmap);
5640 PG_M = pmap_modified_bit(pmap);
5641 PG_V = pmap_valid_bit(pmap);
5642 PG_RW = pmap_rw_bit(pmap);
5644 VM_OBJECT_ASSERT_WLOCKED(object);
5645 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5646 ("pmap_object_init_pt: non-device object"));
5647 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5648 if (!pmap_ps_enabled(pmap))
5650 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5652 p = vm_page_lookup(object, pindex);
5653 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5654 ("pmap_object_init_pt: invalid page %p", p));
5655 pat_mode = p->md.pat_mode;
5658 * Abort the mapping if the first page is not physically
5659 * aligned to a 2MB page boundary.
5661 ptepa = VM_PAGE_TO_PHYS(p);
5662 if (ptepa & (NBPDR - 1))
5666 * Skip the first page. Abort the mapping if the rest of
5667 * the pages are not physically contiguous or have differing
5668 * memory attributes.
5670 p = TAILQ_NEXT(p, listq);
5671 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5673 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5674 ("pmap_object_init_pt: invalid page %p", p));
5675 if (pa != VM_PAGE_TO_PHYS(p) ||
5676 pat_mode != p->md.pat_mode)
5678 p = TAILQ_NEXT(p, listq);
5682 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5683 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5684 * will not affect the termination of this loop.
5687 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5688 pa < ptepa + size; pa += NBPDR) {
5689 pdpg = pmap_allocpde(pmap, addr, NULL);
5692 * The creation of mappings below is only an
5693 * optimization. If a page directory page
5694 * cannot be allocated without blocking,
5695 * continue on to the next mapping rather than
5701 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5702 pde = &pde[pmap_pde_index(addr)];
5703 if ((*pde & PG_V) == 0) {
5704 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5705 PG_U | PG_RW | PG_V);
5706 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5707 atomic_add_long(&pmap_pde_mappings, 1);
5709 /* Continue on if the PDE is already valid. */
5711 KASSERT(pdpg->wire_count > 0,
5712 ("pmap_object_init_pt: missing reference "
5713 "to page directory page, va: 0x%lx", addr));
5722 * Clear the wired attribute from the mappings for the specified range of
5723 * addresses in the given pmap. Every valid mapping within that range
5724 * must have the wired attribute set. In contrast, invalid mappings
5725 * cannot have the wired attribute set, so they are ignored.
5727 * The wired attribute of the page table entry is not a hardware
5728 * feature, so there is no need to invalidate any TLB entries.
5729 * Since pmap_demote_pde() for the wired entry must never fail,
5730 * pmap_delayed_invl_started()/finished() calls around the
5731 * function are not needed.
5734 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5736 vm_offset_t va_next;
5737 pml4_entry_t *pml4e;
5740 pt_entry_t *pte, PG_V;
5742 PG_V = pmap_valid_bit(pmap);
5744 for (; sva < eva; sva = va_next) {
5745 pml4e = pmap_pml4e(pmap, sva);
5746 if ((*pml4e & PG_V) == 0) {
5747 va_next = (sva + NBPML4) & ~PML4MASK;
5752 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5753 if ((*pdpe & PG_V) == 0) {
5754 va_next = (sva + NBPDP) & ~PDPMASK;
5759 va_next = (sva + NBPDR) & ~PDRMASK;
5762 pde = pmap_pdpe_to_pde(pdpe, sva);
5763 if ((*pde & PG_V) == 0)
5765 if ((*pde & PG_PS) != 0) {
5766 if ((*pde & PG_W) == 0)
5767 panic("pmap_unwire: pde %#jx is missing PG_W",
5771 * Are we unwiring the entire large page? If not,
5772 * demote the mapping and fall through.
5774 if (sva + NBPDR == va_next && eva >= va_next) {
5775 atomic_clear_long(pde, PG_W);
5776 pmap->pm_stats.wired_count -= NBPDR /
5779 } else if (!pmap_demote_pde(pmap, pde, sva))
5780 panic("pmap_unwire: demotion failed");
5784 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5786 if ((*pte & PG_V) == 0)
5788 if ((*pte & PG_W) == 0)
5789 panic("pmap_unwire: pte %#jx is missing PG_W",
5793 * PG_W must be cleared atomically. Although the pmap
5794 * lock synchronizes access to PG_W, another processor
5795 * could be setting PG_M and/or PG_A concurrently.
5797 atomic_clear_long(pte, PG_W);
5798 pmap->pm_stats.wired_count--;
5805 * Copy the range specified by src_addr/len
5806 * from the source map to the range dst_addr/len
5807 * in the destination map.
5809 * This routine is only advisory and need not do anything.
5813 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5814 vm_offset_t src_addr)
5816 struct rwlock *lock;
5817 struct spglist free;
5819 vm_offset_t end_addr = src_addr + len;
5820 vm_offset_t va_next;
5821 vm_page_t dst_pdpg, dstmpte, srcmpte;
5822 pt_entry_t PG_A, PG_M, PG_V;
5824 if (dst_addr != src_addr)
5827 if (dst_pmap->pm_type != src_pmap->pm_type)
5831 * EPT page table entries that require emulation of A/D bits are
5832 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5833 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5834 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5835 * implementations flag an EPT misconfiguration for exec-only
5836 * mappings we skip this function entirely for emulated pmaps.
5838 if (pmap_emulate_ad_bits(dst_pmap))
5842 if (dst_pmap < src_pmap) {
5843 PMAP_LOCK(dst_pmap);
5844 PMAP_LOCK(src_pmap);
5846 PMAP_LOCK(src_pmap);
5847 PMAP_LOCK(dst_pmap);
5850 PG_A = pmap_accessed_bit(dst_pmap);
5851 PG_M = pmap_modified_bit(dst_pmap);
5852 PG_V = pmap_valid_bit(dst_pmap);
5854 for (addr = src_addr; addr < end_addr; addr = va_next) {
5855 pt_entry_t *src_pte, *dst_pte;
5856 pml4_entry_t *pml4e;
5858 pd_entry_t srcptepaddr, *pde;
5860 KASSERT(addr < UPT_MIN_ADDRESS,
5861 ("pmap_copy: invalid to pmap_copy page tables"));
5863 pml4e = pmap_pml4e(src_pmap, addr);
5864 if ((*pml4e & PG_V) == 0) {
5865 va_next = (addr + NBPML4) & ~PML4MASK;
5871 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5872 if ((*pdpe & PG_V) == 0) {
5873 va_next = (addr + NBPDP) & ~PDPMASK;
5879 va_next = (addr + NBPDR) & ~PDRMASK;
5883 pde = pmap_pdpe_to_pde(pdpe, addr);
5885 if (srcptepaddr == 0)
5888 if (srcptepaddr & PG_PS) {
5889 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5891 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5892 if (dst_pdpg == NULL)
5894 pde = (pd_entry_t *)
5895 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5896 pde = &pde[pmap_pde_index(addr)];
5897 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5898 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5899 PMAP_ENTER_NORECLAIM, &lock))) {
5900 *pde = srcptepaddr & ~PG_W;
5901 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5902 atomic_add_long(&pmap_pde_mappings, 1);
5904 dst_pdpg->wire_count--;
5908 srcptepaddr &= PG_FRAME;
5909 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5910 KASSERT(srcmpte->wire_count > 0,
5911 ("pmap_copy: source page table page is unused"));
5913 if (va_next > end_addr)
5916 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5917 src_pte = &src_pte[pmap_pte_index(addr)];
5919 while (addr < va_next) {
5923 * we only virtual copy managed pages
5925 if ((ptetemp & PG_MANAGED) != 0) {
5926 if (dstmpte != NULL &&
5927 dstmpte->pindex == pmap_pde_pindex(addr))
5928 dstmpte->wire_count++;
5929 else if ((dstmpte = pmap_allocpte(dst_pmap,
5930 addr, NULL)) == NULL)
5932 dst_pte = (pt_entry_t *)
5933 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5934 dst_pte = &dst_pte[pmap_pte_index(addr)];
5935 if (*dst_pte == 0 &&
5936 pmap_try_insert_pv_entry(dst_pmap, addr,
5937 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5940 * Clear the wired, modified, and
5941 * accessed (referenced) bits
5944 *dst_pte = ptetemp & ~(PG_W | PG_M |
5946 pmap_resident_count_inc(dst_pmap, 1);
5949 if (pmap_unwire_ptp(dst_pmap, addr,
5952 * Although "addr" is not
5953 * mapped, paging-structure
5954 * caches could nonetheless
5955 * have entries that refer to
5956 * the freed page table pages.
5957 * Invalidate those entries.
5959 pmap_invalidate_page(dst_pmap,
5961 vm_page_free_pages_toq(&free,
5966 if (dstmpte->wire_count >= srcmpte->wire_count)
5976 PMAP_UNLOCK(src_pmap);
5977 PMAP_UNLOCK(dst_pmap);
5981 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
5985 if (dst_pmap->pm_type != src_pmap->pm_type ||
5986 dst_pmap->pm_type != PT_X86 ||
5987 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
5990 if (dst_pmap < src_pmap) {
5991 PMAP_LOCK(dst_pmap);
5992 PMAP_LOCK(src_pmap);
5994 PMAP_LOCK(src_pmap);
5995 PMAP_LOCK(dst_pmap);
5997 error = pmap_pkru_copy(dst_pmap, src_pmap);
5998 /* Clean up partial copy on failure due to no memory. */
5999 if (error == ENOMEM)
6000 pmap_pkru_deassign_all(dst_pmap);
6001 PMAP_UNLOCK(src_pmap);
6002 PMAP_UNLOCK(dst_pmap);
6003 if (error != ENOMEM)
6011 * Zero the specified hardware page.
6014 pmap_zero_page(vm_page_t m)
6016 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6018 pagezero((void *)va);
6022 * Zero an an area within a single hardware page. off and size must not
6023 * cover an area beyond a single hardware page.
6026 pmap_zero_page_area(vm_page_t m, int off, int size)
6028 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6030 if (off == 0 && size == PAGE_SIZE)
6031 pagezero((void *)va);
6033 bzero((char *)va + off, size);
6037 * Copy 1 specified hardware page to another.
6040 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6042 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6043 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6045 pagecopy((void *)src, (void *)dst);
6048 int unmapped_buf_allowed = 1;
6051 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6052 vm_offset_t b_offset, int xfersize)
6056 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6060 while (xfersize > 0) {
6061 a_pg_offset = a_offset & PAGE_MASK;
6062 pages[0] = ma[a_offset >> PAGE_SHIFT];
6063 b_pg_offset = b_offset & PAGE_MASK;
6064 pages[1] = mb[b_offset >> PAGE_SHIFT];
6065 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6066 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6067 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6068 a_cp = (char *)vaddr[0] + a_pg_offset;
6069 b_cp = (char *)vaddr[1] + b_pg_offset;
6070 bcopy(a_cp, b_cp, cnt);
6071 if (__predict_false(mapped))
6072 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6080 * Returns true if the pmap's pv is one of the first
6081 * 16 pvs linked to from this page. This count may
6082 * be changed upwards or downwards in the future; it
6083 * is only necessary that true be returned for a small
6084 * subset of pmaps for proper page aging.
6087 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6089 struct md_page *pvh;
6090 struct rwlock *lock;
6095 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6096 ("pmap_page_exists_quick: page %p is not managed", m));
6098 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6100 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6101 if (PV_PMAP(pv) == pmap) {
6109 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6110 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6111 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6112 if (PV_PMAP(pv) == pmap) {
6126 * pmap_page_wired_mappings:
6128 * Return the number of managed mappings to the given physical page
6132 pmap_page_wired_mappings(vm_page_t m)
6134 struct rwlock *lock;
6135 struct md_page *pvh;
6139 int count, md_gen, pvh_gen;
6141 if ((m->oflags & VPO_UNMANAGED) != 0)
6143 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6147 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6149 if (!PMAP_TRYLOCK(pmap)) {
6150 md_gen = m->md.pv_gen;
6154 if (md_gen != m->md.pv_gen) {
6159 pte = pmap_pte(pmap, pv->pv_va);
6160 if ((*pte & PG_W) != 0)
6164 if ((m->flags & PG_FICTITIOUS) == 0) {
6165 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6166 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6168 if (!PMAP_TRYLOCK(pmap)) {
6169 md_gen = m->md.pv_gen;
6170 pvh_gen = pvh->pv_gen;
6174 if (md_gen != m->md.pv_gen ||
6175 pvh_gen != pvh->pv_gen) {
6180 pte = pmap_pde(pmap, pv->pv_va);
6181 if ((*pte & PG_W) != 0)
6191 * Returns TRUE if the given page is mapped individually or as part of
6192 * a 2mpage. Otherwise, returns FALSE.
6195 pmap_page_is_mapped(vm_page_t m)
6197 struct rwlock *lock;
6200 if ((m->oflags & VPO_UNMANAGED) != 0)
6202 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6204 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6205 ((m->flags & PG_FICTITIOUS) == 0 &&
6206 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6212 * Destroy all managed, non-wired mappings in the given user-space
6213 * pmap. This pmap cannot be active on any processor besides the
6216 * This function cannot be applied to the kernel pmap. Moreover, it
6217 * is not intended for general use. It is only to be used during
6218 * process termination. Consequently, it can be implemented in ways
6219 * that make it faster than pmap_remove(). First, it can more quickly
6220 * destroy mappings by iterating over the pmap's collection of PV
6221 * entries, rather than searching the page table. Second, it doesn't
6222 * have to test and clear the page table entries atomically, because
6223 * no processor is currently accessing the user address space. In
6224 * particular, a page table entry's dirty bit won't change state once
6225 * this function starts.
6227 * Although this function destroys all of the pmap's managed,
6228 * non-wired mappings, it can delay and batch the invalidation of TLB
6229 * entries without calling pmap_delayed_invl_started() and
6230 * pmap_delayed_invl_finished(). Because the pmap is not active on
6231 * any other processor, none of these TLB entries will ever be used
6232 * before their eventual invalidation. Consequently, there is no need
6233 * for either pmap_remove_all() or pmap_remove_write() to wait for
6234 * that eventual TLB invalidation.
6237 pmap_remove_pages(pmap_t pmap)
6240 pt_entry_t *pte, tpte;
6241 pt_entry_t PG_M, PG_RW, PG_V;
6242 struct spglist free;
6243 vm_page_t m, mpte, mt;
6245 struct md_page *pvh;
6246 struct pv_chunk *pc, *npc;
6247 struct rwlock *lock;
6249 uint64_t inuse, bitmask;
6250 int allfree, field, freed, idx;
6251 boolean_t superpage;
6255 * Assert that the given pmap is only active on the current
6256 * CPU. Unfortunately, we cannot block another CPU from
6257 * activating the pmap while this function is executing.
6259 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6262 cpuset_t other_cpus;
6264 other_cpus = all_cpus;
6266 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6267 CPU_AND(&other_cpus, &pmap->pm_active);
6269 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6274 PG_M = pmap_modified_bit(pmap);
6275 PG_V = pmap_valid_bit(pmap);
6276 PG_RW = pmap_rw_bit(pmap);
6280 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6283 for (field = 0; field < _NPCM; field++) {
6284 inuse = ~pc->pc_map[field] & pc_freemask[field];
6285 while (inuse != 0) {
6287 bitmask = 1UL << bit;
6288 idx = field * 64 + bit;
6289 pv = &pc->pc_pventry[idx];
6292 pte = pmap_pdpe(pmap, pv->pv_va);
6294 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6296 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6299 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6301 pte = &pte[pmap_pte_index(pv->pv_va)];
6305 * Keep track whether 'tpte' is a
6306 * superpage explicitly instead of
6307 * relying on PG_PS being set.
6309 * This is because PG_PS is numerically
6310 * identical to PG_PTE_PAT and thus a
6311 * regular page could be mistaken for
6317 if ((tpte & PG_V) == 0) {
6318 panic("bad pte va %lx pte %lx",
6323 * We cannot remove wired pages from a process' mapping at this time
6331 pa = tpte & PG_PS_FRAME;
6333 pa = tpte & PG_FRAME;
6335 m = PHYS_TO_VM_PAGE(pa);
6336 KASSERT(m->phys_addr == pa,
6337 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6338 m, (uintmax_t)m->phys_addr,
6341 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6342 m < &vm_page_array[vm_page_array_size],
6343 ("pmap_remove_pages: bad tpte %#jx",
6349 * Update the vm_page_t clean/reference bits.
6351 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6353 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6359 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6362 pc->pc_map[field] |= bitmask;
6364 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6365 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6366 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6368 if (TAILQ_EMPTY(&pvh->pv_list)) {
6369 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6370 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6371 TAILQ_EMPTY(&mt->md.pv_list))
6372 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6374 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6376 pmap_resident_count_dec(pmap, 1);
6377 KASSERT(mpte->wire_count == NPTEPG,
6378 ("pmap_remove_pages: pte page wire count error"));
6379 mpte->wire_count = 0;
6380 pmap_add_delayed_free_list(mpte, &free, FALSE);
6383 pmap_resident_count_dec(pmap, 1);
6384 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6386 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6387 TAILQ_EMPTY(&m->md.pv_list) &&
6388 (m->flags & PG_FICTITIOUS) == 0) {
6389 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6390 if (TAILQ_EMPTY(&pvh->pv_list))
6391 vm_page_aflag_clear(m, PGA_WRITEABLE);
6394 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6398 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6399 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6400 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6402 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6408 pmap_invalidate_all(pmap);
6409 pmap_pkru_deassign_all(pmap);
6411 vm_page_free_pages_toq(&free, true);
6415 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6417 struct rwlock *lock;
6419 struct md_page *pvh;
6420 pt_entry_t *pte, mask;
6421 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6423 int md_gen, pvh_gen;
6427 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6430 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6432 if (!PMAP_TRYLOCK(pmap)) {
6433 md_gen = m->md.pv_gen;
6437 if (md_gen != m->md.pv_gen) {
6442 pte = pmap_pte(pmap, pv->pv_va);
6445 PG_M = pmap_modified_bit(pmap);
6446 PG_RW = pmap_rw_bit(pmap);
6447 mask |= PG_RW | PG_M;
6450 PG_A = pmap_accessed_bit(pmap);
6451 PG_V = pmap_valid_bit(pmap);
6452 mask |= PG_V | PG_A;
6454 rv = (*pte & mask) == mask;
6459 if ((m->flags & PG_FICTITIOUS) == 0) {
6460 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6461 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6463 if (!PMAP_TRYLOCK(pmap)) {
6464 md_gen = m->md.pv_gen;
6465 pvh_gen = pvh->pv_gen;
6469 if (md_gen != m->md.pv_gen ||
6470 pvh_gen != pvh->pv_gen) {
6475 pte = pmap_pde(pmap, pv->pv_va);
6478 PG_M = pmap_modified_bit(pmap);
6479 PG_RW = pmap_rw_bit(pmap);
6480 mask |= PG_RW | PG_M;
6483 PG_A = pmap_accessed_bit(pmap);
6484 PG_V = pmap_valid_bit(pmap);
6485 mask |= PG_V | PG_A;
6487 rv = (*pte & mask) == mask;
6501 * Return whether or not the specified physical page was modified
6502 * in any physical maps.
6505 pmap_is_modified(vm_page_t m)
6508 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6509 ("pmap_is_modified: page %p is not managed", m));
6512 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6513 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6514 * is clear, no PTEs can have PG_M set.
6516 VM_OBJECT_ASSERT_WLOCKED(m->object);
6517 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6519 return (pmap_page_test_mappings(m, FALSE, TRUE));
6523 * pmap_is_prefaultable:
6525 * Return whether or not the specified virtual address is eligible
6529 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6532 pt_entry_t *pte, PG_V;
6535 PG_V = pmap_valid_bit(pmap);
6538 pde = pmap_pde(pmap, addr);
6539 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6540 pte = pmap_pde_to_pte(pde, addr);
6541 rv = (*pte & PG_V) == 0;
6548 * pmap_is_referenced:
6550 * Return whether or not the specified physical page was referenced
6551 * in any physical maps.
6554 pmap_is_referenced(vm_page_t m)
6557 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6558 ("pmap_is_referenced: page %p is not managed", m));
6559 return (pmap_page_test_mappings(m, TRUE, FALSE));
6563 * Clear the write and modified bits in each of the given page's mappings.
6566 pmap_remove_write(vm_page_t m)
6568 struct md_page *pvh;
6570 struct rwlock *lock;
6571 pv_entry_t next_pv, pv;
6573 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6575 int pvh_gen, md_gen;
6577 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6578 ("pmap_remove_write: page %p is not managed", m));
6581 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6582 * set by another thread while the object is locked. Thus,
6583 * if PGA_WRITEABLE is clear, no page table entries need updating.
6585 VM_OBJECT_ASSERT_WLOCKED(m->object);
6586 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6588 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6589 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6590 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6593 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6595 if (!PMAP_TRYLOCK(pmap)) {
6596 pvh_gen = pvh->pv_gen;
6600 if (pvh_gen != pvh->pv_gen) {
6606 PG_RW = pmap_rw_bit(pmap);
6608 pde = pmap_pde(pmap, va);
6609 if ((*pde & PG_RW) != 0)
6610 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6611 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6612 ("inconsistent pv lock %p %p for page %p",
6613 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6616 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6618 if (!PMAP_TRYLOCK(pmap)) {
6619 pvh_gen = pvh->pv_gen;
6620 md_gen = m->md.pv_gen;
6624 if (pvh_gen != pvh->pv_gen ||
6625 md_gen != m->md.pv_gen) {
6631 PG_M = pmap_modified_bit(pmap);
6632 PG_RW = pmap_rw_bit(pmap);
6633 pde = pmap_pde(pmap, pv->pv_va);
6634 KASSERT((*pde & PG_PS) == 0,
6635 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6637 pte = pmap_pde_to_pte(pde, pv->pv_va);
6640 if (oldpte & PG_RW) {
6641 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6644 if ((oldpte & PG_M) != 0)
6646 pmap_invalidate_page(pmap, pv->pv_va);
6651 vm_page_aflag_clear(m, PGA_WRITEABLE);
6652 pmap_delayed_invl_wait(m);
6655 static __inline boolean_t
6656 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6659 if (!pmap_emulate_ad_bits(pmap))
6662 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6665 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6666 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6667 * if the EPT_PG_WRITE bit is set.
6669 if ((pte & EPT_PG_WRITE) != 0)
6673 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6675 if ((pte & EPT_PG_EXECUTE) == 0 ||
6676 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6683 * pmap_ts_referenced:
6685 * Return a count of reference bits for a page, clearing those bits.
6686 * It is not necessary for every reference bit to be cleared, but it
6687 * is necessary that 0 only be returned when there are truly no
6688 * reference bits set.
6690 * As an optimization, update the page's dirty field if a modified bit is
6691 * found while counting reference bits. This opportunistic update can be
6692 * performed at low cost and can eliminate the need for some future calls
6693 * to pmap_is_modified(). However, since this function stops after
6694 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6695 * dirty pages. Those dirty pages will only be detected by a future call
6696 * to pmap_is_modified().
6698 * A DI block is not needed within this function, because
6699 * invalidations are performed before the PV list lock is
6703 pmap_ts_referenced(vm_page_t m)
6705 struct md_page *pvh;
6708 struct rwlock *lock;
6709 pd_entry_t oldpde, *pde;
6710 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6713 int cleared, md_gen, not_cleared, pvh_gen;
6714 struct spglist free;
6717 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6718 ("pmap_ts_referenced: page %p is not managed", m));
6721 pa = VM_PAGE_TO_PHYS(m);
6722 lock = PHYS_TO_PV_LIST_LOCK(pa);
6723 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6727 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6728 goto small_mappings;
6734 if (!PMAP_TRYLOCK(pmap)) {
6735 pvh_gen = pvh->pv_gen;
6739 if (pvh_gen != pvh->pv_gen) {
6744 PG_A = pmap_accessed_bit(pmap);
6745 PG_M = pmap_modified_bit(pmap);
6746 PG_RW = pmap_rw_bit(pmap);
6748 pde = pmap_pde(pmap, pv->pv_va);
6750 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6752 * Although "oldpde" is mapping a 2MB page, because
6753 * this function is called at a 4KB page granularity,
6754 * we only update the 4KB page under test.
6758 if ((oldpde & PG_A) != 0) {
6760 * Since this reference bit is shared by 512 4KB
6761 * pages, it should not be cleared every time it is
6762 * tested. Apply a simple "hash" function on the
6763 * physical page number, the virtual superpage number,
6764 * and the pmap address to select one 4KB page out of
6765 * the 512 on which testing the reference bit will
6766 * result in clearing that reference bit. This
6767 * function is designed to avoid the selection of the
6768 * same 4KB page for every 2MB page mapping.
6770 * On demotion, a mapping that hasn't been referenced
6771 * is simply destroyed. To avoid the possibility of a
6772 * subsequent page fault on a demoted wired mapping,
6773 * always leave its reference bit set. Moreover,
6774 * since the superpage is wired, the current state of
6775 * its reference bit won't affect page replacement.
6777 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6778 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6779 (oldpde & PG_W) == 0) {
6780 if (safe_to_clear_referenced(pmap, oldpde)) {
6781 atomic_clear_long(pde, PG_A);
6782 pmap_invalidate_page(pmap, pv->pv_va);
6784 } else if (pmap_demote_pde_locked(pmap, pde,
6785 pv->pv_va, &lock)) {
6787 * Remove the mapping to a single page
6788 * so that a subsequent access may
6789 * repromote. Since the underlying
6790 * page table page is fully populated,
6791 * this removal never frees a page
6795 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6797 pte = pmap_pde_to_pte(pde, va);
6798 pmap_remove_pte(pmap, pte, va, *pde,
6800 pmap_invalidate_page(pmap, va);
6806 * The superpage mapping was removed
6807 * entirely and therefore 'pv' is no
6815 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6816 ("inconsistent pv lock %p %p for page %p",
6817 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6822 /* Rotate the PV list if it has more than one entry. */
6823 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6824 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6825 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6828 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6830 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6832 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6839 if (!PMAP_TRYLOCK(pmap)) {
6840 pvh_gen = pvh->pv_gen;
6841 md_gen = m->md.pv_gen;
6845 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6850 PG_A = pmap_accessed_bit(pmap);
6851 PG_M = pmap_modified_bit(pmap);
6852 PG_RW = pmap_rw_bit(pmap);
6853 pde = pmap_pde(pmap, pv->pv_va);
6854 KASSERT((*pde & PG_PS) == 0,
6855 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6857 pte = pmap_pde_to_pte(pde, pv->pv_va);
6858 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6860 if ((*pte & PG_A) != 0) {
6861 if (safe_to_clear_referenced(pmap, *pte)) {
6862 atomic_clear_long(pte, PG_A);
6863 pmap_invalidate_page(pmap, pv->pv_va);
6865 } else if ((*pte & PG_W) == 0) {
6867 * Wired pages cannot be paged out so
6868 * doing accessed bit emulation for
6869 * them is wasted effort. We do the
6870 * hard work for unwired pages only.
6872 pmap_remove_pte(pmap, pte, pv->pv_va,
6873 *pde, &free, &lock);
6874 pmap_invalidate_page(pmap, pv->pv_va);
6879 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6880 ("inconsistent pv lock %p %p for page %p",
6881 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6886 /* Rotate the PV list if it has more than one entry. */
6887 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6888 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6889 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6892 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6893 not_cleared < PMAP_TS_REFERENCED_MAX);
6896 vm_page_free_pages_toq(&free, true);
6897 return (cleared + not_cleared);
6901 * Apply the given advice to the specified range of addresses within the
6902 * given pmap. Depending on the advice, clear the referenced and/or
6903 * modified flags in each mapping and set the mapped page's dirty field.
6906 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6908 struct rwlock *lock;
6909 pml4_entry_t *pml4e;
6911 pd_entry_t oldpde, *pde;
6912 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6913 vm_offset_t va, va_next;
6915 boolean_t anychanged;
6917 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6921 * A/D bit emulation requires an alternate code path when clearing
6922 * the modified and accessed bits below. Since this function is
6923 * advisory in nature we skip it entirely for pmaps that require
6924 * A/D bit emulation.
6926 if (pmap_emulate_ad_bits(pmap))
6929 PG_A = pmap_accessed_bit(pmap);
6930 PG_G = pmap_global_bit(pmap);
6931 PG_M = pmap_modified_bit(pmap);
6932 PG_V = pmap_valid_bit(pmap);
6933 PG_RW = pmap_rw_bit(pmap);
6935 pmap_delayed_invl_started();
6937 for (; sva < eva; sva = va_next) {
6938 pml4e = pmap_pml4e(pmap, sva);
6939 if ((*pml4e & PG_V) == 0) {
6940 va_next = (sva + NBPML4) & ~PML4MASK;
6945 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6946 if ((*pdpe & PG_V) == 0) {
6947 va_next = (sva + NBPDP) & ~PDPMASK;
6952 va_next = (sva + NBPDR) & ~PDRMASK;
6955 pde = pmap_pdpe_to_pde(pdpe, sva);
6957 if ((oldpde & PG_V) == 0)
6959 else if ((oldpde & PG_PS) != 0) {
6960 if ((oldpde & PG_MANAGED) == 0)
6963 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6968 * The large page mapping was destroyed.
6974 * Unless the page mappings are wired, remove the
6975 * mapping to a single page so that a subsequent
6976 * access may repromote. Since the underlying page
6977 * table page is fully populated, this removal never
6978 * frees a page table page.
6980 if ((oldpde & PG_W) == 0) {
6981 pte = pmap_pde_to_pte(pde, sva);
6982 KASSERT((*pte & PG_V) != 0,
6983 ("pmap_advise: invalid PTE"));
6984 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6994 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6996 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6998 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6999 if (advice == MADV_DONTNEED) {
7001 * Future calls to pmap_is_modified()
7002 * can be avoided by making the page
7005 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7008 atomic_clear_long(pte, PG_M | PG_A);
7009 } else if ((*pte & PG_A) != 0)
7010 atomic_clear_long(pte, PG_A);
7014 if ((*pte & PG_G) != 0) {
7021 if (va != va_next) {
7022 pmap_invalidate_range(pmap, va, sva);
7027 pmap_invalidate_range(pmap, va, sva);
7030 pmap_invalidate_all(pmap);
7032 pmap_delayed_invl_finished();
7036 * Clear the modify bits on the specified physical page.
7039 pmap_clear_modify(vm_page_t m)
7041 struct md_page *pvh;
7043 pv_entry_t next_pv, pv;
7044 pd_entry_t oldpde, *pde;
7045 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
7046 struct rwlock *lock;
7048 int md_gen, pvh_gen;
7050 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7051 ("pmap_clear_modify: page %p is not managed", m));
7052 VM_OBJECT_ASSERT_WLOCKED(m->object);
7053 KASSERT(!vm_page_xbusied(m),
7054 ("pmap_clear_modify: page %p is exclusive busied", m));
7057 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7058 * If the object containing the page is locked and the page is not
7059 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7061 if ((m->aflags & PGA_WRITEABLE) == 0)
7063 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7064 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7065 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7068 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7070 if (!PMAP_TRYLOCK(pmap)) {
7071 pvh_gen = pvh->pv_gen;
7075 if (pvh_gen != pvh->pv_gen) {
7080 PG_M = pmap_modified_bit(pmap);
7081 PG_V = pmap_valid_bit(pmap);
7082 PG_RW = pmap_rw_bit(pmap);
7084 pde = pmap_pde(pmap, va);
7086 if ((oldpde & PG_RW) != 0) {
7087 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
7088 if ((oldpde & PG_W) == 0) {
7090 * Write protect the mapping to a
7091 * single page so that a subsequent
7092 * write access may repromote.
7094 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7096 pte = pmap_pde_to_pte(pde, va);
7098 if ((oldpte & PG_V) != 0) {
7099 while (!atomic_cmpset_long(pte,
7101 oldpte & ~(PG_M | PG_RW)))
7104 pmap_invalidate_page(pmap, va);
7111 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7113 if (!PMAP_TRYLOCK(pmap)) {
7114 md_gen = m->md.pv_gen;
7115 pvh_gen = pvh->pv_gen;
7119 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7124 PG_M = pmap_modified_bit(pmap);
7125 PG_RW = pmap_rw_bit(pmap);
7126 pde = pmap_pde(pmap, pv->pv_va);
7127 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7128 " a 2mpage in page %p's pv list", m));
7129 pte = pmap_pde_to_pte(pde, pv->pv_va);
7130 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7131 atomic_clear_long(pte, PG_M);
7132 pmap_invalidate_page(pmap, pv->pv_va);
7140 * Miscellaneous support routines follow
7143 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7144 static __inline void
7145 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7150 * The cache mode bits are all in the low 32-bits of the
7151 * PTE, so we can just spin on updating the low 32-bits.
7154 opte = *(u_int *)pte;
7155 npte = opte & ~mask;
7157 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7160 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7161 static __inline void
7162 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7167 * The cache mode bits are all in the low 32-bits of the
7168 * PDE, so we can just spin on updating the low 32-bits.
7171 opde = *(u_int *)pde;
7172 npde = opde & ~mask;
7174 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7178 * Map a set of physical memory pages into the kernel virtual
7179 * address space. Return a pointer to where it is mapped. This
7180 * routine is intended to be used for mapping device memory,
7184 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, bool noflush)
7186 struct pmap_preinit_mapping *ppim;
7187 vm_offset_t va, offset;
7191 offset = pa & PAGE_MASK;
7192 size = round_page(offset + size);
7193 pa = trunc_page(pa);
7195 if (!pmap_initialized) {
7197 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7198 ppim = pmap_preinit_mapping + i;
7199 if (ppim->va == 0) {
7203 ppim->va = virtual_avail;
7204 virtual_avail += size;
7210 panic("%s: too many preinit mappings", __func__);
7213 * If we have a preinit mapping, re-use it.
7215 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7216 ppim = pmap_preinit_mapping + i;
7217 if (ppim->pa == pa && ppim->sz == size &&
7219 return ((void *)(ppim->va + offset));
7222 * If the specified range of physical addresses fits within
7223 * the direct map window, use the direct map.
7225 if (pa < dmaplimit && pa + size <= dmaplimit) {
7226 va = PHYS_TO_DMAP(pa);
7227 PMAP_LOCK(kernel_pmap);
7228 i = pmap_change_attr_locked(va, size, mode, noflush);
7229 PMAP_UNLOCK(kernel_pmap);
7231 return ((void *)(va + offset));
7233 va = kva_alloc(size);
7235 panic("%s: Couldn't allocate KVA", __func__);
7237 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7238 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7239 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7241 pmap_invalidate_cache_range(va, va + tmpsize);
7242 return ((void *)(va + offset));
7246 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7249 return (pmap_mapdev_internal(pa, size, mode, false));
7253 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7256 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, false));
7260 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7263 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, true));
7267 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7270 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK, false));
7274 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7276 struct pmap_preinit_mapping *ppim;
7280 /* If we gave a direct map region in pmap_mapdev, do nothing */
7281 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7283 offset = va & PAGE_MASK;
7284 size = round_page(offset + size);
7285 va = trunc_page(va);
7286 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7287 ppim = pmap_preinit_mapping + i;
7288 if (ppim->va == va && ppim->sz == size) {
7289 if (pmap_initialized)
7295 if (va + size == virtual_avail)
7300 if (pmap_initialized)
7305 * Tries to demote a 1GB page mapping.
7308 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7310 pdp_entry_t newpdpe, oldpdpe;
7311 pd_entry_t *firstpde, newpde, *pde;
7312 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7316 PG_A = pmap_accessed_bit(pmap);
7317 PG_M = pmap_modified_bit(pmap);
7318 PG_V = pmap_valid_bit(pmap);
7319 PG_RW = pmap_rw_bit(pmap);
7321 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7323 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7324 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7325 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7326 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7327 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7328 " in pmap %p", va, pmap);
7331 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7332 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7333 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7334 KASSERT((oldpdpe & PG_A) != 0,
7335 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7336 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7337 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7341 * Initialize the page directory page.
7343 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7349 * Demote the mapping.
7354 * Invalidate a stale recursive mapping of the page directory page.
7356 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7358 pmap_pdpe_demotions++;
7359 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7360 " in pmap %p", va, pmap);
7365 * Sets the memory attribute for the specified page.
7368 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7371 m->md.pat_mode = ma;
7374 * If "m" is a normal page, update its direct mapping. This update
7375 * can be relied upon to perform any cache operations that are
7376 * required for data coherence.
7378 if ((m->flags & PG_FICTITIOUS) == 0 &&
7379 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7381 panic("memory attribute change on the direct map failed");
7385 * Changes the specified virtual address range's memory type to that given by
7386 * the parameter "mode". The specified virtual address range must be
7387 * completely contained within either the direct map or the kernel map. If
7388 * the virtual address range is contained within the kernel map, then the
7389 * memory type for each of the corresponding ranges of the direct map is also
7390 * changed. (The corresponding ranges of the direct map are those ranges that
7391 * map the same physical pages as the specified virtual address range.) These
7392 * changes to the direct map are necessary because Intel describes the
7393 * behavior of their processors as "undefined" if two or more mappings to the
7394 * same physical page have different memory types.
7396 * Returns zero if the change completed successfully, and either EINVAL or
7397 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7398 * of the virtual address range was not mapped, and ENOMEM is returned if
7399 * there was insufficient memory available to complete the change. In the
7400 * latter case, the memory type may have been changed on some part of the
7401 * virtual address range or the direct map.
7404 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7408 PMAP_LOCK(kernel_pmap);
7409 error = pmap_change_attr_locked(va, size, mode, false);
7410 PMAP_UNLOCK(kernel_pmap);
7415 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, bool noflush)
7417 vm_offset_t base, offset, tmpva;
7418 vm_paddr_t pa_start, pa_end, pa_end1;
7422 int cache_bits_pte, cache_bits_pde, error;
7425 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7426 base = trunc_page(va);
7427 offset = va & PAGE_MASK;
7428 size = round_page(offset + size);
7431 * Only supported on kernel virtual addresses, including the direct
7432 * map but excluding the recursive map.
7434 if (base < DMAP_MIN_ADDRESS)
7437 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7438 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7442 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7443 * into 4KB pages if required.
7445 for (tmpva = base; tmpva < base + size; ) {
7446 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7447 if (pdpe == NULL || *pdpe == 0)
7449 if (*pdpe & PG_PS) {
7451 * If the current 1GB page already has the required
7452 * memory type, then we need not demote this page. Just
7453 * increment tmpva to the next 1GB page frame.
7455 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7456 tmpva = trunc_1gpage(tmpva) + NBPDP;
7461 * If the current offset aligns with a 1GB page frame
7462 * and there is at least 1GB left within the range, then
7463 * we need not break down this page into 2MB pages.
7465 if ((tmpva & PDPMASK) == 0 &&
7466 tmpva + PDPMASK < base + size) {
7470 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7473 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7478 * If the current 2MB page already has the required
7479 * memory type, then we need not demote this page. Just
7480 * increment tmpva to the next 2MB page frame.
7482 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7483 tmpva = trunc_2mpage(tmpva) + NBPDR;
7488 * If the current offset aligns with a 2MB page frame
7489 * and there is at least 2MB left within the range, then
7490 * we need not break down this page into 4KB pages.
7492 if ((tmpva & PDRMASK) == 0 &&
7493 tmpva + PDRMASK < base + size) {
7497 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7500 pte = pmap_pde_to_pte(pde, tmpva);
7508 * Ok, all the pages exist, so run through them updating their
7509 * cache mode if required.
7511 pa_start = pa_end = 0;
7512 for (tmpva = base; tmpva < base + size; ) {
7513 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7514 if (*pdpe & PG_PS) {
7515 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7516 pmap_pde_attr(pdpe, cache_bits_pde,
7520 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7521 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7522 if (pa_start == pa_end) {
7523 /* Start physical address run. */
7524 pa_start = *pdpe & PG_PS_FRAME;
7525 pa_end = pa_start + NBPDP;
7526 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7529 /* Run ended, update direct map. */
7530 error = pmap_change_attr_locked(
7531 PHYS_TO_DMAP(pa_start),
7532 pa_end - pa_start, mode, noflush);
7535 /* Start physical address run. */
7536 pa_start = *pdpe & PG_PS_FRAME;
7537 pa_end = pa_start + NBPDP;
7540 tmpva = trunc_1gpage(tmpva) + NBPDP;
7543 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7545 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7546 pmap_pde_attr(pde, cache_bits_pde,
7550 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7551 (*pde & PG_PS_FRAME) < dmaplimit) {
7552 if (pa_start == pa_end) {
7553 /* Start physical address run. */
7554 pa_start = *pde & PG_PS_FRAME;
7555 pa_end = pa_start + NBPDR;
7556 } else if (pa_end == (*pde & PG_PS_FRAME))
7559 /* Run ended, update direct map. */
7560 error = pmap_change_attr_locked(
7561 PHYS_TO_DMAP(pa_start),
7562 pa_end - pa_start, mode, noflush);
7565 /* Start physical address run. */
7566 pa_start = *pde & PG_PS_FRAME;
7567 pa_end = pa_start + NBPDR;
7570 tmpva = trunc_2mpage(tmpva) + NBPDR;
7572 pte = pmap_pde_to_pte(pde, tmpva);
7573 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7574 pmap_pte_attr(pte, cache_bits_pte,
7578 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7579 (*pte & PG_FRAME) < dmaplimit) {
7580 if (pa_start == pa_end) {
7581 /* Start physical address run. */
7582 pa_start = *pte & PG_FRAME;
7583 pa_end = pa_start + PAGE_SIZE;
7584 } else if (pa_end == (*pte & PG_FRAME))
7585 pa_end += PAGE_SIZE;
7587 /* Run ended, update direct map. */
7588 error = pmap_change_attr_locked(
7589 PHYS_TO_DMAP(pa_start),
7590 pa_end - pa_start, mode, noflush);
7593 /* Start physical address run. */
7594 pa_start = *pte & PG_FRAME;
7595 pa_end = pa_start + PAGE_SIZE;
7601 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7602 pa_end1 = MIN(pa_end, dmaplimit);
7603 if (pa_start != pa_end1)
7604 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7605 pa_end1 - pa_start, mode, noflush);
7609 * Flush CPU caches if required to make sure any data isn't cached that
7610 * shouldn't be, etc.
7613 pmap_invalidate_range(kernel_pmap, base, tmpva);
7615 pmap_invalidate_cache_range(base, tmpva);
7621 * Demotes any mapping within the direct map region that covers more than the
7622 * specified range of physical addresses. This range's size must be a power
7623 * of two and its starting address must be a multiple of its size. Since the
7624 * demotion does not change any attributes of the mapping, a TLB invalidation
7625 * is not mandatory. The caller may, however, request a TLB invalidation.
7628 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7637 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7638 KASSERT((base & (len - 1)) == 0,
7639 ("pmap_demote_DMAP: base is not a multiple of len"));
7640 if (len < NBPDP && base < dmaplimit) {
7641 va = PHYS_TO_DMAP(base);
7643 PMAP_LOCK(kernel_pmap);
7644 pdpe = pmap_pdpe(kernel_pmap, va);
7645 if ((*pdpe & X86_PG_V) == 0)
7646 panic("pmap_demote_DMAP: invalid PDPE");
7647 if ((*pdpe & PG_PS) != 0) {
7648 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7649 panic("pmap_demote_DMAP: PDPE failed");
7653 pde = pmap_pdpe_to_pde(pdpe, va);
7654 if ((*pde & X86_PG_V) == 0)
7655 panic("pmap_demote_DMAP: invalid PDE");
7656 if ((*pde & PG_PS) != 0) {
7657 if (!pmap_demote_pde(kernel_pmap, pde, va))
7658 panic("pmap_demote_DMAP: PDE failed");
7662 if (changed && invalidate)
7663 pmap_invalidate_page(kernel_pmap, va);
7664 PMAP_UNLOCK(kernel_pmap);
7669 * perform the pmap work for mincore
7672 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7675 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7679 PG_A = pmap_accessed_bit(pmap);
7680 PG_M = pmap_modified_bit(pmap);
7681 PG_V = pmap_valid_bit(pmap);
7682 PG_RW = pmap_rw_bit(pmap);
7686 pdep = pmap_pde(pmap, addr);
7687 if (pdep != NULL && (*pdep & PG_V)) {
7688 if (*pdep & PG_PS) {
7690 /* Compute the physical address of the 4KB page. */
7691 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7693 val = MINCORE_SUPER;
7695 pte = *pmap_pde_to_pte(pdep, addr);
7696 pa = pte & PG_FRAME;
7704 if ((pte & PG_V) != 0) {
7705 val |= MINCORE_INCORE;
7706 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7707 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7708 if ((pte & PG_A) != 0)
7709 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7711 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7712 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7713 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7714 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7715 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7718 PA_UNLOCK_COND(*locked_pa);
7724 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7726 uint32_t gen, new_gen, pcid_next;
7728 CRITICAL_ASSERT(curthread);
7729 gen = PCPU_GET(pcid_gen);
7730 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7731 return (pti ? 0 : CR3_PCID_SAVE);
7732 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7733 return (CR3_PCID_SAVE);
7734 pcid_next = PCPU_GET(pcid_next);
7735 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7736 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7737 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7738 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7739 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7743 PCPU_SET(pcid_gen, new_gen);
7744 pcid_next = PMAP_PCID_KERN + 1;
7748 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7749 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7750 PCPU_SET(pcid_next, pcid_next + 1);
7755 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
7759 cached = pmap_pcid_alloc(pmap, cpuid);
7760 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7761 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7762 pmap->pm_pcids[cpuid].pm_pcid));
7763 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7764 pmap == kernel_pmap,
7765 ("non-kernel pmap pmap %p cpu %d pcid %#x",
7766 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7771 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
7774 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
7775 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
7779 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
7781 struct invpcid_descr d;
7782 uint64_t cached, cr3, kcr3, ucr3;
7784 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7786 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7787 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
7788 PCPU_SET(curpmap, pmap);
7789 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7790 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7793 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7795 * Explicitly invalidate translations cached from the
7796 * user page table. They are not automatically
7797 * flushed by reload of cr3 with the kernel page table
7800 * Note that the if() condition is resolved statically
7801 * by using the function argument instead of
7802 * runtime-evaluated invpcid_works value.
7804 if (invpcid_works1) {
7805 d.pcid = PMAP_PCID_USER_PT |
7806 pmap->pm_pcids[cpuid].pm_pcid;
7809 invpcid(&d, INVPCID_CTX);
7811 pmap_pti_pcid_invalidate(ucr3, kcr3);
7815 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7816 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7818 PCPU_INC(pm_save_cnt);
7822 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
7825 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
7826 pmap_activate_sw_pti_post(td, pmap);
7830 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
7836 * If the INVPCID instruction is not available,
7837 * invltlb_pcid_handler() is used to handle an invalidate_all
7838 * IPI, which checks for curpmap == smp_tlb_pmap. The below
7839 * sequence of operations has a window where %CR3 is loaded
7840 * with the new pmap's PML4 address, but the curpmap value has
7841 * not yet been updated. This causes the invltlb IPI handler,
7842 * which is called between the updates, to execute as a NOP,
7843 * which leaves stale TLB entries.
7845 * Note that the most typical use of pmap_activate_sw(), from
7846 * the context switch, is immune to this race, because
7847 * interrupts are disabled (while the thread lock is owned),
7848 * and the IPI happens after curpmap is updated. Protect
7849 * other callers in a similar way, by disabling interrupts
7850 * around the %cr3 register reload and curpmap assignment.
7852 rflags = intr_disable();
7853 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
7854 intr_restore(rflags);
7855 pmap_activate_sw_pti_post(td, pmap);
7859 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
7862 uint64_t cached, cr3;
7864 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7866 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7867 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7869 PCPU_SET(curpmap, pmap);
7871 PCPU_INC(pm_save_cnt);
7875 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
7880 rflags = intr_disable();
7881 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
7882 intr_restore(rflags);
7886 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
7887 u_int cpuid __unused)
7890 load_cr3(pmap->pm_cr3);
7891 PCPU_SET(curpmap, pmap);
7895 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
7896 u_int cpuid __unused)
7899 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
7900 PCPU_SET(kcr3, pmap->pm_cr3);
7901 PCPU_SET(ucr3, pmap->pm_ucr3);
7902 pmap_activate_sw_pti_post(td, pmap);
7905 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
7909 if (pmap_pcid_enabled && pti && invpcid_works)
7910 return (pmap_activate_sw_pcid_invpcid_pti);
7911 else if (pmap_pcid_enabled && pti && !invpcid_works)
7912 return (pmap_activate_sw_pcid_noinvpcid_pti);
7913 else if (pmap_pcid_enabled && !pti && invpcid_works)
7914 return (pmap_activate_sw_pcid_nopti);
7915 else if (pmap_pcid_enabled && !pti && !invpcid_works)
7916 return (pmap_activate_sw_pcid_noinvpcid_nopti);
7917 else if (!pmap_pcid_enabled && pti)
7918 return (pmap_activate_sw_nopcid_pti);
7919 else /* if (!pmap_pcid_enabled && !pti) */
7920 return (pmap_activate_sw_nopcid_nopti);
7924 pmap_activate_sw(struct thread *td)
7926 pmap_t oldpmap, pmap;
7929 oldpmap = PCPU_GET(curpmap);
7930 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7931 if (oldpmap == pmap)
7933 cpuid = PCPU_GET(cpuid);
7935 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7937 CPU_SET(cpuid, &pmap->pm_active);
7939 pmap_activate_sw_mode(td, pmap, cpuid);
7941 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7943 CPU_CLR(cpuid, &oldpmap->pm_active);
7948 pmap_activate(struct thread *td)
7952 pmap_activate_sw(td);
7957 pmap_activate_boot(pmap_t pmap)
7963 * kernel_pmap must be never deactivated, and we ensure that
7964 * by never activating it at all.
7966 MPASS(pmap != kernel_pmap);
7968 cpuid = PCPU_GET(cpuid);
7970 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7972 CPU_SET(cpuid, &pmap->pm_active);
7974 PCPU_SET(curpmap, pmap);
7976 kcr3 = pmap->pm_cr3;
7977 if (pmap_pcid_enabled)
7978 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
7982 PCPU_SET(kcr3, kcr3);
7983 PCPU_SET(ucr3, PMAP_NO_CR3);
7987 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7992 * Increase the starting virtual address of the given mapping if a
7993 * different alignment might result in more superpage mappings.
7996 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7997 vm_offset_t *addr, vm_size_t size)
7999 vm_offset_t superpage_offset;
8003 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8004 offset += ptoa(object->pg_color);
8005 superpage_offset = offset & PDRMASK;
8006 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8007 (*addr & PDRMASK) == superpage_offset)
8009 if ((*addr & PDRMASK) < superpage_offset)
8010 *addr = (*addr & ~PDRMASK) + superpage_offset;
8012 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8016 static unsigned long num_dirty_emulations;
8017 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8018 &num_dirty_emulations, 0, NULL);
8020 static unsigned long num_accessed_emulations;
8021 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8022 &num_accessed_emulations, 0, NULL);
8024 static unsigned long num_superpage_accessed_emulations;
8025 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8026 &num_superpage_accessed_emulations, 0, NULL);
8028 static unsigned long ad_emulation_superpage_promotions;
8029 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8030 &ad_emulation_superpage_promotions, 0, NULL);
8031 #endif /* INVARIANTS */
8034 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8037 struct rwlock *lock;
8038 #if VM_NRESERVLEVEL > 0
8042 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8044 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8045 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8047 if (!pmap_emulate_ad_bits(pmap))
8050 PG_A = pmap_accessed_bit(pmap);
8051 PG_M = pmap_modified_bit(pmap);
8052 PG_V = pmap_valid_bit(pmap);
8053 PG_RW = pmap_rw_bit(pmap);
8059 pde = pmap_pde(pmap, va);
8060 if (pde == NULL || (*pde & PG_V) == 0)
8063 if ((*pde & PG_PS) != 0) {
8064 if (ftype == VM_PROT_READ) {
8066 atomic_add_long(&num_superpage_accessed_emulations, 1);
8074 pte = pmap_pde_to_pte(pde, va);
8075 if ((*pte & PG_V) == 0)
8078 if (ftype == VM_PROT_WRITE) {
8079 if ((*pte & PG_RW) == 0)
8082 * Set the modified and accessed bits simultaneously.
8084 * Intel EPT PTEs that do software emulation of A/D bits map
8085 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8086 * An EPT misconfiguration is triggered if the PTE is writable
8087 * but not readable (WR=10). This is avoided by setting PG_A
8088 * and PG_M simultaneously.
8090 *pte |= PG_M | PG_A;
8095 #if VM_NRESERVLEVEL > 0
8096 /* try to promote the mapping */
8097 if (va < VM_MAXUSER_ADDRESS)
8098 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8102 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8104 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8105 pmap_ps_enabled(pmap) &&
8106 (m->flags & PG_FICTITIOUS) == 0 &&
8107 vm_reserv_level_iffullpop(m) == 0) {
8108 pmap_promote_pde(pmap, pde, va, &lock);
8110 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8116 if (ftype == VM_PROT_WRITE)
8117 atomic_add_long(&num_dirty_emulations, 1);
8119 atomic_add_long(&num_accessed_emulations, 1);
8121 rv = 0; /* success */
8130 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8135 pt_entry_t *pte, PG_V;
8139 PG_V = pmap_valid_bit(pmap);
8142 pml4 = pmap_pml4e(pmap, va);
8144 if ((*pml4 & PG_V) == 0)
8147 pdp = pmap_pml4e_to_pdpe(pml4, va);
8149 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8152 pde = pmap_pdpe_to_pde(pdp, va);
8154 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8157 pte = pmap_pde_to_pte(pde, va);
8166 * Get the kernel virtual address of a set of physical pages. If there are
8167 * physical addresses not covered by the DMAP perform a transient mapping
8168 * that will be removed when calling pmap_unmap_io_transient.
8170 * \param page The pages the caller wishes to obtain the virtual
8171 * address on the kernel memory map.
8172 * \param vaddr On return contains the kernel virtual memory address
8173 * of the pages passed in the page parameter.
8174 * \param count Number of pages passed in.
8175 * \param can_fault TRUE if the thread using the mapped pages can take
8176 * page faults, FALSE otherwise.
8178 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8179 * finished or FALSE otherwise.
8183 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8184 boolean_t can_fault)
8187 boolean_t needs_mapping;
8189 int cache_bits, error __unused, i;
8192 * Allocate any KVA space that we need, this is done in a separate
8193 * loop to prevent calling vmem_alloc while pinned.
8195 needs_mapping = FALSE;
8196 for (i = 0; i < count; i++) {
8197 paddr = VM_PAGE_TO_PHYS(page[i]);
8198 if (__predict_false(paddr >= dmaplimit)) {
8199 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8200 M_BESTFIT | M_WAITOK, &vaddr[i]);
8201 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8202 needs_mapping = TRUE;
8204 vaddr[i] = PHYS_TO_DMAP(paddr);
8208 /* Exit early if everything is covered by the DMAP */
8213 * NB: The sequence of updating a page table followed by accesses
8214 * to the corresponding pages used in the !DMAP case is subject to
8215 * the situation described in the "AMD64 Architecture Programmer's
8216 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8217 * Coherency Considerations". Therefore, issuing the INVLPG right
8218 * after modifying the PTE bits is crucial.
8222 for (i = 0; i < count; i++) {
8223 paddr = VM_PAGE_TO_PHYS(page[i]);
8224 if (paddr >= dmaplimit) {
8227 * Slow path, since we can get page faults
8228 * while mappings are active don't pin the
8229 * thread to the CPU and instead add a global
8230 * mapping visible to all CPUs.
8232 pmap_qenter(vaddr[i], &page[i], 1);
8234 pte = vtopte(vaddr[i]);
8235 cache_bits = pmap_cache_bits(kernel_pmap,
8236 page[i]->md.pat_mode, 0);
8237 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8244 return (needs_mapping);
8248 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8249 boolean_t can_fault)
8256 for (i = 0; i < count; i++) {
8257 paddr = VM_PAGE_TO_PHYS(page[i]);
8258 if (paddr >= dmaplimit) {
8260 pmap_qremove(vaddr[i], 1);
8261 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8267 pmap_quick_enter_page(vm_page_t m)
8271 paddr = VM_PAGE_TO_PHYS(m);
8272 if (paddr < dmaplimit)
8273 return (PHYS_TO_DMAP(paddr));
8274 mtx_lock_spin(&qframe_mtx);
8275 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8276 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8277 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8282 pmap_quick_remove_page(vm_offset_t addr)
8287 pte_store(vtopte(qframe), 0);
8289 mtx_unlock_spin(&qframe_mtx);
8293 * Pdp pages from the large map are managed differently from either
8294 * kernel or user page table pages. They are permanently allocated at
8295 * initialization time, and their wire count is permanently set to
8296 * zero. The pml4 entries pointing to those pages are copied into
8297 * each allocated pmap.
8299 * In contrast, pd and pt pages are managed like user page table
8300 * pages. They are dynamically allocated, and their wire count
8301 * represents the number of valid entries within the page.
8304 pmap_large_map_getptp_unlocked(void)
8308 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8310 if (m != NULL && (m->flags & PG_ZERO) == 0)
8316 pmap_large_map_getptp(void)
8320 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8321 m = pmap_large_map_getptp_unlocked();
8323 PMAP_UNLOCK(kernel_pmap);
8325 PMAP_LOCK(kernel_pmap);
8326 /* Callers retry. */
8331 static pdp_entry_t *
8332 pmap_large_map_pdpe(vm_offset_t va)
8334 vm_pindex_t pml4_idx;
8337 pml4_idx = pmap_pml4e_index(va);
8338 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8339 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8341 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8342 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8343 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8344 "LMSPML4I %#jx lm_ents %d",
8345 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8346 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8347 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8351 pmap_large_map_pde(vm_offset_t va)
8358 pdpe = pmap_large_map_pdpe(va);
8360 m = pmap_large_map_getptp();
8363 mphys = VM_PAGE_TO_PHYS(m);
8364 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8366 MPASS((*pdpe & X86_PG_PS) == 0);
8367 mphys = *pdpe & PG_FRAME;
8369 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
8373 pmap_large_map_pte(vm_offset_t va)
8380 pde = pmap_large_map_pde(va);
8382 m = pmap_large_map_getptp();
8385 mphys = VM_PAGE_TO_PHYS(m);
8386 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8387 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
8389 MPASS((*pde & X86_PG_PS) == 0);
8390 mphys = *pde & PG_FRAME;
8392 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
8396 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
8397 vmem_addr_t *vmem_res)
8401 * Large mappings are all but static. Consequently, there
8402 * is no point in waiting for an earlier allocation to be
8405 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
8406 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
8410 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
8416 vm_offset_t va, inc;
8417 vmem_addr_t vmem_res;
8421 if (len == 0 || spa + len < spa)
8424 /* See if DMAP can serve. */
8425 if (spa + len <= dmaplimit) {
8426 va = PHYS_TO_DMAP(spa);
8428 return (pmap_change_attr(va, len, mattr));
8432 * No, allocate KVA. Fit the address with best possible
8433 * alignment for superpages. Fall back to worse align if
8437 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
8438 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
8439 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
8441 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
8443 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
8446 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
8451 * Fill pagetable. PG_M is not pre-set, we scan modified bits
8452 * in the pagetable to minimize flushing. No need to
8453 * invalidate TLB, since we only update invalid entries.
8455 PMAP_LOCK(kernel_pmap);
8456 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
8458 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
8459 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
8460 pdpe = pmap_large_map_pdpe(va);
8462 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
8463 X86_PG_V | X86_PG_A | pg_nx |
8464 pmap_cache_bits(kernel_pmap, mattr, TRUE);
8466 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
8467 (va & PDRMASK) == 0) {
8468 pde = pmap_large_map_pde(va);
8470 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
8471 X86_PG_V | X86_PG_A | pg_nx |
8472 pmap_cache_bits(kernel_pmap, mattr, TRUE);
8473 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
8477 pte = pmap_large_map_pte(va);
8479 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
8480 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
8482 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
8487 PMAP_UNLOCK(kernel_pmap);
8490 *addr = (void *)vmem_res;
8495 pmap_large_unmap(void *svaa, vm_size_t len)
8497 vm_offset_t sva, va;
8499 pdp_entry_t *pdpe, pdp;
8500 pd_entry_t *pde, pd;
8503 struct spglist spgf;
8505 sva = (vm_offset_t)svaa;
8506 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
8507 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
8511 KASSERT(LARGEMAP_MIN_ADDRESS <= sva && sva + len <=
8512 LARGEMAP_MAX_ADDRESS + NBPML4 * (u_long)lm_ents,
8513 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
8514 PMAP_LOCK(kernel_pmap);
8515 for (va = sva; va < sva + len; va += inc) {
8516 pdpe = pmap_large_map_pdpe(va);
8518 KASSERT((pdp & X86_PG_V) != 0,
8519 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
8520 (u_long)pdpe, pdp));
8521 if ((pdp & X86_PG_PS) != 0) {
8522 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
8523 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
8524 (u_long)pdpe, pdp));
8525 KASSERT((va & PDPMASK) == 0,
8526 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
8527 (u_long)pdpe, pdp));
8528 KASSERT(va + NBPDP <= sva + len,
8529 ("unmap covers partial 1GB page, sva %#lx va %#lx "
8530 "pdpe %#lx pdp %#lx len %#lx", sva, va,
8531 (u_long)pdpe, pdp, len));
8536 pde = pmap_pdpe_to_pde(pdpe, va);
8538 KASSERT((pd & X86_PG_V) != 0,
8539 ("invalid pd va %#lx pde %#lx pd %#lx", va,
8541 if ((pd & X86_PG_PS) != 0) {
8542 KASSERT((va & PDRMASK) == 0,
8543 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
8545 KASSERT(va + NBPDR <= sva + len,
8546 ("unmap covers partial 2MB page, sva %#lx va %#lx "
8547 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
8551 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
8553 if (m->wire_count == 0) {
8555 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8559 pte = pmap_pde_to_pte(pde, va);
8560 KASSERT((*pte & X86_PG_V) != 0,
8561 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8562 (u_long)pte, *pte));
8565 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
8567 if (m->wire_count == 0) {
8569 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8570 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
8572 if (m->wire_count == 0) {
8574 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8578 pmap_invalidate_range(kernel_pmap, sva, sva + len);
8579 PMAP_UNLOCK(kernel_pmap);
8580 vm_page_free_pages_toq(&spgf, false);
8581 vmem_free(large_vmem, sva, len);
8585 pmap_large_map_wb_fence_mfence(void)
8592 pmap_large_map_wb_fence_sfence(void)
8599 pmap_large_map_wb_fence_nop(void)
8603 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void), static)
8606 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8607 return (pmap_large_map_wb_fence_mfence);
8608 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
8609 CPUID_STDEXT_CLFLUSHOPT)) == 0)
8610 return (pmap_large_map_wb_fence_sfence);
8612 /* clflush is strongly enough ordered */
8613 return (pmap_large_map_wb_fence_nop);
8617 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
8620 for (; len > 0; len -= cpu_clflush_line_size,
8621 va += cpu_clflush_line_size)
8626 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
8629 for (; len > 0; len -= cpu_clflush_line_size,
8630 va += cpu_clflush_line_size)
8635 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
8638 for (; len > 0; len -= cpu_clflush_line_size,
8639 va += cpu_clflush_line_size)
8644 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
8648 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t),
8652 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
8653 return (pmap_large_map_flush_range_clwb);
8654 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
8655 return (pmap_large_map_flush_range_clflushopt);
8656 else if ((cpu_feature & CPUID_CLFSH) != 0)
8657 return (pmap_large_map_flush_range_clflush);
8659 return (pmap_large_map_flush_range_nop);
8663 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
8665 volatile u_long *pe;
8671 for (va = sva; va < eva; va += inc) {
8673 if ((amd_feature & AMDID_PAGE1GB) != 0) {
8674 pe = (volatile u_long *)pmap_large_map_pdpe(va);
8676 if ((p & X86_PG_PS) != 0)
8680 pe = (volatile u_long *)pmap_large_map_pde(va);
8682 if ((p & X86_PG_PS) != 0)
8686 pe = (volatile u_long *)pmap_large_map_pte(va);
8692 if ((p & X86_PG_AVAIL1) != 0) {
8694 * Spin-wait for the end of a parallel
8701 * If we saw other write-back
8702 * occuring, we cannot rely on PG_M to
8703 * indicate state of the cache. The
8704 * PG_M bit is cleared before the
8705 * flush to avoid ignoring new writes,
8706 * and writes which are relevant for
8707 * us might happen after.
8713 if ((p & X86_PG_M) != 0 || seen_other) {
8714 if (!atomic_fcmpset_long(pe, &p,
8715 (p & ~X86_PG_M) | X86_PG_AVAIL1))
8717 * If we saw PG_M without
8718 * PG_AVAIL1, and then on the
8719 * next attempt we do not
8720 * observe either PG_M or
8721 * PG_AVAIL1, the other
8722 * write-back started after us
8723 * and finished before us. We
8724 * can rely on it doing our
8728 pmap_large_map_flush_range(va, inc);
8729 atomic_clear_long(pe, X86_PG_AVAIL1);
8738 * Write-back cache lines for the given address range.
8740 * Must be called only on the range or sub-range returned from
8741 * pmap_large_map(). Must not be called on the coalesced ranges.
8743 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
8744 * instructions support.
8747 pmap_large_map_wb(void *svap, vm_size_t len)
8749 vm_offset_t eva, sva;
8751 sva = (vm_offset_t)svap;
8753 pmap_large_map_wb_fence();
8754 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
8755 pmap_large_map_flush_range(sva, len);
8757 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
8758 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
8759 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
8760 pmap_large_map_wb_large(sva, eva);
8762 pmap_large_map_wb_fence();
8766 pmap_pti_alloc_page(void)
8770 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8771 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
8772 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
8777 pmap_pti_free_page(vm_page_t m)
8780 KASSERT(m->wire_count > 0, ("page %p not wired", m));
8781 if (!vm_page_unwire_noq(m))
8783 vm_page_free_zero(m);
8797 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
8798 VM_OBJECT_WLOCK(pti_obj);
8799 pml4_pg = pmap_pti_alloc_page();
8800 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
8801 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
8802 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
8803 pdpe = pmap_pti_pdpe(va);
8804 pmap_pti_wire_pte(pdpe);
8806 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
8807 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
8808 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
8809 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
8810 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
8811 sizeof(struct gate_descriptor) * NIDT, false);
8812 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
8813 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
8815 /* Doublefault stack IST 1 */
8816 va = common_tss[i].tss_ist1;
8817 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8818 /* NMI stack IST 2 */
8819 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
8820 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8821 /* MC# stack IST 3 */
8822 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
8823 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8824 /* DB# stack IST 4 */
8825 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
8826 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8828 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
8829 (vm_offset_t)etext, true);
8830 pti_finalized = true;
8831 VM_OBJECT_WUNLOCK(pti_obj);
8833 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
8835 static pdp_entry_t *
8836 pmap_pti_pdpe(vm_offset_t va)
8838 pml4_entry_t *pml4e;
8841 vm_pindex_t pml4_idx;
8844 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8846 pml4_idx = pmap_pml4e_index(va);
8847 pml4e = &pti_pml4[pml4_idx];
8851 panic("pml4 alloc after finalization\n");
8852 m = pmap_pti_alloc_page();
8854 pmap_pti_free_page(m);
8855 mphys = *pml4e & ~PAGE_MASK;
8857 mphys = VM_PAGE_TO_PHYS(m);
8858 *pml4e = mphys | X86_PG_RW | X86_PG_V;
8861 mphys = *pml4e & ~PAGE_MASK;
8863 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
8868 pmap_pti_wire_pte(void *pte)
8872 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8873 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8878 pmap_pti_unwire_pde(void *pde, bool only_ref)
8882 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8883 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
8884 MPASS(m->wire_count > 0);
8885 MPASS(only_ref || m->wire_count > 1);
8886 pmap_pti_free_page(m);
8890 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
8895 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8896 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8897 MPASS(m->wire_count > 0);
8898 if (pmap_pti_free_page(m)) {
8899 pde = pmap_pti_pde(va);
8900 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
8902 pmap_pti_unwire_pde(pde, false);
8907 pmap_pti_pde(vm_offset_t va)
8915 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8917 pdpe = pmap_pti_pdpe(va);
8919 m = pmap_pti_alloc_page();
8921 pmap_pti_free_page(m);
8922 MPASS((*pdpe & X86_PG_PS) == 0);
8923 mphys = *pdpe & ~PAGE_MASK;
8925 mphys = VM_PAGE_TO_PHYS(m);
8926 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8929 MPASS((*pdpe & X86_PG_PS) == 0);
8930 mphys = *pdpe & ~PAGE_MASK;
8933 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8934 pd_idx = pmap_pde_index(va);
8940 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8947 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8949 pde = pmap_pti_pde(va);
8950 if (unwire_pde != NULL) {
8952 pmap_pti_wire_pte(pde);
8955 m = pmap_pti_alloc_page();
8957 pmap_pti_free_page(m);
8958 MPASS((*pde & X86_PG_PS) == 0);
8959 mphys = *pde & ~(PAGE_MASK | pg_nx);
8961 mphys = VM_PAGE_TO_PHYS(m);
8962 *pde = mphys | X86_PG_RW | X86_PG_V;
8963 if (unwire_pde != NULL)
8964 *unwire_pde = false;
8967 MPASS((*pde & X86_PG_PS) == 0);
8968 mphys = *pde & ~(PAGE_MASK | pg_nx);
8971 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8972 pte += pmap_pte_index(va);
8978 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8982 pt_entry_t *pte, ptev;
8985 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8987 sva = trunc_page(sva);
8988 MPASS(sva > VM_MAXUSER_ADDRESS);
8989 eva = round_page(eva);
8991 for (; sva < eva; sva += PAGE_SIZE) {
8992 pte = pmap_pti_pte(sva, &unwire_pde);
8993 pa = pmap_kextract(sva);
8994 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8995 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8996 VM_MEMATTR_DEFAULT, FALSE);
8998 pte_store(pte, ptev);
8999 pmap_pti_wire_pte(pte);
9001 KASSERT(!pti_finalized,
9002 ("pti overlap after fin %#lx %#lx %#lx",
9004 KASSERT(*pte == ptev,
9005 ("pti non-identical pte after fin %#lx %#lx %#lx",
9009 pde = pmap_pti_pde(sva);
9010 pmap_pti_unwire_pde(pde, true);
9016 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9021 VM_OBJECT_WLOCK(pti_obj);
9022 pmap_pti_add_kva_locked(sva, eva, exec);
9023 VM_OBJECT_WUNLOCK(pti_obj);
9027 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9034 sva = rounddown2(sva, PAGE_SIZE);
9035 MPASS(sva > VM_MAXUSER_ADDRESS);
9036 eva = roundup2(eva, PAGE_SIZE);
9038 VM_OBJECT_WLOCK(pti_obj);
9039 for (va = sva; va < eva; va += PAGE_SIZE) {
9040 pte = pmap_pti_pte(va, NULL);
9041 KASSERT((*pte & X86_PG_V) != 0,
9042 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9043 (u_long)pte, *pte));
9045 pmap_pti_unwire_pte(pte, va);
9047 pmap_invalidate_range(kernel_pmap, sva, eva);
9048 VM_OBJECT_WUNLOCK(pti_obj);
9052 pkru_dup_range(void *ctx __unused, void *data)
9054 struct pmap_pkru_range *node, *new_node;
9056 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9057 if (new_node == NULL)
9060 memcpy(new_node, node, sizeof(*node));
9065 pkru_free_range(void *ctx __unused, void *node)
9068 uma_zfree(pmap_pkru_ranges_zone, node);
9072 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9075 struct pmap_pkru_range *ppr;
9078 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9079 MPASS(pmap->pm_type == PT_X86);
9080 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9081 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9082 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9084 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9087 ppr->pkru_keyidx = keyidx;
9088 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9089 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9091 uma_zfree(pmap_pkru_ranges_zone, ppr);
9096 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9099 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9100 MPASS(pmap->pm_type == PT_X86);
9101 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9102 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9106 pmap_pkru_deassign_all(pmap_t pmap)
9109 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9110 if (pmap->pm_type == PT_X86 &&
9111 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9112 rangeset_remove_all(&pmap->pm_pkru);
9116 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9118 struct pmap_pkru_range *ppr, *prev_ppr;
9121 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9122 if (pmap->pm_type != PT_X86 ||
9123 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9124 sva >= VM_MAXUSER_ADDRESS)
9126 MPASS(eva <= VM_MAXUSER_ADDRESS);
9127 for (va = sva, prev_ppr = NULL; va < eva;) {
9128 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9129 if ((ppr == NULL) ^ (prev_ppr == NULL))
9135 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9137 va = ppr->pkru_rs_el.re_end;
9143 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9145 struct pmap_pkru_range *ppr;
9147 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9148 if (pmap->pm_type != PT_X86 ||
9149 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9150 va >= VM_MAXUSER_ADDRESS)
9152 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9154 return (X86_PG_PKU(ppr->pkru_keyidx));
9159 pred_pkru_on_remove(void *ctx __unused, void *r)
9161 struct pmap_pkru_range *ppr;
9164 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9168 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9171 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9172 if (pmap->pm_type == PT_X86 &&
9173 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9174 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9175 pred_pkru_on_remove);
9180 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9183 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9184 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9185 MPASS(dst_pmap->pm_type == PT_X86);
9186 MPASS(src_pmap->pm_type == PT_X86);
9187 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9188 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9190 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9194 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9197 pml4_entry_t *pml4e;
9199 pd_entry_t newpde, ptpaddr, *pde;
9200 pt_entry_t newpte, *ptep, pte;
9201 vm_offset_t va, va_next;
9204 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9205 MPASS(pmap->pm_type == PT_X86);
9206 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9208 for (changed = false, va = sva; va < eva; va = va_next) {
9209 pml4e = pmap_pml4e(pmap, va);
9210 if ((*pml4e & X86_PG_V) == 0) {
9211 va_next = (va + NBPML4) & ~PML4MASK;
9217 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9218 if ((*pdpe & X86_PG_V) == 0) {
9219 va_next = (va + NBPDP) & ~PDPMASK;
9225 va_next = (va + NBPDR) & ~PDRMASK;
9229 pde = pmap_pdpe_to_pde(pdpe, va);
9234 MPASS((ptpaddr & X86_PG_V) != 0);
9235 if ((ptpaddr & PG_PS) != 0) {
9236 if (va + NBPDR == va_next && eva >= va_next) {
9237 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9239 if (newpde != ptpaddr) {
9244 } else if (!pmap_demote_pde(pmap, pde, va)) {
9252 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9253 ptep++, va += PAGE_SIZE) {
9255 if ((pte & X86_PG_V) == 0)
9257 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9258 if (newpte != pte) {
9265 pmap_invalidate_range(pmap, sva, eva);
9269 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9270 u_int keyidx, int flags)
9273 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9274 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9276 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9278 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9284 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9289 sva = trunc_page(sva);
9290 eva = round_page(eva);
9291 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9296 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9298 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9300 if (error != ENOMEM)
9308 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9312 sva = trunc_page(sva);
9313 eva = round_page(eva);
9314 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9319 error = pmap_pkru_deassign(pmap, sva, eva);
9321 pmap_pkru_update_range(pmap, sva, eva, 0);
9323 if (error != ENOMEM)
9330 #include "opt_ddb.h"
9332 #include <sys/kdb.h>
9333 #include <ddb/ddb.h>
9335 DB_SHOW_COMMAND(pte, pmap_print_pte)
9341 pt_entry_t *pte, PG_V;
9345 db_printf("show pte addr\n");
9348 va = (vm_offset_t)addr;
9350 if (kdb_thread != NULL)
9351 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
9353 pmap = PCPU_GET(curpmap);
9355 PG_V = pmap_valid_bit(pmap);
9356 pml4 = pmap_pml4e(pmap, va);
9357 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
9358 if ((*pml4 & PG_V) == 0) {
9362 pdp = pmap_pml4e_to_pdpe(pml4, va);
9363 db_printf(" pdpe %#016lx", *pdp);
9364 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
9368 pde = pmap_pdpe_to_pde(pdp, va);
9369 db_printf(" pde %#016lx", *pde);
9370 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
9374 pte = pmap_pde_to_pte(pde, va);
9375 db_printf(" pte %#016lx\n", *pte);
9378 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
9383 a = (vm_paddr_t)addr;
9384 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
9386 db_printf("show phys2dmap addr\n");