2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
107 #include <sys/bitstring.h>
109 #include <sys/systm.h>
110 #include <sys/kernel.h>
112 #include <sys/lock.h>
113 #include <sys/malloc.h>
114 #include <sys/mman.h>
115 #include <sys/mutex.h>
116 #include <sys/proc.h>
117 #include <sys/rwlock.h>
119 #include <sys/turnstile.h>
120 #include <sys/vmem.h>
121 #include <sys/vmmeter.h>
122 #include <sys/sched.h>
123 #include <sys/sysctl.h>
127 #include <vm/vm_param.h>
128 #include <vm/vm_kern.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_map.h>
131 #include <vm/vm_object.h>
132 #include <vm/vm_extern.h>
133 #include <vm/vm_pageout.h>
134 #include <vm/vm_pager.h>
135 #include <vm/vm_phys.h>
136 #include <vm/vm_radix.h>
137 #include <vm/vm_reserv.h>
140 #include <machine/intr_machdep.h>
141 #include <x86/apicvar.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
151 static __inline boolean_t
152 pmap_type_guest(pmap_t pmap)
155 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
158 static __inline boolean_t
159 pmap_emulate_ad_bits(pmap_t pmap)
162 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
165 static __inline pt_entry_t
166 pmap_valid_bit(pmap_t pmap)
170 switch (pmap->pm_type) {
176 if (pmap_emulate_ad_bits(pmap))
177 mask = EPT_PG_EMUL_V;
182 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
188 static __inline pt_entry_t
189 pmap_rw_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_RW;
205 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_global_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
225 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
231 static __inline pt_entry_t
232 pmap_accessed_bit(pmap_t pmap)
236 switch (pmap->pm_type) {
242 if (pmap_emulate_ad_bits(pmap))
248 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
254 static __inline pt_entry_t
255 pmap_modified_bit(pmap_t pmap)
259 switch (pmap->pm_type) {
265 if (pmap_emulate_ad_bits(pmap))
271 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
277 extern struct pcpu __pcpu[];
279 #if !defined(DIAGNOSTIC)
280 #ifdef __GNUC_GNU_INLINE__
281 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
283 #define PMAP_INLINE extern inline
290 #define PV_STAT(x) do { x ; } while (0)
292 #define PV_STAT(x) do { } while (0)
295 #define pa_index(pa) ((pa) >> PDRSHIFT)
296 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
298 #define NPV_LIST_LOCKS MAXCPU
300 #define PHYS_TO_PV_LIST_LOCK(pa) \
301 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
303 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
304 struct rwlock **_lockp = (lockp); \
305 struct rwlock *_new_lock; \
307 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
308 if (_new_lock != *_lockp) { \
309 if (*_lockp != NULL) \
310 rw_wunlock(*_lockp); \
311 *_lockp = _new_lock; \
316 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
317 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
319 #define RELEASE_PV_LIST_LOCK(lockp) do { \
320 struct rwlock **_lockp = (lockp); \
322 if (*_lockp != NULL) { \
323 rw_wunlock(*_lockp); \
328 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
329 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
331 struct pmap kernel_pmap_store;
333 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
334 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
337 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
338 "Number of kernel page table pages allocated on bootup");
341 vm_paddr_t dmaplimit;
342 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
345 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
347 static int pat_works = 1;
348 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
349 "Is page attribute table fully functional?");
351 static int pg_ps_enabled = 1;
352 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
353 &pg_ps_enabled, 0, "Are large page mappings enabled?");
355 #define PAT_INDEX_SIZE 8
356 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
358 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
359 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
360 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
361 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
363 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
364 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
365 static int ndmpdpphys; /* number of DMPDPphys pages */
368 * pmap_mapdev support pre initialization (i.e. console)
370 #define PMAP_PREINIT_MAPPING_COUNT 8
371 static struct pmap_preinit_mapping {
376 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
377 static int pmap_initialized;
380 * Data for the pv entry allocation mechanism.
381 * Updates to pv_invl_gen are protected by the pv_list_locks[]
382 * elements, but reads are not.
384 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
385 static struct mtx pv_chunks_mutex;
386 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
387 static u_long pv_invl_gen[NPV_LIST_LOCKS];
388 static struct md_page *pv_table;
389 static struct md_page pv_dummy;
392 * All those kernel PT submaps that BSD is so fond of
394 pt_entry_t *CMAP1 = NULL;
396 static vm_offset_t qframe = 0;
397 static struct mtx qframe_mtx;
399 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
401 int pmap_pcid_enabled = 1;
402 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
403 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
404 int invpcid_works = 0;
405 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
406 "Is the invpcid instruction available ?");
409 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
416 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
418 return (sysctl_handle_64(oidp, &res, 0, req));
420 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
421 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
422 "Count of saved TLB context on switch");
424 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
425 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
426 static struct mtx invl_gen_mtx;
427 static u_long pmap_invl_gen = 0;
428 /* Fake lock object to satisfy turnstiles interface. */
429 static struct lock_object invl_gen_ts = {
433 #define PMAP_ASSERT_NOT_IN_DI() \
434 KASSERT(curthread->td_md.md_invl_gen.gen == 0, ("DI already started"))
437 * Start a new Delayed Invalidation (DI) block of code, executed by
438 * the current thread. Within a DI block, the current thread may
439 * destroy both the page table and PV list entries for a mapping and
440 * then release the corresponding PV list lock before ensuring that
441 * the mapping is flushed from the TLBs of any processors with the
445 pmap_delayed_invl_started(void)
447 struct pmap_invl_gen *invl_gen;
450 invl_gen = &curthread->td_md.md_invl_gen;
451 PMAP_ASSERT_NOT_IN_DI();
452 mtx_lock(&invl_gen_mtx);
453 if (LIST_EMPTY(&pmap_invl_gen_tracker))
454 currgen = pmap_invl_gen;
456 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
457 invl_gen->gen = currgen + 1;
458 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
459 mtx_unlock(&invl_gen_mtx);
463 * Finish the DI block, previously started by the current thread. All
464 * required TLB flushes for the pages marked by
465 * pmap_delayed_invl_page() must be finished before this function is
468 * This function works by bumping the global DI generation number to
469 * the generation number of the current thread's DI, unless there is a
470 * pending DI that started earlier. In the latter case, bumping the
471 * global DI generation number would incorrectly signal that the
472 * earlier DI had finished. Instead, this function bumps the earlier
473 * DI's generation number to match the generation number of the
474 * current thread's DI.
477 pmap_delayed_invl_finished(void)
479 struct pmap_invl_gen *invl_gen, *next;
480 struct turnstile *ts;
482 invl_gen = &curthread->td_md.md_invl_gen;
483 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
484 mtx_lock(&invl_gen_mtx);
485 next = LIST_NEXT(invl_gen, link);
487 turnstile_chain_lock(&invl_gen_ts);
488 ts = turnstile_lookup(&invl_gen_ts);
489 pmap_invl_gen = invl_gen->gen;
491 turnstile_broadcast(ts, TS_SHARED_QUEUE);
492 turnstile_unpend(ts, TS_SHARED_LOCK);
494 turnstile_chain_unlock(&invl_gen_ts);
496 next->gen = invl_gen->gen;
498 LIST_REMOVE(invl_gen, link);
499 mtx_unlock(&invl_gen_mtx);
504 static long invl_wait;
505 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
506 "Number of times DI invalidation blocked pmap_remove_all/write");
510 pmap_delayed_invl_genp(vm_page_t m)
513 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
517 * Ensure that all currently executing DI blocks, that need to flush
518 * TLB for the given page m, actually flushed the TLB at the time the
519 * function returned. If the page m has an empty PV list and we call
520 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
521 * valid mapping for the page m in either its page table or TLB.
523 * This function works by blocking until the global DI generation
524 * number catches up with the generation number associated with the
525 * given page m and its PV list. Since this function's callers
526 * typically own an object lock and sometimes own a page lock, it
527 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
531 pmap_delayed_invl_wait(vm_page_t m)
534 struct turnstile *ts;
537 bool accounted = false;
541 m_gen = pmap_delayed_invl_genp(m);
542 while (*m_gen > pmap_invl_gen) {
545 atomic_add_long(&invl_wait, 1);
549 ts = turnstile_trywait(&invl_gen_ts);
550 if (*m_gen > pmap_invl_gen)
551 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
553 turnstile_cancel(ts);
558 * Mark the page m's PV list as participating in the current thread's
559 * DI block. Any threads concurrently using m's PV list to remove or
560 * restrict all mappings to m will wait for the current thread's DI
561 * block to complete before proceeding.
563 * The function works by setting the DI generation number for m's PV
564 * list to at least the DI generation number of the current thread.
565 * This forces a caller of pmap_delayed_invl_wait() to block until
566 * current thread calls pmap_delayed_invl_finished().
569 pmap_delayed_invl_page(vm_page_t m)
573 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
574 gen = curthread->td_md.md_invl_gen.gen;
577 m_gen = pmap_delayed_invl_genp(m);
585 static caddr_t crashdumpmap;
587 static void free_pv_chunk(struct pv_chunk *pc);
588 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
589 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
590 static int popcnt_pc_map_pq(uint64_t *map);
591 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
592 static void reserve_pv_entries(pmap_t pmap, int needed,
593 struct rwlock **lockp);
594 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
595 struct rwlock **lockp);
596 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
597 struct rwlock **lockp);
598 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
599 struct rwlock **lockp);
600 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
601 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
604 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
605 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
606 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
607 vm_offset_t va, struct rwlock **lockp);
608 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
610 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
611 vm_prot_t prot, struct rwlock **lockp);
612 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
613 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
614 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
615 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
616 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
618 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
619 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
620 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
621 struct rwlock **lockp);
622 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
624 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
625 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
626 struct spglist *free, struct rwlock **lockp);
627 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
628 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
629 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
630 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
631 struct spglist *free);
632 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
633 vm_page_t m, struct rwlock **lockp);
634 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
636 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
638 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
639 struct rwlock **lockp);
640 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
641 struct rwlock **lockp);
642 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
643 struct rwlock **lockp);
645 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
646 struct spglist *free);
647 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
648 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
651 * Move the kernel virtual free pointer to the next
652 * 2MB. This is used to help improve performance
653 * by using a large (2MB) page for much of the kernel
654 * (.text, .data, .bss)
657 pmap_kmem_choose(vm_offset_t addr)
659 vm_offset_t newaddr = addr;
661 newaddr = roundup2(addr, NBPDR);
665 /********************/
666 /* Inline functions */
667 /********************/
669 /* Return a non-clipped PD index for a given VA */
670 static __inline vm_pindex_t
671 pmap_pde_pindex(vm_offset_t va)
673 return (va >> PDRSHIFT);
677 /* Return a pointer to the PML4 slot that corresponds to a VA */
678 static __inline pml4_entry_t *
679 pmap_pml4e(pmap_t pmap, vm_offset_t va)
682 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
685 /* Return a pointer to the PDP slot that corresponds to a VA */
686 static __inline pdp_entry_t *
687 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
691 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
692 return (&pdpe[pmap_pdpe_index(va)]);
695 /* Return a pointer to the PDP slot that corresponds to a VA */
696 static __inline pdp_entry_t *
697 pmap_pdpe(pmap_t pmap, vm_offset_t va)
702 PG_V = pmap_valid_bit(pmap);
703 pml4e = pmap_pml4e(pmap, va);
704 if ((*pml4e & PG_V) == 0)
706 return (pmap_pml4e_to_pdpe(pml4e, va));
709 /* Return a pointer to the PD slot that corresponds to a VA */
710 static __inline pd_entry_t *
711 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
715 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
716 return (&pde[pmap_pde_index(va)]);
719 /* Return a pointer to the PD slot that corresponds to a VA */
720 static __inline pd_entry_t *
721 pmap_pde(pmap_t pmap, vm_offset_t va)
726 PG_V = pmap_valid_bit(pmap);
727 pdpe = pmap_pdpe(pmap, va);
728 if (pdpe == NULL || (*pdpe & PG_V) == 0)
730 return (pmap_pdpe_to_pde(pdpe, va));
733 /* Return a pointer to the PT slot that corresponds to a VA */
734 static __inline pt_entry_t *
735 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
739 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
740 return (&pte[pmap_pte_index(va)]);
743 /* Return a pointer to the PT slot that corresponds to a VA */
744 static __inline pt_entry_t *
745 pmap_pte(pmap_t pmap, vm_offset_t va)
750 PG_V = pmap_valid_bit(pmap);
751 pde = pmap_pde(pmap, va);
752 if (pde == NULL || (*pde & PG_V) == 0)
754 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
755 return ((pt_entry_t *)pde);
756 return (pmap_pde_to_pte(pde, va));
760 pmap_resident_count_inc(pmap_t pmap, int count)
763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
764 pmap->pm_stats.resident_count += count;
768 pmap_resident_count_dec(pmap_t pmap, int count)
771 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
772 KASSERT(pmap->pm_stats.resident_count >= count,
773 ("pmap %p resident count underflow %ld %d", pmap,
774 pmap->pm_stats.resident_count, count));
775 pmap->pm_stats.resident_count -= count;
778 PMAP_INLINE pt_entry_t *
779 vtopte(vm_offset_t va)
781 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
783 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
785 return (PTmap + ((va >> PAGE_SHIFT) & mask));
788 static __inline pd_entry_t *
789 vtopde(vm_offset_t va)
791 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
793 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
795 return (PDmap + ((va >> PDRSHIFT) & mask));
799 allocpages(vm_paddr_t *firstaddr, int n)
804 bzero((void *)ret, n * PAGE_SIZE);
805 *firstaddr += n * PAGE_SIZE;
809 CTASSERT(powerof2(NDMPML4E));
811 /* number of kernel PDP slots */
812 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
815 nkpt_init(vm_paddr_t addr)
822 pt_pages = howmany(addr, 1 << PDRSHIFT);
823 pt_pages += NKPDPE(pt_pages);
826 * Add some slop beyond the bare minimum required for bootstrapping
829 * This is quite important when allocating KVA for kernel modules.
830 * The modules are required to be linked in the negative 2GB of
831 * the address space. If we run out of KVA in this region then
832 * pmap_growkernel() will need to allocate page table pages to map
833 * the entire 512GB of KVA space which is an unnecessary tax on
836 * Secondly, device memory mapped as part of setting up the low-
837 * level console(s) is taken from KVA, starting at virtual_avail.
838 * This is because cninit() is called after pmap_bootstrap() but
839 * before vm_init() and pmap_init(). 20MB for a frame buffer is
842 pt_pages += 32; /* 64MB additional slop. */
848 create_pagetables(vm_paddr_t *firstaddr)
850 int i, j, ndm1g, nkpdpe;
856 /* Allocate page table pages for the direct map */
857 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
858 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
860 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
861 if (ndmpdpphys > NDMPML4E) {
863 * Each NDMPML4E allows 512 GB, so limit to that,
864 * and then readjust ndmpdp and ndmpdpphys.
866 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
867 Maxmem = atop(NDMPML4E * NBPML4);
868 ndmpdpphys = NDMPML4E;
869 ndmpdp = NDMPML4E * NPDEPG;
871 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
873 if ((amd_feature & AMDID_PAGE1GB) != 0)
874 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
876 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
877 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
880 KPML4phys = allocpages(firstaddr, 1);
881 KPDPphys = allocpages(firstaddr, NKPML4E);
884 * Allocate the initial number of kernel page table pages required to
885 * bootstrap. We defer this until after all memory-size dependent
886 * allocations are done (e.g. direct map), so that we don't have to
887 * build in too much slop in our estimate.
889 * Note that when NKPML4E > 1, we have an empty page underneath
890 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
891 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
893 nkpt_init(*firstaddr);
894 nkpdpe = NKPDPE(nkpt);
896 KPTphys = allocpages(firstaddr, nkpt);
897 KPDphys = allocpages(firstaddr, nkpdpe);
899 /* Fill in the underlying page table pages */
900 /* Nominally read-only (but really R/W) from zero to physfree */
901 /* XXX not fully used, underneath 2M pages */
902 pt_p = (pt_entry_t *)KPTphys;
903 for (i = 0; ptoa(i) < *firstaddr; i++)
904 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
906 /* Now map the page tables at their location within PTmap */
907 pd_p = (pd_entry_t *)KPDphys;
908 for (i = 0; i < nkpt; i++)
909 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
911 /* Map from zero to end of allocations under 2M pages */
912 /* This replaces some of the KPTphys entries above */
913 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
914 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
917 /* And connect up the PD to the PDP (leaving room for L4 pages) */
918 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
919 for (i = 0; i < nkpdpe; i++)
920 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
924 * Now, set up the direct map region using 2MB and/or 1GB pages. If
925 * the end of physical memory is not aligned to a 1GB page boundary,
926 * then the residual physical memory is mapped with 2MB pages. Later,
927 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
928 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
929 * that are partially used.
931 pd_p = (pd_entry_t *)DMPDphys;
932 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
933 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
934 /* Preset PG_M and PG_A because demotion expects it. */
935 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
938 pdp_p = (pdp_entry_t *)DMPDPphys;
939 for (i = 0; i < ndm1g; i++) {
940 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
941 /* Preset PG_M and PG_A because demotion expects it. */
942 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
945 for (j = 0; i < ndmpdp; i++, j++) {
946 pdp_p[i] = DMPDphys + ptoa(j);
947 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
950 /* And recursively map PML4 to itself in order to get PTmap */
951 p4_p = (pml4_entry_t *)KPML4phys;
952 p4_p[PML4PML4I] = KPML4phys;
953 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
955 /* Connect the Direct Map slot(s) up to the PML4. */
956 for (i = 0; i < ndmpdpphys; i++) {
957 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
958 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
961 /* Connect the KVA slots up to the PML4 */
962 for (i = 0; i < NKPML4E; i++) {
963 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
964 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
969 * Bootstrap the system enough to run with virtual memory.
971 * On amd64 this is called after mapping has already been enabled
972 * and just syncs the pmap module with what has already been done.
973 * [We can't call it easily with mapping off since the kernel is not
974 * mapped with PA == VA, hence we would have to relocate every address
975 * from the linked base (virtual) address "KERNBASE" to the actual
976 * (physical) address starting relative to 0]
979 pmap_bootstrap(vm_paddr_t *firstaddr)
986 * Create an initial set of page tables to run the kernel in.
988 create_pagetables(firstaddr);
991 * Add a physical memory segment (vm_phys_seg) corresponding to the
992 * preallocated kernel page table pages so that vm_page structures
993 * representing these pages will be created. The vm_page structures
994 * are required for promotion of the corresponding kernel virtual
995 * addresses to superpage mappings.
997 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
999 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1000 virtual_avail = pmap_kmem_choose(virtual_avail);
1002 virtual_end = VM_MAX_KERNEL_ADDRESS;
1005 /* XXX do %cr0 as well */
1006 load_cr4(rcr4() | CR4_PGE);
1007 load_cr3(KPML4phys);
1008 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1009 load_cr4(rcr4() | CR4_SMEP);
1012 * Initialize the kernel pmap (which is statically allocated).
1014 PMAP_LOCK_INIT(kernel_pmap);
1015 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1016 kernel_pmap->pm_cr3 = KPML4phys;
1017 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1018 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1019 kernel_pmap->pm_flags = pmap_flags;
1022 * Initialize the TLB invalidations generation number lock.
1024 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1027 * Reserve some special page table entries/VA space for temporary
1030 #define SYSMAP(c, p, v, n) \
1031 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1037 * Crashdump maps. The first page is reused as CMAP1 for the
1040 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1041 CADDR1 = crashdumpmap;
1046 * Initialize the PAT MSR.
1047 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1048 * side-effect, invalidates stale PG_G TLB entries that might
1049 * have been created in our pre-boot environment.
1053 /* Initialize TLB Context Id. */
1054 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
1055 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
1056 /* Check for INVPCID support */
1057 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
1059 for (i = 0; i < MAXCPU; i++) {
1060 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1061 kernel_pmap->pm_pcids[i].pm_gen = 1;
1063 __pcpu[0].pc_pcid_next = PMAP_PCID_KERN + 1;
1064 __pcpu[0].pc_pcid_gen = 1;
1066 * pcpu area for APs is zeroed during AP startup.
1067 * pc_pcid_next and pc_pcid_gen are initialized by AP
1068 * during pcpu setup.
1070 load_cr4(rcr4() | CR4_PCIDE);
1072 pmap_pcid_enabled = 0;
1077 * Setup the PAT MSR.
1082 int pat_table[PAT_INDEX_SIZE];
1087 /* Bail if this CPU doesn't implement PAT. */
1088 if ((cpu_feature & CPUID_PAT) == 0)
1091 /* Set default PAT index table. */
1092 for (i = 0; i < PAT_INDEX_SIZE; i++)
1094 pat_table[PAT_WRITE_BACK] = 0;
1095 pat_table[PAT_WRITE_THROUGH] = 1;
1096 pat_table[PAT_UNCACHEABLE] = 3;
1097 pat_table[PAT_WRITE_COMBINING] = 3;
1098 pat_table[PAT_WRITE_PROTECTED] = 3;
1099 pat_table[PAT_UNCACHED] = 3;
1101 /* Initialize default PAT entries. */
1102 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1103 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1104 PAT_VALUE(2, PAT_UNCACHED) |
1105 PAT_VALUE(3, PAT_UNCACHEABLE) |
1106 PAT_VALUE(4, PAT_WRITE_BACK) |
1107 PAT_VALUE(5, PAT_WRITE_THROUGH) |
1108 PAT_VALUE(6, PAT_UNCACHED) |
1109 PAT_VALUE(7, PAT_UNCACHEABLE);
1113 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1114 * Program 5 and 6 as WP and WC.
1115 * Leave 4 and 7 as WB and UC.
1117 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
1118 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1119 PAT_VALUE(6, PAT_WRITE_COMBINING);
1120 pat_table[PAT_UNCACHED] = 2;
1121 pat_table[PAT_WRITE_PROTECTED] = 5;
1122 pat_table[PAT_WRITE_COMBINING] = 6;
1125 * Just replace PAT Index 2 with WC instead of UC-.
1127 pat_msr &= ~PAT_MASK(2);
1128 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
1129 pat_table[PAT_WRITE_COMBINING] = 2;
1134 load_cr4(cr4 & ~CR4_PGE);
1136 /* Disable caches (CD = 1, NW = 0). */
1138 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1140 /* Flushes caches and TLBs. */
1144 /* Update PAT and index table. */
1145 wrmsr(MSR_PAT, pat_msr);
1146 for (i = 0; i < PAT_INDEX_SIZE; i++)
1147 pat_index[i] = pat_table[i];
1149 /* Flush caches and TLBs again. */
1153 /* Restore caches and PGE. */
1159 * Initialize a vm_page's machine-dependent fields.
1162 pmap_page_init(vm_page_t m)
1165 TAILQ_INIT(&m->md.pv_list);
1166 m->md.pat_mode = PAT_WRITE_BACK;
1170 * Initialize the pmap module.
1171 * Called by vm_init, to initialize any structures that the pmap
1172 * system needs to map virtual memory.
1177 struct pmap_preinit_mapping *ppim;
1180 int error, i, pv_npg;
1183 * Initialize the vm page array entries for the kernel pmap's
1186 for (i = 0; i < nkpt; i++) {
1187 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1188 KASSERT(mpte >= vm_page_array &&
1189 mpte < &vm_page_array[vm_page_array_size],
1190 ("pmap_init: page table page is out of range"));
1191 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1192 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1196 * If the kernel is running on a virtual machine, then it must assume
1197 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1198 * be prepared for the hypervisor changing the vendor and family that
1199 * are reported by CPUID. Consequently, the workaround for AMD Family
1200 * 10h Erratum 383 is enabled if the processor's feature set does not
1201 * include at least one feature that is only supported by older Intel
1202 * or newer AMD processors.
1204 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1205 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1206 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1208 workaround_erratum383 = 1;
1211 * Are large page mappings enabled?
1213 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1214 if (pg_ps_enabled) {
1215 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1216 ("pmap_init: can't assign to pagesizes[1]"));
1217 pagesizes[1] = NBPDR;
1221 * Initialize the pv chunk list mutex.
1223 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1226 * Initialize the pool of pv list locks.
1228 for (i = 0; i < NPV_LIST_LOCKS; i++)
1229 rw_init(&pv_list_locks[i], "pmap pv list");
1232 * Calculate the size of the pv head table for superpages.
1234 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1237 * Allocate memory for the pv head table for superpages.
1239 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1241 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1243 for (i = 0; i < pv_npg; i++)
1244 TAILQ_INIT(&pv_table[i].pv_list);
1245 TAILQ_INIT(&pv_dummy.pv_list);
1247 pmap_initialized = 1;
1248 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1249 ppim = pmap_preinit_mapping + i;
1252 /* Make the direct map consistent */
1253 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1254 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1255 ppim->sz, ppim->mode);
1259 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1260 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1263 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1264 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1265 (vmem_addr_t *)&qframe);
1267 panic("qframe allocation failed");
1270 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1271 "2MB page mapping counters");
1273 static u_long pmap_pde_demotions;
1274 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1275 &pmap_pde_demotions, 0, "2MB page demotions");
1277 static u_long pmap_pde_mappings;
1278 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1279 &pmap_pde_mappings, 0, "2MB page mappings");
1281 static u_long pmap_pde_p_failures;
1282 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1283 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1285 static u_long pmap_pde_promotions;
1286 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1287 &pmap_pde_promotions, 0, "2MB page promotions");
1289 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1290 "1GB page mapping counters");
1292 static u_long pmap_pdpe_demotions;
1293 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1294 &pmap_pdpe_demotions, 0, "1GB page demotions");
1296 /***************************************************
1297 * Low level helper routines.....
1298 ***************************************************/
1301 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1303 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1305 switch (pmap->pm_type) {
1308 /* Verify that both PAT bits are not set at the same time */
1309 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1310 ("Invalid PAT bits in entry %#lx", entry));
1312 /* Swap the PAT bits if one of them is set */
1313 if ((entry & x86_pat_bits) != 0)
1314 entry ^= x86_pat_bits;
1318 * Nothing to do - the memory attributes are represented
1319 * the same way for regular pages and superpages.
1323 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1330 * Determine the appropriate bits to set in a PTE or PDE for a specified
1334 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1336 int cache_bits, pat_flag, pat_idx;
1338 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1339 panic("Unknown caching mode %d\n", mode);
1341 switch (pmap->pm_type) {
1344 /* The PAT bit is different for PTE's and PDE's. */
1345 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1347 /* Map the caching mode to a PAT index. */
1348 pat_idx = pat_index[mode];
1350 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1353 cache_bits |= pat_flag;
1355 cache_bits |= PG_NC_PCD;
1357 cache_bits |= PG_NC_PWT;
1361 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1365 panic("unsupported pmap type %d", pmap->pm_type);
1368 return (cache_bits);
1372 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1376 switch (pmap->pm_type) {
1379 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1382 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1385 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1391 static __inline boolean_t
1392 pmap_ps_enabled(pmap_t pmap)
1395 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1399 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1402 switch (pmap->pm_type) {
1409 * This is a little bogus since the generation number is
1410 * supposed to be bumped up when a region of the address
1411 * space is invalidated in the page tables.
1413 * In this case the old PDE entry is valid but yet we want
1414 * to make sure that any mappings using the old entry are
1415 * invalidated in the TLB.
1417 * The reason this works as expected is because we rendezvous
1418 * "all" host cpus and force any vcpu context to exit as a
1421 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1424 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1426 pde_store(pde, newpde);
1430 * After changing the page size for the specified virtual address in the page
1431 * table, flush the corresponding entries from the processor's TLB. Only the
1432 * calling processor's TLB is affected.
1434 * The calling thread must be pinned to a processor.
1437 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1441 if (pmap_type_guest(pmap))
1444 KASSERT(pmap->pm_type == PT_X86,
1445 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1447 PG_G = pmap_global_bit(pmap);
1449 if ((newpde & PG_PS) == 0)
1450 /* Demotion: flush a specific 2MB page mapping. */
1452 else if ((newpde & PG_G) == 0)
1454 * Promotion: flush every 4KB page mapping from the TLB
1455 * because there are too many to flush individually.
1460 * Promotion: flush every 4KB page mapping from the TLB,
1461 * including any global (PG_G) mappings.
1469 * For SMP, these functions have to use the IPI mechanism for coherence.
1471 * N.B.: Before calling any of the following TLB invalidation functions,
1472 * the calling processor must ensure that all stores updating a non-
1473 * kernel page table are globally performed. Otherwise, another
1474 * processor could cache an old, pre-update entry without being
1475 * invalidated. This can happen one of two ways: (1) The pmap becomes
1476 * active on another processor after its pm_active field is checked by
1477 * one of the following functions but before a store updating the page
1478 * table is globally performed. (2) The pmap becomes active on another
1479 * processor before its pm_active field is checked but due to
1480 * speculative loads one of the following functions stills reads the
1481 * pmap as inactive on the other processor.
1483 * The kernel page table is exempt because its pm_active field is
1484 * immutable. The kernel page table is always active on every
1489 * Interrupt the cpus that are executing in the guest context.
1490 * This will force the vcpu to exit and the cached EPT mappings
1491 * will be invalidated by the host before the next vmresume.
1493 static __inline void
1494 pmap_invalidate_ept(pmap_t pmap)
1499 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1500 ("pmap_invalidate_ept: absurd pm_active"));
1503 * The TLB mappings associated with a vcpu context are not
1504 * flushed each time a different vcpu is chosen to execute.
1506 * This is in contrast with a process's vtop mappings that
1507 * are flushed from the TLB on each context switch.
1509 * Therefore we need to do more than just a TLB shootdown on
1510 * the active cpus in 'pmap->pm_active'. To do this we keep
1511 * track of the number of invalidations performed on this pmap.
1513 * Each vcpu keeps a cache of this counter and compares it
1514 * just before a vmresume. If the counter is out-of-date an
1515 * invept will be done to flush stale mappings from the TLB.
1517 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1520 * Force the vcpu to exit and trap back into the hypervisor.
1522 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1523 ipi_selected(pmap->pm_active, ipinum);
1528 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1533 if (pmap_type_guest(pmap)) {
1534 pmap_invalidate_ept(pmap);
1538 KASSERT(pmap->pm_type == PT_X86,
1539 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1542 if (pmap == kernel_pmap) {
1546 cpuid = PCPU_GET(cpuid);
1547 if (pmap == PCPU_GET(curpmap))
1549 else if (pmap_pcid_enabled)
1550 pmap->pm_pcids[cpuid].pm_gen = 0;
1551 if (pmap_pcid_enabled) {
1554 pmap->pm_pcids[i].pm_gen = 0;
1557 mask = &pmap->pm_active;
1559 smp_masked_invlpg(*mask, va);
1563 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1564 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1567 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1573 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1574 pmap_invalidate_all(pmap);
1578 if (pmap_type_guest(pmap)) {
1579 pmap_invalidate_ept(pmap);
1583 KASSERT(pmap->pm_type == PT_X86,
1584 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1587 cpuid = PCPU_GET(cpuid);
1588 if (pmap == kernel_pmap) {
1589 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1593 if (pmap == PCPU_GET(curpmap)) {
1594 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1596 } else if (pmap_pcid_enabled) {
1597 pmap->pm_pcids[cpuid].pm_gen = 0;
1599 if (pmap_pcid_enabled) {
1602 pmap->pm_pcids[i].pm_gen = 0;
1605 mask = &pmap->pm_active;
1607 smp_masked_invlpg_range(*mask, sva, eva);
1612 pmap_invalidate_all(pmap_t pmap)
1615 struct invpcid_descr d;
1618 if (pmap_type_guest(pmap)) {
1619 pmap_invalidate_ept(pmap);
1623 KASSERT(pmap->pm_type == PT_X86,
1624 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1627 if (pmap == kernel_pmap) {
1628 if (pmap_pcid_enabled && invpcid_works) {
1629 bzero(&d, sizeof(d));
1630 invpcid(&d, INVPCID_CTXGLOB);
1636 cpuid = PCPU_GET(cpuid);
1637 if (pmap == PCPU_GET(curpmap)) {
1638 if (pmap_pcid_enabled) {
1639 if (invpcid_works) {
1640 d.pcid = pmap->pm_pcids[cpuid].pm_pcid;
1643 invpcid(&d, INVPCID_CTX);
1645 load_cr3(pmap->pm_cr3 | pmap->pm_pcids
1646 [PCPU_GET(cpuid)].pm_pcid);
1651 } else if (pmap_pcid_enabled) {
1652 pmap->pm_pcids[cpuid].pm_gen = 0;
1654 if (pmap_pcid_enabled) {
1657 pmap->pm_pcids[i].pm_gen = 0;
1660 mask = &pmap->pm_active;
1662 smp_masked_invltlb(*mask, pmap);
1667 pmap_invalidate_cache(void)
1677 cpuset_t invalidate; /* processors that invalidate their TLB */
1682 u_int store; /* processor that updates the PDE */
1686 pmap_update_pde_action(void *arg)
1688 struct pde_action *act = arg;
1690 if (act->store == PCPU_GET(cpuid))
1691 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1695 pmap_update_pde_teardown(void *arg)
1697 struct pde_action *act = arg;
1699 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1700 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1704 * Change the page size for the specified virtual address in a way that
1705 * prevents any possibility of the TLB ever having two entries that map the
1706 * same virtual address using different page sizes. This is the recommended
1707 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1708 * machine check exception for a TLB state that is improperly diagnosed as a
1712 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1714 struct pde_action act;
1715 cpuset_t active, other_cpus;
1719 cpuid = PCPU_GET(cpuid);
1720 other_cpus = all_cpus;
1721 CPU_CLR(cpuid, &other_cpus);
1722 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1725 active = pmap->pm_active;
1727 if (CPU_OVERLAP(&active, &other_cpus)) {
1729 act.invalidate = active;
1733 act.newpde = newpde;
1734 CPU_SET(cpuid, &active);
1735 smp_rendezvous_cpus(active,
1736 smp_no_rendevous_barrier, pmap_update_pde_action,
1737 pmap_update_pde_teardown, &act);
1739 pmap_update_pde_store(pmap, pde, newpde);
1740 if (CPU_ISSET(cpuid, &active))
1741 pmap_update_pde_invalidate(pmap, va, newpde);
1747 * Normal, non-SMP, invalidation functions.
1750 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1753 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1757 KASSERT(pmap->pm_type == PT_X86,
1758 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
1760 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
1762 else if (pmap_pcid_enabled)
1763 pmap->pm_pcids[0].pm_gen = 0;
1767 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1771 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1775 KASSERT(pmap->pm_type == PT_X86,
1776 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
1778 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
1779 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1781 } else if (pmap_pcid_enabled) {
1782 pmap->pm_pcids[0].pm_gen = 0;
1787 pmap_invalidate_all(pmap_t pmap)
1789 struct invpcid_descr d;
1791 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1795 KASSERT(pmap->pm_type == PT_X86,
1796 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
1798 if (pmap == kernel_pmap) {
1799 if (pmap_pcid_enabled && invpcid_works) {
1800 bzero(&d, sizeof(d));
1801 invpcid(&d, INVPCID_CTXGLOB);
1805 } else if (pmap == PCPU_GET(curpmap)) {
1806 if (pmap_pcid_enabled) {
1807 if (invpcid_works) {
1808 d.pcid = pmap->pm_pcids[0].pm_pcid;
1811 invpcid(&d, INVPCID_CTX);
1813 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[0].
1819 } else if (pmap_pcid_enabled) {
1820 pmap->pm_pcids[0].pm_gen = 0;
1825 pmap_invalidate_cache(void)
1832 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1835 pmap_update_pde_store(pmap, pde, newpde);
1836 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
1837 pmap_update_pde_invalidate(pmap, va, newpde);
1839 pmap->pm_pcids[0].pm_gen = 0;
1844 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1848 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
1849 * by a promotion that did not invalidate the 512 4KB page mappings
1850 * that might exist in the TLB. Consequently, at this point, the TLB
1851 * may hold both 4KB and 2MB page mappings for the address range [va,
1852 * va + NBPDR). Therefore, the entire range must be invalidated here.
1853 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
1854 * 4KB page mappings for the address range [va, va + NBPDR), and so a
1855 * single INVLPG suffices to invalidate the 2MB page mapping from the
1858 if ((pde & PG_PROMOTED) != 0)
1859 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
1861 pmap_invalidate_page(pmap, va);
1864 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1867 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1871 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1873 KASSERT((sva & PAGE_MASK) == 0,
1874 ("pmap_invalidate_cache_range: sva not page-aligned"));
1875 KASSERT((eva & PAGE_MASK) == 0,
1876 ("pmap_invalidate_cache_range: eva not page-aligned"));
1879 if ((cpu_feature & CPUID_SS) != 0 && !force)
1880 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1881 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1882 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1884 * XXX: Some CPUs fault, hang, or trash the local APIC
1885 * registers if we use CLFLUSH on the local APIC
1886 * range. The local APIC is always uncached, so we
1887 * don't need to flush for that range anyway.
1889 if (pmap_kextract(sva) == lapic_paddr)
1893 * Otherwise, do per-cache line flush. Use the sfence
1894 * instruction to insure that previous stores are
1895 * included in the write-back. The processor
1896 * propagates flush to other processors in the cache
1900 for (; sva < eva; sva += cpu_clflush_line_size)
1903 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1904 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1905 if (pmap_kextract(sva) == lapic_paddr)
1908 * Writes are ordered by CLFLUSH on Intel CPUs.
1910 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1912 for (; sva < eva; sva += cpu_clflush_line_size)
1914 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1919 * No targeted cache flush methods are supported by CPU,
1920 * or the supplied range is bigger than 2MB.
1921 * Globally invalidate cache.
1923 pmap_invalidate_cache();
1928 * Remove the specified set of pages from the data and instruction caches.
1930 * In contrast to pmap_invalidate_cache_range(), this function does not
1931 * rely on the CPU's self-snoop feature, because it is intended for use
1932 * when moving pages into a different cache domain.
1935 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1937 vm_offset_t daddr, eva;
1941 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
1942 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1943 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
1944 pmap_invalidate_cache();
1948 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
1950 for (i = 0; i < count; i++) {
1951 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1952 eva = daddr + PAGE_SIZE;
1953 for (; daddr < eva; daddr += cpu_clflush_line_size) {
1962 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
1968 * Routine: pmap_extract
1970 * Extract the physical page address associated
1971 * with the given map/virtual_address pair.
1974 pmap_extract(pmap_t pmap, vm_offset_t va)
1978 pt_entry_t *pte, PG_V;
1982 PG_V = pmap_valid_bit(pmap);
1984 pdpe = pmap_pdpe(pmap, va);
1985 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1986 if ((*pdpe & PG_PS) != 0)
1987 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1989 pde = pmap_pdpe_to_pde(pdpe, va);
1990 if ((*pde & PG_V) != 0) {
1991 if ((*pde & PG_PS) != 0) {
1992 pa = (*pde & PG_PS_FRAME) |
1995 pte = pmap_pde_to_pte(pde, va);
1996 pa = (*pte & PG_FRAME) |
2007 * Routine: pmap_extract_and_hold
2009 * Atomically extract and hold the physical page
2010 * with the given pmap and virtual address pair
2011 * if that mapping permits the given protection.
2014 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2016 pd_entry_t pde, *pdep;
2017 pt_entry_t pte, PG_RW, PG_V;
2023 PG_RW = pmap_rw_bit(pmap);
2024 PG_V = pmap_valid_bit(pmap);
2027 pdep = pmap_pde(pmap, va);
2028 if (pdep != NULL && (pde = *pdep)) {
2030 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2031 if (vm_page_pa_tryrelock(pmap, (pde &
2032 PG_PS_FRAME) | (va & PDRMASK), &pa))
2034 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
2039 pte = *pmap_pde_to_pte(pdep, va);
2041 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2042 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2045 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
2056 pmap_kextract(vm_offset_t va)
2061 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2062 pa = DMAP_TO_PHYS(va);
2066 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2069 * Beware of a concurrent promotion that changes the
2070 * PDE at this point! For example, vtopte() must not
2071 * be used to access the PTE because it would use the
2072 * new PDE. It is, however, safe to use the old PDE
2073 * because the page table page is preserved by the
2076 pa = *pmap_pde_to_pte(&pde, va);
2077 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2083 /***************************************************
2084 * Low level mapping routines.....
2085 ***************************************************/
2088 * Add a wired page to the kva.
2089 * Note: not SMP coherent.
2092 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2097 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
2100 static __inline void
2101 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2107 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2108 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
2112 * Remove a page from the kernel pagetables.
2113 * Note: not SMP coherent.
2116 pmap_kremove(vm_offset_t va)
2125 * Used to map a range of physical addresses into kernel
2126 * virtual address space.
2128 * The value passed in '*virt' is a suggested virtual address for
2129 * the mapping. Architectures which can support a direct-mapped
2130 * physical to virtual region can return the appropriate address
2131 * within that region, leaving '*virt' unchanged. Other
2132 * architectures should map the pages starting at '*virt' and
2133 * update '*virt' with the first usable address after the mapped
2137 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2139 return PHYS_TO_DMAP(start);
2144 * Add a list of wired pages to the kva
2145 * this routine is only used for temporary
2146 * kernel mappings that do not need to have
2147 * page modification or references recorded.
2148 * Note that old mappings are simply written
2149 * over. The page *must* be wired.
2150 * Note: SMP coherent. Uses a ranged shootdown IPI.
2153 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2155 pt_entry_t *endpte, oldpte, pa, *pte;
2161 endpte = pte + count;
2162 while (pte < endpte) {
2164 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2165 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2166 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2168 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
2172 if (__predict_false((oldpte & X86_PG_V) != 0))
2173 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2178 * This routine tears out page mappings from the
2179 * kernel -- it is meant only for temporary mappings.
2180 * Note: SMP coherent. Uses a ranged shootdown IPI.
2183 pmap_qremove(vm_offset_t sva, int count)
2188 while (count-- > 0) {
2189 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2193 pmap_invalidate_range(kernel_pmap, sva, va);
2196 /***************************************************
2197 * Page table page management routines.....
2198 ***************************************************/
2199 static __inline void
2200 pmap_free_zero_pages(struct spglist *free)
2204 while ((m = SLIST_FIRST(free)) != NULL) {
2205 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2206 /* Preserve the page's PG_ZERO setting. */
2207 vm_page_free_toq(m);
2212 * Schedule the specified unused page table page to be freed. Specifically,
2213 * add the page to the specified list of pages that will be released to the
2214 * physical memory manager after the TLB has been updated.
2216 static __inline void
2217 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2218 boolean_t set_PG_ZERO)
2222 m->flags |= PG_ZERO;
2224 m->flags &= ~PG_ZERO;
2225 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2229 * Inserts the specified page table page into the specified pmap's collection
2230 * of idle page table pages. Each of a pmap's page table pages is responsible
2231 * for mapping a distinct range of virtual addresses. The pmap's collection is
2232 * ordered by this virtual address range.
2235 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2238 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2239 return (vm_radix_insert(&pmap->pm_root, mpte));
2243 * Removes the page table page mapping the specified virtual address from the
2244 * specified pmap's collection of idle page table pages, and returns it.
2245 * Otherwise, returns NULL if there is no page table page corresponding to the
2246 * specified virtual address.
2248 static __inline vm_page_t
2249 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2252 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2253 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2257 * Decrements a page table page's wire count, which is used to record the
2258 * number of valid page table entries within the page. If the wire count
2259 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2260 * page table page was unmapped and FALSE otherwise.
2262 static inline boolean_t
2263 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2267 if (m->wire_count == 0) {
2268 _pmap_unwire_ptp(pmap, va, m, free);
2275 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2278 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2280 * unmap the page table page
2282 if (m->pindex >= (NUPDE + NUPDPE)) {
2285 pml4 = pmap_pml4e(pmap, va);
2287 } else if (m->pindex >= NUPDE) {
2290 pdp = pmap_pdpe(pmap, va);
2295 pd = pmap_pde(pmap, va);
2298 pmap_resident_count_dec(pmap, 1);
2299 if (m->pindex < NUPDE) {
2300 /* We just released a PT, unhold the matching PD */
2303 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2304 pmap_unwire_ptp(pmap, va, pdpg, free);
2306 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2307 /* We just released a PD, unhold the matching PDP */
2310 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2311 pmap_unwire_ptp(pmap, va, pdppg, free);
2315 * This is a release store so that the ordinary store unmapping
2316 * the page table page is globally performed before TLB shoot-
2319 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2322 * Put page on a list so that it is released after
2323 * *ALL* TLB shootdown is done
2325 pmap_add_delayed_free_list(m, free, TRUE);
2329 * After removing a page table entry, this routine is used to
2330 * conditionally free the page, and manage the hold/wire counts.
2333 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2334 struct spglist *free)
2338 if (va >= VM_MAXUSER_ADDRESS)
2340 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2341 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2342 return (pmap_unwire_ptp(pmap, va, mpte, free));
2346 pmap_pinit0(pmap_t pmap)
2350 PMAP_LOCK_INIT(pmap);
2351 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2352 pmap->pm_cr3 = KPML4phys;
2353 pmap->pm_root.rt_root = 0;
2354 CPU_ZERO(&pmap->pm_active);
2355 TAILQ_INIT(&pmap->pm_pvchunk);
2356 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2357 pmap->pm_flags = pmap_flags;
2359 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2360 pmap->pm_pcids[i].pm_gen = 0;
2362 PCPU_SET(curpmap, kernel_pmap);
2363 pmap_activate(curthread);
2364 CPU_FILL(&kernel_pmap->pm_active);
2368 pmap_pinit_pml4(vm_page_t pml4pg)
2370 pml4_entry_t *pm_pml4;
2373 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2375 /* Wire in kernel global address entries. */
2376 for (i = 0; i < NKPML4E; i++) {
2377 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2380 for (i = 0; i < ndmpdpphys; i++) {
2381 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2385 /* install self-referential address mapping entry(s) */
2386 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2387 X86_PG_A | X86_PG_M;
2391 * Initialize a preallocated and zeroed pmap structure,
2392 * such as one in a vmspace structure.
2395 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2398 vm_paddr_t pml4phys;
2402 * allocate the page directory page
2404 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2405 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2408 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2409 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2411 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2412 pmap->pm_pcids[i].pm_gen = 0;
2414 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2416 if ((pml4pg->flags & PG_ZERO) == 0)
2417 pagezero(pmap->pm_pml4);
2420 * Do not install the host kernel mappings in the nested page
2421 * tables. These mappings are meaningless in the guest physical
2424 if ((pmap->pm_type = pm_type) == PT_X86) {
2425 pmap->pm_cr3 = pml4phys;
2426 pmap_pinit_pml4(pml4pg);
2429 pmap->pm_root.rt_root = 0;
2430 CPU_ZERO(&pmap->pm_active);
2431 TAILQ_INIT(&pmap->pm_pvchunk);
2432 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2433 pmap->pm_flags = flags;
2434 pmap->pm_eptgen = 0;
2440 pmap_pinit(pmap_t pmap)
2443 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2447 * This routine is called if the desired page table page does not exist.
2449 * If page table page allocation fails, this routine may sleep before
2450 * returning NULL. It sleeps only if a lock pointer was given.
2452 * Note: If a page allocation fails at page table level two or three,
2453 * one or two pages may be held during the wait, only to be released
2454 * afterwards. This conservative approach is easily argued to avoid
2458 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2460 vm_page_t m, pdppg, pdpg;
2461 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2463 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2465 PG_A = pmap_accessed_bit(pmap);
2466 PG_M = pmap_modified_bit(pmap);
2467 PG_V = pmap_valid_bit(pmap);
2468 PG_RW = pmap_rw_bit(pmap);
2471 * Allocate a page table page.
2473 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2474 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2475 if (lockp != NULL) {
2476 RELEASE_PV_LIST_LOCK(lockp);
2478 PMAP_ASSERT_NOT_IN_DI();
2484 * Indicate the need to retry. While waiting, the page table
2485 * page may have been allocated.
2489 if ((m->flags & PG_ZERO) == 0)
2493 * Map the pagetable page into the process address space, if
2494 * it isn't already there.
2497 if (ptepindex >= (NUPDE + NUPDPE)) {
2499 vm_pindex_t pml4index;
2501 /* Wire up a new PDPE page */
2502 pml4index = ptepindex - (NUPDE + NUPDPE);
2503 pml4 = &pmap->pm_pml4[pml4index];
2504 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2506 } else if (ptepindex >= NUPDE) {
2507 vm_pindex_t pml4index;
2508 vm_pindex_t pdpindex;
2512 /* Wire up a new PDE page */
2513 pdpindex = ptepindex - NUPDE;
2514 pml4index = pdpindex >> NPML4EPGSHIFT;
2516 pml4 = &pmap->pm_pml4[pml4index];
2517 if ((*pml4 & PG_V) == 0) {
2518 /* Have to allocate a new pdp, recurse */
2519 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2522 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2523 vm_page_free_zero(m);
2527 /* Add reference to pdp page */
2528 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2529 pdppg->wire_count++;
2531 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2533 /* Now find the pdp page */
2534 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2535 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2538 vm_pindex_t pml4index;
2539 vm_pindex_t pdpindex;
2544 /* Wire up a new PTE page */
2545 pdpindex = ptepindex >> NPDPEPGSHIFT;
2546 pml4index = pdpindex >> NPML4EPGSHIFT;
2548 /* First, find the pdp and check that its valid. */
2549 pml4 = &pmap->pm_pml4[pml4index];
2550 if ((*pml4 & PG_V) == 0) {
2551 /* Have to allocate a new pd, recurse */
2552 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2555 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2556 vm_page_free_zero(m);
2559 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2560 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2562 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2563 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2564 if ((*pdp & PG_V) == 0) {
2565 /* Have to allocate a new pd, recurse */
2566 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2569 atomic_subtract_int(&vm_cnt.v_wire_count,
2571 vm_page_free_zero(m);
2575 /* Add reference to the pd page */
2576 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2580 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2582 /* Now we know where the page directory page is */
2583 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2584 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2587 pmap_resident_count_inc(pmap, 1);
2593 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2595 vm_pindex_t pdpindex, ptepindex;
2596 pdp_entry_t *pdpe, PG_V;
2599 PG_V = pmap_valid_bit(pmap);
2602 pdpe = pmap_pdpe(pmap, va);
2603 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2604 /* Add a reference to the pd page. */
2605 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2608 /* Allocate a pd page. */
2609 ptepindex = pmap_pde_pindex(va);
2610 pdpindex = ptepindex >> NPDPEPGSHIFT;
2611 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2612 if (pdpg == NULL && lockp != NULL)
2619 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2621 vm_pindex_t ptepindex;
2622 pd_entry_t *pd, PG_V;
2625 PG_V = pmap_valid_bit(pmap);
2628 * Calculate pagetable page index
2630 ptepindex = pmap_pde_pindex(va);
2633 * Get the page directory entry
2635 pd = pmap_pde(pmap, va);
2638 * This supports switching from a 2MB page to a
2641 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2642 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2644 * Invalidation of the 2MB page mapping may have caused
2645 * the deallocation of the underlying PD page.
2652 * If the page table page is mapped, we just increment the
2653 * hold count, and activate it.
2655 if (pd != NULL && (*pd & PG_V) != 0) {
2656 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2660 * Here if the pte page isn't mapped, or if it has been
2663 m = _pmap_allocpte(pmap, ptepindex, lockp);
2664 if (m == NULL && lockp != NULL)
2671 /***************************************************
2672 * Pmap allocation/deallocation routines.
2673 ***************************************************/
2676 * Release any resources held by the given physical map.
2677 * Called when a pmap initialized by pmap_pinit is being released.
2678 * Should only be called if the map contains no valid mappings.
2681 pmap_release(pmap_t pmap)
2686 KASSERT(pmap->pm_stats.resident_count == 0,
2687 ("pmap_release: pmap resident count %ld != 0",
2688 pmap->pm_stats.resident_count));
2689 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2690 ("pmap_release: pmap has reserved page table page(s)"));
2691 KASSERT(CPU_EMPTY(&pmap->pm_active),
2692 ("releasing active pmap %p", pmap));
2694 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2696 for (i = 0; i < NKPML4E; i++) /* KVA */
2697 pmap->pm_pml4[KPML4BASE + i] = 0;
2698 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2699 pmap->pm_pml4[DMPML4I + i] = 0;
2700 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2703 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2704 vm_page_free_zero(m);
2708 kvm_size(SYSCTL_HANDLER_ARGS)
2710 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2712 return sysctl_handle_long(oidp, &ksize, 0, req);
2714 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2715 0, 0, kvm_size, "LU", "Size of KVM");
2718 kvm_free(SYSCTL_HANDLER_ARGS)
2720 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2722 return sysctl_handle_long(oidp, &kfree, 0, req);
2724 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2725 0, 0, kvm_free, "LU", "Amount of KVM free");
2728 * grow the number of kernel page table entries, if needed
2731 pmap_growkernel(vm_offset_t addr)
2735 pd_entry_t *pde, newpdir;
2738 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2741 * Return if "addr" is within the range of kernel page table pages
2742 * that were preallocated during pmap bootstrap. Moreover, leave
2743 * "kernel_vm_end" and the kernel page table as they were.
2745 * The correctness of this action is based on the following
2746 * argument: vm_map_insert() allocates contiguous ranges of the
2747 * kernel virtual address space. It calls this function if a range
2748 * ends after "kernel_vm_end". If the kernel is mapped between
2749 * "kernel_vm_end" and "addr", then the range cannot begin at
2750 * "kernel_vm_end". In fact, its beginning address cannot be less
2751 * than the kernel. Thus, there is no immediate need to allocate
2752 * any new kernel page table pages between "kernel_vm_end" and
2755 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2758 addr = roundup2(addr, NBPDR);
2759 if (addr - 1 >= kernel_map->max_offset)
2760 addr = kernel_map->max_offset;
2761 while (kernel_vm_end < addr) {
2762 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2763 if ((*pdpe & X86_PG_V) == 0) {
2764 /* We need a new PDP entry */
2765 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2766 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2767 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2769 panic("pmap_growkernel: no memory to grow kernel");
2770 if ((nkpg->flags & PG_ZERO) == 0)
2771 pmap_zero_page(nkpg);
2772 paddr = VM_PAGE_TO_PHYS(nkpg);
2773 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2774 X86_PG_A | X86_PG_M);
2775 continue; /* try again */
2777 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2778 if ((*pde & X86_PG_V) != 0) {
2779 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2780 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2781 kernel_vm_end = kernel_map->max_offset;
2787 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2788 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2791 panic("pmap_growkernel: no memory to grow kernel");
2792 if ((nkpg->flags & PG_ZERO) == 0)
2793 pmap_zero_page(nkpg);
2794 paddr = VM_PAGE_TO_PHYS(nkpg);
2795 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2796 pde_store(pde, newpdir);
2798 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2799 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2800 kernel_vm_end = kernel_map->max_offset;
2807 /***************************************************
2808 * page management routines.
2809 ***************************************************/
2811 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2812 CTASSERT(_NPCM == 3);
2813 CTASSERT(_NPCPV == 168);
2815 static __inline struct pv_chunk *
2816 pv_to_chunk(pv_entry_t pv)
2819 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2822 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2824 #define PC_FREE0 0xfffffffffffffffful
2825 #define PC_FREE1 0xfffffffffffffffful
2826 #define PC_FREE2 0x000000fffffffffful
2828 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2831 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2833 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2834 "Current number of pv entry chunks");
2835 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2836 "Current number of pv entry chunks allocated");
2837 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2838 "Current number of pv entry chunks frees");
2839 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2840 "Number of times tried to get a chunk page but failed.");
2842 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2843 static int pv_entry_spare;
2845 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2846 "Current number of pv entry frees");
2847 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2848 "Current number of pv entry allocs");
2849 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2850 "Current number of pv entries");
2851 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2852 "Current number of spare pv entries");
2856 * We are in a serious low memory condition. Resort to
2857 * drastic measures to free some pages so we can allocate
2858 * another pv entry chunk.
2860 * Returns NULL if PV entries were reclaimed from the specified pmap.
2862 * We do not, however, unmap 2mpages because subsequent accesses will
2863 * allocate per-page pv entries until repromotion occurs, thereby
2864 * exacerbating the shortage of free pv entries.
2867 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2869 struct pch new_tail;
2870 struct pv_chunk *pc;
2871 struct md_page *pvh;
2874 pt_entry_t *pte, tpte;
2875 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2879 struct spglist free;
2881 int bit, field, freed;
2883 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2884 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2887 PG_G = PG_A = PG_M = PG_RW = 0;
2889 TAILQ_INIT(&new_tail);
2890 pmap_delayed_invl_started();
2891 mtx_lock(&pv_chunks_mutex);
2892 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2893 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2894 mtx_unlock(&pv_chunks_mutex);
2895 if (pmap != pc->pc_pmap) {
2897 pmap_invalidate_all(pmap);
2898 if (pmap != locked_pmap)
2901 pmap_delayed_invl_finished();
2902 pmap_delayed_invl_started();
2904 /* Avoid deadlock and lock recursion. */
2905 if (pmap > locked_pmap) {
2906 RELEASE_PV_LIST_LOCK(lockp);
2908 } else if (pmap != locked_pmap &&
2909 !PMAP_TRYLOCK(pmap)) {
2911 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2912 mtx_lock(&pv_chunks_mutex);
2915 PG_G = pmap_global_bit(pmap);
2916 PG_A = pmap_accessed_bit(pmap);
2917 PG_M = pmap_modified_bit(pmap);
2918 PG_RW = pmap_rw_bit(pmap);
2922 * Destroy every non-wired, 4 KB page mapping in the chunk.
2925 for (field = 0; field < _NPCM; field++) {
2926 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2927 inuse != 0; inuse &= ~(1UL << bit)) {
2929 pv = &pc->pc_pventry[field * 64 + bit];
2931 pde = pmap_pde(pmap, va);
2932 if ((*pde & PG_PS) != 0)
2934 pte = pmap_pde_to_pte(pde, va);
2935 if ((*pte & PG_W) != 0)
2937 tpte = pte_load_clear(pte);
2938 if ((tpte & PG_G) != 0)
2939 pmap_invalidate_page(pmap, va);
2940 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2941 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2943 if ((tpte & PG_A) != 0)
2944 vm_page_aflag_set(m, PGA_REFERENCED);
2945 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2946 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2948 if (TAILQ_EMPTY(&m->md.pv_list) &&
2949 (m->flags & PG_FICTITIOUS) == 0) {
2950 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2951 if (TAILQ_EMPTY(&pvh->pv_list)) {
2952 vm_page_aflag_clear(m,
2956 pmap_delayed_invl_page(m);
2957 pc->pc_map[field] |= 1UL << bit;
2958 pmap_unuse_pt(pmap, va, *pde, &free);
2963 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2964 mtx_lock(&pv_chunks_mutex);
2967 /* Every freed mapping is for a 4 KB page. */
2968 pmap_resident_count_dec(pmap, freed);
2969 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2970 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2971 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2972 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2973 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2974 pc->pc_map[2] == PC_FREE2) {
2975 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2976 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2977 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2978 /* Entire chunk is free; return it. */
2979 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2980 dump_drop_page(m_pc->phys_addr);
2981 mtx_lock(&pv_chunks_mutex);
2984 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2985 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2986 mtx_lock(&pv_chunks_mutex);
2987 /* One freed pv entry in locked_pmap is sufficient. */
2988 if (pmap == locked_pmap)
2991 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2992 mtx_unlock(&pv_chunks_mutex);
2994 pmap_invalidate_all(pmap);
2995 if (pmap != locked_pmap)
2998 pmap_delayed_invl_finished();
2999 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3000 m_pc = SLIST_FIRST(&free);
3001 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3002 /* Recycle a freed page table page. */
3003 m_pc->wire_count = 1;
3004 atomic_add_int(&vm_cnt.v_wire_count, 1);
3006 pmap_free_zero_pages(&free);
3011 * free the pv_entry back to the free list
3014 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3016 struct pv_chunk *pc;
3017 int idx, field, bit;
3019 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3020 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3021 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3022 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3023 pc = pv_to_chunk(pv);
3024 idx = pv - &pc->pc_pventry[0];
3027 pc->pc_map[field] |= 1ul << bit;
3028 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3029 pc->pc_map[2] != PC_FREE2) {
3030 /* 98% of the time, pc is already at the head of the list. */
3031 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3032 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3033 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3037 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3042 free_pv_chunk(struct pv_chunk *pc)
3046 mtx_lock(&pv_chunks_mutex);
3047 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3048 mtx_unlock(&pv_chunks_mutex);
3049 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3050 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3051 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3052 /* entire chunk is free, return it */
3053 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3054 dump_drop_page(m->phys_addr);
3055 vm_page_unwire(m, PQ_NONE);
3060 * Returns a new PV entry, allocating a new PV chunk from the system when
3061 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3062 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3065 * The given PV list lock may be released.
3068 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3072 struct pv_chunk *pc;
3075 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3076 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3078 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3080 for (field = 0; field < _NPCM; field++) {
3081 if (pc->pc_map[field]) {
3082 bit = bsfq(pc->pc_map[field]);
3086 if (field < _NPCM) {
3087 pv = &pc->pc_pventry[field * 64 + bit];
3088 pc->pc_map[field] &= ~(1ul << bit);
3089 /* If this was the last item, move it to tail */
3090 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3091 pc->pc_map[2] == 0) {
3092 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3093 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3096 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3097 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3101 /* No free items, allocate another chunk */
3102 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3105 if (lockp == NULL) {
3106 PV_STAT(pc_chunk_tryfail++);
3109 m = reclaim_pv_chunk(pmap, lockp);
3113 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3114 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3115 dump_add_page(m->phys_addr);
3116 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3118 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3119 pc->pc_map[1] = PC_FREE1;
3120 pc->pc_map[2] = PC_FREE2;
3121 mtx_lock(&pv_chunks_mutex);
3122 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3123 mtx_unlock(&pv_chunks_mutex);
3124 pv = &pc->pc_pventry[0];
3125 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3126 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3127 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3132 * Returns the number of one bits within the given PV chunk map.
3134 * The erratas for Intel processors state that "POPCNT Instruction May
3135 * Take Longer to Execute Than Expected". It is believed that the
3136 * issue is the spurious dependency on the destination register.
3137 * Provide a hint to the register rename logic that the destination
3138 * value is overwritten, by clearing it, as suggested in the
3139 * optimization manual. It should be cheap for unaffected processors
3142 * Reference numbers for erratas are
3143 * 4th Gen Core: HSD146
3144 * 5th Gen Core: BDM85
3145 * 6th Gen Core: SKL029
3148 popcnt_pc_map_pq(uint64_t *map)
3152 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3153 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3154 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3155 : "=&r" (result), "=&r" (tmp)
3156 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3161 * Ensure that the number of spare PV entries in the specified pmap meets or
3162 * exceeds the given count, "needed".
3164 * The given PV list lock may be released.
3167 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3169 struct pch new_tail;
3170 struct pv_chunk *pc;
3174 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3175 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3178 * Newly allocated PV chunks must be stored in a private list until
3179 * the required number of PV chunks have been allocated. Otherwise,
3180 * reclaim_pv_chunk() could recycle one of these chunks. In
3181 * contrast, these chunks must be added to the pmap upon allocation.
3183 TAILQ_INIT(&new_tail);
3186 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3188 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3189 bit_count((bitstr_t *)pc->pc_map, 0,
3190 sizeof(pc->pc_map) * NBBY, &free);
3193 free = popcnt_pc_map_pq(pc->pc_map);
3197 if (avail >= needed)
3200 for (; avail < needed; avail += _NPCPV) {
3201 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3204 m = reclaim_pv_chunk(pmap, lockp);
3208 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3209 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3210 dump_add_page(m->phys_addr);
3211 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3213 pc->pc_map[0] = PC_FREE0;
3214 pc->pc_map[1] = PC_FREE1;
3215 pc->pc_map[2] = PC_FREE2;
3216 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3217 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3218 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3220 if (!TAILQ_EMPTY(&new_tail)) {
3221 mtx_lock(&pv_chunks_mutex);
3222 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3223 mtx_unlock(&pv_chunks_mutex);
3228 * First find and then remove the pv entry for the specified pmap and virtual
3229 * address from the specified pv list. Returns the pv entry if found and NULL
3230 * otherwise. This operation can be performed on pv lists for either 4KB or
3231 * 2MB page mappings.
3233 static __inline pv_entry_t
3234 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3238 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3239 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3240 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3249 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3250 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3251 * entries for each of the 4KB page mappings.
3254 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3255 struct rwlock **lockp)
3257 struct md_page *pvh;
3258 struct pv_chunk *pc;
3260 vm_offset_t va_last;
3264 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3265 KASSERT((pa & PDRMASK) == 0,
3266 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3267 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3270 * Transfer the 2mpage's pv entry for this mapping to the first
3271 * page's pv list. Once this transfer begins, the pv list lock
3272 * must not be released until the last pv entry is reinstantiated.
3274 pvh = pa_to_pvh(pa);
3275 va = trunc_2mpage(va);
3276 pv = pmap_pvh_remove(pvh, pmap, va);
3277 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3278 m = PHYS_TO_VM_PAGE(pa);
3279 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3281 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3282 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3283 va_last = va + NBPDR - PAGE_SIZE;
3285 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3286 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3287 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3288 for (field = 0; field < _NPCM; field++) {
3289 while (pc->pc_map[field]) {
3290 bit = bsfq(pc->pc_map[field]);
3291 pc->pc_map[field] &= ~(1ul << bit);
3292 pv = &pc->pc_pventry[field * 64 + bit];
3296 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3297 ("pmap_pv_demote_pde: page %p is not managed", m));
3298 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3304 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3305 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3308 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3309 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3310 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3312 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3313 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3317 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3318 * replace the many pv entries for the 4KB page mappings by a single pv entry
3319 * for the 2MB page mapping.
3322 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3323 struct rwlock **lockp)
3325 struct md_page *pvh;
3327 vm_offset_t va_last;
3330 KASSERT((pa & PDRMASK) == 0,
3331 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3332 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3335 * Transfer the first page's pv entry for this mapping to the 2mpage's
3336 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3337 * a transfer avoids the possibility that get_pv_entry() calls
3338 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3339 * mappings that is being promoted.
3341 m = PHYS_TO_VM_PAGE(pa);
3342 va = trunc_2mpage(va);
3343 pv = pmap_pvh_remove(&m->md, pmap, va);
3344 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3345 pvh = pa_to_pvh(pa);
3346 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3348 /* Free the remaining NPTEPG - 1 pv entries. */
3349 va_last = va + NBPDR - PAGE_SIZE;
3353 pmap_pvh_free(&m->md, pmap, va);
3354 } while (va < va_last);
3358 * First find and then destroy the pv entry for the specified pmap and virtual
3359 * address. This operation can be performed on pv lists for either 4KB or 2MB
3363 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3367 pv = pmap_pvh_remove(pvh, pmap, va);
3368 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3369 free_pv_entry(pmap, pv);
3373 * Conditionally create the PV entry for a 4KB page mapping if the required
3374 * memory can be allocated without resorting to reclamation.
3377 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3378 struct rwlock **lockp)
3382 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3383 /* Pass NULL instead of the lock pointer to disable reclamation. */
3384 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3386 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3387 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3395 * Conditionally create the PV entry for a 2MB page mapping if the required
3396 * memory can be allocated without resorting to reclamation.
3399 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3400 struct rwlock **lockp)
3402 struct md_page *pvh;
3405 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3406 /* Pass NULL instead of the lock pointer to disable reclamation. */
3407 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3409 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3410 pvh = pa_to_pvh(pa);
3411 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3419 * Fills a page table page with mappings to consecutive physical pages.
3422 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3426 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3428 newpte += PAGE_SIZE;
3433 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3434 * mapping is invalidated.
3437 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3439 struct rwlock *lock;
3443 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3450 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3451 struct rwlock **lockp)
3453 pd_entry_t newpde, oldpde;
3454 pt_entry_t *firstpte, newpte;
3455 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3458 struct spglist free;
3462 PG_G = pmap_global_bit(pmap);
3463 PG_A = pmap_accessed_bit(pmap);
3464 PG_M = pmap_modified_bit(pmap);
3465 PG_RW = pmap_rw_bit(pmap);
3466 PG_V = pmap_valid_bit(pmap);
3467 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3469 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3471 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3472 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3473 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
3475 KASSERT((oldpde & PG_W) == 0,
3476 ("pmap_demote_pde: page table page for a wired mapping"
3480 * Invalidate the 2MB page mapping and return "failure" if the
3481 * mapping was never accessed or the allocation of the new
3482 * page table page fails. If the 2MB page mapping belongs to
3483 * the direct map region of the kernel's address space, then
3484 * the page allocation request specifies the highest possible
3485 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3486 * normal. Page table pages are preallocated for every other
3487 * part of the kernel address space, so the direct map region
3488 * is the only part of the kernel address space that must be
3491 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3492 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3493 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3494 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3496 sva = trunc_2mpage(va);
3497 pmap_remove_pde(pmap, pde, sva, &free, lockp);
3498 if ((oldpde & PG_G) == 0)
3499 pmap_invalidate_pde_page(pmap, sva, oldpde);
3500 pmap_free_zero_pages(&free);
3501 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3502 " in pmap %p", va, pmap);
3505 if (va < VM_MAXUSER_ADDRESS)
3506 pmap_resident_count_inc(pmap, 1);
3508 mptepa = VM_PAGE_TO_PHYS(mpte);
3509 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3510 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3511 KASSERT((oldpde & PG_A) != 0,
3512 ("pmap_demote_pde: oldpde is missing PG_A"));
3513 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3514 ("pmap_demote_pde: oldpde is missing PG_M"));
3515 newpte = oldpde & ~PG_PS;
3516 newpte = pmap_swap_pat(pmap, newpte);
3519 * If the page table page is new, initialize it.
3521 if (mpte->wire_count == 1) {
3522 mpte->wire_count = NPTEPG;
3523 pmap_fill_ptp(firstpte, newpte);
3525 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3526 ("pmap_demote_pde: firstpte and newpte map different physical"
3530 * If the mapping has changed attributes, update the page table
3533 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3534 pmap_fill_ptp(firstpte, newpte);
3537 * The spare PV entries must be reserved prior to demoting the
3538 * mapping, that is, prior to changing the PDE. Otherwise, the state
3539 * of the PDE and the PV lists will be inconsistent, which can result
3540 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3541 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3542 * PV entry for the 2MB page mapping that is being demoted.
3544 if ((oldpde & PG_MANAGED) != 0)
3545 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3548 * Demote the mapping. This pmap is locked. The old PDE has
3549 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3550 * set. Thus, there is no danger of a race with another
3551 * processor changing the setting of PG_A and/or PG_M between
3552 * the read above and the store below.
3554 if (workaround_erratum383)
3555 pmap_update_pde(pmap, va, pde, newpde);
3557 pde_store(pde, newpde);
3560 * Invalidate a stale recursive mapping of the page table page.
3562 if (va >= VM_MAXUSER_ADDRESS)
3563 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3566 * Demote the PV entry.
3568 if ((oldpde & PG_MANAGED) != 0)
3569 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3571 atomic_add_long(&pmap_pde_demotions, 1);
3572 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3573 " in pmap %p", va, pmap);
3578 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3581 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3587 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3588 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3589 mpte = pmap_remove_pt_page(pmap, va);
3591 panic("pmap_remove_kernel_pde: Missing pt page.");
3593 mptepa = VM_PAGE_TO_PHYS(mpte);
3594 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3597 * Initialize the page table page.
3599 pagezero((void *)PHYS_TO_DMAP(mptepa));
3602 * Demote the mapping.
3604 if (workaround_erratum383)
3605 pmap_update_pde(pmap, va, pde, newpde);
3607 pde_store(pde, newpde);
3610 * Invalidate a stale recursive mapping of the page table page.
3612 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3616 * pmap_remove_pde: do the things to unmap a superpage in a process
3619 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3620 struct spglist *free, struct rwlock **lockp)
3622 struct md_page *pvh;
3624 vm_offset_t eva, va;
3626 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3628 PG_G = pmap_global_bit(pmap);
3629 PG_A = pmap_accessed_bit(pmap);
3630 PG_M = pmap_modified_bit(pmap);
3631 PG_RW = pmap_rw_bit(pmap);
3633 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3634 KASSERT((sva & PDRMASK) == 0,
3635 ("pmap_remove_pde: sva is not 2mpage aligned"));
3636 oldpde = pte_load_clear(pdq);
3638 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3639 if ((oldpde & PG_G) != 0)
3640 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3641 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3642 if (oldpde & PG_MANAGED) {
3643 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3644 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3645 pmap_pvh_free(pvh, pmap, sva);
3647 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3648 va < eva; va += PAGE_SIZE, m++) {
3649 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3652 vm_page_aflag_set(m, PGA_REFERENCED);
3653 if (TAILQ_EMPTY(&m->md.pv_list) &&
3654 TAILQ_EMPTY(&pvh->pv_list))
3655 vm_page_aflag_clear(m, PGA_WRITEABLE);
3656 pmap_delayed_invl_page(m);
3659 if (pmap == kernel_pmap) {
3660 pmap_remove_kernel_pde(pmap, pdq, sva);
3662 mpte = pmap_remove_pt_page(pmap, sva);
3664 pmap_resident_count_dec(pmap, 1);
3665 KASSERT(mpte->wire_count == NPTEPG,
3666 ("pmap_remove_pde: pte page wire count error"));
3667 mpte->wire_count = 0;
3668 pmap_add_delayed_free_list(mpte, free, FALSE);
3669 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
3672 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3676 * pmap_remove_pte: do the things to unmap a page in a process
3679 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3680 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3682 struct md_page *pvh;
3683 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3686 PG_A = pmap_accessed_bit(pmap);
3687 PG_M = pmap_modified_bit(pmap);
3688 PG_RW = pmap_rw_bit(pmap);
3690 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3691 oldpte = pte_load_clear(ptq);
3693 pmap->pm_stats.wired_count -= 1;
3694 pmap_resident_count_dec(pmap, 1);
3695 if (oldpte & PG_MANAGED) {
3696 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3697 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3700 vm_page_aflag_set(m, PGA_REFERENCED);
3701 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3702 pmap_pvh_free(&m->md, pmap, va);
3703 if (TAILQ_EMPTY(&m->md.pv_list) &&
3704 (m->flags & PG_FICTITIOUS) == 0) {
3705 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3706 if (TAILQ_EMPTY(&pvh->pv_list))
3707 vm_page_aflag_clear(m, PGA_WRITEABLE);
3709 pmap_delayed_invl_page(m);
3711 return (pmap_unuse_pt(pmap, va, ptepde, free));
3715 * Remove a single page from a process address space
3718 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3719 struct spglist *free)
3721 struct rwlock *lock;
3722 pt_entry_t *pte, PG_V;
3724 PG_V = pmap_valid_bit(pmap);
3725 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3726 if ((*pde & PG_V) == 0)
3728 pte = pmap_pde_to_pte(pde, va);
3729 if ((*pte & PG_V) == 0)
3732 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3735 pmap_invalidate_page(pmap, va);
3739 * Remove the given range of addresses from the specified map.
3741 * It is assumed that the start and end are properly
3742 * rounded to the page size.
3745 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3747 struct rwlock *lock;
3748 vm_offset_t va, va_next;
3749 pml4_entry_t *pml4e;
3751 pd_entry_t ptpaddr, *pde;
3752 pt_entry_t *pte, PG_G, PG_V;
3753 struct spglist free;
3756 PG_G = pmap_global_bit(pmap);
3757 PG_V = pmap_valid_bit(pmap);
3760 * Perform an unsynchronized read. This is, however, safe.
3762 if (pmap->pm_stats.resident_count == 0)
3768 pmap_delayed_invl_started();
3772 * special handling of removing one page. a very
3773 * common operation and easy to short circuit some
3776 if (sva + PAGE_SIZE == eva) {
3777 pde = pmap_pde(pmap, sva);
3778 if (pde && (*pde & PG_PS) == 0) {
3779 pmap_remove_page(pmap, sva, pde, &free);
3785 for (; sva < eva; sva = va_next) {
3787 if (pmap->pm_stats.resident_count == 0)
3790 pml4e = pmap_pml4e(pmap, sva);
3791 if ((*pml4e & PG_V) == 0) {
3792 va_next = (sva + NBPML4) & ~PML4MASK;
3798 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3799 if ((*pdpe & PG_V) == 0) {
3800 va_next = (sva + NBPDP) & ~PDPMASK;
3807 * Calculate index for next page table.
3809 va_next = (sva + NBPDR) & ~PDRMASK;
3813 pde = pmap_pdpe_to_pde(pdpe, sva);
3817 * Weed out invalid mappings.
3823 * Check for large page.
3825 if ((ptpaddr & PG_PS) != 0) {
3827 * Are we removing the entire large page? If not,
3828 * demote the mapping and fall through.
3830 if (sva + NBPDR == va_next && eva >= va_next) {
3832 * The TLB entry for a PG_G mapping is
3833 * invalidated by pmap_remove_pde().
3835 if ((ptpaddr & PG_G) == 0)
3837 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3839 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3841 /* The large page mapping was destroyed. */
3848 * Limit our scan to either the end of the va represented
3849 * by the current page table page, or to the end of the
3850 * range being removed.
3856 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3859 if (va != va_next) {
3860 pmap_invalidate_range(pmap, va, sva);
3865 if ((*pte & PG_G) == 0)
3867 else if (va == va_next)
3869 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3876 pmap_invalidate_range(pmap, va, sva);
3882 pmap_invalidate_all(pmap);
3884 pmap_delayed_invl_finished();
3885 pmap_free_zero_pages(&free);
3889 * Routine: pmap_remove_all
3891 * Removes this physical page from
3892 * all physical maps in which it resides.
3893 * Reflects back modify bits to the pager.
3896 * Original versions of this routine were very
3897 * inefficient because they iteratively called
3898 * pmap_remove (slow...)
3902 pmap_remove_all(vm_page_t m)
3904 struct md_page *pvh;
3907 struct rwlock *lock;
3908 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3911 struct spglist free;
3912 int pvh_gen, md_gen;
3914 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3915 ("pmap_remove_all: page %p is not managed", m));
3917 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3918 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3919 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3922 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3924 if (!PMAP_TRYLOCK(pmap)) {
3925 pvh_gen = pvh->pv_gen;
3929 if (pvh_gen != pvh->pv_gen) {
3936 pde = pmap_pde(pmap, va);
3937 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
3940 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3942 if (!PMAP_TRYLOCK(pmap)) {
3943 pvh_gen = pvh->pv_gen;
3944 md_gen = m->md.pv_gen;
3948 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3954 PG_A = pmap_accessed_bit(pmap);
3955 PG_M = pmap_modified_bit(pmap);
3956 PG_RW = pmap_rw_bit(pmap);
3957 pmap_resident_count_dec(pmap, 1);
3958 pde = pmap_pde(pmap, pv->pv_va);
3959 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3960 " a 2mpage in page %p's pv list", m));
3961 pte = pmap_pde_to_pte(pde, pv->pv_va);
3962 tpte = pte_load_clear(pte);
3964 pmap->pm_stats.wired_count--;
3966 vm_page_aflag_set(m, PGA_REFERENCED);
3969 * Update the vm_page_t clean and reference bits.
3971 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3973 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3974 pmap_invalidate_page(pmap, pv->pv_va);
3975 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3977 free_pv_entry(pmap, pv);
3980 vm_page_aflag_clear(m, PGA_WRITEABLE);
3982 pmap_delayed_invl_wait(m);
3983 pmap_free_zero_pages(&free);
3987 * pmap_protect_pde: do the things to protect a 2mpage in a process
3990 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3992 pd_entry_t newpde, oldpde;
3993 vm_offset_t eva, va;
3995 boolean_t anychanged;
3996 pt_entry_t PG_G, PG_M, PG_RW;
3998 PG_G = pmap_global_bit(pmap);
3999 PG_M = pmap_modified_bit(pmap);
4000 PG_RW = pmap_rw_bit(pmap);
4002 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4003 KASSERT((sva & PDRMASK) == 0,
4004 ("pmap_protect_pde: sva is not 2mpage aligned"));
4007 oldpde = newpde = *pde;
4008 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4009 (PG_MANAGED | PG_M | PG_RW)) {
4011 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4012 va < eva; va += PAGE_SIZE, m++)
4015 if ((prot & VM_PROT_WRITE) == 0)
4016 newpde &= ~(PG_RW | PG_M);
4017 if ((prot & VM_PROT_EXECUTE) == 0)
4019 if (newpde != oldpde) {
4021 * As an optimization to future operations on this PDE, clear
4022 * PG_PROMOTED. The impending invalidation will remove any
4023 * lingering 4KB page mappings from the TLB.
4025 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4027 if ((oldpde & PG_G) != 0)
4028 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4032 return (anychanged);
4036 * Set the physical protection on the
4037 * specified range of this map as requested.
4040 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4042 vm_offset_t va_next;
4043 pml4_entry_t *pml4e;
4045 pd_entry_t ptpaddr, *pde;
4046 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4047 boolean_t anychanged;
4049 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4050 if (prot == VM_PROT_NONE) {
4051 pmap_remove(pmap, sva, eva);
4055 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4056 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4059 PG_G = pmap_global_bit(pmap);
4060 PG_M = pmap_modified_bit(pmap);
4061 PG_V = pmap_valid_bit(pmap);
4062 PG_RW = pmap_rw_bit(pmap);
4066 for (; sva < eva; sva = va_next) {
4068 pml4e = pmap_pml4e(pmap, sva);
4069 if ((*pml4e & PG_V) == 0) {
4070 va_next = (sva + NBPML4) & ~PML4MASK;
4076 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4077 if ((*pdpe & PG_V) == 0) {
4078 va_next = (sva + NBPDP) & ~PDPMASK;
4084 va_next = (sva + NBPDR) & ~PDRMASK;
4088 pde = pmap_pdpe_to_pde(pdpe, sva);
4092 * Weed out invalid mappings.
4098 * Check for large page.
4100 if ((ptpaddr & PG_PS) != 0) {
4102 * Are we protecting the entire large page? If not,
4103 * demote the mapping and fall through.
4105 if (sva + NBPDR == va_next && eva >= va_next) {
4107 * The TLB entry for a PG_G mapping is
4108 * invalidated by pmap_protect_pde().
4110 if (pmap_protect_pde(pmap, pde, sva, prot))
4113 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4115 * The large page mapping was destroyed.
4124 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4126 pt_entry_t obits, pbits;
4130 obits = pbits = *pte;
4131 if ((pbits & PG_V) == 0)
4134 if ((prot & VM_PROT_WRITE) == 0) {
4135 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4136 (PG_MANAGED | PG_M | PG_RW)) {
4137 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4140 pbits &= ~(PG_RW | PG_M);
4142 if ((prot & VM_PROT_EXECUTE) == 0)
4145 if (pbits != obits) {
4146 if (!atomic_cmpset_long(pte, obits, pbits))
4149 pmap_invalidate_page(pmap, sva);
4156 pmap_invalidate_all(pmap);
4161 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4162 * single page table page (PTP) to a single 2MB page mapping. For promotion
4163 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4164 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4165 * identical characteristics.
4168 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4169 struct rwlock **lockp)
4172 pt_entry_t *firstpte, oldpte, pa, *pte;
4173 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4177 PG_A = pmap_accessed_bit(pmap);
4178 PG_G = pmap_global_bit(pmap);
4179 PG_M = pmap_modified_bit(pmap);
4180 PG_V = pmap_valid_bit(pmap);
4181 PG_RW = pmap_rw_bit(pmap);
4182 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4184 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4187 * Examine the first PTE in the specified PTP. Abort if this PTE is
4188 * either invalid, unused, or does not map the first 4KB physical page
4189 * within a 2MB page.
4191 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4194 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4195 atomic_add_long(&pmap_pde_p_failures, 1);
4196 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4197 " in pmap %p", va, pmap);
4200 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4202 * When PG_M is already clear, PG_RW can be cleared without
4203 * a TLB invalidation.
4205 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4211 * Examine each of the other PTEs in the specified PTP. Abort if this
4212 * PTE maps an unexpected 4KB physical page or does not have identical
4213 * characteristics to the first PTE.
4215 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4216 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4219 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4220 atomic_add_long(&pmap_pde_p_failures, 1);
4221 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4222 " in pmap %p", va, pmap);
4225 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4227 * When PG_M is already clear, PG_RW can be cleared
4228 * without a TLB invalidation.
4230 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4233 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4234 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4235 (va & ~PDRMASK), pmap);
4237 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4238 atomic_add_long(&pmap_pde_p_failures, 1);
4239 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4240 " in pmap %p", va, pmap);
4247 * Save the page table page in its current state until the PDE
4248 * mapping the superpage is demoted by pmap_demote_pde() or
4249 * destroyed by pmap_remove_pde().
4251 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4252 KASSERT(mpte >= vm_page_array &&
4253 mpte < &vm_page_array[vm_page_array_size],
4254 ("pmap_promote_pde: page table page is out of range"));
4255 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4256 ("pmap_promote_pde: page table page's pindex is wrong"));
4257 if (pmap_insert_pt_page(pmap, mpte)) {
4258 atomic_add_long(&pmap_pde_p_failures, 1);
4260 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4266 * Promote the pv entries.
4268 if ((newpde & PG_MANAGED) != 0)
4269 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4272 * Propagate the PAT index to its proper position.
4274 newpde = pmap_swap_pat(pmap, newpde);
4277 * Map the superpage.
4279 if (workaround_erratum383)
4280 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4282 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4284 atomic_add_long(&pmap_pde_promotions, 1);
4285 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4286 " in pmap %p", va, pmap);
4290 * Insert the given physical page (p) at
4291 * the specified virtual address (v) in the
4292 * target physical map with the protection requested.
4294 * If specified, the page will be wired down, meaning
4295 * that the related pte can not be reclaimed.
4297 * NB: This is the only routine which MAY NOT lazy-evaluate
4298 * or lose information. That is, this routine must actually
4299 * insert this page into the given map NOW.
4301 * When destroying both a page table and PV entry, this function
4302 * performs the TLB invalidation before releasing the PV list
4303 * lock, so we do not need pmap_delayed_invl_page() calls here.
4306 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4307 u_int flags, int8_t psind __unused)
4309 struct rwlock *lock;
4311 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4312 pt_entry_t newpte, origpte;
4318 PG_A = pmap_accessed_bit(pmap);
4319 PG_G = pmap_global_bit(pmap);
4320 PG_M = pmap_modified_bit(pmap);
4321 PG_V = pmap_valid_bit(pmap);
4322 PG_RW = pmap_rw_bit(pmap);
4324 va = trunc_page(va);
4325 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4326 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4327 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4329 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4330 va >= kmi.clean_eva,
4331 ("pmap_enter: managed mapping within the clean submap"));
4332 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4333 VM_OBJECT_ASSERT_LOCKED(m->object);
4334 pa = VM_PAGE_TO_PHYS(m);
4335 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4336 if ((flags & VM_PROT_WRITE) != 0)
4338 if ((prot & VM_PROT_WRITE) != 0)
4340 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4341 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4342 if ((prot & VM_PROT_EXECUTE) == 0)
4344 if ((flags & PMAP_ENTER_WIRED) != 0)
4346 if (va < VM_MAXUSER_ADDRESS)
4348 if (pmap == kernel_pmap)
4350 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4353 * Set modified bit gratuitously for writeable mappings if
4354 * the page is unmanaged. We do not want to take a fault
4355 * to do the dirty bit accounting for these mappings.
4357 if ((m->oflags & VPO_UNMANAGED) != 0) {
4358 if ((newpte & PG_RW) != 0)
4361 newpte |= PG_MANAGED;
4369 * In the case that a page table page is not
4370 * resident, we are creating it here.
4373 pde = pmap_pde(pmap, va);
4374 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4375 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4376 pte = pmap_pde_to_pte(pde, va);
4377 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4378 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4381 } else if (va < VM_MAXUSER_ADDRESS) {
4383 * Here if the pte page isn't mapped, or if it has been
4386 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4387 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4388 nosleep ? NULL : &lock);
4389 if (mpte == NULL && nosleep) {
4393 return (KERN_RESOURCE_SHORTAGE);
4397 panic("pmap_enter: invalid page directory va=%#lx", va);
4402 * Is the specified virtual address already mapped?
4404 if ((origpte & PG_V) != 0) {
4406 * Wiring change, just update stats. We don't worry about
4407 * wiring PT pages as they remain resident as long as there
4408 * are valid mappings in them. Hence, if a user page is wired,
4409 * the PT page will be also.
4411 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4412 pmap->pm_stats.wired_count++;
4413 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4414 pmap->pm_stats.wired_count--;
4417 * Remove the extra PT page reference.
4421 KASSERT(mpte->wire_count > 0,
4422 ("pmap_enter: missing reference to page table page,"
4427 * Has the physical page changed?
4429 opa = origpte & PG_FRAME;
4432 * No, might be a protection or wiring change.
4434 if ((origpte & PG_MANAGED) != 0 &&
4435 (newpte & PG_RW) != 0)
4436 vm_page_aflag_set(m, PGA_WRITEABLE);
4437 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4443 * Increment the counters.
4445 if ((newpte & PG_W) != 0)
4446 pmap->pm_stats.wired_count++;
4447 pmap_resident_count_inc(pmap, 1);
4451 * Enter on the PV list if part of our managed memory.
4453 if ((newpte & PG_MANAGED) != 0) {
4454 pv = get_pv_entry(pmap, &lock);
4456 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4457 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4459 if ((newpte & PG_RW) != 0)
4460 vm_page_aflag_set(m, PGA_WRITEABLE);
4466 if ((origpte & PG_V) != 0) {
4468 origpte = pte_load_store(pte, newpte);
4469 opa = origpte & PG_FRAME;
4471 if ((origpte & PG_MANAGED) != 0) {
4472 om = PHYS_TO_VM_PAGE(opa);
4473 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4476 if ((origpte & PG_A) != 0)
4477 vm_page_aflag_set(om, PGA_REFERENCED);
4478 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4479 pmap_pvh_free(&om->md, pmap, va);
4480 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4481 TAILQ_EMPTY(&om->md.pv_list) &&
4482 ((om->flags & PG_FICTITIOUS) != 0 ||
4483 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4484 vm_page_aflag_clear(om, PGA_WRITEABLE);
4486 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4487 PG_RW)) == (PG_M | PG_RW)) {
4488 if ((origpte & PG_MANAGED) != 0)
4492 * Although the PTE may still have PG_RW set, TLB
4493 * invalidation may nonetheless be required because
4494 * the PTE no longer has PG_M set.
4496 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4498 * This PTE change does not require TLB invalidation.
4502 if ((origpte & PG_A) != 0)
4503 pmap_invalidate_page(pmap, va);
4505 pte_store(pte, newpte);
4510 * If both the page table page and the reservation are fully
4511 * populated, then attempt promotion.
4513 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4514 pmap_ps_enabled(pmap) &&
4515 (m->flags & PG_FICTITIOUS) == 0 &&
4516 vm_reserv_level_iffullpop(m) == 0)
4517 pmap_promote_pde(pmap, pde, va, &lock);
4522 return (KERN_SUCCESS);
4526 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4527 * otherwise. Fails if (1) a page table page cannot be allocated without
4528 * blocking, (2) a mapping already exists at the specified virtual address, or
4529 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4532 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4533 struct rwlock **lockp)
4535 pd_entry_t *pde, newpde;
4538 struct spglist free;
4540 PG_V = pmap_valid_bit(pmap);
4541 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4543 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4544 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4545 " in pmap %p", va, pmap);
4548 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4549 pde = &pde[pmap_pde_index(va)];
4550 if ((*pde & PG_V) != 0) {
4551 KASSERT(mpde->wire_count > 1,
4552 ("pmap_enter_pde: mpde's wire count is too low"));
4554 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4555 " in pmap %p", va, pmap);
4558 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4560 if ((m->oflags & VPO_UNMANAGED) == 0) {
4561 newpde |= PG_MANAGED;
4564 * Abort this mapping if its PV entry could not be created.
4566 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4569 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4571 * Although "va" is not mapped, paging-
4572 * structure caches could nonetheless have
4573 * entries that refer to the freed page table
4574 * pages. Invalidate those entries.
4576 pmap_invalidate_page(pmap, va);
4577 pmap_free_zero_pages(&free);
4579 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4580 " in pmap %p", va, pmap);
4584 if ((prot & VM_PROT_EXECUTE) == 0)
4586 if (va < VM_MAXUSER_ADDRESS)
4590 * Increment counters.
4592 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4595 * Map the superpage. (This is not a promoted mapping; there will not
4596 * be any lingering 4KB page mappings in the TLB.)
4598 pde_store(pde, newpde);
4600 atomic_add_long(&pmap_pde_mappings, 1);
4601 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4602 " in pmap %p", va, pmap);
4607 * Maps a sequence of resident pages belonging to the same object.
4608 * The sequence begins with the given page m_start. This page is
4609 * mapped at the given virtual address start. Each subsequent page is
4610 * mapped at a virtual address that is offset from start by the same
4611 * amount as the page is offset from m_start within the object. The
4612 * last page in the sequence is the page with the largest offset from
4613 * m_start that can be mapped at a virtual address less than the given
4614 * virtual address end. Not every virtual page between start and end
4615 * is mapped; only those for which a resident page exists with the
4616 * corresponding offset from m_start are mapped.
4619 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4620 vm_page_t m_start, vm_prot_t prot)
4622 struct rwlock *lock;
4625 vm_pindex_t diff, psize;
4627 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4629 psize = atop(end - start);
4634 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4635 va = start + ptoa(diff);
4636 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4637 m->psind == 1 && pmap_ps_enabled(pmap) &&
4638 pmap_enter_pde(pmap, va, m, prot, &lock))
4639 m = &m[NBPDR / PAGE_SIZE - 1];
4641 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4643 m = TAILQ_NEXT(m, listq);
4651 * this code makes some *MAJOR* assumptions:
4652 * 1. Current pmap & pmap exists.
4655 * 4. No page table pages.
4656 * but is *MUCH* faster than pmap_enter...
4660 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4662 struct rwlock *lock;
4666 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4673 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4674 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4676 struct spglist free;
4677 pt_entry_t *pte, PG_V;
4680 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4681 (m->oflags & VPO_UNMANAGED) != 0,
4682 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4683 PG_V = pmap_valid_bit(pmap);
4684 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4687 * In the case that a page table page is not
4688 * resident, we are creating it here.
4690 if (va < VM_MAXUSER_ADDRESS) {
4691 vm_pindex_t ptepindex;
4695 * Calculate pagetable page index
4697 ptepindex = pmap_pde_pindex(va);
4698 if (mpte && (mpte->pindex == ptepindex)) {
4702 * Get the page directory entry
4704 ptepa = pmap_pde(pmap, va);
4707 * If the page table page is mapped, we just increment
4708 * the hold count, and activate it. Otherwise, we
4709 * attempt to allocate a page table page. If this
4710 * attempt fails, we don't retry. Instead, we give up.
4712 if (ptepa && (*ptepa & PG_V) != 0) {
4715 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4719 * Pass NULL instead of the PV list lock
4720 * pointer, because we don't intend to sleep.
4722 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4727 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4728 pte = &pte[pmap_pte_index(va)];
4742 * Enter on the PV list if part of our managed memory.
4744 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4745 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4748 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4750 * Although "va" is not mapped, paging-
4751 * structure caches could nonetheless have
4752 * entries that refer to the freed page table
4753 * pages. Invalidate those entries.
4755 pmap_invalidate_page(pmap, va);
4756 pmap_free_zero_pages(&free);
4764 * Increment counters
4766 pmap_resident_count_inc(pmap, 1);
4768 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4769 if ((prot & VM_PROT_EXECUTE) == 0)
4773 * Now validate mapping with RO protection
4775 if ((m->oflags & VPO_UNMANAGED) != 0)
4776 pte_store(pte, pa | PG_V | PG_U);
4778 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4783 * Make a temporary mapping for a physical address. This is only intended
4784 * to be used for panic dumps.
4787 pmap_kenter_temporary(vm_paddr_t pa, int i)
4791 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4792 pmap_kenter(va, pa);
4794 return ((void *)crashdumpmap);
4798 * This code maps large physical mmap regions into the
4799 * processor address space. Note that some shortcuts
4800 * are taken, but the code works.
4803 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4804 vm_pindex_t pindex, vm_size_t size)
4807 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4808 vm_paddr_t pa, ptepa;
4812 PG_A = pmap_accessed_bit(pmap);
4813 PG_M = pmap_modified_bit(pmap);
4814 PG_V = pmap_valid_bit(pmap);
4815 PG_RW = pmap_rw_bit(pmap);
4817 VM_OBJECT_ASSERT_WLOCKED(object);
4818 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4819 ("pmap_object_init_pt: non-device object"));
4820 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4821 if (!pmap_ps_enabled(pmap))
4823 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4825 p = vm_page_lookup(object, pindex);
4826 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4827 ("pmap_object_init_pt: invalid page %p", p));
4828 pat_mode = p->md.pat_mode;
4831 * Abort the mapping if the first page is not physically
4832 * aligned to a 2MB page boundary.
4834 ptepa = VM_PAGE_TO_PHYS(p);
4835 if (ptepa & (NBPDR - 1))
4839 * Skip the first page. Abort the mapping if the rest of
4840 * the pages are not physically contiguous or have differing
4841 * memory attributes.
4843 p = TAILQ_NEXT(p, listq);
4844 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4846 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4847 ("pmap_object_init_pt: invalid page %p", p));
4848 if (pa != VM_PAGE_TO_PHYS(p) ||
4849 pat_mode != p->md.pat_mode)
4851 p = TAILQ_NEXT(p, listq);
4855 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4856 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4857 * will not affect the termination of this loop.
4860 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4861 pa < ptepa + size; pa += NBPDR) {
4862 pdpg = pmap_allocpde(pmap, addr, NULL);
4865 * The creation of mappings below is only an
4866 * optimization. If a page directory page
4867 * cannot be allocated without blocking,
4868 * continue on to the next mapping rather than
4874 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4875 pde = &pde[pmap_pde_index(addr)];
4876 if ((*pde & PG_V) == 0) {
4877 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4878 PG_U | PG_RW | PG_V);
4879 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4880 atomic_add_long(&pmap_pde_mappings, 1);
4882 /* Continue on if the PDE is already valid. */
4884 KASSERT(pdpg->wire_count > 0,
4885 ("pmap_object_init_pt: missing reference "
4886 "to page directory page, va: 0x%lx", addr));
4895 * Clear the wired attribute from the mappings for the specified range of
4896 * addresses in the given pmap. Every valid mapping within that range
4897 * must have the wired attribute set. In contrast, invalid mappings
4898 * cannot have the wired attribute set, so they are ignored.
4900 * The wired attribute of the page table entry is not a hardware
4901 * feature, so there is no need to invalidate any TLB entries.
4902 * Since pmap_demote_pde() for the wired entry must never fail,
4903 * pmap_delayed_invl_started()/finished() calls around the
4904 * function are not needed.
4907 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4909 vm_offset_t va_next;
4910 pml4_entry_t *pml4e;
4913 pt_entry_t *pte, PG_V;
4915 PG_V = pmap_valid_bit(pmap);
4917 for (; sva < eva; sva = va_next) {
4918 pml4e = pmap_pml4e(pmap, sva);
4919 if ((*pml4e & PG_V) == 0) {
4920 va_next = (sva + NBPML4) & ~PML4MASK;
4925 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4926 if ((*pdpe & PG_V) == 0) {
4927 va_next = (sva + NBPDP) & ~PDPMASK;
4932 va_next = (sva + NBPDR) & ~PDRMASK;
4935 pde = pmap_pdpe_to_pde(pdpe, sva);
4936 if ((*pde & PG_V) == 0)
4938 if ((*pde & PG_PS) != 0) {
4939 if ((*pde & PG_W) == 0)
4940 panic("pmap_unwire: pde %#jx is missing PG_W",
4944 * Are we unwiring the entire large page? If not,
4945 * demote the mapping and fall through.
4947 if (sva + NBPDR == va_next && eva >= va_next) {
4948 atomic_clear_long(pde, PG_W);
4949 pmap->pm_stats.wired_count -= NBPDR /
4952 } else if (!pmap_demote_pde(pmap, pde, sva))
4953 panic("pmap_unwire: demotion failed");
4957 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4959 if ((*pte & PG_V) == 0)
4961 if ((*pte & PG_W) == 0)
4962 panic("pmap_unwire: pte %#jx is missing PG_W",
4966 * PG_W must be cleared atomically. Although the pmap
4967 * lock synchronizes access to PG_W, another processor
4968 * could be setting PG_M and/or PG_A concurrently.
4970 atomic_clear_long(pte, PG_W);
4971 pmap->pm_stats.wired_count--;
4978 * Copy the range specified by src_addr/len
4979 * from the source map to the range dst_addr/len
4980 * in the destination map.
4982 * This routine is only advisory and need not do anything.
4986 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4987 vm_offset_t src_addr)
4989 struct rwlock *lock;
4990 struct spglist free;
4992 vm_offset_t end_addr = src_addr + len;
4993 vm_offset_t va_next;
4994 pt_entry_t PG_A, PG_M, PG_V;
4996 if (dst_addr != src_addr)
4999 if (dst_pmap->pm_type != src_pmap->pm_type)
5003 * EPT page table entries that require emulation of A/D bits are
5004 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5005 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5006 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5007 * implementations flag an EPT misconfiguration for exec-only
5008 * mappings we skip this function entirely for emulated pmaps.
5010 if (pmap_emulate_ad_bits(dst_pmap))
5014 if (dst_pmap < src_pmap) {
5015 PMAP_LOCK(dst_pmap);
5016 PMAP_LOCK(src_pmap);
5018 PMAP_LOCK(src_pmap);
5019 PMAP_LOCK(dst_pmap);
5022 PG_A = pmap_accessed_bit(dst_pmap);
5023 PG_M = pmap_modified_bit(dst_pmap);
5024 PG_V = pmap_valid_bit(dst_pmap);
5026 for (addr = src_addr; addr < end_addr; addr = va_next) {
5027 pt_entry_t *src_pte, *dst_pte;
5028 vm_page_t dstmpde, dstmpte, srcmpte;
5029 pml4_entry_t *pml4e;
5031 pd_entry_t srcptepaddr, *pde;
5033 KASSERT(addr < UPT_MIN_ADDRESS,
5034 ("pmap_copy: invalid to pmap_copy page tables"));
5036 pml4e = pmap_pml4e(src_pmap, addr);
5037 if ((*pml4e & PG_V) == 0) {
5038 va_next = (addr + NBPML4) & ~PML4MASK;
5044 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5045 if ((*pdpe & PG_V) == 0) {
5046 va_next = (addr + NBPDP) & ~PDPMASK;
5052 va_next = (addr + NBPDR) & ~PDRMASK;
5056 pde = pmap_pdpe_to_pde(pdpe, addr);
5058 if (srcptepaddr == 0)
5061 if (srcptepaddr & PG_PS) {
5062 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5064 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
5065 if (dstmpde == NULL)
5067 pde = (pd_entry_t *)
5068 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
5069 pde = &pde[pmap_pde_index(addr)];
5070 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5071 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
5072 PG_PS_FRAME, &lock))) {
5073 *pde = srcptepaddr & ~PG_W;
5074 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5075 atomic_add_long(&pmap_pde_mappings, 1);
5077 dstmpde->wire_count--;
5081 srcptepaddr &= PG_FRAME;
5082 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5083 KASSERT(srcmpte->wire_count > 0,
5084 ("pmap_copy: source page table page is unused"));
5086 if (va_next > end_addr)
5089 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5090 src_pte = &src_pte[pmap_pte_index(addr)];
5092 while (addr < va_next) {
5096 * we only virtual copy managed pages
5098 if ((ptetemp & PG_MANAGED) != 0) {
5099 if (dstmpte != NULL &&
5100 dstmpte->pindex == pmap_pde_pindex(addr))
5101 dstmpte->wire_count++;
5102 else if ((dstmpte = pmap_allocpte(dst_pmap,
5103 addr, NULL)) == NULL)
5105 dst_pte = (pt_entry_t *)
5106 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5107 dst_pte = &dst_pte[pmap_pte_index(addr)];
5108 if (*dst_pte == 0 &&
5109 pmap_try_insert_pv_entry(dst_pmap, addr,
5110 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5113 * Clear the wired, modified, and
5114 * accessed (referenced) bits
5117 *dst_pte = ptetemp & ~(PG_W | PG_M |
5119 pmap_resident_count_inc(dst_pmap, 1);
5122 if (pmap_unwire_ptp(dst_pmap, addr,
5125 * Although "addr" is not
5126 * mapped, paging-structure
5127 * caches could nonetheless
5128 * have entries that refer to
5129 * the freed page table pages.
5130 * Invalidate those entries.
5132 pmap_invalidate_page(dst_pmap,
5134 pmap_free_zero_pages(&free);
5138 if (dstmpte->wire_count >= srcmpte->wire_count)
5148 PMAP_UNLOCK(src_pmap);
5149 PMAP_UNLOCK(dst_pmap);
5153 * Zero the specified hardware page.
5156 pmap_zero_page(vm_page_t m)
5158 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5160 pagezero((void *)va);
5164 * Zero an an area within a single hardware page. off and size must not
5165 * cover an area beyond a single hardware page.
5168 pmap_zero_page_area(vm_page_t m, int off, int size)
5170 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5172 if (off == 0 && size == PAGE_SIZE)
5173 pagezero((void *)va);
5175 bzero((char *)va + off, size);
5179 * Copy 1 specified hardware page to another.
5182 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5184 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5185 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5187 pagecopy((void *)src, (void *)dst);
5190 int unmapped_buf_allowed = 1;
5193 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5194 vm_offset_t b_offset, int xfersize)
5198 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5202 while (xfersize > 0) {
5203 a_pg_offset = a_offset & PAGE_MASK;
5204 pages[0] = ma[a_offset >> PAGE_SHIFT];
5205 b_pg_offset = b_offset & PAGE_MASK;
5206 pages[1] = mb[b_offset >> PAGE_SHIFT];
5207 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5208 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5209 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5210 a_cp = (char *)vaddr[0] + a_pg_offset;
5211 b_cp = (char *)vaddr[1] + b_pg_offset;
5212 bcopy(a_cp, b_cp, cnt);
5213 if (__predict_false(mapped))
5214 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5222 * Returns true if the pmap's pv is one of the first
5223 * 16 pvs linked to from this page. This count may
5224 * be changed upwards or downwards in the future; it
5225 * is only necessary that true be returned for a small
5226 * subset of pmaps for proper page aging.
5229 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5231 struct md_page *pvh;
5232 struct rwlock *lock;
5237 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5238 ("pmap_page_exists_quick: page %p is not managed", m));
5240 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5242 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5243 if (PV_PMAP(pv) == pmap) {
5251 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5252 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5253 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5254 if (PV_PMAP(pv) == pmap) {
5268 * pmap_page_wired_mappings:
5270 * Return the number of managed mappings to the given physical page
5274 pmap_page_wired_mappings(vm_page_t m)
5276 struct rwlock *lock;
5277 struct md_page *pvh;
5281 int count, md_gen, pvh_gen;
5283 if ((m->oflags & VPO_UNMANAGED) != 0)
5285 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5289 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5291 if (!PMAP_TRYLOCK(pmap)) {
5292 md_gen = m->md.pv_gen;
5296 if (md_gen != m->md.pv_gen) {
5301 pte = pmap_pte(pmap, pv->pv_va);
5302 if ((*pte & PG_W) != 0)
5306 if ((m->flags & PG_FICTITIOUS) == 0) {
5307 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5308 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5310 if (!PMAP_TRYLOCK(pmap)) {
5311 md_gen = m->md.pv_gen;
5312 pvh_gen = pvh->pv_gen;
5316 if (md_gen != m->md.pv_gen ||
5317 pvh_gen != pvh->pv_gen) {
5322 pte = pmap_pde(pmap, pv->pv_va);
5323 if ((*pte & PG_W) != 0)
5333 * Returns TRUE if the given page is mapped individually or as part of
5334 * a 2mpage. Otherwise, returns FALSE.
5337 pmap_page_is_mapped(vm_page_t m)
5339 struct rwlock *lock;
5342 if ((m->oflags & VPO_UNMANAGED) != 0)
5344 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5346 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5347 ((m->flags & PG_FICTITIOUS) == 0 &&
5348 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5354 * Destroy all managed, non-wired mappings in the given user-space
5355 * pmap. This pmap cannot be active on any processor besides the
5358 * This function cannot be applied to the kernel pmap. Moreover, it
5359 * is not intended for general use. It is only to be used during
5360 * process termination. Consequently, it can be implemented in ways
5361 * that make it faster than pmap_remove(). First, it can more quickly
5362 * destroy mappings by iterating over the pmap's collection of PV
5363 * entries, rather than searching the page table. Second, it doesn't
5364 * have to test and clear the page table entries atomically, because
5365 * no processor is currently accessing the user address space. In
5366 * particular, a page table entry's dirty bit won't change state once
5367 * this function starts.
5370 pmap_remove_pages(pmap_t pmap)
5373 pt_entry_t *pte, tpte;
5374 pt_entry_t PG_M, PG_RW, PG_V;
5375 struct spglist free;
5376 vm_page_t m, mpte, mt;
5378 struct md_page *pvh;
5379 struct pv_chunk *pc, *npc;
5380 struct rwlock *lock;
5382 uint64_t inuse, bitmask;
5383 int allfree, field, freed, idx;
5384 boolean_t superpage;
5388 * Assert that the given pmap is only active on the current
5389 * CPU. Unfortunately, we cannot block another CPU from
5390 * activating the pmap while this function is executing.
5392 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5395 cpuset_t other_cpus;
5397 other_cpus = all_cpus;
5399 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5400 CPU_AND(&other_cpus, &pmap->pm_active);
5402 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5407 PG_M = pmap_modified_bit(pmap);
5408 PG_V = pmap_valid_bit(pmap);
5409 PG_RW = pmap_rw_bit(pmap);
5413 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5416 for (field = 0; field < _NPCM; field++) {
5417 inuse = ~pc->pc_map[field] & pc_freemask[field];
5418 while (inuse != 0) {
5420 bitmask = 1UL << bit;
5421 idx = field * 64 + bit;
5422 pv = &pc->pc_pventry[idx];
5425 pte = pmap_pdpe(pmap, pv->pv_va);
5427 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5429 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5432 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5434 pte = &pte[pmap_pte_index(pv->pv_va)];
5438 * Keep track whether 'tpte' is a
5439 * superpage explicitly instead of
5440 * relying on PG_PS being set.
5442 * This is because PG_PS is numerically
5443 * identical to PG_PTE_PAT and thus a
5444 * regular page could be mistaken for
5450 if ((tpte & PG_V) == 0) {
5451 panic("bad pte va %lx pte %lx",
5456 * We cannot remove wired pages from a process' mapping at this time
5464 pa = tpte & PG_PS_FRAME;
5466 pa = tpte & PG_FRAME;
5468 m = PHYS_TO_VM_PAGE(pa);
5469 KASSERT(m->phys_addr == pa,
5470 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5471 m, (uintmax_t)m->phys_addr,
5474 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5475 m < &vm_page_array[vm_page_array_size],
5476 ("pmap_remove_pages: bad tpte %#jx",
5482 * Update the vm_page_t clean/reference bits.
5484 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5486 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5492 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5495 pc->pc_map[field] |= bitmask;
5497 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5498 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5499 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5501 if (TAILQ_EMPTY(&pvh->pv_list)) {
5502 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5503 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5504 TAILQ_EMPTY(&mt->md.pv_list))
5505 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5507 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
5509 pmap_resident_count_dec(pmap, 1);
5510 KASSERT(mpte->wire_count == NPTEPG,
5511 ("pmap_remove_pages: pte page wire count error"));
5512 mpte->wire_count = 0;
5513 pmap_add_delayed_free_list(mpte, &free, FALSE);
5514 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
5517 pmap_resident_count_dec(pmap, 1);
5518 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5520 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5521 TAILQ_EMPTY(&m->md.pv_list) &&
5522 (m->flags & PG_FICTITIOUS) == 0) {
5523 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5524 if (TAILQ_EMPTY(&pvh->pv_list))
5525 vm_page_aflag_clear(m, PGA_WRITEABLE);
5528 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5532 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5533 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5534 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5536 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5542 pmap_invalidate_all(pmap);
5544 pmap_free_zero_pages(&free);
5548 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5550 struct rwlock *lock;
5552 struct md_page *pvh;
5553 pt_entry_t *pte, mask;
5554 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5556 int md_gen, pvh_gen;
5560 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5563 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5565 if (!PMAP_TRYLOCK(pmap)) {
5566 md_gen = m->md.pv_gen;
5570 if (md_gen != m->md.pv_gen) {
5575 pte = pmap_pte(pmap, pv->pv_va);
5578 PG_M = pmap_modified_bit(pmap);
5579 PG_RW = pmap_rw_bit(pmap);
5580 mask |= PG_RW | PG_M;
5583 PG_A = pmap_accessed_bit(pmap);
5584 PG_V = pmap_valid_bit(pmap);
5585 mask |= PG_V | PG_A;
5587 rv = (*pte & mask) == mask;
5592 if ((m->flags & PG_FICTITIOUS) == 0) {
5593 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5594 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5596 if (!PMAP_TRYLOCK(pmap)) {
5597 md_gen = m->md.pv_gen;
5598 pvh_gen = pvh->pv_gen;
5602 if (md_gen != m->md.pv_gen ||
5603 pvh_gen != pvh->pv_gen) {
5608 pte = pmap_pde(pmap, pv->pv_va);
5611 PG_M = pmap_modified_bit(pmap);
5612 PG_RW = pmap_rw_bit(pmap);
5613 mask |= PG_RW | PG_M;
5616 PG_A = pmap_accessed_bit(pmap);
5617 PG_V = pmap_valid_bit(pmap);
5618 mask |= PG_V | PG_A;
5620 rv = (*pte & mask) == mask;
5634 * Return whether or not the specified physical page was modified
5635 * in any physical maps.
5638 pmap_is_modified(vm_page_t m)
5641 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5642 ("pmap_is_modified: page %p is not managed", m));
5645 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5646 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5647 * is clear, no PTEs can have PG_M set.
5649 VM_OBJECT_ASSERT_WLOCKED(m->object);
5650 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5652 return (pmap_page_test_mappings(m, FALSE, TRUE));
5656 * pmap_is_prefaultable:
5658 * Return whether or not the specified virtual address is eligible
5662 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5665 pt_entry_t *pte, PG_V;
5668 PG_V = pmap_valid_bit(pmap);
5671 pde = pmap_pde(pmap, addr);
5672 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5673 pte = pmap_pde_to_pte(pde, addr);
5674 rv = (*pte & PG_V) == 0;
5681 * pmap_is_referenced:
5683 * Return whether or not the specified physical page was referenced
5684 * in any physical maps.
5687 pmap_is_referenced(vm_page_t m)
5690 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5691 ("pmap_is_referenced: page %p is not managed", m));
5692 return (pmap_page_test_mappings(m, TRUE, FALSE));
5696 * Clear the write and modified bits in each of the given page's mappings.
5699 pmap_remove_write(vm_page_t m)
5701 struct md_page *pvh;
5703 struct rwlock *lock;
5704 pv_entry_t next_pv, pv;
5706 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5708 int pvh_gen, md_gen;
5710 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5711 ("pmap_remove_write: page %p is not managed", m));
5714 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5715 * set by another thread while the object is locked. Thus,
5716 * if PGA_WRITEABLE is clear, no page table entries need updating.
5718 VM_OBJECT_ASSERT_WLOCKED(m->object);
5719 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5721 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5722 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5723 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5726 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5728 if (!PMAP_TRYLOCK(pmap)) {
5729 pvh_gen = pvh->pv_gen;
5733 if (pvh_gen != pvh->pv_gen) {
5739 PG_RW = pmap_rw_bit(pmap);
5741 pde = pmap_pde(pmap, va);
5742 if ((*pde & PG_RW) != 0)
5743 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5744 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5745 ("inconsistent pv lock %p %p for page %p",
5746 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5749 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5751 if (!PMAP_TRYLOCK(pmap)) {
5752 pvh_gen = pvh->pv_gen;
5753 md_gen = m->md.pv_gen;
5757 if (pvh_gen != pvh->pv_gen ||
5758 md_gen != m->md.pv_gen) {
5764 PG_M = pmap_modified_bit(pmap);
5765 PG_RW = pmap_rw_bit(pmap);
5766 pde = pmap_pde(pmap, pv->pv_va);
5767 KASSERT((*pde & PG_PS) == 0,
5768 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5770 pte = pmap_pde_to_pte(pde, pv->pv_va);
5773 if (oldpte & PG_RW) {
5774 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5777 if ((oldpte & PG_M) != 0)
5779 pmap_invalidate_page(pmap, pv->pv_va);
5784 vm_page_aflag_clear(m, PGA_WRITEABLE);
5785 pmap_delayed_invl_wait(m);
5788 static __inline boolean_t
5789 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5792 if (!pmap_emulate_ad_bits(pmap))
5795 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5798 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
5799 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5800 * if the EPT_PG_WRITE bit is set.
5802 if ((pte & EPT_PG_WRITE) != 0)
5806 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5808 if ((pte & EPT_PG_EXECUTE) == 0 ||
5809 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5816 * pmap_ts_referenced:
5818 * Return a count of reference bits for a page, clearing those bits.
5819 * It is not necessary for every reference bit to be cleared, but it
5820 * is necessary that 0 only be returned when there are truly no
5821 * reference bits set.
5823 * As an optimization, update the page's dirty field if a modified bit is
5824 * found while counting reference bits. This opportunistic update can be
5825 * performed at low cost and can eliminate the need for some future calls
5826 * to pmap_is_modified(). However, since this function stops after
5827 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5828 * dirty pages. Those dirty pages will only be detected by a future call
5829 * to pmap_is_modified().
5831 * A DI block is not needed within this function, because
5832 * invalidations are performed before the PV list lock is
5836 pmap_ts_referenced(vm_page_t m)
5838 struct md_page *pvh;
5841 struct rwlock *lock;
5842 pd_entry_t oldpde, *pde;
5843 pt_entry_t *pte, PG_A, PG_M, PG_RW;
5846 int cleared, md_gen, not_cleared, pvh_gen;
5847 struct spglist free;
5850 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5851 ("pmap_ts_referenced: page %p is not managed", m));
5854 pa = VM_PAGE_TO_PHYS(m);
5855 lock = PHYS_TO_PV_LIST_LOCK(pa);
5856 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
5860 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5861 goto small_mappings;
5867 if (!PMAP_TRYLOCK(pmap)) {
5868 pvh_gen = pvh->pv_gen;
5872 if (pvh_gen != pvh->pv_gen) {
5877 PG_A = pmap_accessed_bit(pmap);
5878 PG_M = pmap_modified_bit(pmap);
5879 PG_RW = pmap_rw_bit(pmap);
5881 pde = pmap_pde(pmap, pv->pv_va);
5883 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5885 * Although "oldpde" is mapping a 2MB page, because
5886 * this function is called at a 4KB page granularity,
5887 * we only update the 4KB page under test.
5891 if ((oldpde & PG_A) != 0) {
5893 * Since this reference bit is shared by 512 4KB
5894 * pages, it should not be cleared every time it is
5895 * tested. Apply a simple "hash" function on the
5896 * physical page number, the virtual superpage number,
5897 * and the pmap address to select one 4KB page out of
5898 * the 512 on which testing the reference bit will
5899 * result in clearing that reference bit. This
5900 * function is designed to avoid the selection of the
5901 * same 4KB page for every 2MB page mapping.
5903 * On demotion, a mapping that hasn't been referenced
5904 * is simply destroyed. To avoid the possibility of a
5905 * subsequent page fault on a demoted wired mapping,
5906 * always leave its reference bit set. Moreover,
5907 * since the superpage is wired, the current state of
5908 * its reference bit won't affect page replacement.
5910 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5911 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5912 (oldpde & PG_W) == 0) {
5913 if (safe_to_clear_referenced(pmap, oldpde)) {
5914 atomic_clear_long(pde, PG_A);
5915 pmap_invalidate_page(pmap, pv->pv_va);
5917 } else if (pmap_demote_pde_locked(pmap, pde,
5918 pv->pv_va, &lock)) {
5920 * Remove the mapping to a single page
5921 * so that a subsequent access may
5922 * repromote. Since the underlying
5923 * page table page is fully populated,
5924 * this removal never frees a page
5928 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5930 pte = pmap_pde_to_pte(pde, va);
5931 pmap_remove_pte(pmap, pte, va, *pde,
5933 pmap_invalidate_page(pmap, va);
5939 * The superpage mapping was removed
5940 * entirely and therefore 'pv' is no
5948 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5949 ("inconsistent pv lock %p %p for page %p",
5950 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5955 /* Rotate the PV list if it has more than one entry. */
5956 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5957 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5958 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5961 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5963 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5965 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5972 if (!PMAP_TRYLOCK(pmap)) {
5973 pvh_gen = pvh->pv_gen;
5974 md_gen = m->md.pv_gen;
5978 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5983 PG_A = pmap_accessed_bit(pmap);
5984 PG_M = pmap_modified_bit(pmap);
5985 PG_RW = pmap_rw_bit(pmap);
5986 pde = pmap_pde(pmap, pv->pv_va);
5987 KASSERT((*pde & PG_PS) == 0,
5988 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5990 pte = pmap_pde_to_pte(pde, pv->pv_va);
5991 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5993 if ((*pte & PG_A) != 0) {
5994 if (safe_to_clear_referenced(pmap, *pte)) {
5995 atomic_clear_long(pte, PG_A);
5996 pmap_invalidate_page(pmap, pv->pv_va);
5998 } else if ((*pte & PG_W) == 0) {
6000 * Wired pages cannot be paged out so
6001 * doing accessed bit emulation for
6002 * them is wasted effort. We do the
6003 * hard work for unwired pages only.
6005 pmap_remove_pte(pmap, pte, pv->pv_va,
6006 *pde, &free, &lock);
6007 pmap_invalidate_page(pmap, pv->pv_va);
6012 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6013 ("inconsistent pv lock %p %p for page %p",
6014 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6019 /* Rotate the PV list if it has more than one entry. */
6020 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6021 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6022 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6025 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6026 not_cleared < PMAP_TS_REFERENCED_MAX);
6029 pmap_free_zero_pages(&free);
6030 return (cleared + not_cleared);
6034 * Apply the given advice to the specified range of addresses within the
6035 * given pmap. Depending on the advice, clear the referenced and/or
6036 * modified flags in each mapping and set the mapped page's dirty field.
6039 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6041 struct rwlock *lock;
6042 pml4_entry_t *pml4e;
6044 pd_entry_t oldpde, *pde;
6045 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6046 vm_offset_t va, va_next;
6048 boolean_t anychanged;
6050 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6054 * A/D bit emulation requires an alternate code path when clearing
6055 * the modified and accessed bits below. Since this function is
6056 * advisory in nature we skip it entirely for pmaps that require
6057 * A/D bit emulation.
6059 if (pmap_emulate_ad_bits(pmap))
6062 PG_A = pmap_accessed_bit(pmap);
6063 PG_G = pmap_global_bit(pmap);
6064 PG_M = pmap_modified_bit(pmap);
6065 PG_V = pmap_valid_bit(pmap);
6066 PG_RW = pmap_rw_bit(pmap);
6068 pmap_delayed_invl_started();
6070 for (; sva < eva; sva = va_next) {
6071 pml4e = pmap_pml4e(pmap, sva);
6072 if ((*pml4e & PG_V) == 0) {
6073 va_next = (sva + NBPML4) & ~PML4MASK;
6078 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6079 if ((*pdpe & PG_V) == 0) {
6080 va_next = (sva + NBPDP) & ~PDPMASK;
6085 va_next = (sva + NBPDR) & ~PDRMASK;
6088 pde = pmap_pdpe_to_pde(pdpe, sva);
6090 if ((oldpde & PG_V) == 0)
6092 else if ((oldpde & PG_PS) != 0) {
6093 if ((oldpde & PG_MANAGED) == 0)
6096 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6101 * The large page mapping was destroyed.
6107 * Unless the page mappings are wired, remove the
6108 * mapping to a single page so that a subsequent
6109 * access may repromote. Since the underlying page
6110 * table page is fully populated, this removal never
6111 * frees a page table page.
6113 if ((oldpde & PG_W) == 0) {
6114 pte = pmap_pde_to_pte(pde, sva);
6115 KASSERT((*pte & PG_V) != 0,
6116 ("pmap_advise: invalid PTE"));
6117 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6127 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6129 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6131 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6132 if (advice == MADV_DONTNEED) {
6134 * Future calls to pmap_is_modified()
6135 * can be avoided by making the page
6138 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6141 atomic_clear_long(pte, PG_M | PG_A);
6142 } else if ((*pte & PG_A) != 0)
6143 atomic_clear_long(pte, PG_A);
6147 if ((*pte & PG_G) != 0) {
6154 if (va != va_next) {
6155 pmap_invalidate_range(pmap, va, sva);
6160 pmap_invalidate_range(pmap, va, sva);
6163 pmap_invalidate_all(pmap);
6165 pmap_delayed_invl_finished();
6169 * Clear the modify bits on the specified physical page.
6172 pmap_clear_modify(vm_page_t m)
6174 struct md_page *pvh;
6176 pv_entry_t next_pv, pv;
6177 pd_entry_t oldpde, *pde;
6178 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6179 struct rwlock *lock;
6181 int md_gen, pvh_gen;
6183 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6184 ("pmap_clear_modify: page %p is not managed", m));
6185 VM_OBJECT_ASSERT_WLOCKED(m->object);
6186 KASSERT(!vm_page_xbusied(m),
6187 ("pmap_clear_modify: page %p is exclusive busied", m));
6190 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6191 * If the object containing the page is locked and the page is not
6192 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6194 if ((m->aflags & PGA_WRITEABLE) == 0)
6196 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6197 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6198 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6201 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6203 if (!PMAP_TRYLOCK(pmap)) {
6204 pvh_gen = pvh->pv_gen;
6208 if (pvh_gen != pvh->pv_gen) {
6213 PG_M = pmap_modified_bit(pmap);
6214 PG_V = pmap_valid_bit(pmap);
6215 PG_RW = pmap_rw_bit(pmap);
6217 pde = pmap_pde(pmap, va);
6219 if ((oldpde & PG_RW) != 0) {
6220 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6221 if ((oldpde & PG_W) == 0) {
6223 * Write protect the mapping to a
6224 * single page so that a subsequent
6225 * write access may repromote.
6227 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6229 pte = pmap_pde_to_pte(pde, va);
6231 if ((oldpte & PG_V) != 0) {
6232 while (!atomic_cmpset_long(pte,
6234 oldpte & ~(PG_M | PG_RW)))
6237 pmap_invalidate_page(pmap, va);
6244 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6246 if (!PMAP_TRYLOCK(pmap)) {
6247 md_gen = m->md.pv_gen;
6248 pvh_gen = pvh->pv_gen;
6252 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6257 PG_M = pmap_modified_bit(pmap);
6258 PG_RW = pmap_rw_bit(pmap);
6259 pde = pmap_pde(pmap, pv->pv_va);
6260 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6261 " a 2mpage in page %p's pv list", m));
6262 pte = pmap_pde_to_pte(pde, pv->pv_va);
6263 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6264 atomic_clear_long(pte, PG_M);
6265 pmap_invalidate_page(pmap, pv->pv_va);
6273 * Miscellaneous support routines follow
6276 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6277 static __inline void
6278 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6283 * The cache mode bits are all in the low 32-bits of the
6284 * PTE, so we can just spin on updating the low 32-bits.
6287 opte = *(u_int *)pte;
6288 npte = opte & ~mask;
6290 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6293 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6294 static __inline void
6295 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6300 * The cache mode bits are all in the low 32-bits of the
6301 * PDE, so we can just spin on updating the low 32-bits.
6304 opde = *(u_int *)pde;
6305 npde = opde & ~mask;
6307 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6311 * Map a set of physical memory pages into the kernel virtual
6312 * address space. Return a pointer to where it is mapped. This
6313 * routine is intended to be used for mapping device memory,
6317 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6319 struct pmap_preinit_mapping *ppim;
6320 vm_offset_t va, offset;
6324 offset = pa & PAGE_MASK;
6325 size = round_page(offset + size);
6326 pa = trunc_page(pa);
6328 if (!pmap_initialized) {
6330 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6331 ppim = pmap_preinit_mapping + i;
6332 if (ppim->va == 0) {
6336 ppim->va = virtual_avail;
6337 virtual_avail += size;
6343 panic("%s: too many preinit mappings", __func__);
6346 * If we have a preinit mapping, re-use it.
6348 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6349 ppim = pmap_preinit_mapping + i;
6350 if (ppim->pa == pa && ppim->sz == size &&
6352 return ((void *)(ppim->va + offset));
6355 * If the specified range of physical addresses fits within
6356 * the direct map window, use the direct map.
6358 if (pa < dmaplimit && pa + size < dmaplimit) {
6359 va = PHYS_TO_DMAP(pa);
6360 if (!pmap_change_attr(va, size, mode))
6361 return ((void *)(va + offset));
6363 va = kva_alloc(size);
6365 panic("%s: Couldn't allocate KVA", __func__);
6367 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6368 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6369 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6370 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6371 return ((void *)(va + offset));
6375 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6378 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6382 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6385 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6389 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6391 struct pmap_preinit_mapping *ppim;
6395 /* If we gave a direct map region in pmap_mapdev, do nothing */
6396 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6398 offset = va & PAGE_MASK;
6399 size = round_page(offset + size);
6400 va = trunc_page(va);
6401 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6402 ppim = pmap_preinit_mapping + i;
6403 if (ppim->va == va && ppim->sz == size) {
6404 if (pmap_initialized)
6410 if (va + size == virtual_avail)
6415 if (pmap_initialized)
6420 * Tries to demote a 1GB page mapping.
6423 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6425 pdp_entry_t newpdpe, oldpdpe;
6426 pd_entry_t *firstpde, newpde, *pde;
6427 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6431 PG_A = pmap_accessed_bit(pmap);
6432 PG_M = pmap_modified_bit(pmap);
6433 PG_V = pmap_valid_bit(pmap);
6434 PG_RW = pmap_rw_bit(pmap);
6436 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6438 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6439 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6440 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6441 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6442 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6443 " in pmap %p", va, pmap);
6446 mpdepa = VM_PAGE_TO_PHYS(mpde);
6447 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6448 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6449 KASSERT((oldpdpe & PG_A) != 0,
6450 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6451 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6452 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6456 * Initialize the page directory page.
6458 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6464 * Demote the mapping.
6469 * Invalidate a stale recursive mapping of the page directory page.
6471 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6473 pmap_pdpe_demotions++;
6474 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6475 " in pmap %p", va, pmap);
6480 * Sets the memory attribute for the specified page.
6483 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6486 m->md.pat_mode = ma;
6489 * If "m" is a normal page, update its direct mapping. This update
6490 * can be relied upon to perform any cache operations that are
6491 * required for data coherence.
6493 if ((m->flags & PG_FICTITIOUS) == 0 &&
6494 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6496 panic("memory attribute change on the direct map failed");
6500 * Changes the specified virtual address range's memory type to that given by
6501 * the parameter "mode". The specified virtual address range must be
6502 * completely contained within either the direct map or the kernel map. If
6503 * the virtual address range is contained within the kernel map, then the
6504 * memory type for each of the corresponding ranges of the direct map is also
6505 * changed. (The corresponding ranges of the direct map are those ranges that
6506 * map the same physical pages as the specified virtual address range.) These
6507 * changes to the direct map are necessary because Intel describes the
6508 * behavior of their processors as "undefined" if two or more mappings to the
6509 * same physical page have different memory types.
6511 * Returns zero if the change completed successfully, and either EINVAL or
6512 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6513 * of the virtual address range was not mapped, and ENOMEM is returned if
6514 * there was insufficient memory available to complete the change. In the
6515 * latter case, the memory type may have been changed on some part of the
6516 * virtual address range or the direct map.
6519 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6523 PMAP_LOCK(kernel_pmap);
6524 error = pmap_change_attr_locked(va, size, mode);
6525 PMAP_UNLOCK(kernel_pmap);
6530 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6532 vm_offset_t base, offset, tmpva;
6533 vm_paddr_t pa_start, pa_end, pa_end1;
6537 int cache_bits_pte, cache_bits_pde, error;
6540 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6541 base = trunc_page(va);
6542 offset = va & PAGE_MASK;
6543 size = round_page(offset + size);
6546 * Only supported on kernel virtual addresses, including the direct
6547 * map but excluding the recursive map.
6549 if (base < DMAP_MIN_ADDRESS)
6552 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6553 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6557 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6558 * into 4KB pages if required.
6560 for (tmpva = base; tmpva < base + size; ) {
6561 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6562 if (pdpe == NULL || *pdpe == 0)
6564 if (*pdpe & PG_PS) {
6566 * If the current 1GB page already has the required
6567 * memory type, then we need not demote this page. Just
6568 * increment tmpva to the next 1GB page frame.
6570 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6571 tmpva = trunc_1gpage(tmpva) + NBPDP;
6576 * If the current offset aligns with a 1GB page frame
6577 * and there is at least 1GB left within the range, then
6578 * we need not break down this page into 2MB pages.
6580 if ((tmpva & PDPMASK) == 0 &&
6581 tmpva + PDPMASK < base + size) {
6585 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6588 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6593 * If the current 2MB page already has the required
6594 * memory type, then we need not demote this page. Just
6595 * increment tmpva to the next 2MB page frame.
6597 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6598 tmpva = trunc_2mpage(tmpva) + NBPDR;
6603 * If the current offset aligns with a 2MB page frame
6604 * and there is at least 2MB left within the range, then
6605 * we need not break down this page into 4KB pages.
6607 if ((tmpva & PDRMASK) == 0 &&
6608 tmpva + PDRMASK < base + size) {
6612 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6615 pte = pmap_pde_to_pte(pde, tmpva);
6623 * Ok, all the pages exist, so run through them updating their
6624 * cache mode if required.
6626 pa_start = pa_end = 0;
6627 for (tmpva = base; tmpva < base + size; ) {
6628 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6629 if (*pdpe & PG_PS) {
6630 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6631 pmap_pde_attr(pdpe, cache_bits_pde,
6635 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6636 (*pdpe & PG_PS_FRAME) < dmaplimit) {
6637 if (pa_start == pa_end) {
6638 /* Start physical address run. */
6639 pa_start = *pdpe & PG_PS_FRAME;
6640 pa_end = pa_start + NBPDP;
6641 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6644 /* Run ended, update direct map. */
6645 error = pmap_change_attr_locked(
6646 PHYS_TO_DMAP(pa_start),
6647 pa_end - pa_start, mode);
6650 /* Start physical address run. */
6651 pa_start = *pdpe & PG_PS_FRAME;
6652 pa_end = pa_start + NBPDP;
6655 tmpva = trunc_1gpage(tmpva) + NBPDP;
6658 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6660 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6661 pmap_pde_attr(pde, cache_bits_pde,
6665 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6666 (*pde & PG_PS_FRAME) < dmaplimit) {
6667 if (pa_start == pa_end) {
6668 /* Start physical address run. */
6669 pa_start = *pde & PG_PS_FRAME;
6670 pa_end = pa_start + NBPDR;
6671 } else if (pa_end == (*pde & PG_PS_FRAME))
6674 /* Run ended, update direct map. */
6675 error = pmap_change_attr_locked(
6676 PHYS_TO_DMAP(pa_start),
6677 pa_end - pa_start, mode);
6680 /* Start physical address run. */
6681 pa_start = *pde & PG_PS_FRAME;
6682 pa_end = pa_start + NBPDR;
6685 tmpva = trunc_2mpage(tmpva) + NBPDR;
6687 pte = pmap_pde_to_pte(pde, tmpva);
6688 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6689 pmap_pte_attr(pte, cache_bits_pte,
6693 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6694 (*pte & PG_PS_FRAME) < dmaplimit) {
6695 if (pa_start == pa_end) {
6696 /* Start physical address run. */
6697 pa_start = *pte & PG_FRAME;
6698 pa_end = pa_start + PAGE_SIZE;
6699 } else if (pa_end == (*pte & PG_FRAME))
6700 pa_end += PAGE_SIZE;
6702 /* Run ended, update direct map. */
6703 error = pmap_change_attr_locked(
6704 PHYS_TO_DMAP(pa_start),
6705 pa_end - pa_start, mode);
6708 /* Start physical address run. */
6709 pa_start = *pte & PG_FRAME;
6710 pa_end = pa_start + PAGE_SIZE;
6716 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
6717 pa_end1 = MIN(pa_end, dmaplimit);
6718 if (pa_start != pa_end1)
6719 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6720 pa_end1 - pa_start, mode);
6724 * Flush CPU caches if required to make sure any data isn't cached that
6725 * shouldn't be, etc.
6728 pmap_invalidate_range(kernel_pmap, base, tmpva);
6729 pmap_invalidate_cache_range(base, tmpva, FALSE);
6735 * Demotes any mapping within the direct map region that covers more than the
6736 * specified range of physical addresses. This range's size must be a power
6737 * of two and its starting address must be a multiple of its size. Since the
6738 * demotion does not change any attributes of the mapping, a TLB invalidation
6739 * is not mandatory. The caller may, however, request a TLB invalidation.
6742 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6751 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6752 KASSERT((base & (len - 1)) == 0,
6753 ("pmap_demote_DMAP: base is not a multiple of len"));
6754 if (len < NBPDP && base < dmaplimit) {
6755 va = PHYS_TO_DMAP(base);
6757 PMAP_LOCK(kernel_pmap);
6758 pdpe = pmap_pdpe(kernel_pmap, va);
6759 if ((*pdpe & X86_PG_V) == 0)
6760 panic("pmap_demote_DMAP: invalid PDPE");
6761 if ((*pdpe & PG_PS) != 0) {
6762 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6763 panic("pmap_demote_DMAP: PDPE failed");
6767 pde = pmap_pdpe_to_pde(pdpe, va);
6768 if ((*pde & X86_PG_V) == 0)
6769 panic("pmap_demote_DMAP: invalid PDE");
6770 if ((*pde & PG_PS) != 0) {
6771 if (!pmap_demote_pde(kernel_pmap, pde, va))
6772 panic("pmap_demote_DMAP: PDE failed");
6776 if (changed && invalidate)
6777 pmap_invalidate_page(kernel_pmap, va);
6778 PMAP_UNLOCK(kernel_pmap);
6783 * perform the pmap work for mincore
6786 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6789 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6793 PG_A = pmap_accessed_bit(pmap);
6794 PG_M = pmap_modified_bit(pmap);
6795 PG_V = pmap_valid_bit(pmap);
6796 PG_RW = pmap_rw_bit(pmap);
6800 pdep = pmap_pde(pmap, addr);
6801 if (pdep != NULL && (*pdep & PG_V)) {
6802 if (*pdep & PG_PS) {
6804 /* Compute the physical address of the 4KB page. */
6805 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6807 val = MINCORE_SUPER;
6809 pte = *pmap_pde_to_pte(pdep, addr);
6810 pa = pte & PG_FRAME;
6818 if ((pte & PG_V) != 0) {
6819 val |= MINCORE_INCORE;
6820 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6821 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6822 if ((pte & PG_A) != 0)
6823 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6825 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6826 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6827 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6828 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6829 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6832 PA_UNLOCK_COND(*locked_pa);
6838 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
6840 uint32_t gen, new_gen, pcid_next;
6842 CRITICAL_ASSERT(curthread);
6843 gen = PCPU_GET(pcid_gen);
6844 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN ||
6845 pmap->pm_pcids[cpuid].pm_gen == gen)
6846 return (CR3_PCID_SAVE);
6847 pcid_next = PCPU_GET(pcid_next);
6848 KASSERT(pcid_next <= PMAP_PCID_OVERMAX, ("cpu %d pcid_next %#x",
6850 if (pcid_next == PMAP_PCID_OVERMAX) {
6854 PCPU_SET(pcid_gen, new_gen);
6855 pcid_next = PMAP_PCID_KERN + 1;
6859 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
6860 pmap->pm_pcids[cpuid].pm_gen = new_gen;
6861 PCPU_SET(pcid_next, pcid_next + 1);
6866 pmap_activate_sw(struct thread *td)
6868 pmap_t oldpmap, pmap;
6869 uint64_t cached, cr3;
6873 oldpmap = PCPU_GET(curpmap);
6874 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6875 if (oldpmap == pmap)
6877 cpuid = PCPU_GET(cpuid);
6879 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6881 CPU_SET(cpuid, &pmap->pm_active);
6884 if (pmap_pcid_enabled) {
6885 cached = pmap_pcid_alloc(pmap, cpuid);
6886 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
6887 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
6888 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
6889 pmap->pm_pcids[cpuid].pm_pcid));
6890 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
6891 pmap == kernel_pmap,
6892 ("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
6893 td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
6896 * If the INVPCID instruction is not available,
6897 * invltlb_pcid_handler() is used for handle
6898 * invalidate_all IPI, which checks for curpmap ==
6899 * smp_tlb_pmap. Below operations sequence has a
6900 * window where %CR3 is loaded with the new pmap's
6901 * PML4 address, but curpmap value is not yet updated.
6902 * This causes invltlb IPI handler, called between the
6903 * updates, to execute as NOP, which leaves stale TLB
6906 * Note that the most typical use of
6907 * pmap_activate_sw(), from the context switch, is
6908 * immune to this race, because interrupts are
6909 * disabled (while the thread lock is owned), and IPI
6910 * happends after curpmap is updated. Protect other
6911 * callers in a similar way, by disabling interrupts
6912 * around the %cr3 register reload and curpmap
6916 rflags = intr_disable();
6918 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
6919 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
6922 PCPU_INC(pm_save_cnt);
6924 PCPU_SET(curpmap, pmap);
6926 intr_restore(rflags);
6927 } else if (cr3 != pmap->pm_cr3) {
6928 load_cr3(pmap->pm_cr3);
6929 PCPU_SET(curpmap, pmap);
6932 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6934 CPU_CLR(cpuid, &oldpmap->pm_active);
6939 pmap_activate(struct thread *td)
6943 pmap_activate_sw(td);
6948 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6953 * Increase the starting virtual address of the given mapping if a
6954 * different alignment might result in more superpage mappings.
6957 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6958 vm_offset_t *addr, vm_size_t size)
6960 vm_offset_t superpage_offset;
6964 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6965 offset += ptoa(object->pg_color);
6966 superpage_offset = offset & PDRMASK;
6967 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6968 (*addr & PDRMASK) == superpage_offset)
6970 if ((*addr & PDRMASK) < superpage_offset)
6971 *addr = (*addr & ~PDRMASK) + superpage_offset;
6973 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6977 static unsigned long num_dirty_emulations;
6978 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6979 &num_dirty_emulations, 0, NULL);
6981 static unsigned long num_accessed_emulations;
6982 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6983 &num_accessed_emulations, 0, NULL);
6985 static unsigned long num_superpage_accessed_emulations;
6986 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6987 &num_superpage_accessed_emulations, 0, NULL);
6989 static unsigned long ad_emulation_superpage_promotions;
6990 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6991 &ad_emulation_superpage_promotions, 0, NULL);
6992 #endif /* INVARIANTS */
6995 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6998 struct rwlock *lock;
7001 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
7003 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
7004 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
7006 if (!pmap_emulate_ad_bits(pmap))
7009 PG_A = pmap_accessed_bit(pmap);
7010 PG_M = pmap_modified_bit(pmap);
7011 PG_V = pmap_valid_bit(pmap);
7012 PG_RW = pmap_rw_bit(pmap);
7018 pde = pmap_pde(pmap, va);
7019 if (pde == NULL || (*pde & PG_V) == 0)
7022 if ((*pde & PG_PS) != 0) {
7023 if (ftype == VM_PROT_READ) {
7025 atomic_add_long(&num_superpage_accessed_emulations, 1);
7033 pte = pmap_pde_to_pte(pde, va);
7034 if ((*pte & PG_V) == 0)
7037 if (ftype == VM_PROT_WRITE) {
7038 if ((*pte & PG_RW) == 0)
7041 * Set the modified and accessed bits simultaneously.
7043 * Intel EPT PTEs that do software emulation of A/D bits map
7044 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
7045 * An EPT misconfiguration is triggered if the PTE is writable
7046 * but not readable (WR=10). This is avoided by setting PG_A
7047 * and PG_M simultaneously.
7049 *pte |= PG_M | PG_A;
7054 /* try to promote the mapping */
7055 if (va < VM_MAXUSER_ADDRESS)
7056 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7060 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7062 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
7063 pmap_ps_enabled(pmap) &&
7064 (m->flags & PG_FICTITIOUS) == 0 &&
7065 vm_reserv_level_iffullpop(m) == 0) {
7066 pmap_promote_pde(pmap, pde, va, &lock);
7068 atomic_add_long(&ad_emulation_superpage_promotions, 1);
7072 if (ftype == VM_PROT_WRITE)
7073 atomic_add_long(&num_dirty_emulations, 1);
7075 atomic_add_long(&num_accessed_emulations, 1);
7077 rv = 0; /* success */
7086 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
7091 pt_entry_t *pte, PG_V;
7095 PG_V = pmap_valid_bit(pmap);
7098 pml4 = pmap_pml4e(pmap, va);
7100 if ((*pml4 & PG_V) == 0)
7103 pdp = pmap_pml4e_to_pdpe(pml4, va);
7105 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
7108 pde = pmap_pdpe_to_pde(pdp, va);
7110 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
7113 pte = pmap_pde_to_pte(pde, va);
7122 * Get the kernel virtual address of a set of physical pages. If there are
7123 * physical addresses not covered by the DMAP perform a transient mapping
7124 * that will be removed when calling pmap_unmap_io_transient.
7126 * \param page The pages the caller wishes to obtain the virtual
7127 * address on the kernel memory map.
7128 * \param vaddr On return contains the kernel virtual memory address
7129 * of the pages passed in the page parameter.
7130 * \param count Number of pages passed in.
7131 * \param can_fault TRUE if the thread using the mapped pages can take
7132 * page faults, FALSE otherwise.
7134 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7135 * finished or FALSE otherwise.
7139 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7140 boolean_t can_fault)
7143 boolean_t needs_mapping;
7145 int cache_bits, error, i;
7148 * Allocate any KVA space that we need, this is done in a separate
7149 * loop to prevent calling vmem_alloc while pinned.
7151 needs_mapping = FALSE;
7152 for (i = 0; i < count; i++) {
7153 paddr = VM_PAGE_TO_PHYS(page[i]);
7154 if (__predict_false(paddr >= dmaplimit)) {
7155 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7156 M_BESTFIT | M_WAITOK, &vaddr[i]);
7157 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7158 needs_mapping = TRUE;
7160 vaddr[i] = PHYS_TO_DMAP(paddr);
7164 /* Exit early if everything is covered by the DMAP */
7169 * NB: The sequence of updating a page table followed by accesses
7170 * to the corresponding pages used in the !DMAP case is subject to
7171 * the situation described in the "AMD64 Architecture Programmer's
7172 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7173 * Coherency Considerations". Therefore, issuing the INVLPG right
7174 * after modifying the PTE bits is crucial.
7178 for (i = 0; i < count; i++) {
7179 paddr = VM_PAGE_TO_PHYS(page[i]);
7180 if (paddr >= dmaplimit) {
7183 * Slow path, since we can get page faults
7184 * while mappings are active don't pin the
7185 * thread to the CPU and instead add a global
7186 * mapping visible to all CPUs.
7188 pmap_qenter(vaddr[i], &page[i], 1);
7190 pte = vtopte(vaddr[i]);
7191 cache_bits = pmap_cache_bits(kernel_pmap,
7192 page[i]->md.pat_mode, 0);
7193 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7200 return (needs_mapping);
7204 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7205 boolean_t can_fault)
7212 for (i = 0; i < count; i++) {
7213 paddr = VM_PAGE_TO_PHYS(page[i]);
7214 if (paddr >= dmaplimit) {
7216 pmap_qremove(vaddr[i], 1);
7217 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7223 pmap_quick_enter_page(vm_page_t m)
7227 paddr = VM_PAGE_TO_PHYS(m);
7228 if (paddr < dmaplimit)
7229 return (PHYS_TO_DMAP(paddr));
7230 mtx_lock_spin(&qframe_mtx);
7231 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7232 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7233 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7238 pmap_quick_remove_page(vm_offset_t addr)
7243 pte_store(vtopte(qframe), 0);
7245 mtx_unlock_spin(&qframe_mtx);
7248 #include "opt_ddb.h"
7250 #include <sys/kdb.h>
7251 #include <ddb/ddb.h>
7253 DB_SHOW_COMMAND(pte, pmap_print_pte)
7259 pt_entry_t *pte, PG_V;
7263 db_printf("show pte addr\n");
7266 va = (vm_offset_t)addr;
7268 if (kdb_thread != NULL)
7269 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
7271 pmap = PCPU_GET(curpmap);
7273 PG_V = pmap_valid_bit(pmap);
7274 pml4 = pmap_pml4e(pmap, va);
7275 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
7276 if ((*pml4 & PG_V) == 0) {
7280 pdp = pmap_pml4e_to_pdpe(pml4, va);
7281 db_printf(" pdpe %#016lx", *pdp);
7282 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
7286 pde = pmap_pdpe_to_pde(pdp, va);
7287 db_printf(" pde %#016lx", *pde);
7288 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
7292 pte = pmap_pde_to_pte(pde, va);
7293 db_printf(" pte %#016lx\n", *pte);
7296 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
7301 a = (vm_paddr_t)addr;
7302 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
7304 db_printf("show phys2dmap addr\n");