2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rangeset.h>
125 #include <sys/rwlock.h>
127 #include <sys/turnstile.h>
128 #include <sys/vmem.h>
129 #include <sys/vmmeter.h>
130 #include <sys/sched.h>
131 #include <sys/sysctl.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/intr_machdep.h>
149 #include <x86/apicvar.h>
150 #include <x86/ifunc.h>
151 #include <machine/cpu.h>
152 #include <machine/cputypes.h>
153 #include <machine/md_var.h>
154 #include <machine/pcb.h>
155 #include <machine/specialreg.h>
157 #include <machine/smp.h>
159 #include <machine/sysarch.h>
160 #include <machine/tss.h>
162 static __inline boolean_t
163 pmap_type_guest(pmap_t pmap)
166 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
169 static __inline boolean_t
170 pmap_emulate_ad_bits(pmap_t pmap)
173 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
176 static __inline pt_entry_t
177 pmap_valid_bit(pmap_t pmap)
181 switch (pmap->pm_type) {
187 if (pmap_emulate_ad_bits(pmap))
188 mask = EPT_PG_EMUL_V;
193 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
199 static __inline pt_entry_t
200 pmap_rw_bit(pmap_t pmap)
204 switch (pmap->pm_type) {
210 if (pmap_emulate_ad_bits(pmap))
211 mask = EPT_PG_EMUL_RW;
216 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
222 static pt_entry_t pg_g;
224 static __inline pt_entry_t
225 pmap_global_bit(pmap_t pmap)
229 switch (pmap->pm_type) {
238 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
244 static __inline pt_entry_t
245 pmap_accessed_bit(pmap_t pmap)
249 switch (pmap->pm_type) {
255 if (pmap_emulate_ad_bits(pmap))
261 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
267 static __inline pt_entry_t
268 pmap_modified_bit(pmap_t pmap)
272 switch (pmap->pm_type) {
278 if (pmap_emulate_ad_bits(pmap))
284 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
290 static __inline pt_entry_t
291 pmap_pku_mask_bit(pmap_t pmap)
294 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
297 #if !defined(DIAGNOSTIC)
298 #ifdef __GNUC_GNU_INLINE__
299 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
301 #define PMAP_INLINE extern inline
308 #define PV_STAT(x) do { x ; } while (0)
310 #define PV_STAT(x) do { } while (0)
313 #define pa_index(pa) ((pa) >> PDRSHIFT)
314 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
316 #define NPV_LIST_LOCKS MAXCPU
318 #define PHYS_TO_PV_LIST_LOCK(pa) \
319 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
321 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
322 struct rwlock **_lockp = (lockp); \
323 struct rwlock *_new_lock; \
325 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
326 if (_new_lock != *_lockp) { \
327 if (*_lockp != NULL) \
328 rw_wunlock(*_lockp); \
329 *_lockp = _new_lock; \
334 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
335 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
337 #define RELEASE_PV_LIST_LOCK(lockp) do { \
338 struct rwlock **_lockp = (lockp); \
340 if (*_lockp != NULL) { \
341 rw_wunlock(*_lockp); \
346 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
347 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
349 struct pmap kernel_pmap_store;
351 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
352 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
355 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
356 "Number of kernel page table pages allocated on bootup");
359 vm_paddr_t dmaplimit;
360 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
363 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
365 /* Unused, kept for ABI stability on the stable branch. */
366 static int pat_works = 1;
367 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
368 "Is page attribute table fully functional?");
370 static int pg_ps_enabled = 1;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
372 &pg_ps_enabled, 0, "Are large page mappings enabled?");
374 #define PAT_INDEX_SIZE 8
375 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
377 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
378 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
379 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
380 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
382 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
383 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
384 static int ndmpdpphys; /* number of DMPDPphys pages */
386 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
389 * pmap_mapdev support pre initialization (i.e. console)
391 #define PMAP_PREINIT_MAPPING_COUNT 8
392 static struct pmap_preinit_mapping {
397 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
398 static int pmap_initialized;
401 * Data for the pv entry allocation mechanism.
402 * Updates to pv_invl_gen are protected by the pv_list_locks[]
403 * elements, but reads are not.
405 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
406 static struct mtx __exclusive_cache_line pv_chunks_mutex;
407 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
408 static u_long pv_invl_gen[NPV_LIST_LOCKS];
409 static struct md_page *pv_table;
410 static struct md_page pv_dummy;
413 * All those kernel PT submaps that BSD is so fond of
415 pt_entry_t *CMAP1 = NULL;
417 static vm_offset_t qframe = 0;
418 static struct mtx qframe_mtx;
420 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
422 static vmem_t *large_vmem;
423 static u_int lm_ents;
425 int pmap_pcid_enabled = 1;
426 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
427 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
428 int invpcid_works = 0;
429 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
430 "Is the invpcid instruction available ?");
432 int __read_frequently pti = 0;
433 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
435 "Page Table Isolation enabled");
436 static vm_object_t pti_obj;
437 static pml4_entry_t *pti_pml4;
438 static vm_pindex_t pti_pg_idx;
439 static bool pti_finalized;
441 struct pmap_pkru_range {
442 struct rs_el pkru_rs_el;
447 static uma_zone_t pmap_pkru_ranges_zone;
448 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
449 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
450 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
451 static void *pkru_dup_range(void *ctx, void *data);
452 static void pkru_free_range(void *ctx, void *node);
453 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
454 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
455 static void pmap_pkru_deassign_all(pmap_t pmap);
458 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
465 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
467 return (sysctl_handle_64(oidp, &res, 0, req));
469 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
470 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
471 "Count of saved TLB context on switch");
473 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
474 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
475 static struct mtx invl_gen_mtx;
476 static u_long pmap_invl_gen = 0;
477 /* Fake lock object to satisfy turnstiles interface. */
478 static struct lock_object invl_gen_ts = {
486 return (curthread->td_md.md_invl_gen.gen == 0);
489 #define PMAP_ASSERT_NOT_IN_DI() \
490 KASSERT(pmap_not_in_di(), ("DI already started"))
493 * Start a new Delayed Invalidation (DI) block of code, executed by
494 * the current thread. Within a DI block, the current thread may
495 * destroy both the page table and PV list entries for a mapping and
496 * then release the corresponding PV list lock before ensuring that
497 * the mapping is flushed from the TLBs of any processors with the
501 pmap_delayed_invl_started(void)
503 struct pmap_invl_gen *invl_gen;
506 invl_gen = &curthread->td_md.md_invl_gen;
507 PMAP_ASSERT_NOT_IN_DI();
508 mtx_lock(&invl_gen_mtx);
509 if (LIST_EMPTY(&pmap_invl_gen_tracker))
510 currgen = pmap_invl_gen;
512 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
513 invl_gen->gen = currgen + 1;
514 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
515 mtx_unlock(&invl_gen_mtx);
519 * Finish the DI block, previously started by the current thread. All
520 * required TLB flushes for the pages marked by
521 * pmap_delayed_invl_page() must be finished before this function is
524 * This function works by bumping the global DI generation number to
525 * the generation number of the current thread's DI, unless there is a
526 * pending DI that started earlier. In the latter case, bumping the
527 * global DI generation number would incorrectly signal that the
528 * earlier DI had finished. Instead, this function bumps the earlier
529 * DI's generation number to match the generation number of the
530 * current thread's DI.
533 pmap_delayed_invl_finished(void)
535 struct pmap_invl_gen *invl_gen, *next;
536 struct turnstile *ts;
538 invl_gen = &curthread->td_md.md_invl_gen;
539 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
540 mtx_lock(&invl_gen_mtx);
541 next = LIST_NEXT(invl_gen, link);
543 turnstile_chain_lock(&invl_gen_ts);
544 ts = turnstile_lookup(&invl_gen_ts);
545 pmap_invl_gen = invl_gen->gen;
547 turnstile_broadcast(ts, TS_SHARED_QUEUE);
548 turnstile_unpend(ts);
550 turnstile_chain_unlock(&invl_gen_ts);
552 next->gen = invl_gen->gen;
554 LIST_REMOVE(invl_gen, link);
555 mtx_unlock(&invl_gen_mtx);
560 static long invl_wait;
561 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
562 "Number of times DI invalidation blocked pmap_remove_all/write");
566 pmap_delayed_invl_genp(vm_page_t m)
569 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
573 * Ensure that all currently executing DI blocks, that need to flush
574 * TLB for the given page m, actually flushed the TLB at the time the
575 * function returned. If the page m has an empty PV list and we call
576 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
577 * valid mapping for the page m in either its page table or TLB.
579 * This function works by blocking until the global DI generation
580 * number catches up with the generation number associated with the
581 * given page m and its PV list. Since this function's callers
582 * typically own an object lock and sometimes own a page lock, it
583 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
587 pmap_delayed_invl_wait(vm_page_t m)
589 struct turnstile *ts;
592 bool accounted = false;
595 m_gen = pmap_delayed_invl_genp(m);
596 while (*m_gen > pmap_invl_gen) {
599 atomic_add_long(&invl_wait, 1);
603 ts = turnstile_trywait(&invl_gen_ts);
604 if (*m_gen > pmap_invl_gen)
605 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
607 turnstile_cancel(ts);
612 * Mark the page m's PV list as participating in the current thread's
613 * DI block. Any threads concurrently using m's PV list to remove or
614 * restrict all mappings to m will wait for the current thread's DI
615 * block to complete before proceeding.
617 * The function works by setting the DI generation number for m's PV
618 * list to at least the DI generation number of the current thread.
619 * This forces a caller of pmap_delayed_invl_wait() to block until
620 * current thread calls pmap_delayed_invl_finished().
623 pmap_delayed_invl_page(vm_page_t m)
627 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
628 gen = curthread->td_md.md_invl_gen.gen;
631 m_gen = pmap_delayed_invl_genp(m);
639 static caddr_t crashdumpmap;
642 * Internal flags for pmap_enter()'s helper functions.
644 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
645 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
647 static void free_pv_chunk(struct pv_chunk *pc);
648 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
649 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
650 static int popcnt_pc_map_pq(uint64_t *map);
651 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
652 static void reserve_pv_entries(pmap_t pmap, int needed,
653 struct rwlock **lockp);
654 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
655 struct rwlock **lockp);
656 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
657 u_int flags, struct rwlock **lockp);
658 #if VM_NRESERVLEVEL > 0
659 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
660 struct rwlock **lockp);
662 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
663 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
666 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
668 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
669 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
670 vm_offset_t va, struct rwlock **lockp);
671 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
673 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
674 vm_prot_t prot, struct rwlock **lockp);
675 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
676 u_int flags, vm_page_t m, struct rwlock **lockp);
677 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
678 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
679 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
680 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
681 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
683 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
685 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
687 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
688 static vm_page_t pmap_large_map_getptp_unlocked(void);
689 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
690 #if VM_NRESERVLEVEL > 0
691 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
692 struct rwlock **lockp);
694 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
696 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
697 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
699 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
700 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
701 static void pmap_pti_wire_pte(void *pte);
702 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
703 struct spglist *free, struct rwlock **lockp);
704 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
705 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
706 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
707 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
708 struct spglist *free);
709 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
710 pd_entry_t *pde, struct spglist *free,
711 struct rwlock **lockp);
712 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
713 vm_page_t m, struct rwlock **lockp);
714 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
716 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
718 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
719 struct rwlock **lockp);
720 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
721 struct rwlock **lockp);
722 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
723 struct rwlock **lockp);
725 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
726 struct spglist *free);
727 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
729 /********************/
730 /* Inline functions */
731 /********************/
733 /* Return a non-clipped PD index for a given VA */
734 static __inline vm_pindex_t
735 pmap_pde_pindex(vm_offset_t va)
737 return (va >> PDRSHIFT);
741 /* Return a pointer to the PML4 slot that corresponds to a VA */
742 static __inline pml4_entry_t *
743 pmap_pml4e(pmap_t pmap, vm_offset_t va)
746 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
749 /* Return a pointer to the PDP slot that corresponds to a VA */
750 static __inline pdp_entry_t *
751 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
755 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
756 return (&pdpe[pmap_pdpe_index(va)]);
759 /* Return a pointer to the PDP slot that corresponds to a VA */
760 static __inline pdp_entry_t *
761 pmap_pdpe(pmap_t pmap, vm_offset_t va)
766 PG_V = pmap_valid_bit(pmap);
767 pml4e = pmap_pml4e(pmap, va);
768 if ((*pml4e & PG_V) == 0)
770 return (pmap_pml4e_to_pdpe(pml4e, va));
773 /* Return a pointer to the PD slot that corresponds to a VA */
774 static __inline pd_entry_t *
775 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
779 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
780 return (&pde[pmap_pde_index(va)]);
783 /* Return a pointer to the PD slot that corresponds to a VA */
784 static __inline pd_entry_t *
785 pmap_pde(pmap_t pmap, vm_offset_t va)
790 PG_V = pmap_valid_bit(pmap);
791 pdpe = pmap_pdpe(pmap, va);
792 if (pdpe == NULL || (*pdpe & PG_V) == 0)
794 return (pmap_pdpe_to_pde(pdpe, va));
797 /* Return a pointer to the PT slot that corresponds to a VA */
798 static __inline pt_entry_t *
799 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
803 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
804 return (&pte[pmap_pte_index(va)]);
807 /* Return a pointer to the PT slot that corresponds to a VA */
808 static __inline pt_entry_t *
809 pmap_pte(pmap_t pmap, vm_offset_t va)
814 PG_V = pmap_valid_bit(pmap);
815 pde = pmap_pde(pmap, va);
816 if (pde == NULL || (*pde & PG_V) == 0)
818 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
819 return ((pt_entry_t *)pde);
820 return (pmap_pde_to_pte(pde, va));
824 pmap_resident_count_inc(pmap_t pmap, int count)
827 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
828 pmap->pm_stats.resident_count += count;
832 pmap_resident_count_dec(pmap_t pmap, int count)
835 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
836 KASSERT(pmap->pm_stats.resident_count >= count,
837 ("pmap %p resident count underflow %ld %d", pmap,
838 pmap->pm_stats.resident_count, count));
839 pmap->pm_stats.resident_count -= count;
842 PMAP_INLINE pt_entry_t *
843 vtopte(vm_offset_t va)
845 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
847 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
849 return (PTmap + ((va >> PAGE_SHIFT) & mask));
852 static __inline pd_entry_t *
853 vtopde(vm_offset_t va)
855 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
857 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
859 return (PDmap + ((va >> PDRSHIFT) & mask));
863 allocpages(vm_paddr_t *firstaddr, int n)
868 bzero((void *)ret, n * PAGE_SIZE);
869 *firstaddr += n * PAGE_SIZE;
873 CTASSERT(powerof2(NDMPML4E));
875 /* number of kernel PDP slots */
876 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
879 nkpt_init(vm_paddr_t addr)
886 pt_pages = howmany(addr, 1 << PDRSHIFT);
887 pt_pages += NKPDPE(pt_pages);
890 * Add some slop beyond the bare minimum required for bootstrapping
893 * This is quite important when allocating KVA for kernel modules.
894 * The modules are required to be linked in the negative 2GB of
895 * the address space. If we run out of KVA in this region then
896 * pmap_growkernel() will need to allocate page table pages to map
897 * the entire 512GB of KVA space which is an unnecessary tax on
900 * Secondly, device memory mapped as part of setting up the low-
901 * level console(s) is taken from KVA, starting at virtual_avail.
902 * This is because cninit() is called after pmap_bootstrap() but
903 * before vm_init() and pmap_init(). 20MB for a frame buffer is
906 pt_pages += 32; /* 64MB additional slop. */
912 * Returns the proper write/execute permission for a physical page that is
913 * part of the initial boot allocations.
915 * If the page has kernel text, it is marked as read-only. If the page has
916 * kernel read-only data, it is marked as read-only/not-executable. If the
917 * page has only read-write data, it is marked as read-write/not-executable.
918 * If the page is below/above the kernel range, it is marked as read-write.
920 * This function operates on 2M pages, since we map the kernel space that
923 * Note that this doesn't currently provide any protection for modules.
925 static inline pt_entry_t
926 bootaddr_rwx(vm_paddr_t pa)
930 * Everything in the same 2M page as the start of the kernel
931 * should be static. On the other hand, things in the same 2M
932 * page as the end of the kernel could be read-write/executable,
933 * as the kernel image is not guaranteed to end on a 2M boundary.
935 if (pa < trunc_2mpage(btext - KERNBASE) ||
936 pa >= trunc_2mpage(_end - KERNBASE))
939 * The linker should ensure that the read-only and read-write
940 * portions don't share the same 2M page, so this shouldn't
941 * impact read-only data. However, in any case, any page with
942 * read-write data needs to be read-write.
944 if (pa >= trunc_2mpage(brwsection - KERNBASE))
945 return (X86_PG_RW | pg_nx);
947 * Mark any 2M page containing kernel text as read-only. Mark
948 * other pages with read-only data as read-only and not executable.
949 * (It is likely a small portion of the read-only data section will
950 * be marked as read-only, but executable. This should be acceptable
951 * since the read-only protection will keep the data from changing.)
952 * Note that fixups to the .text section will still work until we
955 if (pa < round_2mpage(etext - KERNBASE))
961 create_pagetables(vm_paddr_t *firstaddr)
963 int i, j, ndm1g, nkpdpe, nkdmpde;
968 uint64_t DMPDkernphys;
970 /* Allocate page table pages for the direct map */
971 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
972 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
974 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
975 if (ndmpdpphys > NDMPML4E) {
977 * Each NDMPML4E allows 512 GB, so limit to that,
978 * and then readjust ndmpdp and ndmpdpphys.
980 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
981 Maxmem = atop(NDMPML4E * NBPML4);
982 ndmpdpphys = NDMPML4E;
983 ndmpdp = NDMPML4E * NPDEPG;
985 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
987 if ((amd_feature & AMDID_PAGE1GB) != 0) {
989 * Calculate the number of 1G pages that will fully fit in
992 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
995 * Allocate 2M pages for the kernel. These will be used in
996 * place of the first one or more 1G pages from ndm1g.
998 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
999 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1002 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1003 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1005 /* Allocate pages */
1006 KPML4phys = allocpages(firstaddr, 1);
1007 KPDPphys = allocpages(firstaddr, NKPML4E);
1010 * Allocate the initial number of kernel page table pages required to
1011 * bootstrap. We defer this until after all memory-size dependent
1012 * allocations are done (e.g. direct map), so that we don't have to
1013 * build in too much slop in our estimate.
1015 * Note that when NKPML4E > 1, we have an empty page underneath
1016 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1017 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1019 nkpt_init(*firstaddr);
1020 nkpdpe = NKPDPE(nkpt);
1022 KPTphys = allocpages(firstaddr, nkpt);
1023 KPDphys = allocpages(firstaddr, nkpdpe);
1025 /* Fill in the underlying page table pages */
1026 /* XXX not fully used, underneath 2M pages */
1027 pt_p = (pt_entry_t *)KPTphys;
1028 for (i = 0; ptoa(i) < *firstaddr; i++)
1029 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
1031 /* Now map the page tables at their location within PTmap */
1032 pd_p = (pd_entry_t *)KPDphys;
1033 for (i = 0; i < nkpt; i++)
1034 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1036 /* Map from zero to end of allocations under 2M pages */
1037 /* This replaces some of the KPTphys entries above */
1038 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1039 /* Preset PG_M and PG_A because demotion expects it. */
1040 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1041 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1044 * Because we map the physical blocks in 2M pages, adjust firstaddr
1045 * to record the physical blocks we've actually mapped into kernel
1046 * virtual address space.
1048 *firstaddr = round_2mpage(*firstaddr);
1050 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1051 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1052 for (i = 0; i < nkpdpe; i++)
1053 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1056 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1057 * the end of physical memory is not aligned to a 1GB page boundary,
1058 * then the residual physical memory is mapped with 2MB pages. Later,
1059 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1060 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1061 * that are partially used.
1063 pd_p = (pd_entry_t *)DMPDphys;
1064 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1065 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1066 /* Preset PG_M and PG_A because demotion expects it. */
1067 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1068 X86_PG_M | X86_PG_A | pg_nx;
1070 pdp_p = (pdp_entry_t *)DMPDPphys;
1071 for (i = 0; i < ndm1g; i++) {
1072 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1073 /* Preset PG_M and PG_A because demotion expects it. */
1074 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1075 X86_PG_M | X86_PG_A | pg_nx;
1077 for (j = 0; i < ndmpdp; i++, j++) {
1078 pdp_p[i] = DMPDphys + ptoa(j);
1079 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1083 * Instead of using a 1G page for the memory containing the kernel,
1084 * use 2M pages with appropriate permissions. (If using 1G pages,
1085 * this will partially overwrite the PDPEs above.)
1088 pd_p = (pd_entry_t *)DMPDkernphys;
1089 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1090 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1091 X86_PG_M | X86_PG_A | pg_nx |
1092 bootaddr_rwx(i << PDRSHIFT);
1093 for (i = 0; i < nkdmpde; i++)
1094 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1098 /* And recursively map PML4 to itself in order to get PTmap */
1099 p4_p = (pml4_entry_t *)KPML4phys;
1100 p4_p[PML4PML4I] = KPML4phys;
1101 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1103 /* Connect the Direct Map slot(s) up to the PML4. */
1104 for (i = 0; i < ndmpdpphys; i++) {
1105 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1106 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1109 /* Connect the KVA slots up to the PML4 */
1110 for (i = 0; i < NKPML4E; i++) {
1111 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1112 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1117 * Bootstrap the system enough to run with virtual memory.
1119 * On amd64 this is called after mapping has already been enabled
1120 * and just syncs the pmap module with what has already been done.
1121 * [We can't call it easily with mapping off since the kernel is not
1122 * mapped with PA == VA, hence we would have to relocate every address
1123 * from the linked base (virtual) address "KERNBASE" to the actual
1124 * (physical) address starting relative to 0]
1127 pmap_bootstrap(vm_paddr_t *firstaddr)
1135 KERNend = *firstaddr;
1136 res = atop(KERNend - (vm_paddr_t)kernphys);
1142 * Create an initial set of page tables to run the kernel in.
1144 create_pagetables(firstaddr);
1147 * Add a physical memory segment (vm_phys_seg) corresponding to the
1148 * preallocated kernel page table pages so that vm_page structures
1149 * representing these pages will be created. The vm_page structures
1150 * are required for promotion of the corresponding kernel virtual
1151 * addresses to superpage mappings.
1153 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1155 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1156 virtual_end = VM_MAX_KERNEL_ADDRESS;
1159 * Enable PG_G global pages, then switch to the kernel page
1160 * table from the bootstrap page table. After the switch, it
1161 * is possible to enable SMEP and SMAP since PG_U bits are
1167 load_cr3(KPML4phys);
1168 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1170 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1175 * Initialize the kernel pmap (which is statically allocated).
1176 * Count bootstrap data as being resident in case any of this data is
1177 * later unmapped (using pmap_remove()) and freed.
1179 PMAP_LOCK_INIT(kernel_pmap);
1180 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1181 kernel_pmap->pm_cr3 = KPML4phys;
1182 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1183 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1184 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1185 kernel_pmap->pm_stats.resident_count = res;
1186 kernel_pmap->pm_flags = pmap_flags;
1189 * Initialize the TLB invalidations generation number lock.
1191 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1194 * Reserve some special page table entries/VA space for temporary
1197 #define SYSMAP(c, p, v, n) \
1198 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1204 * Crashdump maps. The first page is reused as CMAP1 for the
1207 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1208 CADDR1 = crashdumpmap;
1213 * Initialize the PAT MSR.
1214 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1215 * side-effect, invalidates stale PG_G TLB entries that might
1216 * have been created in our pre-boot environment.
1220 /* Initialize TLB Context Id. */
1221 if (pmap_pcid_enabled) {
1222 for (i = 0; i < MAXCPU; i++) {
1223 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1224 kernel_pmap->pm_pcids[i].pm_gen = 1;
1228 * PMAP_PCID_KERN + 1 is used for initialization of
1229 * proc0 pmap. The pmap' pcid state might be used by
1230 * EFIRT entry before first context switch, so it
1231 * needs to be valid.
1233 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1234 PCPU_SET(pcid_gen, 1);
1237 * pcpu area for APs is zeroed during AP startup.
1238 * pc_pcid_next and pc_pcid_gen are initialized by AP
1239 * during pcpu setup.
1241 load_cr4(rcr4() | CR4_PCIDE);
1246 * Setup the PAT MSR.
1255 /* Bail if this CPU doesn't implement PAT. */
1256 if ((cpu_feature & CPUID_PAT) == 0)
1259 /* Set default PAT index table. */
1260 for (i = 0; i < PAT_INDEX_SIZE; i++)
1262 pat_index[PAT_WRITE_BACK] = 0;
1263 pat_index[PAT_WRITE_THROUGH] = 1;
1264 pat_index[PAT_UNCACHEABLE] = 3;
1265 pat_index[PAT_WRITE_COMBINING] = 6;
1266 pat_index[PAT_WRITE_PROTECTED] = 5;
1267 pat_index[PAT_UNCACHED] = 2;
1270 * Initialize default PAT entries.
1271 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1272 * Program 5 and 6 as WP and WC.
1274 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1275 * mapping for a 2M page uses a PAT value with the bit 3 set due
1276 * to its overload with PG_PS.
1278 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1279 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1280 PAT_VALUE(2, PAT_UNCACHED) |
1281 PAT_VALUE(3, PAT_UNCACHEABLE) |
1282 PAT_VALUE(4, PAT_WRITE_BACK) |
1283 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1284 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1285 PAT_VALUE(7, PAT_UNCACHEABLE);
1289 load_cr4(cr4 & ~CR4_PGE);
1291 /* Disable caches (CD = 1, NW = 0). */
1293 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1295 /* Flushes caches and TLBs. */
1299 /* Update PAT and index table. */
1300 wrmsr(MSR_PAT, pat_msr);
1302 /* Flush caches and TLBs again. */
1306 /* Restore caches and PGE. */
1312 * Initialize a vm_page's machine-dependent fields.
1315 pmap_page_init(vm_page_t m)
1318 TAILQ_INIT(&m->md.pv_list);
1319 m->md.pat_mode = PAT_WRITE_BACK;
1323 * Initialize the pmap module.
1324 * Called by vm_init, to initialize any structures that the pmap
1325 * system needs to map virtual memory.
1330 struct pmap_preinit_mapping *ppim;
1333 int error, i, pv_npg, ret, skz63;
1335 /* L1TF, reserve page @0 unconditionally */
1336 vm_page_blacklist_add(0, bootverbose);
1338 /* Detect bare-metal Skylake Server and Skylake-X. */
1339 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1340 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1342 * Skylake-X errata SKZ63. Processor May Hang When
1343 * Executing Code In an HLE Transaction Region between
1344 * 40000000H and 403FFFFFH.
1346 * Mark the pages in the range as preallocated. It
1347 * seems to be impossible to distinguish between
1348 * Skylake Server and Skylake X.
1351 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1354 printf("SKZ63: skipping 4M RAM starting "
1355 "at physical 1G\n");
1356 for (i = 0; i < atop(0x400000); i++) {
1357 ret = vm_page_blacklist_add(0x40000000 +
1359 if (!ret && bootverbose)
1360 printf("page at %#lx already used\n",
1361 0x40000000 + ptoa(i));
1367 * Initialize the vm page array entries for the kernel pmap's
1370 PMAP_LOCK(kernel_pmap);
1371 for (i = 0; i < nkpt; i++) {
1372 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1373 KASSERT(mpte >= vm_page_array &&
1374 mpte < &vm_page_array[vm_page_array_size],
1375 ("pmap_init: page table page is out of range"));
1376 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1377 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1378 mpte->wire_count = 1;
1379 if (i << PDRSHIFT < KERNend &&
1380 pmap_insert_pt_page(kernel_pmap, mpte))
1381 panic("pmap_init: pmap_insert_pt_page failed");
1383 PMAP_UNLOCK(kernel_pmap);
1387 * If the kernel is running on a virtual machine, then it must assume
1388 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1389 * be prepared for the hypervisor changing the vendor and family that
1390 * are reported by CPUID. Consequently, the workaround for AMD Family
1391 * 10h Erratum 383 is enabled if the processor's feature set does not
1392 * include at least one feature that is only supported by older Intel
1393 * or newer AMD processors.
1395 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1396 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1397 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1399 workaround_erratum383 = 1;
1402 * Are large page mappings enabled?
1404 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1405 if (pg_ps_enabled) {
1406 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1407 ("pmap_init: can't assign to pagesizes[1]"));
1408 pagesizes[1] = NBPDR;
1412 * Initialize the pv chunk list mutex.
1414 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1417 * Initialize the pool of pv list locks.
1419 for (i = 0; i < NPV_LIST_LOCKS; i++)
1420 rw_init(&pv_list_locks[i], "pmap pv list");
1423 * Calculate the size of the pv head table for superpages.
1425 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1428 * Allocate memory for the pv head table for superpages.
1430 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1432 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1433 for (i = 0; i < pv_npg; i++)
1434 TAILQ_INIT(&pv_table[i].pv_list);
1435 TAILQ_INIT(&pv_dummy.pv_list);
1437 pmap_initialized = 1;
1438 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1439 ppim = pmap_preinit_mapping + i;
1442 /* Make the direct map consistent */
1443 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1444 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1445 ppim->sz, ppim->mode);
1449 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1450 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1453 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1454 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1455 (vmem_addr_t *)&qframe);
1457 panic("qframe allocation failed");
1460 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1461 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1462 lm_ents = LMEPML4I - LMSPML4I + 1;
1464 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1465 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1467 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1468 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1469 if (large_vmem == NULL) {
1470 printf("pmap: cannot create large map\n");
1473 for (i = 0; i < lm_ents; i++) {
1474 m = pmap_large_map_getptp_unlocked();
1475 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1476 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1482 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1483 "2MB page mapping counters");
1485 static u_long pmap_pde_demotions;
1486 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1487 &pmap_pde_demotions, 0, "2MB page demotions");
1489 static u_long pmap_pde_mappings;
1490 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1491 &pmap_pde_mappings, 0, "2MB page mappings");
1493 static u_long pmap_pde_p_failures;
1494 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1495 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1497 static u_long pmap_pde_promotions;
1498 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1499 &pmap_pde_promotions, 0, "2MB page promotions");
1501 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1502 "1GB page mapping counters");
1504 static u_long pmap_pdpe_demotions;
1505 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1506 &pmap_pdpe_demotions, 0, "1GB page demotions");
1508 /***************************************************
1509 * Low level helper routines.....
1510 ***************************************************/
1513 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1515 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1517 switch (pmap->pm_type) {
1520 /* Verify that both PAT bits are not set at the same time */
1521 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1522 ("Invalid PAT bits in entry %#lx", entry));
1524 /* Swap the PAT bits if one of them is set */
1525 if ((entry & x86_pat_bits) != 0)
1526 entry ^= x86_pat_bits;
1530 * Nothing to do - the memory attributes are represented
1531 * the same way for regular pages and superpages.
1535 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1542 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1545 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1546 pat_index[(int)mode] >= 0);
1550 * Determine the appropriate bits to set in a PTE or PDE for a specified
1554 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1556 int cache_bits, pat_flag, pat_idx;
1558 if (!pmap_is_valid_memattr(pmap, mode))
1559 panic("Unknown caching mode %d\n", mode);
1561 switch (pmap->pm_type) {
1564 /* The PAT bit is different for PTE's and PDE's. */
1565 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1567 /* Map the caching mode to a PAT index. */
1568 pat_idx = pat_index[mode];
1570 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1573 cache_bits |= pat_flag;
1575 cache_bits |= PG_NC_PCD;
1577 cache_bits |= PG_NC_PWT;
1581 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1585 panic("unsupported pmap type %d", pmap->pm_type);
1588 return (cache_bits);
1592 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1596 switch (pmap->pm_type) {
1599 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1602 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1605 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1612 pmap_ps_enabled(pmap_t pmap)
1615 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1619 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1622 switch (pmap->pm_type) {
1629 * This is a little bogus since the generation number is
1630 * supposed to be bumped up when a region of the address
1631 * space is invalidated in the page tables.
1633 * In this case the old PDE entry is valid but yet we want
1634 * to make sure that any mappings using the old entry are
1635 * invalidated in the TLB.
1637 * The reason this works as expected is because we rendezvous
1638 * "all" host cpus and force any vcpu context to exit as a
1641 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1644 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1646 pde_store(pde, newpde);
1650 * After changing the page size for the specified virtual address in the page
1651 * table, flush the corresponding entries from the processor's TLB. Only the
1652 * calling processor's TLB is affected.
1654 * The calling thread must be pinned to a processor.
1657 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1661 if (pmap_type_guest(pmap))
1664 KASSERT(pmap->pm_type == PT_X86,
1665 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1667 PG_G = pmap_global_bit(pmap);
1669 if ((newpde & PG_PS) == 0)
1670 /* Demotion: flush a specific 2MB page mapping. */
1672 else if ((newpde & PG_G) == 0)
1674 * Promotion: flush every 4KB page mapping from the TLB
1675 * because there are too many to flush individually.
1680 * Promotion: flush every 4KB page mapping from the TLB,
1681 * including any global (PG_G) mappings.
1689 * For SMP, these functions have to use the IPI mechanism for coherence.
1691 * N.B.: Before calling any of the following TLB invalidation functions,
1692 * the calling processor must ensure that all stores updating a non-
1693 * kernel page table are globally performed. Otherwise, another
1694 * processor could cache an old, pre-update entry without being
1695 * invalidated. This can happen one of two ways: (1) The pmap becomes
1696 * active on another processor after its pm_active field is checked by
1697 * one of the following functions but before a store updating the page
1698 * table is globally performed. (2) The pmap becomes active on another
1699 * processor before its pm_active field is checked but due to
1700 * speculative loads one of the following functions stills reads the
1701 * pmap as inactive on the other processor.
1703 * The kernel page table is exempt because its pm_active field is
1704 * immutable. The kernel page table is always active on every
1709 * Interrupt the cpus that are executing in the guest context.
1710 * This will force the vcpu to exit and the cached EPT mappings
1711 * will be invalidated by the host before the next vmresume.
1713 static __inline void
1714 pmap_invalidate_ept(pmap_t pmap)
1719 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1720 ("pmap_invalidate_ept: absurd pm_active"));
1723 * The TLB mappings associated with a vcpu context are not
1724 * flushed each time a different vcpu is chosen to execute.
1726 * This is in contrast with a process's vtop mappings that
1727 * are flushed from the TLB on each context switch.
1729 * Therefore we need to do more than just a TLB shootdown on
1730 * the active cpus in 'pmap->pm_active'. To do this we keep
1731 * track of the number of invalidations performed on this pmap.
1733 * Each vcpu keeps a cache of this counter and compares it
1734 * just before a vmresume. If the counter is out-of-date an
1735 * invept will be done to flush stale mappings from the TLB.
1737 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1740 * Force the vcpu to exit and trap back into the hypervisor.
1742 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1743 ipi_selected(pmap->pm_active, ipinum);
1748 pmap_invalidate_cpu_mask(pmap_t pmap)
1751 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
1755 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
1756 const bool invpcid_works1)
1758 struct invpcid_descr d;
1759 uint64_t kcr3, ucr3;
1763 cpuid = PCPU_GET(cpuid);
1764 if (pmap == PCPU_GET(curpmap)) {
1765 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1767 * Because pm_pcid is recalculated on a
1768 * context switch, we must disable switching.
1769 * Otherwise, we might use a stale value
1773 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1774 if (invpcid_works1) {
1775 d.pcid = pcid | PMAP_PCID_USER_PT;
1778 invpcid(&d, INVPCID_ADDR);
1780 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
1781 ucr3 = pmap->pm_ucr3 | pcid |
1782 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1783 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1788 pmap->pm_pcids[cpuid].pm_gen = 0;
1792 pmap->pm_pcids[i].pm_gen = 0;
1796 * The fence is between stores to pm_gen and the read of the
1797 * pm_active mask. We need to ensure that it is impossible
1798 * for us to miss the bit update in pm_active and
1799 * simultaneously observe a non-zero pm_gen in
1800 * pmap_activate_sw(), otherwise TLB update is missed.
1801 * Without the fence, IA32 allows such an outcome. Note that
1802 * pm_active is updated by a locked operation, which provides
1803 * the reciprocal fence.
1805 atomic_thread_fence_seq_cst();
1809 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
1812 pmap_invalidate_page_pcid(pmap, va, true);
1816 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
1819 pmap_invalidate_page_pcid(pmap, va, false);
1823 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
1827 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t),
1831 if (pmap_pcid_enabled)
1832 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
1833 pmap_invalidate_page_pcid_noinvpcid);
1834 return (pmap_invalidate_page_nopcid);
1838 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1841 if (pmap_type_guest(pmap)) {
1842 pmap_invalidate_ept(pmap);
1846 KASSERT(pmap->pm_type == PT_X86,
1847 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1850 if (pmap == kernel_pmap) {
1853 if (pmap == PCPU_GET(curpmap))
1855 pmap_invalidate_page_mode(pmap, va);
1857 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
1861 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1862 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1865 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1866 const bool invpcid_works1)
1868 struct invpcid_descr d;
1869 uint64_t kcr3, ucr3;
1873 cpuid = PCPU_GET(cpuid);
1874 if (pmap == PCPU_GET(curpmap)) {
1875 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1877 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1878 if (invpcid_works1) {
1879 d.pcid = pcid | PMAP_PCID_USER_PT;
1882 for (; d.addr < eva; d.addr += PAGE_SIZE)
1883 invpcid(&d, INVPCID_ADDR);
1885 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
1886 ucr3 = pmap->pm_ucr3 | pcid |
1887 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1888 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
1893 pmap->pm_pcids[cpuid].pm_gen = 0;
1897 pmap->pm_pcids[i].pm_gen = 0;
1899 /* See the comment in pmap_invalidate_page_pcid(). */
1900 atomic_thread_fence_seq_cst();
1904 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
1908 pmap_invalidate_range_pcid(pmap, sva, eva, true);
1912 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
1916 pmap_invalidate_range_pcid(pmap, sva, eva, false);
1920 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1924 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
1925 vm_offset_t), static)
1928 if (pmap_pcid_enabled)
1929 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
1930 pmap_invalidate_range_pcid_noinvpcid);
1931 return (pmap_invalidate_range_nopcid);
1935 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1939 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1940 pmap_invalidate_all(pmap);
1944 if (pmap_type_guest(pmap)) {
1945 pmap_invalidate_ept(pmap);
1949 KASSERT(pmap->pm_type == PT_X86,
1950 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1953 if (pmap == kernel_pmap) {
1954 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1957 if (pmap == PCPU_GET(curpmap)) {
1958 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1961 pmap_invalidate_range_mode(pmap, sva, eva);
1963 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
1968 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
1970 struct invpcid_descr d;
1971 uint64_t kcr3, ucr3;
1975 if (pmap == kernel_pmap) {
1976 if (invpcid_works1) {
1977 bzero(&d, sizeof(d));
1978 invpcid(&d, INVPCID_CTXGLOB);
1983 cpuid = PCPU_GET(cpuid);
1984 if (pmap == PCPU_GET(curpmap)) {
1986 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1987 if (invpcid_works1) {
1991 invpcid(&d, INVPCID_CTX);
1992 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1993 d.pcid |= PMAP_PCID_USER_PT;
1994 invpcid(&d, INVPCID_CTX);
1997 kcr3 = pmap->pm_cr3 | pcid;
1998 ucr3 = pmap->pm_ucr3;
1999 if (ucr3 != PMAP_NO_CR3) {
2000 ucr3 |= pcid | PMAP_PCID_USER_PT;
2001 pmap_pti_pcid_invalidate(ucr3, kcr3);
2008 pmap->pm_pcids[cpuid].pm_gen = 0;
2011 pmap->pm_pcids[i].pm_gen = 0;
2014 /* See the comment in pmap_invalidate_page_pcid(). */
2015 atomic_thread_fence_seq_cst();
2019 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2022 pmap_invalidate_all_pcid(pmap, true);
2026 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2029 pmap_invalidate_all_pcid(pmap, false);
2033 pmap_invalidate_all_nopcid(pmap_t pmap)
2036 if (pmap == kernel_pmap)
2038 else if (pmap == PCPU_GET(curpmap))
2042 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t), static)
2045 if (pmap_pcid_enabled)
2046 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2047 pmap_invalidate_all_pcid_noinvpcid);
2048 return (pmap_invalidate_all_nopcid);
2052 pmap_invalidate_all(pmap_t pmap)
2055 if (pmap_type_guest(pmap)) {
2056 pmap_invalidate_ept(pmap);
2060 KASSERT(pmap->pm_type == PT_X86,
2061 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2064 pmap_invalidate_all_mode(pmap);
2065 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2070 pmap_invalidate_cache(void)
2080 cpuset_t invalidate; /* processors that invalidate their TLB */
2085 u_int store; /* processor that updates the PDE */
2089 pmap_update_pde_action(void *arg)
2091 struct pde_action *act = arg;
2093 if (act->store == PCPU_GET(cpuid))
2094 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2098 pmap_update_pde_teardown(void *arg)
2100 struct pde_action *act = arg;
2102 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2103 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2107 * Change the page size for the specified virtual address in a way that
2108 * prevents any possibility of the TLB ever having two entries that map the
2109 * same virtual address using different page sizes. This is the recommended
2110 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2111 * machine check exception for a TLB state that is improperly diagnosed as a
2115 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2117 struct pde_action act;
2118 cpuset_t active, other_cpus;
2122 cpuid = PCPU_GET(cpuid);
2123 other_cpus = all_cpus;
2124 CPU_CLR(cpuid, &other_cpus);
2125 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2128 active = pmap->pm_active;
2130 if (CPU_OVERLAP(&active, &other_cpus)) {
2132 act.invalidate = active;
2136 act.newpde = newpde;
2137 CPU_SET(cpuid, &active);
2138 smp_rendezvous_cpus(active,
2139 smp_no_rendezvous_barrier, pmap_update_pde_action,
2140 pmap_update_pde_teardown, &act);
2142 pmap_update_pde_store(pmap, pde, newpde);
2143 if (CPU_ISSET(cpuid, &active))
2144 pmap_update_pde_invalidate(pmap, va, newpde);
2150 * Normal, non-SMP, invalidation functions.
2153 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2155 struct invpcid_descr d;
2156 uint64_t kcr3, ucr3;
2159 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2163 KASSERT(pmap->pm_type == PT_X86,
2164 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2166 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2168 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2169 pmap->pm_ucr3 != PMAP_NO_CR3) {
2171 pcid = pmap->pm_pcids[0].pm_pcid;
2172 if (invpcid_works) {
2173 d.pcid = pcid | PMAP_PCID_USER_PT;
2176 invpcid(&d, INVPCID_ADDR);
2178 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2179 ucr3 = pmap->pm_ucr3 | pcid |
2180 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2181 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2185 } else if (pmap_pcid_enabled)
2186 pmap->pm_pcids[0].pm_gen = 0;
2190 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2192 struct invpcid_descr d;
2194 uint64_t kcr3, ucr3;
2196 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2200 KASSERT(pmap->pm_type == PT_X86,
2201 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2203 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2204 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2206 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2207 pmap->pm_ucr3 != PMAP_NO_CR3) {
2209 if (invpcid_works) {
2210 d.pcid = pmap->pm_pcids[0].pm_pcid |
2214 for (; d.addr < eva; d.addr += PAGE_SIZE)
2215 invpcid(&d, INVPCID_ADDR);
2217 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2218 pm_pcid | CR3_PCID_SAVE;
2219 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2220 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2221 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2225 } else if (pmap_pcid_enabled) {
2226 pmap->pm_pcids[0].pm_gen = 0;
2231 pmap_invalidate_all(pmap_t pmap)
2233 struct invpcid_descr d;
2234 uint64_t kcr3, ucr3;
2236 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2240 KASSERT(pmap->pm_type == PT_X86,
2241 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2243 if (pmap == kernel_pmap) {
2244 if (pmap_pcid_enabled && invpcid_works) {
2245 bzero(&d, sizeof(d));
2246 invpcid(&d, INVPCID_CTXGLOB);
2250 } else if (pmap == PCPU_GET(curpmap)) {
2251 if (pmap_pcid_enabled) {
2253 if (invpcid_works) {
2254 d.pcid = pmap->pm_pcids[0].pm_pcid;
2257 invpcid(&d, INVPCID_CTX);
2258 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2259 d.pcid |= PMAP_PCID_USER_PT;
2260 invpcid(&d, INVPCID_CTX);
2263 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2264 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2265 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2266 0].pm_pcid | PMAP_PCID_USER_PT;
2267 pmap_pti_pcid_invalidate(ucr3, kcr3);
2275 } else if (pmap_pcid_enabled) {
2276 pmap->pm_pcids[0].pm_gen = 0;
2281 pmap_invalidate_cache(void)
2288 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2291 pmap_update_pde_store(pmap, pde, newpde);
2292 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2293 pmap_update_pde_invalidate(pmap, va, newpde);
2295 pmap->pm_pcids[0].pm_gen = 0;
2300 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2304 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2305 * by a promotion that did not invalidate the 512 4KB page mappings
2306 * that might exist in the TLB. Consequently, at this point, the TLB
2307 * may hold both 4KB and 2MB page mappings for the address range [va,
2308 * va + NBPDR). Therefore, the entire range must be invalidated here.
2309 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2310 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2311 * single INVLPG suffices to invalidate the 2MB page mapping from the
2314 if ((pde & PG_PROMOTED) != 0)
2315 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2317 pmap_invalidate_page(pmap, va);
2320 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2321 (vm_offset_t sva, vm_offset_t eva), static)
2324 if ((cpu_feature & CPUID_SS) != 0)
2325 return (pmap_invalidate_cache_range_selfsnoop);
2326 if ((cpu_feature & CPUID_CLFSH) != 0)
2327 return (pmap_force_invalidate_cache_range);
2328 return (pmap_invalidate_cache_range_all);
2331 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2334 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2337 KASSERT((sva & PAGE_MASK) == 0,
2338 ("pmap_invalidate_cache_range: sva not page-aligned"));
2339 KASSERT((eva & PAGE_MASK) == 0,
2340 ("pmap_invalidate_cache_range: eva not page-aligned"));
2344 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2347 pmap_invalidate_cache_range_check_align(sva, eva);
2351 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2354 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2357 * XXX: Some CPUs fault, hang, or trash the local APIC
2358 * registers if we use CLFLUSH on the local APIC range. The
2359 * local APIC is always uncached, so we don't need to flush
2360 * for that range anyway.
2362 if (pmap_kextract(sva) == lapic_paddr)
2365 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2367 * Do per-cache line flush. Use the sfence
2368 * instruction to insure that previous stores are
2369 * included in the write-back. The processor
2370 * propagates flush to other processors in the cache
2374 for (; sva < eva; sva += cpu_clflush_line_size)
2379 * Writes are ordered by CLFLUSH on Intel CPUs.
2381 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2383 for (; sva < eva; sva += cpu_clflush_line_size)
2385 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2391 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2394 pmap_invalidate_cache_range_check_align(sva, eva);
2395 pmap_invalidate_cache();
2399 * Remove the specified set of pages from the data and instruction caches.
2401 * In contrast to pmap_invalidate_cache_range(), this function does not
2402 * rely on the CPU's self-snoop feature, because it is intended for use
2403 * when moving pages into a different cache domain.
2406 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2408 vm_offset_t daddr, eva;
2412 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2413 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2414 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2415 pmap_invalidate_cache();
2419 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2421 for (i = 0; i < count; i++) {
2422 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2423 eva = daddr + PAGE_SIZE;
2424 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2433 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2439 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2442 pmap_invalidate_cache_range_check_align(sva, eva);
2444 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2445 pmap_force_invalidate_cache_range(sva, eva);
2449 /* See comment in pmap_force_invalidate_cache_range(). */
2450 if (pmap_kextract(sva) == lapic_paddr)
2454 for (; sva < eva; sva += cpu_clflush_line_size)
2460 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2464 int error, pte_bits;
2466 KASSERT((spa & PAGE_MASK) == 0,
2467 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2468 KASSERT((epa & PAGE_MASK) == 0,
2469 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2471 if (spa < dmaplimit) {
2472 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2474 if (dmaplimit >= epa)
2479 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
2481 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2483 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
2484 pte = vtopte(vaddr);
2485 for (; spa < epa; spa += PAGE_SIZE) {
2487 pte_store(pte, spa | pte_bits);
2489 /* XXXKIB sfences inside flush_cache_range are excessive */
2490 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
2493 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
2497 * Routine: pmap_extract
2499 * Extract the physical page address associated
2500 * with the given map/virtual_address pair.
2503 pmap_extract(pmap_t pmap, vm_offset_t va)
2507 pt_entry_t *pte, PG_V;
2511 PG_V = pmap_valid_bit(pmap);
2513 pdpe = pmap_pdpe(pmap, va);
2514 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2515 if ((*pdpe & PG_PS) != 0)
2516 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2518 pde = pmap_pdpe_to_pde(pdpe, va);
2519 if ((*pde & PG_V) != 0) {
2520 if ((*pde & PG_PS) != 0) {
2521 pa = (*pde & PG_PS_FRAME) |
2524 pte = pmap_pde_to_pte(pde, va);
2525 pa = (*pte & PG_FRAME) |
2536 * Routine: pmap_extract_and_hold
2538 * Atomically extract and hold the physical page
2539 * with the given pmap and virtual address pair
2540 * if that mapping permits the given protection.
2543 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2545 pd_entry_t pde, *pdep;
2546 pt_entry_t pte, PG_RW, PG_V;
2552 PG_RW = pmap_rw_bit(pmap);
2553 PG_V = pmap_valid_bit(pmap);
2556 pdep = pmap_pde(pmap, va);
2557 if (pdep != NULL && (pde = *pdep)) {
2559 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2560 if (vm_page_pa_tryrelock(pmap, (pde &
2561 PG_PS_FRAME) | (va & PDRMASK), &pa))
2563 m = PHYS_TO_VM_PAGE(pa);
2566 pte = *pmap_pde_to_pte(pdep, va);
2568 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2569 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2572 m = PHYS_TO_VM_PAGE(pa);
2584 pmap_kextract(vm_offset_t va)
2589 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2590 pa = DMAP_TO_PHYS(va);
2594 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2597 * Beware of a concurrent promotion that changes the
2598 * PDE at this point! For example, vtopte() must not
2599 * be used to access the PTE because it would use the
2600 * new PDE. It is, however, safe to use the old PDE
2601 * because the page table page is preserved by the
2604 pa = *pmap_pde_to_pte(&pde, va);
2605 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2611 /***************************************************
2612 * Low level mapping routines.....
2613 ***************************************************/
2616 * Add a wired page to the kva.
2617 * Note: not SMP coherent.
2620 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2625 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2628 static __inline void
2629 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2635 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2636 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2640 * Remove a page from the kernel pagetables.
2641 * Note: not SMP coherent.
2644 pmap_kremove(vm_offset_t va)
2653 * Used to map a range of physical addresses into kernel
2654 * virtual address space.
2656 * The value passed in '*virt' is a suggested virtual address for
2657 * the mapping. Architectures which can support a direct-mapped
2658 * physical to virtual region can return the appropriate address
2659 * within that region, leaving '*virt' unchanged. Other
2660 * architectures should map the pages starting at '*virt' and
2661 * update '*virt' with the first usable address after the mapped
2665 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2667 return PHYS_TO_DMAP(start);
2672 * Add a list of wired pages to the kva
2673 * this routine is only used for temporary
2674 * kernel mappings that do not need to have
2675 * page modification or references recorded.
2676 * Note that old mappings are simply written
2677 * over. The page *must* be wired.
2678 * Note: SMP coherent. Uses a ranged shootdown IPI.
2681 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2683 pt_entry_t *endpte, oldpte, pa, *pte;
2689 endpte = pte + count;
2690 while (pte < endpte) {
2692 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2693 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2694 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2696 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2700 if (__predict_false((oldpte & X86_PG_V) != 0))
2701 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2706 * This routine tears out page mappings from the
2707 * kernel -- it is meant only for temporary mappings.
2708 * Note: SMP coherent. Uses a ranged shootdown IPI.
2711 pmap_qremove(vm_offset_t sva, int count)
2716 while (count-- > 0) {
2717 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2721 pmap_invalidate_range(kernel_pmap, sva, va);
2724 /***************************************************
2725 * Page table page management routines.....
2726 ***************************************************/
2728 * Schedule the specified unused page table page to be freed. Specifically,
2729 * add the page to the specified list of pages that will be released to the
2730 * physical memory manager after the TLB has been updated.
2732 static __inline void
2733 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2734 boolean_t set_PG_ZERO)
2738 m->flags |= PG_ZERO;
2740 m->flags &= ~PG_ZERO;
2741 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2745 * Inserts the specified page table page into the specified pmap's collection
2746 * of idle page table pages. Each of a pmap's page table pages is responsible
2747 * for mapping a distinct range of virtual addresses. The pmap's collection is
2748 * ordered by this virtual address range.
2751 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2754 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2755 return (vm_radix_insert(&pmap->pm_root, mpte));
2759 * Removes the page table page mapping the specified virtual address from the
2760 * specified pmap's collection of idle page table pages, and returns it.
2761 * Otherwise, returns NULL if there is no page table page corresponding to the
2762 * specified virtual address.
2764 static __inline vm_page_t
2765 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2768 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2769 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2773 * Decrements a page table page's wire count, which is used to record the
2774 * number of valid page table entries within the page. If the wire count
2775 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2776 * page table page was unmapped and FALSE otherwise.
2778 static inline boolean_t
2779 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2783 if (m->wire_count == 0) {
2784 _pmap_unwire_ptp(pmap, va, m, free);
2791 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2794 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2796 * unmap the page table page
2798 if (m->pindex >= (NUPDE + NUPDPE)) {
2801 pml4 = pmap_pml4e(pmap, va);
2803 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2804 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2807 } else if (m->pindex >= NUPDE) {
2810 pdp = pmap_pdpe(pmap, va);
2815 pd = pmap_pde(pmap, va);
2818 pmap_resident_count_dec(pmap, 1);
2819 if (m->pindex < NUPDE) {
2820 /* We just released a PT, unhold the matching PD */
2823 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2824 pmap_unwire_ptp(pmap, va, pdpg, free);
2826 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2827 /* We just released a PD, unhold the matching PDP */
2830 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2831 pmap_unwire_ptp(pmap, va, pdppg, free);
2835 * Put page on a list so that it is released after
2836 * *ALL* TLB shootdown is done
2838 pmap_add_delayed_free_list(m, free, TRUE);
2842 * After removing a page table entry, this routine is used to
2843 * conditionally free the page, and manage the hold/wire counts.
2846 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2847 struct spglist *free)
2851 if (va >= VM_MAXUSER_ADDRESS)
2853 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2854 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2855 return (pmap_unwire_ptp(pmap, va, mpte, free));
2859 pmap_pinit0(pmap_t pmap)
2864 PMAP_LOCK_INIT(pmap);
2865 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2866 pmap->pm_pml4u = NULL;
2867 pmap->pm_cr3 = KPML4phys;
2868 /* hack to keep pmap_pti_pcid_invalidate() alive */
2869 pmap->pm_ucr3 = PMAP_NO_CR3;
2870 pmap->pm_root.rt_root = 0;
2871 CPU_ZERO(&pmap->pm_active);
2872 TAILQ_INIT(&pmap->pm_pvchunk);
2873 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2874 pmap->pm_flags = pmap_flags;
2876 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
2877 pmap->pm_pcids[i].pm_gen = 1;
2879 pmap_activate_boot(pmap);
2883 p->p_amd64_md_flags |= P_MD_KPTI;
2887 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
2888 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
2889 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
2895 pmap_pinit_pml4(vm_page_t pml4pg)
2897 pml4_entry_t *pm_pml4;
2900 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2902 /* Wire in kernel global address entries. */
2903 for (i = 0; i < NKPML4E; i++) {
2904 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2907 for (i = 0; i < ndmpdpphys; i++) {
2908 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2912 /* install self-referential address mapping entry(s) */
2913 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2914 X86_PG_A | X86_PG_M;
2916 /* install large map entries if configured */
2917 for (i = 0; i < lm_ents; i++)
2918 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
2922 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2924 pml4_entry_t *pm_pml4;
2927 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2928 for (i = 0; i < NPML4EPG; i++)
2929 pm_pml4[i] = pti_pml4[i];
2933 * Initialize a preallocated and zeroed pmap structure,
2934 * such as one in a vmspace structure.
2937 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2939 vm_page_t pml4pg, pml4pgu;
2940 vm_paddr_t pml4phys;
2944 * allocate the page directory page
2946 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2947 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2949 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2950 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2952 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2953 pmap->pm_pcids[i].pm_gen = 0;
2955 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2956 pmap->pm_ucr3 = PMAP_NO_CR3;
2957 pmap->pm_pml4u = NULL;
2959 pmap->pm_type = pm_type;
2960 if ((pml4pg->flags & PG_ZERO) == 0)
2961 pagezero(pmap->pm_pml4);
2964 * Do not install the host kernel mappings in the nested page
2965 * tables. These mappings are meaningless in the guest physical
2967 * Install minimal kernel mappings in PTI case.
2969 if (pm_type == PT_X86) {
2970 pmap->pm_cr3 = pml4phys;
2971 pmap_pinit_pml4(pml4pg);
2972 if ((curproc->p_amd64_md_flags & P_MD_KPTI) != 0) {
2973 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2974 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2975 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2976 VM_PAGE_TO_PHYS(pml4pgu));
2977 pmap_pinit_pml4_pti(pml4pgu);
2978 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2980 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
2981 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
2982 pkru_free_range, pmap, M_NOWAIT);
2986 pmap->pm_root.rt_root = 0;
2987 CPU_ZERO(&pmap->pm_active);
2988 TAILQ_INIT(&pmap->pm_pvchunk);
2989 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2990 pmap->pm_flags = flags;
2991 pmap->pm_eptgen = 0;
2997 pmap_pinit(pmap_t pmap)
3000 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3004 * This routine is called if the desired page table page does not exist.
3006 * If page table page allocation fails, this routine may sleep before
3007 * returning NULL. It sleeps only if a lock pointer was given.
3009 * Note: If a page allocation fails at page table level two or three,
3010 * one or two pages may be held during the wait, only to be released
3011 * afterwards. This conservative approach is easily argued to avoid
3015 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3017 vm_page_t m, pdppg, pdpg;
3018 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3020 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3022 PG_A = pmap_accessed_bit(pmap);
3023 PG_M = pmap_modified_bit(pmap);
3024 PG_V = pmap_valid_bit(pmap);
3025 PG_RW = pmap_rw_bit(pmap);
3028 * Allocate a page table page.
3030 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3031 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3032 if (lockp != NULL) {
3033 RELEASE_PV_LIST_LOCK(lockp);
3035 PMAP_ASSERT_NOT_IN_DI();
3041 * Indicate the need to retry. While waiting, the page table
3042 * page may have been allocated.
3046 if ((m->flags & PG_ZERO) == 0)
3050 * Map the pagetable page into the process address space, if
3051 * it isn't already there.
3054 if (ptepindex >= (NUPDE + NUPDPE)) {
3055 pml4_entry_t *pml4, *pml4u;
3056 vm_pindex_t pml4index;
3058 /* Wire up a new PDPE page */
3059 pml4index = ptepindex - (NUPDE + NUPDPE);
3060 pml4 = &pmap->pm_pml4[pml4index];
3061 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3062 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3064 * PTI: Make all user-space mappings in the
3065 * kernel-mode page table no-execute so that
3066 * we detect any programming errors that leave
3067 * the kernel-mode page table active on return
3070 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3073 pml4u = &pmap->pm_pml4u[pml4index];
3074 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3078 } else if (ptepindex >= NUPDE) {
3079 vm_pindex_t pml4index;
3080 vm_pindex_t pdpindex;
3084 /* Wire up a new PDE page */
3085 pdpindex = ptepindex - NUPDE;
3086 pml4index = pdpindex >> NPML4EPGSHIFT;
3088 pml4 = &pmap->pm_pml4[pml4index];
3089 if ((*pml4 & PG_V) == 0) {
3090 /* Have to allocate a new pdp, recurse */
3091 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3093 vm_page_unwire_noq(m);
3094 vm_page_free_zero(m);
3098 /* Add reference to pdp page */
3099 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3100 pdppg->wire_count++;
3102 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3104 /* Now find the pdp page */
3105 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3106 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3109 vm_pindex_t pml4index;
3110 vm_pindex_t pdpindex;
3115 /* Wire up a new PTE page */
3116 pdpindex = ptepindex >> NPDPEPGSHIFT;
3117 pml4index = pdpindex >> NPML4EPGSHIFT;
3119 /* First, find the pdp and check that its valid. */
3120 pml4 = &pmap->pm_pml4[pml4index];
3121 if ((*pml4 & PG_V) == 0) {
3122 /* Have to allocate a new pd, recurse */
3123 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3125 vm_page_unwire_noq(m);
3126 vm_page_free_zero(m);
3129 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3130 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3132 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3133 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3134 if ((*pdp & PG_V) == 0) {
3135 /* Have to allocate a new pd, recurse */
3136 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3138 vm_page_unwire_noq(m);
3139 vm_page_free_zero(m);
3143 /* Add reference to the pd page */
3144 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3148 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3150 /* Now we know where the page directory page is */
3151 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3152 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3155 pmap_resident_count_inc(pmap, 1);
3161 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3163 vm_pindex_t pdpindex, ptepindex;
3164 pdp_entry_t *pdpe, PG_V;
3167 PG_V = pmap_valid_bit(pmap);
3170 pdpe = pmap_pdpe(pmap, va);
3171 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3172 /* Add a reference to the pd page. */
3173 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3176 /* Allocate a pd page. */
3177 ptepindex = pmap_pde_pindex(va);
3178 pdpindex = ptepindex >> NPDPEPGSHIFT;
3179 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3180 if (pdpg == NULL && lockp != NULL)
3187 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3189 vm_pindex_t ptepindex;
3190 pd_entry_t *pd, PG_V;
3193 PG_V = pmap_valid_bit(pmap);
3196 * Calculate pagetable page index
3198 ptepindex = pmap_pde_pindex(va);
3201 * Get the page directory entry
3203 pd = pmap_pde(pmap, va);
3206 * This supports switching from a 2MB page to a
3209 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3210 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3212 * Invalidation of the 2MB page mapping may have caused
3213 * the deallocation of the underlying PD page.
3220 * If the page table page is mapped, we just increment the
3221 * hold count, and activate it.
3223 if (pd != NULL && (*pd & PG_V) != 0) {
3224 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3228 * Here if the pte page isn't mapped, or if it has been
3231 m = _pmap_allocpte(pmap, ptepindex, lockp);
3232 if (m == NULL && lockp != NULL)
3239 /***************************************************
3240 * Pmap allocation/deallocation routines.
3241 ***************************************************/
3244 * Release any resources held by the given physical map.
3245 * Called when a pmap initialized by pmap_pinit is being released.
3246 * Should only be called if the map contains no valid mappings.
3249 pmap_release(pmap_t pmap)
3254 KASSERT(pmap->pm_stats.resident_count == 0,
3255 ("pmap_release: pmap resident count %ld != 0",
3256 pmap->pm_stats.resident_count));
3257 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3258 ("pmap_release: pmap has reserved page table page(s)"));
3259 KASSERT(CPU_EMPTY(&pmap->pm_active),
3260 ("releasing active pmap %p", pmap));
3262 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3264 for (i = 0; i < NKPML4E; i++) /* KVA */
3265 pmap->pm_pml4[KPML4BASE + i] = 0;
3266 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3267 pmap->pm_pml4[DMPML4I + i] = 0;
3268 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3269 for (i = 0; i < lm_ents; i++) /* Large Map */
3270 pmap->pm_pml4[LMSPML4I + i] = 0;
3272 vm_page_unwire_noq(m);
3273 vm_page_free_zero(m);
3275 if (pmap->pm_pml4u != NULL) {
3276 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3277 vm_page_unwire_noq(m);
3280 if (pmap->pm_type == PT_X86 &&
3281 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3282 rangeset_fini(&pmap->pm_pkru);
3286 kvm_size(SYSCTL_HANDLER_ARGS)
3288 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3290 return sysctl_handle_long(oidp, &ksize, 0, req);
3292 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3293 0, 0, kvm_size, "LU", "Size of KVM");
3296 kvm_free(SYSCTL_HANDLER_ARGS)
3298 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3300 return sysctl_handle_long(oidp, &kfree, 0, req);
3302 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3303 0, 0, kvm_free, "LU", "Amount of KVM free");
3306 * grow the number of kernel page table entries, if needed
3309 pmap_growkernel(vm_offset_t addr)
3313 pd_entry_t *pde, newpdir;
3316 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3319 * Return if "addr" is within the range of kernel page table pages
3320 * that were preallocated during pmap bootstrap. Moreover, leave
3321 * "kernel_vm_end" and the kernel page table as they were.
3323 * The correctness of this action is based on the following
3324 * argument: vm_map_insert() allocates contiguous ranges of the
3325 * kernel virtual address space. It calls this function if a range
3326 * ends after "kernel_vm_end". If the kernel is mapped between
3327 * "kernel_vm_end" and "addr", then the range cannot begin at
3328 * "kernel_vm_end". In fact, its beginning address cannot be less
3329 * than the kernel. Thus, there is no immediate need to allocate
3330 * any new kernel page table pages between "kernel_vm_end" and
3333 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3336 addr = roundup2(addr, NBPDR);
3337 if (addr - 1 >= vm_map_max(kernel_map))
3338 addr = vm_map_max(kernel_map);
3339 while (kernel_vm_end < addr) {
3340 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3341 if ((*pdpe & X86_PG_V) == 0) {
3342 /* We need a new PDP entry */
3343 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3344 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3345 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3347 panic("pmap_growkernel: no memory to grow kernel");
3348 if ((nkpg->flags & PG_ZERO) == 0)
3349 pmap_zero_page(nkpg);
3350 paddr = VM_PAGE_TO_PHYS(nkpg);
3351 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3352 X86_PG_A | X86_PG_M);
3353 continue; /* try again */
3355 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3356 if ((*pde & X86_PG_V) != 0) {
3357 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3358 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3359 kernel_vm_end = vm_map_max(kernel_map);
3365 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3366 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3369 panic("pmap_growkernel: no memory to grow kernel");
3370 if ((nkpg->flags & PG_ZERO) == 0)
3371 pmap_zero_page(nkpg);
3372 paddr = VM_PAGE_TO_PHYS(nkpg);
3373 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3374 pde_store(pde, newpdir);
3376 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3377 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3378 kernel_vm_end = vm_map_max(kernel_map);
3385 /***************************************************
3386 * page management routines.
3387 ***************************************************/
3389 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3390 CTASSERT(_NPCM == 3);
3391 CTASSERT(_NPCPV == 168);
3393 static __inline struct pv_chunk *
3394 pv_to_chunk(pv_entry_t pv)
3397 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3400 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3402 #define PC_FREE0 0xfffffffffffffffful
3403 #define PC_FREE1 0xfffffffffffffffful
3404 #define PC_FREE2 0x000000fffffffffful
3406 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3409 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3411 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3412 "Current number of pv entry chunks");
3413 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3414 "Current number of pv entry chunks allocated");
3415 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3416 "Current number of pv entry chunks frees");
3417 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3418 "Number of times tried to get a chunk page but failed.");
3420 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3421 static int pv_entry_spare;
3423 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3424 "Current number of pv entry frees");
3425 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3426 "Current number of pv entry allocs");
3427 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3428 "Current number of pv entries");
3429 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3430 "Current number of spare pv entries");
3434 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3439 pmap_invalidate_all(pmap);
3440 if (pmap != locked_pmap)
3443 pmap_delayed_invl_finished();
3447 * We are in a serious low memory condition. Resort to
3448 * drastic measures to free some pages so we can allocate
3449 * another pv entry chunk.
3451 * Returns NULL if PV entries were reclaimed from the specified pmap.
3453 * We do not, however, unmap 2mpages because subsequent accesses will
3454 * allocate per-page pv entries until repromotion occurs, thereby
3455 * exacerbating the shortage of free pv entries.
3458 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3460 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3461 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3462 struct md_page *pvh;
3464 pmap_t next_pmap, pmap;
3465 pt_entry_t *pte, tpte;
3466 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3470 struct spglist free;
3472 int bit, field, freed;
3474 static int active_reclaims = 0;
3476 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3477 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3480 PG_G = PG_A = PG_M = PG_RW = 0;
3482 bzero(&pc_marker_b, sizeof(pc_marker_b));
3483 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3484 pc_marker = (struct pv_chunk *)&pc_marker_b;
3485 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3488 * A delayed invalidation block should already be active if
3489 * pmap_advise() or pmap_remove() called this function by way
3490 * of pmap_demote_pde_locked().
3492 start_di = pmap_not_in_di();
3494 mtx_lock(&pv_chunks_mutex);
3496 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3497 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3498 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3499 SLIST_EMPTY(&free)) {
3500 next_pmap = pc->pc_pmap;
3501 if (next_pmap == NULL) {
3503 * The next chunk is a marker. However, it is
3504 * not our marker, so active_reclaims must be
3505 * > 1. Consequently, the next_chunk code
3506 * will not rotate the pv_chunks list.
3510 mtx_unlock(&pv_chunks_mutex);
3513 * A pv_chunk can only be removed from the pc_lru list
3514 * when both pc_chunks_mutex is owned and the
3515 * corresponding pmap is locked.
3517 if (pmap != next_pmap) {
3518 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3521 /* Avoid deadlock and lock recursion. */
3522 if (pmap > locked_pmap) {
3523 RELEASE_PV_LIST_LOCK(lockp);
3526 pmap_delayed_invl_started();
3527 mtx_lock(&pv_chunks_mutex);
3529 } else if (pmap != locked_pmap) {
3530 if (PMAP_TRYLOCK(pmap)) {
3532 pmap_delayed_invl_started();
3533 mtx_lock(&pv_chunks_mutex);
3536 pmap = NULL; /* pmap is not locked */
3537 mtx_lock(&pv_chunks_mutex);
3538 pc = TAILQ_NEXT(pc_marker, pc_lru);
3540 pc->pc_pmap != next_pmap)
3544 } else if (start_di)
3545 pmap_delayed_invl_started();
3546 PG_G = pmap_global_bit(pmap);
3547 PG_A = pmap_accessed_bit(pmap);
3548 PG_M = pmap_modified_bit(pmap);
3549 PG_RW = pmap_rw_bit(pmap);
3553 * Destroy every non-wired, 4 KB page mapping in the chunk.
3556 for (field = 0; field < _NPCM; field++) {
3557 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3558 inuse != 0; inuse &= ~(1UL << bit)) {
3560 pv = &pc->pc_pventry[field * 64 + bit];
3562 pde = pmap_pde(pmap, va);
3563 if ((*pde & PG_PS) != 0)
3565 pte = pmap_pde_to_pte(pde, va);
3566 if ((*pte & PG_W) != 0)
3568 tpte = pte_load_clear(pte);
3569 if ((tpte & PG_G) != 0)
3570 pmap_invalidate_page(pmap, va);
3571 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3572 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3574 if ((tpte & PG_A) != 0)
3575 vm_page_aflag_set(m, PGA_REFERENCED);
3576 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3577 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3579 if (TAILQ_EMPTY(&m->md.pv_list) &&
3580 (m->flags & PG_FICTITIOUS) == 0) {
3581 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3582 if (TAILQ_EMPTY(&pvh->pv_list)) {
3583 vm_page_aflag_clear(m,
3587 pmap_delayed_invl_page(m);
3588 pc->pc_map[field] |= 1UL << bit;
3589 pmap_unuse_pt(pmap, va, *pde, &free);
3594 mtx_lock(&pv_chunks_mutex);
3597 /* Every freed mapping is for a 4 KB page. */
3598 pmap_resident_count_dec(pmap, freed);
3599 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3600 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3601 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3602 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3603 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3604 pc->pc_map[2] == PC_FREE2) {
3605 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3606 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3607 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3608 /* Entire chunk is free; return it. */
3609 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3610 dump_drop_page(m_pc->phys_addr);
3611 mtx_lock(&pv_chunks_mutex);
3612 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3615 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3616 mtx_lock(&pv_chunks_mutex);
3617 /* One freed pv entry in locked_pmap is sufficient. */
3618 if (pmap == locked_pmap)
3621 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3622 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3623 if (active_reclaims == 1 && pmap != NULL) {
3625 * Rotate the pv chunks list so that we do not
3626 * scan the same pv chunks that could not be
3627 * freed (because they contained a wired
3628 * and/or superpage mapping) on every
3629 * invocation of reclaim_pv_chunk().
3631 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3632 MPASS(pc->pc_pmap != NULL);
3633 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3634 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3638 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3639 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3641 mtx_unlock(&pv_chunks_mutex);
3642 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3643 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3644 m_pc = SLIST_FIRST(&free);
3645 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3646 /* Recycle a freed page table page. */
3647 m_pc->wire_count = 1;
3649 vm_page_free_pages_toq(&free, true);
3654 * free the pv_entry back to the free list
3657 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3659 struct pv_chunk *pc;
3660 int idx, field, bit;
3662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3663 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3664 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3665 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3666 pc = pv_to_chunk(pv);
3667 idx = pv - &pc->pc_pventry[0];
3670 pc->pc_map[field] |= 1ul << bit;
3671 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3672 pc->pc_map[2] != PC_FREE2) {
3673 /* 98% of the time, pc is already at the head of the list. */
3674 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3675 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3676 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3680 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3685 free_pv_chunk(struct pv_chunk *pc)
3689 mtx_lock(&pv_chunks_mutex);
3690 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3691 mtx_unlock(&pv_chunks_mutex);
3692 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3693 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3694 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3695 /* entire chunk is free, return it */
3696 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3697 dump_drop_page(m->phys_addr);
3698 vm_page_unwire(m, PQ_NONE);
3703 * Returns a new PV entry, allocating a new PV chunk from the system when
3704 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3705 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3708 * The given PV list lock may be released.
3711 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3715 struct pv_chunk *pc;
3718 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3719 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3721 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3723 for (field = 0; field < _NPCM; field++) {
3724 if (pc->pc_map[field]) {
3725 bit = bsfq(pc->pc_map[field]);
3729 if (field < _NPCM) {
3730 pv = &pc->pc_pventry[field * 64 + bit];
3731 pc->pc_map[field] &= ~(1ul << bit);
3732 /* If this was the last item, move it to tail */
3733 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3734 pc->pc_map[2] == 0) {
3735 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3736 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3739 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3740 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3744 /* No free items, allocate another chunk */
3745 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3748 if (lockp == NULL) {
3749 PV_STAT(pc_chunk_tryfail++);
3752 m = reclaim_pv_chunk(pmap, lockp);
3756 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3757 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3758 dump_add_page(m->phys_addr);
3759 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3761 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3762 pc->pc_map[1] = PC_FREE1;
3763 pc->pc_map[2] = PC_FREE2;
3764 mtx_lock(&pv_chunks_mutex);
3765 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3766 mtx_unlock(&pv_chunks_mutex);
3767 pv = &pc->pc_pventry[0];
3768 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3769 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3770 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3775 * Returns the number of one bits within the given PV chunk map.
3777 * The erratas for Intel processors state that "POPCNT Instruction May
3778 * Take Longer to Execute Than Expected". It is believed that the
3779 * issue is the spurious dependency on the destination register.
3780 * Provide a hint to the register rename logic that the destination
3781 * value is overwritten, by clearing it, as suggested in the
3782 * optimization manual. It should be cheap for unaffected processors
3785 * Reference numbers for erratas are
3786 * 4th Gen Core: HSD146
3787 * 5th Gen Core: BDM85
3788 * 6th Gen Core: SKL029
3791 popcnt_pc_map_pq(uint64_t *map)
3795 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3796 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3797 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3798 : "=&r" (result), "=&r" (tmp)
3799 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3804 * Ensure that the number of spare PV entries in the specified pmap meets or
3805 * exceeds the given count, "needed".
3807 * The given PV list lock may be released.
3810 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3812 struct pch new_tail;
3813 struct pv_chunk *pc;
3818 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3819 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3822 * Newly allocated PV chunks must be stored in a private list until
3823 * the required number of PV chunks have been allocated. Otherwise,
3824 * reclaim_pv_chunk() could recycle one of these chunks. In
3825 * contrast, these chunks must be added to the pmap upon allocation.
3827 TAILQ_INIT(&new_tail);
3830 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3832 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3833 bit_count((bitstr_t *)pc->pc_map, 0,
3834 sizeof(pc->pc_map) * NBBY, &free);
3837 free = popcnt_pc_map_pq(pc->pc_map);
3841 if (avail >= needed)
3844 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3845 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3848 m = reclaim_pv_chunk(pmap, lockp);
3853 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3854 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3855 dump_add_page(m->phys_addr);
3856 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3858 pc->pc_map[0] = PC_FREE0;
3859 pc->pc_map[1] = PC_FREE1;
3860 pc->pc_map[2] = PC_FREE2;
3861 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3862 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3863 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3866 * The reclaim might have freed a chunk from the current pmap.
3867 * If that chunk contained available entries, we need to
3868 * re-count the number of available entries.
3873 if (!TAILQ_EMPTY(&new_tail)) {
3874 mtx_lock(&pv_chunks_mutex);
3875 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3876 mtx_unlock(&pv_chunks_mutex);
3881 * First find and then remove the pv entry for the specified pmap and virtual
3882 * address from the specified pv list. Returns the pv entry if found and NULL
3883 * otherwise. This operation can be performed on pv lists for either 4KB or
3884 * 2MB page mappings.
3886 static __inline pv_entry_t
3887 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3891 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3892 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3893 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3902 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3903 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3904 * entries for each of the 4KB page mappings.
3907 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3908 struct rwlock **lockp)
3910 struct md_page *pvh;
3911 struct pv_chunk *pc;
3913 vm_offset_t va_last;
3917 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3918 KASSERT((pa & PDRMASK) == 0,
3919 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3920 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3923 * Transfer the 2mpage's pv entry for this mapping to the first
3924 * page's pv list. Once this transfer begins, the pv list lock
3925 * must not be released until the last pv entry is reinstantiated.
3927 pvh = pa_to_pvh(pa);
3928 va = trunc_2mpage(va);
3929 pv = pmap_pvh_remove(pvh, pmap, va);
3930 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3931 m = PHYS_TO_VM_PAGE(pa);
3932 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3934 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3935 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3936 va_last = va + NBPDR - PAGE_SIZE;
3938 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3939 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3940 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3941 for (field = 0; field < _NPCM; field++) {
3942 while (pc->pc_map[field]) {
3943 bit = bsfq(pc->pc_map[field]);
3944 pc->pc_map[field] &= ~(1ul << bit);
3945 pv = &pc->pc_pventry[field * 64 + bit];
3949 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3950 ("pmap_pv_demote_pde: page %p is not managed", m));
3951 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3957 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3958 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3961 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3962 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3963 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3965 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3966 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3969 #if VM_NRESERVLEVEL > 0
3971 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3972 * replace the many pv entries for the 4KB page mappings by a single pv entry
3973 * for the 2MB page mapping.
3976 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3977 struct rwlock **lockp)
3979 struct md_page *pvh;
3981 vm_offset_t va_last;
3984 KASSERT((pa & PDRMASK) == 0,
3985 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3986 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3989 * Transfer the first page's pv entry for this mapping to the 2mpage's
3990 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3991 * a transfer avoids the possibility that get_pv_entry() calls
3992 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3993 * mappings that is being promoted.
3995 m = PHYS_TO_VM_PAGE(pa);
3996 va = trunc_2mpage(va);
3997 pv = pmap_pvh_remove(&m->md, pmap, va);
3998 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3999 pvh = pa_to_pvh(pa);
4000 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4002 /* Free the remaining NPTEPG - 1 pv entries. */
4003 va_last = va + NBPDR - PAGE_SIZE;
4007 pmap_pvh_free(&m->md, pmap, va);
4008 } while (va < va_last);
4010 #endif /* VM_NRESERVLEVEL > 0 */
4013 * First find and then destroy the pv entry for the specified pmap and virtual
4014 * address. This operation can be performed on pv lists for either 4KB or 2MB
4018 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4022 pv = pmap_pvh_remove(pvh, pmap, va);
4023 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4024 free_pv_entry(pmap, pv);
4028 * Conditionally create the PV entry for a 4KB page mapping if the required
4029 * memory can be allocated without resorting to reclamation.
4032 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4033 struct rwlock **lockp)
4037 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4038 /* Pass NULL instead of the lock pointer to disable reclamation. */
4039 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4041 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4042 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4050 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4051 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4052 * false if the PV entry cannot be allocated without resorting to reclamation.
4055 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4056 struct rwlock **lockp)
4058 struct md_page *pvh;
4062 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4063 /* Pass NULL instead of the lock pointer to disable reclamation. */
4064 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4065 NULL : lockp)) == NULL)
4068 pa = pde & PG_PS_FRAME;
4069 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4070 pvh = pa_to_pvh(pa);
4071 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4077 * Fills a page table page with mappings to consecutive physical pages.
4080 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4084 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4086 newpte += PAGE_SIZE;
4091 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4092 * mapping is invalidated.
4095 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4097 struct rwlock *lock;
4101 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4108 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4109 struct rwlock **lockp)
4111 pd_entry_t newpde, oldpde;
4112 pt_entry_t *firstpte, newpte;
4113 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4116 struct spglist free;
4120 PG_G = pmap_global_bit(pmap);
4121 PG_A = pmap_accessed_bit(pmap);
4122 PG_M = pmap_modified_bit(pmap);
4123 PG_RW = pmap_rw_bit(pmap);
4124 PG_V = pmap_valid_bit(pmap);
4125 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4126 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4128 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4130 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4131 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4132 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
4134 KASSERT((oldpde & PG_W) == 0,
4135 ("pmap_demote_pde: page table page for a wired mapping"
4139 * Invalidate the 2MB page mapping and return "failure" if the
4140 * mapping was never accessed or the allocation of the new
4141 * page table page fails. If the 2MB page mapping belongs to
4142 * the direct map region of the kernel's address space, then
4143 * the page allocation request specifies the highest possible
4144 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
4145 * normal. Page table pages are preallocated for every other
4146 * part of the kernel address space, so the direct map region
4147 * is the only part of the kernel address space that must be
4150 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
4151 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
4152 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4153 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4155 sva = trunc_2mpage(va);
4156 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4157 if ((oldpde & PG_G) == 0)
4158 pmap_invalidate_pde_page(pmap, sva, oldpde);
4159 vm_page_free_pages_toq(&free, true);
4160 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
4161 " in pmap %p", va, pmap);
4164 if (va < VM_MAXUSER_ADDRESS)
4165 pmap_resident_count_inc(pmap, 1);
4167 mptepa = VM_PAGE_TO_PHYS(mpte);
4168 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4169 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4170 KASSERT((oldpde & PG_A) != 0,
4171 ("pmap_demote_pde: oldpde is missing PG_A"));
4172 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4173 ("pmap_demote_pde: oldpde is missing PG_M"));
4174 newpte = oldpde & ~PG_PS;
4175 newpte = pmap_swap_pat(pmap, newpte);
4178 * If the page table page is new, initialize it.
4180 if (mpte->wire_count == 1) {
4181 mpte->wire_count = NPTEPG;
4182 pmap_fill_ptp(firstpte, newpte);
4184 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4185 ("pmap_demote_pde: firstpte and newpte map different physical"
4189 * If the mapping has changed attributes, update the page table
4192 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4193 pmap_fill_ptp(firstpte, newpte);
4196 * The spare PV entries must be reserved prior to demoting the
4197 * mapping, that is, prior to changing the PDE. Otherwise, the state
4198 * of the PDE and the PV lists will be inconsistent, which can result
4199 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4200 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4201 * PV entry for the 2MB page mapping that is being demoted.
4203 if ((oldpde & PG_MANAGED) != 0)
4204 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4207 * Demote the mapping. This pmap is locked. The old PDE has
4208 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4209 * set. Thus, there is no danger of a race with another
4210 * processor changing the setting of PG_A and/or PG_M between
4211 * the read above and the store below.
4213 if (workaround_erratum383)
4214 pmap_update_pde(pmap, va, pde, newpde);
4216 pde_store(pde, newpde);
4219 * Invalidate a stale recursive mapping of the page table page.
4221 if (va >= VM_MAXUSER_ADDRESS)
4222 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4225 * Demote the PV entry.
4227 if ((oldpde & PG_MANAGED) != 0)
4228 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4230 atomic_add_long(&pmap_pde_demotions, 1);
4231 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
4232 " in pmap %p", va, pmap);
4237 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4240 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4246 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4247 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4248 mpte = pmap_remove_pt_page(pmap, va);
4250 panic("pmap_remove_kernel_pde: Missing pt page.");
4252 mptepa = VM_PAGE_TO_PHYS(mpte);
4253 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4256 * Initialize the page table page.
4258 pagezero((void *)PHYS_TO_DMAP(mptepa));
4261 * Demote the mapping.
4263 if (workaround_erratum383)
4264 pmap_update_pde(pmap, va, pde, newpde);
4266 pde_store(pde, newpde);
4269 * Invalidate a stale recursive mapping of the page table page.
4271 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4275 * pmap_remove_pde: do the things to unmap a superpage in a process
4278 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4279 struct spglist *free, struct rwlock **lockp)
4281 struct md_page *pvh;
4283 vm_offset_t eva, va;
4285 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4287 PG_G = pmap_global_bit(pmap);
4288 PG_A = pmap_accessed_bit(pmap);
4289 PG_M = pmap_modified_bit(pmap);
4290 PG_RW = pmap_rw_bit(pmap);
4292 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4293 KASSERT((sva & PDRMASK) == 0,
4294 ("pmap_remove_pde: sva is not 2mpage aligned"));
4295 oldpde = pte_load_clear(pdq);
4297 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4298 if ((oldpde & PG_G) != 0)
4299 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4300 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4301 if (oldpde & PG_MANAGED) {
4302 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4303 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4304 pmap_pvh_free(pvh, pmap, sva);
4306 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4307 va < eva; va += PAGE_SIZE, m++) {
4308 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4311 vm_page_aflag_set(m, PGA_REFERENCED);
4312 if (TAILQ_EMPTY(&m->md.pv_list) &&
4313 TAILQ_EMPTY(&pvh->pv_list))
4314 vm_page_aflag_clear(m, PGA_WRITEABLE);
4315 pmap_delayed_invl_page(m);
4318 if (pmap == kernel_pmap) {
4319 pmap_remove_kernel_pde(pmap, pdq, sva);
4321 mpte = pmap_remove_pt_page(pmap, sva);
4323 pmap_resident_count_dec(pmap, 1);
4324 KASSERT(mpte->wire_count == NPTEPG,
4325 ("pmap_remove_pde: pte page wire count error"));
4326 mpte->wire_count = 0;
4327 pmap_add_delayed_free_list(mpte, free, FALSE);
4330 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4334 * pmap_remove_pte: do the things to unmap a page in a process
4337 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4338 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4340 struct md_page *pvh;
4341 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4344 PG_A = pmap_accessed_bit(pmap);
4345 PG_M = pmap_modified_bit(pmap);
4346 PG_RW = pmap_rw_bit(pmap);
4348 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4349 oldpte = pte_load_clear(ptq);
4351 pmap->pm_stats.wired_count -= 1;
4352 pmap_resident_count_dec(pmap, 1);
4353 if (oldpte & PG_MANAGED) {
4354 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4355 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4358 vm_page_aflag_set(m, PGA_REFERENCED);
4359 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4360 pmap_pvh_free(&m->md, pmap, va);
4361 if (TAILQ_EMPTY(&m->md.pv_list) &&
4362 (m->flags & PG_FICTITIOUS) == 0) {
4363 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4364 if (TAILQ_EMPTY(&pvh->pv_list))
4365 vm_page_aflag_clear(m, PGA_WRITEABLE);
4367 pmap_delayed_invl_page(m);
4369 return (pmap_unuse_pt(pmap, va, ptepde, free));
4373 * Remove a single page from a process address space
4376 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4377 struct spglist *free)
4379 struct rwlock *lock;
4380 pt_entry_t *pte, PG_V;
4382 PG_V = pmap_valid_bit(pmap);
4383 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4384 if ((*pde & PG_V) == 0)
4386 pte = pmap_pde_to_pte(pde, va);
4387 if ((*pte & PG_V) == 0)
4390 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4393 pmap_invalidate_page(pmap, va);
4397 * Removes the specified range of addresses from the page table page.
4400 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4401 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4403 pt_entry_t PG_G, *pte;
4407 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4408 PG_G = pmap_global_bit(pmap);
4411 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4415 pmap_invalidate_range(pmap, va, sva);
4420 if ((*pte & PG_G) == 0)
4424 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4430 pmap_invalidate_range(pmap, va, sva);
4435 * Remove the given range of addresses from the specified map.
4437 * It is assumed that the start and end are properly
4438 * rounded to the page size.
4441 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4443 struct rwlock *lock;
4444 vm_offset_t va_next;
4445 pml4_entry_t *pml4e;
4447 pd_entry_t ptpaddr, *pde;
4448 pt_entry_t PG_G, PG_V;
4449 struct spglist free;
4452 PG_G = pmap_global_bit(pmap);
4453 PG_V = pmap_valid_bit(pmap);
4456 * Perform an unsynchronized read. This is, however, safe.
4458 if (pmap->pm_stats.resident_count == 0)
4464 pmap_delayed_invl_started();
4468 * special handling of removing one page. a very
4469 * common operation and easy to short circuit some
4472 if (sva + PAGE_SIZE == eva) {
4473 pde = pmap_pde(pmap, sva);
4474 if (pde && (*pde & PG_PS) == 0) {
4475 pmap_remove_page(pmap, sva, pde, &free);
4481 for (; sva < eva; sva = va_next) {
4483 if (pmap->pm_stats.resident_count == 0)
4486 pml4e = pmap_pml4e(pmap, sva);
4487 if ((*pml4e & PG_V) == 0) {
4488 va_next = (sva + NBPML4) & ~PML4MASK;
4494 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4495 if ((*pdpe & PG_V) == 0) {
4496 va_next = (sva + NBPDP) & ~PDPMASK;
4503 * Calculate index for next page table.
4505 va_next = (sva + NBPDR) & ~PDRMASK;
4509 pde = pmap_pdpe_to_pde(pdpe, sva);
4513 * Weed out invalid mappings.
4519 * Check for large page.
4521 if ((ptpaddr & PG_PS) != 0) {
4523 * Are we removing the entire large page? If not,
4524 * demote the mapping and fall through.
4526 if (sva + NBPDR == va_next && eva >= va_next) {
4528 * The TLB entry for a PG_G mapping is
4529 * invalidated by pmap_remove_pde().
4531 if ((ptpaddr & PG_G) == 0)
4533 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4535 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4537 /* The large page mapping was destroyed. */
4544 * Limit our scan to either the end of the va represented
4545 * by the current page table page, or to the end of the
4546 * range being removed.
4551 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4558 pmap_invalidate_all(pmap);
4559 pmap_pkru_on_remove(pmap, sva, eva);
4561 pmap_delayed_invl_finished();
4562 vm_page_free_pages_toq(&free, true);
4566 * Routine: pmap_remove_all
4568 * Removes this physical page from
4569 * all physical maps in which it resides.
4570 * Reflects back modify bits to the pager.
4573 * Original versions of this routine were very
4574 * inefficient because they iteratively called
4575 * pmap_remove (slow...)
4579 pmap_remove_all(vm_page_t m)
4581 struct md_page *pvh;
4584 struct rwlock *lock;
4585 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4588 struct spglist free;
4589 int pvh_gen, md_gen;
4591 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4592 ("pmap_remove_all: page %p is not managed", m));
4594 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4595 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4596 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4599 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4601 if (!PMAP_TRYLOCK(pmap)) {
4602 pvh_gen = pvh->pv_gen;
4606 if (pvh_gen != pvh->pv_gen) {
4613 pde = pmap_pde(pmap, va);
4614 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4617 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4619 if (!PMAP_TRYLOCK(pmap)) {
4620 pvh_gen = pvh->pv_gen;
4621 md_gen = m->md.pv_gen;
4625 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4631 PG_A = pmap_accessed_bit(pmap);
4632 PG_M = pmap_modified_bit(pmap);
4633 PG_RW = pmap_rw_bit(pmap);
4634 pmap_resident_count_dec(pmap, 1);
4635 pde = pmap_pde(pmap, pv->pv_va);
4636 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4637 " a 2mpage in page %p's pv list", m));
4638 pte = pmap_pde_to_pte(pde, pv->pv_va);
4639 tpte = pte_load_clear(pte);
4641 pmap->pm_stats.wired_count--;
4643 vm_page_aflag_set(m, PGA_REFERENCED);
4646 * Update the vm_page_t clean and reference bits.
4648 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4650 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4651 pmap_invalidate_page(pmap, pv->pv_va);
4652 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4654 free_pv_entry(pmap, pv);
4657 vm_page_aflag_clear(m, PGA_WRITEABLE);
4659 pmap_delayed_invl_wait(m);
4660 vm_page_free_pages_toq(&free, true);
4664 * pmap_protect_pde: do the things to protect a 2mpage in a process
4667 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4669 pd_entry_t newpde, oldpde;
4670 vm_offset_t eva, va;
4672 boolean_t anychanged;
4673 pt_entry_t PG_G, PG_M, PG_RW;
4675 PG_G = pmap_global_bit(pmap);
4676 PG_M = pmap_modified_bit(pmap);
4677 PG_RW = pmap_rw_bit(pmap);
4679 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4680 KASSERT((sva & PDRMASK) == 0,
4681 ("pmap_protect_pde: sva is not 2mpage aligned"));
4684 oldpde = newpde = *pde;
4685 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4686 (PG_MANAGED | PG_M | PG_RW)) {
4688 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4689 va < eva; va += PAGE_SIZE, m++)
4692 if ((prot & VM_PROT_WRITE) == 0)
4693 newpde &= ~(PG_RW | PG_M);
4694 if ((prot & VM_PROT_EXECUTE) == 0)
4696 if (newpde != oldpde) {
4698 * As an optimization to future operations on this PDE, clear
4699 * PG_PROMOTED. The impending invalidation will remove any
4700 * lingering 4KB page mappings from the TLB.
4702 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4704 if ((oldpde & PG_G) != 0)
4705 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4709 return (anychanged);
4713 * Set the physical protection on the
4714 * specified range of this map as requested.
4717 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4719 vm_offset_t va_next;
4720 pml4_entry_t *pml4e;
4722 pd_entry_t ptpaddr, *pde;
4723 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4724 boolean_t anychanged;
4726 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4727 if (prot == VM_PROT_NONE) {
4728 pmap_remove(pmap, sva, eva);
4732 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4733 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4736 PG_G = pmap_global_bit(pmap);
4737 PG_M = pmap_modified_bit(pmap);
4738 PG_V = pmap_valid_bit(pmap);
4739 PG_RW = pmap_rw_bit(pmap);
4743 * Although this function delays and batches the invalidation
4744 * of stale TLB entries, it does not need to call
4745 * pmap_delayed_invl_started() and
4746 * pmap_delayed_invl_finished(), because it does not
4747 * ordinarily destroy mappings. Stale TLB entries from
4748 * protection-only changes need only be invalidated before the
4749 * pmap lock is released, because protection-only changes do
4750 * not destroy PV entries. Even operations that iterate over
4751 * a physical page's PV list of mappings, like
4752 * pmap_remove_write(), acquire the pmap lock for each
4753 * mapping. Consequently, for protection-only changes, the
4754 * pmap lock suffices to synchronize both page table and TLB
4757 * This function only destroys a mapping if pmap_demote_pde()
4758 * fails. In that case, stale TLB entries are immediately
4763 for (; sva < eva; sva = va_next) {
4765 pml4e = pmap_pml4e(pmap, sva);
4766 if ((*pml4e & PG_V) == 0) {
4767 va_next = (sva + NBPML4) & ~PML4MASK;
4773 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4774 if ((*pdpe & PG_V) == 0) {
4775 va_next = (sva + NBPDP) & ~PDPMASK;
4781 va_next = (sva + NBPDR) & ~PDRMASK;
4785 pde = pmap_pdpe_to_pde(pdpe, sva);
4789 * Weed out invalid mappings.
4795 * Check for large page.
4797 if ((ptpaddr & PG_PS) != 0) {
4799 * Are we protecting the entire large page? If not,
4800 * demote the mapping and fall through.
4802 if (sva + NBPDR == va_next && eva >= va_next) {
4804 * The TLB entry for a PG_G mapping is
4805 * invalidated by pmap_protect_pde().
4807 if (pmap_protect_pde(pmap, pde, sva, prot))
4810 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4812 * The large page mapping was destroyed.
4821 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4823 pt_entry_t obits, pbits;
4827 obits = pbits = *pte;
4828 if ((pbits & PG_V) == 0)
4831 if ((prot & VM_PROT_WRITE) == 0) {
4832 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4833 (PG_MANAGED | PG_M | PG_RW)) {
4834 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4837 pbits &= ~(PG_RW | PG_M);
4839 if ((prot & VM_PROT_EXECUTE) == 0)
4842 if (pbits != obits) {
4843 if (!atomic_cmpset_long(pte, obits, pbits))
4846 pmap_invalidate_page(pmap, sva);
4853 pmap_invalidate_all(pmap);
4857 #if VM_NRESERVLEVEL > 0
4859 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4860 * single page table page (PTP) to a single 2MB page mapping. For promotion
4861 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4862 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4863 * identical characteristics.
4866 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4867 struct rwlock **lockp)
4870 pt_entry_t *firstpte, oldpte, pa, *pte;
4871 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
4875 PG_A = pmap_accessed_bit(pmap);
4876 PG_G = pmap_global_bit(pmap);
4877 PG_M = pmap_modified_bit(pmap);
4878 PG_V = pmap_valid_bit(pmap);
4879 PG_RW = pmap_rw_bit(pmap);
4880 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4881 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4883 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4886 * Examine the first PTE in the specified PTP. Abort if this PTE is
4887 * either invalid, unused, or does not map the first 4KB physical page
4888 * within a 2MB page.
4890 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4893 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4894 atomic_add_long(&pmap_pde_p_failures, 1);
4895 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4896 " in pmap %p", va, pmap);
4899 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4901 * When PG_M is already clear, PG_RW can be cleared without
4902 * a TLB invalidation.
4904 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4910 * Examine each of the other PTEs in the specified PTP. Abort if this
4911 * PTE maps an unexpected 4KB physical page or does not have identical
4912 * characteristics to the first PTE.
4914 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4915 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4918 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4919 atomic_add_long(&pmap_pde_p_failures, 1);
4920 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4921 " in pmap %p", va, pmap);
4924 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4926 * When PG_M is already clear, PG_RW can be cleared
4927 * without a TLB invalidation.
4929 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4932 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4933 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4934 (va & ~PDRMASK), pmap);
4936 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4937 atomic_add_long(&pmap_pde_p_failures, 1);
4938 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4939 " in pmap %p", va, pmap);
4946 * Save the page table page in its current state until the PDE
4947 * mapping the superpage is demoted by pmap_demote_pde() or
4948 * destroyed by pmap_remove_pde().
4950 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4951 KASSERT(mpte >= vm_page_array &&
4952 mpte < &vm_page_array[vm_page_array_size],
4953 ("pmap_promote_pde: page table page is out of range"));
4954 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4955 ("pmap_promote_pde: page table page's pindex is wrong"));
4956 if (pmap_insert_pt_page(pmap, mpte)) {
4957 atomic_add_long(&pmap_pde_p_failures, 1);
4959 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4965 * Promote the pv entries.
4967 if ((newpde & PG_MANAGED) != 0)
4968 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4971 * Propagate the PAT index to its proper position.
4973 newpde = pmap_swap_pat(pmap, newpde);
4976 * Map the superpage.
4978 if (workaround_erratum383)
4979 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4981 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4983 atomic_add_long(&pmap_pde_promotions, 1);
4984 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4985 " in pmap %p", va, pmap);
4987 #endif /* VM_NRESERVLEVEL > 0 */
4990 * Insert the given physical page (p) at
4991 * the specified virtual address (v) in the
4992 * target physical map with the protection requested.
4994 * If specified, the page will be wired down, meaning
4995 * that the related pte can not be reclaimed.
4997 * NB: This is the only routine which MAY NOT lazy-evaluate
4998 * or lose information. That is, this routine must actually
4999 * insert this page into the given map NOW.
5001 * When destroying both a page table and PV entry, this function
5002 * performs the TLB invalidation before releasing the PV list
5003 * lock, so we do not need pmap_delayed_invl_page() calls here.
5006 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5007 u_int flags, int8_t psind)
5009 struct rwlock *lock;
5011 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5012 pt_entry_t newpte, origpte;
5019 PG_A = pmap_accessed_bit(pmap);
5020 PG_G = pmap_global_bit(pmap);
5021 PG_M = pmap_modified_bit(pmap);
5022 PG_V = pmap_valid_bit(pmap);
5023 PG_RW = pmap_rw_bit(pmap);
5025 va = trunc_page(va);
5026 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5027 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5028 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5030 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5031 va >= kmi.clean_eva,
5032 ("pmap_enter: managed mapping within the clean submap"));
5033 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5034 VM_OBJECT_ASSERT_LOCKED(m->object);
5035 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5036 ("pmap_enter: flags %u has reserved bits set", flags));
5037 pa = VM_PAGE_TO_PHYS(m);
5038 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5039 if ((flags & VM_PROT_WRITE) != 0)
5041 if ((prot & VM_PROT_WRITE) != 0)
5043 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5044 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5045 if ((prot & VM_PROT_EXECUTE) == 0)
5047 if ((flags & PMAP_ENTER_WIRED) != 0)
5049 if (va < VM_MAXUSER_ADDRESS)
5051 if (pmap == kernel_pmap)
5053 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5056 * Set modified bit gratuitously for writeable mappings if
5057 * the page is unmanaged. We do not want to take a fault
5058 * to do the dirty bit accounting for these mappings.
5060 if ((m->oflags & VPO_UNMANAGED) != 0) {
5061 if ((newpte & PG_RW) != 0)
5064 newpte |= PG_MANAGED;
5069 /* Assert the required virtual and physical alignment. */
5070 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5071 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5072 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5078 * In the case that a page table page is not
5079 * resident, we are creating it here.
5082 pde = pmap_pde(pmap, va);
5083 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5084 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5085 pte = pmap_pde_to_pte(pde, va);
5086 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5087 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5090 } else if (va < VM_MAXUSER_ADDRESS) {
5092 * Here if the pte page isn't mapped, or if it has been
5095 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5096 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5097 nosleep ? NULL : &lock);
5098 if (mpte == NULL && nosleep) {
5099 rv = KERN_RESOURCE_SHORTAGE;
5104 panic("pmap_enter: invalid page directory va=%#lx", va);
5108 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5109 newpte |= pmap_pkru_get(pmap, va);
5112 * Is the specified virtual address already mapped?
5114 if ((origpte & PG_V) != 0) {
5116 * Wiring change, just update stats. We don't worry about
5117 * wiring PT pages as they remain resident as long as there
5118 * are valid mappings in them. Hence, if a user page is wired,
5119 * the PT page will be also.
5121 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5122 pmap->pm_stats.wired_count++;
5123 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5124 pmap->pm_stats.wired_count--;
5127 * Remove the extra PT page reference.
5131 KASSERT(mpte->wire_count > 0,
5132 ("pmap_enter: missing reference to page table page,"
5137 * Has the physical page changed?
5139 opa = origpte & PG_FRAME;
5142 * No, might be a protection or wiring change.
5144 if ((origpte & PG_MANAGED) != 0 &&
5145 (newpte & PG_RW) != 0)
5146 vm_page_aflag_set(m, PGA_WRITEABLE);
5147 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5153 * The physical page has changed. Temporarily invalidate
5154 * the mapping. This ensures that all threads sharing the
5155 * pmap keep a consistent view of the mapping, which is
5156 * necessary for the correct handling of COW faults. It
5157 * also permits reuse of the old mapping's PV entry,
5158 * avoiding an allocation.
5160 * For consistency, handle unmanaged mappings the same way.
5162 origpte = pte_load_clear(pte);
5163 KASSERT((origpte & PG_FRAME) == opa,
5164 ("pmap_enter: unexpected pa update for %#lx", va));
5165 if ((origpte & PG_MANAGED) != 0) {
5166 om = PHYS_TO_VM_PAGE(opa);
5169 * The pmap lock is sufficient to synchronize with
5170 * concurrent calls to pmap_page_test_mappings() and
5171 * pmap_ts_referenced().
5173 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5175 if ((origpte & PG_A) != 0)
5176 vm_page_aflag_set(om, PGA_REFERENCED);
5177 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5178 pv = pmap_pvh_remove(&om->md, pmap, va);
5180 ("pmap_enter: no PV entry for %#lx", va));
5181 if ((newpte & PG_MANAGED) == 0)
5182 free_pv_entry(pmap, pv);
5183 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5184 TAILQ_EMPTY(&om->md.pv_list) &&
5185 ((om->flags & PG_FICTITIOUS) != 0 ||
5186 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5187 vm_page_aflag_clear(om, PGA_WRITEABLE);
5189 if ((origpte & PG_A) != 0)
5190 pmap_invalidate_page(pmap, va);
5194 * Increment the counters.
5196 if ((newpte & PG_W) != 0)
5197 pmap->pm_stats.wired_count++;
5198 pmap_resident_count_inc(pmap, 1);
5202 * Enter on the PV list if part of our managed memory.
5204 if ((newpte & PG_MANAGED) != 0) {
5206 pv = get_pv_entry(pmap, &lock);
5209 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5210 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5212 if ((newpte & PG_RW) != 0)
5213 vm_page_aflag_set(m, PGA_WRITEABLE);
5219 if ((origpte & PG_V) != 0) {
5221 origpte = pte_load_store(pte, newpte);
5222 KASSERT((origpte & PG_FRAME) == pa,
5223 ("pmap_enter: unexpected pa update for %#lx", va));
5224 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5226 if ((origpte & PG_MANAGED) != 0)
5230 * Although the PTE may still have PG_RW set, TLB
5231 * invalidation may nonetheless be required because
5232 * the PTE no longer has PG_M set.
5234 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5236 * This PTE change does not require TLB invalidation.
5240 if ((origpte & PG_A) != 0)
5241 pmap_invalidate_page(pmap, va);
5243 pte_store(pte, newpte);
5247 #if VM_NRESERVLEVEL > 0
5249 * If both the page table page and the reservation are fully
5250 * populated, then attempt promotion.
5252 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5253 pmap_ps_enabled(pmap) &&
5254 (m->flags & PG_FICTITIOUS) == 0 &&
5255 vm_reserv_level_iffullpop(m) == 0)
5256 pmap_promote_pde(pmap, pde, va, &lock);
5268 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5269 * if successful. Returns false if (1) a page table page cannot be allocated
5270 * without sleeping, (2) a mapping already exists at the specified virtual
5271 * address, or (3) a PV entry cannot be allocated without reclaiming another
5275 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5276 struct rwlock **lockp)
5281 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5282 PG_V = pmap_valid_bit(pmap);
5283 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5285 if ((m->oflags & VPO_UNMANAGED) == 0)
5286 newpde |= PG_MANAGED;
5287 if ((prot & VM_PROT_EXECUTE) == 0)
5289 if (va < VM_MAXUSER_ADDRESS)
5291 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5292 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5297 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5298 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5299 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5300 * a mapping already exists at the specified virtual address. Returns
5301 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5302 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5303 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5305 * The parameter "m" is only used when creating a managed, writeable mapping.
5308 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5309 vm_page_t m, struct rwlock **lockp)
5311 struct spglist free;
5312 pd_entry_t oldpde, *pde;
5313 pt_entry_t PG_G, PG_RW, PG_V;
5316 PG_G = pmap_global_bit(pmap);
5317 PG_RW = pmap_rw_bit(pmap);
5318 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5319 ("pmap_enter_pde: newpde is missing PG_M"));
5320 PG_V = pmap_valid_bit(pmap);
5321 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5323 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5324 NULL : lockp)) == NULL) {
5325 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5326 " in pmap %p", va, pmap);
5327 return (KERN_RESOURCE_SHORTAGE);
5331 * If pkru is not same for the whole pde range, return failure
5332 * and let vm_fault() cope. Check after pde allocation, since
5335 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5337 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5338 pmap_invalidate_page(pmap, va);
5339 vm_page_free_pages_toq(&free, true);
5341 return (KERN_FAILURE);
5343 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5344 newpde &= ~X86_PG_PKU_MASK;
5345 newpde |= pmap_pkru_get(pmap, va);
5348 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5349 pde = &pde[pmap_pde_index(va)];
5351 if ((oldpde & PG_V) != 0) {
5352 KASSERT(pdpg->wire_count > 1,
5353 ("pmap_enter_pde: pdpg's wire count is too low"));
5354 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5356 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5357 " in pmap %p", va, pmap);
5358 return (KERN_FAILURE);
5360 /* Break the existing mapping(s). */
5362 if ((oldpde & PG_PS) != 0) {
5364 * The reference to the PD page that was acquired by
5365 * pmap_allocpde() ensures that it won't be freed.
5366 * However, if the PDE resulted from a promotion, then
5367 * a reserved PT page could be freed.
5369 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5370 if ((oldpde & PG_G) == 0)
5371 pmap_invalidate_pde_page(pmap, va, oldpde);
5373 pmap_delayed_invl_started();
5374 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5376 pmap_invalidate_all(pmap);
5377 pmap_delayed_invl_finished();
5379 vm_page_free_pages_toq(&free, true);
5380 if (va >= VM_MAXUSER_ADDRESS) {
5381 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5382 if (pmap_insert_pt_page(pmap, mt)) {
5384 * XXX Currently, this can't happen because
5385 * we do not perform pmap_enter(psind == 1)
5386 * on the kernel pmap.
5388 panic("pmap_enter_pde: trie insert failed");
5391 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5394 if ((newpde & PG_MANAGED) != 0) {
5396 * Abort this mapping if its PV entry could not be created.
5398 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5400 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5402 * Although "va" is not mapped, paging-
5403 * structure caches could nonetheless have
5404 * entries that refer to the freed page table
5405 * pages. Invalidate those entries.
5407 pmap_invalidate_page(pmap, va);
5408 vm_page_free_pages_toq(&free, true);
5410 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5411 " in pmap %p", va, pmap);
5412 return (KERN_RESOURCE_SHORTAGE);
5414 if ((newpde & PG_RW) != 0) {
5415 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5416 vm_page_aflag_set(mt, PGA_WRITEABLE);
5421 * Increment counters.
5423 if ((newpde & PG_W) != 0)
5424 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5425 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5428 * Map the superpage. (This is not a promoted mapping; there will not
5429 * be any lingering 4KB page mappings in the TLB.)
5431 pde_store(pde, newpde);
5433 atomic_add_long(&pmap_pde_mappings, 1);
5434 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5435 " in pmap %p", va, pmap);
5436 return (KERN_SUCCESS);
5440 * Maps a sequence of resident pages belonging to the same object.
5441 * The sequence begins with the given page m_start. This page is
5442 * mapped at the given virtual address start. Each subsequent page is
5443 * mapped at a virtual address that is offset from start by the same
5444 * amount as the page is offset from m_start within the object. The
5445 * last page in the sequence is the page with the largest offset from
5446 * m_start that can be mapped at a virtual address less than the given
5447 * virtual address end. Not every virtual page between start and end
5448 * is mapped; only those for which a resident page exists with the
5449 * corresponding offset from m_start are mapped.
5452 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5453 vm_page_t m_start, vm_prot_t prot)
5455 struct rwlock *lock;
5458 vm_pindex_t diff, psize;
5460 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5462 psize = atop(end - start);
5467 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5468 va = start + ptoa(diff);
5469 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5470 m->psind == 1 && pmap_ps_enabled(pmap) &&
5471 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5472 m = &m[NBPDR / PAGE_SIZE - 1];
5474 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5476 m = TAILQ_NEXT(m, listq);
5484 * this code makes some *MAJOR* assumptions:
5485 * 1. Current pmap & pmap exists.
5488 * 4. No page table pages.
5489 * but is *MUCH* faster than pmap_enter...
5493 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5495 struct rwlock *lock;
5499 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5506 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5507 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5509 struct spglist free;
5510 pt_entry_t newpte, *pte, PG_V;
5512 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5513 (m->oflags & VPO_UNMANAGED) != 0,
5514 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5515 PG_V = pmap_valid_bit(pmap);
5516 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5519 * In the case that a page table page is not
5520 * resident, we are creating it here.
5522 if (va < VM_MAXUSER_ADDRESS) {
5523 vm_pindex_t ptepindex;
5527 * Calculate pagetable page index
5529 ptepindex = pmap_pde_pindex(va);
5530 if (mpte && (mpte->pindex == ptepindex)) {
5534 * Get the page directory entry
5536 ptepa = pmap_pde(pmap, va);
5539 * If the page table page is mapped, we just increment
5540 * the hold count, and activate it. Otherwise, we
5541 * attempt to allocate a page table page. If this
5542 * attempt fails, we don't retry. Instead, we give up.
5544 if (ptepa && (*ptepa & PG_V) != 0) {
5547 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5551 * Pass NULL instead of the PV list lock
5552 * pointer, because we don't intend to sleep.
5554 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5559 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5560 pte = &pte[pmap_pte_index(va)];
5574 * Enter on the PV list if part of our managed memory.
5576 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5577 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5580 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5582 * Although "va" is not mapped, paging-
5583 * structure caches could nonetheless have
5584 * entries that refer to the freed page table
5585 * pages. Invalidate those entries.
5587 pmap_invalidate_page(pmap, va);
5588 vm_page_free_pages_toq(&free, true);
5596 * Increment counters
5598 pmap_resident_count_inc(pmap, 1);
5600 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
5601 pmap_cache_bits(pmap, m->md.pat_mode, 0);
5602 if ((m->oflags & VPO_UNMANAGED) == 0)
5603 newpte |= PG_MANAGED;
5604 if ((prot & VM_PROT_EXECUTE) == 0)
5606 if (va < VM_MAXUSER_ADDRESS)
5607 newpte |= PG_U | pmap_pkru_get(pmap, va);
5608 pte_store(pte, newpte);
5613 * Make a temporary mapping for a physical address. This is only intended
5614 * to be used for panic dumps.
5617 pmap_kenter_temporary(vm_paddr_t pa, int i)
5621 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5622 pmap_kenter(va, pa);
5624 return ((void *)crashdumpmap);
5628 * This code maps large physical mmap regions into the
5629 * processor address space. Note that some shortcuts
5630 * are taken, but the code works.
5633 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5634 vm_pindex_t pindex, vm_size_t size)
5637 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5638 vm_paddr_t pa, ptepa;
5642 PG_A = pmap_accessed_bit(pmap);
5643 PG_M = pmap_modified_bit(pmap);
5644 PG_V = pmap_valid_bit(pmap);
5645 PG_RW = pmap_rw_bit(pmap);
5647 VM_OBJECT_ASSERT_WLOCKED(object);
5648 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5649 ("pmap_object_init_pt: non-device object"));
5650 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5651 if (!pmap_ps_enabled(pmap))
5653 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5655 p = vm_page_lookup(object, pindex);
5656 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5657 ("pmap_object_init_pt: invalid page %p", p));
5658 pat_mode = p->md.pat_mode;
5661 * Abort the mapping if the first page is not physically
5662 * aligned to a 2MB page boundary.
5664 ptepa = VM_PAGE_TO_PHYS(p);
5665 if (ptepa & (NBPDR - 1))
5669 * Skip the first page. Abort the mapping if the rest of
5670 * the pages are not physically contiguous or have differing
5671 * memory attributes.
5673 p = TAILQ_NEXT(p, listq);
5674 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5676 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5677 ("pmap_object_init_pt: invalid page %p", p));
5678 if (pa != VM_PAGE_TO_PHYS(p) ||
5679 pat_mode != p->md.pat_mode)
5681 p = TAILQ_NEXT(p, listq);
5685 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5686 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5687 * will not affect the termination of this loop.
5690 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5691 pa < ptepa + size; pa += NBPDR) {
5692 pdpg = pmap_allocpde(pmap, addr, NULL);
5695 * The creation of mappings below is only an
5696 * optimization. If a page directory page
5697 * cannot be allocated without blocking,
5698 * continue on to the next mapping rather than
5704 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5705 pde = &pde[pmap_pde_index(addr)];
5706 if ((*pde & PG_V) == 0) {
5707 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5708 PG_U | PG_RW | PG_V);
5709 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5710 atomic_add_long(&pmap_pde_mappings, 1);
5712 /* Continue on if the PDE is already valid. */
5714 KASSERT(pdpg->wire_count > 0,
5715 ("pmap_object_init_pt: missing reference "
5716 "to page directory page, va: 0x%lx", addr));
5725 * Clear the wired attribute from the mappings for the specified range of
5726 * addresses in the given pmap. Every valid mapping within that range
5727 * must have the wired attribute set. In contrast, invalid mappings
5728 * cannot have the wired attribute set, so they are ignored.
5730 * The wired attribute of the page table entry is not a hardware
5731 * feature, so there is no need to invalidate any TLB entries.
5732 * Since pmap_demote_pde() for the wired entry must never fail,
5733 * pmap_delayed_invl_started()/finished() calls around the
5734 * function are not needed.
5737 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5739 vm_offset_t va_next;
5740 pml4_entry_t *pml4e;
5743 pt_entry_t *pte, PG_V;
5745 PG_V = pmap_valid_bit(pmap);
5747 for (; sva < eva; sva = va_next) {
5748 pml4e = pmap_pml4e(pmap, sva);
5749 if ((*pml4e & PG_V) == 0) {
5750 va_next = (sva + NBPML4) & ~PML4MASK;
5755 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5756 if ((*pdpe & PG_V) == 0) {
5757 va_next = (sva + NBPDP) & ~PDPMASK;
5762 va_next = (sva + NBPDR) & ~PDRMASK;
5765 pde = pmap_pdpe_to_pde(pdpe, sva);
5766 if ((*pde & PG_V) == 0)
5768 if ((*pde & PG_PS) != 0) {
5769 if ((*pde & PG_W) == 0)
5770 panic("pmap_unwire: pde %#jx is missing PG_W",
5774 * Are we unwiring the entire large page? If not,
5775 * demote the mapping and fall through.
5777 if (sva + NBPDR == va_next && eva >= va_next) {
5778 atomic_clear_long(pde, PG_W);
5779 pmap->pm_stats.wired_count -= NBPDR /
5782 } else if (!pmap_demote_pde(pmap, pde, sva))
5783 panic("pmap_unwire: demotion failed");
5787 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5789 if ((*pte & PG_V) == 0)
5791 if ((*pte & PG_W) == 0)
5792 panic("pmap_unwire: pte %#jx is missing PG_W",
5796 * PG_W must be cleared atomically. Although the pmap
5797 * lock synchronizes access to PG_W, another processor
5798 * could be setting PG_M and/or PG_A concurrently.
5800 atomic_clear_long(pte, PG_W);
5801 pmap->pm_stats.wired_count--;
5808 * Copy the range specified by src_addr/len
5809 * from the source map to the range dst_addr/len
5810 * in the destination map.
5812 * This routine is only advisory and need not do anything.
5816 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5817 vm_offset_t src_addr)
5819 struct rwlock *lock;
5820 struct spglist free;
5822 vm_offset_t end_addr = src_addr + len;
5823 vm_offset_t va_next;
5824 vm_page_t dst_pdpg, dstmpte, srcmpte;
5825 pt_entry_t PG_A, PG_M, PG_V;
5827 if (dst_addr != src_addr)
5830 if (dst_pmap->pm_type != src_pmap->pm_type)
5834 * EPT page table entries that require emulation of A/D bits are
5835 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5836 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5837 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5838 * implementations flag an EPT misconfiguration for exec-only
5839 * mappings we skip this function entirely for emulated pmaps.
5841 if (pmap_emulate_ad_bits(dst_pmap))
5845 if (dst_pmap < src_pmap) {
5846 PMAP_LOCK(dst_pmap);
5847 PMAP_LOCK(src_pmap);
5849 PMAP_LOCK(src_pmap);
5850 PMAP_LOCK(dst_pmap);
5853 PG_A = pmap_accessed_bit(dst_pmap);
5854 PG_M = pmap_modified_bit(dst_pmap);
5855 PG_V = pmap_valid_bit(dst_pmap);
5857 for (addr = src_addr; addr < end_addr; addr = va_next) {
5858 pt_entry_t *src_pte, *dst_pte;
5859 pml4_entry_t *pml4e;
5861 pd_entry_t srcptepaddr, *pde;
5863 KASSERT(addr < UPT_MIN_ADDRESS,
5864 ("pmap_copy: invalid to pmap_copy page tables"));
5866 pml4e = pmap_pml4e(src_pmap, addr);
5867 if ((*pml4e & PG_V) == 0) {
5868 va_next = (addr + NBPML4) & ~PML4MASK;
5874 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5875 if ((*pdpe & PG_V) == 0) {
5876 va_next = (addr + NBPDP) & ~PDPMASK;
5882 va_next = (addr + NBPDR) & ~PDRMASK;
5886 pde = pmap_pdpe_to_pde(pdpe, addr);
5888 if (srcptepaddr == 0)
5891 if (srcptepaddr & PG_PS) {
5892 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5894 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5895 if (dst_pdpg == NULL)
5897 pde = (pd_entry_t *)
5898 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5899 pde = &pde[pmap_pde_index(addr)];
5900 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5901 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5902 PMAP_ENTER_NORECLAIM, &lock))) {
5903 *pde = srcptepaddr & ~PG_W;
5904 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5905 atomic_add_long(&pmap_pde_mappings, 1);
5907 dst_pdpg->wire_count--;
5911 srcptepaddr &= PG_FRAME;
5912 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5913 KASSERT(srcmpte->wire_count > 0,
5914 ("pmap_copy: source page table page is unused"));
5916 if (va_next > end_addr)
5919 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5920 src_pte = &src_pte[pmap_pte_index(addr)];
5922 while (addr < va_next) {
5926 * we only virtual copy managed pages
5928 if ((ptetemp & PG_MANAGED) != 0) {
5929 if (dstmpte != NULL &&
5930 dstmpte->pindex == pmap_pde_pindex(addr))
5931 dstmpte->wire_count++;
5932 else if ((dstmpte = pmap_allocpte(dst_pmap,
5933 addr, NULL)) == NULL)
5935 dst_pte = (pt_entry_t *)
5936 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5937 dst_pte = &dst_pte[pmap_pte_index(addr)];
5938 if (*dst_pte == 0 &&
5939 pmap_try_insert_pv_entry(dst_pmap, addr,
5940 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5943 * Clear the wired, modified, and
5944 * accessed (referenced) bits
5947 *dst_pte = ptetemp & ~(PG_W | PG_M |
5949 pmap_resident_count_inc(dst_pmap, 1);
5952 if (pmap_unwire_ptp(dst_pmap, addr,
5955 * Although "addr" is not
5956 * mapped, paging-structure
5957 * caches could nonetheless
5958 * have entries that refer to
5959 * the freed page table pages.
5960 * Invalidate those entries.
5962 pmap_invalidate_page(dst_pmap,
5964 vm_page_free_pages_toq(&free,
5969 if (dstmpte->wire_count >= srcmpte->wire_count)
5979 PMAP_UNLOCK(src_pmap);
5980 PMAP_UNLOCK(dst_pmap);
5984 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
5988 if (dst_pmap->pm_type != src_pmap->pm_type ||
5989 dst_pmap->pm_type != PT_X86 ||
5990 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
5993 if (dst_pmap < src_pmap) {
5994 PMAP_LOCK(dst_pmap);
5995 PMAP_LOCK(src_pmap);
5997 PMAP_LOCK(src_pmap);
5998 PMAP_LOCK(dst_pmap);
6000 error = pmap_pkru_copy(dst_pmap, src_pmap);
6001 /* Clean up partial copy on failure due to no memory. */
6002 if (error == ENOMEM)
6003 pmap_pkru_deassign_all(dst_pmap);
6004 PMAP_UNLOCK(src_pmap);
6005 PMAP_UNLOCK(dst_pmap);
6006 if (error != ENOMEM)
6014 * Zero the specified hardware page.
6017 pmap_zero_page(vm_page_t m)
6019 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6021 pagezero((void *)va);
6025 * Zero an an area within a single hardware page. off and size must not
6026 * cover an area beyond a single hardware page.
6029 pmap_zero_page_area(vm_page_t m, int off, int size)
6031 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6033 if (off == 0 && size == PAGE_SIZE)
6034 pagezero((void *)va);
6036 bzero((char *)va + off, size);
6040 * Copy 1 specified hardware page to another.
6043 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6045 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6046 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6048 pagecopy((void *)src, (void *)dst);
6051 int unmapped_buf_allowed = 1;
6054 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6055 vm_offset_t b_offset, int xfersize)
6059 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6063 while (xfersize > 0) {
6064 a_pg_offset = a_offset & PAGE_MASK;
6065 pages[0] = ma[a_offset >> PAGE_SHIFT];
6066 b_pg_offset = b_offset & PAGE_MASK;
6067 pages[1] = mb[b_offset >> PAGE_SHIFT];
6068 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6069 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6070 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6071 a_cp = (char *)vaddr[0] + a_pg_offset;
6072 b_cp = (char *)vaddr[1] + b_pg_offset;
6073 bcopy(a_cp, b_cp, cnt);
6074 if (__predict_false(mapped))
6075 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6083 * Returns true if the pmap's pv is one of the first
6084 * 16 pvs linked to from this page. This count may
6085 * be changed upwards or downwards in the future; it
6086 * is only necessary that true be returned for a small
6087 * subset of pmaps for proper page aging.
6090 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6092 struct md_page *pvh;
6093 struct rwlock *lock;
6098 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6099 ("pmap_page_exists_quick: page %p is not managed", m));
6101 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6103 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6104 if (PV_PMAP(pv) == pmap) {
6112 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6113 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6114 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6115 if (PV_PMAP(pv) == pmap) {
6129 * pmap_page_wired_mappings:
6131 * Return the number of managed mappings to the given physical page
6135 pmap_page_wired_mappings(vm_page_t m)
6137 struct rwlock *lock;
6138 struct md_page *pvh;
6142 int count, md_gen, pvh_gen;
6144 if ((m->oflags & VPO_UNMANAGED) != 0)
6146 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6150 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6152 if (!PMAP_TRYLOCK(pmap)) {
6153 md_gen = m->md.pv_gen;
6157 if (md_gen != m->md.pv_gen) {
6162 pte = pmap_pte(pmap, pv->pv_va);
6163 if ((*pte & PG_W) != 0)
6167 if ((m->flags & PG_FICTITIOUS) == 0) {
6168 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6169 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6171 if (!PMAP_TRYLOCK(pmap)) {
6172 md_gen = m->md.pv_gen;
6173 pvh_gen = pvh->pv_gen;
6177 if (md_gen != m->md.pv_gen ||
6178 pvh_gen != pvh->pv_gen) {
6183 pte = pmap_pde(pmap, pv->pv_va);
6184 if ((*pte & PG_W) != 0)
6194 * Returns TRUE if the given page is mapped individually or as part of
6195 * a 2mpage. Otherwise, returns FALSE.
6198 pmap_page_is_mapped(vm_page_t m)
6200 struct rwlock *lock;
6203 if ((m->oflags & VPO_UNMANAGED) != 0)
6205 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6207 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6208 ((m->flags & PG_FICTITIOUS) == 0 &&
6209 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6215 * Destroy all managed, non-wired mappings in the given user-space
6216 * pmap. This pmap cannot be active on any processor besides the
6219 * This function cannot be applied to the kernel pmap. Moreover, it
6220 * is not intended for general use. It is only to be used during
6221 * process termination. Consequently, it can be implemented in ways
6222 * that make it faster than pmap_remove(). First, it can more quickly
6223 * destroy mappings by iterating over the pmap's collection of PV
6224 * entries, rather than searching the page table. Second, it doesn't
6225 * have to test and clear the page table entries atomically, because
6226 * no processor is currently accessing the user address space. In
6227 * particular, a page table entry's dirty bit won't change state once
6228 * this function starts.
6230 * Although this function destroys all of the pmap's managed,
6231 * non-wired mappings, it can delay and batch the invalidation of TLB
6232 * entries without calling pmap_delayed_invl_started() and
6233 * pmap_delayed_invl_finished(). Because the pmap is not active on
6234 * any other processor, none of these TLB entries will ever be used
6235 * before their eventual invalidation. Consequently, there is no need
6236 * for either pmap_remove_all() or pmap_remove_write() to wait for
6237 * that eventual TLB invalidation.
6240 pmap_remove_pages(pmap_t pmap)
6243 pt_entry_t *pte, tpte;
6244 pt_entry_t PG_M, PG_RW, PG_V;
6245 struct spglist free;
6246 vm_page_t m, mpte, mt;
6248 struct md_page *pvh;
6249 struct pv_chunk *pc, *npc;
6250 struct rwlock *lock;
6252 uint64_t inuse, bitmask;
6253 int allfree, field, freed, idx;
6254 boolean_t superpage;
6258 * Assert that the given pmap is only active on the current
6259 * CPU. Unfortunately, we cannot block another CPU from
6260 * activating the pmap while this function is executing.
6262 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6265 cpuset_t other_cpus;
6267 other_cpus = all_cpus;
6269 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6270 CPU_AND(&other_cpus, &pmap->pm_active);
6272 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6277 PG_M = pmap_modified_bit(pmap);
6278 PG_V = pmap_valid_bit(pmap);
6279 PG_RW = pmap_rw_bit(pmap);
6283 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6286 for (field = 0; field < _NPCM; field++) {
6287 inuse = ~pc->pc_map[field] & pc_freemask[field];
6288 while (inuse != 0) {
6290 bitmask = 1UL << bit;
6291 idx = field * 64 + bit;
6292 pv = &pc->pc_pventry[idx];
6295 pte = pmap_pdpe(pmap, pv->pv_va);
6297 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6299 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6302 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6304 pte = &pte[pmap_pte_index(pv->pv_va)];
6308 * Keep track whether 'tpte' is a
6309 * superpage explicitly instead of
6310 * relying on PG_PS being set.
6312 * This is because PG_PS is numerically
6313 * identical to PG_PTE_PAT and thus a
6314 * regular page could be mistaken for
6320 if ((tpte & PG_V) == 0) {
6321 panic("bad pte va %lx pte %lx",
6326 * We cannot remove wired pages from a process' mapping at this time
6334 pa = tpte & PG_PS_FRAME;
6336 pa = tpte & PG_FRAME;
6338 m = PHYS_TO_VM_PAGE(pa);
6339 KASSERT(m->phys_addr == pa,
6340 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6341 m, (uintmax_t)m->phys_addr,
6344 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6345 m < &vm_page_array[vm_page_array_size],
6346 ("pmap_remove_pages: bad tpte %#jx",
6352 * Update the vm_page_t clean/reference bits.
6354 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6356 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6362 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6365 pc->pc_map[field] |= bitmask;
6367 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6368 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6369 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6371 if (TAILQ_EMPTY(&pvh->pv_list)) {
6372 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6373 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6374 TAILQ_EMPTY(&mt->md.pv_list))
6375 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6377 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6379 pmap_resident_count_dec(pmap, 1);
6380 KASSERT(mpte->wire_count == NPTEPG,
6381 ("pmap_remove_pages: pte page wire count error"));
6382 mpte->wire_count = 0;
6383 pmap_add_delayed_free_list(mpte, &free, FALSE);
6386 pmap_resident_count_dec(pmap, 1);
6387 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6389 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6390 TAILQ_EMPTY(&m->md.pv_list) &&
6391 (m->flags & PG_FICTITIOUS) == 0) {
6392 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6393 if (TAILQ_EMPTY(&pvh->pv_list))
6394 vm_page_aflag_clear(m, PGA_WRITEABLE);
6397 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6401 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6402 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6403 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6405 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6411 pmap_invalidate_all(pmap);
6412 pmap_pkru_deassign_all(pmap);
6414 vm_page_free_pages_toq(&free, true);
6418 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6420 struct rwlock *lock;
6422 struct md_page *pvh;
6423 pt_entry_t *pte, mask;
6424 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6426 int md_gen, pvh_gen;
6430 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6433 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6435 if (!PMAP_TRYLOCK(pmap)) {
6436 md_gen = m->md.pv_gen;
6440 if (md_gen != m->md.pv_gen) {
6445 pte = pmap_pte(pmap, pv->pv_va);
6448 PG_M = pmap_modified_bit(pmap);
6449 PG_RW = pmap_rw_bit(pmap);
6450 mask |= PG_RW | PG_M;
6453 PG_A = pmap_accessed_bit(pmap);
6454 PG_V = pmap_valid_bit(pmap);
6455 mask |= PG_V | PG_A;
6457 rv = (*pte & mask) == mask;
6462 if ((m->flags & PG_FICTITIOUS) == 0) {
6463 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6464 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6466 if (!PMAP_TRYLOCK(pmap)) {
6467 md_gen = m->md.pv_gen;
6468 pvh_gen = pvh->pv_gen;
6472 if (md_gen != m->md.pv_gen ||
6473 pvh_gen != pvh->pv_gen) {
6478 pte = pmap_pde(pmap, pv->pv_va);
6481 PG_M = pmap_modified_bit(pmap);
6482 PG_RW = pmap_rw_bit(pmap);
6483 mask |= PG_RW | PG_M;
6486 PG_A = pmap_accessed_bit(pmap);
6487 PG_V = pmap_valid_bit(pmap);
6488 mask |= PG_V | PG_A;
6490 rv = (*pte & mask) == mask;
6504 * Return whether or not the specified physical page was modified
6505 * in any physical maps.
6508 pmap_is_modified(vm_page_t m)
6511 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6512 ("pmap_is_modified: page %p is not managed", m));
6515 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6516 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6517 * is clear, no PTEs can have PG_M set.
6519 VM_OBJECT_ASSERT_WLOCKED(m->object);
6520 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6522 return (pmap_page_test_mappings(m, FALSE, TRUE));
6526 * pmap_is_prefaultable:
6528 * Return whether or not the specified virtual address is eligible
6532 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6535 pt_entry_t *pte, PG_V;
6538 PG_V = pmap_valid_bit(pmap);
6541 pde = pmap_pde(pmap, addr);
6542 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6543 pte = pmap_pde_to_pte(pde, addr);
6544 rv = (*pte & PG_V) == 0;
6551 * pmap_is_referenced:
6553 * Return whether or not the specified physical page was referenced
6554 * in any physical maps.
6557 pmap_is_referenced(vm_page_t m)
6560 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6561 ("pmap_is_referenced: page %p is not managed", m));
6562 return (pmap_page_test_mappings(m, TRUE, FALSE));
6566 * Clear the write and modified bits in each of the given page's mappings.
6569 pmap_remove_write(vm_page_t m)
6571 struct md_page *pvh;
6573 struct rwlock *lock;
6574 pv_entry_t next_pv, pv;
6576 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6578 int pvh_gen, md_gen;
6580 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6581 ("pmap_remove_write: page %p is not managed", m));
6584 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6585 * set by another thread while the object is locked. Thus,
6586 * if PGA_WRITEABLE is clear, no page table entries need updating.
6588 VM_OBJECT_ASSERT_WLOCKED(m->object);
6589 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6591 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6592 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6593 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6596 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6598 if (!PMAP_TRYLOCK(pmap)) {
6599 pvh_gen = pvh->pv_gen;
6603 if (pvh_gen != pvh->pv_gen) {
6609 PG_RW = pmap_rw_bit(pmap);
6611 pde = pmap_pde(pmap, va);
6612 if ((*pde & PG_RW) != 0)
6613 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6614 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6615 ("inconsistent pv lock %p %p for page %p",
6616 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6619 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6621 if (!PMAP_TRYLOCK(pmap)) {
6622 pvh_gen = pvh->pv_gen;
6623 md_gen = m->md.pv_gen;
6627 if (pvh_gen != pvh->pv_gen ||
6628 md_gen != m->md.pv_gen) {
6634 PG_M = pmap_modified_bit(pmap);
6635 PG_RW = pmap_rw_bit(pmap);
6636 pde = pmap_pde(pmap, pv->pv_va);
6637 KASSERT((*pde & PG_PS) == 0,
6638 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6640 pte = pmap_pde_to_pte(pde, pv->pv_va);
6643 if (oldpte & PG_RW) {
6644 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6647 if ((oldpte & PG_M) != 0)
6649 pmap_invalidate_page(pmap, pv->pv_va);
6654 vm_page_aflag_clear(m, PGA_WRITEABLE);
6655 pmap_delayed_invl_wait(m);
6658 static __inline boolean_t
6659 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6662 if (!pmap_emulate_ad_bits(pmap))
6665 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6668 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6669 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6670 * if the EPT_PG_WRITE bit is set.
6672 if ((pte & EPT_PG_WRITE) != 0)
6676 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6678 if ((pte & EPT_PG_EXECUTE) == 0 ||
6679 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6686 * pmap_ts_referenced:
6688 * Return a count of reference bits for a page, clearing those bits.
6689 * It is not necessary for every reference bit to be cleared, but it
6690 * is necessary that 0 only be returned when there are truly no
6691 * reference bits set.
6693 * As an optimization, update the page's dirty field if a modified bit is
6694 * found while counting reference bits. This opportunistic update can be
6695 * performed at low cost and can eliminate the need for some future calls
6696 * to pmap_is_modified(). However, since this function stops after
6697 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6698 * dirty pages. Those dirty pages will only be detected by a future call
6699 * to pmap_is_modified().
6701 * A DI block is not needed within this function, because
6702 * invalidations are performed before the PV list lock is
6706 pmap_ts_referenced(vm_page_t m)
6708 struct md_page *pvh;
6711 struct rwlock *lock;
6712 pd_entry_t oldpde, *pde;
6713 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6716 int cleared, md_gen, not_cleared, pvh_gen;
6717 struct spglist free;
6720 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6721 ("pmap_ts_referenced: page %p is not managed", m));
6724 pa = VM_PAGE_TO_PHYS(m);
6725 lock = PHYS_TO_PV_LIST_LOCK(pa);
6726 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6730 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6731 goto small_mappings;
6737 if (!PMAP_TRYLOCK(pmap)) {
6738 pvh_gen = pvh->pv_gen;
6742 if (pvh_gen != pvh->pv_gen) {
6747 PG_A = pmap_accessed_bit(pmap);
6748 PG_M = pmap_modified_bit(pmap);
6749 PG_RW = pmap_rw_bit(pmap);
6751 pde = pmap_pde(pmap, pv->pv_va);
6753 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6755 * Although "oldpde" is mapping a 2MB page, because
6756 * this function is called at a 4KB page granularity,
6757 * we only update the 4KB page under test.
6761 if ((oldpde & PG_A) != 0) {
6763 * Since this reference bit is shared by 512 4KB
6764 * pages, it should not be cleared every time it is
6765 * tested. Apply a simple "hash" function on the
6766 * physical page number, the virtual superpage number,
6767 * and the pmap address to select one 4KB page out of
6768 * the 512 on which testing the reference bit will
6769 * result in clearing that reference bit. This
6770 * function is designed to avoid the selection of the
6771 * same 4KB page for every 2MB page mapping.
6773 * On demotion, a mapping that hasn't been referenced
6774 * is simply destroyed. To avoid the possibility of a
6775 * subsequent page fault on a demoted wired mapping,
6776 * always leave its reference bit set. Moreover,
6777 * since the superpage is wired, the current state of
6778 * its reference bit won't affect page replacement.
6780 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6781 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6782 (oldpde & PG_W) == 0) {
6783 if (safe_to_clear_referenced(pmap, oldpde)) {
6784 atomic_clear_long(pde, PG_A);
6785 pmap_invalidate_page(pmap, pv->pv_va);
6787 } else if (pmap_demote_pde_locked(pmap, pde,
6788 pv->pv_va, &lock)) {
6790 * Remove the mapping to a single page
6791 * so that a subsequent access may
6792 * repromote. Since the underlying
6793 * page table page is fully populated,
6794 * this removal never frees a page
6798 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6800 pte = pmap_pde_to_pte(pde, va);
6801 pmap_remove_pte(pmap, pte, va, *pde,
6803 pmap_invalidate_page(pmap, va);
6809 * The superpage mapping was removed
6810 * entirely and therefore 'pv' is no
6818 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6819 ("inconsistent pv lock %p %p for page %p",
6820 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6825 /* Rotate the PV list if it has more than one entry. */
6826 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6827 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6828 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6831 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6833 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6835 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6842 if (!PMAP_TRYLOCK(pmap)) {
6843 pvh_gen = pvh->pv_gen;
6844 md_gen = m->md.pv_gen;
6848 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6853 PG_A = pmap_accessed_bit(pmap);
6854 PG_M = pmap_modified_bit(pmap);
6855 PG_RW = pmap_rw_bit(pmap);
6856 pde = pmap_pde(pmap, pv->pv_va);
6857 KASSERT((*pde & PG_PS) == 0,
6858 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6860 pte = pmap_pde_to_pte(pde, pv->pv_va);
6861 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6863 if ((*pte & PG_A) != 0) {
6864 if (safe_to_clear_referenced(pmap, *pte)) {
6865 atomic_clear_long(pte, PG_A);
6866 pmap_invalidate_page(pmap, pv->pv_va);
6868 } else if ((*pte & PG_W) == 0) {
6870 * Wired pages cannot be paged out so
6871 * doing accessed bit emulation for
6872 * them is wasted effort. We do the
6873 * hard work for unwired pages only.
6875 pmap_remove_pte(pmap, pte, pv->pv_va,
6876 *pde, &free, &lock);
6877 pmap_invalidate_page(pmap, pv->pv_va);
6882 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6883 ("inconsistent pv lock %p %p for page %p",
6884 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6889 /* Rotate the PV list if it has more than one entry. */
6890 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6891 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6892 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6895 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6896 not_cleared < PMAP_TS_REFERENCED_MAX);
6899 vm_page_free_pages_toq(&free, true);
6900 return (cleared + not_cleared);
6904 * Apply the given advice to the specified range of addresses within the
6905 * given pmap. Depending on the advice, clear the referenced and/or
6906 * modified flags in each mapping and set the mapped page's dirty field.
6909 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6911 struct rwlock *lock;
6912 pml4_entry_t *pml4e;
6914 pd_entry_t oldpde, *pde;
6915 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6916 vm_offset_t va, va_next;
6918 boolean_t anychanged;
6920 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6924 * A/D bit emulation requires an alternate code path when clearing
6925 * the modified and accessed bits below. Since this function is
6926 * advisory in nature we skip it entirely for pmaps that require
6927 * A/D bit emulation.
6929 if (pmap_emulate_ad_bits(pmap))
6932 PG_A = pmap_accessed_bit(pmap);
6933 PG_G = pmap_global_bit(pmap);
6934 PG_M = pmap_modified_bit(pmap);
6935 PG_V = pmap_valid_bit(pmap);
6936 PG_RW = pmap_rw_bit(pmap);
6938 pmap_delayed_invl_started();
6940 for (; sva < eva; sva = va_next) {
6941 pml4e = pmap_pml4e(pmap, sva);
6942 if ((*pml4e & PG_V) == 0) {
6943 va_next = (sva + NBPML4) & ~PML4MASK;
6948 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6949 if ((*pdpe & PG_V) == 0) {
6950 va_next = (sva + NBPDP) & ~PDPMASK;
6955 va_next = (sva + NBPDR) & ~PDRMASK;
6958 pde = pmap_pdpe_to_pde(pdpe, sva);
6960 if ((oldpde & PG_V) == 0)
6962 else if ((oldpde & PG_PS) != 0) {
6963 if ((oldpde & PG_MANAGED) == 0)
6966 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6971 * The large page mapping was destroyed.
6977 * Unless the page mappings are wired, remove the
6978 * mapping to a single page so that a subsequent
6979 * access may repromote. Since the underlying page
6980 * table page is fully populated, this removal never
6981 * frees a page table page.
6983 if ((oldpde & PG_W) == 0) {
6984 pte = pmap_pde_to_pte(pde, sva);
6985 KASSERT((*pte & PG_V) != 0,
6986 ("pmap_advise: invalid PTE"));
6987 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6997 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6999 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7001 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7002 if (advice == MADV_DONTNEED) {
7004 * Future calls to pmap_is_modified()
7005 * can be avoided by making the page
7008 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7011 atomic_clear_long(pte, PG_M | PG_A);
7012 } else if ((*pte & PG_A) != 0)
7013 atomic_clear_long(pte, PG_A);
7017 if ((*pte & PG_G) != 0) {
7024 if (va != va_next) {
7025 pmap_invalidate_range(pmap, va, sva);
7030 pmap_invalidate_range(pmap, va, sva);
7033 pmap_invalidate_all(pmap);
7035 pmap_delayed_invl_finished();
7039 * Clear the modify bits on the specified physical page.
7042 pmap_clear_modify(vm_page_t m)
7044 struct md_page *pvh;
7046 pv_entry_t next_pv, pv;
7047 pd_entry_t oldpde, *pde;
7048 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
7049 struct rwlock *lock;
7051 int md_gen, pvh_gen;
7053 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7054 ("pmap_clear_modify: page %p is not managed", m));
7055 VM_OBJECT_ASSERT_WLOCKED(m->object);
7056 KASSERT(!vm_page_xbusied(m),
7057 ("pmap_clear_modify: page %p is exclusive busied", m));
7060 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7061 * If the object containing the page is locked and the page is not
7062 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7064 if ((m->aflags & PGA_WRITEABLE) == 0)
7066 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7067 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7068 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7071 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7073 if (!PMAP_TRYLOCK(pmap)) {
7074 pvh_gen = pvh->pv_gen;
7078 if (pvh_gen != pvh->pv_gen) {
7083 PG_M = pmap_modified_bit(pmap);
7084 PG_V = pmap_valid_bit(pmap);
7085 PG_RW = pmap_rw_bit(pmap);
7087 pde = pmap_pde(pmap, va);
7089 if ((oldpde & PG_RW) != 0) {
7090 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
7091 if ((oldpde & PG_W) == 0) {
7093 * Write protect the mapping to a
7094 * single page so that a subsequent
7095 * write access may repromote.
7097 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7099 pte = pmap_pde_to_pte(pde, va);
7101 if ((oldpte & PG_V) != 0) {
7102 while (!atomic_cmpset_long(pte,
7104 oldpte & ~(PG_M | PG_RW)))
7107 pmap_invalidate_page(pmap, va);
7114 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7116 if (!PMAP_TRYLOCK(pmap)) {
7117 md_gen = m->md.pv_gen;
7118 pvh_gen = pvh->pv_gen;
7122 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7127 PG_M = pmap_modified_bit(pmap);
7128 PG_RW = pmap_rw_bit(pmap);
7129 pde = pmap_pde(pmap, pv->pv_va);
7130 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7131 " a 2mpage in page %p's pv list", m));
7132 pte = pmap_pde_to_pte(pde, pv->pv_va);
7133 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7134 atomic_clear_long(pte, PG_M);
7135 pmap_invalidate_page(pmap, pv->pv_va);
7143 * Miscellaneous support routines follow
7146 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7147 static __inline void
7148 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7153 * The cache mode bits are all in the low 32-bits of the
7154 * PTE, so we can just spin on updating the low 32-bits.
7157 opte = *(u_int *)pte;
7158 npte = opte & ~mask;
7160 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7163 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7164 static __inline void
7165 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7170 * The cache mode bits are all in the low 32-bits of the
7171 * PDE, so we can just spin on updating the low 32-bits.
7174 opde = *(u_int *)pde;
7175 npde = opde & ~mask;
7177 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7181 * Map a set of physical memory pages into the kernel virtual
7182 * address space. Return a pointer to where it is mapped. This
7183 * routine is intended to be used for mapping device memory,
7187 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, bool noflush)
7189 struct pmap_preinit_mapping *ppim;
7190 vm_offset_t va, offset;
7194 offset = pa & PAGE_MASK;
7195 size = round_page(offset + size);
7196 pa = trunc_page(pa);
7198 if (!pmap_initialized) {
7200 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7201 ppim = pmap_preinit_mapping + i;
7202 if (ppim->va == 0) {
7206 ppim->va = virtual_avail;
7207 virtual_avail += size;
7213 panic("%s: too many preinit mappings", __func__);
7216 * If we have a preinit mapping, re-use it.
7218 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7219 ppim = pmap_preinit_mapping + i;
7220 if (ppim->pa == pa && ppim->sz == size &&
7222 return ((void *)(ppim->va + offset));
7225 * If the specified range of physical addresses fits within
7226 * the direct map window, use the direct map.
7228 if (pa < dmaplimit && pa + size <= dmaplimit) {
7229 va = PHYS_TO_DMAP(pa);
7230 PMAP_LOCK(kernel_pmap);
7231 i = pmap_change_attr_locked(va, size, mode, noflush);
7232 PMAP_UNLOCK(kernel_pmap);
7234 return ((void *)(va + offset));
7236 va = kva_alloc(size);
7238 panic("%s: Couldn't allocate KVA", __func__);
7240 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7241 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7242 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7244 pmap_invalidate_cache_range(va, va + tmpsize);
7245 return ((void *)(va + offset));
7249 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7252 return (pmap_mapdev_internal(pa, size, mode, false));
7256 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7259 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, false));
7263 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7266 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, true));
7270 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7273 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK, false));
7277 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7279 struct pmap_preinit_mapping *ppim;
7283 /* If we gave a direct map region in pmap_mapdev, do nothing */
7284 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7286 offset = va & PAGE_MASK;
7287 size = round_page(offset + size);
7288 va = trunc_page(va);
7289 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7290 ppim = pmap_preinit_mapping + i;
7291 if (ppim->va == va && ppim->sz == size) {
7292 if (pmap_initialized)
7298 if (va + size == virtual_avail)
7303 if (pmap_initialized)
7308 * Tries to demote a 1GB page mapping.
7311 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7313 pdp_entry_t newpdpe, oldpdpe;
7314 pd_entry_t *firstpde, newpde, *pde;
7315 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7319 PG_A = pmap_accessed_bit(pmap);
7320 PG_M = pmap_modified_bit(pmap);
7321 PG_V = pmap_valid_bit(pmap);
7322 PG_RW = pmap_rw_bit(pmap);
7324 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7326 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7327 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7328 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7329 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7330 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7331 " in pmap %p", va, pmap);
7334 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7335 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7336 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7337 KASSERT((oldpdpe & PG_A) != 0,
7338 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7339 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7340 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7344 * Initialize the page directory page.
7346 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7352 * Demote the mapping.
7357 * Invalidate a stale recursive mapping of the page directory page.
7359 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7361 pmap_pdpe_demotions++;
7362 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7363 " in pmap %p", va, pmap);
7368 * Sets the memory attribute for the specified page.
7371 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7374 m->md.pat_mode = ma;
7377 * If "m" is a normal page, update its direct mapping. This update
7378 * can be relied upon to perform any cache operations that are
7379 * required for data coherence.
7381 if ((m->flags & PG_FICTITIOUS) == 0 &&
7382 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7384 panic("memory attribute change on the direct map failed");
7388 * Changes the specified virtual address range's memory type to that given by
7389 * the parameter "mode". The specified virtual address range must be
7390 * completely contained within either the direct map or the kernel map. If
7391 * the virtual address range is contained within the kernel map, then the
7392 * memory type for each of the corresponding ranges of the direct map is also
7393 * changed. (The corresponding ranges of the direct map are those ranges that
7394 * map the same physical pages as the specified virtual address range.) These
7395 * changes to the direct map are necessary because Intel describes the
7396 * behavior of their processors as "undefined" if two or more mappings to the
7397 * same physical page have different memory types.
7399 * Returns zero if the change completed successfully, and either EINVAL or
7400 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7401 * of the virtual address range was not mapped, and ENOMEM is returned if
7402 * there was insufficient memory available to complete the change. In the
7403 * latter case, the memory type may have been changed on some part of the
7404 * virtual address range or the direct map.
7407 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7411 PMAP_LOCK(kernel_pmap);
7412 error = pmap_change_attr_locked(va, size, mode, false);
7413 PMAP_UNLOCK(kernel_pmap);
7418 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, bool noflush)
7420 vm_offset_t base, offset, tmpva;
7421 vm_paddr_t pa_start, pa_end, pa_end1;
7425 int cache_bits_pte, cache_bits_pde, error;
7428 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7429 base = trunc_page(va);
7430 offset = va & PAGE_MASK;
7431 size = round_page(offset + size);
7434 * Only supported on kernel virtual addresses, including the direct
7435 * map but excluding the recursive map.
7437 if (base < DMAP_MIN_ADDRESS)
7440 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7441 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7445 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7446 * into 4KB pages if required.
7448 for (tmpva = base; tmpva < base + size; ) {
7449 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7450 if (pdpe == NULL || *pdpe == 0)
7452 if (*pdpe & PG_PS) {
7454 * If the current 1GB page already has the required
7455 * memory type, then we need not demote this page. Just
7456 * increment tmpva to the next 1GB page frame.
7458 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7459 tmpva = trunc_1gpage(tmpva) + NBPDP;
7464 * If the current offset aligns with a 1GB page frame
7465 * and there is at least 1GB left within the range, then
7466 * we need not break down this page into 2MB pages.
7468 if ((tmpva & PDPMASK) == 0 &&
7469 tmpva + PDPMASK < base + size) {
7473 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7476 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7481 * If the current 2MB page already has the required
7482 * memory type, then we need not demote this page. Just
7483 * increment tmpva to the next 2MB page frame.
7485 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7486 tmpva = trunc_2mpage(tmpva) + NBPDR;
7491 * If the current offset aligns with a 2MB page frame
7492 * and there is at least 2MB left within the range, then
7493 * we need not break down this page into 4KB pages.
7495 if ((tmpva & PDRMASK) == 0 &&
7496 tmpva + PDRMASK < base + size) {
7500 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7503 pte = pmap_pde_to_pte(pde, tmpva);
7511 * Ok, all the pages exist, so run through them updating their
7512 * cache mode if required.
7514 pa_start = pa_end = 0;
7515 for (tmpva = base; tmpva < base + size; ) {
7516 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7517 if (*pdpe & PG_PS) {
7518 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7519 pmap_pde_attr(pdpe, cache_bits_pde,
7523 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7524 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7525 if (pa_start == pa_end) {
7526 /* Start physical address run. */
7527 pa_start = *pdpe & PG_PS_FRAME;
7528 pa_end = pa_start + NBPDP;
7529 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7532 /* Run ended, update direct map. */
7533 error = pmap_change_attr_locked(
7534 PHYS_TO_DMAP(pa_start),
7535 pa_end - pa_start, mode, noflush);
7538 /* Start physical address run. */
7539 pa_start = *pdpe & PG_PS_FRAME;
7540 pa_end = pa_start + NBPDP;
7543 tmpva = trunc_1gpage(tmpva) + NBPDP;
7546 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7548 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7549 pmap_pde_attr(pde, cache_bits_pde,
7553 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7554 (*pde & PG_PS_FRAME) < dmaplimit) {
7555 if (pa_start == pa_end) {
7556 /* Start physical address run. */
7557 pa_start = *pde & PG_PS_FRAME;
7558 pa_end = pa_start + NBPDR;
7559 } else if (pa_end == (*pde & PG_PS_FRAME))
7562 /* Run ended, update direct map. */
7563 error = pmap_change_attr_locked(
7564 PHYS_TO_DMAP(pa_start),
7565 pa_end - pa_start, mode, noflush);
7568 /* Start physical address run. */
7569 pa_start = *pde & PG_PS_FRAME;
7570 pa_end = pa_start + NBPDR;
7573 tmpva = trunc_2mpage(tmpva) + NBPDR;
7575 pte = pmap_pde_to_pte(pde, tmpva);
7576 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7577 pmap_pte_attr(pte, cache_bits_pte,
7581 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7582 (*pte & PG_FRAME) < dmaplimit) {
7583 if (pa_start == pa_end) {
7584 /* Start physical address run. */
7585 pa_start = *pte & PG_FRAME;
7586 pa_end = pa_start + PAGE_SIZE;
7587 } else if (pa_end == (*pte & PG_FRAME))
7588 pa_end += PAGE_SIZE;
7590 /* Run ended, update direct map. */
7591 error = pmap_change_attr_locked(
7592 PHYS_TO_DMAP(pa_start),
7593 pa_end - pa_start, mode, noflush);
7596 /* Start physical address run. */
7597 pa_start = *pte & PG_FRAME;
7598 pa_end = pa_start + PAGE_SIZE;
7604 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7605 pa_end1 = MIN(pa_end, dmaplimit);
7606 if (pa_start != pa_end1)
7607 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7608 pa_end1 - pa_start, mode, noflush);
7612 * Flush CPU caches if required to make sure any data isn't cached that
7613 * shouldn't be, etc.
7616 pmap_invalidate_range(kernel_pmap, base, tmpva);
7618 pmap_invalidate_cache_range(base, tmpva);
7624 * Demotes any mapping within the direct map region that covers more than the
7625 * specified range of physical addresses. This range's size must be a power
7626 * of two and its starting address must be a multiple of its size. Since the
7627 * demotion does not change any attributes of the mapping, a TLB invalidation
7628 * is not mandatory. The caller may, however, request a TLB invalidation.
7631 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7640 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7641 KASSERT((base & (len - 1)) == 0,
7642 ("pmap_demote_DMAP: base is not a multiple of len"));
7643 if (len < NBPDP && base < dmaplimit) {
7644 va = PHYS_TO_DMAP(base);
7646 PMAP_LOCK(kernel_pmap);
7647 pdpe = pmap_pdpe(kernel_pmap, va);
7648 if ((*pdpe & X86_PG_V) == 0)
7649 panic("pmap_demote_DMAP: invalid PDPE");
7650 if ((*pdpe & PG_PS) != 0) {
7651 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7652 panic("pmap_demote_DMAP: PDPE failed");
7656 pde = pmap_pdpe_to_pde(pdpe, va);
7657 if ((*pde & X86_PG_V) == 0)
7658 panic("pmap_demote_DMAP: invalid PDE");
7659 if ((*pde & PG_PS) != 0) {
7660 if (!pmap_demote_pde(kernel_pmap, pde, va))
7661 panic("pmap_demote_DMAP: PDE failed");
7665 if (changed && invalidate)
7666 pmap_invalidate_page(kernel_pmap, va);
7667 PMAP_UNLOCK(kernel_pmap);
7672 * perform the pmap work for mincore
7675 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7678 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7682 PG_A = pmap_accessed_bit(pmap);
7683 PG_M = pmap_modified_bit(pmap);
7684 PG_V = pmap_valid_bit(pmap);
7685 PG_RW = pmap_rw_bit(pmap);
7689 pdep = pmap_pde(pmap, addr);
7690 if (pdep != NULL && (*pdep & PG_V)) {
7691 if (*pdep & PG_PS) {
7693 /* Compute the physical address of the 4KB page. */
7694 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7696 val = MINCORE_SUPER;
7698 pte = *pmap_pde_to_pte(pdep, addr);
7699 pa = pte & PG_FRAME;
7707 if ((pte & PG_V) != 0) {
7708 val |= MINCORE_INCORE;
7709 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7710 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7711 if ((pte & PG_A) != 0)
7712 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7714 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7715 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7716 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7717 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7718 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7721 PA_UNLOCK_COND(*locked_pa);
7727 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7729 uint32_t gen, new_gen, pcid_next;
7731 CRITICAL_ASSERT(curthread);
7732 gen = PCPU_GET(pcid_gen);
7733 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7734 return (pti ? 0 : CR3_PCID_SAVE);
7735 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7736 return (CR3_PCID_SAVE);
7737 pcid_next = PCPU_GET(pcid_next);
7738 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7739 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7740 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7741 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7742 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7746 PCPU_SET(pcid_gen, new_gen);
7747 pcid_next = PMAP_PCID_KERN + 1;
7751 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7752 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7753 PCPU_SET(pcid_next, pcid_next + 1);
7758 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
7762 cached = pmap_pcid_alloc(pmap, cpuid);
7763 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7764 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7765 pmap->pm_pcids[cpuid].pm_pcid));
7766 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7767 pmap == kernel_pmap,
7768 ("non-kernel pmap pmap %p cpu %d pcid %#x",
7769 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7774 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
7777 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
7778 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
7782 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
7784 struct invpcid_descr d;
7785 uint64_t cached, cr3, kcr3, ucr3;
7787 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7789 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7790 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
7791 PCPU_SET(curpmap, pmap);
7792 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7793 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7796 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7798 * Explicitly invalidate translations cached from the
7799 * user page table. They are not automatically
7800 * flushed by reload of cr3 with the kernel page table
7803 * Note that the if() condition is resolved statically
7804 * by using the function argument instead of
7805 * runtime-evaluated invpcid_works value.
7807 if (invpcid_works1) {
7808 d.pcid = PMAP_PCID_USER_PT |
7809 pmap->pm_pcids[cpuid].pm_pcid;
7812 invpcid(&d, INVPCID_CTX);
7814 pmap_pti_pcid_invalidate(ucr3, kcr3);
7818 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7819 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7821 PCPU_INC(pm_save_cnt);
7825 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
7828 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
7829 pmap_activate_sw_pti_post(td, pmap);
7833 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
7839 * If the INVPCID instruction is not available,
7840 * invltlb_pcid_handler() is used to handle an invalidate_all
7841 * IPI, which checks for curpmap == smp_tlb_pmap. The below
7842 * sequence of operations has a window where %CR3 is loaded
7843 * with the new pmap's PML4 address, but the curpmap value has
7844 * not yet been updated. This causes the invltlb IPI handler,
7845 * which is called between the updates, to execute as a NOP,
7846 * which leaves stale TLB entries.
7848 * Note that the most typical use of pmap_activate_sw(), from
7849 * the context switch, is immune to this race, because
7850 * interrupts are disabled (while the thread lock is owned),
7851 * and the IPI happens after curpmap is updated. Protect
7852 * other callers in a similar way, by disabling interrupts
7853 * around the %cr3 register reload and curpmap assignment.
7855 rflags = intr_disable();
7856 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
7857 intr_restore(rflags);
7858 pmap_activate_sw_pti_post(td, pmap);
7862 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
7865 uint64_t cached, cr3;
7867 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7869 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7870 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7872 PCPU_SET(curpmap, pmap);
7874 PCPU_INC(pm_save_cnt);
7878 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
7883 rflags = intr_disable();
7884 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
7885 intr_restore(rflags);
7889 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
7890 u_int cpuid __unused)
7893 load_cr3(pmap->pm_cr3);
7894 PCPU_SET(curpmap, pmap);
7898 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
7899 u_int cpuid __unused)
7902 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
7903 PCPU_SET(kcr3, pmap->pm_cr3);
7904 PCPU_SET(ucr3, pmap->pm_ucr3);
7905 pmap_activate_sw_pti_post(td, pmap);
7908 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
7912 if (pmap_pcid_enabled && pti && invpcid_works)
7913 return (pmap_activate_sw_pcid_invpcid_pti);
7914 else if (pmap_pcid_enabled && pti && !invpcid_works)
7915 return (pmap_activate_sw_pcid_noinvpcid_pti);
7916 else if (pmap_pcid_enabled && !pti && invpcid_works)
7917 return (pmap_activate_sw_pcid_nopti);
7918 else if (pmap_pcid_enabled && !pti && !invpcid_works)
7919 return (pmap_activate_sw_pcid_noinvpcid_nopti);
7920 else if (!pmap_pcid_enabled && pti)
7921 return (pmap_activate_sw_nopcid_pti);
7922 else /* if (!pmap_pcid_enabled && !pti) */
7923 return (pmap_activate_sw_nopcid_nopti);
7927 pmap_activate_sw(struct thread *td)
7929 pmap_t oldpmap, pmap;
7932 oldpmap = PCPU_GET(curpmap);
7933 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7934 if (oldpmap == pmap)
7936 cpuid = PCPU_GET(cpuid);
7938 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7940 CPU_SET(cpuid, &pmap->pm_active);
7942 pmap_activate_sw_mode(td, pmap, cpuid);
7944 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7946 CPU_CLR(cpuid, &oldpmap->pm_active);
7951 pmap_activate(struct thread *td)
7955 pmap_activate_sw(td);
7960 pmap_activate_boot(pmap_t pmap)
7966 * kernel_pmap must be never deactivated, and we ensure that
7967 * by never activating it at all.
7969 MPASS(pmap != kernel_pmap);
7971 cpuid = PCPU_GET(cpuid);
7973 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7975 CPU_SET(cpuid, &pmap->pm_active);
7977 PCPU_SET(curpmap, pmap);
7979 kcr3 = pmap->pm_cr3;
7980 if (pmap_pcid_enabled)
7981 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
7985 PCPU_SET(kcr3, kcr3);
7986 PCPU_SET(ucr3, PMAP_NO_CR3);
7990 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7995 * Increase the starting virtual address of the given mapping if a
7996 * different alignment might result in more superpage mappings.
7999 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8000 vm_offset_t *addr, vm_size_t size)
8002 vm_offset_t superpage_offset;
8006 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8007 offset += ptoa(object->pg_color);
8008 superpage_offset = offset & PDRMASK;
8009 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8010 (*addr & PDRMASK) == superpage_offset)
8012 if ((*addr & PDRMASK) < superpage_offset)
8013 *addr = (*addr & ~PDRMASK) + superpage_offset;
8015 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8019 static unsigned long num_dirty_emulations;
8020 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8021 &num_dirty_emulations, 0, NULL);
8023 static unsigned long num_accessed_emulations;
8024 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8025 &num_accessed_emulations, 0, NULL);
8027 static unsigned long num_superpage_accessed_emulations;
8028 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8029 &num_superpage_accessed_emulations, 0, NULL);
8031 static unsigned long ad_emulation_superpage_promotions;
8032 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8033 &ad_emulation_superpage_promotions, 0, NULL);
8034 #endif /* INVARIANTS */
8037 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8040 struct rwlock *lock;
8041 #if VM_NRESERVLEVEL > 0
8045 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8047 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8048 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8050 if (!pmap_emulate_ad_bits(pmap))
8053 PG_A = pmap_accessed_bit(pmap);
8054 PG_M = pmap_modified_bit(pmap);
8055 PG_V = pmap_valid_bit(pmap);
8056 PG_RW = pmap_rw_bit(pmap);
8062 pde = pmap_pde(pmap, va);
8063 if (pde == NULL || (*pde & PG_V) == 0)
8066 if ((*pde & PG_PS) != 0) {
8067 if (ftype == VM_PROT_READ) {
8069 atomic_add_long(&num_superpage_accessed_emulations, 1);
8077 pte = pmap_pde_to_pte(pde, va);
8078 if ((*pte & PG_V) == 0)
8081 if (ftype == VM_PROT_WRITE) {
8082 if ((*pte & PG_RW) == 0)
8085 * Set the modified and accessed bits simultaneously.
8087 * Intel EPT PTEs that do software emulation of A/D bits map
8088 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8089 * An EPT misconfiguration is triggered if the PTE is writable
8090 * but not readable (WR=10). This is avoided by setting PG_A
8091 * and PG_M simultaneously.
8093 *pte |= PG_M | PG_A;
8098 #if VM_NRESERVLEVEL > 0
8099 /* try to promote the mapping */
8100 if (va < VM_MAXUSER_ADDRESS)
8101 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8105 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8107 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8108 pmap_ps_enabled(pmap) &&
8109 (m->flags & PG_FICTITIOUS) == 0 &&
8110 vm_reserv_level_iffullpop(m) == 0) {
8111 pmap_promote_pde(pmap, pde, va, &lock);
8113 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8119 if (ftype == VM_PROT_WRITE)
8120 atomic_add_long(&num_dirty_emulations, 1);
8122 atomic_add_long(&num_accessed_emulations, 1);
8124 rv = 0; /* success */
8133 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8138 pt_entry_t *pte, PG_V;
8142 PG_V = pmap_valid_bit(pmap);
8145 pml4 = pmap_pml4e(pmap, va);
8147 if ((*pml4 & PG_V) == 0)
8150 pdp = pmap_pml4e_to_pdpe(pml4, va);
8152 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8155 pde = pmap_pdpe_to_pde(pdp, va);
8157 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8160 pte = pmap_pde_to_pte(pde, va);
8169 * Get the kernel virtual address of a set of physical pages. If there are
8170 * physical addresses not covered by the DMAP perform a transient mapping
8171 * that will be removed when calling pmap_unmap_io_transient.
8173 * \param page The pages the caller wishes to obtain the virtual
8174 * address on the kernel memory map.
8175 * \param vaddr On return contains the kernel virtual memory address
8176 * of the pages passed in the page parameter.
8177 * \param count Number of pages passed in.
8178 * \param can_fault TRUE if the thread using the mapped pages can take
8179 * page faults, FALSE otherwise.
8181 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8182 * finished or FALSE otherwise.
8186 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8187 boolean_t can_fault)
8190 boolean_t needs_mapping;
8192 int cache_bits, error __unused, i;
8195 * Allocate any KVA space that we need, this is done in a separate
8196 * loop to prevent calling vmem_alloc while pinned.
8198 needs_mapping = FALSE;
8199 for (i = 0; i < count; i++) {
8200 paddr = VM_PAGE_TO_PHYS(page[i]);
8201 if (__predict_false(paddr >= dmaplimit)) {
8202 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8203 M_BESTFIT | M_WAITOK, &vaddr[i]);
8204 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8205 needs_mapping = TRUE;
8207 vaddr[i] = PHYS_TO_DMAP(paddr);
8211 /* Exit early if everything is covered by the DMAP */
8216 * NB: The sequence of updating a page table followed by accesses
8217 * to the corresponding pages used in the !DMAP case is subject to
8218 * the situation described in the "AMD64 Architecture Programmer's
8219 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8220 * Coherency Considerations". Therefore, issuing the INVLPG right
8221 * after modifying the PTE bits is crucial.
8225 for (i = 0; i < count; i++) {
8226 paddr = VM_PAGE_TO_PHYS(page[i]);
8227 if (paddr >= dmaplimit) {
8230 * Slow path, since we can get page faults
8231 * while mappings are active don't pin the
8232 * thread to the CPU and instead add a global
8233 * mapping visible to all CPUs.
8235 pmap_qenter(vaddr[i], &page[i], 1);
8237 pte = vtopte(vaddr[i]);
8238 cache_bits = pmap_cache_bits(kernel_pmap,
8239 page[i]->md.pat_mode, 0);
8240 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8247 return (needs_mapping);
8251 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8252 boolean_t can_fault)
8259 for (i = 0; i < count; i++) {
8260 paddr = VM_PAGE_TO_PHYS(page[i]);
8261 if (paddr >= dmaplimit) {
8263 pmap_qremove(vaddr[i], 1);
8264 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8270 pmap_quick_enter_page(vm_page_t m)
8274 paddr = VM_PAGE_TO_PHYS(m);
8275 if (paddr < dmaplimit)
8276 return (PHYS_TO_DMAP(paddr));
8277 mtx_lock_spin(&qframe_mtx);
8278 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8279 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8280 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8285 pmap_quick_remove_page(vm_offset_t addr)
8290 pte_store(vtopte(qframe), 0);
8292 mtx_unlock_spin(&qframe_mtx);
8296 * Pdp pages from the large map are managed differently from either
8297 * kernel or user page table pages. They are permanently allocated at
8298 * initialization time, and their wire count is permanently set to
8299 * zero. The pml4 entries pointing to those pages are copied into
8300 * each allocated pmap.
8302 * In contrast, pd and pt pages are managed like user page table
8303 * pages. They are dynamically allocated, and their wire count
8304 * represents the number of valid entries within the page.
8307 pmap_large_map_getptp_unlocked(void)
8311 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8313 if (m != NULL && (m->flags & PG_ZERO) == 0)
8319 pmap_large_map_getptp(void)
8323 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8324 m = pmap_large_map_getptp_unlocked();
8326 PMAP_UNLOCK(kernel_pmap);
8328 PMAP_LOCK(kernel_pmap);
8329 /* Callers retry. */
8334 static pdp_entry_t *
8335 pmap_large_map_pdpe(vm_offset_t va)
8337 vm_pindex_t pml4_idx;
8340 pml4_idx = pmap_pml4e_index(va);
8341 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8342 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8344 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8345 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8346 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8347 "LMSPML4I %#jx lm_ents %d",
8348 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8349 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8350 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8354 pmap_large_map_pde(vm_offset_t va)
8361 pdpe = pmap_large_map_pdpe(va);
8363 m = pmap_large_map_getptp();
8366 mphys = VM_PAGE_TO_PHYS(m);
8367 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8369 MPASS((*pdpe & X86_PG_PS) == 0);
8370 mphys = *pdpe & PG_FRAME;
8372 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
8376 pmap_large_map_pte(vm_offset_t va)
8383 pde = pmap_large_map_pde(va);
8385 m = pmap_large_map_getptp();
8388 mphys = VM_PAGE_TO_PHYS(m);
8389 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8390 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
8392 MPASS((*pde & X86_PG_PS) == 0);
8393 mphys = *pde & PG_FRAME;
8395 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
8399 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
8400 vmem_addr_t *vmem_res)
8404 * Large mappings are all but static. Consequently, there
8405 * is no point in waiting for an earlier allocation to be
8408 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
8409 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
8413 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
8419 vm_offset_t va, inc;
8420 vmem_addr_t vmem_res;
8424 if (len == 0 || spa + len < spa)
8427 /* See if DMAP can serve. */
8428 if (spa + len <= dmaplimit) {
8429 va = PHYS_TO_DMAP(spa);
8431 return (pmap_change_attr(va, len, mattr));
8435 * No, allocate KVA. Fit the address with best possible
8436 * alignment for superpages. Fall back to worse align if
8440 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
8441 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
8442 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
8444 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
8446 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
8449 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
8454 * Fill pagetable. PG_M is not pre-set, we scan modified bits
8455 * in the pagetable to minimize flushing. No need to
8456 * invalidate TLB, since we only update invalid entries.
8458 PMAP_LOCK(kernel_pmap);
8459 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
8461 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
8462 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
8463 pdpe = pmap_large_map_pdpe(va);
8465 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
8466 X86_PG_V | X86_PG_A | pg_nx |
8467 pmap_cache_bits(kernel_pmap, mattr, TRUE);
8469 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
8470 (va & PDRMASK) == 0) {
8471 pde = pmap_large_map_pde(va);
8473 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
8474 X86_PG_V | X86_PG_A | pg_nx |
8475 pmap_cache_bits(kernel_pmap, mattr, TRUE);
8476 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
8480 pte = pmap_large_map_pte(va);
8482 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
8483 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
8485 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
8490 PMAP_UNLOCK(kernel_pmap);
8493 *addr = (void *)vmem_res;
8498 pmap_large_unmap(void *svaa, vm_size_t len)
8500 vm_offset_t sva, va;
8502 pdp_entry_t *pdpe, pdp;
8503 pd_entry_t *pde, pd;
8506 struct spglist spgf;
8508 sva = (vm_offset_t)svaa;
8509 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
8510 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
8514 KASSERT(LARGEMAP_MIN_ADDRESS <= sva && sva + len <=
8515 LARGEMAP_MAX_ADDRESS + NBPML4 * (u_long)lm_ents,
8516 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
8517 PMAP_LOCK(kernel_pmap);
8518 for (va = sva; va < sva + len; va += inc) {
8519 pdpe = pmap_large_map_pdpe(va);
8521 KASSERT((pdp & X86_PG_V) != 0,
8522 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
8523 (u_long)pdpe, pdp));
8524 if ((pdp & X86_PG_PS) != 0) {
8525 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
8526 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
8527 (u_long)pdpe, pdp));
8528 KASSERT((va & PDPMASK) == 0,
8529 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
8530 (u_long)pdpe, pdp));
8531 KASSERT(va + NBPDP <= sva + len,
8532 ("unmap covers partial 1GB page, sva %#lx va %#lx "
8533 "pdpe %#lx pdp %#lx len %#lx", sva, va,
8534 (u_long)pdpe, pdp, len));
8539 pde = pmap_pdpe_to_pde(pdpe, va);
8541 KASSERT((pd & X86_PG_V) != 0,
8542 ("invalid pd va %#lx pde %#lx pd %#lx", va,
8544 if ((pd & X86_PG_PS) != 0) {
8545 KASSERT((va & PDRMASK) == 0,
8546 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
8548 KASSERT(va + NBPDR <= sva + len,
8549 ("unmap covers partial 2MB page, sva %#lx va %#lx "
8550 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
8554 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
8556 if (m->wire_count == 0) {
8558 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8562 pte = pmap_pde_to_pte(pde, va);
8563 KASSERT((*pte & X86_PG_V) != 0,
8564 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8565 (u_long)pte, *pte));
8568 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
8570 if (m->wire_count == 0) {
8572 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8573 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
8575 if (m->wire_count == 0) {
8577 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
8581 pmap_invalidate_range(kernel_pmap, sva, sva + len);
8582 PMAP_UNLOCK(kernel_pmap);
8583 vm_page_free_pages_toq(&spgf, false);
8584 vmem_free(large_vmem, sva, len);
8588 pmap_large_map_wb_fence_mfence(void)
8595 pmap_large_map_wb_fence_sfence(void)
8602 pmap_large_map_wb_fence_nop(void)
8606 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void), static)
8609 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8610 return (pmap_large_map_wb_fence_mfence);
8611 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
8612 CPUID_STDEXT_CLFLUSHOPT)) == 0)
8613 return (pmap_large_map_wb_fence_sfence);
8615 /* clflush is strongly enough ordered */
8616 return (pmap_large_map_wb_fence_nop);
8620 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
8623 for (; len > 0; len -= cpu_clflush_line_size,
8624 va += cpu_clflush_line_size)
8629 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
8632 for (; len > 0; len -= cpu_clflush_line_size,
8633 va += cpu_clflush_line_size)
8638 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
8641 for (; len > 0; len -= cpu_clflush_line_size,
8642 va += cpu_clflush_line_size)
8647 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
8651 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t),
8655 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
8656 return (pmap_large_map_flush_range_clwb);
8657 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
8658 return (pmap_large_map_flush_range_clflushopt);
8659 else if ((cpu_feature & CPUID_CLFSH) != 0)
8660 return (pmap_large_map_flush_range_clflush);
8662 return (pmap_large_map_flush_range_nop);
8666 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
8668 volatile u_long *pe;
8674 for (va = sva; va < eva; va += inc) {
8676 if ((amd_feature & AMDID_PAGE1GB) != 0) {
8677 pe = (volatile u_long *)pmap_large_map_pdpe(va);
8679 if ((p & X86_PG_PS) != 0)
8683 pe = (volatile u_long *)pmap_large_map_pde(va);
8685 if ((p & X86_PG_PS) != 0)
8689 pe = (volatile u_long *)pmap_large_map_pte(va);
8695 if ((p & X86_PG_AVAIL1) != 0) {
8697 * Spin-wait for the end of a parallel
8704 * If we saw other write-back
8705 * occuring, we cannot rely on PG_M to
8706 * indicate state of the cache. The
8707 * PG_M bit is cleared before the
8708 * flush to avoid ignoring new writes,
8709 * and writes which are relevant for
8710 * us might happen after.
8716 if ((p & X86_PG_M) != 0 || seen_other) {
8717 if (!atomic_fcmpset_long(pe, &p,
8718 (p & ~X86_PG_M) | X86_PG_AVAIL1))
8720 * If we saw PG_M without
8721 * PG_AVAIL1, and then on the
8722 * next attempt we do not
8723 * observe either PG_M or
8724 * PG_AVAIL1, the other
8725 * write-back started after us
8726 * and finished before us. We
8727 * can rely on it doing our
8731 pmap_large_map_flush_range(va, inc);
8732 atomic_clear_long(pe, X86_PG_AVAIL1);
8741 * Write-back cache lines for the given address range.
8743 * Must be called only on the range or sub-range returned from
8744 * pmap_large_map(). Must not be called on the coalesced ranges.
8746 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
8747 * instructions support.
8750 pmap_large_map_wb(void *svap, vm_size_t len)
8752 vm_offset_t eva, sva;
8754 sva = (vm_offset_t)svap;
8756 pmap_large_map_wb_fence();
8757 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
8758 pmap_large_map_flush_range(sva, len);
8760 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
8761 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
8762 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
8763 pmap_large_map_wb_large(sva, eva);
8765 pmap_large_map_wb_fence();
8769 pmap_pti_alloc_page(void)
8773 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8774 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
8775 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
8780 pmap_pti_free_page(vm_page_t m)
8783 KASSERT(m->wire_count > 0, ("page %p not wired", m));
8784 if (!vm_page_unwire_noq(m))
8786 vm_page_free_zero(m);
8800 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
8801 VM_OBJECT_WLOCK(pti_obj);
8802 pml4_pg = pmap_pti_alloc_page();
8803 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
8804 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
8805 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
8806 pdpe = pmap_pti_pdpe(va);
8807 pmap_pti_wire_pte(pdpe);
8809 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
8810 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
8811 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
8812 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
8813 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
8814 sizeof(struct gate_descriptor) * NIDT, false);
8815 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
8816 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
8818 /* Doublefault stack IST 1 */
8819 va = common_tss[i].tss_ist1;
8820 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8821 /* NMI stack IST 2 */
8822 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
8823 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8824 /* MC# stack IST 3 */
8825 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
8826 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8827 /* DB# stack IST 4 */
8828 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
8829 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8831 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
8832 (vm_offset_t)etext, true);
8833 pti_finalized = true;
8834 VM_OBJECT_WUNLOCK(pti_obj);
8836 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
8838 static pdp_entry_t *
8839 pmap_pti_pdpe(vm_offset_t va)
8841 pml4_entry_t *pml4e;
8844 vm_pindex_t pml4_idx;
8847 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8849 pml4_idx = pmap_pml4e_index(va);
8850 pml4e = &pti_pml4[pml4_idx];
8854 panic("pml4 alloc after finalization\n");
8855 m = pmap_pti_alloc_page();
8857 pmap_pti_free_page(m);
8858 mphys = *pml4e & ~PAGE_MASK;
8860 mphys = VM_PAGE_TO_PHYS(m);
8861 *pml4e = mphys | X86_PG_RW | X86_PG_V;
8864 mphys = *pml4e & ~PAGE_MASK;
8866 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
8871 pmap_pti_wire_pte(void *pte)
8875 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8876 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8881 pmap_pti_unwire_pde(void *pde, bool only_ref)
8885 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8886 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
8887 MPASS(m->wire_count > 0);
8888 MPASS(only_ref || m->wire_count > 1);
8889 pmap_pti_free_page(m);
8893 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
8898 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8899 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8900 MPASS(m->wire_count > 0);
8901 if (pmap_pti_free_page(m)) {
8902 pde = pmap_pti_pde(va);
8903 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
8905 pmap_pti_unwire_pde(pde, false);
8910 pmap_pti_pde(vm_offset_t va)
8918 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8920 pdpe = pmap_pti_pdpe(va);
8922 m = pmap_pti_alloc_page();
8924 pmap_pti_free_page(m);
8925 MPASS((*pdpe & X86_PG_PS) == 0);
8926 mphys = *pdpe & ~PAGE_MASK;
8928 mphys = VM_PAGE_TO_PHYS(m);
8929 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8932 MPASS((*pdpe & X86_PG_PS) == 0);
8933 mphys = *pdpe & ~PAGE_MASK;
8936 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8937 pd_idx = pmap_pde_index(va);
8943 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8950 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8952 pde = pmap_pti_pde(va);
8953 if (unwire_pde != NULL) {
8955 pmap_pti_wire_pte(pde);
8958 m = pmap_pti_alloc_page();
8960 pmap_pti_free_page(m);
8961 MPASS((*pde & X86_PG_PS) == 0);
8962 mphys = *pde & ~(PAGE_MASK | pg_nx);
8964 mphys = VM_PAGE_TO_PHYS(m);
8965 *pde = mphys | X86_PG_RW | X86_PG_V;
8966 if (unwire_pde != NULL)
8967 *unwire_pde = false;
8970 MPASS((*pde & X86_PG_PS) == 0);
8971 mphys = *pde & ~(PAGE_MASK | pg_nx);
8974 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8975 pte += pmap_pte_index(va);
8981 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8985 pt_entry_t *pte, ptev;
8988 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8990 sva = trunc_page(sva);
8991 MPASS(sva > VM_MAXUSER_ADDRESS);
8992 eva = round_page(eva);
8994 for (; sva < eva; sva += PAGE_SIZE) {
8995 pte = pmap_pti_pte(sva, &unwire_pde);
8996 pa = pmap_kextract(sva);
8997 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8998 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8999 VM_MEMATTR_DEFAULT, FALSE);
9001 pte_store(pte, ptev);
9002 pmap_pti_wire_pte(pte);
9004 KASSERT(!pti_finalized,
9005 ("pti overlap after fin %#lx %#lx %#lx",
9007 KASSERT(*pte == ptev,
9008 ("pti non-identical pte after fin %#lx %#lx %#lx",
9012 pde = pmap_pti_pde(sva);
9013 pmap_pti_unwire_pde(pde, true);
9019 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9024 VM_OBJECT_WLOCK(pti_obj);
9025 pmap_pti_add_kva_locked(sva, eva, exec);
9026 VM_OBJECT_WUNLOCK(pti_obj);
9030 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9037 sva = rounddown2(sva, PAGE_SIZE);
9038 MPASS(sva > VM_MAXUSER_ADDRESS);
9039 eva = roundup2(eva, PAGE_SIZE);
9041 VM_OBJECT_WLOCK(pti_obj);
9042 for (va = sva; va < eva; va += PAGE_SIZE) {
9043 pte = pmap_pti_pte(va, NULL);
9044 KASSERT((*pte & X86_PG_V) != 0,
9045 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9046 (u_long)pte, *pte));
9048 pmap_pti_unwire_pte(pte, va);
9050 pmap_invalidate_range(kernel_pmap, sva, eva);
9051 VM_OBJECT_WUNLOCK(pti_obj);
9055 pkru_dup_range(void *ctx __unused, void *data)
9057 struct pmap_pkru_range *node, *new_node;
9059 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9060 if (new_node == NULL)
9063 memcpy(new_node, node, sizeof(*node));
9068 pkru_free_range(void *ctx __unused, void *node)
9071 uma_zfree(pmap_pkru_ranges_zone, node);
9075 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9078 struct pmap_pkru_range *ppr;
9081 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9082 MPASS(pmap->pm_type == PT_X86);
9083 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9084 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9085 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9087 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9090 ppr->pkru_keyidx = keyidx;
9091 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9092 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9094 uma_zfree(pmap_pkru_ranges_zone, ppr);
9099 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9102 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9103 MPASS(pmap->pm_type == PT_X86);
9104 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9105 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9109 pmap_pkru_deassign_all(pmap_t pmap)
9112 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9113 if (pmap->pm_type == PT_X86 &&
9114 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9115 rangeset_remove_all(&pmap->pm_pkru);
9119 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9121 struct pmap_pkru_range *ppr, *prev_ppr;
9124 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9125 if (pmap->pm_type != PT_X86 ||
9126 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9127 sva >= VM_MAXUSER_ADDRESS)
9129 MPASS(eva <= VM_MAXUSER_ADDRESS);
9130 for (va = sva, prev_ppr = NULL; va < eva;) {
9131 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9132 if ((ppr == NULL) ^ (prev_ppr == NULL))
9138 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9140 va = ppr->pkru_rs_el.re_end;
9146 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9148 struct pmap_pkru_range *ppr;
9150 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9151 if (pmap->pm_type != PT_X86 ||
9152 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9153 va >= VM_MAXUSER_ADDRESS)
9155 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9157 return (X86_PG_PKU(ppr->pkru_keyidx));
9162 pred_pkru_on_remove(void *ctx __unused, void *r)
9164 struct pmap_pkru_range *ppr;
9167 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9171 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9174 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9175 if (pmap->pm_type == PT_X86 &&
9176 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9177 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9178 pred_pkru_on_remove);
9183 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9186 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9187 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9188 MPASS(dst_pmap->pm_type == PT_X86);
9189 MPASS(src_pmap->pm_type == PT_X86);
9190 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9191 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9193 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9197 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9200 pml4_entry_t *pml4e;
9202 pd_entry_t newpde, ptpaddr, *pde;
9203 pt_entry_t newpte, *ptep, pte;
9204 vm_offset_t va, va_next;
9207 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9208 MPASS(pmap->pm_type == PT_X86);
9209 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9211 for (changed = false, va = sva; va < eva; va = va_next) {
9212 pml4e = pmap_pml4e(pmap, va);
9213 if ((*pml4e & X86_PG_V) == 0) {
9214 va_next = (va + NBPML4) & ~PML4MASK;
9220 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9221 if ((*pdpe & X86_PG_V) == 0) {
9222 va_next = (va + NBPDP) & ~PDPMASK;
9228 va_next = (va + NBPDR) & ~PDRMASK;
9232 pde = pmap_pdpe_to_pde(pdpe, va);
9237 MPASS((ptpaddr & X86_PG_V) != 0);
9238 if ((ptpaddr & PG_PS) != 0) {
9239 if (va + NBPDR == va_next && eva >= va_next) {
9240 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9242 if (newpde != ptpaddr) {
9247 } else if (!pmap_demote_pde(pmap, pde, va)) {
9255 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9256 ptep++, va += PAGE_SIZE) {
9258 if ((pte & X86_PG_V) == 0)
9260 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9261 if (newpte != pte) {
9268 pmap_invalidate_range(pmap, sva, eva);
9272 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9273 u_int keyidx, int flags)
9276 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9277 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9279 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9281 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9287 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9292 sva = trunc_page(sva);
9293 eva = round_page(eva);
9294 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9299 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9301 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9303 if (error != ENOMEM)
9311 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9315 sva = trunc_page(sva);
9316 eva = round_page(eva);
9317 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9322 error = pmap_pkru_deassign(pmap, sva, eva);
9324 pmap_pkru_update_range(pmap, sva, eva, 0);
9326 if (error != ENOMEM)
9333 #include "opt_ddb.h"
9335 #include <sys/kdb.h>
9336 #include <ddb/ddb.h>
9338 DB_SHOW_COMMAND(pte, pmap_print_pte)
9344 pt_entry_t *pte, PG_V;
9348 db_printf("show pte addr\n");
9351 va = (vm_offset_t)addr;
9353 if (kdb_thread != NULL)
9354 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
9356 pmap = PCPU_GET(curpmap);
9358 PG_V = pmap_valid_bit(pmap);
9359 pml4 = pmap_pml4e(pmap, va);
9360 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
9361 if ((*pml4 & PG_V) == 0) {
9365 pdp = pmap_pml4e_to_pdpe(pml4, va);
9366 db_printf(" pdpe %#016lx", *pdp);
9367 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
9371 pde = pmap_pdpe_to_pde(pdp, va);
9372 db_printf(" pde %#016lx", *pde);
9373 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
9377 pte = pmap_pde_to_pte(pde, va);
9378 db_printf(" pte %#016lx\n", *pte);
9381 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
9386 a = (vm_paddr_t)addr;
9387 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
9389 db_printf("show phys2dmap addr\n");