2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
128 #include <sys/turnstile.h>
129 #include <sys/vmem.h>
130 #include <sys/vmmeter.h>
131 #include <sys/sched.h>
132 #include <sys/sysctl.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
148 #include <vm/vm_phys.h>
149 #include <vm/vm_radix.h>
150 #include <vm/vm_reserv.h>
153 #include <machine/intr_machdep.h>
154 #include <x86/apicvar.h>
155 #include <x86/ifunc.h>
156 #include <machine/cpu.h>
157 #include <machine/cputypes.h>
158 #include <machine/md_var.h>
159 #include <machine/pcb.h>
160 #include <machine/specialreg.h>
162 #include <machine/smp.h>
164 #include <machine/sysarch.h>
165 #include <machine/tss.h>
167 static __inline boolean_t
168 pmap_type_guest(pmap_t pmap)
171 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
174 static __inline boolean_t
175 pmap_emulate_ad_bits(pmap_t pmap)
178 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
181 static __inline pt_entry_t
182 pmap_valid_bit(pmap_t pmap)
186 switch (pmap->pm_type) {
192 if (pmap_emulate_ad_bits(pmap))
193 mask = EPT_PG_EMUL_V;
198 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
204 static __inline pt_entry_t
205 pmap_rw_bit(pmap_t pmap)
209 switch (pmap->pm_type) {
215 if (pmap_emulate_ad_bits(pmap))
216 mask = EPT_PG_EMUL_RW;
221 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
227 static pt_entry_t pg_g;
229 static __inline pt_entry_t
230 pmap_global_bit(pmap_t pmap)
234 switch (pmap->pm_type) {
243 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
249 static __inline pt_entry_t
250 pmap_accessed_bit(pmap_t pmap)
254 switch (pmap->pm_type) {
260 if (pmap_emulate_ad_bits(pmap))
266 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
272 static __inline pt_entry_t
273 pmap_modified_bit(pmap_t pmap)
277 switch (pmap->pm_type) {
283 if (pmap_emulate_ad_bits(pmap))
289 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
295 static __inline pt_entry_t
296 pmap_pku_mask_bit(pmap_t pmap)
299 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
302 #if !defined(DIAGNOSTIC)
303 #ifdef __GNUC_GNU_INLINE__
304 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
306 #define PMAP_INLINE extern inline
313 #define PV_STAT(x) do { x ; } while (0)
315 #define PV_STAT(x) do { } while (0)
318 #define pa_index(pa) ((pa) >> PDRSHIFT)
319 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
321 #define NPV_LIST_LOCKS MAXCPU
323 #define PHYS_TO_PV_LIST_LOCK(pa) \
324 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
326 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
327 struct rwlock **_lockp = (lockp); \
328 struct rwlock *_new_lock; \
330 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
331 if (_new_lock != *_lockp) { \
332 if (*_lockp != NULL) \
333 rw_wunlock(*_lockp); \
334 *_lockp = _new_lock; \
339 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
340 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
342 #define RELEASE_PV_LIST_LOCK(lockp) do { \
343 struct rwlock **_lockp = (lockp); \
345 if (*_lockp != NULL) { \
346 rw_wunlock(*_lockp); \
351 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
352 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
354 struct pmap kernel_pmap_store;
356 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
357 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
360 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
361 "Number of kernel page table pages allocated on bootup");
364 vm_paddr_t dmaplimit;
365 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
368 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
370 static int pg_ps_enabled = 1;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
372 &pg_ps_enabled, 0, "Are large page mappings enabled?");
374 #define PAT_INDEX_SIZE 8
375 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
377 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
378 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
379 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
380 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
382 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
383 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
384 static int ndmpdpphys; /* number of DMPDPphys pages */
386 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
389 * pmap_mapdev support pre initialization (i.e. console)
391 #define PMAP_PREINIT_MAPPING_COUNT 8
392 static struct pmap_preinit_mapping {
397 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
398 static int pmap_initialized;
401 * Data for the pv entry allocation mechanism.
402 * Updates to pv_invl_gen are protected by the pv_list_locks[]
403 * elements, but reads are not.
405 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
406 static struct mtx __exclusive_cache_line pv_chunks_mutex;
407 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
408 static u_long pv_invl_gen[NPV_LIST_LOCKS];
409 static struct md_page *pv_table;
410 static struct md_page pv_dummy;
413 * All those kernel PT submaps that BSD is so fond of
415 pt_entry_t *CMAP1 = NULL;
417 static vm_offset_t qframe = 0;
418 static struct mtx qframe_mtx;
420 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
422 static vmem_t *large_vmem;
423 static u_int lm_ents;
424 #define PMAP_LARGEMAP_MAX_ADDRESS() \
425 (LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
427 int pmap_pcid_enabled = 1;
428 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
429 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
430 int invpcid_works = 0;
431 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
432 "Is the invpcid instruction available ?");
434 int __read_frequently pti = 0;
435 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
437 "Page Table Isolation enabled");
438 static vm_object_t pti_obj;
439 static pml4_entry_t *pti_pml4;
440 static vm_pindex_t pti_pg_idx;
441 static bool pti_finalized;
443 struct pmap_pkru_range {
444 struct rs_el pkru_rs_el;
449 static uma_zone_t pmap_pkru_ranges_zone;
450 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
451 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
452 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
453 static void *pkru_dup_range(void *ctx, void *data);
454 static void pkru_free_range(void *ctx, void *node);
455 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
456 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
457 static void pmap_pkru_deassign_all(pmap_t pmap);
460 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
467 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
469 return (sysctl_handle_64(oidp, &res, 0, req));
471 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
472 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
473 "Count of saved TLB context on switch");
475 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
476 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
477 static struct mtx invl_gen_mtx;
478 /* Fake lock object to satisfy turnstiles interface. */
479 static struct lock_object invl_gen_ts = {
482 static struct pmap_invl_gen pmap_invl_gen_head = {
486 static u_long pmap_invl_gen = 1;
487 static int pmap_invl_waiters;
488 static struct callout pmap_invl_callout;
489 static bool pmap_invl_callout_inited;
491 #define PMAP_ASSERT_NOT_IN_DI() \
492 KASSERT(pmap_not_in_di(), ("DI already started"))
499 if ((cpu_feature2 & CPUID2_CX16) == 0)
502 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
507 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
511 locked = pmap_di_locked();
512 return (sysctl_handle_int(oidp, &locked, 0, req));
514 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
515 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
516 "Locked delayed invalidation");
518 static bool pmap_not_in_di_l(void);
519 static bool pmap_not_in_di_u(void);
520 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
523 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
527 pmap_not_in_di_l(void)
529 struct pmap_invl_gen *invl_gen;
531 invl_gen = &curthread->td_md.md_invl_gen;
532 return (invl_gen->gen == 0);
536 pmap_thread_init_invl_gen_l(struct thread *td)
538 struct pmap_invl_gen *invl_gen;
540 invl_gen = &td->td_md.md_invl_gen;
545 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
547 struct turnstile *ts;
549 ts = turnstile_trywait(&invl_gen_ts);
550 if (*m_gen > atomic_load_long(invl_gen))
551 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
553 turnstile_cancel(ts);
557 pmap_delayed_invl_finish_unblock(u_long new_gen)
559 struct turnstile *ts;
561 turnstile_chain_lock(&invl_gen_ts);
562 ts = turnstile_lookup(&invl_gen_ts);
564 pmap_invl_gen = new_gen;
566 turnstile_broadcast(ts, TS_SHARED_QUEUE);
567 turnstile_unpend(ts);
569 turnstile_chain_unlock(&invl_gen_ts);
573 * Start a new Delayed Invalidation (DI) block of code, executed by
574 * the current thread. Within a DI block, the current thread may
575 * destroy both the page table and PV list entries for a mapping and
576 * then release the corresponding PV list lock before ensuring that
577 * the mapping is flushed from the TLBs of any processors with the
581 pmap_delayed_invl_start_l(void)
583 struct pmap_invl_gen *invl_gen;
586 invl_gen = &curthread->td_md.md_invl_gen;
587 PMAP_ASSERT_NOT_IN_DI();
588 mtx_lock(&invl_gen_mtx);
589 if (LIST_EMPTY(&pmap_invl_gen_tracker))
590 currgen = pmap_invl_gen;
592 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
593 invl_gen->gen = currgen + 1;
594 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
595 mtx_unlock(&invl_gen_mtx);
599 * Finish the DI block, previously started by the current thread. All
600 * required TLB flushes for the pages marked by
601 * pmap_delayed_invl_page() must be finished before this function is
604 * This function works by bumping the global DI generation number to
605 * the generation number of the current thread's DI, unless there is a
606 * pending DI that started earlier. In the latter case, bumping the
607 * global DI generation number would incorrectly signal that the
608 * earlier DI had finished. Instead, this function bumps the earlier
609 * DI's generation number to match the generation number of the
610 * current thread's DI.
613 pmap_delayed_invl_finish_l(void)
615 struct pmap_invl_gen *invl_gen, *next;
617 invl_gen = &curthread->td_md.md_invl_gen;
618 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
619 mtx_lock(&invl_gen_mtx);
620 next = LIST_NEXT(invl_gen, link);
622 pmap_delayed_invl_finish_unblock(invl_gen->gen);
624 next->gen = invl_gen->gen;
625 LIST_REMOVE(invl_gen, link);
626 mtx_unlock(&invl_gen_mtx);
631 pmap_not_in_di_u(void)
633 struct pmap_invl_gen *invl_gen;
635 invl_gen = &curthread->td_md.md_invl_gen;
636 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
640 pmap_thread_init_invl_gen_u(struct thread *td)
642 struct pmap_invl_gen *invl_gen;
644 invl_gen = &td->td_md.md_invl_gen;
646 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
650 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
652 uint64_t new_high, new_low, old_high, old_low;
655 old_low = new_low = 0;
656 old_high = new_high = (uintptr_t)0;
658 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
659 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
660 : "b"(new_low), "c" (new_high)
663 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
666 out->next = (void *)old_high;
669 out->next = (void *)new_high;
675 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
676 struct pmap_invl_gen *new_val)
678 uint64_t new_high, new_low, old_high, old_low;
681 new_low = new_val->gen;
682 new_high = (uintptr_t)new_val->next;
683 old_low = old_val->gen;
684 old_high = (uintptr_t)old_val->next;
686 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
687 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
688 : "b"(new_low), "c" (new_high)
694 static long invl_start_restart;
695 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
696 &invl_start_restart, 0,
698 static long invl_finish_restart;
699 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
700 &invl_finish_restart, 0,
702 static int invl_max_qlen;
703 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
708 static struct lock_delay_config __read_frequently di_delay;
709 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
712 pmap_delayed_invl_start_u(void)
714 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
716 struct lock_delay_arg lda;
724 invl_gen = &td->td_md.md_invl_gen;
725 PMAP_ASSERT_NOT_IN_DI();
726 lock_delay_arg_init(&lda, &di_delay);
727 invl_gen->saved_pri = 0;
728 pri = td->td_base_pri;
731 pri = td->td_base_pri;
733 invl_gen->saved_pri = pri;
740 for (p = &pmap_invl_gen_head;; p = prev.next) {
742 prevl = atomic_load_ptr(&p->next);
743 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
744 PV_STAT(atomic_add_long(&invl_start_restart, 1));
750 prev.next = (void *)prevl;
753 if ((ii = invl_max_qlen) < i)
754 atomic_cmpset_int(&invl_max_qlen, ii, i);
757 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
758 PV_STAT(atomic_add_long(&invl_start_restart, 1));
763 new_prev.gen = prev.gen;
764 new_prev.next = invl_gen;
765 invl_gen->gen = prev.gen + 1;
767 /* Formal fence between store to invl->gen and updating *p. */
768 atomic_thread_fence_rel();
771 * After inserting an invl_gen element with invalid bit set,
772 * this thread blocks any other thread trying to enter the
773 * delayed invalidation block. Do not allow to remove us from
774 * the CPU, because it causes starvation for other threads.
779 * ABA for *p is not possible there, since p->gen can only
780 * increase. So if the *p thread finished its di, then
781 * started a new one and got inserted into the list at the
782 * same place, its gen will appear greater than the previously
785 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
787 PV_STAT(atomic_add_long(&invl_start_restart, 1));
793 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
794 * invl_gen->next, allowing other threads to iterate past us.
795 * pmap_di_store_invl() provides fence between the generation
796 * write and the update of next.
798 invl_gen->next = NULL;
803 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
804 struct pmap_invl_gen *p)
806 struct pmap_invl_gen prev, new_prev;
810 * Load invl_gen->gen after setting invl_gen->next
811 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
812 * generations to propagate to our invl_gen->gen. Lock prefix
813 * in atomic_set_ptr() worked as seq_cst fence.
815 mygen = atomic_load_long(&invl_gen->gen);
817 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
820 KASSERT(prev.gen < mygen,
821 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
822 new_prev.gen = mygen;
823 new_prev.next = (void *)((uintptr_t)invl_gen->next &
824 ~PMAP_INVL_GEN_NEXT_INVALID);
826 /* Formal fence between load of prev and storing update to it. */
827 atomic_thread_fence_rel();
829 return (pmap_di_store_invl(p, &prev, &new_prev));
833 pmap_delayed_invl_finish_u(void)
835 struct pmap_invl_gen *invl_gen, *p;
837 struct lock_delay_arg lda;
841 invl_gen = &td->td_md.md_invl_gen;
842 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
843 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
844 ("missed invl_start: INVALID"));
845 lock_delay_arg_init(&lda, &di_delay);
848 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
849 prevl = atomic_load_ptr(&p->next);
850 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
851 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
855 if ((void *)prevl == invl_gen)
860 * It is legitimate to not find ourself on the list if a
861 * thread before us finished its DI and started it again.
863 if (__predict_false(p == NULL)) {
864 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
870 atomic_set_ptr((uintptr_t *)&invl_gen->next,
871 PMAP_INVL_GEN_NEXT_INVALID);
872 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
873 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
874 PMAP_INVL_GEN_NEXT_INVALID);
876 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
881 if (atomic_load_int(&pmap_invl_waiters) > 0)
882 pmap_delayed_invl_finish_unblock(0);
883 if (invl_gen->saved_pri != 0) {
885 sched_prio(td, invl_gen->saved_pri);
891 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
893 struct pmap_invl_gen *p, *pn;
898 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
900 nextl = atomic_load_ptr(&p->next);
901 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
902 td = first ? NULL : __containerof(p, struct thread,
904 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
905 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
906 td != NULL ? td->td_tid : -1);
912 static long invl_wait;
913 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
914 "Number of times DI invalidation blocked pmap_remove_all/write");
915 static long invl_wait_slow;
916 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
917 "Number of slow invalidation waits for lockless DI");
921 pmap_delayed_invl_genp(vm_page_t m)
924 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
928 pmap_delayed_invl_callout_func(void *arg __unused)
931 if (atomic_load_int(&pmap_invl_waiters) == 0)
933 pmap_delayed_invl_finish_unblock(0);
937 pmap_delayed_invl_callout_init(void *arg __unused)
940 if (pmap_di_locked())
942 callout_init(&pmap_invl_callout, 1);
943 pmap_invl_callout_inited = true;
945 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
946 pmap_delayed_invl_callout_init, NULL);
949 * Ensure that all currently executing DI blocks, that need to flush
950 * TLB for the given page m, actually flushed the TLB at the time the
951 * function returned. If the page m has an empty PV list and we call
952 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
953 * valid mapping for the page m in either its page table or TLB.
955 * This function works by blocking until the global DI generation
956 * number catches up with the generation number associated with the
957 * given page m and its PV list. Since this function's callers
958 * typically own an object lock and sometimes own a page lock, it
959 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
963 pmap_delayed_invl_wait_l(vm_page_t m)
967 bool accounted = false;
970 m_gen = pmap_delayed_invl_genp(m);
971 while (*m_gen > pmap_invl_gen) {
974 atomic_add_long(&invl_wait, 1);
978 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
983 pmap_delayed_invl_wait_u(vm_page_t m)
986 struct lock_delay_arg lda;
990 m_gen = pmap_delayed_invl_genp(m);
991 lock_delay_arg_init(&lda, &di_delay);
992 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
993 if (fast || !pmap_invl_callout_inited) {
994 PV_STAT(atomic_add_long(&invl_wait, 1));
999 * The page's invalidation generation number
1000 * is still below the current thread's number.
1001 * Prepare to block so that we do not waste
1002 * CPU cycles or worse, suffer livelock.
1004 * Since it is impossible to block without
1005 * racing with pmap_delayed_invl_finish_u(),
1006 * prepare for the race by incrementing
1007 * pmap_invl_waiters and arming a 1-tick
1008 * callout which will unblock us if we lose
1011 atomic_add_int(&pmap_invl_waiters, 1);
1014 * Re-check the current thread's invalidation
1015 * generation after incrementing
1016 * pmap_invl_waiters, so that there is no race
1017 * with pmap_delayed_invl_finish_u() setting
1018 * the page generation and checking
1019 * pmap_invl_waiters. The only race allowed
1020 * is for a missed unblock, which is handled
1024 atomic_load_long(&pmap_invl_gen_head.gen)) {
1025 callout_reset(&pmap_invl_callout, 1,
1026 pmap_delayed_invl_callout_func, NULL);
1027 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1028 pmap_delayed_invl_wait_block(m_gen,
1029 &pmap_invl_gen_head.gen);
1031 atomic_add_int(&pmap_invl_waiters, -1);
1036 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1039 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1040 pmap_thread_init_invl_gen_u);
1043 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1046 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1047 pmap_delayed_invl_start_u);
1050 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1053 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1054 pmap_delayed_invl_finish_u);
1057 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1060 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1061 pmap_delayed_invl_wait_u);
1065 * Mark the page m's PV list as participating in the current thread's
1066 * DI block. Any threads concurrently using m's PV list to remove or
1067 * restrict all mappings to m will wait for the current thread's DI
1068 * block to complete before proceeding.
1070 * The function works by setting the DI generation number for m's PV
1071 * list to at least the DI generation number of the current thread.
1072 * This forces a caller of pmap_delayed_invl_wait() to block until
1073 * current thread calls pmap_delayed_invl_finish().
1076 pmap_delayed_invl_page(vm_page_t m)
1080 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1081 gen = curthread->td_md.md_invl_gen.gen;
1084 m_gen = pmap_delayed_invl_genp(m);
1092 static caddr_t crashdumpmap;
1095 * Internal flags for pmap_enter()'s helper functions.
1097 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1098 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1100 static void free_pv_chunk(struct pv_chunk *pc);
1101 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1102 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1103 static int popcnt_pc_map_pq(uint64_t *map);
1104 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1105 static void reserve_pv_entries(pmap_t pmap, int needed,
1106 struct rwlock **lockp);
1107 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1108 struct rwlock **lockp);
1109 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1110 u_int flags, struct rwlock **lockp);
1111 #if VM_NRESERVLEVEL > 0
1112 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1113 struct rwlock **lockp);
1115 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1116 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1119 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
1121 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1122 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1123 vm_offset_t va, struct rwlock **lockp);
1124 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1126 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1127 vm_prot_t prot, struct rwlock **lockp);
1128 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1129 u_int flags, vm_page_t m, struct rwlock **lockp);
1130 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1131 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1132 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1133 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1134 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1136 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1138 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1140 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1141 static vm_page_t pmap_large_map_getptp_unlocked(void);
1142 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1143 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
1144 #if VM_NRESERVLEVEL > 0
1145 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1146 struct rwlock **lockp);
1148 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1150 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
1151 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1153 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1154 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1155 static void pmap_pti_wire_pte(void *pte);
1156 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1157 struct spglist *free, struct rwlock **lockp);
1158 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1159 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1160 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1161 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1162 struct spglist *free);
1163 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1164 pd_entry_t *pde, struct spglist *free,
1165 struct rwlock **lockp);
1166 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1167 vm_page_t m, struct rwlock **lockp);
1168 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1170 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1172 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1173 struct rwlock **lockp);
1174 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1175 struct rwlock **lockp);
1176 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1177 struct rwlock **lockp);
1179 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1180 struct spglist *free);
1181 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1183 /********************/
1184 /* Inline functions */
1185 /********************/
1187 /* Return a non-clipped PD index for a given VA */
1188 static __inline vm_pindex_t
1189 pmap_pde_pindex(vm_offset_t va)
1191 return (va >> PDRSHIFT);
1195 /* Return a pointer to the PML4 slot that corresponds to a VA */
1196 static __inline pml4_entry_t *
1197 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1200 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1203 /* Return a pointer to the PDP slot that corresponds to a VA */
1204 static __inline pdp_entry_t *
1205 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1209 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1210 return (&pdpe[pmap_pdpe_index(va)]);
1213 /* Return a pointer to the PDP slot that corresponds to a VA */
1214 static __inline pdp_entry_t *
1215 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1217 pml4_entry_t *pml4e;
1220 PG_V = pmap_valid_bit(pmap);
1221 pml4e = pmap_pml4e(pmap, va);
1222 if ((*pml4e & PG_V) == 0)
1224 return (pmap_pml4e_to_pdpe(pml4e, va));
1227 /* Return a pointer to the PD slot that corresponds to a VA */
1228 static __inline pd_entry_t *
1229 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1233 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1234 return (&pde[pmap_pde_index(va)]);
1237 /* Return a pointer to the PD slot that corresponds to a VA */
1238 static __inline pd_entry_t *
1239 pmap_pde(pmap_t pmap, vm_offset_t va)
1244 PG_V = pmap_valid_bit(pmap);
1245 pdpe = pmap_pdpe(pmap, va);
1246 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1248 return (pmap_pdpe_to_pde(pdpe, va));
1251 /* Return a pointer to the PT slot that corresponds to a VA */
1252 static __inline pt_entry_t *
1253 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1257 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1258 return (&pte[pmap_pte_index(va)]);
1261 /* Return a pointer to the PT slot that corresponds to a VA */
1262 static __inline pt_entry_t *
1263 pmap_pte(pmap_t pmap, vm_offset_t va)
1268 PG_V = pmap_valid_bit(pmap);
1269 pde = pmap_pde(pmap, va);
1270 if (pde == NULL || (*pde & PG_V) == 0)
1272 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1273 return ((pt_entry_t *)pde);
1274 return (pmap_pde_to_pte(pde, va));
1277 static __inline void
1278 pmap_resident_count_inc(pmap_t pmap, int count)
1281 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1282 pmap->pm_stats.resident_count += count;
1285 static __inline void
1286 pmap_resident_count_dec(pmap_t pmap, int count)
1289 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1290 KASSERT(pmap->pm_stats.resident_count >= count,
1291 ("pmap %p resident count underflow %ld %d", pmap,
1292 pmap->pm_stats.resident_count, count));
1293 pmap->pm_stats.resident_count -= count;
1296 PMAP_INLINE pt_entry_t *
1297 vtopte(vm_offset_t va)
1299 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1301 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1303 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1306 static __inline pd_entry_t *
1307 vtopde(vm_offset_t va)
1309 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1311 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1313 return (PDmap + ((va >> PDRSHIFT) & mask));
1317 allocpages(vm_paddr_t *firstaddr, int n)
1322 bzero((void *)ret, n * PAGE_SIZE);
1323 *firstaddr += n * PAGE_SIZE;
1327 CTASSERT(powerof2(NDMPML4E));
1329 /* number of kernel PDP slots */
1330 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1333 nkpt_init(vm_paddr_t addr)
1340 pt_pages = howmany(addr, 1 << PDRSHIFT);
1341 pt_pages += NKPDPE(pt_pages);
1344 * Add some slop beyond the bare minimum required for bootstrapping
1347 * This is quite important when allocating KVA for kernel modules.
1348 * The modules are required to be linked in the negative 2GB of
1349 * the address space. If we run out of KVA in this region then
1350 * pmap_growkernel() will need to allocate page table pages to map
1351 * the entire 512GB of KVA space which is an unnecessary tax on
1354 * Secondly, device memory mapped as part of setting up the low-
1355 * level console(s) is taken from KVA, starting at virtual_avail.
1356 * This is because cninit() is called after pmap_bootstrap() but
1357 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1360 pt_pages += 32; /* 64MB additional slop. */
1366 * Returns the proper write/execute permission for a physical page that is
1367 * part of the initial boot allocations.
1369 * If the page has kernel text, it is marked as read-only. If the page has
1370 * kernel read-only data, it is marked as read-only/not-executable. If the
1371 * page has only read-write data, it is marked as read-write/not-executable.
1372 * If the page is below/above the kernel range, it is marked as read-write.
1374 * This function operates on 2M pages, since we map the kernel space that
1377 * Note that this doesn't currently provide any protection for modules.
1379 static inline pt_entry_t
1380 bootaddr_rwx(vm_paddr_t pa)
1384 * Everything in the same 2M page as the start of the kernel
1385 * should be static. On the other hand, things in the same 2M
1386 * page as the end of the kernel could be read-write/executable,
1387 * as the kernel image is not guaranteed to end on a 2M boundary.
1389 if (pa < trunc_2mpage(btext - KERNBASE) ||
1390 pa >= trunc_2mpage(_end - KERNBASE))
1393 * The linker should ensure that the read-only and read-write
1394 * portions don't share the same 2M page, so this shouldn't
1395 * impact read-only data. However, in any case, any page with
1396 * read-write data needs to be read-write.
1398 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1399 return (X86_PG_RW | pg_nx);
1401 * Mark any 2M page containing kernel text as read-only. Mark
1402 * other pages with read-only data as read-only and not executable.
1403 * (It is likely a small portion of the read-only data section will
1404 * be marked as read-only, but executable. This should be acceptable
1405 * since the read-only protection will keep the data from changing.)
1406 * Note that fixups to the .text section will still work until we
1409 if (pa < round_2mpage(etext - KERNBASE))
1415 create_pagetables(vm_paddr_t *firstaddr)
1417 int i, j, ndm1g, nkpdpe, nkdmpde;
1421 uint64_t DMPDkernphys;
1423 /* Allocate page table pages for the direct map */
1424 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1425 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1427 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1428 if (ndmpdpphys > NDMPML4E) {
1430 * Each NDMPML4E allows 512 GB, so limit to that,
1431 * and then readjust ndmpdp and ndmpdpphys.
1433 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1434 Maxmem = atop(NDMPML4E * NBPML4);
1435 ndmpdpphys = NDMPML4E;
1436 ndmpdp = NDMPML4E * NPDEPG;
1438 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1440 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1442 * Calculate the number of 1G pages that will fully fit in
1445 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1448 * Allocate 2M pages for the kernel. These will be used in
1449 * place of the first one or more 1G pages from ndm1g.
1451 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1452 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1455 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1456 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1458 /* Allocate pages */
1459 KPML4phys = allocpages(firstaddr, 1);
1460 KPDPphys = allocpages(firstaddr, NKPML4E);
1463 * Allocate the initial number of kernel page table pages required to
1464 * bootstrap. We defer this until after all memory-size dependent
1465 * allocations are done (e.g. direct map), so that we don't have to
1466 * build in too much slop in our estimate.
1468 * Note that when NKPML4E > 1, we have an empty page underneath
1469 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1470 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1472 nkpt_init(*firstaddr);
1473 nkpdpe = NKPDPE(nkpt);
1475 KPTphys = allocpages(firstaddr, nkpt);
1476 KPDphys = allocpages(firstaddr, nkpdpe);
1479 * Connect the zero-filled PT pages to their PD entries. This
1480 * implicitly maps the PT pages at their correct locations within
1483 pd_p = (pd_entry_t *)KPDphys;
1484 for (i = 0; i < nkpt; i++)
1485 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1488 * Map from physical address zero to the end of loader preallocated
1489 * memory using 2MB pages. This replaces some of the PD entries
1492 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1493 /* Preset PG_M and PG_A because demotion expects it. */
1494 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1495 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1498 * Because we map the physical blocks in 2M pages, adjust firstaddr
1499 * to record the physical blocks we've actually mapped into kernel
1500 * virtual address space.
1502 if (*firstaddr < round_2mpage(KERNend))
1503 *firstaddr = round_2mpage(KERNend);
1505 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1506 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1507 for (i = 0; i < nkpdpe; i++)
1508 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1511 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1512 * the end of physical memory is not aligned to a 1GB page boundary,
1513 * then the residual physical memory is mapped with 2MB pages. Later,
1514 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1515 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1516 * that are partially used.
1518 pd_p = (pd_entry_t *)DMPDphys;
1519 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1520 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1521 /* Preset PG_M and PG_A because demotion expects it. */
1522 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1523 X86_PG_M | X86_PG_A | pg_nx;
1525 pdp_p = (pdp_entry_t *)DMPDPphys;
1526 for (i = 0; i < ndm1g; i++) {
1527 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1528 /* Preset PG_M and PG_A because demotion expects it. */
1529 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1530 X86_PG_M | X86_PG_A | pg_nx;
1532 for (j = 0; i < ndmpdp; i++, j++) {
1533 pdp_p[i] = DMPDphys + ptoa(j);
1534 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1538 * Instead of using a 1G page for the memory containing the kernel,
1539 * use 2M pages with appropriate permissions. (If using 1G pages,
1540 * this will partially overwrite the PDPEs above.)
1543 pd_p = (pd_entry_t *)DMPDkernphys;
1544 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1545 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1546 X86_PG_M | X86_PG_A | pg_nx |
1547 bootaddr_rwx(i << PDRSHIFT);
1548 for (i = 0; i < nkdmpde; i++)
1549 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1553 /* And recursively map PML4 to itself in order to get PTmap */
1554 p4_p = (pml4_entry_t *)KPML4phys;
1555 p4_p[PML4PML4I] = KPML4phys;
1556 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1558 /* Connect the Direct Map slot(s) up to the PML4. */
1559 for (i = 0; i < ndmpdpphys; i++) {
1560 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1561 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1564 /* Connect the KVA slots up to the PML4 */
1565 for (i = 0; i < NKPML4E; i++) {
1566 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1567 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1572 * Bootstrap the system enough to run with virtual memory.
1574 * On amd64 this is called after mapping has already been enabled
1575 * and just syncs the pmap module with what has already been done.
1576 * [We can't call it easily with mapping off since the kernel is not
1577 * mapped with PA == VA, hence we would have to relocate every address
1578 * from the linked base (virtual) address "KERNBASE" to the actual
1579 * (physical) address starting relative to 0]
1582 pmap_bootstrap(vm_paddr_t *firstaddr)
1590 KERNend = *firstaddr;
1591 res = atop(KERNend - (vm_paddr_t)kernphys);
1597 * Create an initial set of page tables to run the kernel in.
1599 create_pagetables(firstaddr);
1602 * Add a physical memory segment (vm_phys_seg) corresponding to the
1603 * preallocated kernel page table pages so that vm_page structures
1604 * representing these pages will be created. The vm_page structures
1605 * are required for promotion of the corresponding kernel virtual
1606 * addresses to superpage mappings.
1608 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1611 * Account for the virtual addresses mapped by create_pagetables().
1613 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1614 virtual_end = VM_MAX_KERNEL_ADDRESS;
1617 * Enable PG_G global pages, then switch to the kernel page
1618 * table from the bootstrap page table. After the switch, it
1619 * is possible to enable SMEP and SMAP since PG_U bits are
1625 load_cr3(KPML4phys);
1626 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1628 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1633 * Initialize the kernel pmap (which is statically allocated).
1634 * Count bootstrap data as being resident in case any of this data is
1635 * later unmapped (using pmap_remove()) and freed.
1637 PMAP_LOCK_INIT(kernel_pmap);
1638 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1639 kernel_pmap->pm_cr3 = KPML4phys;
1640 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1641 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1642 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1643 kernel_pmap->pm_stats.resident_count = res;
1644 kernel_pmap->pm_flags = pmap_flags;
1647 * Initialize the TLB invalidations generation number lock.
1649 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1652 * Reserve some special page table entries/VA space for temporary
1655 #define SYSMAP(c, p, v, n) \
1656 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1662 * Crashdump maps. The first page is reused as CMAP1 for the
1665 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1666 CADDR1 = crashdumpmap;
1671 * Initialize the PAT MSR.
1672 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1673 * side-effect, invalidates stale PG_G TLB entries that might
1674 * have been created in our pre-boot environment.
1678 /* Initialize TLB Context Id. */
1679 if (pmap_pcid_enabled) {
1680 for (i = 0; i < MAXCPU; i++) {
1681 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1682 kernel_pmap->pm_pcids[i].pm_gen = 1;
1686 * PMAP_PCID_KERN + 1 is used for initialization of
1687 * proc0 pmap. The pmap' pcid state might be used by
1688 * EFIRT entry before first context switch, so it
1689 * needs to be valid.
1691 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1692 PCPU_SET(pcid_gen, 1);
1695 * pcpu area for APs is zeroed during AP startup.
1696 * pc_pcid_next and pc_pcid_gen are initialized by AP
1697 * during pcpu setup.
1699 load_cr4(rcr4() | CR4_PCIDE);
1704 * Setup the PAT MSR.
1713 /* Bail if this CPU doesn't implement PAT. */
1714 if ((cpu_feature & CPUID_PAT) == 0)
1717 /* Set default PAT index table. */
1718 for (i = 0; i < PAT_INDEX_SIZE; i++)
1720 pat_index[PAT_WRITE_BACK] = 0;
1721 pat_index[PAT_WRITE_THROUGH] = 1;
1722 pat_index[PAT_UNCACHEABLE] = 3;
1723 pat_index[PAT_WRITE_COMBINING] = 6;
1724 pat_index[PAT_WRITE_PROTECTED] = 5;
1725 pat_index[PAT_UNCACHED] = 2;
1728 * Initialize default PAT entries.
1729 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1730 * Program 5 and 6 as WP and WC.
1732 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1733 * mapping for a 2M page uses a PAT value with the bit 3 set due
1734 * to its overload with PG_PS.
1736 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1737 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1738 PAT_VALUE(2, PAT_UNCACHED) |
1739 PAT_VALUE(3, PAT_UNCACHEABLE) |
1740 PAT_VALUE(4, PAT_WRITE_BACK) |
1741 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1742 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1743 PAT_VALUE(7, PAT_UNCACHEABLE);
1747 load_cr4(cr4 & ~CR4_PGE);
1749 /* Disable caches (CD = 1, NW = 0). */
1751 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1753 /* Flushes caches and TLBs. */
1757 /* Update PAT and index table. */
1758 wrmsr(MSR_PAT, pat_msr);
1760 /* Flush caches and TLBs again. */
1764 /* Restore caches and PGE. */
1770 * Initialize a vm_page's machine-dependent fields.
1773 pmap_page_init(vm_page_t m)
1776 TAILQ_INIT(&m->md.pv_list);
1777 m->md.pat_mode = PAT_WRITE_BACK;
1781 * Initialize the pmap module.
1782 * Called by vm_init, to initialize any structures that the pmap
1783 * system needs to map virtual memory.
1788 struct pmap_preinit_mapping *ppim;
1791 int error, i, pv_npg, ret, skz63;
1793 /* L1TF, reserve page @0 unconditionally */
1794 vm_page_blacklist_add(0, bootverbose);
1796 /* Detect bare-metal Skylake Server and Skylake-X. */
1797 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1798 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1800 * Skylake-X errata SKZ63. Processor May Hang When
1801 * Executing Code In an HLE Transaction Region between
1802 * 40000000H and 403FFFFFH.
1804 * Mark the pages in the range as preallocated. It
1805 * seems to be impossible to distinguish between
1806 * Skylake Server and Skylake X.
1809 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1812 printf("SKZ63: skipping 4M RAM starting "
1813 "at physical 1G\n");
1814 for (i = 0; i < atop(0x400000); i++) {
1815 ret = vm_page_blacklist_add(0x40000000 +
1817 if (!ret && bootverbose)
1818 printf("page at %#lx already used\n",
1819 0x40000000 + ptoa(i));
1825 * Initialize the vm page array entries for the kernel pmap's
1828 PMAP_LOCK(kernel_pmap);
1829 for (i = 0; i < nkpt; i++) {
1830 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1831 KASSERT(mpte >= vm_page_array &&
1832 mpte < &vm_page_array[vm_page_array_size],
1833 ("pmap_init: page table page is out of range"));
1834 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1835 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1836 mpte->wire_count = 1;
1839 * Collect the page table pages that were replaced by a 2MB
1840 * page in create_pagetables(). They are zero filled.
1842 if (i << PDRSHIFT < KERNend &&
1843 pmap_insert_pt_page(kernel_pmap, mpte, false))
1844 panic("pmap_init: pmap_insert_pt_page failed");
1846 PMAP_UNLOCK(kernel_pmap);
1850 * If the kernel is running on a virtual machine, then it must assume
1851 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1852 * be prepared for the hypervisor changing the vendor and family that
1853 * are reported by CPUID. Consequently, the workaround for AMD Family
1854 * 10h Erratum 383 is enabled if the processor's feature set does not
1855 * include at least one feature that is only supported by older Intel
1856 * or newer AMD processors.
1858 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1859 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1860 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1862 workaround_erratum383 = 1;
1865 * Are large page mappings enabled?
1867 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1868 if (pg_ps_enabled) {
1869 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1870 ("pmap_init: can't assign to pagesizes[1]"));
1871 pagesizes[1] = NBPDR;
1875 * Initialize the pv chunk list mutex.
1877 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1880 * Initialize the pool of pv list locks.
1882 for (i = 0; i < NPV_LIST_LOCKS; i++)
1883 rw_init(&pv_list_locks[i], "pmap pv list");
1886 * Calculate the size of the pv head table for superpages.
1888 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1891 * Allocate memory for the pv head table for superpages.
1893 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1895 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1896 for (i = 0; i < pv_npg; i++)
1897 TAILQ_INIT(&pv_table[i].pv_list);
1898 TAILQ_INIT(&pv_dummy.pv_list);
1900 pmap_initialized = 1;
1901 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1902 ppim = pmap_preinit_mapping + i;
1905 /* Make the direct map consistent */
1906 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1907 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1908 ppim->sz, ppim->mode);
1912 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1913 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1916 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1917 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1918 (vmem_addr_t *)&qframe);
1920 panic("qframe allocation failed");
1923 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1924 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1925 lm_ents = LMEPML4I - LMSPML4I + 1;
1927 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1928 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1930 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1931 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1932 if (large_vmem == NULL) {
1933 printf("pmap: cannot create large map\n");
1936 for (i = 0; i < lm_ents; i++) {
1937 m = pmap_large_map_getptp_unlocked();
1938 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1939 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1945 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1946 "2MB page mapping counters");
1948 static u_long pmap_pde_demotions;
1949 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1950 &pmap_pde_demotions, 0, "2MB page demotions");
1952 static u_long pmap_pde_mappings;
1953 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1954 &pmap_pde_mappings, 0, "2MB page mappings");
1956 static u_long pmap_pde_p_failures;
1957 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1958 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1960 static u_long pmap_pde_promotions;
1961 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1962 &pmap_pde_promotions, 0, "2MB page promotions");
1964 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1965 "1GB page mapping counters");
1967 static u_long pmap_pdpe_demotions;
1968 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1969 &pmap_pdpe_demotions, 0, "1GB page demotions");
1971 /***************************************************
1972 * Low level helper routines.....
1973 ***************************************************/
1976 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1978 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1980 switch (pmap->pm_type) {
1983 /* Verify that both PAT bits are not set at the same time */
1984 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1985 ("Invalid PAT bits in entry %#lx", entry));
1987 /* Swap the PAT bits if one of them is set */
1988 if ((entry & x86_pat_bits) != 0)
1989 entry ^= x86_pat_bits;
1993 * Nothing to do - the memory attributes are represented
1994 * the same way for regular pages and superpages.
1998 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2005 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2008 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2009 pat_index[(int)mode] >= 0);
2013 * Determine the appropriate bits to set in a PTE or PDE for a specified
2017 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2019 int cache_bits, pat_flag, pat_idx;
2021 if (!pmap_is_valid_memattr(pmap, mode))
2022 panic("Unknown caching mode %d\n", mode);
2024 switch (pmap->pm_type) {
2027 /* The PAT bit is different for PTE's and PDE's. */
2028 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2030 /* Map the caching mode to a PAT index. */
2031 pat_idx = pat_index[mode];
2033 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2036 cache_bits |= pat_flag;
2038 cache_bits |= PG_NC_PCD;
2040 cache_bits |= PG_NC_PWT;
2044 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2048 panic("unsupported pmap type %d", pmap->pm_type);
2051 return (cache_bits);
2055 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2059 switch (pmap->pm_type) {
2062 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2065 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2068 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2075 pmap_ps_enabled(pmap_t pmap)
2078 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2082 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2085 switch (pmap->pm_type) {
2092 * This is a little bogus since the generation number is
2093 * supposed to be bumped up when a region of the address
2094 * space is invalidated in the page tables.
2096 * In this case the old PDE entry is valid but yet we want
2097 * to make sure that any mappings using the old entry are
2098 * invalidated in the TLB.
2100 * The reason this works as expected is because we rendezvous
2101 * "all" host cpus and force any vcpu context to exit as a
2104 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2107 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2109 pde_store(pde, newpde);
2113 * After changing the page size for the specified virtual address in the page
2114 * table, flush the corresponding entries from the processor's TLB. Only the
2115 * calling processor's TLB is affected.
2117 * The calling thread must be pinned to a processor.
2120 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2124 if (pmap_type_guest(pmap))
2127 KASSERT(pmap->pm_type == PT_X86,
2128 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2130 PG_G = pmap_global_bit(pmap);
2132 if ((newpde & PG_PS) == 0)
2133 /* Demotion: flush a specific 2MB page mapping. */
2135 else if ((newpde & PG_G) == 0)
2137 * Promotion: flush every 4KB page mapping from the TLB
2138 * because there are too many to flush individually.
2143 * Promotion: flush every 4KB page mapping from the TLB,
2144 * including any global (PG_G) mappings.
2152 * For SMP, these functions have to use the IPI mechanism for coherence.
2154 * N.B.: Before calling any of the following TLB invalidation functions,
2155 * the calling processor must ensure that all stores updating a non-
2156 * kernel page table are globally performed. Otherwise, another
2157 * processor could cache an old, pre-update entry without being
2158 * invalidated. This can happen one of two ways: (1) The pmap becomes
2159 * active on another processor after its pm_active field is checked by
2160 * one of the following functions but before a store updating the page
2161 * table is globally performed. (2) The pmap becomes active on another
2162 * processor before its pm_active field is checked but due to
2163 * speculative loads one of the following functions stills reads the
2164 * pmap as inactive on the other processor.
2166 * The kernel page table is exempt because its pm_active field is
2167 * immutable. The kernel page table is always active on every
2172 * Interrupt the cpus that are executing in the guest context.
2173 * This will force the vcpu to exit and the cached EPT mappings
2174 * will be invalidated by the host before the next vmresume.
2176 static __inline void
2177 pmap_invalidate_ept(pmap_t pmap)
2182 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2183 ("pmap_invalidate_ept: absurd pm_active"));
2186 * The TLB mappings associated with a vcpu context are not
2187 * flushed each time a different vcpu is chosen to execute.
2189 * This is in contrast with a process's vtop mappings that
2190 * are flushed from the TLB on each context switch.
2192 * Therefore we need to do more than just a TLB shootdown on
2193 * the active cpus in 'pmap->pm_active'. To do this we keep
2194 * track of the number of invalidations performed on this pmap.
2196 * Each vcpu keeps a cache of this counter and compares it
2197 * just before a vmresume. If the counter is out-of-date an
2198 * invept will be done to flush stale mappings from the TLB.
2200 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2203 * Force the vcpu to exit and trap back into the hypervisor.
2205 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2206 ipi_selected(pmap->pm_active, ipinum);
2211 pmap_invalidate_cpu_mask(pmap_t pmap)
2214 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2218 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2219 const bool invpcid_works1)
2221 struct invpcid_descr d;
2222 uint64_t kcr3, ucr3;
2226 cpuid = PCPU_GET(cpuid);
2227 if (pmap == PCPU_GET(curpmap)) {
2228 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2230 * Because pm_pcid is recalculated on a
2231 * context switch, we must disable switching.
2232 * Otherwise, we might use a stale value
2236 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2237 if (invpcid_works1) {
2238 d.pcid = pcid | PMAP_PCID_USER_PT;
2241 invpcid(&d, INVPCID_ADDR);
2243 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2244 ucr3 = pmap->pm_ucr3 | pcid |
2245 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2246 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2251 pmap->pm_pcids[cpuid].pm_gen = 0;
2255 pmap->pm_pcids[i].pm_gen = 0;
2259 * The fence is between stores to pm_gen and the read of the
2260 * pm_active mask. We need to ensure that it is impossible
2261 * for us to miss the bit update in pm_active and
2262 * simultaneously observe a non-zero pm_gen in
2263 * pmap_activate_sw(), otherwise TLB update is missed.
2264 * Without the fence, IA32 allows such an outcome. Note that
2265 * pm_active is updated by a locked operation, which provides
2266 * the reciprocal fence.
2268 atomic_thread_fence_seq_cst();
2272 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2275 pmap_invalidate_page_pcid(pmap, va, true);
2279 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2282 pmap_invalidate_page_pcid(pmap, va, false);
2286 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2290 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2293 if (pmap_pcid_enabled)
2294 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2295 pmap_invalidate_page_pcid_noinvpcid);
2296 return (pmap_invalidate_page_nopcid);
2300 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2303 if (pmap_type_guest(pmap)) {
2304 pmap_invalidate_ept(pmap);
2308 KASSERT(pmap->pm_type == PT_X86,
2309 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2312 if (pmap == kernel_pmap) {
2315 if (pmap == PCPU_GET(curpmap))
2317 pmap_invalidate_page_mode(pmap, va);
2319 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2323 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2324 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2327 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2328 const bool invpcid_works1)
2330 struct invpcid_descr d;
2331 uint64_t kcr3, ucr3;
2335 cpuid = PCPU_GET(cpuid);
2336 if (pmap == PCPU_GET(curpmap)) {
2337 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2339 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2340 if (invpcid_works1) {
2341 d.pcid = pcid | PMAP_PCID_USER_PT;
2344 for (; d.addr < eva; d.addr += PAGE_SIZE)
2345 invpcid(&d, INVPCID_ADDR);
2347 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2348 ucr3 = pmap->pm_ucr3 | pcid |
2349 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2350 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2355 pmap->pm_pcids[cpuid].pm_gen = 0;
2359 pmap->pm_pcids[i].pm_gen = 0;
2361 /* See the comment in pmap_invalidate_page_pcid(). */
2362 atomic_thread_fence_seq_cst();
2366 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2370 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2374 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2378 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2382 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2386 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2390 if (pmap_pcid_enabled)
2391 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2392 pmap_invalidate_range_pcid_noinvpcid);
2393 return (pmap_invalidate_range_nopcid);
2397 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2401 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2402 pmap_invalidate_all(pmap);
2406 if (pmap_type_guest(pmap)) {
2407 pmap_invalidate_ept(pmap);
2411 KASSERT(pmap->pm_type == PT_X86,
2412 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2415 if (pmap == kernel_pmap) {
2416 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2419 if (pmap == PCPU_GET(curpmap)) {
2420 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2423 pmap_invalidate_range_mode(pmap, sva, eva);
2425 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2430 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2432 struct invpcid_descr d;
2433 uint64_t kcr3, ucr3;
2437 if (pmap == kernel_pmap) {
2438 if (invpcid_works1) {
2439 bzero(&d, sizeof(d));
2440 invpcid(&d, INVPCID_CTXGLOB);
2445 cpuid = PCPU_GET(cpuid);
2446 if (pmap == PCPU_GET(curpmap)) {
2448 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2449 if (invpcid_works1) {
2453 invpcid(&d, INVPCID_CTX);
2454 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2455 d.pcid |= PMAP_PCID_USER_PT;
2456 invpcid(&d, INVPCID_CTX);
2459 kcr3 = pmap->pm_cr3 | pcid;
2460 ucr3 = pmap->pm_ucr3;
2461 if (ucr3 != PMAP_NO_CR3) {
2462 ucr3 |= pcid | PMAP_PCID_USER_PT;
2463 pmap_pti_pcid_invalidate(ucr3, kcr3);
2470 pmap->pm_pcids[cpuid].pm_gen = 0;
2473 pmap->pm_pcids[i].pm_gen = 0;
2476 /* See the comment in pmap_invalidate_page_pcid(). */
2477 atomic_thread_fence_seq_cst();
2481 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2484 pmap_invalidate_all_pcid(pmap, true);
2488 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2491 pmap_invalidate_all_pcid(pmap, false);
2495 pmap_invalidate_all_nopcid(pmap_t pmap)
2498 if (pmap == kernel_pmap)
2500 else if (pmap == PCPU_GET(curpmap))
2504 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2507 if (pmap_pcid_enabled)
2508 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2509 pmap_invalidate_all_pcid_noinvpcid);
2510 return (pmap_invalidate_all_nopcid);
2514 pmap_invalidate_all(pmap_t pmap)
2517 if (pmap_type_guest(pmap)) {
2518 pmap_invalidate_ept(pmap);
2522 KASSERT(pmap->pm_type == PT_X86,
2523 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2526 pmap_invalidate_all_mode(pmap);
2527 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2532 pmap_invalidate_cache(void)
2542 cpuset_t invalidate; /* processors that invalidate their TLB */
2547 u_int store; /* processor that updates the PDE */
2551 pmap_update_pde_action(void *arg)
2553 struct pde_action *act = arg;
2555 if (act->store == PCPU_GET(cpuid))
2556 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2560 pmap_update_pde_teardown(void *arg)
2562 struct pde_action *act = arg;
2564 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2565 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2569 * Change the page size for the specified virtual address in a way that
2570 * prevents any possibility of the TLB ever having two entries that map the
2571 * same virtual address using different page sizes. This is the recommended
2572 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2573 * machine check exception for a TLB state that is improperly diagnosed as a
2577 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2579 struct pde_action act;
2580 cpuset_t active, other_cpus;
2584 cpuid = PCPU_GET(cpuid);
2585 other_cpus = all_cpus;
2586 CPU_CLR(cpuid, &other_cpus);
2587 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2590 active = pmap->pm_active;
2592 if (CPU_OVERLAP(&active, &other_cpus)) {
2594 act.invalidate = active;
2598 act.newpde = newpde;
2599 CPU_SET(cpuid, &active);
2600 smp_rendezvous_cpus(active,
2601 smp_no_rendezvous_barrier, pmap_update_pde_action,
2602 pmap_update_pde_teardown, &act);
2604 pmap_update_pde_store(pmap, pde, newpde);
2605 if (CPU_ISSET(cpuid, &active))
2606 pmap_update_pde_invalidate(pmap, va, newpde);
2612 * Normal, non-SMP, invalidation functions.
2615 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2617 struct invpcid_descr d;
2618 uint64_t kcr3, ucr3;
2621 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2625 KASSERT(pmap->pm_type == PT_X86,
2626 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2628 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2630 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2631 pmap->pm_ucr3 != PMAP_NO_CR3) {
2633 pcid = pmap->pm_pcids[0].pm_pcid;
2634 if (invpcid_works) {
2635 d.pcid = pcid | PMAP_PCID_USER_PT;
2638 invpcid(&d, INVPCID_ADDR);
2640 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2641 ucr3 = pmap->pm_ucr3 | pcid |
2642 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2643 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2647 } else if (pmap_pcid_enabled)
2648 pmap->pm_pcids[0].pm_gen = 0;
2652 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2654 struct invpcid_descr d;
2656 uint64_t kcr3, ucr3;
2658 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2662 KASSERT(pmap->pm_type == PT_X86,
2663 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2665 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2666 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2668 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2669 pmap->pm_ucr3 != PMAP_NO_CR3) {
2671 if (invpcid_works) {
2672 d.pcid = pmap->pm_pcids[0].pm_pcid |
2676 for (; d.addr < eva; d.addr += PAGE_SIZE)
2677 invpcid(&d, INVPCID_ADDR);
2679 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2680 pm_pcid | CR3_PCID_SAVE;
2681 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2682 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2683 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2687 } else if (pmap_pcid_enabled) {
2688 pmap->pm_pcids[0].pm_gen = 0;
2693 pmap_invalidate_all(pmap_t pmap)
2695 struct invpcid_descr d;
2696 uint64_t kcr3, ucr3;
2698 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2702 KASSERT(pmap->pm_type == PT_X86,
2703 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2705 if (pmap == kernel_pmap) {
2706 if (pmap_pcid_enabled && invpcid_works) {
2707 bzero(&d, sizeof(d));
2708 invpcid(&d, INVPCID_CTXGLOB);
2712 } else if (pmap == PCPU_GET(curpmap)) {
2713 if (pmap_pcid_enabled) {
2715 if (invpcid_works) {
2716 d.pcid = pmap->pm_pcids[0].pm_pcid;
2719 invpcid(&d, INVPCID_CTX);
2720 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2721 d.pcid |= PMAP_PCID_USER_PT;
2722 invpcid(&d, INVPCID_CTX);
2725 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2726 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2727 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2728 0].pm_pcid | PMAP_PCID_USER_PT;
2729 pmap_pti_pcid_invalidate(ucr3, kcr3);
2737 } else if (pmap_pcid_enabled) {
2738 pmap->pm_pcids[0].pm_gen = 0;
2743 pmap_invalidate_cache(void)
2750 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2753 pmap_update_pde_store(pmap, pde, newpde);
2754 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2755 pmap_update_pde_invalidate(pmap, va, newpde);
2757 pmap->pm_pcids[0].pm_gen = 0;
2762 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2766 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2767 * by a promotion that did not invalidate the 512 4KB page mappings
2768 * that might exist in the TLB. Consequently, at this point, the TLB
2769 * may hold both 4KB and 2MB page mappings for the address range [va,
2770 * va + NBPDR). Therefore, the entire range must be invalidated here.
2771 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2772 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2773 * single INVLPG suffices to invalidate the 2MB page mapping from the
2776 if ((pde & PG_PROMOTED) != 0)
2777 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2779 pmap_invalidate_page(pmap, va);
2782 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2783 (vm_offset_t sva, vm_offset_t eva))
2786 if ((cpu_feature & CPUID_SS) != 0)
2787 return (pmap_invalidate_cache_range_selfsnoop);
2788 if ((cpu_feature & CPUID_CLFSH) != 0)
2789 return (pmap_force_invalidate_cache_range);
2790 return (pmap_invalidate_cache_range_all);
2793 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2796 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2799 KASSERT((sva & PAGE_MASK) == 0,
2800 ("pmap_invalidate_cache_range: sva not page-aligned"));
2801 KASSERT((eva & PAGE_MASK) == 0,
2802 ("pmap_invalidate_cache_range: eva not page-aligned"));
2806 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2809 pmap_invalidate_cache_range_check_align(sva, eva);
2813 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2816 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2819 * XXX: Some CPUs fault, hang, or trash the local APIC
2820 * registers if we use CLFLUSH on the local APIC range. The
2821 * local APIC is always uncached, so we don't need to flush
2822 * for that range anyway.
2824 if (pmap_kextract(sva) == lapic_paddr)
2827 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2829 * Do per-cache line flush. Use the sfence
2830 * instruction to insure that previous stores are
2831 * included in the write-back. The processor
2832 * propagates flush to other processors in the cache
2836 for (; sva < eva; sva += cpu_clflush_line_size)
2841 * Writes are ordered by CLFLUSH on Intel CPUs.
2843 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2845 for (; sva < eva; sva += cpu_clflush_line_size)
2847 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2853 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2856 pmap_invalidate_cache_range_check_align(sva, eva);
2857 pmap_invalidate_cache();
2861 * Remove the specified set of pages from the data and instruction caches.
2863 * In contrast to pmap_invalidate_cache_range(), this function does not
2864 * rely on the CPU's self-snoop feature, because it is intended for use
2865 * when moving pages into a different cache domain.
2868 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2870 vm_offset_t daddr, eva;
2874 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2875 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2876 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2877 pmap_invalidate_cache();
2881 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2883 for (i = 0; i < count; i++) {
2884 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2885 eva = daddr + PAGE_SIZE;
2886 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2895 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2901 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2904 pmap_invalidate_cache_range_check_align(sva, eva);
2906 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2907 pmap_force_invalidate_cache_range(sva, eva);
2911 /* See comment in pmap_force_invalidate_cache_range(). */
2912 if (pmap_kextract(sva) == lapic_paddr)
2916 for (; sva < eva; sva += cpu_clflush_line_size)
2922 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2926 int error, pte_bits;
2928 KASSERT((spa & PAGE_MASK) == 0,
2929 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2930 KASSERT((epa & PAGE_MASK) == 0,
2931 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2933 if (spa < dmaplimit) {
2934 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2936 if (dmaplimit >= epa)
2941 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
2943 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2945 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
2946 pte = vtopte(vaddr);
2947 for (; spa < epa; spa += PAGE_SIZE) {
2949 pte_store(pte, spa | pte_bits);
2951 /* XXXKIB sfences inside flush_cache_range are excessive */
2952 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
2955 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
2959 * Routine: pmap_extract
2961 * Extract the physical page address associated
2962 * with the given map/virtual_address pair.
2965 pmap_extract(pmap_t pmap, vm_offset_t va)
2969 pt_entry_t *pte, PG_V;
2973 PG_V = pmap_valid_bit(pmap);
2975 pdpe = pmap_pdpe(pmap, va);
2976 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2977 if ((*pdpe & PG_PS) != 0)
2978 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2980 pde = pmap_pdpe_to_pde(pdpe, va);
2981 if ((*pde & PG_V) != 0) {
2982 if ((*pde & PG_PS) != 0) {
2983 pa = (*pde & PG_PS_FRAME) |
2986 pte = pmap_pde_to_pte(pde, va);
2987 pa = (*pte & PG_FRAME) |
2998 * Routine: pmap_extract_and_hold
3000 * Atomically extract and hold the physical page
3001 * with the given pmap and virtual address pair
3002 * if that mapping permits the given protection.
3005 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3007 pd_entry_t pde, *pdep;
3008 pt_entry_t pte, PG_RW, PG_V;
3014 PG_RW = pmap_rw_bit(pmap);
3015 PG_V = pmap_valid_bit(pmap);
3018 pdep = pmap_pde(pmap, va);
3019 if (pdep != NULL && (pde = *pdep)) {
3021 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
3022 if (vm_page_pa_tryrelock(pmap, (pde &
3023 PG_PS_FRAME) | (va & PDRMASK), &pa))
3025 m = PHYS_TO_VM_PAGE(pa);
3028 pte = *pmap_pde_to_pte(pdep, va);
3030 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
3031 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
3034 m = PHYS_TO_VM_PAGE(pa);
3046 pmap_kextract(vm_offset_t va)
3051 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3052 pa = DMAP_TO_PHYS(va);
3053 } else if (LARGEMAP_MIN_ADDRESS <= va &&
3054 va < PMAP_LARGEMAP_MAX_ADDRESS()) {
3055 pa = pmap_large_map_kextract(va);
3059 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3062 * Beware of a concurrent promotion that changes the
3063 * PDE at this point! For example, vtopte() must not
3064 * be used to access the PTE because it would use the
3065 * new PDE. It is, however, safe to use the old PDE
3066 * because the page table page is preserved by the
3069 pa = *pmap_pde_to_pte(&pde, va);
3070 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3076 /***************************************************
3077 * Low level mapping routines.....
3078 ***************************************************/
3081 * Add a wired page to the kva.
3082 * Note: not SMP coherent.
3085 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3090 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
3093 static __inline void
3094 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3100 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3101 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
3105 * Remove a page from the kernel pagetables.
3106 * Note: not SMP coherent.
3109 pmap_kremove(vm_offset_t va)
3118 * Used to map a range of physical addresses into kernel
3119 * virtual address space.
3121 * The value passed in '*virt' is a suggested virtual address for
3122 * the mapping. Architectures which can support a direct-mapped
3123 * physical to virtual region can return the appropriate address
3124 * within that region, leaving '*virt' unchanged. Other
3125 * architectures should map the pages starting at '*virt' and
3126 * update '*virt' with the first usable address after the mapped
3130 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3132 return PHYS_TO_DMAP(start);
3137 * Add a list of wired pages to the kva
3138 * this routine is only used for temporary
3139 * kernel mappings that do not need to have
3140 * page modification or references recorded.
3141 * Note that old mappings are simply written
3142 * over. The page *must* be wired.
3143 * Note: SMP coherent. Uses a ranged shootdown IPI.
3146 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3148 pt_entry_t *endpte, oldpte, pa, *pte;
3154 endpte = pte + count;
3155 while (pte < endpte) {
3157 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3158 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3159 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3161 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3165 if (__predict_false((oldpte & X86_PG_V) != 0))
3166 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3171 * This routine tears out page mappings from the
3172 * kernel -- it is meant only for temporary mappings.
3173 * Note: SMP coherent. Uses a ranged shootdown IPI.
3176 pmap_qremove(vm_offset_t sva, int count)
3181 while (count-- > 0) {
3182 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3186 pmap_invalidate_range(kernel_pmap, sva, va);
3189 /***************************************************
3190 * Page table page management routines.....
3191 ***************************************************/
3193 * Schedule the specified unused page table page to be freed. Specifically,
3194 * add the page to the specified list of pages that will be released to the
3195 * physical memory manager after the TLB has been updated.
3197 static __inline void
3198 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3199 boolean_t set_PG_ZERO)
3203 m->flags |= PG_ZERO;
3205 m->flags &= ~PG_ZERO;
3206 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3210 * Inserts the specified page table page into the specified pmap's collection
3211 * of idle page table pages. Each of a pmap's page table pages is responsible
3212 * for mapping a distinct range of virtual addresses. The pmap's collection is
3213 * ordered by this virtual address range.
3215 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3218 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3221 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3222 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3223 return (vm_radix_insert(&pmap->pm_root, mpte));
3227 * Removes the page table page mapping the specified virtual address from the
3228 * specified pmap's collection of idle page table pages, and returns it.
3229 * Otherwise, returns NULL if there is no page table page corresponding to the
3230 * specified virtual address.
3232 static __inline vm_page_t
3233 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3236 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3237 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3241 * Decrements a page table page's wire count, which is used to record the
3242 * number of valid page table entries within the page. If the wire count
3243 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3244 * page table page was unmapped and FALSE otherwise.
3246 static inline boolean_t
3247 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3251 if (m->wire_count == 0) {
3252 _pmap_unwire_ptp(pmap, va, m, free);
3259 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3262 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3264 * unmap the page table page
3266 if (m->pindex >= (NUPDE + NUPDPE)) {
3269 pml4 = pmap_pml4e(pmap, va);
3271 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3272 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3275 } else if (m->pindex >= NUPDE) {
3278 pdp = pmap_pdpe(pmap, va);
3283 pd = pmap_pde(pmap, va);
3286 pmap_resident_count_dec(pmap, 1);
3287 if (m->pindex < NUPDE) {
3288 /* We just released a PT, unhold the matching PD */
3291 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3292 pmap_unwire_ptp(pmap, va, pdpg, free);
3294 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3295 /* We just released a PD, unhold the matching PDP */
3298 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3299 pmap_unwire_ptp(pmap, va, pdppg, free);
3303 * Put page on a list so that it is released after
3304 * *ALL* TLB shootdown is done
3306 pmap_add_delayed_free_list(m, free, TRUE);
3310 * After removing a page table entry, this routine is used to
3311 * conditionally free the page, and manage the hold/wire counts.
3314 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3315 struct spglist *free)
3319 if (va >= VM_MAXUSER_ADDRESS)
3321 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3322 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3323 return (pmap_unwire_ptp(pmap, va, mpte, free));
3327 pmap_pinit0(pmap_t pmap)
3333 PMAP_LOCK_INIT(pmap);
3334 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3335 pmap->pm_pml4u = NULL;
3336 pmap->pm_cr3 = KPML4phys;
3337 /* hack to keep pmap_pti_pcid_invalidate() alive */
3338 pmap->pm_ucr3 = PMAP_NO_CR3;
3339 pmap->pm_root.rt_root = 0;
3340 CPU_ZERO(&pmap->pm_active);
3341 TAILQ_INIT(&pmap->pm_pvchunk);
3342 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3343 pmap->pm_flags = pmap_flags;
3345 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3346 pmap->pm_pcids[i].pm_gen = 1;
3348 pmap_activate_boot(pmap);
3353 p->p_md.md_flags |= P_MD_KPTI;
3356 pmap_thread_init_invl_gen(td);
3358 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3359 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3360 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3366 pmap_pinit_pml4(vm_page_t pml4pg)
3368 pml4_entry_t *pm_pml4;
3371 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3373 /* Wire in kernel global address entries. */
3374 for (i = 0; i < NKPML4E; i++) {
3375 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3378 for (i = 0; i < ndmpdpphys; i++) {
3379 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3383 /* install self-referential address mapping entry(s) */
3384 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3385 X86_PG_A | X86_PG_M;
3387 /* install large map entries if configured */
3388 for (i = 0; i < lm_ents; i++)
3389 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3393 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3395 pml4_entry_t *pm_pml4;
3398 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3399 for (i = 0; i < NPML4EPG; i++)
3400 pm_pml4[i] = pti_pml4[i];
3404 * Initialize a preallocated and zeroed pmap structure,
3405 * such as one in a vmspace structure.
3408 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3410 vm_page_t pml4pg, pml4pgu;
3411 vm_paddr_t pml4phys;
3415 * allocate the page directory page
3417 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3418 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3420 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3421 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3423 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3424 pmap->pm_pcids[i].pm_gen = 0;
3426 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3427 pmap->pm_ucr3 = PMAP_NO_CR3;
3428 pmap->pm_pml4u = NULL;
3430 pmap->pm_type = pm_type;
3431 if ((pml4pg->flags & PG_ZERO) == 0)
3432 pagezero(pmap->pm_pml4);
3435 * Do not install the host kernel mappings in the nested page
3436 * tables. These mappings are meaningless in the guest physical
3438 * Install minimal kernel mappings in PTI case.
3440 if (pm_type == PT_X86) {
3441 pmap->pm_cr3 = pml4phys;
3442 pmap_pinit_pml4(pml4pg);
3443 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3444 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3445 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3446 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3447 VM_PAGE_TO_PHYS(pml4pgu));
3448 pmap_pinit_pml4_pti(pml4pgu);
3449 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3451 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3452 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3453 pkru_free_range, pmap, M_NOWAIT);
3457 pmap->pm_root.rt_root = 0;
3458 CPU_ZERO(&pmap->pm_active);
3459 TAILQ_INIT(&pmap->pm_pvchunk);
3460 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3461 pmap->pm_flags = flags;
3462 pmap->pm_eptgen = 0;
3468 pmap_pinit(pmap_t pmap)
3471 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3475 * This routine is called if the desired page table page does not exist.
3477 * If page table page allocation fails, this routine may sleep before
3478 * returning NULL. It sleeps only if a lock pointer was given.
3480 * Note: If a page allocation fails at page table level two or three,
3481 * one or two pages may be held during the wait, only to be released
3482 * afterwards. This conservative approach is easily argued to avoid
3486 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3488 vm_page_t m, pdppg, pdpg;
3489 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3491 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3493 PG_A = pmap_accessed_bit(pmap);
3494 PG_M = pmap_modified_bit(pmap);
3495 PG_V = pmap_valid_bit(pmap);
3496 PG_RW = pmap_rw_bit(pmap);
3499 * Allocate a page table page.
3501 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3502 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3503 if (lockp != NULL) {
3504 RELEASE_PV_LIST_LOCK(lockp);
3506 PMAP_ASSERT_NOT_IN_DI();
3512 * Indicate the need to retry. While waiting, the page table
3513 * page may have been allocated.
3517 if ((m->flags & PG_ZERO) == 0)
3521 * Map the pagetable page into the process address space, if
3522 * it isn't already there.
3525 if (ptepindex >= (NUPDE + NUPDPE)) {
3526 pml4_entry_t *pml4, *pml4u;
3527 vm_pindex_t pml4index;
3529 /* Wire up a new PDPE page */
3530 pml4index = ptepindex - (NUPDE + NUPDPE);
3531 pml4 = &pmap->pm_pml4[pml4index];
3532 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3533 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3535 * PTI: Make all user-space mappings in the
3536 * kernel-mode page table no-execute so that
3537 * we detect any programming errors that leave
3538 * the kernel-mode page table active on return
3541 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3544 pml4u = &pmap->pm_pml4u[pml4index];
3545 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3549 } else if (ptepindex >= NUPDE) {
3550 vm_pindex_t pml4index;
3551 vm_pindex_t pdpindex;
3555 /* Wire up a new PDE page */
3556 pdpindex = ptepindex - NUPDE;
3557 pml4index = pdpindex >> NPML4EPGSHIFT;
3559 pml4 = &pmap->pm_pml4[pml4index];
3560 if ((*pml4 & PG_V) == 0) {
3561 /* Have to allocate a new pdp, recurse */
3562 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3564 vm_page_unwire_noq(m);
3565 vm_page_free_zero(m);
3569 /* Add reference to pdp page */
3570 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3571 pdppg->wire_count++;
3573 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3575 /* Now find the pdp page */
3576 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3577 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3580 vm_pindex_t pml4index;
3581 vm_pindex_t pdpindex;
3586 /* Wire up a new PTE page */
3587 pdpindex = ptepindex >> NPDPEPGSHIFT;
3588 pml4index = pdpindex >> NPML4EPGSHIFT;
3590 /* First, find the pdp and check that its valid. */
3591 pml4 = &pmap->pm_pml4[pml4index];
3592 if ((*pml4 & PG_V) == 0) {
3593 /* Have to allocate a new pd, recurse */
3594 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3596 vm_page_unwire_noq(m);
3597 vm_page_free_zero(m);
3600 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3601 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3603 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3604 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3605 if ((*pdp & PG_V) == 0) {
3606 /* Have to allocate a new pd, recurse */
3607 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3609 vm_page_unwire_noq(m);
3610 vm_page_free_zero(m);
3614 /* Add reference to the pd page */
3615 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3619 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3621 /* Now we know where the page directory page is */
3622 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3623 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3626 pmap_resident_count_inc(pmap, 1);
3632 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3634 vm_pindex_t pdpindex, ptepindex;
3635 pdp_entry_t *pdpe, PG_V;
3638 PG_V = pmap_valid_bit(pmap);
3641 pdpe = pmap_pdpe(pmap, va);
3642 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3643 /* Add a reference to the pd page. */
3644 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3647 /* Allocate a pd page. */
3648 ptepindex = pmap_pde_pindex(va);
3649 pdpindex = ptepindex >> NPDPEPGSHIFT;
3650 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3651 if (pdpg == NULL && lockp != NULL)
3658 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3660 vm_pindex_t ptepindex;
3661 pd_entry_t *pd, PG_V;
3664 PG_V = pmap_valid_bit(pmap);
3667 * Calculate pagetable page index
3669 ptepindex = pmap_pde_pindex(va);
3672 * Get the page directory entry
3674 pd = pmap_pde(pmap, va);
3677 * This supports switching from a 2MB page to a
3680 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3681 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3683 * Invalidation of the 2MB page mapping may have caused
3684 * the deallocation of the underlying PD page.
3691 * If the page table page is mapped, we just increment the
3692 * hold count, and activate it.
3694 if (pd != NULL && (*pd & PG_V) != 0) {
3695 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3699 * Here if the pte page isn't mapped, or if it has been
3702 m = _pmap_allocpte(pmap, ptepindex, lockp);
3703 if (m == NULL && lockp != NULL)
3710 /***************************************************
3711 * Pmap allocation/deallocation routines.
3712 ***************************************************/
3715 * Release any resources held by the given physical map.
3716 * Called when a pmap initialized by pmap_pinit is being released.
3717 * Should only be called if the map contains no valid mappings.
3720 pmap_release(pmap_t pmap)
3725 KASSERT(pmap->pm_stats.resident_count == 0,
3726 ("pmap_release: pmap resident count %ld != 0",
3727 pmap->pm_stats.resident_count));
3728 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3729 ("pmap_release: pmap has reserved page table page(s)"));
3730 KASSERT(CPU_EMPTY(&pmap->pm_active),
3731 ("releasing active pmap %p", pmap));
3733 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3735 for (i = 0; i < NKPML4E; i++) /* KVA */
3736 pmap->pm_pml4[KPML4BASE + i] = 0;
3737 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3738 pmap->pm_pml4[DMPML4I + i] = 0;
3739 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3740 for (i = 0; i < lm_ents; i++) /* Large Map */
3741 pmap->pm_pml4[LMSPML4I + i] = 0;
3743 vm_page_unwire_noq(m);
3744 vm_page_free_zero(m);
3746 if (pmap->pm_pml4u != NULL) {
3747 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3748 vm_page_unwire_noq(m);
3751 if (pmap->pm_type == PT_X86 &&
3752 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3753 rangeset_fini(&pmap->pm_pkru);
3757 kvm_size(SYSCTL_HANDLER_ARGS)
3759 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3761 return sysctl_handle_long(oidp, &ksize, 0, req);
3763 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3764 0, 0, kvm_size, "LU", "Size of KVM");
3767 kvm_free(SYSCTL_HANDLER_ARGS)
3769 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3771 return sysctl_handle_long(oidp, &kfree, 0, req);
3773 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3774 0, 0, kvm_free, "LU", "Amount of KVM free");
3777 * grow the number of kernel page table entries, if needed
3780 pmap_growkernel(vm_offset_t addr)
3784 pd_entry_t *pde, newpdir;
3787 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3790 * Return if "addr" is within the range of kernel page table pages
3791 * that were preallocated during pmap bootstrap. Moreover, leave
3792 * "kernel_vm_end" and the kernel page table as they were.
3794 * The correctness of this action is based on the following
3795 * argument: vm_map_insert() allocates contiguous ranges of the
3796 * kernel virtual address space. It calls this function if a range
3797 * ends after "kernel_vm_end". If the kernel is mapped between
3798 * "kernel_vm_end" and "addr", then the range cannot begin at
3799 * "kernel_vm_end". In fact, its beginning address cannot be less
3800 * than the kernel. Thus, there is no immediate need to allocate
3801 * any new kernel page table pages between "kernel_vm_end" and
3804 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3807 addr = roundup2(addr, NBPDR);
3808 if (addr - 1 >= vm_map_max(kernel_map))
3809 addr = vm_map_max(kernel_map);
3810 while (kernel_vm_end < addr) {
3811 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3812 if ((*pdpe & X86_PG_V) == 0) {
3813 /* We need a new PDP entry */
3814 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3815 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3816 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3818 panic("pmap_growkernel: no memory to grow kernel");
3819 if ((nkpg->flags & PG_ZERO) == 0)
3820 pmap_zero_page(nkpg);
3821 paddr = VM_PAGE_TO_PHYS(nkpg);
3822 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3823 X86_PG_A | X86_PG_M);
3824 continue; /* try again */
3826 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3827 if ((*pde & X86_PG_V) != 0) {
3828 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3829 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3830 kernel_vm_end = vm_map_max(kernel_map);
3836 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3837 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3840 panic("pmap_growkernel: no memory to grow kernel");
3841 if ((nkpg->flags & PG_ZERO) == 0)
3842 pmap_zero_page(nkpg);
3843 paddr = VM_PAGE_TO_PHYS(nkpg);
3844 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3845 pde_store(pde, newpdir);
3847 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3848 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3849 kernel_vm_end = vm_map_max(kernel_map);
3856 /***************************************************
3857 * page management routines.
3858 ***************************************************/
3860 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3861 CTASSERT(_NPCM == 3);
3862 CTASSERT(_NPCPV == 168);
3864 static __inline struct pv_chunk *
3865 pv_to_chunk(pv_entry_t pv)
3868 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3871 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3873 #define PC_FREE0 0xfffffffffffffffful
3874 #define PC_FREE1 0xfffffffffffffffful
3875 #define PC_FREE2 0x000000fffffffffful
3877 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3880 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3882 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3883 "Current number of pv entry chunks");
3884 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3885 "Current number of pv entry chunks allocated");
3886 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3887 "Current number of pv entry chunks frees");
3888 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3889 "Number of times tried to get a chunk page but failed.");
3891 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3892 static int pv_entry_spare;
3894 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3895 "Current number of pv entry frees");
3896 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3897 "Current number of pv entry allocs");
3898 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3899 "Current number of pv entries");
3900 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3901 "Current number of spare pv entries");
3905 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3910 pmap_invalidate_all(pmap);
3911 if (pmap != locked_pmap)
3914 pmap_delayed_invl_finish();
3918 * We are in a serious low memory condition. Resort to
3919 * drastic measures to free some pages so we can allocate
3920 * another pv entry chunk.
3922 * Returns NULL if PV entries were reclaimed from the specified pmap.
3924 * We do not, however, unmap 2mpages because subsequent accesses will
3925 * allocate per-page pv entries until repromotion occurs, thereby
3926 * exacerbating the shortage of free pv entries.
3929 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3931 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3932 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3933 struct md_page *pvh;
3935 pmap_t next_pmap, pmap;
3936 pt_entry_t *pte, tpte;
3937 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3941 struct spglist free;
3943 int bit, field, freed;
3945 static int active_reclaims = 0;
3947 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3948 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3951 PG_G = PG_A = PG_M = PG_RW = 0;
3953 bzero(&pc_marker_b, sizeof(pc_marker_b));
3954 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3955 pc_marker = (struct pv_chunk *)&pc_marker_b;
3956 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3959 * A delayed invalidation block should already be active if
3960 * pmap_advise() or pmap_remove() called this function by way
3961 * of pmap_demote_pde_locked().
3963 start_di = pmap_not_in_di();
3965 mtx_lock(&pv_chunks_mutex);
3967 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3968 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3969 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3970 SLIST_EMPTY(&free)) {
3971 next_pmap = pc->pc_pmap;
3972 if (next_pmap == NULL) {
3974 * The next chunk is a marker. However, it is
3975 * not our marker, so active_reclaims must be
3976 * > 1. Consequently, the next_chunk code
3977 * will not rotate the pv_chunks list.
3981 mtx_unlock(&pv_chunks_mutex);
3984 * A pv_chunk can only be removed from the pc_lru list
3985 * when both pc_chunks_mutex is owned and the
3986 * corresponding pmap is locked.
3988 if (pmap != next_pmap) {
3989 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3992 /* Avoid deadlock and lock recursion. */
3993 if (pmap > locked_pmap) {
3994 RELEASE_PV_LIST_LOCK(lockp);
3997 pmap_delayed_invl_start();
3998 mtx_lock(&pv_chunks_mutex);
4000 } else if (pmap != locked_pmap) {
4001 if (PMAP_TRYLOCK(pmap)) {
4003 pmap_delayed_invl_start();
4004 mtx_lock(&pv_chunks_mutex);
4007 pmap = NULL; /* pmap is not locked */
4008 mtx_lock(&pv_chunks_mutex);
4009 pc = TAILQ_NEXT(pc_marker, pc_lru);
4011 pc->pc_pmap != next_pmap)
4015 } else if (start_di)
4016 pmap_delayed_invl_start();
4017 PG_G = pmap_global_bit(pmap);
4018 PG_A = pmap_accessed_bit(pmap);
4019 PG_M = pmap_modified_bit(pmap);
4020 PG_RW = pmap_rw_bit(pmap);
4024 * Destroy every non-wired, 4 KB page mapping in the chunk.
4027 for (field = 0; field < _NPCM; field++) {
4028 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4029 inuse != 0; inuse &= ~(1UL << bit)) {
4031 pv = &pc->pc_pventry[field * 64 + bit];
4033 pde = pmap_pde(pmap, va);
4034 if ((*pde & PG_PS) != 0)
4036 pte = pmap_pde_to_pte(pde, va);
4037 if ((*pte & PG_W) != 0)
4039 tpte = pte_load_clear(pte);
4040 if ((tpte & PG_G) != 0)
4041 pmap_invalidate_page(pmap, va);
4042 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4043 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4045 if ((tpte & PG_A) != 0)
4046 vm_page_aflag_set(m, PGA_REFERENCED);
4047 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4048 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4050 if (TAILQ_EMPTY(&m->md.pv_list) &&
4051 (m->flags & PG_FICTITIOUS) == 0) {
4052 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4053 if (TAILQ_EMPTY(&pvh->pv_list)) {
4054 vm_page_aflag_clear(m,
4058 pmap_delayed_invl_page(m);
4059 pc->pc_map[field] |= 1UL << bit;
4060 pmap_unuse_pt(pmap, va, *pde, &free);
4065 mtx_lock(&pv_chunks_mutex);
4068 /* Every freed mapping is for a 4 KB page. */
4069 pmap_resident_count_dec(pmap, freed);
4070 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4071 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4072 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4073 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4074 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4075 pc->pc_map[2] == PC_FREE2) {
4076 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4077 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4078 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4079 /* Entire chunk is free; return it. */
4080 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4081 dump_drop_page(m_pc->phys_addr);
4082 mtx_lock(&pv_chunks_mutex);
4083 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4086 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4087 mtx_lock(&pv_chunks_mutex);
4088 /* One freed pv entry in locked_pmap is sufficient. */
4089 if (pmap == locked_pmap)
4092 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4093 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
4094 if (active_reclaims == 1 && pmap != NULL) {
4096 * Rotate the pv chunks list so that we do not
4097 * scan the same pv chunks that could not be
4098 * freed (because they contained a wired
4099 * and/or superpage mapping) on every
4100 * invocation of reclaim_pv_chunk().
4102 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4103 MPASS(pc->pc_pmap != NULL);
4104 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4105 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4109 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4110 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4112 mtx_unlock(&pv_chunks_mutex);
4113 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4114 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4115 m_pc = SLIST_FIRST(&free);
4116 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4117 /* Recycle a freed page table page. */
4118 m_pc->wire_count = 1;
4120 vm_page_free_pages_toq(&free, true);
4125 * free the pv_entry back to the free list
4128 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4130 struct pv_chunk *pc;
4131 int idx, field, bit;
4133 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4134 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4135 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4136 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4137 pc = pv_to_chunk(pv);
4138 idx = pv - &pc->pc_pventry[0];
4141 pc->pc_map[field] |= 1ul << bit;
4142 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4143 pc->pc_map[2] != PC_FREE2) {
4144 /* 98% of the time, pc is already at the head of the list. */
4145 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4146 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4147 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4151 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4156 free_pv_chunk(struct pv_chunk *pc)
4160 mtx_lock(&pv_chunks_mutex);
4161 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4162 mtx_unlock(&pv_chunks_mutex);
4163 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4164 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4165 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4166 /* entire chunk is free, return it */
4167 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4168 dump_drop_page(m->phys_addr);
4169 vm_page_unwire_noq(m);
4174 * Returns a new PV entry, allocating a new PV chunk from the system when
4175 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4176 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4179 * The given PV list lock may be released.
4182 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4186 struct pv_chunk *pc;
4189 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4190 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4192 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4194 for (field = 0; field < _NPCM; field++) {
4195 if (pc->pc_map[field]) {
4196 bit = bsfq(pc->pc_map[field]);
4200 if (field < _NPCM) {
4201 pv = &pc->pc_pventry[field * 64 + bit];
4202 pc->pc_map[field] &= ~(1ul << bit);
4203 /* If this was the last item, move it to tail */
4204 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4205 pc->pc_map[2] == 0) {
4206 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4207 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4210 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4211 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4215 /* No free items, allocate another chunk */
4216 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4219 if (lockp == NULL) {
4220 PV_STAT(pc_chunk_tryfail++);
4223 m = reclaim_pv_chunk(pmap, lockp);
4227 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4228 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4229 dump_add_page(m->phys_addr);
4230 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4232 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4233 pc->pc_map[1] = PC_FREE1;
4234 pc->pc_map[2] = PC_FREE2;
4235 mtx_lock(&pv_chunks_mutex);
4236 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4237 mtx_unlock(&pv_chunks_mutex);
4238 pv = &pc->pc_pventry[0];
4239 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4240 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4241 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4246 * Returns the number of one bits within the given PV chunk map.
4248 * The erratas for Intel processors state that "POPCNT Instruction May
4249 * Take Longer to Execute Than Expected". It is believed that the
4250 * issue is the spurious dependency on the destination register.
4251 * Provide a hint to the register rename logic that the destination
4252 * value is overwritten, by clearing it, as suggested in the
4253 * optimization manual. It should be cheap for unaffected processors
4256 * Reference numbers for erratas are
4257 * 4th Gen Core: HSD146
4258 * 5th Gen Core: BDM85
4259 * 6th Gen Core: SKL029
4262 popcnt_pc_map_pq(uint64_t *map)
4266 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4267 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4268 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4269 : "=&r" (result), "=&r" (tmp)
4270 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4275 * Ensure that the number of spare PV entries in the specified pmap meets or
4276 * exceeds the given count, "needed".
4278 * The given PV list lock may be released.
4281 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4283 struct pch new_tail;
4284 struct pv_chunk *pc;
4289 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4290 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4293 * Newly allocated PV chunks must be stored in a private list until
4294 * the required number of PV chunks have been allocated. Otherwise,
4295 * reclaim_pv_chunk() could recycle one of these chunks. In
4296 * contrast, these chunks must be added to the pmap upon allocation.
4298 TAILQ_INIT(&new_tail);
4301 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4303 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4304 bit_count((bitstr_t *)pc->pc_map, 0,
4305 sizeof(pc->pc_map) * NBBY, &free);
4308 free = popcnt_pc_map_pq(pc->pc_map);
4312 if (avail >= needed)
4315 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4316 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4319 m = reclaim_pv_chunk(pmap, lockp);
4324 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4325 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4326 dump_add_page(m->phys_addr);
4327 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4329 pc->pc_map[0] = PC_FREE0;
4330 pc->pc_map[1] = PC_FREE1;
4331 pc->pc_map[2] = PC_FREE2;
4332 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4333 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4334 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4337 * The reclaim might have freed a chunk from the current pmap.
4338 * If that chunk contained available entries, we need to
4339 * re-count the number of available entries.
4344 if (!TAILQ_EMPTY(&new_tail)) {
4345 mtx_lock(&pv_chunks_mutex);
4346 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4347 mtx_unlock(&pv_chunks_mutex);
4352 * First find and then remove the pv entry for the specified pmap and virtual
4353 * address from the specified pv list. Returns the pv entry if found and NULL
4354 * otherwise. This operation can be performed on pv lists for either 4KB or
4355 * 2MB page mappings.
4357 static __inline pv_entry_t
4358 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4362 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4363 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4364 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4373 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4374 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4375 * entries for each of the 4KB page mappings.
4378 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4379 struct rwlock **lockp)
4381 struct md_page *pvh;
4382 struct pv_chunk *pc;
4384 vm_offset_t va_last;
4388 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4389 KASSERT((pa & PDRMASK) == 0,
4390 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4391 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4394 * Transfer the 2mpage's pv entry for this mapping to the first
4395 * page's pv list. Once this transfer begins, the pv list lock
4396 * must not be released until the last pv entry is reinstantiated.
4398 pvh = pa_to_pvh(pa);
4399 va = trunc_2mpage(va);
4400 pv = pmap_pvh_remove(pvh, pmap, va);
4401 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4402 m = PHYS_TO_VM_PAGE(pa);
4403 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4405 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4406 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4407 va_last = va + NBPDR - PAGE_SIZE;
4409 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4410 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4411 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4412 for (field = 0; field < _NPCM; field++) {
4413 while (pc->pc_map[field]) {
4414 bit = bsfq(pc->pc_map[field]);
4415 pc->pc_map[field] &= ~(1ul << bit);
4416 pv = &pc->pc_pventry[field * 64 + bit];
4420 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4421 ("pmap_pv_demote_pde: page %p is not managed", m));
4422 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4428 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4429 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4432 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4433 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4434 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4436 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4437 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4440 #if VM_NRESERVLEVEL > 0
4442 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4443 * replace the many pv entries for the 4KB page mappings by a single pv entry
4444 * for the 2MB page mapping.
4447 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4448 struct rwlock **lockp)
4450 struct md_page *pvh;
4452 vm_offset_t va_last;
4455 KASSERT((pa & PDRMASK) == 0,
4456 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4457 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4460 * Transfer the first page's pv entry for this mapping to the 2mpage's
4461 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4462 * a transfer avoids the possibility that get_pv_entry() calls
4463 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4464 * mappings that is being promoted.
4466 m = PHYS_TO_VM_PAGE(pa);
4467 va = trunc_2mpage(va);
4468 pv = pmap_pvh_remove(&m->md, pmap, va);
4469 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4470 pvh = pa_to_pvh(pa);
4471 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4473 /* Free the remaining NPTEPG - 1 pv entries. */
4474 va_last = va + NBPDR - PAGE_SIZE;
4478 pmap_pvh_free(&m->md, pmap, va);
4479 } while (va < va_last);
4481 #endif /* VM_NRESERVLEVEL > 0 */
4484 * First find and then destroy the pv entry for the specified pmap and virtual
4485 * address. This operation can be performed on pv lists for either 4KB or 2MB
4489 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4493 pv = pmap_pvh_remove(pvh, pmap, va);
4494 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4495 free_pv_entry(pmap, pv);
4499 * Conditionally create the PV entry for a 4KB page mapping if the required
4500 * memory can be allocated without resorting to reclamation.
4503 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4504 struct rwlock **lockp)
4508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4509 /* Pass NULL instead of the lock pointer to disable reclamation. */
4510 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4512 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4513 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4521 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4522 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4523 * false if the PV entry cannot be allocated without resorting to reclamation.
4526 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4527 struct rwlock **lockp)
4529 struct md_page *pvh;
4533 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4534 /* Pass NULL instead of the lock pointer to disable reclamation. */
4535 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4536 NULL : lockp)) == NULL)
4539 pa = pde & PG_PS_FRAME;
4540 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4541 pvh = pa_to_pvh(pa);
4542 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4548 * Fills a page table page with mappings to consecutive physical pages.
4551 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4555 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4557 newpte += PAGE_SIZE;
4562 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4563 * mapping is invalidated.
4566 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4568 struct rwlock *lock;
4572 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4579 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4583 pt_entry_t *xpte, *ypte;
4585 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4586 xpte++, newpte += PAGE_SIZE) {
4587 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4588 printf("pmap_demote_pde: xpte %zd and newpte map "
4589 "different pages: found %#lx, expected %#lx\n",
4590 xpte - firstpte, *xpte, newpte);
4591 printf("page table dump\n");
4592 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4593 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4598 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4599 ("pmap_demote_pde: firstpte and newpte map different physical"
4606 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4607 pd_entry_t oldpde, struct rwlock **lockp)
4609 struct spglist free;
4613 sva = trunc_2mpage(va);
4614 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4615 if ((oldpde & pmap_global_bit(pmap)) == 0)
4616 pmap_invalidate_pde_page(pmap, sva, oldpde);
4617 vm_page_free_pages_toq(&free, true);
4618 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
4623 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4624 struct rwlock **lockp)
4626 pd_entry_t newpde, oldpde;
4627 pt_entry_t *firstpte, newpte;
4628 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4634 PG_A = pmap_accessed_bit(pmap);
4635 PG_G = pmap_global_bit(pmap);
4636 PG_M = pmap_modified_bit(pmap);
4637 PG_RW = pmap_rw_bit(pmap);
4638 PG_V = pmap_valid_bit(pmap);
4639 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4640 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4642 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4643 in_kernel = va >= VM_MAXUSER_ADDRESS;
4645 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4646 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4649 * Invalidate the 2MB page mapping and return "failure" if the
4650 * mapping was never accessed.
4652 if ((oldpde & PG_A) == 0) {
4653 KASSERT((oldpde & PG_W) == 0,
4654 ("pmap_demote_pde: a wired mapping is missing PG_A"));
4655 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4659 mpte = pmap_remove_pt_page(pmap, va);
4661 KASSERT((oldpde & PG_W) == 0,
4662 ("pmap_demote_pde: page table page for a wired mapping"
4666 * If the page table page is missing and the mapping
4667 * is for a kernel address, the mapping must belong to
4668 * the direct map. Page table pages are preallocated
4669 * for every other part of the kernel address space,
4670 * so the direct map region is the only part of the
4671 * kernel address space that must be handled here.
4673 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
4674 va < DMAP_MAX_ADDRESS),
4675 ("pmap_demote_pde: No saved mpte for va %#lx", va));
4678 * If the 2MB page mapping belongs to the direct map
4679 * region of the kernel's address space, then the page
4680 * allocation request specifies the highest possible
4681 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
4682 * priority is normal.
4684 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
4685 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4686 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4689 * If the allocation of the new page table page fails,
4690 * invalidate the 2MB page mapping and return "failure".
4693 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4698 mpte->wire_count = NPTEPG;
4699 pmap_resident_count_inc(pmap, 1);
4702 mptepa = VM_PAGE_TO_PHYS(mpte);
4703 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4704 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4705 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4706 ("pmap_demote_pde: oldpde is missing PG_M"));
4707 newpte = oldpde & ~PG_PS;
4708 newpte = pmap_swap_pat(pmap, newpte);
4711 * If the page table page is not leftover from an earlier promotion,
4714 if (mpte->valid == 0)
4715 pmap_fill_ptp(firstpte, newpte);
4717 pmap_demote_pde_check(firstpte, newpte);
4720 * If the mapping has changed attributes, update the page table
4723 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4724 pmap_fill_ptp(firstpte, newpte);
4727 * The spare PV entries must be reserved prior to demoting the
4728 * mapping, that is, prior to changing the PDE. Otherwise, the state
4729 * of the PDE and the PV lists will be inconsistent, which can result
4730 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4731 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4732 * PV entry for the 2MB page mapping that is being demoted.
4734 if ((oldpde & PG_MANAGED) != 0)
4735 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4738 * Demote the mapping. This pmap is locked. The old PDE has
4739 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4740 * set. Thus, there is no danger of a race with another
4741 * processor changing the setting of PG_A and/or PG_M between
4742 * the read above and the store below.
4744 if (workaround_erratum383)
4745 pmap_update_pde(pmap, va, pde, newpde);
4747 pde_store(pde, newpde);
4750 * Invalidate a stale recursive mapping of the page table page.
4753 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4756 * Demote the PV entry.
4758 if ((oldpde & PG_MANAGED) != 0)
4759 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4761 atomic_add_long(&pmap_pde_demotions, 1);
4762 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
4768 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4771 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4777 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4778 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4779 mpte = pmap_remove_pt_page(pmap, va);
4781 panic("pmap_remove_kernel_pde: Missing pt page.");
4783 mptepa = VM_PAGE_TO_PHYS(mpte);
4784 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4787 * If this page table page was unmapped by a promotion, then it
4788 * contains valid mappings. Zero it to invalidate those mappings.
4790 if (mpte->valid != 0)
4791 pagezero((void *)PHYS_TO_DMAP(mptepa));
4794 * Demote the mapping.
4796 if (workaround_erratum383)
4797 pmap_update_pde(pmap, va, pde, newpde);
4799 pde_store(pde, newpde);
4802 * Invalidate a stale recursive mapping of the page table page.
4804 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4808 * pmap_remove_pde: do the things to unmap a superpage in a process
4811 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4812 struct spglist *free, struct rwlock **lockp)
4814 struct md_page *pvh;
4816 vm_offset_t eva, va;
4818 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4820 PG_G = pmap_global_bit(pmap);
4821 PG_A = pmap_accessed_bit(pmap);
4822 PG_M = pmap_modified_bit(pmap);
4823 PG_RW = pmap_rw_bit(pmap);
4825 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4826 KASSERT((sva & PDRMASK) == 0,
4827 ("pmap_remove_pde: sva is not 2mpage aligned"));
4828 oldpde = pte_load_clear(pdq);
4830 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4831 if ((oldpde & PG_G) != 0)
4832 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4833 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4834 if (oldpde & PG_MANAGED) {
4835 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4836 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4837 pmap_pvh_free(pvh, pmap, sva);
4839 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4840 va < eva; va += PAGE_SIZE, m++) {
4841 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4844 vm_page_aflag_set(m, PGA_REFERENCED);
4845 if (TAILQ_EMPTY(&m->md.pv_list) &&
4846 TAILQ_EMPTY(&pvh->pv_list))
4847 vm_page_aflag_clear(m, PGA_WRITEABLE);
4848 pmap_delayed_invl_page(m);
4851 if (pmap == kernel_pmap) {
4852 pmap_remove_kernel_pde(pmap, pdq, sva);
4854 mpte = pmap_remove_pt_page(pmap, sva);
4856 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4857 ("pmap_remove_pde: pte page not promoted"));
4858 pmap_resident_count_dec(pmap, 1);
4859 KASSERT(mpte->wire_count == NPTEPG,
4860 ("pmap_remove_pde: pte page wire count error"));
4861 mpte->wire_count = 0;
4862 pmap_add_delayed_free_list(mpte, free, FALSE);
4865 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4869 * pmap_remove_pte: do the things to unmap a page in a process
4872 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4873 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4875 struct md_page *pvh;
4876 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4879 PG_A = pmap_accessed_bit(pmap);
4880 PG_M = pmap_modified_bit(pmap);
4881 PG_RW = pmap_rw_bit(pmap);
4883 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4884 oldpte = pte_load_clear(ptq);
4886 pmap->pm_stats.wired_count -= 1;
4887 pmap_resident_count_dec(pmap, 1);
4888 if (oldpte & PG_MANAGED) {
4889 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4890 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4893 vm_page_aflag_set(m, PGA_REFERENCED);
4894 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4895 pmap_pvh_free(&m->md, pmap, va);
4896 if (TAILQ_EMPTY(&m->md.pv_list) &&
4897 (m->flags & PG_FICTITIOUS) == 0) {
4898 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4899 if (TAILQ_EMPTY(&pvh->pv_list))
4900 vm_page_aflag_clear(m, PGA_WRITEABLE);
4902 pmap_delayed_invl_page(m);
4904 return (pmap_unuse_pt(pmap, va, ptepde, free));
4908 * Remove a single page from a process address space
4911 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4912 struct spglist *free)
4914 struct rwlock *lock;
4915 pt_entry_t *pte, PG_V;
4917 PG_V = pmap_valid_bit(pmap);
4918 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4919 if ((*pde & PG_V) == 0)
4921 pte = pmap_pde_to_pte(pde, va);
4922 if ((*pte & PG_V) == 0)
4925 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4928 pmap_invalidate_page(pmap, va);
4932 * Removes the specified range of addresses from the page table page.
4935 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4936 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4938 pt_entry_t PG_G, *pte;
4942 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4943 PG_G = pmap_global_bit(pmap);
4946 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4950 pmap_invalidate_range(pmap, va, sva);
4955 if ((*pte & PG_G) == 0)
4959 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4965 pmap_invalidate_range(pmap, va, sva);
4970 * Remove the given range of addresses from the specified map.
4972 * It is assumed that the start and end are properly
4973 * rounded to the page size.
4976 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4978 struct rwlock *lock;
4979 vm_offset_t va_next;
4980 pml4_entry_t *pml4e;
4982 pd_entry_t ptpaddr, *pde;
4983 pt_entry_t PG_G, PG_V;
4984 struct spglist free;
4987 PG_G = pmap_global_bit(pmap);
4988 PG_V = pmap_valid_bit(pmap);
4991 * Perform an unsynchronized read. This is, however, safe.
4993 if (pmap->pm_stats.resident_count == 0)
4999 pmap_delayed_invl_start();
5001 pmap_pkru_on_remove(pmap, sva, eva);
5004 * special handling of removing one page. a very
5005 * common operation and easy to short circuit some
5008 if (sva + PAGE_SIZE == eva) {
5009 pde = pmap_pde(pmap, sva);
5010 if (pde && (*pde & PG_PS) == 0) {
5011 pmap_remove_page(pmap, sva, pde, &free);
5017 for (; sva < eva; sva = va_next) {
5019 if (pmap->pm_stats.resident_count == 0)
5022 pml4e = pmap_pml4e(pmap, sva);
5023 if ((*pml4e & PG_V) == 0) {
5024 va_next = (sva + NBPML4) & ~PML4MASK;
5030 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5031 if ((*pdpe & PG_V) == 0) {
5032 va_next = (sva + NBPDP) & ~PDPMASK;
5039 * Calculate index for next page table.
5041 va_next = (sva + NBPDR) & ~PDRMASK;
5045 pde = pmap_pdpe_to_pde(pdpe, sva);
5049 * Weed out invalid mappings.
5055 * Check for large page.
5057 if ((ptpaddr & PG_PS) != 0) {
5059 * Are we removing the entire large page? If not,
5060 * demote the mapping and fall through.
5062 if (sva + NBPDR == va_next && eva >= va_next) {
5064 * The TLB entry for a PG_G mapping is
5065 * invalidated by pmap_remove_pde().
5067 if ((ptpaddr & PG_G) == 0)
5069 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5071 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5073 /* The large page mapping was destroyed. */
5080 * Limit our scan to either the end of the va represented
5081 * by the current page table page, or to the end of the
5082 * range being removed.
5087 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5094 pmap_invalidate_all(pmap);
5096 pmap_delayed_invl_finish();
5097 vm_page_free_pages_toq(&free, true);
5101 * Routine: pmap_remove_all
5103 * Removes this physical page from
5104 * all physical maps in which it resides.
5105 * Reflects back modify bits to the pager.
5108 * Original versions of this routine were very
5109 * inefficient because they iteratively called
5110 * pmap_remove (slow...)
5114 pmap_remove_all(vm_page_t m)
5116 struct md_page *pvh;
5119 struct rwlock *lock;
5120 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5123 struct spglist free;
5124 int pvh_gen, md_gen;
5126 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5127 ("pmap_remove_all: page %p is not managed", m));
5129 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5130 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5131 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5134 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5136 if (!PMAP_TRYLOCK(pmap)) {
5137 pvh_gen = pvh->pv_gen;
5141 if (pvh_gen != pvh->pv_gen) {
5148 pde = pmap_pde(pmap, va);
5149 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5152 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5154 if (!PMAP_TRYLOCK(pmap)) {
5155 pvh_gen = pvh->pv_gen;
5156 md_gen = m->md.pv_gen;
5160 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5166 PG_A = pmap_accessed_bit(pmap);
5167 PG_M = pmap_modified_bit(pmap);
5168 PG_RW = pmap_rw_bit(pmap);
5169 pmap_resident_count_dec(pmap, 1);
5170 pde = pmap_pde(pmap, pv->pv_va);
5171 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5172 " a 2mpage in page %p's pv list", m));
5173 pte = pmap_pde_to_pte(pde, pv->pv_va);
5174 tpte = pte_load_clear(pte);
5176 pmap->pm_stats.wired_count--;
5178 vm_page_aflag_set(m, PGA_REFERENCED);
5181 * Update the vm_page_t clean and reference bits.
5183 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5185 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5186 pmap_invalidate_page(pmap, pv->pv_va);
5187 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5189 free_pv_entry(pmap, pv);
5192 vm_page_aflag_clear(m, PGA_WRITEABLE);
5194 pmap_delayed_invl_wait(m);
5195 vm_page_free_pages_toq(&free, true);
5199 * pmap_protect_pde: do the things to protect a 2mpage in a process
5202 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5204 pd_entry_t newpde, oldpde;
5205 vm_offset_t eva, va;
5207 boolean_t anychanged;
5208 pt_entry_t PG_G, PG_M, PG_RW;
5210 PG_G = pmap_global_bit(pmap);
5211 PG_M = pmap_modified_bit(pmap);
5212 PG_RW = pmap_rw_bit(pmap);
5214 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5215 KASSERT((sva & PDRMASK) == 0,
5216 ("pmap_protect_pde: sva is not 2mpage aligned"));
5219 oldpde = newpde = *pde;
5220 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5221 (PG_MANAGED | PG_M | PG_RW)) {
5223 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5224 va < eva; va += PAGE_SIZE, m++)
5227 if ((prot & VM_PROT_WRITE) == 0)
5228 newpde &= ~(PG_RW | PG_M);
5229 if ((prot & VM_PROT_EXECUTE) == 0)
5231 if (newpde != oldpde) {
5233 * As an optimization to future operations on this PDE, clear
5234 * PG_PROMOTED. The impending invalidation will remove any
5235 * lingering 4KB page mappings from the TLB.
5237 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5239 if ((oldpde & PG_G) != 0)
5240 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5244 return (anychanged);
5248 * Set the physical protection on the
5249 * specified range of this map as requested.
5252 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5254 vm_offset_t va_next;
5255 pml4_entry_t *pml4e;
5257 pd_entry_t ptpaddr, *pde;
5258 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5259 boolean_t anychanged;
5261 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5262 if (prot == VM_PROT_NONE) {
5263 pmap_remove(pmap, sva, eva);
5267 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5268 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5271 PG_G = pmap_global_bit(pmap);
5272 PG_M = pmap_modified_bit(pmap);
5273 PG_V = pmap_valid_bit(pmap);
5274 PG_RW = pmap_rw_bit(pmap);
5278 * Although this function delays and batches the invalidation
5279 * of stale TLB entries, it does not need to call
5280 * pmap_delayed_invl_start() and
5281 * pmap_delayed_invl_finish(), because it does not
5282 * ordinarily destroy mappings. Stale TLB entries from
5283 * protection-only changes need only be invalidated before the
5284 * pmap lock is released, because protection-only changes do
5285 * not destroy PV entries. Even operations that iterate over
5286 * a physical page's PV list of mappings, like
5287 * pmap_remove_write(), acquire the pmap lock for each
5288 * mapping. Consequently, for protection-only changes, the
5289 * pmap lock suffices to synchronize both page table and TLB
5292 * This function only destroys a mapping if pmap_demote_pde()
5293 * fails. In that case, stale TLB entries are immediately
5298 for (; sva < eva; sva = va_next) {
5300 pml4e = pmap_pml4e(pmap, sva);
5301 if ((*pml4e & PG_V) == 0) {
5302 va_next = (sva + NBPML4) & ~PML4MASK;
5308 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5309 if ((*pdpe & PG_V) == 0) {
5310 va_next = (sva + NBPDP) & ~PDPMASK;
5316 va_next = (sva + NBPDR) & ~PDRMASK;
5320 pde = pmap_pdpe_to_pde(pdpe, sva);
5324 * Weed out invalid mappings.
5330 * Check for large page.
5332 if ((ptpaddr & PG_PS) != 0) {
5334 * Are we protecting the entire large page? If not,
5335 * demote the mapping and fall through.
5337 if (sva + NBPDR == va_next && eva >= va_next) {
5339 * The TLB entry for a PG_G mapping is
5340 * invalidated by pmap_protect_pde().
5342 if (pmap_protect_pde(pmap, pde, sva, prot))
5345 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5347 * The large page mapping was destroyed.
5356 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5358 pt_entry_t obits, pbits;
5362 obits = pbits = *pte;
5363 if ((pbits & PG_V) == 0)
5366 if ((prot & VM_PROT_WRITE) == 0) {
5367 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5368 (PG_MANAGED | PG_M | PG_RW)) {
5369 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5372 pbits &= ~(PG_RW | PG_M);
5374 if ((prot & VM_PROT_EXECUTE) == 0)
5377 if (pbits != obits) {
5378 if (!atomic_cmpset_long(pte, obits, pbits))
5381 pmap_invalidate_page(pmap, sva);
5388 pmap_invalidate_all(pmap);
5392 #if VM_NRESERVLEVEL > 0
5394 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5395 * single page table page (PTP) to a single 2MB page mapping. For promotion
5396 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5397 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5398 * identical characteristics.
5401 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5402 struct rwlock **lockp)
5405 pt_entry_t *firstpte, oldpte, pa, *pte;
5406 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5410 PG_A = pmap_accessed_bit(pmap);
5411 PG_G = pmap_global_bit(pmap);
5412 PG_M = pmap_modified_bit(pmap);
5413 PG_V = pmap_valid_bit(pmap);
5414 PG_RW = pmap_rw_bit(pmap);
5415 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5416 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5418 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5421 * Examine the first PTE in the specified PTP. Abort if this PTE is
5422 * either invalid, unused, or does not map the first 4KB physical page
5423 * within a 2MB page.
5425 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5428 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
5429 atomic_add_long(&pmap_pde_p_failures, 1);
5430 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5431 " in pmap %p", va, pmap);
5434 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5436 * When PG_M is already clear, PG_RW can be cleared without
5437 * a TLB invalidation.
5439 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5445 * Examine each of the other PTEs in the specified PTP. Abort if this
5446 * PTE maps an unexpected 4KB physical page or does not have identical
5447 * characteristics to the first PTE.
5449 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5450 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5453 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5454 atomic_add_long(&pmap_pde_p_failures, 1);
5455 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5456 " in pmap %p", va, pmap);
5459 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5461 * When PG_M is already clear, PG_RW can be cleared
5462 * without a TLB invalidation.
5464 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5467 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5468 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5469 (va & ~PDRMASK), pmap);
5471 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5472 atomic_add_long(&pmap_pde_p_failures, 1);
5473 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5474 " in pmap %p", va, pmap);
5481 * Save the page table page in its current state until the PDE
5482 * mapping the superpage is demoted by pmap_demote_pde() or
5483 * destroyed by pmap_remove_pde().
5485 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5486 KASSERT(mpte >= vm_page_array &&
5487 mpte < &vm_page_array[vm_page_array_size],
5488 ("pmap_promote_pde: page table page is out of range"));
5489 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5490 ("pmap_promote_pde: page table page's pindex is wrong"));
5491 if (pmap_insert_pt_page(pmap, mpte, true)) {
5492 atomic_add_long(&pmap_pde_p_failures, 1);
5494 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5500 * Promote the pv entries.
5502 if ((newpde & PG_MANAGED) != 0)
5503 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5506 * Propagate the PAT index to its proper position.
5508 newpde = pmap_swap_pat(pmap, newpde);
5511 * Map the superpage.
5513 if (workaround_erratum383)
5514 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5516 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5518 atomic_add_long(&pmap_pde_promotions, 1);
5519 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5520 " in pmap %p", va, pmap);
5522 #endif /* VM_NRESERVLEVEL > 0 */
5525 * Insert the given physical page (p) at
5526 * the specified virtual address (v) in the
5527 * target physical map with the protection requested.
5529 * If specified, the page will be wired down, meaning
5530 * that the related pte can not be reclaimed.
5532 * NB: This is the only routine which MAY NOT lazy-evaluate
5533 * or lose information. That is, this routine must actually
5534 * insert this page into the given map NOW.
5536 * When destroying both a page table and PV entry, this function
5537 * performs the TLB invalidation before releasing the PV list
5538 * lock, so we do not need pmap_delayed_invl_page() calls here.
5541 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5542 u_int flags, int8_t psind)
5544 struct rwlock *lock;
5546 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5547 pt_entry_t newpte, origpte;
5554 PG_A = pmap_accessed_bit(pmap);
5555 PG_G = pmap_global_bit(pmap);
5556 PG_M = pmap_modified_bit(pmap);
5557 PG_V = pmap_valid_bit(pmap);
5558 PG_RW = pmap_rw_bit(pmap);
5560 va = trunc_page(va);
5561 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5562 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5563 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5565 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5566 va >= kmi.clean_eva,
5567 ("pmap_enter: managed mapping within the clean submap"));
5568 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5569 VM_OBJECT_ASSERT_LOCKED(m->object);
5570 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5571 ("pmap_enter: flags %u has reserved bits set", flags));
5572 pa = VM_PAGE_TO_PHYS(m);
5573 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5574 if ((flags & VM_PROT_WRITE) != 0)
5576 if ((prot & VM_PROT_WRITE) != 0)
5578 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5579 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5580 if ((prot & VM_PROT_EXECUTE) == 0)
5582 if ((flags & PMAP_ENTER_WIRED) != 0)
5584 if (va < VM_MAXUSER_ADDRESS)
5586 if (pmap == kernel_pmap)
5588 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5591 * Set modified bit gratuitously for writeable mappings if
5592 * the page is unmanaged. We do not want to take a fault
5593 * to do the dirty bit accounting for these mappings.
5595 if ((m->oflags & VPO_UNMANAGED) != 0) {
5596 if ((newpte & PG_RW) != 0)
5599 newpte |= PG_MANAGED;
5604 /* Assert the required virtual and physical alignment. */
5605 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5606 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5607 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5613 * In the case that a page table page is not
5614 * resident, we are creating it here.
5617 pde = pmap_pde(pmap, va);
5618 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5619 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5620 pte = pmap_pde_to_pte(pde, va);
5621 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5622 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5625 } else if (va < VM_MAXUSER_ADDRESS) {
5627 * Here if the pte page isn't mapped, or if it has been
5630 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5631 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5632 nosleep ? NULL : &lock);
5633 if (mpte == NULL && nosleep) {
5634 rv = KERN_RESOURCE_SHORTAGE;
5639 panic("pmap_enter: invalid page directory va=%#lx", va);
5643 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5644 newpte |= pmap_pkru_get(pmap, va);
5647 * Is the specified virtual address already mapped?
5649 if ((origpte & PG_V) != 0) {
5651 * Wiring change, just update stats. We don't worry about
5652 * wiring PT pages as they remain resident as long as there
5653 * are valid mappings in them. Hence, if a user page is wired,
5654 * the PT page will be also.
5656 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5657 pmap->pm_stats.wired_count++;
5658 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5659 pmap->pm_stats.wired_count--;
5662 * Remove the extra PT page reference.
5666 KASSERT(mpte->wire_count > 0,
5667 ("pmap_enter: missing reference to page table page,"
5672 * Has the physical page changed?
5674 opa = origpte & PG_FRAME;
5677 * No, might be a protection or wiring change.
5679 if ((origpte & PG_MANAGED) != 0 &&
5680 (newpte & PG_RW) != 0)
5681 vm_page_aflag_set(m, PGA_WRITEABLE);
5682 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5688 * The physical page has changed. Temporarily invalidate
5689 * the mapping. This ensures that all threads sharing the
5690 * pmap keep a consistent view of the mapping, which is
5691 * necessary for the correct handling of COW faults. It
5692 * also permits reuse of the old mapping's PV entry,
5693 * avoiding an allocation.
5695 * For consistency, handle unmanaged mappings the same way.
5697 origpte = pte_load_clear(pte);
5698 KASSERT((origpte & PG_FRAME) == opa,
5699 ("pmap_enter: unexpected pa update for %#lx", va));
5700 if ((origpte & PG_MANAGED) != 0) {
5701 om = PHYS_TO_VM_PAGE(opa);
5704 * The pmap lock is sufficient to synchronize with
5705 * concurrent calls to pmap_page_test_mappings() and
5706 * pmap_ts_referenced().
5708 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5710 if ((origpte & PG_A) != 0)
5711 vm_page_aflag_set(om, PGA_REFERENCED);
5712 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5713 pv = pmap_pvh_remove(&om->md, pmap, va);
5715 ("pmap_enter: no PV entry for %#lx", va));
5716 if ((newpte & PG_MANAGED) == 0)
5717 free_pv_entry(pmap, pv);
5718 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5719 TAILQ_EMPTY(&om->md.pv_list) &&
5720 ((om->flags & PG_FICTITIOUS) != 0 ||
5721 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5722 vm_page_aflag_clear(om, PGA_WRITEABLE);
5724 if ((origpte & PG_A) != 0)
5725 pmap_invalidate_page(pmap, va);
5729 * Increment the counters.
5731 if ((newpte & PG_W) != 0)
5732 pmap->pm_stats.wired_count++;
5733 pmap_resident_count_inc(pmap, 1);
5737 * Enter on the PV list if part of our managed memory.
5739 if ((newpte & PG_MANAGED) != 0) {
5741 pv = get_pv_entry(pmap, &lock);
5744 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5745 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5747 if ((newpte & PG_RW) != 0)
5748 vm_page_aflag_set(m, PGA_WRITEABLE);
5754 if ((origpte & PG_V) != 0) {
5756 origpte = pte_load_store(pte, newpte);
5757 KASSERT((origpte & PG_FRAME) == pa,
5758 ("pmap_enter: unexpected pa update for %#lx", va));
5759 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5761 if ((origpte & PG_MANAGED) != 0)
5765 * Although the PTE may still have PG_RW set, TLB
5766 * invalidation may nonetheless be required because
5767 * the PTE no longer has PG_M set.
5769 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5771 * This PTE change does not require TLB invalidation.
5775 if ((origpte & PG_A) != 0)
5776 pmap_invalidate_page(pmap, va);
5778 pte_store(pte, newpte);
5782 #if VM_NRESERVLEVEL > 0
5784 * If both the page table page and the reservation are fully
5785 * populated, then attempt promotion.
5787 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5788 pmap_ps_enabled(pmap) &&
5789 (m->flags & PG_FICTITIOUS) == 0 &&
5790 vm_reserv_level_iffullpop(m) == 0)
5791 pmap_promote_pde(pmap, pde, va, &lock);
5803 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5804 * if successful. Returns false if (1) a page table page cannot be allocated
5805 * without sleeping, (2) a mapping already exists at the specified virtual
5806 * address, or (3) a PV entry cannot be allocated without reclaiming another
5810 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5811 struct rwlock **lockp)
5816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5817 PG_V = pmap_valid_bit(pmap);
5818 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5820 if ((m->oflags & VPO_UNMANAGED) == 0)
5821 newpde |= PG_MANAGED;
5822 if ((prot & VM_PROT_EXECUTE) == 0)
5824 if (va < VM_MAXUSER_ADDRESS)
5826 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5827 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5832 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5833 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5834 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5835 * a mapping already exists at the specified virtual address. Returns
5836 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5837 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5838 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5840 * The parameter "m" is only used when creating a managed, writeable mapping.
5843 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5844 vm_page_t m, struct rwlock **lockp)
5846 struct spglist free;
5847 pd_entry_t oldpde, *pde;
5848 pt_entry_t PG_G, PG_RW, PG_V;
5851 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
5852 ("pmap_enter_pde: cannot create wired user mapping"));
5853 PG_G = pmap_global_bit(pmap);
5854 PG_RW = pmap_rw_bit(pmap);
5855 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5856 ("pmap_enter_pde: newpde is missing PG_M"));
5857 PG_V = pmap_valid_bit(pmap);
5858 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5860 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5861 NULL : lockp)) == NULL) {
5862 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5863 " in pmap %p", va, pmap);
5864 return (KERN_RESOURCE_SHORTAGE);
5868 * If pkru is not same for the whole pde range, return failure
5869 * and let vm_fault() cope. Check after pde allocation, since
5872 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5874 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5875 pmap_invalidate_page(pmap, va);
5876 vm_page_free_pages_toq(&free, true);
5878 return (KERN_FAILURE);
5880 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5881 newpde &= ~X86_PG_PKU_MASK;
5882 newpde |= pmap_pkru_get(pmap, va);
5885 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5886 pde = &pde[pmap_pde_index(va)];
5888 if ((oldpde & PG_V) != 0) {
5889 KASSERT(pdpg->wire_count > 1,
5890 ("pmap_enter_pde: pdpg's wire count is too low"));
5891 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5893 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5894 " in pmap %p", va, pmap);
5895 return (KERN_FAILURE);
5897 /* Break the existing mapping(s). */
5899 if ((oldpde & PG_PS) != 0) {
5901 * The reference to the PD page that was acquired by
5902 * pmap_allocpde() ensures that it won't be freed.
5903 * However, if the PDE resulted from a promotion, then
5904 * a reserved PT page could be freed.
5906 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5907 if ((oldpde & PG_G) == 0)
5908 pmap_invalidate_pde_page(pmap, va, oldpde);
5910 pmap_delayed_invl_start();
5911 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5913 pmap_invalidate_all(pmap);
5914 pmap_delayed_invl_finish();
5916 vm_page_free_pages_toq(&free, true);
5917 if (va >= VM_MAXUSER_ADDRESS) {
5919 * Both pmap_remove_pde() and pmap_remove_ptes() will
5920 * leave the kernel page table page zero filled.
5922 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5923 if (pmap_insert_pt_page(pmap, mt, false))
5924 panic("pmap_enter_pde: trie insert failed");
5926 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5929 if ((newpde & PG_MANAGED) != 0) {
5931 * Abort this mapping if its PV entry could not be created.
5933 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5935 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5937 * Although "va" is not mapped, paging-
5938 * structure caches could nonetheless have
5939 * entries that refer to the freed page table
5940 * pages. Invalidate those entries.
5942 pmap_invalidate_page(pmap, va);
5943 vm_page_free_pages_toq(&free, true);
5945 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5946 " in pmap %p", va, pmap);
5947 return (KERN_RESOURCE_SHORTAGE);
5949 if ((newpde & PG_RW) != 0) {
5950 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5951 vm_page_aflag_set(mt, PGA_WRITEABLE);
5956 * Increment counters.
5958 if ((newpde & PG_W) != 0)
5959 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5960 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5963 * Map the superpage. (This is not a promoted mapping; there will not
5964 * be any lingering 4KB page mappings in the TLB.)
5966 pde_store(pde, newpde);
5968 atomic_add_long(&pmap_pde_mappings, 1);
5969 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5970 " in pmap %p", va, pmap);
5971 return (KERN_SUCCESS);
5975 * Maps a sequence of resident pages belonging to the same object.
5976 * The sequence begins with the given page m_start. This page is
5977 * mapped at the given virtual address start. Each subsequent page is
5978 * mapped at a virtual address that is offset from start by the same
5979 * amount as the page is offset from m_start within the object. The
5980 * last page in the sequence is the page with the largest offset from
5981 * m_start that can be mapped at a virtual address less than the given
5982 * virtual address end. Not every virtual page between start and end
5983 * is mapped; only those for which a resident page exists with the
5984 * corresponding offset from m_start are mapped.
5987 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5988 vm_page_t m_start, vm_prot_t prot)
5990 struct rwlock *lock;
5993 vm_pindex_t diff, psize;
5995 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5997 psize = atop(end - start);
6002 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6003 va = start + ptoa(diff);
6004 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6005 m->psind == 1 && pmap_ps_enabled(pmap) &&
6006 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6007 m = &m[NBPDR / PAGE_SIZE - 1];
6009 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6011 m = TAILQ_NEXT(m, listq);
6019 * this code makes some *MAJOR* assumptions:
6020 * 1. Current pmap & pmap exists.
6023 * 4. No page table pages.
6024 * but is *MUCH* faster than pmap_enter...
6028 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6030 struct rwlock *lock;
6034 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6041 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6042 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6044 struct spglist free;
6045 pt_entry_t newpte, *pte, PG_V;
6047 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6048 (m->oflags & VPO_UNMANAGED) != 0,
6049 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6050 PG_V = pmap_valid_bit(pmap);
6051 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6054 * In the case that a page table page is not
6055 * resident, we are creating it here.
6057 if (va < VM_MAXUSER_ADDRESS) {
6058 vm_pindex_t ptepindex;
6062 * Calculate pagetable page index
6064 ptepindex = pmap_pde_pindex(va);
6065 if (mpte && (mpte->pindex == ptepindex)) {
6069 * Get the page directory entry
6071 ptepa = pmap_pde(pmap, va);
6074 * If the page table page is mapped, we just increment
6075 * the hold count, and activate it. Otherwise, we
6076 * attempt to allocate a page table page. If this
6077 * attempt fails, we don't retry. Instead, we give up.
6079 if (ptepa && (*ptepa & PG_V) != 0) {
6082 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6086 * Pass NULL instead of the PV list lock
6087 * pointer, because we don't intend to sleep.
6089 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6094 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6095 pte = &pte[pmap_pte_index(va)];
6109 * Enter on the PV list if part of our managed memory.
6111 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6112 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6115 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6117 * Although "va" is not mapped, paging-
6118 * structure caches could nonetheless have
6119 * entries that refer to the freed page table
6120 * pages. Invalidate those entries.
6122 pmap_invalidate_page(pmap, va);
6123 vm_page_free_pages_toq(&free, true);
6131 * Increment counters
6133 pmap_resident_count_inc(pmap, 1);
6135 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6136 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6137 if ((m->oflags & VPO_UNMANAGED) == 0)
6138 newpte |= PG_MANAGED;
6139 if ((prot & VM_PROT_EXECUTE) == 0)
6141 if (va < VM_MAXUSER_ADDRESS)
6142 newpte |= PG_U | pmap_pkru_get(pmap, va);
6143 pte_store(pte, newpte);
6148 * Make a temporary mapping for a physical address. This is only intended
6149 * to be used for panic dumps.
6152 pmap_kenter_temporary(vm_paddr_t pa, int i)
6156 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6157 pmap_kenter(va, pa);
6159 return ((void *)crashdumpmap);
6163 * This code maps large physical mmap regions into the
6164 * processor address space. Note that some shortcuts
6165 * are taken, but the code works.
6168 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6169 vm_pindex_t pindex, vm_size_t size)
6172 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6173 vm_paddr_t pa, ptepa;
6177 PG_A = pmap_accessed_bit(pmap);
6178 PG_M = pmap_modified_bit(pmap);
6179 PG_V = pmap_valid_bit(pmap);
6180 PG_RW = pmap_rw_bit(pmap);
6182 VM_OBJECT_ASSERT_WLOCKED(object);
6183 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6184 ("pmap_object_init_pt: non-device object"));
6185 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6186 if (!pmap_ps_enabled(pmap))
6188 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6190 p = vm_page_lookup(object, pindex);
6191 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6192 ("pmap_object_init_pt: invalid page %p", p));
6193 pat_mode = p->md.pat_mode;
6196 * Abort the mapping if the first page is not physically
6197 * aligned to a 2MB page boundary.
6199 ptepa = VM_PAGE_TO_PHYS(p);
6200 if (ptepa & (NBPDR - 1))
6204 * Skip the first page. Abort the mapping if the rest of
6205 * the pages are not physically contiguous or have differing
6206 * memory attributes.
6208 p = TAILQ_NEXT(p, listq);
6209 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6211 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6212 ("pmap_object_init_pt: invalid page %p", p));
6213 if (pa != VM_PAGE_TO_PHYS(p) ||
6214 pat_mode != p->md.pat_mode)
6216 p = TAILQ_NEXT(p, listq);
6220 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6221 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6222 * will not affect the termination of this loop.
6225 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6226 pa < ptepa + size; pa += NBPDR) {
6227 pdpg = pmap_allocpde(pmap, addr, NULL);
6230 * The creation of mappings below is only an
6231 * optimization. If a page directory page
6232 * cannot be allocated without blocking,
6233 * continue on to the next mapping rather than
6239 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6240 pde = &pde[pmap_pde_index(addr)];
6241 if ((*pde & PG_V) == 0) {
6242 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6243 PG_U | PG_RW | PG_V);
6244 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6245 atomic_add_long(&pmap_pde_mappings, 1);
6247 /* Continue on if the PDE is already valid. */
6249 KASSERT(pdpg->wire_count > 0,
6250 ("pmap_object_init_pt: missing reference "
6251 "to page directory page, va: 0x%lx", addr));
6260 * Clear the wired attribute from the mappings for the specified range of
6261 * addresses in the given pmap. Every valid mapping within that range
6262 * must have the wired attribute set. In contrast, invalid mappings
6263 * cannot have the wired attribute set, so they are ignored.
6265 * The wired attribute of the page table entry is not a hardware
6266 * feature, so there is no need to invalidate any TLB entries.
6267 * Since pmap_demote_pde() for the wired entry must never fail,
6268 * pmap_delayed_invl_start()/finish() calls around the
6269 * function are not needed.
6272 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6274 vm_offset_t va_next;
6275 pml4_entry_t *pml4e;
6278 pt_entry_t *pte, PG_V;
6280 PG_V = pmap_valid_bit(pmap);
6282 for (; sva < eva; sva = va_next) {
6283 pml4e = pmap_pml4e(pmap, sva);
6284 if ((*pml4e & PG_V) == 0) {
6285 va_next = (sva + NBPML4) & ~PML4MASK;
6290 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6291 if ((*pdpe & PG_V) == 0) {
6292 va_next = (sva + NBPDP) & ~PDPMASK;
6297 va_next = (sva + NBPDR) & ~PDRMASK;
6300 pde = pmap_pdpe_to_pde(pdpe, sva);
6301 if ((*pde & PG_V) == 0)
6303 if ((*pde & PG_PS) != 0) {
6304 if ((*pde & PG_W) == 0)
6305 panic("pmap_unwire: pde %#jx is missing PG_W",
6309 * Are we unwiring the entire large page? If not,
6310 * demote the mapping and fall through.
6312 if (sva + NBPDR == va_next && eva >= va_next) {
6313 atomic_clear_long(pde, PG_W);
6314 pmap->pm_stats.wired_count -= NBPDR /
6317 } else if (!pmap_demote_pde(pmap, pde, sva))
6318 panic("pmap_unwire: demotion failed");
6322 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6324 if ((*pte & PG_V) == 0)
6326 if ((*pte & PG_W) == 0)
6327 panic("pmap_unwire: pte %#jx is missing PG_W",
6331 * PG_W must be cleared atomically. Although the pmap
6332 * lock synchronizes access to PG_W, another processor
6333 * could be setting PG_M and/or PG_A concurrently.
6335 atomic_clear_long(pte, PG_W);
6336 pmap->pm_stats.wired_count--;
6343 * Copy the range specified by src_addr/len
6344 * from the source map to the range dst_addr/len
6345 * in the destination map.
6347 * This routine is only advisory and need not do anything.
6351 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6352 vm_offset_t src_addr)
6354 struct rwlock *lock;
6355 struct spglist free;
6357 vm_offset_t end_addr = src_addr + len;
6358 vm_offset_t va_next;
6359 vm_page_t dst_pdpg, dstmpte, srcmpte;
6360 pt_entry_t PG_A, PG_M, PG_V;
6362 if (dst_addr != src_addr)
6365 if (dst_pmap->pm_type != src_pmap->pm_type)
6369 * EPT page table entries that require emulation of A/D bits are
6370 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6371 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6372 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6373 * implementations flag an EPT misconfiguration for exec-only
6374 * mappings we skip this function entirely for emulated pmaps.
6376 if (pmap_emulate_ad_bits(dst_pmap))
6380 if (dst_pmap < src_pmap) {
6381 PMAP_LOCK(dst_pmap);
6382 PMAP_LOCK(src_pmap);
6384 PMAP_LOCK(src_pmap);
6385 PMAP_LOCK(dst_pmap);
6388 PG_A = pmap_accessed_bit(dst_pmap);
6389 PG_M = pmap_modified_bit(dst_pmap);
6390 PG_V = pmap_valid_bit(dst_pmap);
6392 for (addr = src_addr; addr < end_addr; addr = va_next) {
6393 pt_entry_t *src_pte, *dst_pte;
6394 pml4_entry_t *pml4e;
6396 pd_entry_t srcptepaddr, *pde;
6398 KASSERT(addr < UPT_MIN_ADDRESS,
6399 ("pmap_copy: invalid to pmap_copy page tables"));
6401 pml4e = pmap_pml4e(src_pmap, addr);
6402 if ((*pml4e & PG_V) == 0) {
6403 va_next = (addr + NBPML4) & ~PML4MASK;
6409 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6410 if ((*pdpe & PG_V) == 0) {
6411 va_next = (addr + NBPDP) & ~PDPMASK;
6417 va_next = (addr + NBPDR) & ~PDRMASK;
6421 pde = pmap_pdpe_to_pde(pdpe, addr);
6423 if (srcptepaddr == 0)
6426 if (srcptepaddr & PG_PS) {
6427 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6429 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6430 if (dst_pdpg == NULL)
6432 pde = (pd_entry_t *)
6433 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6434 pde = &pde[pmap_pde_index(addr)];
6435 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6436 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6437 PMAP_ENTER_NORECLAIM, &lock))) {
6438 *pde = srcptepaddr & ~PG_W;
6439 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
6440 atomic_add_long(&pmap_pde_mappings, 1);
6442 dst_pdpg->wire_count--;
6446 srcptepaddr &= PG_FRAME;
6447 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6448 KASSERT(srcmpte->wire_count > 0,
6449 ("pmap_copy: source page table page is unused"));
6451 if (va_next > end_addr)
6454 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6455 src_pte = &src_pte[pmap_pte_index(addr)];
6457 while (addr < va_next) {
6461 * we only virtual copy managed pages
6463 if ((ptetemp & PG_MANAGED) != 0) {
6464 if (dstmpte != NULL &&
6465 dstmpte->pindex == pmap_pde_pindex(addr))
6466 dstmpte->wire_count++;
6467 else if ((dstmpte = pmap_allocpte(dst_pmap,
6468 addr, NULL)) == NULL)
6470 dst_pte = (pt_entry_t *)
6471 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6472 dst_pte = &dst_pte[pmap_pte_index(addr)];
6473 if (*dst_pte == 0 &&
6474 pmap_try_insert_pv_entry(dst_pmap, addr,
6475 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
6478 * Clear the wired, modified, and
6479 * accessed (referenced) bits
6482 *dst_pte = ptetemp & ~(PG_W | PG_M |
6484 pmap_resident_count_inc(dst_pmap, 1);
6487 if (pmap_unwire_ptp(dst_pmap, addr,
6490 * Although "addr" is not
6491 * mapped, paging-structure
6492 * caches could nonetheless
6493 * have entries that refer to
6494 * the freed page table pages.
6495 * Invalidate those entries.
6497 pmap_invalidate_page(dst_pmap,
6499 vm_page_free_pages_toq(&free,
6504 if (dstmpte->wire_count >= srcmpte->wire_count)
6514 PMAP_UNLOCK(src_pmap);
6515 PMAP_UNLOCK(dst_pmap);
6519 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6523 if (dst_pmap->pm_type != src_pmap->pm_type ||
6524 dst_pmap->pm_type != PT_X86 ||
6525 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6528 if (dst_pmap < src_pmap) {
6529 PMAP_LOCK(dst_pmap);
6530 PMAP_LOCK(src_pmap);
6532 PMAP_LOCK(src_pmap);
6533 PMAP_LOCK(dst_pmap);
6535 error = pmap_pkru_copy(dst_pmap, src_pmap);
6536 /* Clean up partial copy on failure due to no memory. */
6537 if (error == ENOMEM)
6538 pmap_pkru_deassign_all(dst_pmap);
6539 PMAP_UNLOCK(src_pmap);
6540 PMAP_UNLOCK(dst_pmap);
6541 if (error != ENOMEM)
6549 * Zero the specified hardware page.
6552 pmap_zero_page(vm_page_t m)
6554 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6556 pagezero((void *)va);
6560 * Zero an an area within a single hardware page. off and size must not
6561 * cover an area beyond a single hardware page.
6564 pmap_zero_page_area(vm_page_t m, int off, int size)
6566 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6568 if (off == 0 && size == PAGE_SIZE)
6569 pagezero((void *)va);
6571 bzero((char *)va + off, size);
6575 * Copy 1 specified hardware page to another.
6578 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6580 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6581 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6583 pagecopy((void *)src, (void *)dst);
6586 int unmapped_buf_allowed = 1;
6589 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6590 vm_offset_t b_offset, int xfersize)
6594 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6598 while (xfersize > 0) {
6599 a_pg_offset = a_offset & PAGE_MASK;
6600 pages[0] = ma[a_offset >> PAGE_SHIFT];
6601 b_pg_offset = b_offset & PAGE_MASK;
6602 pages[1] = mb[b_offset >> PAGE_SHIFT];
6603 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6604 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6605 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6606 a_cp = (char *)vaddr[0] + a_pg_offset;
6607 b_cp = (char *)vaddr[1] + b_pg_offset;
6608 bcopy(a_cp, b_cp, cnt);
6609 if (__predict_false(mapped))
6610 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6618 * Returns true if the pmap's pv is one of the first
6619 * 16 pvs linked to from this page. This count may
6620 * be changed upwards or downwards in the future; it
6621 * is only necessary that true be returned for a small
6622 * subset of pmaps for proper page aging.
6625 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6627 struct md_page *pvh;
6628 struct rwlock *lock;
6633 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6634 ("pmap_page_exists_quick: page %p is not managed", m));
6636 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6638 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6639 if (PV_PMAP(pv) == pmap) {
6647 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6648 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6649 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6650 if (PV_PMAP(pv) == pmap) {
6664 * pmap_page_wired_mappings:
6666 * Return the number of managed mappings to the given physical page
6670 pmap_page_wired_mappings(vm_page_t m)
6672 struct rwlock *lock;
6673 struct md_page *pvh;
6677 int count, md_gen, pvh_gen;
6679 if ((m->oflags & VPO_UNMANAGED) != 0)
6681 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6685 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6687 if (!PMAP_TRYLOCK(pmap)) {
6688 md_gen = m->md.pv_gen;
6692 if (md_gen != m->md.pv_gen) {
6697 pte = pmap_pte(pmap, pv->pv_va);
6698 if ((*pte & PG_W) != 0)
6702 if ((m->flags & PG_FICTITIOUS) == 0) {
6703 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6704 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6706 if (!PMAP_TRYLOCK(pmap)) {
6707 md_gen = m->md.pv_gen;
6708 pvh_gen = pvh->pv_gen;
6712 if (md_gen != m->md.pv_gen ||
6713 pvh_gen != pvh->pv_gen) {
6718 pte = pmap_pde(pmap, pv->pv_va);
6719 if ((*pte & PG_W) != 0)
6729 * Returns TRUE if the given page is mapped individually or as part of
6730 * a 2mpage. Otherwise, returns FALSE.
6733 pmap_page_is_mapped(vm_page_t m)
6735 struct rwlock *lock;
6738 if ((m->oflags & VPO_UNMANAGED) != 0)
6740 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6742 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6743 ((m->flags & PG_FICTITIOUS) == 0 &&
6744 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6750 * Destroy all managed, non-wired mappings in the given user-space
6751 * pmap. This pmap cannot be active on any processor besides the
6754 * This function cannot be applied to the kernel pmap. Moreover, it
6755 * is not intended for general use. It is only to be used during
6756 * process termination. Consequently, it can be implemented in ways
6757 * that make it faster than pmap_remove(). First, it can more quickly
6758 * destroy mappings by iterating over the pmap's collection of PV
6759 * entries, rather than searching the page table. Second, it doesn't
6760 * have to test and clear the page table entries atomically, because
6761 * no processor is currently accessing the user address space. In
6762 * particular, a page table entry's dirty bit won't change state once
6763 * this function starts.
6765 * Although this function destroys all of the pmap's managed,
6766 * non-wired mappings, it can delay and batch the invalidation of TLB
6767 * entries without calling pmap_delayed_invl_start() and
6768 * pmap_delayed_invl_finish(). Because the pmap is not active on
6769 * any other processor, none of these TLB entries will ever be used
6770 * before their eventual invalidation. Consequently, there is no need
6771 * for either pmap_remove_all() or pmap_remove_write() to wait for
6772 * that eventual TLB invalidation.
6775 pmap_remove_pages(pmap_t pmap)
6778 pt_entry_t *pte, tpte;
6779 pt_entry_t PG_M, PG_RW, PG_V;
6780 struct spglist free;
6781 vm_page_t m, mpte, mt;
6783 struct md_page *pvh;
6784 struct pv_chunk *pc, *npc;
6785 struct rwlock *lock;
6787 uint64_t inuse, bitmask;
6788 int allfree, field, freed, idx;
6789 boolean_t superpage;
6793 * Assert that the given pmap is only active on the current
6794 * CPU. Unfortunately, we cannot block another CPU from
6795 * activating the pmap while this function is executing.
6797 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6800 cpuset_t other_cpus;
6802 other_cpus = all_cpus;
6804 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6805 CPU_AND(&other_cpus, &pmap->pm_active);
6807 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6812 PG_M = pmap_modified_bit(pmap);
6813 PG_V = pmap_valid_bit(pmap);
6814 PG_RW = pmap_rw_bit(pmap);
6818 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6821 for (field = 0; field < _NPCM; field++) {
6822 inuse = ~pc->pc_map[field] & pc_freemask[field];
6823 while (inuse != 0) {
6825 bitmask = 1UL << bit;
6826 idx = field * 64 + bit;
6827 pv = &pc->pc_pventry[idx];
6830 pte = pmap_pdpe(pmap, pv->pv_va);
6832 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6834 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6837 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6839 pte = &pte[pmap_pte_index(pv->pv_va)];
6843 * Keep track whether 'tpte' is a
6844 * superpage explicitly instead of
6845 * relying on PG_PS being set.
6847 * This is because PG_PS is numerically
6848 * identical to PG_PTE_PAT and thus a
6849 * regular page could be mistaken for
6855 if ((tpte & PG_V) == 0) {
6856 panic("bad pte va %lx pte %lx",
6861 * We cannot remove wired pages from a process' mapping at this time
6869 pa = tpte & PG_PS_FRAME;
6871 pa = tpte & PG_FRAME;
6873 m = PHYS_TO_VM_PAGE(pa);
6874 KASSERT(m->phys_addr == pa,
6875 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6876 m, (uintmax_t)m->phys_addr,
6879 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6880 m < &vm_page_array[vm_page_array_size],
6881 ("pmap_remove_pages: bad tpte %#jx",
6887 * Update the vm_page_t clean/reference bits.
6889 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6891 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6897 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6900 pc->pc_map[field] |= bitmask;
6902 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6903 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6904 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6906 if (TAILQ_EMPTY(&pvh->pv_list)) {
6907 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6908 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6909 TAILQ_EMPTY(&mt->md.pv_list))
6910 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6912 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6914 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6915 ("pmap_remove_pages: pte page not promoted"));
6916 pmap_resident_count_dec(pmap, 1);
6917 KASSERT(mpte->wire_count == NPTEPG,
6918 ("pmap_remove_pages: pte page wire count error"));
6919 mpte->wire_count = 0;
6920 pmap_add_delayed_free_list(mpte, &free, FALSE);
6923 pmap_resident_count_dec(pmap, 1);
6924 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6926 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6927 TAILQ_EMPTY(&m->md.pv_list) &&
6928 (m->flags & PG_FICTITIOUS) == 0) {
6929 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6930 if (TAILQ_EMPTY(&pvh->pv_list))
6931 vm_page_aflag_clear(m, PGA_WRITEABLE);
6934 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6938 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6939 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6940 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6942 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6948 pmap_invalidate_all(pmap);
6949 pmap_pkru_deassign_all(pmap);
6951 vm_page_free_pages_toq(&free, true);
6955 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6957 struct rwlock *lock;
6959 struct md_page *pvh;
6960 pt_entry_t *pte, mask;
6961 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6963 int md_gen, pvh_gen;
6967 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6970 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6972 if (!PMAP_TRYLOCK(pmap)) {
6973 md_gen = m->md.pv_gen;
6977 if (md_gen != m->md.pv_gen) {
6982 pte = pmap_pte(pmap, pv->pv_va);
6985 PG_M = pmap_modified_bit(pmap);
6986 PG_RW = pmap_rw_bit(pmap);
6987 mask |= PG_RW | PG_M;
6990 PG_A = pmap_accessed_bit(pmap);
6991 PG_V = pmap_valid_bit(pmap);
6992 mask |= PG_V | PG_A;
6994 rv = (*pte & mask) == mask;
6999 if ((m->flags & PG_FICTITIOUS) == 0) {
7000 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7001 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7003 if (!PMAP_TRYLOCK(pmap)) {
7004 md_gen = m->md.pv_gen;
7005 pvh_gen = pvh->pv_gen;
7009 if (md_gen != m->md.pv_gen ||
7010 pvh_gen != pvh->pv_gen) {
7015 pte = pmap_pde(pmap, pv->pv_va);
7018 PG_M = pmap_modified_bit(pmap);
7019 PG_RW = pmap_rw_bit(pmap);
7020 mask |= PG_RW | PG_M;
7023 PG_A = pmap_accessed_bit(pmap);
7024 PG_V = pmap_valid_bit(pmap);
7025 mask |= PG_V | PG_A;
7027 rv = (*pte & mask) == mask;
7041 * Return whether or not the specified physical page was modified
7042 * in any physical maps.
7045 pmap_is_modified(vm_page_t m)
7048 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7049 ("pmap_is_modified: page %p is not managed", m));
7052 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7053 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
7054 * is clear, no PTEs can have PG_M set.
7056 VM_OBJECT_ASSERT_WLOCKED(m->object);
7057 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7059 return (pmap_page_test_mappings(m, FALSE, TRUE));
7063 * pmap_is_prefaultable:
7065 * Return whether or not the specified virtual address is eligible
7069 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7072 pt_entry_t *pte, PG_V;
7075 PG_V = pmap_valid_bit(pmap);
7078 pde = pmap_pde(pmap, addr);
7079 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7080 pte = pmap_pde_to_pte(pde, addr);
7081 rv = (*pte & PG_V) == 0;
7088 * pmap_is_referenced:
7090 * Return whether or not the specified physical page was referenced
7091 * in any physical maps.
7094 pmap_is_referenced(vm_page_t m)
7097 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7098 ("pmap_is_referenced: page %p is not managed", m));
7099 return (pmap_page_test_mappings(m, TRUE, FALSE));
7103 * Clear the write and modified bits in each of the given page's mappings.
7106 pmap_remove_write(vm_page_t m)
7108 struct md_page *pvh;
7110 struct rwlock *lock;
7111 pv_entry_t next_pv, pv;
7113 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7115 int pvh_gen, md_gen;
7117 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7118 ("pmap_remove_write: page %p is not managed", m));
7121 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7122 * set by another thread while the object is locked. Thus,
7123 * if PGA_WRITEABLE is clear, no page table entries need updating.
7125 VM_OBJECT_ASSERT_WLOCKED(m->object);
7126 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7128 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7129 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7130 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7133 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7135 if (!PMAP_TRYLOCK(pmap)) {
7136 pvh_gen = pvh->pv_gen;
7140 if (pvh_gen != pvh->pv_gen) {
7146 PG_RW = pmap_rw_bit(pmap);
7148 pde = pmap_pde(pmap, va);
7149 if ((*pde & PG_RW) != 0)
7150 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7151 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7152 ("inconsistent pv lock %p %p for page %p",
7153 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7156 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7158 if (!PMAP_TRYLOCK(pmap)) {
7159 pvh_gen = pvh->pv_gen;
7160 md_gen = m->md.pv_gen;
7164 if (pvh_gen != pvh->pv_gen ||
7165 md_gen != m->md.pv_gen) {
7171 PG_M = pmap_modified_bit(pmap);
7172 PG_RW = pmap_rw_bit(pmap);
7173 pde = pmap_pde(pmap, pv->pv_va);
7174 KASSERT((*pde & PG_PS) == 0,
7175 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7177 pte = pmap_pde_to_pte(pde, pv->pv_va);
7180 if (oldpte & PG_RW) {
7181 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7184 if ((oldpte & PG_M) != 0)
7186 pmap_invalidate_page(pmap, pv->pv_va);
7191 vm_page_aflag_clear(m, PGA_WRITEABLE);
7192 pmap_delayed_invl_wait(m);
7195 static __inline boolean_t
7196 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7199 if (!pmap_emulate_ad_bits(pmap))
7202 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7205 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7206 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7207 * if the EPT_PG_WRITE bit is set.
7209 if ((pte & EPT_PG_WRITE) != 0)
7213 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7215 if ((pte & EPT_PG_EXECUTE) == 0 ||
7216 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7223 * pmap_ts_referenced:
7225 * Return a count of reference bits for a page, clearing those bits.
7226 * It is not necessary for every reference bit to be cleared, but it
7227 * is necessary that 0 only be returned when there are truly no
7228 * reference bits set.
7230 * As an optimization, update the page's dirty field if a modified bit is
7231 * found while counting reference bits. This opportunistic update can be
7232 * performed at low cost and can eliminate the need for some future calls
7233 * to pmap_is_modified(). However, since this function stops after
7234 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7235 * dirty pages. Those dirty pages will only be detected by a future call
7236 * to pmap_is_modified().
7238 * A DI block is not needed within this function, because
7239 * invalidations are performed before the PV list lock is
7243 pmap_ts_referenced(vm_page_t m)
7245 struct md_page *pvh;
7248 struct rwlock *lock;
7249 pd_entry_t oldpde, *pde;
7250 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7253 int cleared, md_gen, not_cleared, pvh_gen;
7254 struct spglist free;
7257 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7258 ("pmap_ts_referenced: page %p is not managed", m));
7261 pa = VM_PAGE_TO_PHYS(m);
7262 lock = PHYS_TO_PV_LIST_LOCK(pa);
7263 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7267 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7268 goto small_mappings;
7274 if (!PMAP_TRYLOCK(pmap)) {
7275 pvh_gen = pvh->pv_gen;
7279 if (pvh_gen != pvh->pv_gen) {
7284 PG_A = pmap_accessed_bit(pmap);
7285 PG_M = pmap_modified_bit(pmap);
7286 PG_RW = pmap_rw_bit(pmap);
7288 pde = pmap_pde(pmap, pv->pv_va);
7290 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7292 * Although "oldpde" is mapping a 2MB page, because
7293 * this function is called at a 4KB page granularity,
7294 * we only update the 4KB page under test.
7298 if ((oldpde & PG_A) != 0) {
7300 * Since this reference bit is shared by 512 4KB
7301 * pages, it should not be cleared every time it is
7302 * tested. Apply a simple "hash" function on the
7303 * physical page number, the virtual superpage number,
7304 * and the pmap address to select one 4KB page out of
7305 * the 512 on which testing the reference bit will
7306 * result in clearing that reference bit. This
7307 * function is designed to avoid the selection of the
7308 * same 4KB page for every 2MB page mapping.
7310 * On demotion, a mapping that hasn't been referenced
7311 * is simply destroyed. To avoid the possibility of a
7312 * subsequent page fault on a demoted wired mapping,
7313 * always leave its reference bit set. Moreover,
7314 * since the superpage is wired, the current state of
7315 * its reference bit won't affect page replacement.
7317 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7318 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7319 (oldpde & PG_W) == 0) {
7320 if (safe_to_clear_referenced(pmap, oldpde)) {
7321 atomic_clear_long(pde, PG_A);
7322 pmap_invalidate_page(pmap, pv->pv_va);
7324 } else if (pmap_demote_pde_locked(pmap, pde,
7325 pv->pv_va, &lock)) {
7327 * Remove the mapping to a single page
7328 * so that a subsequent access may
7329 * repromote. Since the underlying
7330 * page table page is fully populated,
7331 * this removal never frees a page
7335 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7337 pte = pmap_pde_to_pte(pde, va);
7338 pmap_remove_pte(pmap, pte, va, *pde,
7340 pmap_invalidate_page(pmap, va);
7346 * The superpage mapping was removed
7347 * entirely and therefore 'pv' is no
7355 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7356 ("inconsistent pv lock %p %p for page %p",
7357 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7362 /* Rotate the PV list if it has more than one entry. */
7363 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7364 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7365 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7368 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7370 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7372 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7379 if (!PMAP_TRYLOCK(pmap)) {
7380 pvh_gen = pvh->pv_gen;
7381 md_gen = m->md.pv_gen;
7385 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7390 PG_A = pmap_accessed_bit(pmap);
7391 PG_M = pmap_modified_bit(pmap);
7392 PG_RW = pmap_rw_bit(pmap);
7393 pde = pmap_pde(pmap, pv->pv_va);
7394 KASSERT((*pde & PG_PS) == 0,
7395 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7397 pte = pmap_pde_to_pte(pde, pv->pv_va);
7398 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7400 if ((*pte & PG_A) != 0) {
7401 if (safe_to_clear_referenced(pmap, *pte)) {
7402 atomic_clear_long(pte, PG_A);
7403 pmap_invalidate_page(pmap, pv->pv_va);
7405 } else if ((*pte & PG_W) == 0) {
7407 * Wired pages cannot be paged out so
7408 * doing accessed bit emulation for
7409 * them is wasted effort. We do the
7410 * hard work for unwired pages only.
7412 pmap_remove_pte(pmap, pte, pv->pv_va,
7413 *pde, &free, &lock);
7414 pmap_invalidate_page(pmap, pv->pv_va);
7419 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7420 ("inconsistent pv lock %p %p for page %p",
7421 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7426 /* Rotate the PV list if it has more than one entry. */
7427 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7428 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7429 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7432 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7433 not_cleared < PMAP_TS_REFERENCED_MAX);
7436 vm_page_free_pages_toq(&free, true);
7437 return (cleared + not_cleared);
7441 * Apply the given advice to the specified range of addresses within the
7442 * given pmap. Depending on the advice, clear the referenced and/or
7443 * modified flags in each mapping and set the mapped page's dirty field.
7446 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7448 struct rwlock *lock;
7449 pml4_entry_t *pml4e;
7451 pd_entry_t oldpde, *pde;
7452 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7453 vm_offset_t va, va_next;
7455 boolean_t anychanged;
7457 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7461 * A/D bit emulation requires an alternate code path when clearing
7462 * the modified and accessed bits below. Since this function is
7463 * advisory in nature we skip it entirely for pmaps that require
7464 * A/D bit emulation.
7466 if (pmap_emulate_ad_bits(pmap))
7469 PG_A = pmap_accessed_bit(pmap);
7470 PG_G = pmap_global_bit(pmap);
7471 PG_M = pmap_modified_bit(pmap);
7472 PG_V = pmap_valid_bit(pmap);
7473 PG_RW = pmap_rw_bit(pmap);
7475 pmap_delayed_invl_start();
7477 for (; sva < eva; sva = va_next) {
7478 pml4e = pmap_pml4e(pmap, sva);
7479 if ((*pml4e & PG_V) == 0) {
7480 va_next = (sva + NBPML4) & ~PML4MASK;
7485 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7486 if ((*pdpe & PG_V) == 0) {
7487 va_next = (sva + NBPDP) & ~PDPMASK;
7492 va_next = (sva + NBPDR) & ~PDRMASK;
7495 pde = pmap_pdpe_to_pde(pdpe, sva);
7497 if ((oldpde & PG_V) == 0)
7499 else if ((oldpde & PG_PS) != 0) {
7500 if ((oldpde & PG_MANAGED) == 0)
7503 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7508 * The large page mapping was destroyed.
7514 * Unless the page mappings are wired, remove the
7515 * mapping to a single page so that a subsequent
7516 * access may repromote. Since the underlying page
7517 * table page is fully populated, this removal never
7518 * frees a page table page.
7520 if ((oldpde & PG_W) == 0) {
7521 pte = pmap_pde_to_pte(pde, sva);
7522 KASSERT((*pte & PG_V) != 0,
7523 ("pmap_advise: invalid PTE"));
7524 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
7534 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7536 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7538 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7539 if (advice == MADV_DONTNEED) {
7541 * Future calls to pmap_is_modified()
7542 * can be avoided by making the page
7545 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7548 atomic_clear_long(pte, PG_M | PG_A);
7549 } else if ((*pte & PG_A) != 0)
7550 atomic_clear_long(pte, PG_A);
7554 if ((*pte & PG_G) != 0) {
7561 if (va != va_next) {
7562 pmap_invalidate_range(pmap, va, sva);
7567 pmap_invalidate_range(pmap, va, sva);
7570 pmap_invalidate_all(pmap);
7572 pmap_delayed_invl_finish();
7576 * Clear the modify bits on the specified physical page.
7579 pmap_clear_modify(vm_page_t m)
7581 struct md_page *pvh;
7583 pv_entry_t next_pv, pv;
7584 pd_entry_t oldpde, *pde;
7585 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
7586 struct rwlock *lock;
7588 int md_gen, pvh_gen;
7590 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7591 ("pmap_clear_modify: page %p is not managed", m));
7592 VM_OBJECT_ASSERT_WLOCKED(m->object);
7593 KASSERT(!vm_page_xbusied(m),
7594 ("pmap_clear_modify: page %p is exclusive busied", m));
7597 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7598 * If the object containing the page is locked and the page is not
7599 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7601 if ((m->aflags & PGA_WRITEABLE) == 0)
7603 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7604 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7605 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7608 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7610 if (!PMAP_TRYLOCK(pmap)) {
7611 pvh_gen = pvh->pv_gen;
7615 if (pvh_gen != pvh->pv_gen) {
7620 PG_M = pmap_modified_bit(pmap);
7621 PG_V = pmap_valid_bit(pmap);
7622 PG_RW = pmap_rw_bit(pmap);
7624 pde = pmap_pde(pmap, va);
7626 if ((oldpde & PG_RW) != 0) {
7627 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
7628 if ((oldpde & PG_W) == 0) {
7630 * Write protect the mapping to a
7631 * single page so that a subsequent
7632 * write access may repromote.
7634 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7636 pte = pmap_pde_to_pte(pde, va);
7638 if ((oldpte & PG_V) != 0) {
7639 while (!atomic_cmpset_long(pte,
7641 oldpte & ~(PG_M | PG_RW)))
7644 pmap_invalidate_page(pmap, va);
7651 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7653 if (!PMAP_TRYLOCK(pmap)) {
7654 md_gen = m->md.pv_gen;
7655 pvh_gen = pvh->pv_gen;
7659 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7664 PG_M = pmap_modified_bit(pmap);
7665 PG_RW = pmap_rw_bit(pmap);
7666 pde = pmap_pde(pmap, pv->pv_va);
7667 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7668 " a 2mpage in page %p's pv list", m));
7669 pte = pmap_pde_to_pte(pde, pv->pv_va);
7670 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7671 atomic_clear_long(pte, PG_M);
7672 pmap_invalidate_page(pmap, pv->pv_va);
7680 * Miscellaneous support routines follow
7683 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7684 static __inline void
7685 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7690 * The cache mode bits are all in the low 32-bits of the
7691 * PTE, so we can just spin on updating the low 32-bits.
7694 opte = *(u_int *)pte;
7695 npte = opte & ~mask;
7697 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7700 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7701 static __inline void
7702 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7707 * The cache mode bits are all in the low 32-bits of the
7708 * PDE, so we can just spin on updating the low 32-bits.
7711 opde = *(u_int *)pde;
7712 npde = opde & ~mask;
7714 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7718 * Map a set of physical memory pages into the kernel virtual
7719 * address space. Return a pointer to where it is mapped. This
7720 * routine is intended to be used for mapping device memory,
7724 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, bool noflush)
7726 struct pmap_preinit_mapping *ppim;
7727 vm_offset_t va, offset;
7731 offset = pa & PAGE_MASK;
7732 size = round_page(offset + size);
7733 pa = trunc_page(pa);
7735 if (!pmap_initialized) {
7737 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7738 ppim = pmap_preinit_mapping + i;
7739 if (ppim->va == 0) {
7743 ppim->va = virtual_avail;
7744 virtual_avail += size;
7750 panic("%s: too many preinit mappings", __func__);
7753 * If we have a preinit mapping, re-use it.
7755 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7756 ppim = pmap_preinit_mapping + i;
7757 if (ppim->pa == pa && ppim->sz == size &&
7759 return ((void *)(ppim->va + offset));
7762 * If the specified range of physical addresses fits within
7763 * the direct map window, use the direct map.
7765 if (pa < dmaplimit && pa + size <= dmaplimit) {
7766 va = PHYS_TO_DMAP(pa);
7767 PMAP_LOCK(kernel_pmap);
7768 i = pmap_change_attr_locked(va, size, mode, noflush);
7769 PMAP_UNLOCK(kernel_pmap);
7771 return ((void *)(va + offset));
7773 va = kva_alloc(size);
7775 panic("%s: Couldn't allocate KVA", __func__);
7777 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7778 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7779 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7781 pmap_invalidate_cache_range(va, va + tmpsize);
7782 return ((void *)(va + offset));
7786 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7789 return (pmap_mapdev_internal(pa, size, mode, false));
7793 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7796 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, false));
7800 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7803 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE, true));
7807 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7810 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK, false));
7814 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7816 struct pmap_preinit_mapping *ppim;
7820 /* If we gave a direct map region in pmap_mapdev, do nothing */
7821 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7823 offset = va & PAGE_MASK;
7824 size = round_page(offset + size);
7825 va = trunc_page(va);
7826 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7827 ppim = pmap_preinit_mapping + i;
7828 if (ppim->va == va && ppim->sz == size) {
7829 if (pmap_initialized)
7835 if (va + size == virtual_avail)
7840 if (pmap_initialized)
7845 * Tries to demote a 1GB page mapping.
7848 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7850 pdp_entry_t newpdpe, oldpdpe;
7851 pd_entry_t *firstpde, newpde, *pde;
7852 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7856 PG_A = pmap_accessed_bit(pmap);
7857 PG_M = pmap_modified_bit(pmap);
7858 PG_V = pmap_valid_bit(pmap);
7859 PG_RW = pmap_rw_bit(pmap);
7861 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7863 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7864 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7865 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7866 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7867 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7868 " in pmap %p", va, pmap);
7871 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7872 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7873 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7874 KASSERT((oldpdpe & PG_A) != 0,
7875 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7876 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7877 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7881 * Initialize the page directory page.
7883 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7889 * Demote the mapping.
7894 * Invalidate a stale recursive mapping of the page directory page.
7896 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7898 pmap_pdpe_demotions++;
7899 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7900 " in pmap %p", va, pmap);
7905 * Sets the memory attribute for the specified page.
7908 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7911 m->md.pat_mode = ma;
7914 * If "m" is a normal page, update its direct mapping. This update
7915 * can be relied upon to perform any cache operations that are
7916 * required for data coherence.
7918 if ((m->flags & PG_FICTITIOUS) == 0 &&
7919 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7921 panic("memory attribute change on the direct map failed");
7925 * Changes the specified virtual address range's memory type to that given by
7926 * the parameter "mode". The specified virtual address range must be
7927 * completely contained within either the direct map or the kernel map. If
7928 * the virtual address range is contained within the kernel map, then the
7929 * memory type for each of the corresponding ranges of the direct map is also
7930 * changed. (The corresponding ranges of the direct map are those ranges that
7931 * map the same physical pages as the specified virtual address range.) These
7932 * changes to the direct map are necessary because Intel describes the
7933 * behavior of their processors as "undefined" if two or more mappings to the
7934 * same physical page have different memory types.
7936 * Returns zero if the change completed successfully, and either EINVAL or
7937 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7938 * of the virtual address range was not mapped, and ENOMEM is returned if
7939 * there was insufficient memory available to complete the change. In the
7940 * latter case, the memory type may have been changed on some part of the
7941 * virtual address range or the direct map.
7944 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7948 PMAP_LOCK(kernel_pmap);
7949 error = pmap_change_attr_locked(va, size, mode, false);
7950 PMAP_UNLOCK(kernel_pmap);
7955 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, bool noflush)
7957 vm_offset_t base, offset, tmpva;
7958 vm_paddr_t pa_start, pa_end, pa_end1;
7962 int cache_bits_pte, cache_bits_pde, error;
7965 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7966 base = trunc_page(va);
7967 offset = va & PAGE_MASK;
7968 size = round_page(offset + size);
7971 * Only supported on kernel virtual addresses, including the direct
7972 * map but excluding the recursive map.
7974 if (base < DMAP_MIN_ADDRESS)
7977 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7978 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7982 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7983 * into 4KB pages if required.
7985 for (tmpva = base; tmpva < base + size; ) {
7986 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7987 if (pdpe == NULL || *pdpe == 0)
7989 if (*pdpe & PG_PS) {
7991 * If the current 1GB page already has the required
7992 * memory type, then we need not demote this page. Just
7993 * increment tmpva to the next 1GB page frame.
7995 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7996 tmpva = trunc_1gpage(tmpva) + NBPDP;
8001 * If the current offset aligns with a 1GB page frame
8002 * and there is at least 1GB left within the range, then
8003 * we need not break down this page into 2MB pages.
8005 if ((tmpva & PDPMASK) == 0 &&
8006 tmpva + PDPMASK < base + size) {
8010 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8013 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8018 * If the current 2MB page already has the required
8019 * memory type, then we need not demote this page. Just
8020 * increment tmpva to the next 2MB page frame.
8022 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
8023 tmpva = trunc_2mpage(tmpva) + NBPDR;
8028 * If the current offset aligns with a 2MB page frame
8029 * and there is at least 2MB left within the range, then
8030 * we need not break down this page into 4KB pages.
8032 if ((tmpva & PDRMASK) == 0 &&
8033 tmpva + PDRMASK < base + size) {
8037 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8040 pte = pmap_pde_to_pte(pde, tmpva);
8048 * Ok, all the pages exist, so run through them updating their
8049 * cache mode if required.
8051 pa_start = pa_end = 0;
8052 for (tmpva = base; tmpva < base + size; ) {
8053 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8054 if (*pdpe & PG_PS) {
8055 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
8056 pmap_pde_attr(pdpe, cache_bits_pde,
8060 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8061 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8062 if (pa_start == pa_end) {
8063 /* Start physical address run. */
8064 pa_start = *pdpe & PG_PS_FRAME;
8065 pa_end = pa_start + NBPDP;
8066 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8069 /* Run ended, update direct map. */
8070 error = pmap_change_attr_locked(
8071 PHYS_TO_DMAP(pa_start),
8072 pa_end - pa_start, mode, noflush);
8075 /* Start physical address run. */
8076 pa_start = *pdpe & PG_PS_FRAME;
8077 pa_end = pa_start + NBPDP;
8080 tmpva = trunc_1gpage(tmpva) + NBPDP;
8083 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8085 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
8086 pmap_pde_attr(pde, cache_bits_pde,
8090 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8091 (*pde & PG_PS_FRAME) < dmaplimit) {
8092 if (pa_start == pa_end) {
8093 /* Start physical address run. */
8094 pa_start = *pde & PG_PS_FRAME;
8095 pa_end = pa_start + NBPDR;
8096 } else if (pa_end == (*pde & PG_PS_FRAME))
8099 /* Run ended, update direct map. */
8100 error = pmap_change_attr_locked(
8101 PHYS_TO_DMAP(pa_start),
8102 pa_end - pa_start, mode, noflush);
8105 /* Start physical address run. */
8106 pa_start = *pde & PG_PS_FRAME;
8107 pa_end = pa_start + NBPDR;
8110 tmpva = trunc_2mpage(tmpva) + NBPDR;
8112 pte = pmap_pde_to_pte(pde, tmpva);
8113 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
8114 pmap_pte_attr(pte, cache_bits_pte,
8118 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8119 (*pte & PG_FRAME) < dmaplimit) {
8120 if (pa_start == pa_end) {
8121 /* Start physical address run. */
8122 pa_start = *pte & PG_FRAME;
8123 pa_end = pa_start + PAGE_SIZE;
8124 } else if (pa_end == (*pte & PG_FRAME))
8125 pa_end += PAGE_SIZE;
8127 /* Run ended, update direct map. */
8128 error = pmap_change_attr_locked(
8129 PHYS_TO_DMAP(pa_start),
8130 pa_end - pa_start, mode, noflush);
8133 /* Start physical address run. */
8134 pa_start = *pte & PG_FRAME;
8135 pa_end = pa_start + PAGE_SIZE;
8141 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8142 pa_end1 = MIN(pa_end, dmaplimit);
8143 if (pa_start != pa_end1)
8144 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
8145 pa_end1 - pa_start, mode, noflush);
8149 * Flush CPU caches if required to make sure any data isn't cached that
8150 * shouldn't be, etc.
8153 pmap_invalidate_range(kernel_pmap, base, tmpva);
8155 pmap_invalidate_cache_range(base, tmpva);
8161 * Demotes any mapping within the direct map region that covers more than the
8162 * specified range of physical addresses. This range's size must be a power
8163 * of two and its starting address must be a multiple of its size. Since the
8164 * demotion does not change any attributes of the mapping, a TLB invalidation
8165 * is not mandatory. The caller may, however, request a TLB invalidation.
8168 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8177 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8178 KASSERT((base & (len - 1)) == 0,
8179 ("pmap_demote_DMAP: base is not a multiple of len"));
8180 if (len < NBPDP && base < dmaplimit) {
8181 va = PHYS_TO_DMAP(base);
8183 PMAP_LOCK(kernel_pmap);
8184 pdpe = pmap_pdpe(kernel_pmap, va);
8185 if ((*pdpe & X86_PG_V) == 0)
8186 panic("pmap_demote_DMAP: invalid PDPE");
8187 if ((*pdpe & PG_PS) != 0) {
8188 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8189 panic("pmap_demote_DMAP: PDPE failed");
8193 pde = pmap_pdpe_to_pde(pdpe, va);
8194 if ((*pde & X86_PG_V) == 0)
8195 panic("pmap_demote_DMAP: invalid PDE");
8196 if ((*pde & PG_PS) != 0) {
8197 if (!pmap_demote_pde(kernel_pmap, pde, va))
8198 panic("pmap_demote_DMAP: PDE failed");
8202 if (changed && invalidate)
8203 pmap_invalidate_page(kernel_pmap, va);
8204 PMAP_UNLOCK(kernel_pmap);
8209 * perform the pmap work for mincore
8212 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8215 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8219 PG_A = pmap_accessed_bit(pmap);
8220 PG_M = pmap_modified_bit(pmap);
8221 PG_V = pmap_valid_bit(pmap);
8222 PG_RW = pmap_rw_bit(pmap);
8226 pdep = pmap_pde(pmap, addr);
8227 if (pdep != NULL && (*pdep & PG_V)) {
8228 if (*pdep & PG_PS) {
8230 /* Compute the physical address of the 4KB page. */
8231 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8233 val = MINCORE_SUPER;
8235 pte = *pmap_pde_to_pte(pdep, addr);
8236 pa = pte & PG_FRAME;
8244 if ((pte & PG_V) != 0) {
8245 val |= MINCORE_INCORE;
8246 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8247 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8248 if ((pte & PG_A) != 0)
8249 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8251 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8252 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8253 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8254 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8255 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8258 PA_UNLOCK_COND(*locked_pa);
8264 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8266 uint32_t gen, new_gen, pcid_next;
8268 CRITICAL_ASSERT(curthread);
8269 gen = PCPU_GET(pcid_gen);
8270 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8271 return (pti ? 0 : CR3_PCID_SAVE);
8272 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8273 return (CR3_PCID_SAVE);
8274 pcid_next = PCPU_GET(pcid_next);
8275 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8276 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8277 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8278 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8279 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8283 PCPU_SET(pcid_gen, new_gen);
8284 pcid_next = PMAP_PCID_KERN + 1;
8288 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8289 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8290 PCPU_SET(pcid_next, pcid_next + 1);
8295 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8299 cached = pmap_pcid_alloc(pmap, cpuid);
8300 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8301 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8302 pmap->pm_pcids[cpuid].pm_pcid));
8303 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8304 pmap == kernel_pmap,
8305 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8306 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8311 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8314 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8315 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
8319 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8321 struct invpcid_descr d;
8322 uint64_t cached, cr3, kcr3, ucr3;
8324 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8326 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8327 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8328 PCPU_SET(curpmap, pmap);
8329 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8330 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8333 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8335 * Explicitly invalidate translations cached from the
8336 * user page table. They are not automatically
8337 * flushed by reload of cr3 with the kernel page table
8340 * Note that the if() condition is resolved statically
8341 * by using the function argument instead of
8342 * runtime-evaluated invpcid_works value.
8344 if (invpcid_works1) {
8345 d.pcid = PMAP_PCID_USER_PT |
8346 pmap->pm_pcids[cpuid].pm_pcid;
8349 invpcid(&d, INVPCID_CTX);
8351 pmap_pti_pcid_invalidate(ucr3, kcr3);
8355 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8356 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8358 PCPU_INC(pm_save_cnt);
8362 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8365 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8366 pmap_activate_sw_pti_post(td, pmap);
8370 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8376 * If the INVPCID instruction is not available,
8377 * invltlb_pcid_handler() is used to handle an invalidate_all
8378 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8379 * sequence of operations has a window where %CR3 is loaded
8380 * with the new pmap's PML4 address, but the curpmap value has
8381 * not yet been updated. This causes the invltlb IPI handler,
8382 * which is called between the updates, to execute as a NOP,
8383 * which leaves stale TLB entries.
8385 * Note that the most typical use of pmap_activate_sw(), from
8386 * the context switch, is immune to this race, because
8387 * interrupts are disabled (while the thread lock is owned),
8388 * and the IPI happens after curpmap is updated. Protect
8389 * other callers in a similar way, by disabling interrupts
8390 * around the %cr3 register reload and curpmap assignment.
8392 rflags = intr_disable();
8393 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8394 intr_restore(rflags);
8395 pmap_activate_sw_pti_post(td, pmap);
8399 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8402 uint64_t cached, cr3;
8404 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8406 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8407 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8409 PCPU_SET(curpmap, pmap);
8411 PCPU_INC(pm_save_cnt);
8415 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8420 rflags = intr_disable();
8421 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8422 intr_restore(rflags);
8426 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8427 u_int cpuid __unused)
8430 load_cr3(pmap->pm_cr3);
8431 PCPU_SET(curpmap, pmap);
8435 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8436 u_int cpuid __unused)
8439 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8440 PCPU_SET(kcr3, pmap->pm_cr3);
8441 PCPU_SET(ucr3, pmap->pm_ucr3);
8442 pmap_activate_sw_pti_post(td, pmap);
8445 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8449 if (pmap_pcid_enabled && pti && invpcid_works)
8450 return (pmap_activate_sw_pcid_invpcid_pti);
8451 else if (pmap_pcid_enabled && pti && !invpcid_works)
8452 return (pmap_activate_sw_pcid_noinvpcid_pti);
8453 else if (pmap_pcid_enabled && !pti && invpcid_works)
8454 return (pmap_activate_sw_pcid_nopti);
8455 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8456 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8457 else if (!pmap_pcid_enabled && pti)
8458 return (pmap_activate_sw_nopcid_pti);
8459 else /* if (!pmap_pcid_enabled && !pti) */
8460 return (pmap_activate_sw_nopcid_nopti);
8464 pmap_activate_sw(struct thread *td)
8466 pmap_t oldpmap, pmap;
8469 oldpmap = PCPU_GET(curpmap);
8470 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8471 if (oldpmap == pmap)
8473 cpuid = PCPU_GET(cpuid);
8475 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8477 CPU_SET(cpuid, &pmap->pm_active);
8479 pmap_activate_sw_mode(td, pmap, cpuid);
8481 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8483 CPU_CLR(cpuid, &oldpmap->pm_active);
8488 pmap_activate(struct thread *td)
8492 pmap_activate_sw(td);
8497 pmap_activate_boot(pmap_t pmap)
8503 * kernel_pmap must be never deactivated, and we ensure that
8504 * by never activating it at all.
8506 MPASS(pmap != kernel_pmap);
8508 cpuid = PCPU_GET(cpuid);
8510 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8512 CPU_SET(cpuid, &pmap->pm_active);
8514 PCPU_SET(curpmap, pmap);
8516 kcr3 = pmap->pm_cr3;
8517 if (pmap_pcid_enabled)
8518 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8522 PCPU_SET(kcr3, kcr3);
8523 PCPU_SET(ucr3, PMAP_NO_CR3);
8527 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8532 * Increase the starting virtual address of the given mapping if a
8533 * different alignment might result in more superpage mappings.
8536 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8537 vm_offset_t *addr, vm_size_t size)
8539 vm_offset_t superpage_offset;
8543 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8544 offset += ptoa(object->pg_color);
8545 superpage_offset = offset & PDRMASK;
8546 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8547 (*addr & PDRMASK) == superpage_offset)
8549 if ((*addr & PDRMASK) < superpage_offset)
8550 *addr = (*addr & ~PDRMASK) + superpage_offset;
8552 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8556 static unsigned long num_dirty_emulations;
8557 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8558 &num_dirty_emulations, 0, NULL);
8560 static unsigned long num_accessed_emulations;
8561 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8562 &num_accessed_emulations, 0, NULL);
8564 static unsigned long num_superpage_accessed_emulations;
8565 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8566 &num_superpage_accessed_emulations, 0, NULL);
8568 static unsigned long ad_emulation_superpage_promotions;
8569 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8570 &ad_emulation_superpage_promotions, 0, NULL);
8571 #endif /* INVARIANTS */
8574 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8577 struct rwlock *lock;
8578 #if VM_NRESERVLEVEL > 0
8582 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8584 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8585 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8587 if (!pmap_emulate_ad_bits(pmap))
8590 PG_A = pmap_accessed_bit(pmap);
8591 PG_M = pmap_modified_bit(pmap);
8592 PG_V = pmap_valid_bit(pmap);
8593 PG_RW = pmap_rw_bit(pmap);
8599 pde = pmap_pde(pmap, va);
8600 if (pde == NULL || (*pde & PG_V) == 0)
8603 if ((*pde & PG_PS) != 0) {
8604 if (ftype == VM_PROT_READ) {
8606 atomic_add_long(&num_superpage_accessed_emulations, 1);
8614 pte = pmap_pde_to_pte(pde, va);
8615 if ((*pte & PG_V) == 0)
8618 if (ftype == VM_PROT_WRITE) {
8619 if ((*pte & PG_RW) == 0)
8622 * Set the modified and accessed bits simultaneously.
8624 * Intel EPT PTEs that do software emulation of A/D bits map
8625 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8626 * An EPT misconfiguration is triggered if the PTE is writable
8627 * but not readable (WR=10). This is avoided by setting PG_A
8628 * and PG_M simultaneously.
8630 *pte |= PG_M | PG_A;
8635 #if VM_NRESERVLEVEL > 0
8636 /* try to promote the mapping */
8637 if (va < VM_MAXUSER_ADDRESS)
8638 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8642 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8644 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8645 pmap_ps_enabled(pmap) &&
8646 (m->flags & PG_FICTITIOUS) == 0 &&
8647 vm_reserv_level_iffullpop(m) == 0) {
8648 pmap_promote_pde(pmap, pde, va, &lock);
8650 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8656 if (ftype == VM_PROT_WRITE)
8657 atomic_add_long(&num_dirty_emulations, 1);
8659 atomic_add_long(&num_accessed_emulations, 1);
8661 rv = 0; /* success */
8670 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8675 pt_entry_t *pte, PG_V;
8679 PG_V = pmap_valid_bit(pmap);
8682 pml4 = pmap_pml4e(pmap, va);
8684 if ((*pml4 & PG_V) == 0)
8687 pdp = pmap_pml4e_to_pdpe(pml4, va);
8689 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8692 pde = pmap_pdpe_to_pde(pdp, va);
8694 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8697 pte = pmap_pde_to_pte(pde, va);
8706 * Get the kernel virtual address of a set of physical pages. If there are
8707 * physical addresses not covered by the DMAP perform a transient mapping
8708 * that will be removed when calling pmap_unmap_io_transient.
8710 * \param page The pages the caller wishes to obtain the virtual
8711 * address on the kernel memory map.
8712 * \param vaddr On return contains the kernel virtual memory address
8713 * of the pages passed in the page parameter.
8714 * \param count Number of pages passed in.
8715 * \param can_fault TRUE if the thread using the mapped pages can take
8716 * page faults, FALSE otherwise.
8718 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8719 * finished or FALSE otherwise.
8723 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8724 boolean_t can_fault)
8727 boolean_t needs_mapping;
8729 int cache_bits, error __unused, i;
8732 * Allocate any KVA space that we need, this is done in a separate
8733 * loop to prevent calling vmem_alloc while pinned.
8735 needs_mapping = FALSE;
8736 for (i = 0; i < count; i++) {
8737 paddr = VM_PAGE_TO_PHYS(page[i]);
8738 if (__predict_false(paddr >= dmaplimit)) {
8739 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8740 M_BESTFIT | M_WAITOK, &vaddr[i]);
8741 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8742 needs_mapping = TRUE;
8744 vaddr[i] = PHYS_TO_DMAP(paddr);
8748 /* Exit early if everything is covered by the DMAP */
8753 * NB: The sequence of updating a page table followed by accesses
8754 * to the corresponding pages used in the !DMAP case is subject to
8755 * the situation described in the "AMD64 Architecture Programmer's
8756 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8757 * Coherency Considerations". Therefore, issuing the INVLPG right
8758 * after modifying the PTE bits is crucial.
8762 for (i = 0; i < count; i++) {
8763 paddr = VM_PAGE_TO_PHYS(page[i]);
8764 if (paddr >= dmaplimit) {
8767 * Slow path, since we can get page faults
8768 * while mappings are active don't pin the
8769 * thread to the CPU and instead add a global
8770 * mapping visible to all CPUs.
8772 pmap_qenter(vaddr[i], &page[i], 1);
8774 pte = vtopte(vaddr[i]);
8775 cache_bits = pmap_cache_bits(kernel_pmap,
8776 page[i]->md.pat_mode, 0);
8777 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8784 return (needs_mapping);
8788 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8789 boolean_t can_fault)
8796 for (i = 0; i < count; i++) {
8797 paddr = VM_PAGE_TO_PHYS(page[i]);
8798 if (paddr >= dmaplimit) {
8800 pmap_qremove(vaddr[i], 1);
8801 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8807 pmap_quick_enter_page(vm_page_t m)
8811 paddr = VM_PAGE_TO_PHYS(m);
8812 if (paddr < dmaplimit)
8813 return (PHYS_TO_DMAP(paddr));
8814 mtx_lock_spin(&qframe_mtx);
8815 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8816 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8817 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8822 pmap_quick_remove_page(vm_offset_t addr)
8827 pte_store(vtopte(qframe), 0);
8829 mtx_unlock_spin(&qframe_mtx);
8833 * Pdp pages from the large map are managed differently from either
8834 * kernel or user page table pages. They are permanently allocated at
8835 * initialization time, and their wire count is permanently set to
8836 * zero. The pml4 entries pointing to those pages are copied into
8837 * each allocated pmap.
8839 * In contrast, pd and pt pages are managed like user page table
8840 * pages. They are dynamically allocated, and their wire count
8841 * represents the number of valid entries within the page.
8844 pmap_large_map_getptp_unlocked(void)
8848 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8850 if (m != NULL && (m->flags & PG_ZERO) == 0)
8856 pmap_large_map_getptp(void)
8860 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8861 m = pmap_large_map_getptp_unlocked();
8863 PMAP_UNLOCK(kernel_pmap);
8865 PMAP_LOCK(kernel_pmap);
8866 /* Callers retry. */
8871 static pdp_entry_t *
8872 pmap_large_map_pdpe(vm_offset_t va)
8874 vm_pindex_t pml4_idx;
8877 pml4_idx = pmap_pml4e_index(va);
8878 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8879 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8881 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8882 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8883 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8884 "LMSPML4I %#jx lm_ents %d",
8885 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8886 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8887 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8891 pmap_large_map_pde(vm_offset_t va)
8898 pdpe = pmap_large_map_pdpe(va);
8900 m = pmap_large_map_getptp();
8903 mphys = VM_PAGE_TO_PHYS(m);
8904 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8906 MPASS((*pdpe & X86_PG_PS) == 0);
8907 mphys = *pdpe & PG_FRAME;
8909 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
8913 pmap_large_map_pte(vm_offset_t va)
8920 pde = pmap_large_map_pde(va);
8922 m = pmap_large_map_getptp();
8925 mphys = VM_PAGE_TO_PHYS(m);
8926 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8927 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
8929 MPASS((*pde & X86_PG_PS) == 0);
8930 mphys = *pde & PG_FRAME;
8932 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
8936 pmap_large_map_kextract(vm_offset_t va)
8938 pdp_entry_t *pdpe, pdp;
8939 pd_entry_t *pde, pd;
8940 pt_entry_t *pte, pt;
8942 KASSERT(LARGEMAP_MIN_ADDRESS <= va && va < PMAP_LARGEMAP_MAX_ADDRESS(),
8943 ("not largemap range %#lx", (u_long)va));
8944 pdpe = pmap_large_map_pdpe(va);
8946 KASSERT((pdp & X86_PG_V) != 0,
8947 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
8948 (u_long)pdpe, pdp));
8949 if ((pdp & X86_PG_PS) != 0) {
8950 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
8951 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
8952 (u_long)pdpe, pdp));
8953 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
8955 pde = pmap_pdpe_to_pde(pdpe, va);
8957 KASSERT((pd & X86_PG_V) != 0,
8958 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
8959 if ((pd & X86_PG_PS) != 0)
8960 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
8961 pte = pmap_pde_to_pte(pde, va);
8963 KASSERT((pt & X86_PG_V) != 0,
8964 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
8965 return ((pt & PG_FRAME) | (va & PAGE_MASK));
8969 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
8970 vmem_addr_t *vmem_res)
8974 * Large mappings are all but static. Consequently, there
8975 * is no point in waiting for an earlier allocation to be
8978 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
8979 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
8983 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
8989 vm_offset_t va, inc;
8990 vmem_addr_t vmem_res;
8994 if (len == 0 || spa + len < spa)
8997 /* See if DMAP can serve. */
8998 if (spa + len <= dmaplimit) {
8999 va = PHYS_TO_DMAP(spa);
9001 return (pmap_change_attr(va, len, mattr));
9005 * No, allocate KVA. Fit the address with best possible
9006 * alignment for superpages. Fall back to worse align if
9010 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9011 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9012 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9014 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9016 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9019 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9024 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9025 * in the pagetable to minimize flushing. No need to
9026 * invalidate TLB, since we only update invalid entries.
9028 PMAP_LOCK(kernel_pmap);
9029 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9031 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9032 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9033 pdpe = pmap_large_map_pdpe(va);
9035 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9036 X86_PG_V | X86_PG_A | pg_nx |
9037 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9039 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9040 (va & PDRMASK) == 0) {
9041 pde = pmap_large_map_pde(va);
9043 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9044 X86_PG_V | X86_PG_A | pg_nx |
9045 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9046 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9050 pte = pmap_large_map_pte(va);
9052 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9053 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9055 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9060 PMAP_UNLOCK(kernel_pmap);
9063 *addr = (void *)vmem_res;
9068 pmap_large_unmap(void *svaa, vm_size_t len)
9070 vm_offset_t sva, va;
9072 pdp_entry_t *pdpe, pdp;
9073 pd_entry_t *pde, pd;
9076 struct spglist spgf;
9078 sva = (vm_offset_t)svaa;
9079 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9080 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9084 KASSERT(LARGEMAP_MIN_ADDRESS <= sva &&
9085 sva + len <= PMAP_LARGEMAP_MAX_ADDRESS(),
9086 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9087 PMAP_LOCK(kernel_pmap);
9088 for (va = sva; va < sva + len; va += inc) {
9089 pdpe = pmap_large_map_pdpe(va);
9091 KASSERT((pdp & X86_PG_V) != 0,
9092 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9093 (u_long)pdpe, pdp));
9094 if ((pdp & X86_PG_PS) != 0) {
9095 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9096 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9097 (u_long)pdpe, pdp));
9098 KASSERT((va & PDPMASK) == 0,
9099 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9100 (u_long)pdpe, pdp));
9101 KASSERT(va + NBPDP <= sva + len,
9102 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9103 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9104 (u_long)pdpe, pdp, len));
9109 pde = pmap_pdpe_to_pde(pdpe, va);
9111 KASSERT((pd & X86_PG_V) != 0,
9112 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9114 if ((pd & X86_PG_PS) != 0) {
9115 KASSERT((va & PDRMASK) == 0,
9116 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9118 KASSERT(va + NBPDR <= sva + len,
9119 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9120 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9124 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9126 if (m->wire_count == 0) {
9128 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9132 pte = pmap_pde_to_pte(pde, va);
9133 KASSERT((*pte & X86_PG_V) != 0,
9134 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9135 (u_long)pte, *pte));
9138 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9140 if (m->wire_count == 0) {
9142 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9143 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9145 if (m->wire_count == 0) {
9147 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9151 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9152 PMAP_UNLOCK(kernel_pmap);
9153 vm_page_free_pages_toq(&spgf, false);
9154 vmem_free(large_vmem, sva, len);
9158 pmap_large_map_wb_fence_mfence(void)
9165 pmap_large_map_wb_fence_sfence(void)
9172 pmap_large_map_wb_fence_nop(void)
9176 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9179 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9180 return (pmap_large_map_wb_fence_mfence);
9181 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9182 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9183 return (pmap_large_map_wb_fence_sfence);
9185 /* clflush is strongly enough ordered */
9186 return (pmap_large_map_wb_fence_nop);
9190 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9193 for (; len > 0; len -= cpu_clflush_line_size,
9194 va += cpu_clflush_line_size)
9199 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9202 for (; len > 0; len -= cpu_clflush_line_size,
9203 va += cpu_clflush_line_size)
9208 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9211 for (; len > 0; len -= cpu_clflush_line_size,
9212 va += cpu_clflush_line_size)
9217 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9221 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9224 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9225 return (pmap_large_map_flush_range_clwb);
9226 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9227 return (pmap_large_map_flush_range_clflushopt);
9228 else if ((cpu_feature & CPUID_CLFSH) != 0)
9229 return (pmap_large_map_flush_range_clflush);
9231 return (pmap_large_map_flush_range_nop);
9235 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9237 volatile u_long *pe;
9243 for (va = sva; va < eva; va += inc) {
9245 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9246 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9248 if ((p & X86_PG_PS) != 0)
9252 pe = (volatile u_long *)pmap_large_map_pde(va);
9254 if ((p & X86_PG_PS) != 0)
9258 pe = (volatile u_long *)pmap_large_map_pte(va);
9264 if ((p & X86_PG_AVAIL1) != 0) {
9266 * Spin-wait for the end of a parallel
9273 * If we saw other write-back
9274 * occuring, we cannot rely on PG_M to
9275 * indicate state of the cache. The
9276 * PG_M bit is cleared before the
9277 * flush to avoid ignoring new writes,
9278 * and writes which are relevant for
9279 * us might happen after.
9285 if ((p & X86_PG_M) != 0 || seen_other) {
9286 if (!atomic_fcmpset_long(pe, &p,
9287 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9289 * If we saw PG_M without
9290 * PG_AVAIL1, and then on the
9291 * next attempt we do not
9292 * observe either PG_M or
9293 * PG_AVAIL1, the other
9294 * write-back started after us
9295 * and finished before us. We
9296 * can rely on it doing our
9300 pmap_large_map_flush_range(va, inc);
9301 atomic_clear_long(pe, X86_PG_AVAIL1);
9310 * Write-back cache lines for the given address range.
9312 * Must be called only on the range or sub-range returned from
9313 * pmap_large_map(). Must not be called on the coalesced ranges.
9315 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9316 * instructions support.
9319 pmap_large_map_wb(void *svap, vm_size_t len)
9321 vm_offset_t eva, sva;
9323 sva = (vm_offset_t)svap;
9325 pmap_large_map_wb_fence();
9326 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9327 pmap_large_map_flush_range(sva, len);
9329 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9330 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9331 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9332 pmap_large_map_wb_large(sva, eva);
9334 pmap_large_map_wb_fence();
9338 pmap_pti_alloc_page(void)
9342 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9343 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9344 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9349 pmap_pti_free_page(vm_page_t m)
9352 KASSERT(m->wire_count > 0, ("page %p not wired", m));
9353 if (!vm_page_unwire_noq(m))
9355 vm_page_free_zero(m);
9369 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9370 VM_OBJECT_WLOCK(pti_obj);
9371 pml4_pg = pmap_pti_alloc_page();
9372 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9373 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9374 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9375 pdpe = pmap_pti_pdpe(va);
9376 pmap_pti_wire_pte(pdpe);
9378 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9379 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9380 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9381 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9382 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9383 sizeof(struct gate_descriptor) * NIDT, false);
9384 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9385 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9387 /* Doublefault stack IST 1 */
9388 va = common_tss[i].tss_ist1;
9389 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9390 /* NMI stack IST 2 */
9391 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9392 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9393 /* MC# stack IST 3 */
9394 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9395 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9396 /* DB# stack IST 4 */
9397 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9398 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9400 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9401 (vm_offset_t)etext, true);
9402 pti_finalized = true;
9403 VM_OBJECT_WUNLOCK(pti_obj);
9405 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9407 static pdp_entry_t *
9408 pmap_pti_pdpe(vm_offset_t va)
9410 pml4_entry_t *pml4e;
9413 vm_pindex_t pml4_idx;
9416 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9418 pml4_idx = pmap_pml4e_index(va);
9419 pml4e = &pti_pml4[pml4_idx];
9423 panic("pml4 alloc after finalization\n");
9424 m = pmap_pti_alloc_page();
9426 pmap_pti_free_page(m);
9427 mphys = *pml4e & ~PAGE_MASK;
9429 mphys = VM_PAGE_TO_PHYS(m);
9430 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9433 mphys = *pml4e & ~PAGE_MASK;
9435 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9440 pmap_pti_wire_pte(void *pte)
9444 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9445 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9450 pmap_pti_unwire_pde(void *pde, bool only_ref)
9454 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9455 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9456 MPASS(m->wire_count > 0);
9457 MPASS(only_ref || m->wire_count > 1);
9458 pmap_pti_free_page(m);
9462 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9467 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9468 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9469 MPASS(m->wire_count > 0);
9470 if (pmap_pti_free_page(m)) {
9471 pde = pmap_pti_pde(va);
9472 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9474 pmap_pti_unwire_pde(pde, false);
9479 pmap_pti_pde(vm_offset_t va)
9487 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9489 pdpe = pmap_pti_pdpe(va);
9491 m = pmap_pti_alloc_page();
9493 pmap_pti_free_page(m);
9494 MPASS((*pdpe & X86_PG_PS) == 0);
9495 mphys = *pdpe & ~PAGE_MASK;
9497 mphys = VM_PAGE_TO_PHYS(m);
9498 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9501 MPASS((*pdpe & X86_PG_PS) == 0);
9502 mphys = *pdpe & ~PAGE_MASK;
9505 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9506 pd_idx = pmap_pde_index(va);
9512 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9519 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9521 pde = pmap_pti_pde(va);
9522 if (unwire_pde != NULL) {
9524 pmap_pti_wire_pte(pde);
9527 m = pmap_pti_alloc_page();
9529 pmap_pti_free_page(m);
9530 MPASS((*pde & X86_PG_PS) == 0);
9531 mphys = *pde & ~(PAGE_MASK | pg_nx);
9533 mphys = VM_PAGE_TO_PHYS(m);
9534 *pde = mphys | X86_PG_RW | X86_PG_V;
9535 if (unwire_pde != NULL)
9536 *unwire_pde = false;
9539 MPASS((*pde & X86_PG_PS) == 0);
9540 mphys = *pde & ~(PAGE_MASK | pg_nx);
9543 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9544 pte += pmap_pte_index(va);
9550 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9554 pt_entry_t *pte, ptev;
9557 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9559 sva = trunc_page(sva);
9560 MPASS(sva > VM_MAXUSER_ADDRESS);
9561 eva = round_page(eva);
9563 for (; sva < eva; sva += PAGE_SIZE) {
9564 pte = pmap_pti_pte(sva, &unwire_pde);
9565 pa = pmap_kextract(sva);
9566 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9567 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9568 VM_MEMATTR_DEFAULT, FALSE);
9570 pte_store(pte, ptev);
9571 pmap_pti_wire_pte(pte);
9573 KASSERT(!pti_finalized,
9574 ("pti overlap after fin %#lx %#lx %#lx",
9576 KASSERT(*pte == ptev,
9577 ("pti non-identical pte after fin %#lx %#lx %#lx",
9581 pde = pmap_pti_pde(sva);
9582 pmap_pti_unwire_pde(pde, true);
9588 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9593 VM_OBJECT_WLOCK(pti_obj);
9594 pmap_pti_add_kva_locked(sva, eva, exec);
9595 VM_OBJECT_WUNLOCK(pti_obj);
9599 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9606 sva = rounddown2(sva, PAGE_SIZE);
9607 MPASS(sva > VM_MAXUSER_ADDRESS);
9608 eva = roundup2(eva, PAGE_SIZE);
9610 VM_OBJECT_WLOCK(pti_obj);
9611 for (va = sva; va < eva; va += PAGE_SIZE) {
9612 pte = pmap_pti_pte(va, NULL);
9613 KASSERT((*pte & X86_PG_V) != 0,
9614 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9615 (u_long)pte, *pte));
9617 pmap_pti_unwire_pte(pte, va);
9619 pmap_invalidate_range(kernel_pmap, sva, eva);
9620 VM_OBJECT_WUNLOCK(pti_obj);
9624 pkru_dup_range(void *ctx __unused, void *data)
9626 struct pmap_pkru_range *node, *new_node;
9628 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9629 if (new_node == NULL)
9632 memcpy(new_node, node, sizeof(*node));
9637 pkru_free_range(void *ctx __unused, void *node)
9640 uma_zfree(pmap_pkru_ranges_zone, node);
9644 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9647 struct pmap_pkru_range *ppr;
9650 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9651 MPASS(pmap->pm_type == PT_X86);
9652 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9653 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9654 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9656 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9659 ppr->pkru_keyidx = keyidx;
9660 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9661 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9663 uma_zfree(pmap_pkru_ranges_zone, ppr);
9668 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9671 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9672 MPASS(pmap->pm_type == PT_X86);
9673 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9674 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9678 pmap_pkru_deassign_all(pmap_t pmap)
9681 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9682 if (pmap->pm_type == PT_X86 &&
9683 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9684 rangeset_remove_all(&pmap->pm_pkru);
9688 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9690 struct pmap_pkru_range *ppr, *prev_ppr;
9693 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9694 if (pmap->pm_type != PT_X86 ||
9695 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9696 sva >= VM_MAXUSER_ADDRESS)
9698 MPASS(eva <= VM_MAXUSER_ADDRESS);
9699 for (va = sva, prev_ppr = NULL; va < eva;) {
9700 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9701 if ((ppr == NULL) ^ (prev_ppr == NULL))
9707 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9709 va = ppr->pkru_rs_el.re_end;
9715 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9717 struct pmap_pkru_range *ppr;
9719 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9720 if (pmap->pm_type != PT_X86 ||
9721 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9722 va >= VM_MAXUSER_ADDRESS)
9724 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9726 return (X86_PG_PKU(ppr->pkru_keyidx));
9731 pred_pkru_on_remove(void *ctx __unused, void *r)
9733 struct pmap_pkru_range *ppr;
9736 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9740 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9743 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9744 if (pmap->pm_type == PT_X86 &&
9745 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9746 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9747 pred_pkru_on_remove);
9752 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9755 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9756 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9757 MPASS(dst_pmap->pm_type == PT_X86);
9758 MPASS(src_pmap->pm_type == PT_X86);
9759 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9760 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9762 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9766 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9769 pml4_entry_t *pml4e;
9771 pd_entry_t newpde, ptpaddr, *pde;
9772 pt_entry_t newpte, *ptep, pte;
9773 vm_offset_t va, va_next;
9776 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9777 MPASS(pmap->pm_type == PT_X86);
9778 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9780 for (changed = false, va = sva; va < eva; va = va_next) {
9781 pml4e = pmap_pml4e(pmap, va);
9782 if ((*pml4e & X86_PG_V) == 0) {
9783 va_next = (va + NBPML4) & ~PML4MASK;
9789 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9790 if ((*pdpe & X86_PG_V) == 0) {
9791 va_next = (va + NBPDP) & ~PDPMASK;
9797 va_next = (va + NBPDR) & ~PDRMASK;
9801 pde = pmap_pdpe_to_pde(pdpe, va);
9806 MPASS((ptpaddr & X86_PG_V) != 0);
9807 if ((ptpaddr & PG_PS) != 0) {
9808 if (va + NBPDR == va_next && eva >= va_next) {
9809 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9811 if (newpde != ptpaddr) {
9816 } else if (!pmap_demote_pde(pmap, pde, va)) {
9824 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9825 ptep++, va += PAGE_SIZE) {
9827 if ((pte & X86_PG_V) == 0)
9829 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9830 if (newpte != pte) {
9837 pmap_invalidate_range(pmap, sva, eva);
9841 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9842 u_int keyidx, int flags)
9845 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9846 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9848 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9850 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9856 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9861 sva = trunc_page(sva);
9862 eva = round_page(eva);
9863 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9868 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9870 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9872 if (error != ENOMEM)
9880 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9884 sva = trunc_page(sva);
9885 eva = round_page(eva);
9886 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9891 error = pmap_pkru_deassign(pmap, sva, eva);
9893 pmap_pkru_update_range(pmap, sva, eva, 0);
9895 if (error != ENOMEM)
9903 DB_SHOW_COMMAND(pte, pmap_print_pte)
9909 pt_entry_t *pte, PG_V;
9913 db_printf("show pte addr\n");
9916 va = (vm_offset_t)addr;
9918 if (kdb_thread != NULL)
9919 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
9921 pmap = PCPU_GET(curpmap);
9923 PG_V = pmap_valid_bit(pmap);
9924 pml4 = pmap_pml4e(pmap, va);
9925 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
9926 if ((*pml4 & PG_V) == 0) {
9930 pdp = pmap_pml4e_to_pdpe(pml4, va);
9931 db_printf(" pdpe %#016lx", *pdp);
9932 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
9936 pde = pmap_pdpe_to_pde(pdp, va);
9937 db_printf(" pde %#016lx", *pde);
9938 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
9942 pte = pmap_pde_to_pte(pde, va);
9943 db_printf(" pte %#016lx\n", *pte);
9946 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
9951 a = (vm_paddr_t)addr;
9952 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
9954 db_printf("show phys2dmap addr\n");