2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmem.h>
119 #include <sys/vmmeter.h>
120 #include <sys/sched.h>
121 #include <sys/sysctl.h>
122 #include <sys/_unrhdr.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
141 #include <machine/cpu.h>
142 #include <machine/cputypes.h>
143 #include <machine/md_var.h>
144 #include <machine/pcb.h>
145 #include <machine/specialreg.h>
147 #include <machine/smp.h>
150 static __inline boolean_t
151 pmap_type_guest(pmap_t pmap)
154 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
157 static __inline boolean_t
158 pmap_emulate_ad_bits(pmap_t pmap)
161 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
164 static __inline pt_entry_t
165 pmap_valid_bit(pmap_t pmap)
169 switch (pmap->pm_type) {
175 if (pmap_emulate_ad_bits(pmap))
176 mask = EPT_PG_EMUL_V;
181 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
187 static __inline pt_entry_t
188 pmap_rw_bit(pmap_t pmap)
192 switch (pmap->pm_type) {
198 if (pmap_emulate_ad_bits(pmap))
199 mask = EPT_PG_EMUL_RW;
204 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
210 static __inline pt_entry_t
211 pmap_global_bit(pmap_t pmap)
215 switch (pmap->pm_type) {
224 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
230 static __inline pt_entry_t
231 pmap_accessed_bit(pmap_t pmap)
235 switch (pmap->pm_type) {
241 if (pmap_emulate_ad_bits(pmap))
247 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
253 static __inline pt_entry_t
254 pmap_modified_bit(pmap_t pmap)
258 switch (pmap->pm_type) {
264 if (pmap_emulate_ad_bits(pmap))
270 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
276 extern struct pcpu __pcpu[];
278 #if !defined(DIAGNOSTIC)
279 #ifdef __GNUC_GNU_INLINE__
280 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
282 #define PMAP_INLINE extern inline
289 #define PV_STAT(x) do { x ; } while (0)
291 #define PV_STAT(x) do { } while (0)
294 #define pa_index(pa) ((pa) >> PDRSHIFT)
295 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
297 #define NPV_LIST_LOCKS MAXCPU
299 #define PHYS_TO_PV_LIST_LOCK(pa) \
300 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
302 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
303 struct rwlock **_lockp = (lockp); \
304 struct rwlock *_new_lock; \
306 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
307 if (_new_lock != *_lockp) { \
308 if (*_lockp != NULL) \
309 rw_wunlock(*_lockp); \
310 *_lockp = _new_lock; \
315 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
316 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
318 #define RELEASE_PV_LIST_LOCK(lockp) do { \
319 struct rwlock **_lockp = (lockp); \
321 if (*_lockp != NULL) { \
322 rw_wunlock(*_lockp); \
327 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
328 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
330 struct pmap kernel_pmap_store;
332 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
333 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
336 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
337 "Number of kernel page table pages allocated on bootup");
340 vm_paddr_t dmaplimit;
341 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
344 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
346 static int pat_works = 1;
347 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
348 "Is page attribute table fully functional?");
350 static int pg_ps_enabled = 1;
351 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
352 &pg_ps_enabled, 0, "Are large page mappings enabled?");
354 #define PAT_INDEX_SIZE 8
355 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
357 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
358 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
359 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
360 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
362 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
363 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
364 static int ndmpdpphys; /* number of DMPDPphys pages */
367 * pmap_mapdev support pre initialization (i.e. console)
369 #define PMAP_PREINIT_MAPPING_COUNT 8
370 static struct pmap_preinit_mapping {
375 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
376 static int pmap_initialized;
378 static struct rwlock_padalign pvh_global_lock;
381 * Data for the pv entry allocation mechanism
383 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
384 static struct mtx pv_chunks_mutex;
385 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
386 static struct md_page *pv_table;
389 * All those kernel PT submaps that BSD is so fond of
391 pt_entry_t *CMAP1 = 0;
393 static vm_offset_t qframe = 0;
394 static struct mtx qframe_mtx;
396 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
398 int pmap_pcid_enabled = 1;
399 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
400 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
401 int invpcid_works = 0;
402 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
403 "Is the invpcid instruction available ?");
406 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
413 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
415 return (sysctl_handle_64(oidp, &res, 0, req));
417 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
418 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
419 "Count of saved TLB context on switch");
424 static caddr_t crashdumpmap;
426 static void free_pv_chunk(struct pv_chunk *pc);
427 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
428 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
429 static int popcnt_pc_map_elem_pq(uint64_t elem);
430 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
431 static void reserve_pv_entries(pmap_t pmap, int needed,
432 struct rwlock **lockp);
433 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
434 struct rwlock **lockp);
435 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
436 struct rwlock **lockp);
437 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
438 struct rwlock **lockp);
439 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
440 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
443 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
444 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
445 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
446 vm_offset_t va, struct rwlock **lockp);
447 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
449 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
450 vm_prot_t prot, struct rwlock **lockp);
451 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
452 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
453 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
454 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
455 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
456 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
457 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
458 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
459 struct rwlock **lockp);
460 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
462 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
463 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
464 struct spglist *free, struct rwlock **lockp);
465 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
466 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
467 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
468 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
469 struct spglist *free);
470 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
471 vm_page_t m, struct rwlock **lockp);
472 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
474 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
476 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
477 struct rwlock **lockp);
478 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
479 struct rwlock **lockp);
480 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
481 struct rwlock **lockp);
483 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
484 struct spglist *free);
485 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
486 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
489 * Move the kernel virtual free pointer to the next
490 * 2MB. This is used to help improve performance
491 * by using a large (2MB) page for much of the kernel
492 * (.text, .data, .bss)
495 pmap_kmem_choose(vm_offset_t addr)
497 vm_offset_t newaddr = addr;
499 newaddr = roundup2(addr, NBPDR);
503 /********************/
504 /* Inline functions */
505 /********************/
507 /* Return a non-clipped PD index for a given VA */
508 static __inline vm_pindex_t
509 pmap_pde_pindex(vm_offset_t va)
511 return (va >> PDRSHIFT);
515 /* Return various clipped indexes for a given VA */
516 static __inline vm_pindex_t
517 pmap_pte_index(vm_offset_t va)
520 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
523 static __inline vm_pindex_t
524 pmap_pde_index(vm_offset_t va)
527 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
530 static __inline vm_pindex_t
531 pmap_pdpe_index(vm_offset_t va)
534 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
537 static __inline vm_pindex_t
538 pmap_pml4e_index(vm_offset_t va)
541 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
544 /* Return a pointer to the PML4 slot that corresponds to a VA */
545 static __inline pml4_entry_t *
546 pmap_pml4e(pmap_t pmap, vm_offset_t va)
549 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
552 /* Return a pointer to the PDP slot that corresponds to a VA */
553 static __inline pdp_entry_t *
554 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
558 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
559 return (&pdpe[pmap_pdpe_index(va)]);
562 /* Return a pointer to the PDP slot that corresponds to a VA */
563 static __inline pdp_entry_t *
564 pmap_pdpe(pmap_t pmap, vm_offset_t va)
569 PG_V = pmap_valid_bit(pmap);
570 pml4e = pmap_pml4e(pmap, va);
571 if ((*pml4e & PG_V) == 0)
573 return (pmap_pml4e_to_pdpe(pml4e, va));
576 /* Return a pointer to the PD slot that corresponds to a VA */
577 static __inline pd_entry_t *
578 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
582 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
583 return (&pde[pmap_pde_index(va)]);
586 /* Return a pointer to the PD slot that corresponds to a VA */
587 static __inline pd_entry_t *
588 pmap_pde(pmap_t pmap, vm_offset_t va)
593 PG_V = pmap_valid_bit(pmap);
594 pdpe = pmap_pdpe(pmap, va);
595 if (pdpe == NULL || (*pdpe & PG_V) == 0)
597 return (pmap_pdpe_to_pde(pdpe, va));
600 /* Return a pointer to the PT slot that corresponds to a VA */
601 static __inline pt_entry_t *
602 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
606 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
607 return (&pte[pmap_pte_index(va)]);
610 /* Return a pointer to the PT slot that corresponds to a VA */
611 static __inline pt_entry_t *
612 pmap_pte(pmap_t pmap, vm_offset_t va)
617 PG_V = pmap_valid_bit(pmap);
618 pde = pmap_pde(pmap, va);
619 if (pde == NULL || (*pde & PG_V) == 0)
621 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
622 return ((pt_entry_t *)pde);
623 return (pmap_pde_to_pte(pde, va));
627 pmap_resident_count_inc(pmap_t pmap, int count)
630 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
631 pmap->pm_stats.resident_count += count;
635 pmap_resident_count_dec(pmap_t pmap, int count)
638 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
639 KASSERT(pmap->pm_stats.resident_count >= count,
640 ("pmap %p resident count underflow %ld %d", pmap,
641 pmap->pm_stats.resident_count, count));
642 pmap->pm_stats.resident_count -= count;
645 PMAP_INLINE pt_entry_t *
646 vtopte(vm_offset_t va)
648 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
650 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
652 return (PTmap + ((va >> PAGE_SHIFT) & mask));
655 static __inline pd_entry_t *
656 vtopde(vm_offset_t va)
658 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
660 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
662 return (PDmap + ((va >> PDRSHIFT) & mask));
666 allocpages(vm_paddr_t *firstaddr, int n)
671 bzero((void *)ret, n * PAGE_SIZE);
672 *firstaddr += n * PAGE_SIZE;
676 CTASSERT(powerof2(NDMPML4E));
678 /* number of kernel PDP slots */
679 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
682 nkpt_init(vm_paddr_t addr)
689 pt_pages = howmany(addr, 1 << PDRSHIFT);
690 pt_pages += NKPDPE(pt_pages);
693 * Add some slop beyond the bare minimum required for bootstrapping
696 * This is quite important when allocating KVA for kernel modules.
697 * The modules are required to be linked in the negative 2GB of
698 * the address space. If we run out of KVA in this region then
699 * pmap_growkernel() will need to allocate page table pages to map
700 * the entire 512GB of KVA space which is an unnecessary tax on
703 * Secondly, device memory mapped as part of setting up the low-
704 * level console(s) is taken from KVA, starting at virtual_avail.
705 * This is because cninit() is called after pmap_bootstrap() but
706 * before vm_init() and pmap_init(). 20MB for a frame buffer is
709 pt_pages += 32; /* 64MB additional slop. */
715 create_pagetables(vm_paddr_t *firstaddr)
717 int i, j, ndm1g, nkpdpe;
723 /* Allocate page table pages for the direct map */
724 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
725 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
727 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
728 if (ndmpdpphys > NDMPML4E) {
730 * Each NDMPML4E allows 512 GB, so limit to that,
731 * and then readjust ndmpdp and ndmpdpphys.
733 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
734 Maxmem = atop(NDMPML4E * NBPML4);
735 ndmpdpphys = NDMPML4E;
736 ndmpdp = NDMPML4E * NPDEPG;
738 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
740 if ((amd_feature & AMDID_PAGE1GB) != 0)
741 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
743 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
744 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
747 KPML4phys = allocpages(firstaddr, 1);
748 KPDPphys = allocpages(firstaddr, NKPML4E);
751 * Allocate the initial number of kernel page table pages required to
752 * bootstrap. We defer this until after all memory-size dependent
753 * allocations are done (e.g. direct map), so that we don't have to
754 * build in too much slop in our estimate.
756 * Note that when NKPML4E > 1, we have an empty page underneath
757 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
758 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
760 nkpt_init(*firstaddr);
761 nkpdpe = NKPDPE(nkpt);
763 KPTphys = allocpages(firstaddr, nkpt);
764 KPDphys = allocpages(firstaddr, nkpdpe);
766 /* Fill in the underlying page table pages */
767 /* Nominally read-only (but really R/W) from zero to physfree */
768 /* XXX not fully used, underneath 2M pages */
769 pt_p = (pt_entry_t *)KPTphys;
770 for (i = 0; ptoa(i) < *firstaddr; i++)
771 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
773 /* Now map the page tables at their location within PTmap */
774 pd_p = (pd_entry_t *)KPDphys;
775 for (i = 0; i < nkpt; i++)
776 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
778 /* Map from zero to end of allocations under 2M pages */
779 /* This replaces some of the KPTphys entries above */
780 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
781 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
784 /* And connect up the PD to the PDP (leaving room for L4 pages) */
785 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
786 for (i = 0; i < nkpdpe; i++)
787 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
791 * Now, set up the direct map region using 2MB and/or 1GB pages. If
792 * the end of physical memory is not aligned to a 1GB page boundary,
793 * then the residual physical memory is mapped with 2MB pages. Later,
794 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
795 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
796 * that are partially used.
798 pd_p = (pd_entry_t *)DMPDphys;
799 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
800 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
801 /* Preset PG_M and PG_A because demotion expects it. */
802 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
805 pdp_p = (pdp_entry_t *)DMPDPphys;
806 for (i = 0; i < ndm1g; i++) {
807 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
808 /* Preset PG_M and PG_A because demotion expects it. */
809 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
812 for (j = 0; i < ndmpdp; i++, j++) {
813 pdp_p[i] = DMPDphys + ptoa(j);
814 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
817 /* And recursively map PML4 to itself in order to get PTmap */
818 p4_p = (pml4_entry_t *)KPML4phys;
819 p4_p[PML4PML4I] = KPML4phys;
820 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
822 /* Connect the Direct Map slot(s) up to the PML4. */
823 for (i = 0; i < ndmpdpphys; i++) {
824 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
825 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
828 /* Connect the KVA slots up to the PML4 */
829 for (i = 0; i < NKPML4E; i++) {
830 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
831 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
836 * Bootstrap the system enough to run with virtual memory.
838 * On amd64 this is called after mapping has already been enabled
839 * and just syncs the pmap module with what has already been done.
840 * [We can't call it easily with mapping off since the kernel is not
841 * mapped with PA == VA, hence we would have to relocate every address
842 * from the linked base (virtual) address "KERNBASE" to the actual
843 * (physical) address starting relative to 0]
846 pmap_bootstrap(vm_paddr_t *firstaddr)
853 * Create an initial set of page tables to run the kernel in.
855 create_pagetables(firstaddr);
858 * Add a physical memory segment (vm_phys_seg) corresponding to the
859 * preallocated kernel page table pages so that vm_page structures
860 * representing these pages will be created. The vm_page structures
861 * are required for promotion of the corresponding kernel virtual
862 * addresses to superpage mappings.
864 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
866 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
867 virtual_avail = pmap_kmem_choose(virtual_avail);
869 virtual_end = VM_MAX_KERNEL_ADDRESS;
872 /* XXX do %cr0 as well */
873 load_cr4(rcr4() | CR4_PGE);
875 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
876 load_cr4(rcr4() | CR4_SMEP);
879 * Initialize the kernel pmap (which is statically allocated).
881 PMAP_LOCK_INIT(kernel_pmap);
882 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
883 kernel_pmap->pm_cr3 = KPML4phys;
884 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
885 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
886 kernel_pmap->pm_flags = pmap_flags;
889 * Initialize the global pv list lock.
891 rw_init(&pvh_global_lock, "pmap pv global");
894 * Reserve some special page table entries/VA space for temporary
897 #define SYSMAP(c, p, v, n) \
898 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
904 * Crashdump maps. The first page is reused as CMAP1 for the
907 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
908 CADDR1 = crashdumpmap;
912 /* Initialize the PAT MSR. */
915 /* Initialize TLB Context Id. */
916 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
917 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
918 /* Check for INVPCID support */
919 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
921 for (i = 0; i < MAXCPU; i++) {
922 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
923 kernel_pmap->pm_pcids[i].pm_gen = 1;
925 __pcpu[0].pc_pcid_next = PMAP_PCID_KERN + 1;
926 __pcpu[0].pc_pcid_gen = 1;
928 * pcpu area for APs is zeroed during AP startup.
929 * pc_pcid_next and pc_pcid_gen are initialized by AP
932 load_cr4(rcr4() | CR4_PCIDE);
934 pmap_pcid_enabled = 0;
944 int pat_table[PAT_INDEX_SIZE];
949 /* Bail if this CPU doesn't implement PAT. */
950 if ((cpu_feature & CPUID_PAT) == 0)
953 /* Set default PAT index table. */
954 for (i = 0; i < PAT_INDEX_SIZE; i++)
956 pat_table[PAT_WRITE_BACK] = 0;
957 pat_table[PAT_WRITE_THROUGH] = 1;
958 pat_table[PAT_UNCACHEABLE] = 3;
959 pat_table[PAT_WRITE_COMBINING] = 3;
960 pat_table[PAT_WRITE_PROTECTED] = 3;
961 pat_table[PAT_UNCACHED] = 3;
963 /* Initialize default PAT entries. */
964 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
965 PAT_VALUE(1, PAT_WRITE_THROUGH) |
966 PAT_VALUE(2, PAT_UNCACHED) |
967 PAT_VALUE(3, PAT_UNCACHEABLE) |
968 PAT_VALUE(4, PAT_WRITE_BACK) |
969 PAT_VALUE(5, PAT_WRITE_THROUGH) |
970 PAT_VALUE(6, PAT_UNCACHED) |
971 PAT_VALUE(7, PAT_UNCACHEABLE);
975 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
976 * Program 5 and 6 as WP and WC.
977 * Leave 4 and 7 as WB and UC.
979 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
980 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
981 PAT_VALUE(6, PAT_WRITE_COMBINING);
982 pat_table[PAT_UNCACHED] = 2;
983 pat_table[PAT_WRITE_PROTECTED] = 5;
984 pat_table[PAT_WRITE_COMBINING] = 6;
987 * Just replace PAT Index 2 with WC instead of UC-.
989 pat_msr &= ~PAT_MASK(2);
990 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
991 pat_table[PAT_WRITE_COMBINING] = 2;
996 load_cr4(cr4 & ~CR4_PGE);
998 /* Disable caches (CD = 1, NW = 0). */
1000 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1002 /* Flushes caches and TLBs. */
1006 /* Update PAT and index table. */
1007 wrmsr(MSR_PAT, pat_msr);
1008 for (i = 0; i < PAT_INDEX_SIZE; i++)
1009 pat_index[i] = pat_table[i];
1011 /* Flush caches and TLBs again. */
1015 /* Restore caches and PGE. */
1021 * Initialize a vm_page's machine-dependent fields.
1024 pmap_page_init(vm_page_t m)
1027 TAILQ_INIT(&m->md.pv_list);
1028 m->md.pat_mode = PAT_WRITE_BACK;
1032 * Initialize the pmap module.
1033 * Called by vm_init, to initialize any structures that the pmap
1034 * system needs to map virtual memory.
1039 struct pmap_preinit_mapping *ppim;
1042 int error, i, pv_npg;
1045 * Initialize the vm page array entries for the kernel pmap's
1048 for (i = 0; i < nkpt; i++) {
1049 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1050 KASSERT(mpte >= vm_page_array &&
1051 mpte < &vm_page_array[vm_page_array_size],
1052 ("pmap_init: page table page is out of range"));
1053 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1054 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1058 * If the kernel is running on a virtual machine, then it must assume
1059 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1060 * be prepared for the hypervisor changing the vendor and family that
1061 * are reported by CPUID. Consequently, the workaround for AMD Family
1062 * 10h Erratum 383 is enabled if the processor's feature set does not
1063 * include at least one feature that is only supported by older Intel
1064 * or newer AMD processors.
1066 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1067 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1068 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1070 workaround_erratum383 = 1;
1073 * Are large page mappings enabled?
1075 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1076 if (pg_ps_enabled) {
1077 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1078 ("pmap_init: can't assign to pagesizes[1]"));
1079 pagesizes[1] = NBPDR;
1083 * Initialize the pv chunk list mutex.
1085 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1088 * Initialize the pool of pv list locks.
1090 for (i = 0; i < NPV_LIST_LOCKS; i++)
1091 rw_init(&pv_list_locks[i], "pmap pv list");
1094 * Calculate the size of the pv head table for superpages.
1096 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1099 * Allocate memory for the pv head table for superpages.
1101 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1103 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1105 for (i = 0; i < pv_npg; i++)
1106 TAILQ_INIT(&pv_table[i].pv_list);
1108 pmap_initialized = 1;
1109 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1110 ppim = pmap_preinit_mapping + i;
1113 /* Make the direct map consistent */
1114 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1115 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1116 ppim->sz, ppim->mode);
1120 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1121 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1124 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1125 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1126 (vmem_addr_t *)&qframe);
1128 panic("qframe allocation failed");
1131 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1132 "2MB page mapping counters");
1134 static u_long pmap_pde_demotions;
1135 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1136 &pmap_pde_demotions, 0, "2MB page demotions");
1138 static u_long pmap_pde_mappings;
1139 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1140 &pmap_pde_mappings, 0, "2MB page mappings");
1142 static u_long pmap_pde_p_failures;
1143 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1144 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1146 static u_long pmap_pde_promotions;
1147 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1148 &pmap_pde_promotions, 0, "2MB page promotions");
1150 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1151 "1GB page mapping counters");
1153 static u_long pmap_pdpe_demotions;
1154 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1155 &pmap_pdpe_demotions, 0, "1GB page demotions");
1157 /***************************************************
1158 * Low level helper routines.....
1159 ***************************************************/
1162 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1164 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1166 switch (pmap->pm_type) {
1169 /* Verify that both PAT bits are not set at the same time */
1170 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1171 ("Invalid PAT bits in entry %#lx", entry));
1173 /* Swap the PAT bits if one of them is set */
1174 if ((entry & x86_pat_bits) != 0)
1175 entry ^= x86_pat_bits;
1179 * Nothing to do - the memory attributes are represented
1180 * the same way for regular pages and superpages.
1184 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1191 * Determine the appropriate bits to set in a PTE or PDE for a specified
1195 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1197 int cache_bits, pat_flag, pat_idx;
1199 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1200 panic("Unknown caching mode %d\n", mode);
1202 switch (pmap->pm_type) {
1205 /* The PAT bit is different for PTE's and PDE's. */
1206 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1208 /* Map the caching mode to a PAT index. */
1209 pat_idx = pat_index[mode];
1211 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1214 cache_bits |= pat_flag;
1216 cache_bits |= PG_NC_PCD;
1218 cache_bits |= PG_NC_PWT;
1222 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1226 panic("unsupported pmap type %d", pmap->pm_type);
1229 return (cache_bits);
1233 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1237 switch (pmap->pm_type) {
1240 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1243 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1246 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1252 static __inline boolean_t
1253 pmap_ps_enabled(pmap_t pmap)
1256 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1260 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1263 switch (pmap->pm_type) {
1270 * This is a little bogus since the generation number is
1271 * supposed to be bumped up when a region of the address
1272 * space is invalidated in the page tables.
1274 * In this case the old PDE entry is valid but yet we want
1275 * to make sure that any mappings using the old entry are
1276 * invalidated in the TLB.
1278 * The reason this works as expected is because we rendezvous
1279 * "all" host cpus and force any vcpu context to exit as a
1282 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1285 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1287 pde_store(pde, newpde);
1291 * After changing the page size for the specified virtual address in the page
1292 * table, flush the corresponding entries from the processor's TLB. Only the
1293 * calling processor's TLB is affected.
1295 * The calling thread must be pinned to a processor.
1298 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1302 if (pmap_type_guest(pmap))
1305 KASSERT(pmap->pm_type == PT_X86,
1306 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1308 PG_G = pmap_global_bit(pmap);
1310 if ((newpde & PG_PS) == 0)
1311 /* Demotion: flush a specific 2MB page mapping. */
1313 else if ((newpde & PG_G) == 0)
1315 * Promotion: flush every 4KB page mapping from the TLB
1316 * because there are too many to flush individually.
1321 * Promotion: flush every 4KB page mapping from the TLB,
1322 * including any global (PG_G) mappings.
1330 * For SMP, these functions have to use the IPI mechanism for coherence.
1332 * N.B.: Before calling any of the following TLB invalidation functions,
1333 * the calling processor must ensure that all stores updating a non-
1334 * kernel page table are globally performed. Otherwise, another
1335 * processor could cache an old, pre-update entry without being
1336 * invalidated. This can happen one of two ways: (1) The pmap becomes
1337 * active on another processor after its pm_active field is checked by
1338 * one of the following functions but before a store updating the page
1339 * table is globally performed. (2) The pmap becomes active on another
1340 * processor before its pm_active field is checked but due to
1341 * speculative loads one of the following functions stills reads the
1342 * pmap as inactive on the other processor.
1344 * The kernel page table is exempt because its pm_active field is
1345 * immutable. The kernel page table is always active on every
1350 * Interrupt the cpus that are executing in the guest context.
1351 * This will force the vcpu to exit and the cached EPT mappings
1352 * will be invalidated by the host before the next vmresume.
1354 static __inline void
1355 pmap_invalidate_ept(pmap_t pmap)
1360 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1361 ("pmap_invalidate_ept: absurd pm_active"));
1364 * The TLB mappings associated with a vcpu context are not
1365 * flushed each time a different vcpu is chosen to execute.
1367 * This is in contrast with a process's vtop mappings that
1368 * are flushed from the TLB on each context switch.
1370 * Therefore we need to do more than just a TLB shootdown on
1371 * the active cpus in 'pmap->pm_active'. To do this we keep
1372 * track of the number of invalidations performed on this pmap.
1374 * Each vcpu keeps a cache of this counter and compares it
1375 * just before a vmresume. If the counter is out-of-date an
1376 * invept will be done to flush stale mappings from the TLB.
1378 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1381 * Force the vcpu to exit and trap back into the hypervisor.
1383 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1384 ipi_selected(pmap->pm_active, ipinum);
1389 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1394 if (pmap_type_guest(pmap)) {
1395 pmap_invalidate_ept(pmap);
1399 KASSERT(pmap->pm_type == PT_X86,
1400 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1403 if (pmap == kernel_pmap) {
1407 cpuid = PCPU_GET(cpuid);
1408 if (pmap == PCPU_GET(curpmap))
1410 else if (pmap_pcid_enabled)
1411 pmap->pm_pcids[cpuid].pm_gen = 0;
1412 if (pmap_pcid_enabled) {
1415 pmap->pm_pcids[i].pm_gen = 0;
1418 mask = &pmap->pm_active;
1420 smp_masked_invlpg(*mask, va);
1424 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1425 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1428 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1434 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1435 pmap_invalidate_all(pmap);
1439 if (pmap_type_guest(pmap)) {
1440 pmap_invalidate_ept(pmap);
1444 KASSERT(pmap->pm_type == PT_X86,
1445 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1448 cpuid = PCPU_GET(cpuid);
1449 if (pmap == kernel_pmap) {
1450 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1454 if (pmap == PCPU_GET(curpmap)) {
1455 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1457 } else if (pmap_pcid_enabled) {
1458 pmap->pm_pcids[cpuid].pm_gen = 0;
1460 if (pmap_pcid_enabled) {
1463 pmap->pm_pcids[i].pm_gen = 0;
1466 mask = &pmap->pm_active;
1468 smp_masked_invlpg_range(*mask, sva, eva);
1473 pmap_invalidate_all(pmap_t pmap)
1476 struct invpcid_descr d;
1479 if (pmap_type_guest(pmap)) {
1480 pmap_invalidate_ept(pmap);
1484 KASSERT(pmap->pm_type == PT_X86,
1485 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1488 if (pmap == kernel_pmap) {
1489 if (pmap_pcid_enabled && invpcid_works) {
1490 bzero(&d, sizeof(d));
1491 invpcid(&d, INVPCID_CTXGLOB);
1497 cpuid = PCPU_GET(cpuid);
1498 if (pmap == PCPU_GET(curpmap)) {
1499 if (pmap_pcid_enabled) {
1500 if (invpcid_works) {
1501 d.pcid = pmap->pm_pcids[cpuid].pm_pcid;
1504 invpcid(&d, INVPCID_CTX);
1506 load_cr3(pmap->pm_cr3 | pmap->pm_pcids
1507 [PCPU_GET(cpuid)].pm_pcid);
1512 } else if (pmap_pcid_enabled) {
1513 pmap->pm_pcids[cpuid].pm_gen = 0;
1515 if (pmap_pcid_enabled) {
1518 pmap->pm_pcids[i].pm_gen = 0;
1521 mask = &pmap->pm_active;
1523 smp_masked_invltlb(*mask, pmap);
1528 pmap_invalidate_cache(void)
1538 cpuset_t invalidate; /* processors that invalidate their TLB */
1543 u_int store; /* processor that updates the PDE */
1547 pmap_update_pde_action(void *arg)
1549 struct pde_action *act = arg;
1551 if (act->store == PCPU_GET(cpuid))
1552 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1556 pmap_update_pde_teardown(void *arg)
1558 struct pde_action *act = arg;
1560 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1561 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1565 * Change the page size for the specified virtual address in a way that
1566 * prevents any possibility of the TLB ever having two entries that map the
1567 * same virtual address using different page sizes. This is the recommended
1568 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1569 * machine check exception for a TLB state that is improperly diagnosed as a
1573 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1575 struct pde_action act;
1576 cpuset_t active, other_cpus;
1580 cpuid = PCPU_GET(cpuid);
1581 other_cpus = all_cpus;
1582 CPU_CLR(cpuid, &other_cpus);
1583 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1586 active = pmap->pm_active;
1588 if (CPU_OVERLAP(&active, &other_cpus)) {
1590 act.invalidate = active;
1594 act.newpde = newpde;
1595 CPU_SET(cpuid, &active);
1596 smp_rendezvous_cpus(active,
1597 smp_no_rendevous_barrier, pmap_update_pde_action,
1598 pmap_update_pde_teardown, &act);
1600 pmap_update_pde_store(pmap, pde, newpde);
1601 if (CPU_ISSET(cpuid, &active))
1602 pmap_update_pde_invalidate(pmap, va, newpde);
1608 * Normal, non-SMP, invalidation functions.
1611 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1614 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1618 KASSERT(pmap->pm_type == PT_X86,
1619 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
1621 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
1623 else if (pmap_pcid_enabled)
1624 pmap->pm_pcids[0].pm_gen = 0;
1628 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1632 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1636 KASSERT(pmap->pm_type == PT_X86,
1637 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
1639 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
1640 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1642 } else if (pmap_pcid_enabled) {
1643 pmap->pm_pcids[0].pm_gen = 0;
1648 pmap_invalidate_all(pmap_t pmap)
1650 struct invpcid_descr d;
1652 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1656 KASSERT(pmap->pm_type == PT_X86,
1657 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
1659 if (pmap == kernel_pmap) {
1660 if (pmap_pcid_enabled && invpcid_works) {
1661 bzero(&d, sizeof(d));
1662 invpcid(&d, INVPCID_CTXGLOB);
1666 } else if (pmap == PCPU_GET(curpmap)) {
1667 if (pmap_pcid_enabled) {
1668 if (invpcid_works) {
1669 d.pcid = pmap->pm_pcids[0].pm_pcid;
1672 invpcid(&d, INVPCID_CTX);
1674 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[0].
1680 } else if (pmap_pcid_enabled) {
1681 pmap->pm_pcids[0].pm_gen = 0;
1686 pmap_invalidate_cache(void)
1693 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1696 pmap_update_pde_store(pmap, pde, newpde);
1697 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
1698 pmap_update_pde_invalidate(pmap, va, newpde);
1700 pmap->pm_pcids[0].pm_gen = 0;
1704 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1707 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1711 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1713 KASSERT((sva & PAGE_MASK) == 0,
1714 ("pmap_invalidate_cache_range: sva not page-aligned"));
1715 KASSERT((eva & PAGE_MASK) == 0,
1716 ("pmap_invalidate_cache_range: eva not page-aligned"));
1719 if ((cpu_feature & CPUID_SS) != 0 && !force)
1720 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1721 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1722 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1724 * XXX: Some CPUs fault, hang, or trash the local APIC
1725 * registers if we use CLFLUSH on the local APIC
1726 * range. The local APIC is always uncached, so we
1727 * don't need to flush for that range anyway.
1729 if (pmap_kextract(sva) == lapic_paddr)
1733 * Otherwise, do per-cache line flush. Use the mfence
1734 * instruction to insure that previous stores are
1735 * included in the write-back. The processor
1736 * propagates flush to other processors in the cache
1740 for (; sva < eva; sva += cpu_clflush_line_size)
1743 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1744 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1745 if (pmap_kextract(sva) == lapic_paddr)
1748 * Writes are ordered by CLFLUSH on Intel CPUs.
1750 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1752 for (; sva < eva; sva += cpu_clflush_line_size)
1754 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1759 * No targeted cache flush methods are supported by CPU,
1760 * or the supplied range is bigger than 2MB.
1761 * Globally invalidate cache.
1763 pmap_invalidate_cache();
1768 * Remove the specified set of pages from the data and instruction caches.
1770 * In contrast to pmap_invalidate_cache_range(), this function does not
1771 * rely on the CPU's self-snoop feature, because it is intended for use
1772 * when moving pages into a different cache domain.
1775 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1777 vm_offset_t daddr, eva;
1781 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
1782 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1783 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
1784 pmap_invalidate_cache();
1786 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
1788 for (i = 0; i < count; i++) {
1789 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1790 eva = daddr + PAGE_SIZE;
1791 for (; daddr < eva; daddr += cpu_clflush_line_size) {
1798 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
1804 * Routine: pmap_extract
1806 * Extract the physical page address associated
1807 * with the given map/virtual_address pair.
1810 pmap_extract(pmap_t pmap, vm_offset_t va)
1814 pt_entry_t *pte, PG_V;
1818 PG_V = pmap_valid_bit(pmap);
1820 pdpe = pmap_pdpe(pmap, va);
1821 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1822 if ((*pdpe & PG_PS) != 0)
1823 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1825 pde = pmap_pdpe_to_pde(pdpe, va);
1826 if ((*pde & PG_V) != 0) {
1827 if ((*pde & PG_PS) != 0) {
1828 pa = (*pde & PG_PS_FRAME) |
1831 pte = pmap_pde_to_pte(pde, va);
1832 pa = (*pte & PG_FRAME) |
1843 * Routine: pmap_extract_and_hold
1845 * Atomically extract and hold the physical page
1846 * with the given pmap and virtual address pair
1847 * if that mapping permits the given protection.
1850 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1852 pd_entry_t pde, *pdep;
1853 pt_entry_t pte, PG_RW, PG_V;
1859 PG_RW = pmap_rw_bit(pmap);
1860 PG_V = pmap_valid_bit(pmap);
1863 pdep = pmap_pde(pmap, va);
1864 if (pdep != NULL && (pde = *pdep)) {
1866 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1867 if (vm_page_pa_tryrelock(pmap, (pde &
1868 PG_PS_FRAME) | (va & PDRMASK), &pa))
1870 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1875 pte = *pmap_pde_to_pte(pdep, va);
1877 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1878 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1881 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1892 pmap_kextract(vm_offset_t va)
1897 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1898 pa = DMAP_TO_PHYS(va);
1902 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1905 * Beware of a concurrent promotion that changes the
1906 * PDE at this point! For example, vtopte() must not
1907 * be used to access the PTE because it would use the
1908 * new PDE. It is, however, safe to use the old PDE
1909 * because the page table page is preserved by the
1912 pa = *pmap_pde_to_pte(&pde, va);
1913 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1919 /***************************************************
1920 * Low level mapping routines.....
1921 ***************************************************/
1924 * Add a wired page to the kva.
1925 * Note: not SMP coherent.
1928 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1933 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1936 static __inline void
1937 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1943 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1944 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1948 * Remove a page from the kernel pagetables.
1949 * Note: not SMP coherent.
1952 pmap_kremove(vm_offset_t va)
1961 * Used to map a range of physical addresses into kernel
1962 * virtual address space.
1964 * The value passed in '*virt' is a suggested virtual address for
1965 * the mapping. Architectures which can support a direct-mapped
1966 * physical to virtual region can return the appropriate address
1967 * within that region, leaving '*virt' unchanged. Other
1968 * architectures should map the pages starting at '*virt' and
1969 * update '*virt' with the first usable address after the mapped
1973 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1975 return PHYS_TO_DMAP(start);
1980 * Add a list of wired pages to the kva
1981 * this routine is only used for temporary
1982 * kernel mappings that do not need to have
1983 * page modification or references recorded.
1984 * Note that old mappings are simply written
1985 * over. The page *must* be wired.
1986 * Note: SMP coherent. Uses a ranged shootdown IPI.
1989 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1991 pt_entry_t *endpte, oldpte, pa, *pte;
1997 endpte = pte + count;
1998 while (pte < endpte) {
2000 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2001 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2002 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2004 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
2008 if (__predict_false((oldpte & X86_PG_V) != 0))
2009 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2014 * This routine tears out page mappings from the
2015 * kernel -- it is meant only for temporary mappings.
2016 * Note: SMP coherent. Uses a ranged shootdown IPI.
2019 pmap_qremove(vm_offset_t sva, int count)
2024 while (count-- > 0) {
2025 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2029 pmap_invalidate_range(kernel_pmap, sva, va);
2032 /***************************************************
2033 * Page table page management routines.....
2034 ***************************************************/
2035 static __inline void
2036 pmap_free_zero_pages(struct spglist *free)
2040 while ((m = SLIST_FIRST(free)) != NULL) {
2041 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2042 /* Preserve the page's PG_ZERO setting. */
2043 vm_page_free_toq(m);
2048 * Schedule the specified unused page table page to be freed. Specifically,
2049 * add the page to the specified list of pages that will be released to the
2050 * physical memory manager after the TLB has been updated.
2052 static __inline void
2053 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2054 boolean_t set_PG_ZERO)
2058 m->flags |= PG_ZERO;
2060 m->flags &= ~PG_ZERO;
2061 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2065 * Inserts the specified page table page into the specified pmap's collection
2066 * of idle page table pages. Each of a pmap's page table pages is responsible
2067 * for mapping a distinct range of virtual addresses. The pmap's collection is
2068 * ordered by this virtual address range.
2071 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2074 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2075 return (vm_radix_insert(&pmap->pm_root, mpte));
2079 * Looks for a page table page mapping the specified virtual address in the
2080 * specified pmap's collection of idle page table pages. Returns NULL if there
2081 * is no page table page corresponding to the specified virtual address.
2083 static __inline vm_page_t
2084 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2087 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2088 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2092 * Removes the specified page table page from the specified pmap's collection
2093 * of idle page table pages. The specified page table page must be a member of
2094 * the pmap's collection.
2096 static __inline void
2097 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2100 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2101 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2105 * Decrements a page table page's wire count, which is used to record the
2106 * number of valid page table entries within the page. If the wire count
2107 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2108 * page table page was unmapped and FALSE otherwise.
2110 static inline boolean_t
2111 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2115 if (m->wire_count == 0) {
2116 _pmap_unwire_ptp(pmap, va, m, free);
2123 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2126 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2128 * unmap the page table page
2130 if (m->pindex >= (NUPDE + NUPDPE)) {
2133 pml4 = pmap_pml4e(pmap, va);
2135 } else if (m->pindex >= NUPDE) {
2138 pdp = pmap_pdpe(pmap, va);
2143 pd = pmap_pde(pmap, va);
2146 pmap_resident_count_dec(pmap, 1);
2147 if (m->pindex < NUPDE) {
2148 /* We just released a PT, unhold the matching PD */
2151 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2152 pmap_unwire_ptp(pmap, va, pdpg, free);
2154 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2155 /* We just released a PD, unhold the matching PDP */
2158 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2159 pmap_unwire_ptp(pmap, va, pdppg, free);
2163 * This is a release store so that the ordinary store unmapping
2164 * the page table page is globally performed before TLB shoot-
2167 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2170 * Put page on a list so that it is released after
2171 * *ALL* TLB shootdown is done
2173 pmap_add_delayed_free_list(m, free, TRUE);
2177 * After removing a page table entry, this routine is used to
2178 * conditionally free the page, and manage the hold/wire counts.
2181 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2182 struct spglist *free)
2186 if (va >= VM_MAXUSER_ADDRESS)
2188 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2189 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2190 return (pmap_unwire_ptp(pmap, va, mpte, free));
2194 pmap_pinit0(pmap_t pmap)
2198 PMAP_LOCK_INIT(pmap);
2199 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2200 pmap->pm_cr3 = KPML4phys;
2201 pmap->pm_root.rt_root = 0;
2202 CPU_ZERO(&pmap->pm_active);
2203 TAILQ_INIT(&pmap->pm_pvchunk);
2204 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2205 pmap->pm_flags = pmap_flags;
2207 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2208 pmap->pm_pcids[i].pm_gen = 0;
2210 PCPU_SET(curpmap, kernel_pmap);
2211 pmap_activate(curthread);
2212 CPU_FILL(&kernel_pmap->pm_active);
2216 * Initialize a preallocated and zeroed pmap structure,
2217 * such as one in a vmspace structure.
2220 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2223 vm_paddr_t pml4phys;
2227 * allocate the page directory page
2229 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2230 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2233 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2234 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2236 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2237 pmap->pm_pcids[i].pm_gen = 0;
2239 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2241 if ((pml4pg->flags & PG_ZERO) == 0)
2242 pagezero(pmap->pm_pml4);
2245 * Do not install the host kernel mappings in the nested page
2246 * tables. These mappings are meaningless in the guest physical
2249 if ((pmap->pm_type = pm_type) == PT_X86) {
2250 pmap->pm_cr3 = pml4phys;
2252 /* Wire in kernel global address entries. */
2253 for (i = 0; i < NKPML4E; i++) {
2254 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2255 X86_PG_RW | X86_PG_V | PG_U;
2257 for (i = 0; i < ndmpdpphys; i++) {
2258 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2259 X86_PG_RW | X86_PG_V | PG_U;
2262 /* install self-referential address mapping entry(s) */
2263 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2264 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2267 pmap->pm_root.rt_root = 0;
2268 CPU_ZERO(&pmap->pm_active);
2269 TAILQ_INIT(&pmap->pm_pvchunk);
2270 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2271 pmap->pm_flags = flags;
2272 pmap->pm_eptgen = 0;
2278 pmap_pinit(pmap_t pmap)
2281 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2285 * This routine is called if the desired page table page does not exist.
2287 * If page table page allocation fails, this routine may sleep before
2288 * returning NULL. It sleeps only if a lock pointer was given.
2290 * Note: If a page allocation fails at page table level two or three,
2291 * one or two pages may be held during the wait, only to be released
2292 * afterwards. This conservative approach is easily argued to avoid
2296 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2298 vm_page_t m, pdppg, pdpg;
2299 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2301 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2303 PG_A = pmap_accessed_bit(pmap);
2304 PG_M = pmap_modified_bit(pmap);
2305 PG_V = pmap_valid_bit(pmap);
2306 PG_RW = pmap_rw_bit(pmap);
2309 * Allocate a page table page.
2311 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2312 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2313 if (lockp != NULL) {
2314 RELEASE_PV_LIST_LOCK(lockp);
2316 rw_runlock(&pvh_global_lock);
2318 rw_rlock(&pvh_global_lock);
2323 * Indicate the need to retry. While waiting, the page table
2324 * page may have been allocated.
2328 if ((m->flags & PG_ZERO) == 0)
2332 * Map the pagetable page into the process address space, if
2333 * it isn't already there.
2336 if (ptepindex >= (NUPDE + NUPDPE)) {
2338 vm_pindex_t pml4index;
2340 /* Wire up a new PDPE page */
2341 pml4index = ptepindex - (NUPDE + NUPDPE);
2342 pml4 = &pmap->pm_pml4[pml4index];
2343 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2345 } else if (ptepindex >= NUPDE) {
2346 vm_pindex_t pml4index;
2347 vm_pindex_t pdpindex;
2351 /* Wire up a new PDE page */
2352 pdpindex = ptepindex - NUPDE;
2353 pml4index = pdpindex >> NPML4EPGSHIFT;
2355 pml4 = &pmap->pm_pml4[pml4index];
2356 if ((*pml4 & PG_V) == 0) {
2357 /* Have to allocate a new pdp, recurse */
2358 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2361 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2362 vm_page_free_zero(m);
2366 /* Add reference to pdp page */
2367 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2368 pdppg->wire_count++;
2370 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2372 /* Now find the pdp page */
2373 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2374 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2377 vm_pindex_t pml4index;
2378 vm_pindex_t pdpindex;
2383 /* Wire up a new PTE page */
2384 pdpindex = ptepindex >> NPDPEPGSHIFT;
2385 pml4index = pdpindex >> NPML4EPGSHIFT;
2387 /* First, find the pdp and check that its valid. */
2388 pml4 = &pmap->pm_pml4[pml4index];
2389 if ((*pml4 & PG_V) == 0) {
2390 /* Have to allocate a new pd, recurse */
2391 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2394 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2395 vm_page_free_zero(m);
2398 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2399 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2401 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2402 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2403 if ((*pdp & PG_V) == 0) {
2404 /* Have to allocate a new pd, recurse */
2405 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2408 atomic_subtract_int(&vm_cnt.v_wire_count,
2410 vm_page_free_zero(m);
2414 /* Add reference to the pd page */
2415 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2419 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2421 /* Now we know where the page directory page is */
2422 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2423 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2426 pmap_resident_count_inc(pmap, 1);
2432 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2434 vm_pindex_t pdpindex, ptepindex;
2435 pdp_entry_t *pdpe, PG_V;
2438 PG_V = pmap_valid_bit(pmap);
2441 pdpe = pmap_pdpe(pmap, va);
2442 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2443 /* Add a reference to the pd page. */
2444 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2447 /* Allocate a pd page. */
2448 ptepindex = pmap_pde_pindex(va);
2449 pdpindex = ptepindex >> NPDPEPGSHIFT;
2450 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2451 if (pdpg == NULL && lockp != NULL)
2458 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2460 vm_pindex_t ptepindex;
2461 pd_entry_t *pd, PG_V;
2464 PG_V = pmap_valid_bit(pmap);
2467 * Calculate pagetable page index
2469 ptepindex = pmap_pde_pindex(va);
2472 * Get the page directory entry
2474 pd = pmap_pde(pmap, va);
2477 * This supports switching from a 2MB page to a
2480 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2481 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2483 * Invalidation of the 2MB page mapping may have caused
2484 * the deallocation of the underlying PD page.
2491 * If the page table page is mapped, we just increment the
2492 * hold count, and activate it.
2494 if (pd != NULL && (*pd & PG_V) != 0) {
2495 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2499 * Here if the pte page isn't mapped, or if it has been
2502 m = _pmap_allocpte(pmap, ptepindex, lockp);
2503 if (m == NULL && lockp != NULL)
2510 /***************************************************
2511 * Pmap allocation/deallocation routines.
2512 ***************************************************/
2515 * Release any resources held by the given physical map.
2516 * Called when a pmap initialized by pmap_pinit is being released.
2517 * Should only be called if the map contains no valid mappings.
2520 pmap_release(pmap_t pmap)
2525 KASSERT(pmap->pm_stats.resident_count == 0,
2526 ("pmap_release: pmap resident count %ld != 0",
2527 pmap->pm_stats.resident_count));
2528 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2529 ("pmap_release: pmap has reserved page table page(s)"));
2530 KASSERT(CPU_EMPTY(&pmap->pm_active),
2531 ("releasing active pmap %p", pmap));
2533 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2535 for (i = 0; i < NKPML4E; i++) /* KVA */
2536 pmap->pm_pml4[KPML4BASE + i] = 0;
2537 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2538 pmap->pm_pml4[DMPML4I + i] = 0;
2539 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2542 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2543 vm_page_free_zero(m);
2547 kvm_size(SYSCTL_HANDLER_ARGS)
2549 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2551 return sysctl_handle_long(oidp, &ksize, 0, req);
2553 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2554 0, 0, kvm_size, "LU", "Size of KVM");
2557 kvm_free(SYSCTL_HANDLER_ARGS)
2559 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2561 return sysctl_handle_long(oidp, &kfree, 0, req);
2563 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2564 0, 0, kvm_free, "LU", "Amount of KVM free");
2567 * grow the number of kernel page table entries, if needed
2570 pmap_growkernel(vm_offset_t addr)
2574 pd_entry_t *pde, newpdir;
2577 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2580 * Return if "addr" is within the range of kernel page table pages
2581 * that were preallocated during pmap bootstrap. Moreover, leave
2582 * "kernel_vm_end" and the kernel page table as they were.
2584 * The correctness of this action is based on the following
2585 * argument: vm_map_insert() allocates contiguous ranges of the
2586 * kernel virtual address space. It calls this function if a range
2587 * ends after "kernel_vm_end". If the kernel is mapped between
2588 * "kernel_vm_end" and "addr", then the range cannot begin at
2589 * "kernel_vm_end". In fact, its beginning address cannot be less
2590 * than the kernel. Thus, there is no immediate need to allocate
2591 * any new kernel page table pages between "kernel_vm_end" and
2594 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2597 addr = roundup2(addr, NBPDR);
2598 if (addr - 1 >= kernel_map->max_offset)
2599 addr = kernel_map->max_offset;
2600 while (kernel_vm_end < addr) {
2601 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2602 if ((*pdpe & X86_PG_V) == 0) {
2603 /* We need a new PDP entry */
2604 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2605 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2606 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2608 panic("pmap_growkernel: no memory to grow kernel");
2609 if ((nkpg->flags & PG_ZERO) == 0)
2610 pmap_zero_page(nkpg);
2611 paddr = VM_PAGE_TO_PHYS(nkpg);
2612 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2613 X86_PG_A | X86_PG_M);
2614 continue; /* try again */
2616 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2617 if ((*pde & X86_PG_V) != 0) {
2618 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2619 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2620 kernel_vm_end = kernel_map->max_offset;
2626 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2627 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2630 panic("pmap_growkernel: no memory to grow kernel");
2631 if ((nkpg->flags & PG_ZERO) == 0)
2632 pmap_zero_page(nkpg);
2633 paddr = VM_PAGE_TO_PHYS(nkpg);
2634 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2635 pde_store(pde, newpdir);
2637 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2638 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2639 kernel_vm_end = kernel_map->max_offset;
2646 /***************************************************
2647 * page management routines.
2648 ***************************************************/
2650 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2651 CTASSERT(_NPCM == 3);
2652 CTASSERT(_NPCPV == 168);
2654 static __inline struct pv_chunk *
2655 pv_to_chunk(pv_entry_t pv)
2658 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2661 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2663 #define PC_FREE0 0xfffffffffffffffful
2664 #define PC_FREE1 0xfffffffffffffffful
2665 #define PC_FREE2 0x000000fffffffffful
2667 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2670 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2672 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2673 "Current number of pv entry chunks");
2674 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2675 "Current number of pv entry chunks allocated");
2676 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2677 "Current number of pv entry chunks frees");
2678 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2679 "Number of times tried to get a chunk page but failed.");
2681 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2682 static int pv_entry_spare;
2684 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2685 "Current number of pv entry frees");
2686 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2687 "Current number of pv entry allocs");
2688 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2689 "Current number of pv entries");
2690 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2691 "Current number of spare pv entries");
2695 * We are in a serious low memory condition. Resort to
2696 * drastic measures to free some pages so we can allocate
2697 * another pv entry chunk.
2699 * Returns NULL if PV entries were reclaimed from the specified pmap.
2701 * We do not, however, unmap 2mpages because subsequent accesses will
2702 * allocate per-page pv entries until repromotion occurs, thereby
2703 * exacerbating the shortage of free pv entries.
2706 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2708 struct pch new_tail;
2709 struct pv_chunk *pc;
2710 struct md_page *pvh;
2713 pt_entry_t *pte, tpte;
2714 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2718 struct spglist free;
2720 int bit, field, freed;
2722 rw_assert(&pvh_global_lock, RA_LOCKED);
2723 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2724 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2727 PG_G = PG_A = PG_M = PG_RW = 0;
2729 TAILQ_INIT(&new_tail);
2730 mtx_lock(&pv_chunks_mutex);
2731 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2732 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2733 mtx_unlock(&pv_chunks_mutex);
2734 if (pmap != pc->pc_pmap) {
2736 pmap_invalidate_all(pmap);
2737 if (pmap != locked_pmap)
2741 /* Avoid deadlock and lock recursion. */
2742 if (pmap > locked_pmap) {
2743 RELEASE_PV_LIST_LOCK(lockp);
2745 } else if (pmap != locked_pmap &&
2746 !PMAP_TRYLOCK(pmap)) {
2748 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2749 mtx_lock(&pv_chunks_mutex);
2752 PG_G = pmap_global_bit(pmap);
2753 PG_A = pmap_accessed_bit(pmap);
2754 PG_M = pmap_modified_bit(pmap);
2755 PG_RW = pmap_rw_bit(pmap);
2759 * Destroy every non-wired, 4 KB page mapping in the chunk.
2762 for (field = 0; field < _NPCM; field++) {
2763 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2764 inuse != 0; inuse &= ~(1UL << bit)) {
2766 pv = &pc->pc_pventry[field * 64 + bit];
2768 pde = pmap_pde(pmap, va);
2769 if ((*pde & PG_PS) != 0)
2771 pte = pmap_pde_to_pte(pde, va);
2772 if ((*pte & PG_W) != 0)
2774 tpte = pte_load_clear(pte);
2775 if ((tpte & PG_G) != 0)
2776 pmap_invalidate_page(pmap, va);
2777 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2778 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2780 if ((tpte & PG_A) != 0)
2781 vm_page_aflag_set(m, PGA_REFERENCED);
2782 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2783 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2785 if (TAILQ_EMPTY(&m->md.pv_list) &&
2786 (m->flags & PG_FICTITIOUS) == 0) {
2787 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2788 if (TAILQ_EMPTY(&pvh->pv_list)) {
2789 vm_page_aflag_clear(m,
2793 pc->pc_map[field] |= 1UL << bit;
2794 pmap_unuse_pt(pmap, va, *pde, &free);
2799 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2800 mtx_lock(&pv_chunks_mutex);
2803 /* Every freed mapping is for a 4 KB page. */
2804 pmap_resident_count_dec(pmap, freed);
2805 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2806 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2807 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2808 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2809 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2810 pc->pc_map[2] == PC_FREE2) {
2811 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2812 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2813 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2814 /* Entire chunk is free; return it. */
2815 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2816 dump_drop_page(m_pc->phys_addr);
2817 mtx_lock(&pv_chunks_mutex);
2820 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2821 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2822 mtx_lock(&pv_chunks_mutex);
2823 /* One freed pv entry in locked_pmap is sufficient. */
2824 if (pmap == locked_pmap)
2827 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2828 mtx_unlock(&pv_chunks_mutex);
2830 pmap_invalidate_all(pmap);
2831 if (pmap != locked_pmap)
2834 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2835 m_pc = SLIST_FIRST(&free);
2836 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2837 /* Recycle a freed page table page. */
2838 m_pc->wire_count = 1;
2839 atomic_add_int(&vm_cnt.v_wire_count, 1);
2841 pmap_free_zero_pages(&free);
2846 * free the pv_entry back to the free list
2849 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2851 struct pv_chunk *pc;
2852 int idx, field, bit;
2854 rw_assert(&pvh_global_lock, RA_LOCKED);
2855 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2856 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2857 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2858 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2859 pc = pv_to_chunk(pv);
2860 idx = pv - &pc->pc_pventry[0];
2863 pc->pc_map[field] |= 1ul << bit;
2864 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2865 pc->pc_map[2] != PC_FREE2) {
2866 /* 98% of the time, pc is already at the head of the list. */
2867 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2868 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2869 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2873 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2878 free_pv_chunk(struct pv_chunk *pc)
2882 mtx_lock(&pv_chunks_mutex);
2883 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2884 mtx_unlock(&pv_chunks_mutex);
2885 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2886 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2887 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2888 /* entire chunk is free, return it */
2889 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2890 dump_drop_page(m->phys_addr);
2891 vm_page_unwire(m, PQ_NONE);
2896 * Returns a new PV entry, allocating a new PV chunk from the system when
2897 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2898 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2901 * The given PV list lock may be released.
2904 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2908 struct pv_chunk *pc;
2911 rw_assert(&pvh_global_lock, RA_LOCKED);
2912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2913 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2915 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2917 for (field = 0; field < _NPCM; field++) {
2918 if (pc->pc_map[field]) {
2919 bit = bsfq(pc->pc_map[field]);
2923 if (field < _NPCM) {
2924 pv = &pc->pc_pventry[field * 64 + bit];
2925 pc->pc_map[field] &= ~(1ul << bit);
2926 /* If this was the last item, move it to tail */
2927 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2928 pc->pc_map[2] == 0) {
2929 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2930 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2933 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2934 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2938 /* No free items, allocate another chunk */
2939 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2942 if (lockp == NULL) {
2943 PV_STAT(pc_chunk_tryfail++);
2946 m = reclaim_pv_chunk(pmap, lockp);
2950 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2951 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2952 dump_add_page(m->phys_addr);
2953 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2955 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2956 pc->pc_map[1] = PC_FREE1;
2957 pc->pc_map[2] = PC_FREE2;
2958 mtx_lock(&pv_chunks_mutex);
2959 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2960 mtx_unlock(&pv_chunks_mutex);
2961 pv = &pc->pc_pventry[0];
2962 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2963 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2964 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2969 * Returns the number of one bits within the given PV chunk map element.
2971 * The erratas for Intel processors state that "POPCNT Instruction May
2972 * Take Longer to Execute Than Expected". It is believed that the
2973 * issue is the spurious dependency on the destination register.
2974 * Provide a hint to the register rename logic that the destination
2975 * value is overwritten, by clearing it, as suggested in the
2976 * optimization manual. It should be cheap for unaffected processors
2979 * Reference numbers for erratas are
2980 * 4th Gen Core: HSD146
2981 * 5th Gen Core: BDM85
2984 popcnt_pc_map_elem_pq(uint64_t elem)
2988 __asm __volatile("xorl %k0,%k0;popcntq %1,%0"
2989 : "=&r" (result) : "rm" (elem));
2994 * Ensure that the number of spare PV entries in the specified pmap meets or
2995 * exceeds the given count, "needed".
2997 * The given PV list lock may be released.
3000 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3002 struct pch new_tail;
3003 struct pv_chunk *pc;
3007 rw_assert(&pvh_global_lock, RA_LOCKED);
3008 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3009 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3012 * Newly allocated PV chunks must be stored in a private list until
3013 * the required number of PV chunks have been allocated. Otherwise,
3014 * reclaim_pv_chunk() could recycle one of these chunks. In
3015 * contrast, these chunks must be added to the pmap upon allocation.
3017 TAILQ_INIT(&new_tail);
3020 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3022 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
3023 free = bitcount64(pc->pc_map[0]);
3024 free += bitcount64(pc->pc_map[1]);
3025 free += bitcount64(pc->pc_map[2]);
3029 free = popcnt_pc_map_elem_pq(pc->pc_map[0]);
3030 free += popcnt_pc_map_elem_pq(pc->pc_map[1]);
3031 free += popcnt_pc_map_elem_pq(pc->pc_map[2]);
3036 if (avail >= needed)
3039 for (; avail < needed; avail += _NPCPV) {
3040 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3043 m = reclaim_pv_chunk(pmap, lockp);
3047 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3048 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3049 dump_add_page(m->phys_addr);
3050 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3052 pc->pc_map[0] = PC_FREE0;
3053 pc->pc_map[1] = PC_FREE1;
3054 pc->pc_map[2] = PC_FREE2;
3055 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3056 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3057 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3059 if (!TAILQ_EMPTY(&new_tail)) {
3060 mtx_lock(&pv_chunks_mutex);
3061 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3062 mtx_unlock(&pv_chunks_mutex);
3067 * First find and then remove the pv entry for the specified pmap and virtual
3068 * address from the specified pv list. Returns the pv entry if found and NULL
3069 * otherwise. This operation can be performed on pv lists for either 4KB or
3070 * 2MB page mappings.
3072 static __inline pv_entry_t
3073 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3077 rw_assert(&pvh_global_lock, RA_LOCKED);
3078 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3079 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3080 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3089 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3090 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3091 * entries for each of the 4KB page mappings.
3094 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3095 struct rwlock **lockp)
3097 struct md_page *pvh;
3098 struct pv_chunk *pc;
3100 vm_offset_t va_last;
3104 rw_assert(&pvh_global_lock, RA_LOCKED);
3105 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3106 KASSERT((pa & PDRMASK) == 0,
3107 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3108 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3111 * Transfer the 2mpage's pv entry for this mapping to the first
3112 * page's pv list. Once this transfer begins, the pv list lock
3113 * must not be released until the last pv entry is reinstantiated.
3115 pvh = pa_to_pvh(pa);
3116 va = trunc_2mpage(va);
3117 pv = pmap_pvh_remove(pvh, pmap, va);
3118 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3119 m = PHYS_TO_VM_PAGE(pa);
3120 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3122 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3123 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3124 va_last = va + NBPDR - PAGE_SIZE;
3126 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3127 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3128 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3129 for (field = 0; field < _NPCM; field++) {
3130 while (pc->pc_map[field]) {
3131 bit = bsfq(pc->pc_map[field]);
3132 pc->pc_map[field] &= ~(1ul << bit);
3133 pv = &pc->pc_pventry[field * 64 + bit];
3137 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3138 ("pmap_pv_demote_pde: page %p is not managed", m));
3139 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3145 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3146 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3149 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3150 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3151 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3153 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3154 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3158 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3159 * replace the many pv entries for the 4KB page mappings by a single pv entry
3160 * for the 2MB page mapping.
3163 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3164 struct rwlock **lockp)
3166 struct md_page *pvh;
3168 vm_offset_t va_last;
3171 rw_assert(&pvh_global_lock, RA_LOCKED);
3172 KASSERT((pa & PDRMASK) == 0,
3173 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3174 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3177 * Transfer the first page's pv entry for this mapping to the 2mpage's
3178 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3179 * a transfer avoids the possibility that get_pv_entry() calls
3180 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3181 * mappings that is being promoted.
3183 m = PHYS_TO_VM_PAGE(pa);
3184 va = trunc_2mpage(va);
3185 pv = pmap_pvh_remove(&m->md, pmap, va);
3186 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3187 pvh = pa_to_pvh(pa);
3188 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3190 /* Free the remaining NPTEPG - 1 pv entries. */
3191 va_last = va + NBPDR - PAGE_SIZE;
3195 pmap_pvh_free(&m->md, pmap, va);
3196 } while (va < va_last);
3200 * First find and then destroy the pv entry for the specified pmap and virtual
3201 * address. This operation can be performed on pv lists for either 4KB or 2MB
3205 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3209 pv = pmap_pvh_remove(pvh, pmap, va);
3210 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3211 free_pv_entry(pmap, pv);
3215 * Conditionally create the PV entry for a 4KB page mapping if the required
3216 * memory can be allocated without resorting to reclamation.
3219 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3220 struct rwlock **lockp)
3224 rw_assert(&pvh_global_lock, RA_LOCKED);
3225 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3226 /* Pass NULL instead of the lock pointer to disable reclamation. */
3227 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3229 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3230 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3238 * Conditionally create the PV entry for a 2MB page mapping if the required
3239 * memory can be allocated without resorting to reclamation.
3242 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3243 struct rwlock **lockp)
3245 struct md_page *pvh;
3248 rw_assert(&pvh_global_lock, RA_LOCKED);
3249 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3250 /* Pass NULL instead of the lock pointer to disable reclamation. */
3251 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3253 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3254 pvh = pa_to_pvh(pa);
3255 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3263 * Fills a page table page with mappings to consecutive physical pages.
3266 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3270 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3272 newpte += PAGE_SIZE;
3277 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3278 * mapping is invalidated.
3281 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3283 struct rwlock *lock;
3287 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3294 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3295 struct rwlock **lockp)
3297 pd_entry_t newpde, oldpde;
3298 pt_entry_t *firstpte, newpte;
3299 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3302 struct spglist free;
3305 PG_G = pmap_global_bit(pmap);
3306 PG_A = pmap_accessed_bit(pmap);
3307 PG_M = pmap_modified_bit(pmap);
3308 PG_RW = pmap_rw_bit(pmap);
3309 PG_V = pmap_valid_bit(pmap);
3310 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3312 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3314 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3315 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3316 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3318 pmap_remove_pt_page(pmap, mpte);
3320 KASSERT((oldpde & PG_W) == 0,
3321 ("pmap_demote_pde: page table page for a wired mapping"
3325 * Invalidate the 2MB page mapping and return "failure" if the
3326 * mapping was never accessed or the allocation of the new
3327 * page table page fails. If the 2MB page mapping belongs to
3328 * the direct map region of the kernel's address space, then
3329 * the page allocation request specifies the highest possible
3330 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3331 * normal. Page table pages are preallocated for every other
3332 * part of the kernel address space, so the direct map region
3333 * is the only part of the kernel address space that must be
3336 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3337 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3338 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3339 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3341 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3343 pmap_invalidate_page(pmap, trunc_2mpage(va));
3344 pmap_free_zero_pages(&free);
3345 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3346 " in pmap %p", va, pmap);
3349 if (va < VM_MAXUSER_ADDRESS)
3350 pmap_resident_count_inc(pmap, 1);
3352 mptepa = VM_PAGE_TO_PHYS(mpte);
3353 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3354 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3355 KASSERT((oldpde & PG_A) != 0,
3356 ("pmap_demote_pde: oldpde is missing PG_A"));
3357 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3358 ("pmap_demote_pde: oldpde is missing PG_M"));
3359 newpte = oldpde & ~PG_PS;
3360 newpte = pmap_swap_pat(pmap, newpte);
3363 * If the page table page is new, initialize it.
3365 if (mpte->wire_count == 1) {
3366 mpte->wire_count = NPTEPG;
3367 pmap_fill_ptp(firstpte, newpte);
3369 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3370 ("pmap_demote_pde: firstpte and newpte map different physical"
3374 * If the mapping has changed attributes, update the page table
3377 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3378 pmap_fill_ptp(firstpte, newpte);
3381 * The spare PV entries must be reserved prior to demoting the
3382 * mapping, that is, prior to changing the PDE. Otherwise, the state
3383 * of the PDE and the PV lists will be inconsistent, which can result
3384 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3385 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3386 * PV entry for the 2MB page mapping that is being demoted.
3388 if ((oldpde & PG_MANAGED) != 0)
3389 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3392 * Demote the mapping. This pmap is locked. The old PDE has
3393 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3394 * set. Thus, there is no danger of a race with another
3395 * processor changing the setting of PG_A and/or PG_M between
3396 * the read above and the store below.
3398 if (workaround_erratum383)
3399 pmap_update_pde(pmap, va, pde, newpde);
3401 pde_store(pde, newpde);
3404 * Invalidate a stale recursive mapping of the page table page.
3406 if (va >= VM_MAXUSER_ADDRESS)
3407 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3410 * Demote the PV entry.
3412 if ((oldpde & PG_MANAGED) != 0)
3413 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3415 atomic_add_long(&pmap_pde_demotions, 1);
3416 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3417 " in pmap %p", va, pmap);
3422 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3425 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3431 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3432 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3433 mpte = pmap_lookup_pt_page(pmap, va);
3435 panic("pmap_remove_kernel_pde: Missing pt page.");
3437 pmap_remove_pt_page(pmap, mpte);
3438 mptepa = VM_PAGE_TO_PHYS(mpte);
3439 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3442 * Initialize the page table page.
3444 pagezero((void *)PHYS_TO_DMAP(mptepa));
3447 * Demote the mapping.
3449 if (workaround_erratum383)
3450 pmap_update_pde(pmap, va, pde, newpde);
3452 pde_store(pde, newpde);
3455 * Invalidate a stale recursive mapping of the page table page.
3457 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3461 * pmap_remove_pde: do the things to unmap a superpage in a process
3464 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3465 struct spglist *free, struct rwlock **lockp)
3467 struct md_page *pvh;
3469 vm_offset_t eva, va;
3471 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3473 PG_G = pmap_global_bit(pmap);
3474 PG_A = pmap_accessed_bit(pmap);
3475 PG_M = pmap_modified_bit(pmap);
3476 PG_RW = pmap_rw_bit(pmap);
3478 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3479 KASSERT((sva & PDRMASK) == 0,
3480 ("pmap_remove_pde: sva is not 2mpage aligned"));
3481 oldpde = pte_load_clear(pdq);
3483 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3486 * Machines that don't support invlpg, also don't support
3490 pmap_invalidate_page(kernel_pmap, sva);
3491 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3492 if (oldpde & PG_MANAGED) {
3493 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3494 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3495 pmap_pvh_free(pvh, pmap, sva);
3497 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3498 va < eva; va += PAGE_SIZE, m++) {
3499 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3502 vm_page_aflag_set(m, PGA_REFERENCED);
3503 if (TAILQ_EMPTY(&m->md.pv_list) &&
3504 TAILQ_EMPTY(&pvh->pv_list))
3505 vm_page_aflag_clear(m, PGA_WRITEABLE);
3508 if (pmap == kernel_pmap) {
3509 pmap_remove_kernel_pde(pmap, pdq, sva);
3511 mpte = pmap_lookup_pt_page(pmap, sva);
3513 pmap_remove_pt_page(pmap, mpte);
3514 pmap_resident_count_dec(pmap, 1);
3515 KASSERT(mpte->wire_count == NPTEPG,
3516 ("pmap_remove_pde: pte page wire count error"));
3517 mpte->wire_count = 0;
3518 pmap_add_delayed_free_list(mpte, free, FALSE);
3519 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
3522 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3526 * pmap_remove_pte: do the things to unmap a page in a process
3529 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3530 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3532 struct md_page *pvh;
3533 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3536 PG_A = pmap_accessed_bit(pmap);
3537 PG_M = pmap_modified_bit(pmap);
3538 PG_RW = pmap_rw_bit(pmap);
3540 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3541 oldpte = pte_load_clear(ptq);
3543 pmap->pm_stats.wired_count -= 1;
3544 pmap_resident_count_dec(pmap, 1);
3545 if (oldpte & PG_MANAGED) {
3546 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3547 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3550 vm_page_aflag_set(m, PGA_REFERENCED);
3551 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3552 pmap_pvh_free(&m->md, pmap, va);
3553 if (TAILQ_EMPTY(&m->md.pv_list) &&
3554 (m->flags & PG_FICTITIOUS) == 0) {
3555 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3556 if (TAILQ_EMPTY(&pvh->pv_list))
3557 vm_page_aflag_clear(m, PGA_WRITEABLE);
3560 return (pmap_unuse_pt(pmap, va, ptepde, free));
3564 * Remove a single page from a process address space
3567 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3568 struct spglist *free)
3570 struct rwlock *lock;
3571 pt_entry_t *pte, PG_V;
3573 PG_V = pmap_valid_bit(pmap);
3574 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3575 if ((*pde & PG_V) == 0)
3577 pte = pmap_pde_to_pte(pde, va);
3578 if ((*pte & PG_V) == 0)
3581 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3584 pmap_invalidate_page(pmap, va);
3588 * Remove the given range of addresses from the specified map.
3590 * It is assumed that the start and end are properly
3591 * rounded to the page size.
3594 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3596 struct rwlock *lock;
3597 vm_offset_t va, va_next;
3598 pml4_entry_t *pml4e;
3600 pd_entry_t ptpaddr, *pde;
3601 pt_entry_t *pte, PG_G, PG_V;
3602 struct spglist free;
3605 PG_G = pmap_global_bit(pmap);
3606 PG_V = pmap_valid_bit(pmap);
3609 * Perform an unsynchronized read. This is, however, safe.
3611 if (pmap->pm_stats.resident_count == 0)
3617 rw_rlock(&pvh_global_lock);
3621 * special handling of removing one page. a very
3622 * common operation and easy to short circuit some
3625 if (sva + PAGE_SIZE == eva) {
3626 pde = pmap_pde(pmap, sva);
3627 if (pde && (*pde & PG_PS) == 0) {
3628 pmap_remove_page(pmap, sva, pde, &free);
3634 for (; sva < eva; sva = va_next) {
3636 if (pmap->pm_stats.resident_count == 0)
3639 pml4e = pmap_pml4e(pmap, sva);
3640 if ((*pml4e & PG_V) == 0) {
3641 va_next = (sva + NBPML4) & ~PML4MASK;
3647 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3648 if ((*pdpe & PG_V) == 0) {
3649 va_next = (sva + NBPDP) & ~PDPMASK;
3656 * Calculate index for next page table.
3658 va_next = (sva + NBPDR) & ~PDRMASK;
3662 pde = pmap_pdpe_to_pde(pdpe, sva);
3666 * Weed out invalid mappings.
3672 * Check for large page.
3674 if ((ptpaddr & PG_PS) != 0) {
3676 * Are we removing the entire large page? If not,
3677 * demote the mapping and fall through.
3679 if (sva + NBPDR == va_next && eva >= va_next) {
3681 * The TLB entry for a PG_G mapping is
3682 * invalidated by pmap_remove_pde().
3684 if ((ptpaddr & PG_G) == 0)
3686 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3688 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3690 /* The large page mapping was destroyed. */
3697 * Limit our scan to either the end of the va represented
3698 * by the current page table page, or to the end of the
3699 * range being removed.
3705 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3708 if (va != va_next) {
3709 pmap_invalidate_range(pmap, va, sva);
3714 if ((*pte & PG_G) == 0)
3716 else if (va == va_next)
3718 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3725 pmap_invalidate_range(pmap, va, sva);
3731 pmap_invalidate_all(pmap);
3732 rw_runlock(&pvh_global_lock);
3734 pmap_free_zero_pages(&free);
3738 * Routine: pmap_remove_all
3740 * Removes this physical page from
3741 * all physical maps in which it resides.
3742 * Reflects back modify bits to the pager.
3745 * Original versions of this routine were very
3746 * inefficient because they iteratively called
3747 * pmap_remove (slow...)
3751 pmap_remove_all(vm_page_t m)
3753 struct md_page *pvh;
3756 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3759 struct spglist free;
3761 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3762 ("pmap_remove_all: page %p is not managed", m));
3764 rw_wlock(&pvh_global_lock);
3765 if ((m->flags & PG_FICTITIOUS) != 0)
3766 goto small_mappings;
3767 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3768 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3772 pde = pmap_pde(pmap, va);
3773 (void)pmap_demote_pde(pmap, pde, va);
3777 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3780 PG_A = pmap_accessed_bit(pmap);
3781 PG_M = pmap_modified_bit(pmap);
3782 PG_RW = pmap_rw_bit(pmap);
3783 pmap_resident_count_dec(pmap, 1);
3784 pde = pmap_pde(pmap, pv->pv_va);
3785 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3786 " a 2mpage in page %p's pv list", m));
3787 pte = pmap_pde_to_pte(pde, pv->pv_va);
3788 tpte = pte_load_clear(pte);
3790 pmap->pm_stats.wired_count--;
3792 vm_page_aflag_set(m, PGA_REFERENCED);
3795 * Update the vm_page_t clean and reference bits.
3797 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3799 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3800 pmap_invalidate_page(pmap, pv->pv_va);
3801 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3803 free_pv_entry(pmap, pv);
3806 vm_page_aflag_clear(m, PGA_WRITEABLE);
3807 rw_wunlock(&pvh_global_lock);
3808 pmap_free_zero_pages(&free);
3812 * pmap_protect_pde: do the things to protect a 2mpage in a process
3815 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3817 pd_entry_t newpde, oldpde;
3818 vm_offset_t eva, va;
3820 boolean_t anychanged;
3821 pt_entry_t PG_G, PG_M, PG_RW;
3823 PG_G = pmap_global_bit(pmap);
3824 PG_M = pmap_modified_bit(pmap);
3825 PG_RW = pmap_rw_bit(pmap);
3827 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3828 KASSERT((sva & PDRMASK) == 0,
3829 ("pmap_protect_pde: sva is not 2mpage aligned"));
3832 oldpde = newpde = *pde;
3833 if (oldpde & PG_MANAGED) {
3835 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3836 va < eva; va += PAGE_SIZE, m++)
3837 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3840 if ((prot & VM_PROT_WRITE) == 0)
3841 newpde &= ~(PG_RW | PG_M);
3842 if ((prot & VM_PROT_EXECUTE) == 0)
3844 if (newpde != oldpde) {
3845 if (!atomic_cmpset_long(pde, oldpde, newpde))
3848 pmap_invalidate_page(pmap, sva);
3852 return (anychanged);
3856 * Set the physical protection on the
3857 * specified range of this map as requested.
3860 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3862 vm_offset_t va_next;
3863 pml4_entry_t *pml4e;
3865 pd_entry_t ptpaddr, *pde;
3866 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3867 boolean_t anychanged, pv_lists_locked;
3869 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3870 if (prot == VM_PROT_NONE) {
3871 pmap_remove(pmap, sva, eva);
3875 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3876 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3879 PG_G = pmap_global_bit(pmap);
3880 PG_M = pmap_modified_bit(pmap);
3881 PG_V = pmap_valid_bit(pmap);
3882 PG_RW = pmap_rw_bit(pmap);
3883 pv_lists_locked = FALSE;
3888 for (; sva < eva; sva = va_next) {
3890 pml4e = pmap_pml4e(pmap, sva);
3891 if ((*pml4e & PG_V) == 0) {
3892 va_next = (sva + NBPML4) & ~PML4MASK;
3898 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3899 if ((*pdpe & PG_V) == 0) {
3900 va_next = (sva + NBPDP) & ~PDPMASK;
3906 va_next = (sva + NBPDR) & ~PDRMASK;
3910 pde = pmap_pdpe_to_pde(pdpe, sva);
3914 * Weed out invalid mappings.
3920 * Check for large page.
3922 if ((ptpaddr & PG_PS) != 0) {
3924 * Are we protecting the entire large page? If not,
3925 * demote the mapping and fall through.
3927 if (sva + NBPDR == va_next && eva >= va_next) {
3929 * The TLB entry for a PG_G mapping is
3930 * invalidated by pmap_protect_pde().
3932 if (pmap_protect_pde(pmap, pde, sva, prot))
3936 if (!pv_lists_locked) {
3937 pv_lists_locked = TRUE;
3938 if (!rw_try_rlock(&pvh_global_lock)) {
3940 pmap_invalidate_all(
3943 rw_rlock(&pvh_global_lock);
3947 if (!pmap_demote_pde(pmap, pde, sva)) {
3949 * The large page mapping was
3960 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3962 pt_entry_t obits, pbits;
3966 obits = pbits = *pte;
3967 if ((pbits & PG_V) == 0)
3970 if ((prot & VM_PROT_WRITE) == 0) {
3971 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3972 (PG_MANAGED | PG_M | PG_RW)) {
3973 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3976 pbits &= ~(PG_RW | PG_M);
3978 if ((prot & VM_PROT_EXECUTE) == 0)
3981 if (pbits != obits) {
3982 if (!atomic_cmpset_long(pte, obits, pbits))
3985 pmap_invalidate_page(pmap, sva);
3992 pmap_invalidate_all(pmap);
3993 if (pv_lists_locked)
3994 rw_runlock(&pvh_global_lock);
3999 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4000 * single page table page (PTP) to a single 2MB page mapping. For promotion
4001 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4002 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4003 * identical characteristics.
4006 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4007 struct rwlock **lockp)
4010 pt_entry_t *firstpte, oldpte, pa, *pte;
4011 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4015 PG_A = pmap_accessed_bit(pmap);
4016 PG_G = pmap_global_bit(pmap);
4017 PG_M = pmap_modified_bit(pmap);
4018 PG_V = pmap_valid_bit(pmap);
4019 PG_RW = pmap_rw_bit(pmap);
4020 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4022 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4025 * Examine the first PTE in the specified PTP. Abort if this PTE is
4026 * either invalid, unused, or does not map the first 4KB physical page
4027 * within a 2MB page.
4029 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4032 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4033 atomic_add_long(&pmap_pde_p_failures, 1);
4034 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4035 " in pmap %p", va, pmap);
4038 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4040 * When PG_M is already clear, PG_RW can be cleared without
4041 * a TLB invalidation.
4043 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4049 * Examine each of the other PTEs in the specified PTP. Abort if this
4050 * PTE maps an unexpected 4KB physical page or does not have identical
4051 * characteristics to the first PTE.
4053 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4054 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4057 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4058 atomic_add_long(&pmap_pde_p_failures, 1);
4059 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4060 " in pmap %p", va, pmap);
4063 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4065 * When PG_M is already clear, PG_RW can be cleared
4066 * without a TLB invalidation.
4068 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4071 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4072 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4073 (va & ~PDRMASK), pmap);
4075 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4076 atomic_add_long(&pmap_pde_p_failures, 1);
4077 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4078 " in pmap %p", va, pmap);
4085 * Save the page table page in its current state until the PDE
4086 * mapping the superpage is demoted by pmap_demote_pde() or
4087 * destroyed by pmap_remove_pde().
4089 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4090 KASSERT(mpte >= vm_page_array &&
4091 mpte < &vm_page_array[vm_page_array_size],
4092 ("pmap_promote_pde: page table page is out of range"));
4093 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4094 ("pmap_promote_pde: page table page's pindex is wrong"));
4095 if (pmap_insert_pt_page(pmap, mpte)) {
4096 atomic_add_long(&pmap_pde_p_failures, 1);
4098 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4104 * Promote the pv entries.
4106 if ((newpde & PG_MANAGED) != 0)
4107 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4110 * Propagate the PAT index to its proper position.
4112 newpde = pmap_swap_pat(pmap, newpde);
4115 * Map the superpage.
4117 if (workaround_erratum383)
4118 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4120 pde_store(pde, PG_PS | newpde);
4122 atomic_add_long(&pmap_pde_promotions, 1);
4123 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4124 " in pmap %p", va, pmap);
4128 * Insert the given physical page (p) at
4129 * the specified virtual address (v) in the
4130 * target physical map with the protection requested.
4132 * If specified, the page will be wired down, meaning
4133 * that the related pte can not be reclaimed.
4135 * NB: This is the only routine which MAY NOT lazy-evaluate
4136 * or lose information. That is, this routine must actually
4137 * insert this page into the given map NOW.
4140 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4141 u_int flags, int8_t psind __unused)
4143 struct rwlock *lock;
4145 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4146 pt_entry_t newpte, origpte;
4152 PG_A = pmap_accessed_bit(pmap);
4153 PG_G = pmap_global_bit(pmap);
4154 PG_M = pmap_modified_bit(pmap);
4155 PG_V = pmap_valid_bit(pmap);
4156 PG_RW = pmap_rw_bit(pmap);
4158 va = trunc_page(va);
4159 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4160 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4161 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4163 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4164 va >= kmi.clean_eva,
4165 ("pmap_enter: managed mapping within the clean submap"));
4166 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4167 VM_OBJECT_ASSERT_LOCKED(m->object);
4168 pa = VM_PAGE_TO_PHYS(m);
4169 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4170 if ((flags & VM_PROT_WRITE) != 0)
4172 if ((prot & VM_PROT_WRITE) != 0)
4174 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4175 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4176 if ((prot & VM_PROT_EXECUTE) == 0)
4178 if ((flags & PMAP_ENTER_WIRED) != 0)
4180 if (va < VM_MAXUSER_ADDRESS)
4182 if (pmap == kernel_pmap)
4184 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4187 * Set modified bit gratuitously for writeable mappings if
4188 * the page is unmanaged. We do not want to take a fault
4189 * to do the dirty bit accounting for these mappings.
4191 if ((m->oflags & VPO_UNMANAGED) != 0) {
4192 if ((newpte & PG_RW) != 0)
4199 rw_rlock(&pvh_global_lock);
4203 * In the case that a page table page is not
4204 * resident, we are creating it here.
4207 pde = pmap_pde(pmap, va);
4208 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4209 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4210 pte = pmap_pde_to_pte(pde, va);
4211 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4212 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4215 } else if (va < VM_MAXUSER_ADDRESS) {
4217 * Here if the pte page isn't mapped, or if it has been
4220 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4221 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4222 nosleep ? NULL : &lock);
4223 if (mpte == NULL && nosleep) {
4226 rw_runlock(&pvh_global_lock);
4228 return (KERN_RESOURCE_SHORTAGE);
4232 panic("pmap_enter: invalid page directory va=%#lx", va);
4237 * Is the specified virtual address already mapped?
4239 if ((origpte & PG_V) != 0) {
4241 * Wiring change, just update stats. We don't worry about
4242 * wiring PT pages as they remain resident as long as there
4243 * are valid mappings in them. Hence, if a user page is wired,
4244 * the PT page will be also.
4246 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4247 pmap->pm_stats.wired_count++;
4248 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4249 pmap->pm_stats.wired_count--;
4252 * Remove the extra PT page reference.
4256 KASSERT(mpte->wire_count > 0,
4257 ("pmap_enter: missing reference to page table page,"
4262 * Has the physical page changed?
4264 opa = origpte & PG_FRAME;
4267 * No, might be a protection or wiring change.
4269 if ((origpte & PG_MANAGED) != 0) {
4270 newpte |= PG_MANAGED;
4271 if ((newpte & PG_RW) != 0)
4272 vm_page_aflag_set(m, PGA_WRITEABLE);
4274 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4280 * Increment the counters.
4282 if ((newpte & PG_W) != 0)
4283 pmap->pm_stats.wired_count++;
4284 pmap_resident_count_inc(pmap, 1);
4288 * Enter on the PV list if part of our managed memory.
4290 if ((m->oflags & VPO_UNMANAGED) == 0) {
4291 newpte |= PG_MANAGED;
4292 pv = get_pv_entry(pmap, &lock);
4294 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4295 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4297 if ((newpte & PG_RW) != 0)
4298 vm_page_aflag_set(m, PGA_WRITEABLE);
4304 if ((origpte & PG_V) != 0) {
4306 origpte = pte_load_store(pte, newpte);
4307 opa = origpte & PG_FRAME;
4309 if ((origpte & PG_MANAGED) != 0) {
4310 om = PHYS_TO_VM_PAGE(opa);
4311 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4314 if ((origpte & PG_A) != 0)
4315 vm_page_aflag_set(om, PGA_REFERENCED);
4316 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4317 pmap_pvh_free(&om->md, pmap, va);
4318 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4319 TAILQ_EMPTY(&om->md.pv_list) &&
4320 ((om->flags & PG_FICTITIOUS) != 0 ||
4321 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4322 vm_page_aflag_clear(om, PGA_WRITEABLE);
4324 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4325 PG_RW)) == (PG_M | PG_RW)) {
4326 if ((origpte & PG_MANAGED) != 0)
4330 * Although the PTE may still have PG_RW set, TLB
4331 * invalidation may nonetheless be required because
4332 * the PTE no longer has PG_M set.
4334 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4336 * This PTE change does not require TLB invalidation.
4340 if ((origpte & PG_A) != 0)
4341 pmap_invalidate_page(pmap, va);
4343 pte_store(pte, newpte);
4348 * If both the page table page and the reservation are fully
4349 * populated, then attempt promotion.
4351 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4352 pmap_ps_enabled(pmap) &&
4353 (m->flags & PG_FICTITIOUS) == 0 &&
4354 vm_reserv_level_iffullpop(m) == 0)
4355 pmap_promote_pde(pmap, pde, va, &lock);
4359 rw_runlock(&pvh_global_lock);
4361 return (KERN_SUCCESS);
4365 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4366 * otherwise. Fails if (1) a page table page cannot be allocated without
4367 * blocking, (2) a mapping already exists at the specified virtual address, or
4368 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4371 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4372 struct rwlock **lockp)
4374 pd_entry_t *pde, newpde;
4377 struct spglist free;
4379 PG_V = pmap_valid_bit(pmap);
4380 rw_assert(&pvh_global_lock, RA_LOCKED);
4381 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4383 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4384 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4385 " in pmap %p", va, pmap);
4388 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4389 pde = &pde[pmap_pde_index(va)];
4390 if ((*pde & PG_V) != 0) {
4391 KASSERT(mpde->wire_count > 1,
4392 ("pmap_enter_pde: mpde's wire count is too low"));
4394 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4395 " in pmap %p", va, pmap);
4398 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4400 if ((m->oflags & VPO_UNMANAGED) == 0) {
4401 newpde |= PG_MANAGED;
4404 * Abort this mapping if its PV entry could not be created.
4406 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4409 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4410 pmap_invalidate_page(pmap, va);
4411 pmap_free_zero_pages(&free);
4413 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4414 " in pmap %p", va, pmap);
4418 if ((prot & VM_PROT_EXECUTE) == 0)
4420 if (va < VM_MAXUSER_ADDRESS)
4424 * Increment counters.
4426 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4429 * Map the superpage.
4431 pde_store(pde, newpde);
4433 atomic_add_long(&pmap_pde_mappings, 1);
4434 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4435 " in pmap %p", va, pmap);
4440 * Maps a sequence of resident pages belonging to the same object.
4441 * The sequence begins with the given page m_start. This page is
4442 * mapped at the given virtual address start. Each subsequent page is
4443 * mapped at a virtual address that is offset from start by the same
4444 * amount as the page is offset from m_start within the object. The
4445 * last page in the sequence is the page with the largest offset from
4446 * m_start that can be mapped at a virtual address less than the given
4447 * virtual address end. Not every virtual page between start and end
4448 * is mapped; only those for which a resident page exists with the
4449 * corresponding offset from m_start are mapped.
4452 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4453 vm_page_t m_start, vm_prot_t prot)
4455 struct rwlock *lock;
4458 vm_pindex_t diff, psize;
4460 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4462 psize = atop(end - start);
4466 rw_rlock(&pvh_global_lock);
4468 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4469 va = start + ptoa(diff);
4470 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4471 m->psind == 1 && pmap_ps_enabled(pmap) &&
4472 pmap_enter_pde(pmap, va, m, prot, &lock))
4473 m = &m[NBPDR / PAGE_SIZE - 1];
4475 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4477 m = TAILQ_NEXT(m, listq);
4481 rw_runlock(&pvh_global_lock);
4486 * this code makes some *MAJOR* assumptions:
4487 * 1. Current pmap & pmap exists.
4490 * 4. No page table pages.
4491 * but is *MUCH* faster than pmap_enter...
4495 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4497 struct rwlock *lock;
4500 rw_rlock(&pvh_global_lock);
4502 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4505 rw_runlock(&pvh_global_lock);
4510 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4511 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4513 struct spglist free;
4514 pt_entry_t *pte, PG_V;
4517 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4518 (m->oflags & VPO_UNMANAGED) != 0,
4519 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4520 PG_V = pmap_valid_bit(pmap);
4521 rw_assert(&pvh_global_lock, RA_LOCKED);
4522 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4525 * In the case that a page table page is not
4526 * resident, we are creating it here.
4528 if (va < VM_MAXUSER_ADDRESS) {
4529 vm_pindex_t ptepindex;
4533 * Calculate pagetable page index
4535 ptepindex = pmap_pde_pindex(va);
4536 if (mpte && (mpte->pindex == ptepindex)) {
4540 * Get the page directory entry
4542 ptepa = pmap_pde(pmap, va);
4545 * If the page table page is mapped, we just increment
4546 * the hold count, and activate it. Otherwise, we
4547 * attempt to allocate a page table page. If this
4548 * attempt fails, we don't retry. Instead, we give up.
4550 if (ptepa && (*ptepa & PG_V) != 0) {
4553 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4557 * Pass NULL instead of the PV list lock
4558 * pointer, because we don't intend to sleep.
4560 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4565 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4566 pte = &pte[pmap_pte_index(va)];
4580 * Enter on the PV list if part of our managed memory.
4582 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4583 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4586 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4587 pmap_invalidate_page(pmap, va);
4588 pmap_free_zero_pages(&free);
4596 * Increment counters
4598 pmap_resident_count_inc(pmap, 1);
4600 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4601 if ((prot & VM_PROT_EXECUTE) == 0)
4605 * Now validate mapping with RO protection
4607 if ((m->oflags & VPO_UNMANAGED) != 0)
4608 pte_store(pte, pa | PG_V | PG_U);
4610 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4615 * Make a temporary mapping for a physical address. This is only intended
4616 * to be used for panic dumps.
4619 pmap_kenter_temporary(vm_paddr_t pa, int i)
4623 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4624 pmap_kenter(va, pa);
4626 return ((void *)crashdumpmap);
4630 * This code maps large physical mmap regions into the
4631 * processor address space. Note that some shortcuts
4632 * are taken, but the code works.
4635 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4636 vm_pindex_t pindex, vm_size_t size)
4639 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4640 vm_paddr_t pa, ptepa;
4644 PG_A = pmap_accessed_bit(pmap);
4645 PG_M = pmap_modified_bit(pmap);
4646 PG_V = pmap_valid_bit(pmap);
4647 PG_RW = pmap_rw_bit(pmap);
4649 VM_OBJECT_ASSERT_WLOCKED(object);
4650 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4651 ("pmap_object_init_pt: non-device object"));
4652 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4653 if (!pmap_ps_enabled(pmap))
4655 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4657 p = vm_page_lookup(object, pindex);
4658 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4659 ("pmap_object_init_pt: invalid page %p", p));
4660 pat_mode = p->md.pat_mode;
4663 * Abort the mapping if the first page is not physically
4664 * aligned to a 2MB page boundary.
4666 ptepa = VM_PAGE_TO_PHYS(p);
4667 if (ptepa & (NBPDR - 1))
4671 * Skip the first page. Abort the mapping if the rest of
4672 * the pages are not physically contiguous or have differing
4673 * memory attributes.
4675 p = TAILQ_NEXT(p, listq);
4676 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4678 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4679 ("pmap_object_init_pt: invalid page %p", p));
4680 if (pa != VM_PAGE_TO_PHYS(p) ||
4681 pat_mode != p->md.pat_mode)
4683 p = TAILQ_NEXT(p, listq);
4687 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4688 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4689 * will not affect the termination of this loop.
4692 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4693 pa < ptepa + size; pa += NBPDR) {
4694 pdpg = pmap_allocpde(pmap, addr, NULL);
4697 * The creation of mappings below is only an
4698 * optimization. If a page directory page
4699 * cannot be allocated without blocking,
4700 * continue on to the next mapping rather than
4706 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4707 pde = &pde[pmap_pde_index(addr)];
4708 if ((*pde & PG_V) == 0) {
4709 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4710 PG_U | PG_RW | PG_V);
4711 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4712 atomic_add_long(&pmap_pde_mappings, 1);
4714 /* Continue on if the PDE is already valid. */
4716 KASSERT(pdpg->wire_count > 0,
4717 ("pmap_object_init_pt: missing reference "
4718 "to page directory page, va: 0x%lx", addr));
4727 * Clear the wired attribute from the mappings for the specified range of
4728 * addresses in the given pmap. Every valid mapping within that range
4729 * must have the wired attribute set. In contrast, invalid mappings
4730 * cannot have the wired attribute set, so they are ignored.
4732 * The wired attribute of the page table entry is not a hardware feature,
4733 * so there is no need to invalidate any TLB entries.
4736 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4738 vm_offset_t va_next;
4739 pml4_entry_t *pml4e;
4742 pt_entry_t *pte, PG_V;
4743 boolean_t pv_lists_locked;
4745 PG_V = pmap_valid_bit(pmap);
4746 pv_lists_locked = FALSE;
4749 for (; sva < eva; sva = va_next) {
4750 pml4e = pmap_pml4e(pmap, sva);
4751 if ((*pml4e & PG_V) == 0) {
4752 va_next = (sva + NBPML4) & ~PML4MASK;
4757 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4758 if ((*pdpe & PG_V) == 0) {
4759 va_next = (sva + NBPDP) & ~PDPMASK;
4764 va_next = (sva + NBPDR) & ~PDRMASK;
4767 pde = pmap_pdpe_to_pde(pdpe, sva);
4768 if ((*pde & PG_V) == 0)
4770 if ((*pde & PG_PS) != 0) {
4771 if ((*pde & PG_W) == 0)
4772 panic("pmap_unwire: pde %#jx is missing PG_W",
4776 * Are we unwiring the entire large page? If not,
4777 * demote the mapping and fall through.
4779 if (sva + NBPDR == va_next && eva >= va_next) {
4780 atomic_clear_long(pde, PG_W);
4781 pmap->pm_stats.wired_count -= NBPDR /
4785 if (!pv_lists_locked) {
4786 pv_lists_locked = TRUE;
4787 if (!rw_try_rlock(&pvh_global_lock)) {
4789 rw_rlock(&pvh_global_lock);
4794 if (!pmap_demote_pde(pmap, pde, sva))
4795 panic("pmap_unwire: demotion failed");
4800 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4802 if ((*pte & PG_V) == 0)
4804 if ((*pte & PG_W) == 0)
4805 panic("pmap_unwire: pte %#jx is missing PG_W",
4809 * PG_W must be cleared atomically. Although the pmap
4810 * lock synchronizes access to PG_W, another processor
4811 * could be setting PG_M and/or PG_A concurrently.
4813 atomic_clear_long(pte, PG_W);
4814 pmap->pm_stats.wired_count--;
4817 if (pv_lists_locked)
4818 rw_runlock(&pvh_global_lock);
4823 * Copy the range specified by src_addr/len
4824 * from the source map to the range dst_addr/len
4825 * in the destination map.
4827 * This routine is only advisory and need not do anything.
4831 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4832 vm_offset_t src_addr)
4834 struct rwlock *lock;
4835 struct spglist free;
4837 vm_offset_t end_addr = src_addr + len;
4838 vm_offset_t va_next;
4839 pt_entry_t PG_A, PG_M, PG_V;
4841 if (dst_addr != src_addr)
4844 if (dst_pmap->pm_type != src_pmap->pm_type)
4848 * EPT page table entries that require emulation of A/D bits are
4849 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4850 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4851 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4852 * implementations flag an EPT misconfiguration for exec-only
4853 * mappings we skip this function entirely for emulated pmaps.
4855 if (pmap_emulate_ad_bits(dst_pmap))
4859 rw_rlock(&pvh_global_lock);
4860 if (dst_pmap < src_pmap) {
4861 PMAP_LOCK(dst_pmap);
4862 PMAP_LOCK(src_pmap);
4864 PMAP_LOCK(src_pmap);
4865 PMAP_LOCK(dst_pmap);
4868 PG_A = pmap_accessed_bit(dst_pmap);
4869 PG_M = pmap_modified_bit(dst_pmap);
4870 PG_V = pmap_valid_bit(dst_pmap);
4872 for (addr = src_addr; addr < end_addr; addr = va_next) {
4873 pt_entry_t *src_pte, *dst_pte;
4874 vm_page_t dstmpde, dstmpte, srcmpte;
4875 pml4_entry_t *pml4e;
4877 pd_entry_t srcptepaddr, *pde;
4879 KASSERT(addr < UPT_MIN_ADDRESS,
4880 ("pmap_copy: invalid to pmap_copy page tables"));
4882 pml4e = pmap_pml4e(src_pmap, addr);
4883 if ((*pml4e & PG_V) == 0) {
4884 va_next = (addr + NBPML4) & ~PML4MASK;
4890 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4891 if ((*pdpe & PG_V) == 0) {
4892 va_next = (addr + NBPDP) & ~PDPMASK;
4898 va_next = (addr + NBPDR) & ~PDRMASK;
4902 pde = pmap_pdpe_to_pde(pdpe, addr);
4904 if (srcptepaddr == 0)
4907 if (srcptepaddr & PG_PS) {
4908 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4910 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4911 if (dstmpde == NULL)
4913 pde = (pd_entry_t *)
4914 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4915 pde = &pde[pmap_pde_index(addr)];
4916 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4917 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4918 PG_PS_FRAME, &lock))) {
4919 *pde = srcptepaddr & ~PG_W;
4920 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4921 atomic_add_long(&pmap_pde_mappings, 1);
4923 dstmpde->wire_count--;
4927 srcptepaddr &= PG_FRAME;
4928 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4929 KASSERT(srcmpte->wire_count > 0,
4930 ("pmap_copy: source page table page is unused"));
4932 if (va_next > end_addr)
4935 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4936 src_pte = &src_pte[pmap_pte_index(addr)];
4938 while (addr < va_next) {
4942 * we only virtual copy managed pages
4944 if ((ptetemp & PG_MANAGED) != 0) {
4945 if (dstmpte != NULL &&
4946 dstmpte->pindex == pmap_pde_pindex(addr))
4947 dstmpte->wire_count++;
4948 else if ((dstmpte = pmap_allocpte(dst_pmap,
4949 addr, NULL)) == NULL)
4951 dst_pte = (pt_entry_t *)
4952 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4953 dst_pte = &dst_pte[pmap_pte_index(addr)];
4954 if (*dst_pte == 0 &&
4955 pmap_try_insert_pv_entry(dst_pmap, addr,
4956 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4959 * Clear the wired, modified, and
4960 * accessed (referenced) bits
4963 *dst_pte = ptetemp & ~(PG_W | PG_M |
4965 pmap_resident_count_inc(dst_pmap, 1);
4968 if (pmap_unwire_ptp(dst_pmap, addr,
4970 pmap_invalidate_page(dst_pmap,
4972 pmap_free_zero_pages(&free);
4976 if (dstmpte->wire_count >= srcmpte->wire_count)
4986 rw_runlock(&pvh_global_lock);
4987 PMAP_UNLOCK(src_pmap);
4988 PMAP_UNLOCK(dst_pmap);
4992 * pmap_zero_page zeros the specified hardware page by mapping
4993 * the page into KVM and using bzero to clear its contents.
4996 pmap_zero_page(vm_page_t m)
4998 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5000 pagezero((void *)va);
5004 * pmap_zero_page_area zeros the specified hardware page by mapping
5005 * the page into KVM and using bzero to clear its contents.
5007 * off and size may not cover an area beyond a single hardware page.
5010 pmap_zero_page_area(vm_page_t m, int off, int size)
5012 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5014 if (off == 0 && size == PAGE_SIZE)
5015 pagezero((void *)va);
5017 bzero((char *)va + off, size);
5021 * pmap_zero_page_idle zeros the specified hardware page by mapping
5022 * the page into KVM and using bzero to clear its contents. This
5023 * is intended to be called from the vm_pagezero process only and
5027 pmap_zero_page_idle(vm_page_t m)
5029 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5031 pagezero((void *)va);
5035 * pmap_copy_page copies the specified (machine independent)
5036 * page by mapping the page into virtual memory and using
5037 * bcopy to copy the page, one machine dependent page at a
5041 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5043 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5044 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5046 pagecopy((void *)src, (void *)dst);
5049 int unmapped_buf_allowed = 1;
5052 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5053 vm_offset_t b_offset, int xfersize)
5057 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5061 while (xfersize > 0) {
5062 a_pg_offset = a_offset & PAGE_MASK;
5063 pages[0] = ma[a_offset >> PAGE_SHIFT];
5064 b_pg_offset = b_offset & PAGE_MASK;
5065 pages[1] = mb[b_offset >> PAGE_SHIFT];
5066 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5067 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5068 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5069 a_cp = (char *)vaddr[0] + a_pg_offset;
5070 b_cp = (char *)vaddr[1] + b_pg_offset;
5071 bcopy(a_cp, b_cp, cnt);
5072 if (__predict_false(mapped))
5073 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5081 * Returns true if the pmap's pv is one of the first
5082 * 16 pvs linked to from this page. This count may
5083 * be changed upwards or downwards in the future; it
5084 * is only necessary that true be returned for a small
5085 * subset of pmaps for proper page aging.
5088 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5090 struct md_page *pvh;
5091 struct rwlock *lock;
5096 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5097 ("pmap_page_exists_quick: page %p is not managed", m));
5099 rw_rlock(&pvh_global_lock);
5100 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5102 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5103 if (PV_PMAP(pv) == pmap) {
5111 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5112 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5113 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5114 if (PV_PMAP(pv) == pmap) {
5124 rw_runlock(&pvh_global_lock);
5129 * pmap_page_wired_mappings:
5131 * Return the number of managed mappings to the given physical page
5135 pmap_page_wired_mappings(vm_page_t m)
5137 struct rwlock *lock;
5138 struct md_page *pvh;
5142 int count, md_gen, pvh_gen;
5144 if ((m->oflags & VPO_UNMANAGED) != 0)
5146 rw_rlock(&pvh_global_lock);
5147 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5151 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5153 if (!PMAP_TRYLOCK(pmap)) {
5154 md_gen = m->md.pv_gen;
5158 if (md_gen != m->md.pv_gen) {
5163 pte = pmap_pte(pmap, pv->pv_va);
5164 if ((*pte & PG_W) != 0)
5168 if ((m->flags & PG_FICTITIOUS) == 0) {
5169 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5170 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5172 if (!PMAP_TRYLOCK(pmap)) {
5173 md_gen = m->md.pv_gen;
5174 pvh_gen = pvh->pv_gen;
5178 if (md_gen != m->md.pv_gen ||
5179 pvh_gen != pvh->pv_gen) {
5184 pte = pmap_pde(pmap, pv->pv_va);
5185 if ((*pte & PG_W) != 0)
5191 rw_runlock(&pvh_global_lock);
5196 * Returns TRUE if the given page is mapped individually or as part of
5197 * a 2mpage. Otherwise, returns FALSE.
5200 pmap_page_is_mapped(vm_page_t m)
5202 struct rwlock *lock;
5205 if ((m->oflags & VPO_UNMANAGED) != 0)
5207 rw_rlock(&pvh_global_lock);
5208 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5210 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5211 ((m->flags & PG_FICTITIOUS) == 0 &&
5212 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5214 rw_runlock(&pvh_global_lock);
5219 * Destroy all managed, non-wired mappings in the given user-space
5220 * pmap. This pmap cannot be active on any processor besides the
5223 * This function cannot be applied to the kernel pmap. Moreover, it
5224 * is not intended for general use. It is only to be used during
5225 * process termination. Consequently, it can be implemented in ways
5226 * that make it faster than pmap_remove(). First, it can more quickly
5227 * destroy mappings by iterating over the pmap's collection of PV
5228 * entries, rather than searching the page table. Second, it doesn't
5229 * have to test and clear the page table entries atomically, because
5230 * no processor is currently accessing the user address space. In
5231 * particular, a page table entry's dirty bit won't change state once
5232 * this function starts.
5235 pmap_remove_pages(pmap_t pmap)
5238 pt_entry_t *pte, tpte;
5239 pt_entry_t PG_M, PG_RW, PG_V;
5240 struct spglist free;
5241 vm_page_t m, mpte, mt;
5243 struct md_page *pvh;
5244 struct pv_chunk *pc, *npc;
5245 struct rwlock *lock;
5247 uint64_t inuse, bitmask;
5248 int allfree, field, freed, idx;
5249 boolean_t superpage;
5253 * Assert that the given pmap is only active on the current
5254 * CPU. Unfortunately, we cannot block another CPU from
5255 * activating the pmap while this function is executing.
5257 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5260 cpuset_t other_cpus;
5262 other_cpus = all_cpus;
5264 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5265 CPU_AND(&other_cpus, &pmap->pm_active);
5267 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5272 PG_M = pmap_modified_bit(pmap);
5273 PG_V = pmap_valid_bit(pmap);
5274 PG_RW = pmap_rw_bit(pmap);
5277 rw_rlock(&pvh_global_lock);
5279 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5282 for (field = 0; field < _NPCM; field++) {
5283 inuse = ~pc->pc_map[field] & pc_freemask[field];
5284 while (inuse != 0) {
5286 bitmask = 1UL << bit;
5287 idx = field * 64 + bit;
5288 pv = &pc->pc_pventry[idx];
5291 pte = pmap_pdpe(pmap, pv->pv_va);
5293 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5295 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5298 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5300 pte = &pte[pmap_pte_index(pv->pv_va)];
5304 * Keep track whether 'tpte' is a
5305 * superpage explicitly instead of
5306 * relying on PG_PS being set.
5308 * This is because PG_PS is numerically
5309 * identical to PG_PTE_PAT and thus a
5310 * regular page could be mistaken for
5316 if ((tpte & PG_V) == 0) {
5317 panic("bad pte va %lx pte %lx",
5322 * We cannot remove wired pages from a process' mapping at this time
5330 pa = tpte & PG_PS_FRAME;
5332 pa = tpte & PG_FRAME;
5334 m = PHYS_TO_VM_PAGE(pa);
5335 KASSERT(m->phys_addr == pa,
5336 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5337 m, (uintmax_t)m->phys_addr,
5340 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5341 m < &vm_page_array[vm_page_array_size],
5342 ("pmap_remove_pages: bad tpte %#jx",
5348 * Update the vm_page_t clean/reference bits.
5350 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5352 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5358 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5361 pc->pc_map[field] |= bitmask;
5363 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5364 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5365 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5367 if (TAILQ_EMPTY(&pvh->pv_list)) {
5368 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5369 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5370 TAILQ_EMPTY(&mt->md.pv_list))
5371 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5373 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5375 pmap_remove_pt_page(pmap, mpte);
5376 pmap_resident_count_dec(pmap, 1);
5377 KASSERT(mpte->wire_count == NPTEPG,
5378 ("pmap_remove_pages: pte page wire count error"));
5379 mpte->wire_count = 0;
5380 pmap_add_delayed_free_list(mpte, &free, FALSE);
5381 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
5384 pmap_resident_count_dec(pmap, 1);
5385 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5387 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5388 TAILQ_EMPTY(&m->md.pv_list) &&
5389 (m->flags & PG_FICTITIOUS) == 0) {
5390 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5391 if (TAILQ_EMPTY(&pvh->pv_list))
5392 vm_page_aflag_clear(m, PGA_WRITEABLE);
5395 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5399 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5400 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5401 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5403 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5409 pmap_invalidate_all(pmap);
5410 rw_runlock(&pvh_global_lock);
5412 pmap_free_zero_pages(&free);
5416 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5418 struct rwlock *lock;
5420 struct md_page *pvh;
5421 pt_entry_t *pte, mask;
5422 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5424 int md_gen, pvh_gen;
5428 rw_rlock(&pvh_global_lock);
5429 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5432 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5434 if (!PMAP_TRYLOCK(pmap)) {
5435 md_gen = m->md.pv_gen;
5439 if (md_gen != m->md.pv_gen) {
5444 pte = pmap_pte(pmap, pv->pv_va);
5447 PG_M = pmap_modified_bit(pmap);
5448 PG_RW = pmap_rw_bit(pmap);
5449 mask |= PG_RW | PG_M;
5452 PG_A = pmap_accessed_bit(pmap);
5453 PG_V = pmap_valid_bit(pmap);
5454 mask |= PG_V | PG_A;
5456 rv = (*pte & mask) == mask;
5461 if ((m->flags & PG_FICTITIOUS) == 0) {
5462 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5463 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5465 if (!PMAP_TRYLOCK(pmap)) {
5466 md_gen = m->md.pv_gen;
5467 pvh_gen = pvh->pv_gen;
5471 if (md_gen != m->md.pv_gen ||
5472 pvh_gen != pvh->pv_gen) {
5477 pte = pmap_pde(pmap, pv->pv_va);
5480 PG_M = pmap_modified_bit(pmap);
5481 PG_RW = pmap_rw_bit(pmap);
5482 mask |= PG_RW | PG_M;
5485 PG_A = pmap_accessed_bit(pmap);
5486 PG_V = pmap_valid_bit(pmap);
5487 mask |= PG_V | PG_A;
5489 rv = (*pte & mask) == mask;
5497 rw_runlock(&pvh_global_lock);
5504 * Return whether or not the specified physical page was modified
5505 * in any physical maps.
5508 pmap_is_modified(vm_page_t m)
5511 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5512 ("pmap_is_modified: page %p is not managed", m));
5515 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5516 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5517 * is clear, no PTEs can have PG_M set.
5519 VM_OBJECT_ASSERT_WLOCKED(m->object);
5520 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5522 return (pmap_page_test_mappings(m, FALSE, TRUE));
5526 * pmap_is_prefaultable:
5528 * Return whether or not the specified virtual address is eligible
5532 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5535 pt_entry_t *pte, PG_V;
5538 PG_V = pmap_valid_bit(pmap);
5541 pde = pmap_pde(pmap, addr);
5542 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5543 pte = pmap_pde_to_pte(pde, addr);
5544 rv = (*pte & PG_V) == 0;
5551 * pmap_is_referenced:
5553 * Return whether or not the specified physical page was referenced
5554 * in any physical maps.
5557 pmap_is_referenced(vm_page_t m)
5560 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5561 ("pmap_is_referenced: page %p is not managed", m));
5562 return (pmap_page_test_mappings(m, TRUE, FALSE));
5566 * Clear the write and modified bits in each of the given page's mappings.
5569 pmap_remove_write(vm_page_t m)
5571 struct md_page *pvh;
5573 struct rwlock *lock;
5574 pv_entry_t next_pv, pv;
5576 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5578 int pvh_gen, md_gen;
5580 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5581 ("pmap_remove_write: page %p is not managed", m));
5584 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5585 * set by another thread while the object is locked. Thus,
5586 * if PGA_WRITEABLE is clear, no page table entries need updating.
5588 VM_OBJECT_ASSERT_WLOCKED(m->object);
5589 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5591 rw_rlock(&pvh_global_lock);
5592 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5593 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5596 if ((m->flags & PG_FICTITIOUS) != 0)
5597 goto small_mappings;
5598 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5600 if (!PMAP_TRYLOCK(pmap)) {
5601 pvh_gen = pvh->pv_gen;
5605 if (pvh_gen != pvh->pv_gen) {
5611 PG_RW = pmap_rw_bit(pmap);
5613 pde = pmap_pde(pmap, va);
5614 if ((*pde & PG_RW) != 0)
5615 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5616 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5617 ("inconsistent pv lock %p %p for page %p",
5618 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5622 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5624 if (!PMAP_TRYLOCK(pmap)) {
5625 pvh_gen = pvh->pv_gen;
5626 md_gen = m->md.pv_gen;
5630 if (pvh_gen != pvh->pv_gen ||
5631 md_gen != m->md.pv_gen) {
5637 PG_M = pmap_modified_bit(pmap);
5638 PG_RW = pmap_rw_bit(pmap);
5639 pde = pmap_pde(pmap, pv->pv_va);
5640 KASSERT((*pde & PG_PS) == 0,
5641 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5643 pte = pmap_pde_to_pte(pde, pv->pv_va);
5646 if (oldpte & PG_RW) {
5647 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5650 if ((oldpte & PG_M) != 0)
5652 pmap_invalidate_page(pmap, pv->pv_va);
5657 vm_page_aflag_clear(m, PGA_WRITEABLE);
5658 rw_runlock(&pvh_global_lock);
5661 static __inline boolean_t
5662 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5665 if (!pmap_emulate_ad_bits(pmap))
5668 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5671 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
5672 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5673 * if the EPT_PG_WRITE bit is set.
5675 if ((pte & EPT_PG_WRITE) != 0)
5679 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5681 if ((pte & EPT_PG_EXECUTE) == 0 ||
5682 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5688 #define PMAP_TS_REFERENCED_MAX 5
5691 * pmap_ts_referenced:
5693 * Return a count of reference bits for a page, clearing those bits.
5694 * It is not necessary for every reference bit to be cleared, but it
5695 * is necessary that 0 only be returned when there are truly no
5696 * reference bits set.
5698 * XXX: The exact number of bits to check and clear is a matter that
5699 * should be tested and standardized at some point in the future for
5700 * optimal aging of shared pages.
5703 pmap_ts_referenced(vm_page_t m)
5705 struct md_page *pvh;
5708 struct rwlock *lock;
5709 pd_entry_t oldpde, *pde;
5710 pt_entry_t *pte, PG_A;
5713 int cleared, md_gen, not_cleared, pvh_gen;
5714 struct spglist free;
5717 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5718 ("pmap_ts_referenced: page %p is not managed", m));
5721 pa = VM_PAGE_TO_PHYS(m);
5722 lock = PHYS_TO_PV_LIST_LOCK(pa);
5723 pvh = pa_to_pvh(pa);
5724 rw_rlock(&pvh_global_lock);
5728 if ((m->flags & PG_FICTITIOUS) != 0 ||
5729 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5730 goto small_mappings;
5736 if (!PMAP_TRYLOCK(pmap)) {
5737 pvh_gen = pvh->pv_gen;
5741 if (pvh_gen != pvh->pv_gen) {
5746 PG_A = pmap_accessed_bit(pmap);
5748 pde = pmap_pde(pmap, pv->pv_va);
5750 if ((*pde & PG_A) != 0) {
5752 * Since this reference bit is shared by 512 4KB
5753 * pages, it should not be cleared every time it is
5754 * tested. Apply a simple "hash" function on the
5755 * physical page number, the virtual superpage number,
5756 * and the pmap address to select one 4KB page out of
5757 * the 512 on which testing the reference bit will
5758 * result in clearing that reference bit. This
5759 * function is designed to avoid the selection of the
5760 * same 4KB page for every 2MB page mapping.
5762 * On demotion, a mapping that hasn't been referenced
5763 * is simply destroyed. To avoid the possibility of a
5764 * subsequent page fault on a demoted wired mapping,
5765 * always leave its reference bit set. Moreover,
5766 * since the superpage is wired, the current state of
5767 * its reference bit won't affect page replacement.
5769 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5770 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5771 (*pde & PG_W) == 0) {
5772 if (safe_to_clear_referenced(pmap, oldpde)) {
5773 atomic_clear_long(pde, PG_A);
5774 pmap_invalidate_page(pmap, pv->pv_va);
5776 } else if (pmap_demote_pde_locked(pmap, pde,
5777 pv->pv_va, &lock)) {
5779 * Remove the mapping to a single page
5780 * so that a subsequent access may
5781 * repromote. Since the underlying
5782 * page table page is fully populated,
5783 * this removal never frees a page
5787 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5789 pte = pmap_pde_to_pte(pde, va);
5790 pmap_remove_pte(pmap, pte, va, *pde,
5792 pmap_invalidate_page(pmap, va);
5798 * The superpage mapping was removed
5799 * entirely and therefore 'pv' is no
5807 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5808 ("inconsistent pv lock %p %p for page %p",
5809 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5814 /* Rotate the PV list if it has more than one entry. */
5815 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5816 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5817 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5820 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5822 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5824 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5831 if (!PMAP_TRYLOCK(pmap)) {
5832 pvh_gen = pvh->pv_gen;
5833 md_gen = m->md.pv_gen;
5837 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5842 PG_A = pmap_accessed_bit(pmap);
5843 pde = pmap_pde(pmap, pv->pv_va);
5844 KASSERT((*pde & PG_PS) == 0,
5845 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5847 pte = pmap_pde_to_pte(pde, pv->pv_va);
5848 if ((*pte & PG_A) != 0) {
5849 if (safe_to_clear_referenced(pmap, *pte)) {
5850 atomic_clear_long(pte, PG_A);
5851 pmap_invalidate_page(pmap, pv->pv_va);
5853 } else if ((*pte & PG_W) == 0) {
5855 * Wired pages cannot be paged out so
5856 * doing accessed bit emulation for
5857 * them is wasted effort. We do the
5858 * hard work for unwired pages only.
5860 pmap_remove_pte(pmap, pte, pv->pv_va,
5861 *pde, &free, &lock);
5862 pmap_invalidate_page(pmap, pv->pv_va);
5867 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5868 ("inconsistent pv lock %p %p for page %p",
5869 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5874 /* Rotate the PV list if it has more than one entry. */
5875 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5876 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5877 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5880 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5881 not_cleared < PMAP_TS_REFERENCED_MAX);
5884 rw_runlock(&pvh_global_lock);
5885 pmap_free_zero_pages(&free);
5886 return (cleared + not_cleared);
5890 * Apply the given advice to the specified range of addresses within the
5891 * given pmap. Depending on the advice, clear the referenced and/or
5892 * modified flags in each mapping and set the mapped page's dirty field.
5895 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5897 struct rwlock *lock;
5898 pml4_entry_t *pml4e;
5900 pd_entry_t oldpde, *pde;
5901 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5902 vm_offset_t va_next;
5904 boolean_t anychanged, pv_lists_locked;
5906 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5910 * A/D bit emulation requires an alternate code path when clearing
5911 * the modified and accessed bits below. Since this function is
5912 * advisory in nature we skip it entirely for pmaps that require
5913 * A/D bit emulation.
5915 if (pmap_emulate_ad_bits(pmap))
5918 PG_A = pmap_accessed_bit(pmap);
5919 PG_G = pmap_global_bit(pmap);
5920 PG_M = pmap_modified_bit(pmap);
5921 PG_V = pmap_valid_bit(pmap);
5922 PG_RW = pmap_rw_bit(pmap);
5924 pv_lists_locked = FALSE;
5928 for (; sva < eva; sva = va_next) {
5929 pml4e = pmap_pml4e(pmap, sva);
5930 if ((*pml4e & PG_V) == 0) {
5931 va_next = (sva + NBPML4) & ~PML4MASK;
5936 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5937 if ((*pdpe & PG_V) == 0) {
5938 va_next = (sva + NBPDP) & ~PDPMASK;
5943 va_next = (sva + NBPDR) & ~PDRMASK;
5946 pde = pmap_pdpe_to_pde(pdpe, sva);
5948 if ((oldpde & PG_V) == 0)
5950 else if ((oldpde & PG_PS) != 0) {
5951 if ((oldpde & PG_MANAGED) == 0)
5953 if (!pv_lists_locked) {
5954 pv_lists_locked = TRUE;
5955 if (!rw_try_rlock(&pvh_global_lock)) {
5957 pmap_invalidate_all(pmap);
5959 rw_rlock(&pvh_global_lock);
5964 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5969 * The large page mapping was destroyed.
5975 * Unless the page mappings are wired, remove the
5976 * mapping to a single page so that a subsequent
5977 * access may repromote. Since the underlying page
5978 * table page is fully populated, this removal never
5979 * frees a page table page.
5981 if ((oldpde & PG_W) == 0) {
5982 pte = pmap_pde_to_pte(pde, sva);
5983 KASSERT((*pte & PG_V) != 0,
5984 ("pmap_advise: invalid PTE"));
5985 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
5994 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5996 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
5999 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6000 if (advice == MADV_DONTNEED) {
6002 * Future calls to pmap_is_modified()
6003 * can be avoided by making the page
6006 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6009 atomic_clear_long(pte, PG_M | PG_A);
6010 } else if ((*pte & PG_A) != 0)
6011 atomic_clear_long(pte, PG_A);
6014 if ((*pte & PG_G) != 0)
6015 pmap_invalidate_page(pmap, sva);
6021 pmap_invalidate_all(pmap);
6022 if (pv_lists_locked)
6023 rw_runlock(&pvh_global_lock);
6028 * Clear the modify bits on the specified physical page.
6031 pmap_clear_modify(vm_page_t m)
6033 struct md_page *pvh;
6035 pv_entry_t next_pv, pv;
6036 pd_entry_t oldpde, *pde;
6037 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6038 struct rwlock *lock;
6040 int md_gen, pvh_gen;
6042 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6043 ("pmap_clear_modify: page %p is not managed", m));
6044 VM_OBJECT_ASSERT_WLOCKED(m->object);
6045 KASSERT(!vm_page_xbusied(m),
6046 ("pmap_clear_modify: page %p is exclusive busied", m));
6049 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6050 * If the object containing the page is locked and the page is not
6051 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6053 if ((m->aflags & PGA_WRITEABLE) == 0)
6055 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6056 rw_rlock(&pvh_global_lock);
6057 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6060 if ((m->flags & PG_FICTITIOUS) != 0)
6061 goto small_mappings;
6062 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6064 if (!PMAP_TRYLOCK(pmap)) {
6065 pvh_gen = pvh->pv_gen;
6069 if (pvh_gen != pvh->pv_gen) {
6074 PG_M = pmap_modified_bit(pmap);
6075 PG_V = pmap_valid_bit(pmap);
6076 PG_RW = pmap_rw_bit(pmap);
6078 pde = pmap_pde(pmap, va);
6080 if ((oldpde & PG_RW) != 0) {
6081 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6082 if ((oldpde & PG_W) == 0) {
6084 * Write protect the mapping to a
6085 * single page so that a subsequent
6086 * write access may repromote.
6088 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6090 pte = pmap_pde_to_pte(pde, va);
6092 if ((oldpte & PG_V) != 0) {
6093 while (!atomic_cmpset_long(pte,
6095 oldpte & ~(PG_M | PG_RW)))
6098 pmap_invalidate_page(pmap, va);
6106 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6108 if (!PMAP_TRYLOCK(pmap)) {
6109 md_gen = m->md.pv_gen;
6110 pvh_gen = pvh->pv_gen;
6114 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6119 PG_M = pmap_modified_bit(pmap);
6120 PG_RW = pmap_rw_bit(pmap);
6121 pde = pmap_pde(pmap, pv->pv_va);
6122 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6123 " a 2mpage in page %p's pv list", m));
6124 pte = pmap_pde_to_pte(pde, pv->pv_va);
6125 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6126 atomic_clear_long(pte, PG_M);
6127 pmap_invalidate_page(pmap, pv->pv_va);
6132 rw_runlock(&pvh_global_lock);
6136 * Miscellaneous support routines follow
6139 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6140 static __inline void
6141 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6146 * The cache mode bits are all in the low 32-bits of the
6147 * PTE, so we can just spin on updating the low 32-bits.
6150 opte = *(u_int *)pte;
6151 npte = opte & ~mask;
6153 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6156 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6157 static __inline void
6158 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6163 * The cache mode bits are all in the low 32-bits of the
6164 * PDE, so we can just spin on updating the low 32-bits.
6167 opde = *(u_int *)pde;
6168 npde = opde & ~mask;
6170 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6174 * Map a set of physical memory pages into the kernel virtual
6175 * address space. Return a pointer to where it is mapped. This
6176 * routine is intended to be used for mapping device memory,
6180 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6182 struct pmap_preinit_mapping *ppim;
6183 vm_offset_t va, offset;
6187 offset = pa & PAGE_MASK;
6188 size = round_page(offset + size);
6189 pa = trunc_page(pa);
6191 if (!pmap_initialized) {
6193 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6194 ppim = pmap_preinit_mapping + i;
6195 if (ppim->va == 0) {
6199 ppim->va = virtual_avail;
6200 virtual_avail += size;
6206 panic("%s: too many preinit mappings", __func__);
6209 * If we have a preinit mapping, re-use it.
6211 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6212 ppim = pmap_preinit_mapping + i;
6213 if (ppim->pa == pa && ppim->sz == size &&
6215 return ((void *)(ppim->va + offset));
6218 * If the specified range of physical addresses fits within
6219 * the direct map window, use the direct map.
6221 if (pa < dmaplimit && pa + size < dmaplimit) {
6222 va = PHYS_TO_DMAP(pa);
6223 if (!pmap_change_attr(va, size, mode))
6224 return ((void *)(va + offset));
6226 va = kva_alloc(size);
6228 panic("%s: Couldn't allocate KVA", __func__);
6230 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6231 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6232 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6233 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6234 return ((void *)(va + offset));
6238 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6241 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6245 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6248 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6252 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6254 struct pmap_preinit_mapping *ppim;
6258 /* If we gave a direct map region in pmap_mapdev, do nothing */
6259 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6261 offset = va & PAGE_MASK;
6262 size = round_page(offset + size);
6263 va = trunc_page(va);
6264 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6265 ppim = pmap_preinit_mapping + i;
6266 if (ppim->va == va && ppim->sz == size) {
6267 if (pmap_initialized)
6273 if (va + size == virtual_avail)
6278 if (pmap_initialized)
6283 * Tries to demote a 1GB page mapping.
6286 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6288 pdp_entry_t newpdpe, oldpdpe;
6289 pd_entry_t *firstpde, newpde, *pde;
6290 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6294 PG_A = pmap_accessed_bit(pmap);
6295 PG_M = pmap_modified_bit(pmap);
6296 PG_V = pmap_valid_bit(pmap);
6297 PG_RW = pmap_rw_bit(pmap);
6299 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6301 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6302 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6303 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6304 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6305 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6306 " in pmap %p", va, pmap);
6309 mpdepa = VM_PAGE_TO_PHYS(mpde);
6310 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6311 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6312 KASSERT((oldpdpe & PG_A) != 0,
6313 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6314 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6315 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6319 * Initialize the page directory page.
6321 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6327 * Demote the mapping.
6332 * Invalidate a stale recursive mapping of the page directory page.
6334 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6336 pmap_pdpe_demotions++;
6337 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6338 " in pmap %p", va, pmap);
6343 * Sets the memory attribute for the specified page.
6346 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6349 m->md.pat_mode = ma;
6352 * If "m" is a normal page, update its direct mapping. This update
6353 * can be relied upon to perform any cache operations that are
6354 * required for data coherence.
6356 if ((m->flags & PG_FICTITIOUS) == 0 &&
6357 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6359 panic("memory attribute change on the direct map failed");
6363 * Changes the specified virtual address range's memory type to that given by
6364 * the parameter "mode". The specified virtual address range must be
6365 * completely contained within either the direct map or the kernel map. If
6366 * the virtual address range is contained within the kernel map, then the
6367 * memory type for each of the corresponding ranges of the direct map is also
6368 * changed. (The corresponding ranges of the direct map are those ranges that
6369 * map the same physical pages as the specified virtual address range.) These
6370 * changes to the direct map are necessary because Intel describes the
6371 * behavior of their processors as "undefined" if two or more mappings to the
6372 * same physical page have different memory types.
6374 * Returns zero if the change completed successfully, and either EINVAL or
6375 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6376 * of the virtual address range was not mapped, and ENOMEM is returned if
6377 * there was insufficient memory available to complete the change. In the
6378 * latter case, the memory type may have been changed on some part of the
6379 * virtual address range or the direct map.
6382 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6386 PMAP_LOCK(kernel_pmap);
6387 error = pmap_change_attr_locked(va, size, mode);
6388 PMAP_UNLOCK(kernel_pmap);
6393 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6395 vm_offset_t base, offset, tmpva;
6396 vm_paddr_t pa_start, pa_end;
6400 int cache_bits_pte, cache_bits_pde, error;
6403 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6404 base = trunc_page(va);
6405 offset = va & PAGE_MASK;
6406 size = round_page(offset + size);
6409 * Only supported on kernel virtual addresses, including the direct
6410 * map but excluding the recursive map.
6412 if (base < DMAP_MIN_ADDRESS)
6415 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6416 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6420 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6421 * into 4KB pages if required.
6423 for (tmpva = base; tmpva < base + size; ) {
6424 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6425 if (pdpe == NULL || *pdpe == 0)
6427 if (*pdpe & PG_PS) {
6429 * If the current 1GB page already has the required
6430 * memory type, then we need not demote this page. Just
6431 * increment tmpva to the next 1GB page frame.
6433 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6434 tmpva = trunc_1gpage(tmpva) + NBPDP;
6439 * If the current offset aligns with a 1GB page frame
6440 * and there is at least 1GB left within the range, then
6441 * we need not break down this page into 2MB pages.
6443 if ((tmpva & PDPMASK) == 0 &&
6444 tmpva + PDPMASK < base + size) {
6448 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6451 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6456 * If the current 2MB page already has the required
6457 * memory type, then we need not demote this page. Just
6458 * increment tmpva to the next 2MB page frame.
6460 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6461 tmpva = trunc_2mpage(tmpva) + NBPDR;
6466 * If the current offset aligns with a 2MB page frame
6467 * and there is at least 2MB left within the range, then
6468 * we need not break down this page into 4KB pages.
6470 if ((tmpva & PDRMASK) == 0 &&
6471 tmpva + PDRMASK < base + size) {
6475 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6478 pte = pmap_pde_to_pte(pde, tmpva);
6486 * Ok, all the pages exist, so run through them updating their
6487 * cache mode if required.
6489 pa_start = pa_end = 0;
6490 for (tmpva = base; tmpva < base + size; ) {
6491 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6492 if (*pdpe & PG_PS) {
6493 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6494 pmap_pde_attr(pdpe, cache_bits_pde,
6498 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6499 (*pdpe & PG_PS_FRAME) < dmaplimit) {
6500 if (pa_start == pa_end) {
6501 /* Start physical address run. */
6502 pa_start = *pdpe & PG_PS_FRAME;
6503 pa_end = pa_start + NBPDP;
6504 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6507 /* Run ended, update direct map. */
6508 error = pmap_change_attr_locked(
6509 PHYS_TO_DMAP(pa_start),
6510 pa_end - pa_start, mode);
6513 /* Start physical address run. */
6514 pa_start = *pdpe & PG_PS_FRAME;
6515 pa_end = pa_start + NBPDP;
6518 tmpva = trunc_1gpage(tmpva) + NBPDP;
6521 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6523 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6524 pmap_pde_attr(pde, cache_bits_pde,
6528 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6529 (*pde & PG_PS_FRAME) < dmaplimit) {
6530 if (pa_start == pa_end) {
6531 /* Start physical address run. */
6532 pa_start = *pde & PG_PS_FRAME;
6533 pa_end = pa_start + NBPDR;
6534 } else if (pa_end == (*pde & PG_PS_FRAME))
6537 /* Run ended, update direct map. */
6538 error = pmap_change_attr_locked(
6539 PHYS_TO_DMAP(pa_start),
6540 pa_end - pa_start, mode);
6543 /* Start physical address run. */
6544 pa_start = *pde & PG_PS_FRAME;
6545 pa_end = pa_start + NBPDR;
6548 tmpva = trunc_2mpage(tmpva) + NBPDR;
6550 pte = pmap_pde_to_pte(pde, tmpva);
6551 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6552 pmap_pte_attr(pte, cache_bits_pte,
6556 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6557 (*pte & PG_PS_FRAME) < dmaplimit) {
6558 if (pa_start == pa_end) {
6559 /* Start physical address run. */
6560 pa_start = *pte & PG_FRAME;
6561 pa_end = pa_start + PAGE_SIZE;
6562 } else if (pa_end == (*pte & PG_FRAME))
6563 pa_end += PAGE_SIZE;
6565 /* Run ended, update direct map. */
6566 error = pmap_change_attr_locked(
6567 PHYS_TO_DMAP(pa_start),
6568 pa_end - pa_start, mode);
6571 /* Start physical address run. */
6572 pa_start = *pte & PG_FRAME;
6573 pa_end = pa_start + PAGE_SIZE;
6579 if (error == 0 && pa_start != pa_end)
6580 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6581 pa_end - pa_start, mode);
6584 * Flush CPU caches if required to make sure any data isn't cached that
6585 * shouldn't be, etc.
6588 pmap_invalidate_range(kernel_pmap, base, tmpva);
6589 pmap_invalidate_cache_range(base, tmpva, FALSE);
6595 * Demotes any mapping within the direct map region that covers more than the
6596 * specified range of physical addresses. This range's size must be a power
6597 * of two and its starting address must be a multiple of its size. Since the
6598 * demotion does not change any attributes of the mapping, a TLB invalidation
6599 * is not mandatory. The caller may, however, request a TLB invalidation.
6602 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6611 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6612 KASSERT((base & (len - 1)) == 0,
6613 ("pmap_demote_DMAP: base is not a multiple of len"));
6614 if (len < NBPDP && base < dmaplimit) {
6615 va = PHYS_TO_DMAP(base);
6617 PMAP_LOCK(kernel_pmap);
6618 pdpe = pmap_pdpe(kernel_pmap, va);
6619 if ((*pdpe & X86_PG_V) == 0)
6620 panic("pmap_demote_DMAP: invalid PDPE");
6621 if ((*pdpe & PG_PS) != 0) {
6622 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6623 panic("pmap_demote_DMAP: PDPE failed");
6627 pde = pmap_pdpe_to_pde(pdpe, va);
6628 if ((*pde & X86_PG_V) == 0)
6629 panic("pmap_demote_DMAP: invalid PDE");
6630 if ((*pde & PG_PS) != 0) {
6631 if (!pmap_demote_pde(kernel_pmap, pde, va))
6632 panic("pmap_demote_DMAP: PDE failed");
6636 if (changed && invalidate)
6637 pmap_invalidate_page(kernel_pmap, va);
6638 PMAP_UNLOCK(kernel_pmap);
6643 * perform the pmap work for mincore
6646 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6649 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6653 PG_A = pmap_accessed_bit(pmap);
6654 PG_M = pmap_modified_bit(pmap);
6655 PG_V = pmap_valid_bit(pmap);
6656 PG_RW = pmap_rw_bit(pmap);
6660 pdep = pmap_pde(pmap, addr);
6661 if (pdep != NULL && (*pdep & PG_V)) {
6662 if (*pdep & PG_PS) {
6664 /* Compute the physical address of the 4KB page. */
6665 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6667 val = MINCORE_SUPER;
6669 pte = *pmap_pde_to_pte(pdep, addr);
6670 pa = pte & PG_FRAME;
6678 if ((pte & PG_V) != 0) {
6679 val |= MINCORE_INCORE;
6680 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6681 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6682 if ((pte & PG_A) != 0)
6683 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6685 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6686 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6687 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6688 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6689 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6692 PA_UNLOCK_COND(*locked_pa);
6698 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
6700 uint32_t gen, new_gen, pcid_next;
6702 CRITICAL_ASSERT(curthread);
6703 gen = PCPU_GET(pcid_gen);
6704 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN ||
6705 pmap->pm_pcids[cpuid].pm_gen == gen)
6706 return (CR3_PCID_SAVE);
6707 pcid_next = PCPU_GET(pcid_next);
6708 KASSERT(pcid_next <= PMAP_PCID_OVERMAX, ("cpu %d pcid_next %#x",
6710 if (pcid_next == PMAP_PCID_OVERMAX) {
6714 PCPU_SET(pcid_gen, new_gen);
6715 pcid_next = PMAP_PCID_KERN + 1;
6719 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
6720 pmap->pm_pcids[cpuid].pm_gen = new_gen;
6721 PCPU_SET(pcid_next, pcid_next + 1);
6726 pmap_activate_sw(struct thread *td)
6728 pmap_t oldpmap, pmap;
6729 uint64_t cached, cr3;
6732 oldpmap = PCPU_GET(curpmap);
6733 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6734 if (oldpmap == pmap)
6736 cpuid = PCPU_GET(cpuid);
6738 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6740 CPU_SET(cpuid, &pmap->pm_active);
6743 if (pmap_pcid_enabled) {
6744 cached = pmap_pcid_alloc(pmap, cpuid);
6745 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
6746 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
6747 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
6748 pmap->pm_pcids[cpuid].pm_pcid));
6749 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
6750 pmap == kernel_pmap,
6751 ("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
6752 td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
6753 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
6754 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
6757 PCPU_INC(pm_save_cnt);
6759 } else if (cr3 != pmap->pm_cr3) {
6760 load_cr3(pmap->pm_cr3);
6762 PCPU_SET(curpmap, pmap);
6764 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6766 CPU_CLR(cpuid, &oldpmap->pm_active);
6771 pmap_activate(struct thread *td)
6775 pmap_activate_sw(td);
6780 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6785 * Increase the starting virtual address of the given mapping if a
6786 * different alignment might result in more superpage mappings.
6789 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6790 vm_offset_t *addr, vm_size_t size)
6792 vm_offset_t superpage_offset;
6796 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6797 offset += ptoa(object->pg_color);
6798 superpage_offset = offset & PDRMASK;
6799 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6800 (*addr & PDRMASK) == superpage_offset)
6802 if ((*addr & PDRMASK) < superpage_offset)
6803 *addr = (*addr & ~PDRMASK) + superpage_offset;
6805 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6809 static unsigned long num_dirty_emulations;
6810 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6811 &num_dirty_emulations, 0, NULL);
6813 static unsigned long num_accessed_emulations;
6814 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6815 &num_accessed_emulations, 0, NULL);
6817 static unsigned long num_superpage_accessed_emulations;
6818 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6819 &num_superpage_accessed_emulations, 0, NULL);
6821 static unsigned long ad_emulation_superpage_promotions;
6822 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6823 &ad_emulation_superpage_promotions, 0, NULL);
6824 #endif /* INVARIANTS */
6827 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6830 struct rwlock *lock;
6833 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6834 boolean_t pv_lists_locked;
6836 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6837 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6839 if (!pmap_emulate_ad_bits(pmap))
6842 PG_A = pmap_accessed_bit(pmap);
6843 PG_M = pmap_modified_bit(pmap);
6844 PG_V = pmap_valid_bit(pmap);
6845 PG_RW = pmap_rw_bit(pmap);
6849 pv_lists_locked = FALSE;
6853 pde = pmap_pde(pmap, va);
6854 if (pde == NULL || (*pde & PG_V) == 0)
6857 if ((*pde & PG_PS) != 0) {
6858 if (ftype == VM_PROT_READ) {
6860 atomic_add_long(&num_superpage_accessed_emulations, 1);
6868 pte = pmap_pde_to_pte(pde, va);
6869 if ((*pte & PG_V) == 0)
6872 if (ftype == VM_PROT_WRITE) {
6873 if ((*pte & PG_RW) == 0)
6876 * Set the modified and accessed bits simultaneously.
6878 * Intel EPT PTEs that do software emulation of A/D bits map
6879 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
6880 * An EPT misconfiguration is triggered if the PTE is writable
6881 * but not readable (WR=10). This is avoided by setting PG_A
6882 * and PG_M simultaneously.
6884 *pte |= PG_M | PG_A;
6889 /* try to promote the mapping */
6890 if (va < VM_MAXUSER_ADDRESS)
6891 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6895 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6897 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6898 pmap_ps_enabled(pmap) &&
6899 (m->flags & PG_FICTITIOUS) == 0 &&
6900 vm_reserv_level_iffullpop(m) == 0) {
6901 if (!pv_lists_locked) {
6902 pv_lists_locked = TRUE;
6903 if (!rw_try_rlock(&pvh_global_lock)) {
6905 rw_rlock(&pvh_global_lock);
6909 pmap_promote_pde(pmap, pde, va, &lock);
6911 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6915 if (ftype == VM_PROT_WRITE)
6916 atomic_add_long(&num_dirty_emulations, 1);
6918 atomic_add_long(&num_accessed_emulations, 1);
6920 rv = 0; /* success */
6924 if (pv_lists_locked)
6925 rw_runlock(&pvh_global_lock);
6931 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6936 pt_entry_t *pte, PG_V;
6940 PG_V = pmap_valid_bit(pmap);
6943 pml4 = pmap_pml4e(pmap, va);
6945 if ((*pml4 & PG_V) == 0)
6948 pdp = pmap_pml4e_to_pdpe(pml4, va);
6950 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6953 pde = pmap_pdpe_to_pde(pdp, va);
6955 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6958 pte = pmap_pde_to_pte(pde, va);
6967 * Get the kernel virtual address of a set of physical pages. If there are
6968 * physical addresses not covered by the DMAP perform a transient mapping
6969 * that will be removed when calling pmap_unmap_io_transient.
6971 * \param page The pages the caller wishes to obtain the virtual
6972 * address on the kernel memory map.
6973 * \param vaddr On return contains the kernel virtual memory address
6974 * of the pages passed in the page parameter.
6975 * \param count Number of pages passed in.
6976 * \param can_fault TRUE if the thread using the mapped pages can take
6977 * page faults, FALSE otherwise.
6979 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6980 * finished or FALSE otherwise.
6984 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6985 boolean_t can_fault)
6988 boolean_t needs_mapping;
6990 int cache_bits, error, i;
6993 * Allocate any KVA space that we need, this is done in a separate
6994 * loop to prevent calling vmem_alloc while pinned.
6996 needs_mapping = FALSE;
6997 for (i = 0; i < count; i++) {
6998 paddr = VM_PAGE_TO_PHYS(page[i]);
6999 if (__predict_false(paddr >= dmaplimit)) {
7000 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7001 M_BESTFIT | M_WAITOK, &vaddr[i]);
7002 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7003 needs_mapping = TRUE;
7005 vaddr[i] = PHYS_TO_DMAP(paddr);
7009 /* Exit early if everything is covered by the DMAP */
7014 * NB: The sequence of updating a page table followed by accesses
7015 * to the corresponding pages used in the !DMAP case is subject to
7016 * the situation described in the "AMD64 Architecture Programmer's
7017 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7018 * Coherency Considerations". Therefore, issuing the INVLPG right
7019 * after modifying the PTE bits is crucial.
7023 for (i = 0; i < count; i++) {
7024 paddr = VM_PAGE_TO_PHYS(page[i]);
7025 if (paddr >= dmaplimit) {
7028 * Slow path, since we can get page faults
7029 * while mappings are active don't pin the
7030 * thread to the CPU and instead add a global
7031 * mapping visible to all CPUs.
7033 pmap_qenter(vaddr[i], &page[i], 1);
7035 pte = vtopte(vaddr[i]);
7036 cache_bits = pmap_cache_bits(kernel_pmap,
7037 page[i]->md.pat_mode, 0);
7038 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7045 return (needs_mapping);
7049 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7050 boolean_t can_fault)
7057 for (i = 0; i < count; i++) {
7058 paddr = VM_PAGE_TO_PHYS(page[i]);
7059 if (paddr >= dmaplimit) {
7061 pmap_qremove(vaddr[i], 1);
7062 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7068 pmap_quick_enter_page(vm_page_t m)
7072 paddr = VM_PAGE_TO_PHYS(m);
7073 if (paddr < dmaplimit)
7074 return (PHYS_TO_DMAP(paddr));
7075 mtx_lock_spin(&qframe_mtx);
7076 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7077 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7078 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7083 pmap_quick_remove_page(vm_offset_t addr)
7088 pte_store(vtopte(qframe), 0);
7090 mtx_unlock_spin(&qframe_mtx);
7093 #include "opt_ddb.h"
7095 #include <ddb/ddb.h>
7097 DB_SHOW_COMMAND(pte, pmap_print_pte)
7103 pt_entry_t *pte, PG_V;
7107 va = (vm_offset_t)addr;
7108 pmap = PCPU_GET(curpmap); /* XXX */
7110 db_printf("show pte addr\n");
7113 PG_V = pmap_valid_bit(pmap);
7114 pml4 = pmap_pml4e(pmap, va);
7115 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
7116 if ((*pml4 & PG_V) == 0) {
7120 pdp = pmap_pml4e_to_pdpe(pml4, va);
7121 db_printf(" pdpe %#016lx", *pdp);
7122 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
7126 pde = pmap_pdpe_to_pde(pdp, va);
7127 db_printf(" pde %#016lx", *pde);
7128 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
7132 pte = pmap_pde_to_pte(pde, va);
7133 db_printf(" pte %#016lx\n", *pte);
7136 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
7141 a = (vm_paddr_t)addr;
7142 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
7144 db_printf("show phys2dmap addr\n");