2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
128 #include <sys/turnstile.h>
129 #include <sys/vmem.h>
130 #include <sys/vmmeter.h>
131 #include <sys/sched.h>
132 #include <sys/sysctl.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
148 #include <vm/vm_phys.h>
149 #include <vm/vm_radix.h>
150 #include <vm/vm_reserv.h>
153 #include <machine/intr_machdep.h>
154 #include <x86/apicvar.h>
155 #include <x86/ifunc.h>
156 #include <machine/cpu.h>
157 #include <machine/cputypes.h>
158 #include <machine/md_var.h>
159 #include <machine/pcb.h>
160 #include <machine/specialreg.h>
162 #include <machine/smp.h>
164 #include <machine/sysarch.h>
165 #include <machine/tss.h>
167 static __inline boolean_t
168 pmap_type_guest(pmap_t pmap)
171 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
174 static __inline boolean_t
175 pmap_emulate_ad_bits(pmap_t pmap)
178 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
181 static __inline pt_entry_t
182 pmap_valid_bit(pmap_t pmap)
186 switch (pmap->pm_type) {
192 if (pmap_emulate_ad_bits(pmap))
193 mask = EPT_PG_EMUL_V;
198 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
204 static __inline pt_entry_t
205 pmap_rw_bit(pmap_t pmap)
209 switch (pmap->pm_type) {
215 if (pmap_emulate_ad_bits(pmap))
216 mask = EPT_PG_EMUL_RW;
221 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
227 static pt_entry_t pg_g;
229 static __inline pt_entry_t
230 pmap_global_bit(pmap_t pmap)
234 switch (pmap->pm_type) {
243 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
249 static __inline pt_entry_t
250 pmap_accessed_bit(pmap_t pmap)
254 switch (pmap->pm_type) {
260 if (pmap_emulate_ad_bits(pmap))
266 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
272 static __inline pt_entry_t
273 pmap_modified_bit(pmap_t pmap)
277 switch (pmap->pm_type) {
283 if (pmap_emulate_ad_bits(pmap))
289 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
295 static __inline pt_entry_t
296 pmap_pku_mask_bit(pmap_t pmap)
299 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
302 #if !defined(DIAGNOSTIC)
303 #ifdef __GNUC_GNU_INLINE__
304 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
306 #define PMAP_INLINE extern inline
313 #define PV_STAT(x) do { x ; } while (0)
315 #define PV_STAT(x) do { } while (0)
318 #define pa_index(pa) ((pa) >> PDRSHIFT)
319 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
321 #define NPV_LIST_LOCKS MAXCPU
323 #define PHYS_TO_PV_LIST_LOCK(pa) \
324 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
326 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
327 struct rwlock **_lockp = (lockp); \
328 struct rwlock *_new_lock; \
330 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
331 if (_new_lock != *_lockp) { \
332 if (*_lockp != NULL) \
333 rw_wunlock(*_lockp); \
334 *_lockp = _new_lock; \
339 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
340 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
342 #define RELEASE_PV_LIST_LOCK(lockp) do { \
343 struct rwlock **_lockp = (lockp); \
345 if (*_lockp != NULL) { \
346 rw_wunlock(*_lockp); \
351 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
352 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
354 struct pmap kernel_pmap_store;
356 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
357 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
360 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
361 "Number of kernel page table pages allocated on bootup");
364 vm_paddr_t dmaplimit;
365 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
368 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
370 /* Unused, kept for ABI stability on the stable branch. */
371 static int pat_works = 1;
372 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
373 "Is page attribute table fully functional?");
375 static int pg_ps_enabled = 1;
376 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
377 &pg_ps_enabled, 0, "Are large page mappings enabled?");
379 #define PAT_INDEX_SIZE 8
380 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
382 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
383 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
384 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
385 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
387 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
388 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
389 static int ndmpdpphys; /* number of DMPDPphys pages */
391 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
394 * pmap_mapdev support pre initialization (i.e. console)
396 #define PMAP_PREINIT_MAPPING_COUNT 8
397 static struct pmap_preinit_mapping {
402 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
403 static int pmap_initialized;
406 * Data for the pv entry allocation mechanism.
407 * Updates to pv_invl_gen are protected by the pv_list_locks[]
408 * elements, but reads are not.
410 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
411 static struct mtx __exclusive_cache_line pv_chunks_mutex;
412 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
413 static u_long pv_invl_gen[NPV_LIST_LOCKS];
414 static struct md_page *pv_table;
415 static struct md_page pv_dummy;
418 * All those kernel PT submaps that BSD is so fond of
420 pt_entry_t *CMAP1 = NULL;
422 static vm_offset_t qframe = 0;
423 static struct mtx qframe_mtx;
425 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
427 static vmem_t *large_vmem;
428 static u_int lm_ents;
429 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
430 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
432 int pmap_pcid_enabled = 1;
433 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
434 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
435 int invpcid_works = 0;
436 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
437 "Is the invpcid instruction available ?");
439 int __read_frequently pti = 0;
440 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
442 "Page Table Isolation enabled");
443 static vm_object_t pti_obj;
444 static pml4_entry_t *pti_pml4;
445 static vm_pindex_t pti_pg_idx;
446 static bool pti_finalized;
448 struct pmap_pkru_range {
449 struct rs_el pkru_rs_el;
454 static uma_zone_t pmap_pkru_ranges_zone;
455 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
456 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
457 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
458 static void *pkru_dup_range(void *ctx, void *data);
459 static void pkru_free_range(void *ctx, void *node);
460 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
461 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
462 static void pmap_pkru_deassign_all(pmap_t pmap);
465 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
472 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
474 return (sysctl_handle_64(oidp, &res, 0, req));
476 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
477 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
478 "Count of saved TLB context on switch");
480 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
481 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
482 static struct mtx invl_gen_mtx;
483 /* Fake lock object to satisfy turnstiles interface. */
484 static struct lock_object invl_gen_ts = {
487 static struct pmap_invl_gen pmap_invl_gen_head = {
491 static u_long pmap_invl_gen = 1;
492 static int pmap_invl_waiters;
493 static struct callout pmap_invl_callout;
494 static bool pmap_invl_callout_inited;
496 #define PMAP_ASSERT_NOT_IN_DI() \
497 KASSERT(pmap_not_in_di(), ("DI already started"))
504 if ((cpu_feature2 & CPUID2_CX16) == 0)
507 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
512 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
516 locked = pmap_di_locked();
517 return (sysctl_handle_int(oidp, &locked, 0, req));
519 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
520 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
521 "Locked delayed invalidation");
523 static bool pmap_not_in_di_l(void);
524 static bool pmap_not_in_di_u(void);
525 DEFINE_IFUNC(, bool, pmap_not_in_di, (void), static)
528 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
532 pmap_not_in_di_l(void)
534 struct pmap_invl_gen *invl_gen;
536 invl_gen = &curthread->td_md.md_invl_gen;
537 return (invl_gen->gen == 0);
541 pmap_thread_init_invl_gen_l(struct thread *td)
543 struct pmap_invl_gen *invl_gen;
545 invl_gen = &td->td_md.md_invl_gen;
550 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
552 struct turnstile *ts;
554 ts = turnstile_trywait(&invl_gen_ts);
555 if (*m_gen > atomic_load_long(invl_gen))
556 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
558 turnstile_cancel(ts);
562 pmap_delayed_invl_finish_unblock(u_long new_gen)
564 struct turnstile *ts;
566 turnstile_chain_lock(&invl_gen_ts);
567 ts = turnstile_lookup(&invl_gen_ts);
569 pmap_invl_gen = new_gen;
571 turnstile_broadcast(ts, TS_SHARED_QUEUE);
572 turnstile_unpend(ts);
574 turnstile_chain_unlock(&invl_gen_ts);
578 * Start a new Delayed Invalidation (DI) block of code, executed by
579 * the current thread. Within a DI block, the current thread may
580 * destroy both the page table and PV list entries for a mapping and
581 * then release the corresponding PV list lock before ensuring that
582 * the mapping is flushed from the TLBs of any processors with the
586 pmap_delayed_invl_start_l(void)
588 struct pmap_invl_gen *invl_gen;
591 invl_gen = &curthread->td_md.md_invl_gen;
592 PMAP_ASSERT_NOT_IN_DI();
593 mtx_lock(&invl_gen_mtx);
594 if (LIST_EMPTY(&pmap_invl_gen_tracker))
595 currgen = pmap_invl_gen;
597 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
598 invl_gen->gen = currgen + 1;
599 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
600 mtx_unlock(&invl_gen_mtx);
604 * Finish the DI block, previously started by the current thread. All
605 * required TLB flushes for the pages marked by
606 * pmap_delayed_invl_page() must be finished before this function is
609 * This function works by bumping the global DI generation number to
610 * the generation number of the current thread's DI, unless there is a
611 * pending DI that started earlier. In the latter case, bumping the
612 * global DI generation number would incorrectly signal that the
613 * earlier DI had finished. Instead, this function bumps the earlier
614 * DI's generation number to match the generation number of the
615 * current thread's DI.
618 pmap_delayed_invl_finish_l(void)
620 struct pmap_invl_gen *invl_gen, *next;
622 invl_gen = &curthread->td_md.md_invl_gen;
623 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
624 mtx_lock(&invl_gen_mtx);
625 next = LIST_NEXT(invl_gen, link);
627 pmap_delayed_invl_finish_unblock(invl_gen->gen);
629 next->gen = invl_gen->gen;
630 LIST_REMOVE(invl_gen, link);
631 mtx_unlock(&invl_gen_mtx);
636 pmap_not_in_di_u(void)
638 struct pmap_invl_gen *invl_gen;
640 invl_gen = &curthread->td_md.md_invl_gen;
641 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
645 pmap_thread_init_invl_gen_u(struct thread *td)
647 struct pmap_invl_gen *invl_gen;
649 invl_gen = &td->td_md.md_invl_gen;
651 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
655 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
657 uint64_t new_high, new_low, old_high, old_low;
660 old_low = new_low = 0;
661 old_high = new_high = (uintptr_t)0;
663 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
664 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
665 : "b"(new_low), "c" (new_high)
668 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
671 out->next = (void *)old_high;
674 out->next = (void *)new_high;
680 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
681 struct pmap_invl_gen *new_val)
683 uint64_t new_high, new_low, old_high, old_low;
686 new_low = new_val->gen;
687 new_high = (uintptr_t)new_val->next;
688 old_low = old_val->gen;
689 old_high = (uintptr_t)old_val->next;
691 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
692 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
693 : "b"(new_low), "c" (new_high)
699 static long invl_start_restart;
700 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
701 &invl_start_restart, 0,
703 static long invl_finish_restart;
704 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
705 &invl_finish_restart, 0,
707 static int invl_max_qlen;
708 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
713 static struct lock_delay_config __read_frequently di_delay;
714 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
717 pmap_delayed_invl_start_u(void)
719 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
721 struct lock_delay_arg lda;
729 invl_gen = &td->td_md.md_invl_gen;
730 PMAP_ASSERT_NOT_IN_DI();
731 lock_delay_arg_init(&lda, &di_delay);
732 invl_gen->saved_pri = 0;
733 pri = td->td_base_pri;
736 pri = td->td_base_pri;
738 invl_gen->saved_pri = pri;
745 for (p = &pmap_invl_gen_head;; p = prev.next) {
747 prevl = atomic_load_ptr(&p->next);
748 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
749 PV_STAT(atomic_add_long(&invl_start_restart, 1));
755 prev.next = (void *)prevl;
758 if ((ii = invl_max_qlen) < i)
759 atomic_cmpset_int(&invl_max_qlen, ii, i);
762 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
763 PV_STAT(atomic_add_long(&invl_start_restart, 1));
768 new_prev.gen = prev.gen;
769 new_prev.next = invl_gen;
770 invl_gen->gen = prev.gen + 1;
772 /* Formal fence between store to invl->gen and updating *p. */
773 atomic_thread_fence_rel();
776 * After inserting an invl_gen element with invalid bit set,
777 * this thread blocks any other thread trying to enter the
778 * delayed invalidation block. Do not allow to remove us from
779 * the CPU, because it causes starvation for other threads.
784 * ABA for *p is not possible there, since p->gen can only
785 * increase. So if the *p thread finished its di, then
786 * started a new one and got inserted into the list at the
787 * same place, its gen will appear greater than the previously
790 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
792 PV_STAT(atomic_add_long(&invl_start_restart, 1));
798 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
799 * invl_gen->next, allowing other threads to iterate past us.
800 * pmap_di_store_invl() provides fence between the generation
801 * write and the update of next.
803 invl_gen->next = NULL;
808 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
809 struct pmap_invl_gen *p)
811 struct pmap_invl_gen prev, new_prev;
815 * Load invl_gen->gen after setting invl_gen->next
816 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
817 * generations to propagate to our invl_gen->gen. Lock prefix
818 * in atomic_set_ptr() worked as seq_cst fence.
820 mygen = atomic_load_long(&invl_gen->gen);
822 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
825 KASSERT(prev.gen < mygen,
826 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
827 new_prev.gen = mygen;
828 new_prev.next = (void *)((uintptr_t)invl_gen->next &
829 ~PMAP_INVL_GEN_NEXT_INVALID);
831 /* Formal fence between load of prev and storing update to it. */
832 atomic_thread_fence_rel();
834 return (pmap_di_store_invl(p, &prev, &new_prev));
838 pmap_delayed_invl_finish_u(void)
840 struct pmap_invl_gen *invl_gen, *p;
842 struct lock_delay_arg lda;
846 invl_gen = &td->td_md.md_invl_gen;
847 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
848 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
849 ("missed invl_start: INVALID"));
850 lock_delay_arg_init(&lda, &di_delay);
853 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
854 prevl = atomic_load_ptr(&p->next);
855 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
856 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
860 if ((void *)prevl == invl_gen)
865 * It is legitimate to not find ourself on the list if a
866 * thread before us finished its DI and started it again.
868 if (__predict_false(p == NULL)) {
869 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
875 atomic_set_ptr((uintptr_t *)&invl_gen->next,
876 PMAP_INVL_GEN_NEXT_INVALID);
877 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
878 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
879 PMAP_INVL_GEN_NEXT_INVALID);
881 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
886 if (atomic_load_int(&pmap_invl_waiters) > 0)
887 pmap_delayed_invl_finish_unblock(0);
888 if (invl_gen->saved_pri != 0) {
890 sched_prio(td, invl_gen->saved_pri);
896 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
898 struct pmap_invl_gen *p, *pn;
903 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
905 nextl = atomic_load_ptr(&p->next);
906 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
907 td = first ? NULL : __containerof(p, struct thread,
909 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
910 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
911 td != NULL ? td->td_tid : -1);
917 static long invl_wait;
918 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
919 "Number of times DI invalidation blocked pmap_remove_all/write");
920 static long invl_wait_slow;
921 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
922 "Number of slow invalidation waits for lockless DI");
926 pmap_delayed_invl_genp(vm_page_t m)
929 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
933 pmap_delayed_invl_callout_func(void *arg __unused)
936 if (atomic_load_int(&pmap_invl_waiters) == 0)
938 pmap_delayed_invl_finish_unblock(0);
942 pmap_delayed_invl_callout_init(void *arg __unused)
945 if (pmap_di_locked())
947 callout_init(&pmap_invl_callout, 1);
948 pmap_invl_callout_inited = true;
950 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
951 pmap_delayed_invl_callout_init, NULL);
954 * Ensure that all currently executing DI blocks, that need to flush
955 * TLB for the given page m, actually flushed the TLB at the time the
956 * function returned. If the page m has an empty PV list and we call
957 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
958 * valid mapping for the page m in either its page table or TLB.
960 * This function works by blocking until the global DI generation
961 * number catches up with the generation number associated with the
962 * given page m and its PV list. Since this function's callers
963 * typically own an object lock and sometimes own a page lock, it
964 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
968 pmap_delayed_invl_wait_l(vm_page_t m)
972 bool accounted = false;
975 m_gen = pmap_delayed_invl_genp(m);
976 while (*m_gen > pmap_invl_gen) {
979 atomic_add_long(&invl_wait, 1);
983 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
988 pmap_delayed_invl_wait_u(vm_page_t m)
991 struct lock_delay_arg lda;
995 m_gen = pmap_delayed_invl_genp(m);
996 lock_delay_arg_init(&lda, &di_delay);
997 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
998 if (fast || !pmap_invl_callout_inited) {
999 PV_STAT(atomic_add_long(&invl_wait, 1));
1004 * The page's invalidation generation number
1005 * is still below the current thread's number.
1006 * Prepare to block so that we do not waste
1007 * CPU cycles or worse, suffer livelock.
1009 * Since it is impossible to block without
1010 * racing with pmap_delayed_invl_finish_u(),
1011 * prepare for the race by incrementing
1012 * pmap_invl_waiters and arming a 1-tick
1013 * callout which will unblock us if we lose
1016 atomic_add_int(&pmap_invl_waiters, 1);
1019 * Re-check the current thread's invalidation
1020 * generation after incrementing
1021 * pmap_invl_waiters, so that there is no race
1022 * with pmap_delayed_invl_finish_u() setting
1023 * the page generation and checking
1024 * pmap_invl_waiters. The only race allowed
1025 * is for a missed unblock, which is handled
1029 atomic_load_long(&pmap_invl_gen_head.gen)) {
1030 callout_reset(&pmap_invl_callout, 1,
1031 pmap_delayed_invl_callout_func, NULL);
1032 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1033 pmap_delayed_invl_wait_block(m_gen,
1034 &pmap_invl_gen_head.gen);
1036 atomic_add_int(&pmap_invl_waiters, -1);
1041 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *), static)
1044 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1045 pmap_thread_init_invl_gen_u);
1048 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void), static)
1051 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1052 pmap_delayed_invl_start_u);
1055 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void), static)
1058 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1059 pmap_delayed_invl_finish_u);
1062 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t), static)
1065 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1066 pmap_delayed_invl_wait_u);
1070 * Mark the page m's PV list as participating in the current thread's
1071 * DI block. Any threads concurrently using m's PV list to remove or
1072 * restrict all mappings to m will wait for the current thread's DI
1073 * block to complete before proceeding.
1075 * The function works by setting the DI generation number for m's PV
1076 * list to at least the DI generation number of the current thread.
1077 * This forces a caller of pmap_delayed_invl_wait() to block until
1078 * current thread calls pmap_delayed_invl_finish().
1081 pmap_delayed_invl_page(vm_page_t m)
1085 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1086 gen = curthread->td_md.md_invl_gen.gen;
1089 m_gen = pmap_delayed_invl_genp(m);
1097 static caddr_t crashdumpmap;
1100 * Internal flags for pmap_enter()'s helper functions.
1102 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1103 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1106 * Internal flags for pmap_mapdev_internal() and
1107 * pmap_change_attr_locked().
1109 #define MAPDEV_FLUSHCACHE 0x0000001 /* Flush cache after mapping. */
1110 #define MAPDEV_SETATTR 0x0000002 /* Modify existing attrs. */
1112 static void free_pv_chunk(struct pv_chunk *pc);
1113 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1114 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1115 static int popcnt_pc_map_pq(uint64_t *map);
1116 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1117 static void reserve_pv_entries(pmap_t pmap, int needed,
1118 struct rwlock **lockp);
1119 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1120 struct rwlock **lockp);
1121 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1122 u_int flags, struct rwlock **lockp);
1123 #if VM_NRESERVLEVEL > 0
1124 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1125 struct rwlock **lockp);
1127 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1128 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1131 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
1133 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1134 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1135 vm_offset_t va, struct rwlock **lockp);
1136 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1138 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1139 vm_prot_t prot, struct rwlock **lockp);
1140 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1141 u_int flags, vm_page_t m, struct rwlock **lockp);
1142 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1143 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1144 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1145 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1146 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1148 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1150 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1152 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1153 static vm_page_t pmap_large_map_getptp_unlocked(void);
1154 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1155 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
1156 #if VM_NRESERVLEVEL > 0
1157 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1158 struct rwlock **lockp);
1160 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1162 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
1163 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1165 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1166 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1167 static void pmap_pti_wire_pte(void *pte);
1168 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1169 struct spglist *free, struct rwlock **lockp);
1170 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1171 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1172 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1173 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1174 struct spglist *free);
1175 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1176 pd_entry_t *pde, struct spglist *free,
1177 struct rwlock **lockp);
1178 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1179 vm_page_t m, struct rwlock **lockp);
1180 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1182 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1184 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1185 struct rwlock **lockp);
1186 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1187 struct rwlock **lockp);
1188 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1189 struct rwlock **lockp);
1191 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1192 struct spglist *free);
1193 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1195 /********************/
1196 /* Inline functions */
1197 /********************/
1199 /* Return a non-clipped PD index for a given VA */
1200 static __inline vm_pindex_t
1201 pmap_pde_pindex(vm_offset_t va)
1203 return (va >> PDRSHIFT);
1207 /* Return a pointer to the PML4 slot that corresponds to a VA */
1208 static __inline pml4_entry_t *
1209 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1212 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1215 /* Return a pointer to the PDP slot that corresponds to a VA */
1216 static __inline pdp_entry_t *
1217 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1221 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1222 return (&pdpe[pmap_pdpe_index(va)]);
1225 /* Return a pointer to the PDP slot that corresponds to a VA */
1226 static __inline pdp_entry_t *
1227 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1229 pml4_entry_t *pml4e;
1232 PG_V = pmap_valid_bit(pmap);
1233 pml4e = pmap_pml4e(pmap, va);
1234 if ((*pml4e & PG_V) == 0)
1236 return (pmap_pml4e_to_pdpe(pml4e, va));
1239 /* Return a pointer to the PD slot that corresponds to a VA */
1240 static __inline pd_entry_t *
1241 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1245 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1246 return (&pde[pmap_pde_index(va)]);
1249 /* Return a pointer to the PD slot that corresponds to a VA */
1250 static __inline pd_entry_t *
1251 pmap_pde(pmap_t pmap, vm_offset_t va)
1256 PG_V = pmap_valid_bit(pmap);
1257 pdpe = pmap_pdpe(pmap, va);
1258 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1260 return (pmap_pdpe_to_pde(pdpe, va));
1263 /* Return a pointer to the PT slot that corresponds to a VA */
1264 static __inline pt_entry_t *
1265 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1269 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1270 return (&pte[pmap_pte_index(va)]);
1273 /* Return a pointer to the PT slot that corresponds to a VA */
1274 static __inline pt_entry_t *
1275 pmap_pte(pmap_t pmap, vm_offset_t va)
1280 PG_V = pmap_valid_bit(pmap);
1281 pde = pmap_pde(pmap, va);
1282 if (pde == NULL || (*pde & PG_V) == 0)
1284 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1285 return ((pt_entry_t *)pde);
1286 return (pmap_pde_to_pte(pde, va));
1289 static __inline void
1290 pmap_resident_count_inc(pmap_t pmap, int count)
1293 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1294 pmap->pm_stats.resident_count += count;
1297 static __inline void
1298 pmap_resident_count_dec(pmap_t pmap, int count)
1301 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1302 KASSERT(pmap->pm_stats.resident_count >= count,
1303 ("pmap %p resident count underflow %ld %d", pmap,
1304 pmap->pm_stats.resident_count, count));
1305 pmap->pm_stats.resident_count -= count;
1308 PMAP_INLINE pt_entry_t *
1309 vtopte(vm_offset_t va)
1311 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1313 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1315 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1318 static __inline pd_entry_t *
1319 vtopde(vm_offset_t va)
1321 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1323 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1325 return (PDmap + ((va >> PDRSHIFT) & mask));
1329 allocpages(vm_paddr_t *firstaddr, int n)
1334 bzero((void *)ret, n * PAGE_SIZE);
1335 *firstaddr += n * PAGE_SIZE;
1339 CTASSERT(powerof2(NDMPML4E));
1341 /* number of kernel PDP slots */
1342 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1345 nkpt_init(vm_paddr_t addr)
1352 pt_pages = howmany(addr, 1 << PDRSHIFT);
1353 pt_pages += NKPDPE(pt_pages);
1356 * Add some slop beyond the bare minimum required for bootstrapping
1359 * This is quite important when allocating KVA for kernel modules.
1360 * The modules are required to be linked in the negative 2GB of
1361 * the address space. If we run out of KVA in this region then
1362 * pmap_growkernel() will need to allocate page table pages to map
1363 * the entire 512GB of KVA space which is an unnecessary tax on
1366 * Secondly, device memory mapped as part of setting up the low-
1367 * level console(s) is taken from KVA, starting at virtual_avail.
1368 * This is because cninit() is called after pmap_bootstrap() but
1369 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1372 pt_pages += 32; /* 64MB additional slop. */
1378 * Returns the proper write/execute permission for a physical page that is
1379 * part of the initial boot allocations.
1381 * If the page has kernel text, it is marked as read-only. If the page has
1382 * kernel read-only data, it is marked as read-only/not-executable. If the
1383 * page has only read-write data, it is marked as read-write/not-executable.
1384 * If the page is below/above the kernel range, it is marked as read-write.
1386 * This function operates on 2M pages, since we map the kernel space that
1389 * Note that this doesn't currently provide any protection for modules.
1391 static inline pt_entry_t
1392 bootaddr_rwx(vm_paddr_t pa)
1396 * Everything in the same 2M page as the start of the kernel
1397 * should be static. On the other hand, things in the same 2M
1398 * page as the end of the kernel could be read-write/executable,
1399 * as the kernel image is not guaranteed to end on a 2M boundary.
1401 if (pa < trunc_2mpage(btext - KERNBASE) ||
1402 pa >= trunc_2mpage(_end - KERNBASE))
1405 * The linker should ensure that the read-only and read-write
1406 * portions don't share the same 2M page, so this shouldn't
1407 * impact read-only data. However, in any case, any page with
1408 * read-write data needs to be read-write.
1410 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1411 return (X86_PG_RW | pg_nx);
1413 * Mark any 2M page containing kernel text as read-only. Mark
1414 * other pages with read-only data as read-only and not executable.
1415 * (It is likely a small portion of the read-only data section will
1416 * be marked as read-only, but executable. This should be acceptable
1417 * since the read-only protection will keep the data from changing.)
1418 * Note that fixups to the .text section will still work until we
1421 if (pa < round_2mpage(etext - KERNBASE))
1427 create_pagetables(vm_paddr_t *firstaddr)
1429 int i, j, ndm1g, nkpdpe, nkdmpde;
1433 uint64_t DMPDkernphys;
1435 /* Allocate page table pages for the direct map */
1436 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1437 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1439 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1440 if (ndmpdpphys > NDMPML4E) {
1442 * Each NDMPML4E allows 512 GB, so limit to that,
1443 * and then readjust ndmpdp and ndmpdpphys.
1445 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1446 Maxmem = atop(NDMPML4E * NBPML4);
1447 ndmpdpphys = NDMPML4E;
1448 ndmpdp = NDMPML4E * NPDEPG;
1450 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1452 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1454 * Calculate the number of 1G pages that will fully fit in
1457 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1460 * Allocate 2M pages for the kernel. These will be used in
1461 * place of the first one or more 1G pages from ndm1g.
1463 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1464 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1467 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1468 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1470 /* Allocate pages */
1471 KPML4phys = allocpages(firstaddr, 1);
1472 KPDPphys = allocpages(firstaddr, NKPML4E);
1475 * Allocate the initial number of kernel page table pages required to
1476 * bootstrap. We defer this until after all memory-size dependent
1477 * allocations are done (e.g. direct map), so that we don't have to
1478 * build in too much slop in our estimate.
1480 * Note that when NKPML4E > 1, we have an empty page underneath
1481 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1482 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1484 nkpt_init(*firstaddr);
1485 nkpdpe = NKPDPE(nkpt);
1487 KPTphys = allocpages(firstaddr, nkpt);
1488 KPDphys = allocpages(firstaddr, nkpdpe);
1491 * Connect the zero-filled PT pages to their PD entries. This
1492 * implicitly maps the PT pages at their correct locations within
1495 pd_p = (pd_entry_t *)KPDphys;
1496 for (i = 0; i < nkpt; i++)
1497 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1500 * Map from physical address zero to the end of loader preallocated
1501 * memory using 2MB pages. This replaces some of the PD entries
1504 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1505 /* Preset PG_M and PG_A because demotion expects it. */
1506 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1507 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1510 * Because we map the physical blocks in 2M pages, adjust firstaddr
1511 * to record the physical blocks we've actually mapped into kernel
1512 * virtual address space.
1514 if (*firstaddr < round_2mpage(KERNend))
1515 *firstaddr = round_2mpage(KERNend);
1517 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1518 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1519 for (i = 0; i < nkpdpe; i++)
1520 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1523 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1524 * the end of physical memory is not aligned to a 1GB page boundary,
1525 * then the residual physical memory is mapped with 2MB pages. Later,
1526 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1527 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1528 * that are partially used.
1530 pd_p = (pd_entry_t *)DMPDphys;
1531 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1532 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1533 /* Preset PG_M and PG_A because demotion expects it. */
1534 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1535 X86_PG_M | X86_PG_A | pg_nx;
1537 pdp_p = (pdp_entry_t *)DMPDPphys;
1538 for (i = 0; i < ndm1g; i++) {
1539 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1540 /* Preset PG_M and PG_A because demotion expects it. */
1541 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1542 X86_PG_M | X86_PG_A | pg_nx;
1544 for (j = 0; i < ndmpdp; i++, j++) {
1545 pdp_p[i] = DMPDphys + ptoa(j);
1546 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1550 * Instead of using a 1G page for the memory containing the kernel,
1551 * use 2M pages with appropriate permissions. (If using 1G pages,
1552 * this will partially overwrite the PDPEs above.)
1555 pd_p = (pd_entry_t *)DMPDkernphys;
1556 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1557 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1558 X86_PG_M | X86_PG_A | pg_nx |
1559 bootaddr_rwx(i << PDRSHIFT);
1560 for (i = 0; i < nkdmpde; i++)
1561 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1565 /* And recursively map PML4 to itself in order to get PTmap */
1566 p4_p = (pml4_entry_t *)KPML4phys;
1567 p4_p[PML4PML4I] = KPML4phys;
1568 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1570 /* Connect the Direct Map slot(s) up to the PML4. */
1571 for (i = 0; i < ndmpdpphys; i++) {
1572 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1573 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1576 /* Connect the KVA slots up to the PML4 */
1577 for (i = 0; i < NKPML4E; i++) {
1578 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1579 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1584 * Bootstrap the system enough to run with virtual memory.
1586 * On amd64 this is called after mapping has already been enabled
1587 * and just syncs the pmap module with what has already been done.
1588 * [We can't call it easily with mapping off since the kernel is not
1589 * mapped with PA == VA, hence we would have to relocate every address
1590 * from the linked base (virtual) address "KERNBASE" to the actual
1591 * (physical) address starting relative to 0]
1594 pmap_bootstrap(vm_paddr_t *firstaddr)
1602 KERNend = *firstaddr;
1603 res = atop(KERNend - (vm_paddr_t)kernphys);
1609 * Create an initial set of page tables to run the kernel in.
1611 create_pagetables(firstaddr);
1614 * Add a physical memory segment (vm_phys_seg) corresponding to the
1615 * preallocated kernel page table pages so that vm_page structures
1616 * representing these pages will be created. The vm_page structures
1617 * are required for promotion of the corresponding kernel virtual
1618 * addresses to superpage mappings.
1620 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1623 * Account for the virtual addresses mapped by create_pagetables().
1625 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1626 virtual_end = VM_MAX_KERNEL_ADDRESS;
1629 * Enable PG_G global pages, then switch to the kernel page
1630 * table from the bootstrap page table. After the switch, it
1631 * is possible to enable SMEP and SMAP since PG_U bits are
1637 load_cr3(KPML4phys);
1638 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1640 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1645 * Initialize the kernel pmap (which is statically allocated).
1646 * Count bootstrap data as being resident in case any of this data is
1647 * later unmapped (using pmap_remove()) and freed.
1649 PMAP_LOCK_INIT(kernel_pmap);
1650 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1651 kernel_pmap->pm_cr3 = KPML4phys;
1652 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1653 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1654 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1655 kernel_pmap->pm_stats.resident_count = res;
1656 kernel_pmap->pm_flags = pmap_flags;
1659 * Initialize the TLB invalidations generation number lock.
1661 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1664 * Reserve some special page table entries/VA space for temporary
1667 #define SYSMAP(c, p, v, n) \
1668 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1674 * Crashdump maps. The first page is reused as CMAP1 for the
1677 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1678 CADDR1 = crashdumpmap;
1683 * Initialize the PAT MSR.
1684 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1685 * side-effect, invalidates stale PG_G TLB entries that might
1686 * have been created in our pre-boot environment.
1690 /* Initialize TLB Context Id. */
1691 if (pmap_pcid_enabled) {
1692 for (i = 0; i < MAXCPU; i++) {
1693 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1694 kernel_pmap->pm_pcids[i].pm_gen = 1;
1698 * PMAP_PCID_KERN + 1 is used for initialization of
1699 * proc0 pmap. The pmap' pcid state might be used by
1700 * EFIRT entry before first context switch, so it
1701 * needs to be valid.
1703 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1704 PCPU_SET(pcid_gen, 1);
1707 * pcpu area for APs is zeroed during AP startup.
1708 * pc_pcid_next and pc_pcid_gen are initialized by AP
1709 * during pcpu setup.
1711 load_cr4(rcr4() | CR4_PCIDE);
1716 * Setup the PAT MSR.
1725 /* Bail if this CPU doesn't implement PAT. */
1726 if ((cpu_feature & CPUID_PAT) == 0)
1729 /* Set default PAT index table. */
1730 for (i = 0; i < PAT_INDEX_SIZE; i++)
1732 pat_index[PAT_WRITE_BACK] = 0;
1733 pat_index[PAT_WRITE_THROUGH] = 1;
1734 pat_index[PAT_UNCACHEABLE] = 3;
1735 pat_index[PAT_WRITE_COMBINING] = 6;
1736 pat_index[PAT_WRITE_PROTECTED] = 5;
1737 pat_index[PAT_UNCACHED] = 2;
1740 * Initialize default PAT entries.
1741 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1742 * Program 5 and 6 as WP and WC.
1744 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1745 * mapping for a 2M page uses a PAT value with the bit 3 set due
1746 * to its overload with PG_PS.
1748 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1749 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1750 PAT_VALUE(2, PAT_UNCACHED) |
1751 PAT_VALUE(3, PAT_UNCACHEABLE) |
1752 PAT_VALUE(4, PAT_WRITE_BACK) |
1753 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1754 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1755 PAT_VALUE(7, PAT_UNCACHEABLE);
1759 load_cr4(cr4 & ~CR4_PGE);
1761 /* Disable caches (CD = 1, NW = 0). */
1763 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1765 /* Flushes caches and TLBs. */
1769 /* Update PAT and index table. */
1770 wrmsr(MSR_PAT, pat_msr);
1772 /* Flush caches and TLBs again. */
1776 /* Restore caches and PGE. */
1782 * Initialize a vm_page's machine-dependent fields.
1785 pmap_page_init(vm_page_t m)
1788 TAILQ_INIT(&m->md.pv_list);
1789 m->md.pat_mode = PAT_WRITE_BACK;
1793 * Initialize the pmap module.
1794 * Called by vm_init, to initialize any structures that the pmap
1795 * system needs to map virtual memory.
1800 struct pmap_preinit_mapping *ppim;
1803 int error, i, pv_npg, ret, skz63;
1805 /* L1TF, reserve page @0 unconditionally */
1806 vm_page_blacklist_add(0, bootverbose);
1808 /* Detect bare-metal Skylake Server and Skylake-X. */
1809 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1810 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1812 * Skylake-X errata SKZ63. Processor May Hang When
1813 * Executing Code In an HLE Transaction Region between
1814 * 40000000H and 403FFFFFH.
1816 * Mark the pages in the range as preallocated. It
1817 * seems to be impossible to distinguish between
1818 * Skylake Server and Skylake X.
1821 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1824 printf("SKZ63: skipping 4M RAM starting "
1825 "at physical 1G\n");
1826 for (i = 0; i < atop(0x400000); i++) {
1827 ret = vm_page_blacklist_add(0x40000000 +
1829 if (!ret && bootverbose)
1830 printf("page at %#lx already used\n",
1831 0x40000000 + ptoa(i));
1837 * Initialize the vm page array entries for the kernel pmap's
1840 PMAP_LOCK(kernel_pmap);
1841 for (i = 0; i < nkpt; i++) {
1842 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1843 KASSERT(mpte >= vm_page_array &&
1844 mpte < &vm_page_array[vm_page_array_size],
1845 ("pmap_init: page table page is out of range"));
1846 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1847 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1848 mpte->wire_count = 1;
1851 * Collect the page table pages that were replaced by a 2MB
1852 * page in create_pagetables(). They are zero filled.
1854 if (i << PDRSHIFT < KERNend &&
1855 pmap_insert_pt_page(kernel_pmap, mpte, false))
1856 panic("pmap_init: pmap_insert_pt_page failed");
1858 PMAP_UNLOCK(kernel_pmap);
1862 * If the kernel is running on a virtual machine, then it must assume
1863 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1864 * be prepared for the hypervisor changing the vendor and family that
1865 * are reported by CPUID. Consequently, the workaround for AMD Family
1866 * 10h Erratum 383 is enabled if the processor's feature set does not
1867 * include at least one feature that is only supported by older Intel
1868 * or newer AMD processors.
1870 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1871 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1872 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1874 workaround_erratum383 = 1;
1877 * Are large page mappings enabled?
1879 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1880 if (pg_ps_enabled) {
1881 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1882 ("pmap_init: can't assign to pagesizes[1]"));
1883 pagesizes[1] = NBPDR;
1887 * Initialize the pv chunk list mutex.
1889 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1892 * Initialize the pool of pv list locks.
1894 for (i = 0; i < NPV_LIST_LOCKS; i++)
1895 rw_init(&pv_list_locks[i], "pmap pv list");
1898 * Calculate the size of the pv head table for superpages.
1900 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1903 * Allocate memory for the pv head table for superpages.
1905 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1907 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1908 for (i = 0; i < pv_npg; i++)
1909 TAILQ_INIT(&pv_table[i].pv_list);
1910 TAILQ_INIT(&pv_dummy.pv_list);
1912 pmap_initialized = 1;
1913 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1914 ppim = pmap_preinit_mapping + i;
1917 /* Make the direct map consistent */
1918 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1919 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1920 ppim->sz, ppim->mode);
1924 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1925 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1928 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1929 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1930 (vmem_addr_t *)&qframe);
1932 panic("qframe allocation failed");
1935 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1936 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1937 lm_ents = LMEPML4I - LMSPML4I + 1;
1939 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1940 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1942 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1943 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1944 if (large_vmem == NULL) {
1945 printf("pmap: cannot create large map\n");
1948 for (i = 0; i < lm_ents; i++) {
1949 m = pmap_large_map_getptp_unlocked();
1950 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1951 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
1957 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1958 "2MB page mapping counters");
1960 static u_long pmap_pde_demotions;
1961 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1962 &pmap_pde_demotions, 0, "2MB page demotions");
1964 static u_long pmap_pde_mappings;
1965 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1966 &pmap_pde_mappings, 0, "2MB page mappings");
1968 static u_long pmap_pde_p_failures;
1969 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1970 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1972 static u_long pmap_pde_promotions;
1973 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1974 &pmap_pde_promotions, 0, "2MB page promotions");
1976 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1977 "1GB page mapping counters");
1979 static u_long pmap_pdpe_demotions;
1980 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1981 &pmap_pdpe_demotions, 0, "1GB page demotions");
1983 /***************************************************
1984 * Low level helper routines.....
1985 ***************************************************/
1988 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1990 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1992 switch (pmap->pm_type) {
1995 /* Verify that both PAT bits are not set at the same time */
1996 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1997 ("Invalid PAT bits in entry %#lx", entry));
1999 /* Swap the PAT bits if one of them is set */
2000 if ((entry & x86_pat_bits) != 0)
2001 entry ^= x86_pat_bits;
2005 * Nothing to do - the memory attributes are represented
2006 * the same way for regular pages and superpages.
2010 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2017 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2020 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2021 pat_index[(int)mode] >= 0);
2025 * Determine the appropriate bits to set in a PTE or PDE for a specified
2029 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2031 int cache_bits, pat_flag, pat_idx;
2033 if (!pmap_is_valid_memattr(pmap, mode))
2034 panic("Unknown caching mode %d\n", mode);
2036 switch (pmap->pm_type) {
2039 /* The PAT bit is different for PTE's and PDE's. */
2040 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2042 /* Map the caching mode to a PAT index. */
2043 pat_idx = pat_index[mode];
2045 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2048 cache_bits |= pat_flag;
2050 cache_bits |= PG_NC_PCD;
2052 cache_bits |= PG_NC_PWT;
2056 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2060 panic("unsupported pmap type %d", pmap->pm_type);
2063 return (cache_bits);
2067 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2071 switch (pmap->pm_type) {
2074 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2077 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2080 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2087 pmap_ps_enabled(pmap_t pmap)
2090 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2094 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2097 switch (pmap->pm_type) {
2104 * This is a little bogus since the generation number is
2105 * supposed to be bumped up when a region of the address
2106 * space is invalidated in the page tables.
2108 * In this case the old PDE entry is valid but yet we want
2109 * to make sure that any mappings using the old entry are
2110 * invalidated in the TLB.
2112 * The reason this works as expected is because we rendezvous
2113 * "all" host cpus and force any vcpu context to exit as a
2116 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2119 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2121 pde_store(pde, newpde);
2125 * After changing the page size for the specified virtual address in the page
2126 * table, flush the corresponding entries from the processor's TLB. Only the
2127 * calling processor's TLB is affected.
2129 * The calling thread must be pinned to a processor.
2132 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2136 if (pmap_type_guest(pmap))
2139 KASSERT(pmap->pm_type == PT_X86,
2140 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2142 PG_G = pmap_global_bit(pmap);
2144 if ((newpde & PG_PS) == 0)
2145 /* Demotion: flush a specific 2MB page mapping. */
2147 else if ((newpde & PG_G) == 0)
2149 * Promotion: flush every 4KB page mapping from the TLB
2150 * because there are too many to flush individually.
2155 * Promotion: flush every 4KB page mapping from the TLB,
2156 * including any global (PG_G) mappings.
2164 * For SMP, these functions have to use the IPI mechanism for coherence.
2166 * N.B.: Before calling any of the following TLB invalidation functions,
2167 * the calling processor must ensure that all stores updating a non-
2168 * kernel page table are globally performed. Otherwise, another
2169 * processor could cache an old, pre-update entry without being
2170 * invalidated. This can happen one of two ways: (1) The pmap becomes
2171 * active on another processor after its pm_active field is checked by
2172 * one of the following functions but before a store updating the page
2173 * table is globally performed. (2) The pmap becomes active on another
2174 * processor before its pm_active field is checked but due to
2175 * speculative loads one of the following functions stills reads the
2176 * pmap as inactive on the other processor.
2178 * The kernel page table is exempt because its pm_active field is
2179 * immutable. The kernel page table is always active on every
2184 * Interrupt the cpus that are executing in the guest context.
2185 * This will force the vcpu to exit and the cached EPT mappings
2186 * will be invalidated by the host before the next vmresume.
2188 static __inline void
2189 pmap_invalidate_ept(pmap_t pmap)
2194 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2195 ("pmap_invalidate_ept: absurd pm_active"));
2198 * The TLB mappings associated with a vcpu context are not
2199 * flushed each time a different vcpu is chosen to execute.
2201 * This is in contrast with a process's vtop mappings that
2202 * are flushed from the TLB on each context switch.
2204 * Therefore we need to do more than just a TLB shootdown on
2205 * the active cpus in 'pmap->pm_active'. To do this we keep
2206 * track of the number of invalidations performed on this pmap.
2208 * Each vcpu keeps a cache of this counter and compares it
2209 * just before a vmresume. If the counter is out-of-date an
2210 * invept will be done to flush stale mappings from the TLB.
2212 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2215 * Force the vcpu to exit and trap back into the hypervisor.
2217 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2218 ipi_selected(pmap->pm_active, ipinum);
2223 pmap_invalidate_cpu_mask(pmap_t pmap)
2226 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2230 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2231 const bool invpcid_works1)
2233 struct invpcid_descr d;
2234 uint64_t kcr3, ucr3;
2238 cpuid = PCPU_GET(cpuid);
2239 if (pmap == PCPU_GET(curpmap)) {
2240 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2242 * Because pm_pcid is recalculated on a
2243 * context switch, we must disable switching.
2244 * Otherwise, we might use a stale value
2248 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2249 if (invpcid_works1) {
2250 d.pcid = pcid | PMAP_PCID_USER_PT;
2253 invpcid(&d, INVPCID_ADDR);
2255 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2256 ucr3 = pmap->pm_ucr3 | pcid |
2257 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2258 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2263 pmap->pm_pcids[cpuid].pm_gen = 0;
2267 pmap->pm_pcids[i].pm_gen = 0;
2271 * The fence is between stores to pm_gen and the read of the
2272 * pm_active mask. We need to ensure that it is impossible
2273 * for us to miss the bit update in pm_active and
2274 * simultaneously observe a non-zero pm_gen in
2275 * pmap_activate_sw(), otherwise TLB update is missed.
2276 * Without the fence, IA32 allows such an outcome. Note that
2277 * pm_active is updated by a locked operation, which provides
2278 * the reciprocal fence.
2280 atomic_thread_fence_seq_cst();
2284 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2287 pmap_invalidate_page_pcid(pmap, va, true);
2291 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2294 pmap_invalidate_page_pcid(pmap, va, false);
2298 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2302 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t),
2306 if (pmap_pcid_enabled)
2307 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2308 pmap_invalidate_page_pcid_noinvpcid);
2309 return (pmap_invalidate_page_nopcid);
2313 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2316 if (pmap_type_guest(pmap)) {
2317 pmap_invalidate_ept(pmap);
2321 KASSERT(pmap->pm_type == PT_X86,
2322 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2325 if (pmap == kernel_pmap) {
2328 if (pmap == PCPU_GET(curpmap))
2330 pmap_invalidate_page_mode(pmap, va);
2332 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2336 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2337 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2340 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2341 const bool invpcid_works1)
2343 struct invpcid_descr d;
2344 uint64_t kcr3, ucr3;
2348 cpuid = PCPU_GET(cpuid);
2349 if (pmap == PCPU_GET(curpmap)) {
2350 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2352 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2353 if (invpcid_works1) {
2354 d.pcid = pcid | PMAP_PCID_USER_PT;
2357 for (; d.addr < eva; d.addr += PAGE_SIZE)
2358 invpcid(&d, INVPCID_ADDR);
2360 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2361 ucr3 = pmap->pm_ucr3 | pcid |
2362 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2363 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2368 pmap->pm_pcids[cpuid].pm_gen = 0;
2372 pmap->pm_pcids[i].pm_gen = 0;
2374 /* See the comment in pmap_invalidate_page_pcid(). */
2375 atomic_thread_fence_seq_cst();
2379 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2383 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2387 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2391 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2395 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2399 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2400 vm_offset_t), static)
2403 if (pmap_pcid_enabled)
2404 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2405 pmap_invalidate_range_pcid_noinvpcid);
2406 return (pmap_invalidate_range_nopcid);
2410 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2414 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2415 pmap_invalidate_all(pmap);
2419 if (pmap_type_guest(pmap)) {
2420 pmap_invalidate_ept(pmap);
2424 KASSERT(pmap->pm_type == PT_X86,
2425 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2428 if (pmap == kernel_pmap) {
2429 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2432 if (pmap == PCPU_GET(curpmap)) {
2433 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2436 pmap_invalidate_range_mode(pmap, sva, eva);
2438 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2443 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2445 struct invpcid_descr d;
2446 uint64_t kcr3, ucr3;
2450 if (pmap == kernel_pmap) {
2451 if (invpcid_works1) {
2452 bzero(&d, sizeof(d));
2453 invpcid(&d, INVPCID_CTXGLOB);
2458 cpuid = PCPU_GET(cpuid);
2459 if (pmap == PCPU_GET(curpmap)) {
2461 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2462 if (invpcid_works1) {
2466 invpcid(&d, INVPCID_CTX);
2467 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2468 d.pcid |= PMAP_PCID_USER_PT;
2469 invpcid(&d, INVPCID_CTX);
2472 kcr3 = pmap->pm_cr3 | pcid;
2473 ucr3 = pmap->pm_ucr3;
2474 if (ucr3 != PMAP_NO_CR3) {
2475 ucr3 |= pcid | PMAP_PCID_USER_PT;
2476 pmap_pti_pcid_invalidate(ucr3, kcr3);
2483 pmap->pm_pcids[cpuid].pm_gen = 0;
2486 pmap->pm_pcids[i].pm_gen = 0;
2489 /* See the comment in pmap_invalidate_page_pcid(). */
2490 atomic_thread_fence_seq_cst();
2494 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2497 pmap_invalidate_all_pcid(pmap, true);
2501 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2504 pmap_invalidate_all_pcid(pmap, false);
2508 pmap_invalidate_all_nopcid(pmap_t pmap)
2511 if (pmap == kernel_pmap)
2513 else if (pmap == PCPU_GET(curpmap))
2517 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t), static)
2520 if (pmap_pcid_enabled)
2521 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2522 pmap_invalidate_all_pcid_noinvpcid);
2523 return (pmap_invalidate_all_nopcid);
2527 pmap_invalidate_all(pmap_t pmap)
2530 if (pmap_type_guest(pmap)) {
2531 pmap_invalidate_ept(pmap);
2535 KASSERT(pmap->pm_type == PT_X86,
2536 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2539 pmap_invalidate_all_mode(pmap);
2540 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2545 pmap_invalidate_cache(void)
2555 cpuset_t invalidate; /* processors that invalidate their TLB */
2560 u_int store; /* processor that updates the PDE */
2564 pmap_update_pde_action(void *arg)
2566 struct pde_action *act = arg;
2568 if (act->store == PCPU_GET(cpuid))
2569 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2573 pmap_update_pde_teardown(void *arg)
2575 struct pde_action *act = arg;
2577 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2578 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2582 * Change the page size for the specified virtual address in a way that
2583 * prevents any possibility of the TLB ever having two entries that map the
2584 * same virtual address using different page sizes. This is the recommended
2585 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2586 * machine check exception for a TLB state that is improperly diagnosed as a
2590 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2592 struct pde_action act;
2593 cpuset_t active, other_cpus;
2597 cpuid = PCPU_GET(cpuid);
2598 other_cpus = all_cpus;
2599 CPU_CLR(cpuid, &other_cpus);
2600 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2603 active = pmap->pm_active;
2605 if (CPU_OVERLAP(&active, &other_cpus)) {
2607 act.invalidate = active;
2611 act.newpde = newpde;
2612 CPU_SET(cpuid, &active);
2613 smp_rendezvous_cpus(active,
2614 smp_no_rendezvous_barrier, pmap_update_pde_action,
2615 pmap_update_pde_teardown, &act);
2617 pmap_update_pde_store(pmap, pde, newpde);
2618 if (CPU_ISSET(cpuid, &active))
2619 pmap_update_pde_invalidate(pmap, va, newpde);
2625 * Normal, non-SMP, invalidation functions.
2628 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2630 struct invpcid_descr d;
2631 uint64_t kcr3, ucr3;
2634 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2638 KASSERT(pmap->pm_type == PT_X86,
2639 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2641 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2643 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2644 pmap->pm_ucr3 != PMAP_NO_CR3) {
2646 pcid = pmap->pm_pcids[0].pm_pcid;
2647 if (invpcid_works) {
2648 d.pcid = pcid | PMAP_PCID_USER_PT;
2651 invpcid(&d, INVPCID_ADDR);
2653 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2654 ucr3 = pmap->pm_ucr3 | pcid |
2655 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2656 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2660 } else if (pmap_pcid_enabled)
2661 pmap->pm_pcids[0].pm_gen = 0;
2665 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2667 struct invpcid_descr d;
2669 uint64_t kcr3, ucr3;
2671 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2675 KASSERT(pmap->pm_type == PT_X86,
2676 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2678 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2679 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2681 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2682 pmap->pm_ucr3 != PMAP_NO_CR3) {
2684 if (invpcid_works) {
2685 d.pcid = pmap->pm_pcids[0].pm_pcid |
2689 for (; d.addr < eva; d.addr += PAGE_SIZE)
2690 invpcid(&d, INVPCID_ADDR);
2692 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2693 pm_pcid | CR3_PCID_SAVE;
2694 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2695 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2696 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2700 } else if (pmap_pcid_enabled) {
2701 pmap->pm_pcids[0].pm_gen = 0;
2706 pmap_invalidate_all(pmap_t pmap)
2708 struct invpcid_descr d;
2709 uint64_t kcr3, ucr3;
2711 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2715 KASSERT(pmap->pm_type == PT_X86,
2716 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2718 if (pmap == kernel_pmap) {
2719 if (pmap_pcid_enabled && invpcid_works) {
2720 bzero(&d, sizeof(d));
2721 invpcid(&d, INVPCID_CTXGLOB);
2725 } else if (pmap == PCPU_GET(curpmap)) {
2726 if (pmap_pcid_enabled) {
2728 if (invpcid_works) {
2729 d.pcid = pmap->pm_pcids[0].pm_pcid;
2732 invpcid(&d, INVPCID_CTX);
2733 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2734 d.pcid |= PMAP_PCID_USER_PT;
2735 invpcid(&d, INVPCID_CTX);
2738 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2739 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2740 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2741 0].pm_pcid | PMAP_PCID_USER_PT;
2742 pmap_pti_pcid_invalidate(ucr3, kcr3);
2750 } else if (pmap_pcid_enabled) {
2751 pmap->pm_pcids[0].pm_gen = 0;
2756 pmap_invalidate_cache(void)
2763 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2766 pmap_update_pde_store(pmap, pde, newpde);
2767 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2768 pmap_update_pde_invalidate(pmap, va, newpde);
2770 pmap->pm_pcids[0].pm_gen = 0;
2775 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2779 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2780 * by a promotion that did not invalidate the 512 4KB page mappings
2781 * that might exist in the TLB. Consequently, at this point, the TLB
2782 * may hold both 4KB and 2MB page mappings for the address range [va,
2783 * va + NBPDR). Therefore, the entire range must be invalidated here.
2784 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2785 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2786 * single INVLPG suffices to invalidate the 2MB page mapping from the
2789 if ((pde & PG_PROMOTED) != 0)
2790 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2792 pmap_invalidate_page(pmap, va);
2795 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2796 (vm_offset_t sva, vm_offset_t eva), static)
2799 if ((cpu_feature & CPUID_SS) != 0)
2800 return (pmap_invalidate_cache_range_selfsnoop);
2801 if ((cpu_feature & CPUID_CLFSH) != 0)
2802 return (pmap_force_invalidate_cache_range);
2803 return (pmap_invalidate_cache_range_all);
2806 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2809 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2812 KASSERT((sva & PAGE_MASK) == 0,
2813 ("pmap_invalidate_cache_range: sva not page-aligned"));
2814 KASSERT((eva & PAGE_MASK) == 0,
2815 ("pmap_invalidate_cache_range: eva not page-aligned"));
2819 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2822 pmap_invalidate_cache_range_check_align(sva, eva);
2826 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2829 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2832 * XXX: Some CPUs fault, hang, or trash the local APIC
2833 * registers if we use CLFLUSH on the local APIC range. The
2834 * local APIC is always uncached, so we don't need to flush
2835 * for that range anyway.
2837 if (pmap_kextract(sva) == lapic_paddr)
2840 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2842 * Do per-cache line flush. Use the sfence
2843 * instruction to insure that previous stores are
2844 * included in the write-back. The processor
2845 * propagates flush to other processors in the cache
2849 for (; sva < eva; sva += cpu_clflush_line_size)
2854 * Writes are ordered by CLFLUSH on Intel CPUs.
2856 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2858 for (; sva < eva; sva += cpu_clflush_line_size)
2860 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2866 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2869 pmap_invalidate_cache_range_check_align(sva, eva);
2870 pmap_invalidate_cache();
2874 * Remove the specified set of pages from the data and instruction caches.
2876 * In contrast to pmap_invalidate_cache_range(), this function does not
2877 * rely on the CPU's self-snoop feature, because it is intended for use
2878 * when moving pages into a different cache domain.
2881 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2883 vm_offset_t daddr, eva;
2887 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2888 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2889 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2890 pmap_invalidate_cache();
2894 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2896 for (i = 0; i < count; i++) {
2897 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2898 eva = daddr + PAGE_SIZE;
2899 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2908 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2914 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2917 pmap_invalidate_cache_range_check_align(sva, eva);
2919 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2920 pmap_force_invalidate_cache_range(sva, eva);
2924 /* See comment in pmap_force_invalidate_cache_range(). */
2925 if (pmap_kextract(sva) == lapic_paddr)
2929 for (; sva < eva; sva += cpu_clflush_line_size)
2935 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2939 int error, pte_bits;
2941 KASSERT((spa & PAGE_MASK) == 0,
2942 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2943 KASSERT((epa & PAGE_MASK) == 0,
2944 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2946 if (spa < dmaplimit) {
2947 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2949 if (dmaplimit >= epa)
2954 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
2956 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2958 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
2959 pte = vtopte(vaddr);
2960 for (; spa < epa; spa += PAGE_SIZE) {
2962 pte_store(pte, spa | pte_bits);
2964 /* XXXKIB sfences inside flush_cache_range are excessive */
2965 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
2968 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
2972 * Routine: pmap_extract
2974 * Extract the physical page address associated
2975 * with the given map/virtual_address pair.
2978 pmap_extract(pmap_t pmap, vm_offset_t va)
2982 pt_entry_t *pte, PG_V;
2986 PG_V = pmap_valid_bit(pmap);
2988 pdpe = pmap_pdpe(pmap, va);
2989 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2990 if ((*pdpe & PG_PS) != 0)
2991 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2993 pde = pmap_pdpe_to_pde(pdpe, va);
2994 if ((*pde & PG_V) != 0) {
2995 if ((*pde & PG_PS) != 0) {
2996 pa = (*pde & PG_PS_FRAME) |
2999 pte = pmap_pde_to_pte(pde, va);
3000 pa = (*pte & PG_FRAME) |
3011 * Routine: pmap_extract_and_hold
3013 * Atomically extract and hold the physical page
3014 * with the given pmap and virtual address pair
3015 * if that mapping permits the given protection.
3018 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3020 pd_entry_t pde, *pdep;
3021 pt_entry_t pte, PG_RW, PG_V;
3027 PG_RW = pmap_rw_bit(pmap);
3028 PG_V = pmap_valid_bit(pmap);
3031 pdep = pmap_pde(pmap, va);
3032 if (pdep != NULL && (pde = *pdep)) {
3034 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
3035 if (vm_page_pa_tryrelock(pmap, (pde &
3036 PG_PS_FRAME) | (va & PDRMASK), &pa))
3038 m = PHYS_TO_VM_PAGE(pa);
3041 pte = *pmap_pde_to_pte(pdep, va);
3043 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
3044 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
3047 m = PHYS_TO_VM_PAGE(pa);
3059 pmap_kextract(vm_offset_t va)
3064 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3065 pa = DMAP_TO_PHYS(va);
3066 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3067 pa = pmap_large_map_kextract(va);
3071 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3074 * Beware of a concurrent promotion that changes the
3075 * PDE at this point! For example, vtopte() must not
3076 * be used to access the PTE because it would use the
3077 * new PDE. It is, however, safe to use the old PDE
3078 * because the page table page is preserved by the
3081 pa = *pmap_pde_to_pte(&pde, va);
3082 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3088 /***************************************************
3089 * Low level mapping routines.....
3090 ***************************************************/
3093 * Add a wired page to the kva.
3094 * Note: not SMP coherent.
3097 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3102 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
3105 static __inline void
3106 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3112 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3113 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
3117 * Remove a page from the kernel pagetables.
3118 * Note: not SMP coherent.
3121 pmap_kremove(vm_offset_t va)
3130 * Used to map a range of physical addresses into kernel
3131 * virtual address space.
3133 * The value passed in '*virt' is a suggested virtual address for
3134 * the mapping. Architectures which can support a direct-mapped
3135 * physical to virtual region can return the appropriate address
3136 * within that region, leaving '*virt' unchanged. Other
3137 * architectures should map the pages starting at '*virt' and
3138 * update '*virt' with the first usable address after the mapped
3142 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3144 return PHYS_TO_DMAP(start);
3149 * Add a list of wired pages to the kva
3150 * this routine is only used for temporary
3151 * kernel mappings that do not need to have
3152 * page modification or references recorded.
3153 * Note that old mappings are simply written
3154 * over. The page *must* be wired.
3155 * Note: SMP coherent. Uses a ranged shootdown IPI.
3158 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3160 pt_entry_t *endpte, oldpte, pa, *pte;
3166 endpte = pte + count;
3167 while (pte < endpte) {
3169 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3170 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3171 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3173 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3177 if (__predict_false((oldpte & X86_PG_V) != 0))
3178 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3183 * This routine tears out page mappings from the
3184 * kernel -- it is meant only for temporary mappings.
3185 * Note: SMP coherent. Uses a ranged shootdown IPI.
3188 pmap_qremove(vm_offset_t sva, int count)
3193 while (count-- > 0) {
3194 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3198 pmap_invalidate_range(kernel_pmap, sva, va);
3201 /***************************************************
3202 * Page table page management routines.....
3203 ***************************************************/
3205 * Schedule the specified unused page table page to be freed. Specifically,
3206 * add the page to the specified list of pages that will be released to the
3207 * physical memory manager after the TLB has been updated.
3209 static __inline void
3210 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3211 boolean_t set_PG_ZERO)
3215 m->flags |= PG_ZERO;
3217 m->flags &= ~PG_ZERO;
3218 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3222 * Inserts the specified page table page into the specified pmap's collection
3223 * of idle page table pages. Each of a pmap's page table pages is responsible
3224 * for mapping a distinct range of virtual addresses. The pmap's collection is
3225 * ordered by this virtual address range.
3227 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3230 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3233 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3234 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3235 return (vm_radix_insert(&pmap->pm_root, mpte));
3239 * Removes the page table page mapping the specified virtual address from the
3240 * specified pmap's collection of idle page table pages, and returns it.
3241 * Otherwise, returns NULL if there is no page table page corresponding to the
3242 * specified virtual address.
3244 static __inline vm_page_t
3245 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3248 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3249 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3253 * Decrements a page table page's wire count, which is used to record the
3254 * number of valid page table entries within the page. If the wire count
3255 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3256 * page table page was unmapped and FALSE otherwise.
3258 static inline boolean_t
3259 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3263 if (m->wire_count == 0) {
3264 _pmap_unwire_ptp(pmap, va, m, free);
3271 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3274 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3276 * unmap the page table page
3278 if (m->pindex >= (NUPDE + NUPDPE)) {
3281 pml4 = pmap_pml4e(pmap, va);
3283 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3284 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3287 } else if (m->pindex >= NUPDE) {
3290 pdp = pmap_pdpe(pmap, va);
3295 pd = pmap_pde(pmap, va);
3298 pmap_resident_count_dec(pmap, 1);
3299 if (m->pindex < NUPDE) {
3300 /* We just released a PT, unhold the matching PD */
3303 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3304 pmap_unwire_ptp(pmap, va, pdpg, free);
3306 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3307 /* We just released a PD, unhold the matching PDP */
3310 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3311 pmap_unwire_ptp(pmap, va, pdppg, free);
3315 * Put page on a list so that it is released after
3316 * *ALL* TLB shootdown is done
3318 pmap_add_delayed_free_list(m, free, TRUE);
3322 * After removing a page table entry, this routine is used to
3323 * conditionally free the page, and manage the hold/wire counts.
3326 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3327 struct spglist *free)
3331 if (va >= VM_MAXUSER_ADDRESS)
3333 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3334 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3335 return (pmap_unwire_ptp(pmap, va, mpte, free));
3339 pmap_pinit0(pmap_t pmap)
3345 PMAP_LOCK_INIT(pmap);
3346 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3347 pmap->pm_pml4u = NULL;
3348 pmap->pm_cr3 = KPML4phys;
3349 /* hack to keep pmap_pti_pcid_invalidate() alive */
3350 pmap->pm_ucr3 = PMAP_NO_CR3;
3351 pmap->pm_root.rt_root = 0;
3352 CPU_ZERO(&pmap->pm_active);
3353 TAILQ_INIT(&pmap->pm_pvchunk);
3354 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3355 pmap->pm_flags = pmap_flags;
3357 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3358 pmap->pm_pcids[i].pm_gen = 1;
3360 pmap_activate_boot(pmap);
3365 p->p_amd64_md_flags |= P_MD_KPTI;
3368 pmap_thread_init_invl_gen(td);
3370 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3371 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3372 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3378 pmap_pinit_pml4(vm_page_t pml4pg)
3380 pml4_entry_t *pm_pml4;
3383 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3385 /* Wire in kernel global address entries. */
3386 for (i = 0; i < NKPML4E; i++) {
3387 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3390 for (i = 0; i < ndmpdpphys; i++) {
3391 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3395 /* install self-referential address mapping entry(s) */
3396 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3397 X86_PG_A | X86_PG_M;
3399 /* install large map entries if configured */
3400 for (i = 0; i < lm_ents; i++)
3401 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3405 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3407 pml4_entry_t *pm_pml4;
3410 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3411 for (i = 0; i < NPML4EPG; i++)
3412 pm_pml4[i] = pti_pml4[i];
3416 * Initialize a preallocated and zeroed pmap structure,
3417 * such as one in a vmspace structure.
3420 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3422 vm_page_t pml4pg, pml4pgu;
3423 vm_paddr_t pml4phys;
3427 * allocate the page directory page
3429 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3430 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3432 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3433 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3435 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3436 pmap->pm_pcids[i].pm_gen = 0;
3438 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3439 pmap->pm_ucr3 = PMAP_NO_CR3;
3440 pmap->pm_pml4u = NULL;
3442 pmap->pm_type = pm_type;
3443 if ((pml4pg->flags & PG_ZERO) == 0)
3444 pagezero(pmap->pm_pml4);
3447 * Do not install the host kernel mappings in the nested page
3448 * tables. These mappings are meaningless in the guest physical
3450 * Install minimal kernel mappings in PTI case.
3452 if (pm_type == PT_X86) {
3453 pmap->pm_cr3 = pml4phys;
3454 pmap_pinit_pml4(pml4pg);
3455 if ((curproc->p_amd64_md_flags & P_MD_KPTI) != 0) {
3456 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3457 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3458 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3459 VM_PAGE_TO_PHYS(pml4pgu));
3460 pmap_pinit_pml4_pti(pml4pgu);
3461 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3463 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3464 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3465 pkru_free_range, pmap, M_NOWAIT);
3469 pmap->pm_root.rt_root = 0;
3470 CPU_ZERO(&pmap->pm_active);
3471 TAILQ_INIT(&pmap->pm_pvchunk);
3472 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3473 pmap->pm_flags = flags;
3474 pmap->pm_eptgen = 0;
3480 pmap_pinit(pmap_t pmap)
3483 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3487 * This routine is called if the desired page table page does not exist.
3489 * If page table page allocation fails, this routine may sleep before
3490 * returning NULL. It sleeps only if a lock pointer was given.
3492 * Note: If a page allocation fails at page table level two or three,
3493 * one or two pages may be held during the wait, only to be released
3494 * afterwards. This conservative approach is easily argued to avoid
3498 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3500 vm_page_t m, pdppg, pdpg;
3501 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3503 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3505 PG_A = pmap_accessed_bit(pmap);
3506 PG_M = pmap_modified_bit(pmap);
3507 PG_V = pmap_valid_bit(pmap);
3508 PG_RW = pmap_rw_bit(pmap);
3511 * Allocate a page table page.
3513 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3514 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3515 if (lockp != NULL) {
3516 RELEASE_PV_LIST_LOCK(lockp);
3518 PMAP_ASSERT_NOT_IN_DI();
3524 * Indicate the need to retry. While waiting, the page table
3525 * page may have been allocated.
3529 if ((m->flags & PG_ZERO) == 0)
3533 * Map the pagetable page into the process address space, if
3534 * it isn't already there.
3537 if (ptepindex >= (NUPDE + NUPDPE)) {
3538 pml4_entry_t *pml4, *pml4u;
3539 vm_pindex_t pml4index;
3541 /* Wire up a new PDPE page */
3542 pml4index = ptepindex - (NUPDE + NUPDPE);
3543 pml4 = &pmap->pm_pml4[pml4index];
3544 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3545 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3547 * PTI: Make all user-space mappings in the
3548 * kernel-mode page table no-execute so that
3549 * we detect any programming errors that leave
3550 * the kernel-mode page table active on return
3553 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3556 pml4u = &pmap->pm_pml4u[pml4index];
3557 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3561 } else if (ptepindex >= NUPDE) {
3562 vm_pindex_t pml4index;
3563 vm_pindex_t pdpindex;
3567 /* Wire up a new PDE page */
3568 pdpindex = ptepindex - NUPDE;
3569 pml4index = pdpindex >> NPML4EPGSHIFT;
3571 pml4 = &pmap->pm_pml4[pml4index];
3572 if ((*pml4 & PG_V) == 0) {
3573 /* Have to allocate a new pdp, recurse */
3574 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3576 vm_page_unwire_noq(m);
3577 vm_page_free_zero(m);
3581 /* Add reference to pdp page */
3582 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3583 pdppg->wire_count++;
3585 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3587 /* Now find the pdp page */
3588 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3589 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3592 vm_pindex_t pml4index;
3593 vm_pindex_t pdpindex;
3598 /* Wire up a new PTE page */
3599 pdpindex = ptepindex >> NPDPEPGSHIFT;
3600 pml4index = pdpindex >> NPML4EPGSHIFT;
3602 /* First, find the pdp and check that its valid. */
3603 pml4 = &pmap->pm_pml4[pml4index];
3604 if ((*pml4 & PG_V) == 0) {
3605 /* Have to allocate a new pd, recurse */
3606 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3608 vm_page_unwire_noq(m);
3609 vm_page_free_zero(m);
3612 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3613 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3615 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3616 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3617 if ((*pdp & PG_V) == 0) {
3618 /* Have to allocate a new pd, recurse */
3619 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3621 vm_page_unwire_noq(m);
3622 vm_page_free_zero(m);
3626 /* Add reference to the pd page */
3627 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3631 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3633 /* Now we know where the page directory page is */
3634 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3635 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3638 pmap_resident_count_inc(pmap, 1);
3644 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3646 vm_pindex_t pdpindex, ptepindex;
3647 pdp_entry_t *pdpe, PG_V;
3650 PG_V = pmap_valid_bit(pmap);
3653 pdpe = pmap_pdpe(pmap, va);
3654 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3655 /* Add a reference to the pd page. */
3656 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3659 /* Allocate a pd page. */
3660 ptepindex = pmap_pde_pindex(va);
3661 pdpindex = ptepindex >> NPDPEPGSHIFT;
3662 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3663 if (pdpg == NULL && lockp != NULL)
3670 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3672 vm_pindex_t ptepindex;
3673 pd_entry_t *pd, PG_V;
3676 PG_V = pmap_valid_bit(pmap);
3679 * Calculate pagetable page index
3681 ptepindex = pmap_pde_pindex(va);
3684 * Get the page directory entry
3686 pd = pmap_pde(pmap, va);
3689 * This supports switching from a 2MB page to a
3692 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3693 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3695 * Invalidation of the 2MB page mapping may have caused
3696 * the deallocation of the underlying PD page.
3703 * If the page table page is mapped, we just increment the
3704 * hold count, and activate it.
3706 if (pd != NULL && (*pd & PG_V) != 0) {
3707 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3711 * Here if the pte page isn't mapped, or if it has been
3714 m = _pmap_allocpte(pmap, ptepindex, lockp);
3715 if (m == NULL && lockp != NULL)
3722 /***************************************************
3723 * Pmap allocation/deallocation routines.
3724 ***************************************************/
3727 * Release any resources held by the given physical map.
3728 * Called when a pmap initialized by pmap_pinit is being released.
3729 * Should only be called if the map contains no valid mappings.
3732 pmap_release(pmap_t pmap)
3737 KASSERT(pmap->pm_stats.resident_count == 0,
3738 ("pmap_release: pmap resident count %ld != 0",
3739 pmap->pm_stats.resident_count));
3740 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3741 ("pmap_release: pmap has reserved page table page(s)"));
3742 KASSERT(CPU_EMPTY(&pmap->pm_active),
3743 ("releasing active pmap %p", pmap));
3745 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3747 for (i = 0; i < NKPML4E; i++) /* KVA */
3748 pmap->pm_pml4[KPML4BASE + i] = 0;
3749 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3750 pmap->pm_pml4[DMPML4I + i] = 0;
3751 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3752 for (i = 0; i < lm_ents; i++) /* Large Map */
3753 pmap->pm_pml4[LMSPML4I + i] = 0;
3755 vm_page_unwire_noq(m);
3756 vm_page_free_zero(m);
3758 if (pmap->pm_pml4u != NULL) {
3759 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3760 vm_page_unwire_noq(m);
3763 if (pmap->pm_type == PT_X86 &&
3764 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3765 rangeset_fini(&pmap->pm_pkru);
3769 kvm_size(SYSCTL_HANDLER_ARGS)
3771 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3773 return sysctl_handle_long(oidp, &ksize, 0, req);
3775 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3776 0, 0, kvm_size, "LU", "Size of KVM");
3779 kvm_free(SYSCTL_HANDLER_ARGS)
3781 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3783 return sysctl_handle_long(oidp, &kfree, 0, req);
3785 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3786 0, 0, kvm_free, "LU", "Amount of KVM free");
3789 * grow the number of kernel page table entries, if needed
3792 pmap_growkernel(vm_offset_t addr)
3796 pd_entry_t *pde, newpdir;
3799 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3802 * Return if "addr" is within the range of kernel page table pages
3803 * that were preallocated during pmap bootstrap. Moreover, leave
3804 * "kernel_vm_end" and the kernel page table as they were.
3806 * The correctness of this action is based on the following
3807 * argument: vm_map_insert() allocates contiguous ranges of the
3808 * kernel virtual address space. It calls this function if a range
3809 * ends after "kernel_vm_end". If the kernel is mapped between
3810 * "kernel_vm_end" and "addr", then the range cannot begin at
3811 * "kernel_vm_end". In fact, its beginning address cannot be less
3812 * than the kernel. Thus, there is no immediate need to allocate
3813 * any new kernel page table pages between "kernel_vm_end" and
3816 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3819 addr = roundup2(addr, NBPDR);
3820 if (addr - 1 >= vm_map_max(kernel_map))
3821 addr = vm_map_max(kernel_map);
3822 while (kernel_vm_end < addr) {
3823 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3824 if ((*pdpe & X86_PG_V) == 0) {
3825 /* We need a new PDP entry */
3826 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3827 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3828 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3830 panic("pmap_growkernel: no memory to grow kernel");
3831 if ((nkpg->flags & PG_ZERO) == 0)
3832 pmap_zero_page(nkpg);
3833 paddr = VM_PAGE_TO_PHYS(nkpg);
3834 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3835 X86_PG_A | X86_PG_M);
3836 continue; /* try again */
3838 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3839 if ((*pde & X86_PG_V) != 0) {
3840 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3841 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3842 kernel_vm_end = vm_map_max(kernel_map);
3848 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3849 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3852 panic("pmap_growkernel: no memory to grow kernel");
3853 if ((nkpg->flags & PG_ZERO) == 0)
3854 pmap_zero_page(nkpg);
3855 paddr = VM_PAGE_TO_PHYS(nkpg);
3856 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3857 pde_store(pde, newpdir);
3859 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3860 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3861 kernel_vm_end = vm_map_max(kernel_map);
3868 /***************************************************
3869 * page management routines.
3870 ***************************************************/
3872 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3873 CTASSERT(_NPCM == 3);
3874 CTASSERT(_NPCPV == 168);
3876 static __inline struct pv_chunk *
3877 pv_to_chunk(pv_entry_t pv)
3880 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3883 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3885 #define PC_FREE0 0xfffffffffffffffful
3886 #define PC_FREE1 0xfffffffffffffffful
3887 #define PC_FREE2 0x000000fffffffffful
3889 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3892 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3894 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3895 "Current number of pv entry chunks");
3896 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3897 "Current number of pv entry chunks allocated");
3898 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3899 "Current number of pv entry chunks frees");
3900 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3901 "Number of times tried to get a chunk page but failed.");
3903 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3904 static int pv_entry_spare;
3906 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3907 "Current number of pv entry frees");
3908 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3909 "Current number of pv entry allocs");
3910 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3911 "Current number of pv entries");
3912 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3913 "Current number of spare pv entries");
3917 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3922 pmap_invalidate_all(pmap);
3923 if (pmap != locked_pmap)
3926 pmap_delayed_invl_finish();
3930 * We are in a serious low memory condition. Resort to
3931 * drastic measures to free some pages so we can allocate
3932 * another pv entry chunk.
3934 * Returns NULL if PV entries were reclaimed from the specified pmap.
3936 * We do not, however, unmap 2mpages because subsequent accesses will
3937 * allocate per-page pv entries until repromotion occurs, thereby
3938 * exacerbating the shortage of free pv entries.
3941 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3943 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3944 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3945 struct md_page *pvh;
3947 pmap_t next_pmap, pmap;
3948 pt_entry_t *pte, tpte;
3949 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3953 struct spglist free;
3955 int bit, field, freed;
3957 static int active_reclaims = 0;
3959 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3960 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3963 PG_G = PG_A = PG_M = PG_RW = 0;
3965 bzero(&pc_marker_b, sizeof(pc_marker_b));
3966 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3967 pc_marker = (struct pv_chunk *)&pc_marker_b;
3968 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3971 * A delayed invalidation block should already be active if
3972 * pmap_advise() or pmap_remove() called this function by way
3973 * of pmap_demote_pde_locked().
3975 start_di = pmap_not_in_di();
3977 mtx_lock(&pv_chunks_mutex);
3979 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3980 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3981 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3982 SLIST_EMPTY(&free)) {
3983 next_pmap = pc->pc_pmap;
3984 if (next_pmap == NULL) {
3986 * The next chunk is a marker. However, it is
3987 * not our marker, so active_reclaims must be
3988 * > 1. Consequently, the next_chunk code
3989 * will not rotate the pv_chunks list.
3993 mtx_unlock(&pv_chunks_mutex);
3996 * A pv_chunk can only be removed from the pc_lru list
3997 * when both pc_chunks_mutex is owned and the
3998 * corresponding pmap is locked.
4000 if (pmap != next_pmap) {
4001 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4004 /* Avoid deadlock and lock recursion. */
4005 if (pmap > locked_pmap) {
4006 RELEASE_PV_LIST_LOCK(lockp);
4009 pmap_delayed_invl_start();
4010 mtx_lock(&pv_chunks_mutex);
4012 } else if (pmap != locked_pmap) {
4013 if (PMAP_TRYLOCK(pmap)) {
4015 pmap_delayed_invl_start();
4016 mtx_lock(&pv_chunks_mutex);
4019 pmap = NULL; /* pmap is not locked */
4020 mtx_lock(&pv_chunks_mutex);
4021 pc = TAILQ_NEXT(pc_marker, pc_lru);
4023 pc->pc_pmap != next_pmap)
4027 } else if (start_di)
4028 pmap_delayed_invl_start();
4029 PG_G = pmap_global_bit(pmap);
4030 PG_A = pmap_accessed_bit(pmap);
4031 PG_M = pmap_modified_bit(pmap);
4032 PG_RW = pmap_rw_bit(pmap);
4036 * Destroy every non-wired, 4 KB page mapping in the chunk.
4039 for (field = 0; field < _NPCM; field++) {
4040 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4041 inuse != 0; inuse &= ~(1UL << bit)) {
4043 pv = &pc->pc_pventry[field * 64 + bit];
4045 pde = pmap_pde(pmap, va);
4046 if ((*pde & PG_PS) != 0)
4048 pte = pmap_pde_to_pte(pde, va);
4049 if ((*pte & PG_W) != 0)
4051 tpte = pte_load_clear(pte);
4052 if ((tpte & PG_G) != 0)
4053 pmap_invalidate_page(pmap, va);
4054 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4055 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4057 if ((tpte & PG_A) != 0)
4058 vm_page_aflag_set(m, PGA_REFERENCED);
4059 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4060 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4062 if (TAILQ_EMPTY(&m->md.pv_list) &&
4063 (m->flags & PG_FICTITIOUS) == 0) {
4064 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4065 if (TAILQ_EMPTY(&pvh->pv_list)) {
4066 vm_page_aflag_clear(m,
4070 pmap_delayed_invl_page(m);
4071 pc->pc_map[field] |= 1UL << bit;
4072 pmap_unuse_pt(pmap, va, *pde, &free);
4077 mtx_lock(&pv_chunks_mutex);
4080 /* Every freed mapping is for a 4 KB page. */
4081 pmap_resident_count_dec(pmap, freed);
4082 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4083 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4084 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4085 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4086 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4087 pc->pc_map[2] == PC_FREE2) {
4088 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4089 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4090 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4091 /* Entire chunk is free; return it. */
4092 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4093 dump_drop_page(m_pc->phys_addr);
4094 mtx_lock(&pv_chunks_mutex);
4095 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4098 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4099 mtx_lock(&pv_chunks_mutex);
4100 /* One freed pv entry in locked_pmap is sufficient. */
4101 if (pmap == locked_pmap)
4104 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4105 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
4106 if (active_reclaims == 1 && pmap != NULL) {
4108 * Rotate the pv chunks list so that we do not
4109 * scan the same pv chunks that could not be
4110 * freed (because they contained a wired
4111 * and/or superpage mapping) on every
4112 * invocation of reclaim_pv_chunk().
4114 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4115 MPASS(pc->pc_pmap != NULL);
4116 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4117 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4121 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4122 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4124 mtx_unlock(&pv_chunks_mutex);
4125 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4126 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4127 m_pc = SLIST_FIRST(&free);
4128 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4129 /* Recycle a freed page table page. */
4130 m_pc->wire_count = 1;
4132 vm_page_free_pages_toq(&free, true);
4137 * free the pv_entry back to the free list
4140 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4142 struct pv_chunk *pc;
4143 int idx, field, bit;
4145 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4146 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4147 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4148 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4149 pc = pv_to_chunk(pv);
4150 idx = pv - &pc->pc_pventry[0];
4153 pc->pc_map[field] |= 1ul << bit;
4154 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4155 pc->pc_map[2] != PC_FREE2) {
4156 /* 98% of the time, pc is already at the head of the list. */
4157 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4158 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4159 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4163 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4168 free_pv_chunk(struct pv_chunk *pc)
4172 mtx_lock(&pv_chunks_mutex);
4173 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4174 mtx_unlock(&pv_chunks_mutex);
4175 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4176 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4177 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4178 /* entire chunk is free, return it */
4179 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4180 dump_drop_page(m->phys_addr);
4181 vm_page_unwire_noq(m);
4186 * Returns a new PV entry, allocating a new PV chunk from the system when
4187 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4188 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4191 * The given PV list lock may be released.
4194 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4198 struct pv_chunk *pc;
4201 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4202 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4204 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4206 for (field = 0; field < _NPCM; field++) {
4207 if (pc->pc_map[field]) {
4208 bit = bsfq(pc->pc_map[field]);
4212 if (field < _NPCM) {
4213 pv = &pc->pc_pventry[field * 64 + bit];
4214 pc->pc_map[field] &= ~(1ul << bit);
4215 /* If this was the last item, move it to tail */
4216 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4217 pc->pc_map[2] == 0) {
4218 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4219 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4222 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4223 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4227 /* No free items, allocate another chunk */
4228 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4231 if (lockp == NULL) {
4232 PV_STAT(pc_chunk_tryfail++);
4235 m = reclaim_pv_chunk(pmap, lockp);
4239 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4240 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4241 dump_add_page(m->phys_addr);
4242 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4244 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4245 pc->pc_map[1] = PC_FREE1;
4246 pc->pc_map[2] = PC_FREE2;
4247 mtx_lock(&pv_chunks_mutex);
4248 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4249 mtx_unlock(&pv_chunks_mutex);
4250 pv = &pc->pc_pventry[0];
4251 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4252 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4253 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4258 * Returns the number of one bits within the given PV chunk map.
4260 * The erratas for Intel processors state that "POPCNT Instruction May
4261 * Take Longer to Execute Than Expected". It is believed that the
4262 * issue is the spurious dependency on the destination register.
4263 * Provide a hint to the register rename logic that the destination
4264 * value is overwritten, by clearing it, as suggested in the
4265 * optimization manual. It should be cheap for unaffected processors
4268 * Reference numbers for erratas are
4269 * 4th Gen Core: HSD146
4270 * 5th Gen Core: BDM85
4271 * 6th Gen Core: SKL029
4274 popcnt_pc_map_pq(uint64_t *map)
4278 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4279 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4280 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4281 : "=&r" (result), "=&r" (tmp)
4282 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4287 * Ensure that the number of spare PV entries in the specified pmap meets or
4288 * exceeds the given count, "needed".
4290 * The given PV list lock may be released.
4293 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4295 struct pch new_tail;
4296 struct pv_chunk *pc;
4301 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4302 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4305 * Newly allocated PV chunks must be stored in a private list until
4306 * the required number of PV chunks have been allocated. Otherwise,
4307 * reclaim_pv_chunk() could recycle one of these chunks. In
4308 * contrast, these chunks must be added to the pmap upon allocation.
4310 TAILQ_INIT(&new_tail);
4313 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4315 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4316 bit_count((bitstr_t *)pc->pc_map, 0,
4317 sizeof(pc->pc_map) * NBBY, &free);
4320 free = popcnt_pc_map_pq(pc->pc_map);
4324 if (avail >= needed)
4327 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4328 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4331 m = reclaim_pv_chunk(pmap, lockp);
4336 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4337 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4338 dump_add_page(m->phys_addr);
4339 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4341 pc->pc_map[0] = PC_FREE0;
4342 pc->pc_map[1] = PC_FREE1;
4343 pc->pc_map[2] = PC_FREE2;
4344 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4345 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4346 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4349 * The reclaim might have freed a chunk from the current pmap.
4350 * If that chunk contained available entries, we need to
4351 * re-count the number of available entries.
4356 if (!TAILQ_EMPTY(&new_tail)) {
4357 mtx_lock(&pv_chunks_mutex);
4358 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4359 mtx_unlock(&pv_chunks_mutex);
4364 * First find and then remove the pv entry for the specified pmap and virtual
4365 * address from the specified pv list. Returns the pv entry if found and NULL
4366 * otherwise. This operation can be performed on pv lists for either 4KB or
4367 * 2MB page mappings.
4369 static __inline pv_entry_t
4370 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4374 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4375 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4376 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4385 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4386 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4387 * entries for each of the 4KB page mappings.
4390 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4391 struct rwlock **lockp)
4393 struct md_page *pvh;
4394 struct pv_chunk *pc;
4396 vm_offset_t va_last;
4400 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4401 KASSERT((pa & PDRMASK) == 0,
4402 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4403 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4406 * Transfer the 2mpage's pv entry for this mapping to the first
4407 * page's pv list. Once this transfer begins, the pv list lock
4408 * must not be released until the last pv entry is reinstantiated.
4410 pvh = pa_to_pvh(pa);
4411 va = trunc_2mpage(va);
4412 pv = pmap_pvh_remove(pvh, pmap, va);
4413 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4414 m = PHYS_TO_VM_PAGE(pa);
4415 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4417 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4418 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4419 va_last = va + NBPDR - PAGE_SIZE;
4421 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4422 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4423 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4424 for (field = 0; field < _NPCM; field++) {
4425 while (pc->pc_map[field]) {
4426 bit = bsfq(pc->pc_map[field]);
4427 pc->pc_map[field] &= ~(1ul << bit);
4428 pv = &pc->pc_pventry[field * 64 + bit];
4432 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4433 ("pmap_pv_demote_pde: page %p is not managed", m));
4434 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4440 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4441 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4444 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4445 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4446 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4448 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4449 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4452 #if VM_NRESERVLEVEL > 0
4454 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4455 * replace the many pv entries for the 4KB page mappings by a single pv entry
4456 * for the 2MB page mapping.
4459 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4460 struct rwlock **lockp)
4462 struct md_page *pvh;
4464 vm_offset_t va_last;
4467 KASSERT((pa & PDRMASK) == 0,
4468 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4469 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4472 * Transfer the first page's pv entry for this mapping to the 2mpage's
4473 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4474 * a transfer avoids the possibility that get_pv_entry() calls
4475 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4476 * mappings that is being promoted.
4478 m = PHYS_TO_VM_PAGE(pa);
4479 va = trunc_2mpage(va);
4480 pv = pmap_pvh_remove(&m->md, pmap, va);
4481 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4482 pvh = pa_to_pvh(pa);
4483 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4485 /* Free the remaining NPTEPG - 1 pv entries. */
4486 va_last = va + NBPDR - PAGE_SIZE;
4490 pmap_pvh_free(&m->md, pmap, va);
4491 } while (va < va_last);
4493 #endif /* VM_NRESERVLEVEL > 0 */
4496 * First find and then destroy the pv entry for the specified pmap and virtual
4497 * address. This operation can be performed on pv lists for either 4KB or 2MB
4501 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4505 pv = pmap_pvh_remove(pvh, pmap, va);
4506 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4507 free_pv_entry(pmap, pv);
4511 * Conditionally create the PV entry for a 4KB page mapping if the required
4512 * memory can be allocated without resorting to reclamation.
4515 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4516 struct rwlock **lockp)
4520 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4521 /* Pass NULL instead of the lock pointer to disable reclamation. */
4522 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4524 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4525 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4533 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4534 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4535 * false if the PV entry cannot be allocated without resorting to reclamation.
4538 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4539 struct rwlock **lockp)
4541 struct md_page *pvh;
4545 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4546 /* Pass NULL instead of the lock pointer to disable reclamation. */
4547 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4548 NULL : lockp)) == NULL)
4551 pa = pde & PG_PS_FRAME;
4552 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4553 pvh = pa_to_pvh(pa);
4554 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4560 * Fills a page table page with mappings to consecutive physical pages.
4563 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4567 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4569 newpte += PAGE_SIZE;
4574 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4575 * mapping is invalidated.
4578 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4580 struct rwlock *lock;
4584 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4591 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4595 pt_entry_t *xpte, *ypte;
4597 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4598 xpte++, newpte += PAGE_SIZE) {
4599 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4600 printf("pmap_demote_pde: xpte %zd and newpte map "
4601 "different pages: found %#lx, expected %#lx\n",
4602 xpte - firstpte, *xpte, newpte);
4603 printf("page table dump\n");
4604 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4605 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4610 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4611 ("pmap_demote_pde: firstpte and newpte map different physical"
4618 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4619 pd_entry_t oldpde, struct rwlock **lockp)
4621 struct spglist free;
4625 sva = trunc_2mpage(va);
4626 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4627 if ((oldpde & pmap_global_bit(pmap)) == 0)
4628 pmap_invalidate_pde_page(pmap, sva, oldpde);
4629 vm_page_free_pages_toq(&free, true);
4630 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
4635 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4636 struct rwlock **lockp)
4638 pd_entry_t newpde, oldpde;
4639 pt_entry_t *firstpte, newpte;
4640 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4646 PG_A = pmap_accessed_bit(pmap);
4647 PG_G = pmap_global_bit(pmap);
4648 PG_M = pmap_modified_bit(pmap);
4649 PG_RW = pmap_rw_bit(pmap);
4650 PG_V = pmap_valid_bit(pmap);
4651 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4652 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4654 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4655 in_kernel = va >= VM_MAXUSER_ADDRESS;
4657 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4658 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4661 * Invalidate the 2MB page mapping and return "failure" if the
4662 * mapping was never accessed.
4664 if ((oldpde & PG_A) == 0) {
4665 KASSERT((oldpde & PG_W) == 0,
4666 ("pmap_demote_pde: a wired mapping is missing PG_A"));
4667 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4671 mpte = pmap_remove_pt_page(pmap, va);
4673 KASSERT((oldpde & PG_W) == 0,
4674 ("pmap_demote_pde: page table page for a wired mapping"
4678 * If the page table page is missing and the mapping
4679 * is for a kernel address, the mapping must belong to
4680 * the direct map. Page table pages are preallocated
4681 * for every other part of the kernel address space,
4682 * so the direct map region is the only part of the
4683 * kernel address space that must be handled here.
4685 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
4686 va < DMAP_MAX_ADDRESS),
4687 ("pmap_demote_pde: No saved mpte for va %#lx", va));
4690 * If the 2MB page mapping belongs to the direct map
4691 * region of the kernel's address space, then the page
4692 * allocation request specifies the highest possible
4693 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
4694 * priority is normal.
4696 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
4697 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4698 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4701 * If the allocation of the new page table page fails,
4702 * invalidate the 2MB page mapping and return "failure".
4705 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4710 mpte->wire_count = NPTEPG;
4711 pmap_resident_count_inc(pmap, 1);
4714 mptepa = VM_PAGE_TO_PHYS(mpte);
4715 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4716 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4717 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4718 ("pmap_demote_pde: oldpde is missing PG_M"));
4719 newpte = oldpde & ~PG_PS;
4720 newpte = pmap_swap_pat(pmap, newpte);
4723 * If the page table page is not leftover from an earlier promotion,
4726 if (mpte->valid == 0)
4727 pmap_fill_ptp(firstpte, newpte);
4729 pmap_demote_pde_check(firstpte, newpte);
4732 * If the mapping has changed attributes, update the page table
4735 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4736 pmap_fill_ptp(firstpte, newpte);
4739 * The spare PV entries must be reserved prior to demoting the
4740 * mapping, that is, prior to changing the PDE. Otherwise, the state
4741 * of the PDE and the PV lists will be inconsistent, which can result
4742 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4743 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4744 * PV entry for the 2MB page mapping that is being demoted.
4746 if ((oldpde & PG_MANAGED) != 0)
4747 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4750 * Demote the mapping. This pmap is locked. The old PDE has
4751 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4752 * set. Thus, there is no danger of a race with another
4753 * processor changing the setting of PG_A and/or PG_M between
4754 * the read above and the store below.
4756 if (workaround_erratum383)
4757 pmap_update_pde(pmap, va, pde, newpde);
4759 pde_store(pde, newpde);
4762 * Invalidate a stale recursive mapping of the page table page.
4765 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4768 * Demote the PV entry.
4770 if ((oldpde & PG_MANAGED) != 0)
4771 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4773 atomic_add_long(&pmap_pde_demotions, 1);
4774 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
4780 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4783 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4789 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4790 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4791 mpte = pmap_remove_pt_page(pmap, va);
4793 panic("pmap_remove_kernel_pde: Missing pt page.");
4795 mptepa = VM_PAGE_TO_PHYS(mpte);
4796 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4799 * If this page table page was unmapped by a promotion, then it
4800 * contains valid mappings. Zero it to invalidate those mappings.
4802 if (mpte->valid != 0)
4803 pagezero((void *)PHYS_TO_DMAP(mptepa));
4806 * Demote the mapping.
4808 if (workaround_erratum383)
4809 pmap_update_pde(pmap, va, pde, newpde);
4811 pde_store(pde, newpde);
4814 * Invalidate a stale recursive mapping of the page table page.
4816 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4820 * pmap_remove_pde: do the things to unmap a superpage in a process
4823 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4824 struct spglist *free, struct rwlock **lockp)
4826 struct md_page *pvh;
4828 vm_offset_t eva, va;
4830 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4832 PG_G = pmap_global_bit(pmap);
4833 PG_A = pmap_accessed_bit(pmap);
4834 PG_M = pmap_modified_bit(pmap);
4835 PG_RW = pmap_rw_bit(pmap);
4837 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4838 KASSERT((sva & PDRMASK) == 0,
4839 ("pmap_remove_pde: sva is not 2mpage aligned"));
4840 oldpde = pte_load_clear(pdq);
4842 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4843 if ((oldpde & PG_G) != 0)
4844 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4845 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4846 if (oldpde & PG_MANAGED) {
4847 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4848 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4849 pmap_pvh_free(pvh, pmap, sva);
4851 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4852 va < eva; va += PAGE_SIZE, m++) {
4853 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4856 vm_page_aflag_set(m, PGA_REFERENCED);
4857 if (TAILQ_EMPTY(&m->md.pv_list) &&
4858 TAILQ_EMPTY(&pvh->pv_list))
4859 vm_page_aflag_clear(m, PGA_WRITEABLE);
4860 pmap_delayed_invl_page(m);
4863 if (pmap == kernel_pmap) {
4864 pmap_remove_kernel_pde(pmap, pdq, sva);
4866 mpte = pmap_remove_pt_page(pmap, sva);
4868 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4869 ("pmap_remove_pde: pte page not promoted"));
4870 pmap_resident_count_dec(pmap, 1);
4871 KASSERT(mpte->wire_count == NPTEPG,
4872 ("pmap_remove_pde: pte page wire count error"));
4873 mpte->wire_count = 0;
4874 pmap_add_delayed_free_list(mpte, free, FALSE);
4877 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4881 * pmap_remove_pte: do the things to unmap a page in a process
4884 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4885 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4887 struct md_page *pvh;
4888 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4891 PG_A = pmap_accessed_bit(pmap);
4892 PG_M = pmap_modified_bit(pmap);
4893 PG_RW = pmap_rw_bit(pmap);
4895 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4896 oldpte = pte_load_clear(ptq);
4898 pmap->pm_stats.wired_count -= 1;
4899 pmap_resident_count_dec(pmap, 1);
4900 if (oldpte & PG_MANAGED) {
4901 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4902 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4905 vm_page_aflag_set(m, PGA_REFERENCED);
4906 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4907 pmap_pvh_free(&m->md, pmap, va);
4908 if (TAILQ_EMPTY(&m->md.pv_list) &&
4909 (m->flags & PG_FICTITIOUS) == 0) {
4910 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4911 if (TAILQ_EMPTY(&pvh->pv_list))
4912 vm_page_aflag_clear(m, PGA_WRITEABLE);
4914 pmap_delayed_invl_page(m);
4916 return (pmap_unuse_pt(pmap, va, ptepde, free));
4920 * Remove a single page from a process address space
4923 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4924 struct spglist *free)
4926 struct rwlock *lock;
4927 pt_entry_t *pte, PG_V;
4929 PG_V = pmap_valid_bit(pmap);
4930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4931 if ((*pde & PG_V) == 0)
4933 pte = pmap_pde_to_pte(pde, va);
4934 if ((*pte & PG_V) == 0)
4937 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4940 pmap_invalidate_page(pmap, va);
4944 * Removes the specified range of addresses from the page table page.
4947 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4948 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4950 pt_entry_t PG_G, *pte;
4954 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4955 PG_G = pmap_global_bit(pmap);
4958 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4962 pmap_invalidate_range(pmap, va, sva);
4967 if ((*pte & PG_G) == 0)
4971 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4977 pmap_invalidate_range(pmap, va, sva);
4982 * Remove the given range of addresses from the specified map.
4984 * It is assumed that the start and end are properly
4985 * rounded to the page size.
4988 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4990 struct rwlock *lock;
4991 vm_offset_t va_next;
4992 pml4_entry_t *pml4e;
4994 pd_entry_t ptpaddr, *pde;
4995 pt_entry_t PG_G, PG_V;
4996 struct spglist free;
4999 PG_G = pmap_global_bit(pmap);
5000 PG_V = pmap_valid_bit(pmap);
5003 * Perform an unsynchronized read. This is, however, safe.
5005 if (pmap->pm_stats.resident_count == 0)
5011 pmap_delayed_invl_start();
5013 pmap_pkru_on_remove(pmap, sva, eva);
5016 * special handling of removing one page. a very
5017 * common operation and easy to short circuit some
5020 if (sva + PAGE_SIZE == eva) {
5021 pde = pmap_pde(pmap, sva);
5022 if (pde && (*pde & PG_PS) == 0) {
5023 pmap_remove_page(pmap, sva, pde, &free);
5029 for (; sva < eva; sva = va_next) {
5031 if (pmap->pm_stats.resident_count == 0)
5034 pml4e = pmap_pml4e(pmap, sva);
5035 if ((*pml4e & PG_V) == 0) {
5036 va_next = (sva + NBPML4) & ~PML4MASK;
5042 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5043 if ((*pdpe & PG_V) == 0) {
5044 va_next = (sva + NBPDP) & ~PDPMASK;
5051 * Calculate index for next page table.
5053 va_next = (sva + NBPDR) & ~PDRMASK;
5057 pde = pmap_pdpe_to_pde(pdpe, sva);
5061 * Weed out invalid mappings.
5067 * Check for large page.
5069 if ((ptpaddr & PG_PS) != 0) {
5071 * Are we removing the entire large page? If not,
5072 * demote the mapping and fall through.
5074 if (sva + NBPDR == va_next && eva >= va_next) {
5076 * The TLB entry for a PG_G mapping is
5077 * invalidated by pmap_remove_pde().
5079 if ((ptpaddr & PG_G) == 0)
5081 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5083 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5085 /* The large page mapping was destroyed. */
5092 * Limit our scan to either the end of the va represented
5093 * by the current page table page, or to the end of the
5094 * range being removed.
5099 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5106 pmap_invalidate_all(pmap);
5108 pmap_delayed_invl_finish();
5109 vm_page_free_pages_toq(&free, true);
5113 * Routine: pmap_remove_all
5115 * Removes this physical page from
5116 * all physical maps in which it resides.
5117 * Reflects back modify bits to the pager.
5120 * Original versions of this routine were very
5121 * inefficient because they iteratively called
5122 * pmap_remove (slow...)
5126 pmap_remove_all(vm_page_t m)
5128 struct md_page *pvh;
5131 struct rwlock *lock;
5132 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5135 struct spglist free;
5136 int pvh_gen, md_gen;
5138 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5139 ("pmap_remove_all: page %p is not managed", m));
5141 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5142 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5143 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5146 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5148 if (!PMAP_TRYLOCK(pmap)) {
5149 pvh_gen = pvh->pv_gen;
5153 if (pvh_gen != pvh->pv_gen) {
5160 pde = pmap_pde(pmap, va);
5161 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5164 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5166 if (!PMAP_TRYLOCK(pmap)) {
5167 pvh_gen = pvh->pv_gen;
5168 md_gen = m->md.pv_gen;
5172 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5178 PG_A = pmap_accessed_bit(pmap);
5179 PG_M = pmap_modified_bit(pmap);
5180 PG_RW = pmap_rw_bit(pmap);
5181 pmap_resident_count_dec(pmap, 1);
5182 pde = pmap_pde(pmap, pv->pv_va);
5183 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5184 " a 2mpage in page %p's pv list", m));
5185 pte = pmap_pde_to_pte(pde, pv->pv_va);
5186 tpte = pte_load_clear(pte);
5188 pmap->pm_stats.wired_count--;
5190 vm_page_aflag_set(m, PGA_REFERENCED);
5193 * Update the vm_page_t clean and reference bits.
5195 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5197 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5198 pmap_invalidate_page(pmap, pv->pv_va);
5199 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5201 free_pv_entry(pmap, pv);
5204 vm_page_aflag_clear(m, PGA_WRITEABLE);
5206 pmap_delayed_invl_wait(m);
5207 vm_page_free_pages_toq(&free, true);
5211 * pmap_protect_pde: do the things to protect a 2mpage in a process
5214 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5216 pd_entry_t newpde, oldpde;
5217 vm_offset_t eva, va;
5219 boolean_t anychanged;
5220 pt_entry_t PG_G, PG_M, PG_RW;
5222 PG_G = pmap_global_bit(pmap);
5223 PG_M = pmap_modified_bit(pmap);
5224 PG_RW = pmap_rw_bit(pmap);
5226 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5227 KASSERT((sva & PDRMASK) == 0,
5228 ("pmap_protect_pde: sva is not 2mpage aligned"));
5231 oldpde = newpde = *pde;
5232 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5233 (PG_MANAGED | PG_M | PG_RW)) {
5235 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5236 va < eva; va += PAGE_SIZE, m++)
5239 if ((prot & VM_PROT_WRITE) == 0)
5240 newpde &= ~(PG_RW | PG_M);
5241 if ((prot & VM_PROT_EXECUTE) == 0)
5243 if (newpde != oldpde) {
5245 * As an optimization to future operations on this PDE, clear
5246 * PG_PROMOTED. The impending invalidation will remove any
5247 * lingering 4KB page mappings from the TLB.
5249 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5251 if ((oldpde & PG_G) != 0)
5252 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5256 return (anychanged);
5260 * Set the physical protection on the
5261 * specified range of this map as requested.
5264 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5266 vm_offset_t va_next;
5267 pml4_entry_t *pml4e;
5269 pd_entry_t ptpaddr, *pde;
5270 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5271 boolean_t anychanged;
5273 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5274 if (prot == VM_PROT_NONE) {
5275 pmap_remove(pmap, sva, eva);
5279 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5280 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5283 PG_G = pmap_global_bit(pmap);
5284 PG_M = pmap_modified_bit(pmap);
5285 PG_V = pmap_valid_bit(pmap);
5286 PG_RW = pmap_rw_bit(pmap);
5290 * Although this function delays and batches the invalidation
5291 * of stale TLB entries, it does not need to call
5292 * pmap_delayed_invl_start() and
5293 * pmap_delayed_invl_finish(), because it does not
5294 * ordinarily destroy mappings. Stale TLB entries from
5295 * protection-only changes need only be invalidated before the
5296 * pmap lock is released, because protection-only changes do
5297 * not destroy PV entries. Even operations that iterate over
5298 * a physical page's PV list of mappings, like
5299 * pmap_remove_write(), acquire the pmap lock for each
5300 * mapping. Consequently, for protection-only changes, the
5301 * pmap lock suffices to synchronize both page table and TLB
5304 * This function only destroys a mapping if pmap_demote_pde()
5305 * fails. In that case, stale TLB entries are immediately
5310 for (; sva < eva; sva = va_next) {
5312 pml4e = pmap_pml4e(pmap, sva);
5313 if ((*pml4e & PG_V) == 0) {
5314 va_next = (sva + NBPML4) & ~PML4MASK;
5320 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5321 if ((*pdpe & PG_V) == 0) {
5322 va_next = (sva + NBPDP) & ~PDPMASK;
5328 va_next = (sva + NBPDR) & ~PDRMASK;
5332 pde = pmap_pdpe_to_pde(pdpe, sva);
5336 * Weed out invalid mappings.
5342 * Check for large page.
5344 if ((ptpaddr & PG_PS) != 0) {
5346 * Are we protecting the entire large page? If not,
5347 * demote the mapping and fall through.
5349 if (sva + NBPDR == va_next && eva >= va_next) {
5351 * The TLB entry for a PG_G mapping is
5352 * invalidated by pmap_protect_pde().
5354 if (pmap_protect_pde(pmap, pde, sva, prot))
5357 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5359 * The large page mapping was destroyed.
5368 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5370 pt_entry_t obits, pbits;
5374 obits = pbits = *pte;
5375 if ((pbits & PG_V) == 0)
5378 if ((prot & VM_PROT_WRITE) == 0) {
5379 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5380 (PG_MANAGED | PG_M | PG_RW)) {
5381 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5384 pbits &= ~(PG_RW | PG_M);
5386 if ((prot & VM_PROT_EXECUTE) == 0)
5389 if (pbits != obits) {
5390 if (!atomic_cmpset_long(pte, obits, pbits))
5393 pmap_invalidate_page(pmap, sva);
5400 pmap_invalidate_all(pmap);
5404 #if VM_NRESERVLEVEL > 0
5406 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5407 * single page table page (PTP) to a single 2MB page mapping. For promotion
5408 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5409 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5410 * identical characteristics.
5413 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5414 struct rwlock **lockp)
5417 pt_entry_t *firstpte, oldpte, pa, *pte;
5418 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5422 PG_A = pmap_accessed_bit(pmap);
5423 PG_G = pmap_global_bit(pmap);
5424 PG_M = pmap_modified_bit(pmap);
5425 PG_V = pmap_valid_bit(pmap);
5426 PG_RW = pmap_rw_bit(pmap);
5427 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5428 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5430 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5433 * Examine the first PTE in the specified PTP. Abort if this PTE is
5434 * either invalid, unused, or does not map the first 4KB physical page
5435 * within a 2MB page.
5437 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5440 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
5441 atomic_add_long(&pmap_pde_p_failures, 1);
5442 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5443 " in pmap %p", va, pmap);
5446 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5448 * When PG_M is already clear, PG_RW can be cleared without
5449 * a TLB invalidation.
5451 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5457 * Examine each of the other PTEs in the specified PTP. Abort if this
5458 * PTE maps an unexpected 4KB physical page or does not have identical
5459 * characteristics to the first PTE.
5461 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5462 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5465 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5466 atomic_add_long(&pmap_pde_p_failures, 1);
5467 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5468 " in pmap %p", va, pmap);
5471 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5473 * When PG_M is already clear, PG_RW can be cleared
5474 * without a TLB invalidation.
5476 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5479 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5480 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5481 (va & ~PDRMASK), pmap);
5483 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5484 atomic_add_long(&pmap_pde_p_failures, 1);
5485 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5486 " in pmap %p", va, pmap);
5493 * Save the page table page in its current state until the PDE
5494 * mapping the superpage is demoted by pmap_demote_pde() or
5495 * destroyed by pmap_remove_pde().
5497 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5498 KASSERT(mpte >= vm_page_array &&
5499 mpte < &vm_page_array[vm_page_array_size],
5500 ("pmap_promote_pde: page table page is out of range"));
5501 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5502 ("pmap_promote_pde: page table page's pindex is wrong"));
5503 if (pmap_insert_pt_page(pmap, mpte, true)) {
5504 atomic_add_long(&pmap_pde_p_failures, 1);
5506 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5512 * Promote the pv entries.
5514 if ((newpde & PG_MANAGED) != 0)
5515 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5518 * Propagate the PAT index to its proper position.
5520 newpde = pmap_swap_pat(pmap, newpde);
5523 * Map the superpage.
5525 if (workaround_erratum383)
5526 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5528 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5530 atomic_add_long(&pmap_pde_promotions, 1);
5531 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5532 " in pmap %p", va, pmap);
5534 #endif /* VM_NRESERVLEVEL > 0 */
5537 * Insert the given physical page (p) at
5538 * the specified virtual address (v) in the
5539 * target physical map with the protection requested.
5541 * If specified, the page will be wired down, meaning
5542 * that the related pte can not be reclaimed.
5544 * NB: This is the only routine which MAY NOT lazy-evaluate
5545 * or lose information. That is, this routine must actually
5546 * insert this page into the given map NOW.
5548 * When destroying both a page table and PV entry, this function
5549 * performs the TLB invalidation before releasing the PV list
5550 * lock, so we do not need pmap_delayed_invl_page() calls here.
5553 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5554 u_int flags, int8_t psind)
5556 struct rwlock *lock;
5558 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5559 pt_entry_t newpte, origpte;
5566 PG_A = pmap_accessed_bit(pmap);
5567 PG_G = pmap_global_bit(pmap);
5568 PG_M = pmap_modified_bit(pmap);
5569 PG_V = pmap_valid_bit(pmap);
5570 PG_RW = pmap_rw_bit(pmap);
5572 va = trunc_page(va);
5573 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5574 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5575 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5577 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5578 va >= kmi.clean_eva,
5579 ("pmap_enter: managed mapping within the clean submap"));
5580 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5581 VM_OBJECT_ASSERT_LOCKED(m->object);
5582 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5583 ("pmap_enter: flags %u has reserved bits set", flags));
5584 pa = VM_PAGE_TO_PHYS(m);
5585 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5586 if ((flags & VM_PROT_WRITE) != 0)
5588 if ((prot & VM_PROT_WRITE) != 0)
5590 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5591 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5592 if ((prot & VM_PROT_EXECUTE) == 0)
5594 if ((flags & PMAP_ENTER_WIRED) != 0)
5596 if (va < VM_MAXUSER_ADDRESS)
5598 if (pmap == kernel_pmap)
5600 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5603 * Set modified bit gratuitously for writeable mappings if
5604 * the page is unmanaged. We do not want to take a fault
5605 * to do the dirty bit accounting for these mappings.
5607 if ((m->oflags & VPO_UNMANAGED) != 0) {
5608 if ((newpte & PG_RW) != 0)
5611 newpte |= PG_MANAGED;
5616 /* Assert the required virtual and physical alignment. */
5617 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5618 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5619 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5625 * In the case that a page table page is not
5626 * resident, we are creating it here.
5629 pde = pmap_pde(pmap, va);
5630 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5631 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5632 pte = pmap_pde_to_pte(pde, va);
5633 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5634 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5637 } else if (va < VM_MAXUSER_ADDRESS) {
5639 * Here if the pte page isn't mapped, or if it has been
5642 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5643 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5644 nosleep ? NULL : &lock);
5645 if (mpte == NULL && nosleep) {
5646 rv = KERN_RESOURCE_SHORTAGE;
5651 panic("pmap_enter: invalid page directory va=%#lx", va);
5655 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5656 newpte |= pmap_pkru_get(pmap, va);
5659 * Is the specified virtual address already mapped?
5661 if ((origpte & PG_V) != 0) {
5663 * Wiring change, just update stats. We don't worry about
5664 * wiring PT pages as they remain resident as long as there
5665 * are valid mappings in them. Hence, if a user page is wired,
5666 * the PT page will be also.
5668 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5669 pmap->pm_stats.wired_count++;
5670 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5671 pmap->pm_stats.wired_count--;
5674 * Remove the extra PT page reference.
5678 KASSERT(mpte->wire_count > 0,
5679 ("pmap_enter: missing reference to page table page,"
5684 * Has the physical page changed?
5686 opa = origpte & PG_FRAME;
5689 * No, might be a protection or wiring change.
5691 if ((origpte & PG_MANAGED) != 0 &&
5692 (newpte & PG_RW) != 0)
5693 vm_page_aflag_set(m, PGA_WRITEABLE);
5694 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5700 * The physical page has changed. Temporarily invalidate
5701 * the mapping. This ensures that all threads sharing the
5702 * pmap keep a consistent view of the mapping, which is
5703 * necessary for the correct handling of COW faults. It
5704 * also permits reuse of the old mapping's PV entry,
5705 * avoiding an allocation.
5707 * For consistency, handle unmanaged mappings the same way.
5709 origpte = pte_load_clear(pte);
5710 KASSERT((origpte & PG_FRAME) == opa,
5711 ("pmap_enter: unexpected pa update for %#lx", va));
5712 if ((origpte & PG_MANAGED) != 0) {
5713 om = PHYS_TO_VM_PAGE(opa);
5716 * The pmap lock is sufficient to synchronize with
5717 * concurrent calls to pmap_page_test_mappings() and
5718 * pmap_ts_referenced().
5720 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5722 if ((origpte & PG_A) != 0)
5723 vm_page_aflag_set(om, PGA_REFERENCED);
5724 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5725 pv = pmap_pvh_remove(&om->md, pmap, va);
5727 ("pmap_enter: no PV entry for %#lx", va));
5728 if ((newpte & PG_MANAGED) == 0)
5729 free_pv_entry(pmap, pv);
5730 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5731 TAILQ_EMPTY(&om->md.pv_list) &&
5732 ((om->flags & PG_FICTITIOUS) != 0 ||
5733 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5734 vm_page_aflag_clear(om, PGA_WRITEABLE);
5736 if ((origpte & PG_A) != 0)
5737 pmap_invalidate_page(pmap, va);
5741 * Increment the counters.
5743 if ((newpte & PG_W) != 0)
5744 pmap->pm_stats.wired_count++;
5745 pmap_resident_count_inc(pmap, 1);
5749 * Enter on the PV list if part of our managed memory.
5751 if ((newpte & PG_MANAGED) != 0) {
5753 pv = get_pv_entry(pmap, &lock);
5756 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5757 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5759 if ((newpte & PG_RW) != 0)
5760 vm_page_aflag_set(m, PGA_WRITEABLE);
5766 if ((origpte & PG_V) != 0) {
5768 origpte = pte_load_store(pte, newpte);
5769 KASSERT((origpte & PG_FRAME) == pa,
5770 ("pmap_enter: unexpected pa update for %#lx", va));
5771 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5773 if ((origpte & PG_MANAGED) != 0)
5777 * Although the PTE may still have PG_RW set, TLB
5778 * invalidation may nonetheless be required because
5779 * the PTE no longer has PG_M set.
5781 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5783 * This PTE change does not require TLB invalidation.
5787 if ((origpte & PG_A) != 0)
5788 pmap_invalidate_page(pmap, va);
5790 pte_store(pte, newpte);
5794 #if VM_NRESERVLEVEL > 0
5796 * If both the page table page and the reservation are fully
5797 * populated, then attempt promotion.
5799 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5800 pmap_ps_enabled(pmap) &&
5801 (m->flags & PG_FICTITIOUS) == 0 &&
5802 vm_reserv_level_iffullpop(m) == 0)
5803 pmap_promote_pde(pmap, pde, va, &lock);
5815 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5816 * if successful. Returns false if (1) a page table page cannot be allocated
5817 * without sleeping, (2) a mapping already exists at the specified virtual
5818 * address, or (3) a PV entry cannot be allocated without reclaiming another
5822 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5823 struct rwlock **lockp)
5828 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5829 PG_V = pmap_valid_bit(pmap);
5830 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5832 if ((m->oflags & VPO_UNMANAGED) == 0)
5833 newpde |= PG_MANAGED;
5834 if ((prot & VM_PROT_EXECUTE) == 0)
5836 if (va < VM_MAXUSER_ADDRESS)
5838 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5839 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5844 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5845 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5846 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5847 * a mapping already exists at the specified virtual address. Returns
5848 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5849 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5850 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5852 * The parameter "m" is only used when creating a managed, writeable mapping.
5855 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5856 vm_page_t m, struct rwlock **lockp)
5858 struct spglist free;
5859 pd_entry_t oldpde, *pde;
5860 pt_entry_t PG_G, PG_RW, PG_V;
5863 PG_G = pmap_global_bit(pmap);
5864 PG_RW = pmap_rw_bit(pmap);
5865 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5866 ("pmap_enter_pde: newpde is missing PG_M"));
5867 PG_V = pmap_valid_bit(pmap);
5868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5870 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5871 NULL : lockp)) == NULL) {
5872 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5873 " in pmap %p", va, pmap);
5874 return (KERN_RESOURCE_SHORTAGE);
5878 * If pkru is not same for the whole pde range, return failure
5879 * and let vm_fault() cope. Check after pde allocation, since
5882 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5884 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5885 pmap_invalidate_page(pmap, va);
5886 vm_page_free_pages_toq(&free, true);
5888 return (KERN_FAILURE);
5890 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5891 newpde &= ~X86_PG_PKU_MASK;
5892 newpde |= pmap_pkru_get(pmap, va);
5895 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5896 pde = &pde[pmap_pde_index(va)];
5898 if ((oldpde & PG_V) != 0) {
5899 KASSERT(pdpg->wire_count > 1,
5900 ("pmap_enter_pde: pdpg's wire count is too low"));
5901 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5903 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5904 " in pmap %p", va, pmap);
5905 return (KERN_FAILURE);
5907 /* Break the existing mapping(s). */
5909 if ((oldpde & PG_PS) != 0) {
5911 * The reference to the PD page that was acquired by
5912 * pmap_allocpde() ensures that it won't be freed.
5913 * However, if the PDE resulted from a promotion, then
5914 * a reserved PT page could be freed.
5916 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5917 if ((oldpde & PG_G) == 0)
5918 pmap_invalidate_pde_page(pmap, va, oldpde);
5920 pmap_delayed_invl_start();
5921 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5923 pmap_invalidate_all(pmap);
5924 pmap_delayed_invl_finish();
5926 vm_page_free_pages_toq(&free, true);
5927 if (va >= VM_MAXUSER_ADDRESS) {
5929 * Both pmap_remove_pde() and pmap_remove_ptes() will
5930 * leave the kernel page table page zero filled.
5932 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5933 if (pmap_insert_pt_page(pmap, mt, false))
5934 panic("pmap_enter_pde: trie insert failed");
5936 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5939 if ((newpde & PG_MANAGED) != 0) {
5941 * Abort this mapping if its PV entry could not be created.
5943 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5945 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5947 * Although "va" is not mapped, paging-
5948 * structure caches could nonetheless have
5949 * entries that refer to the freed page table
5950 * pages. Invalidate those entries.
5952 pmap_invalidate_page(pmap, va);
5953 vm_page_free_pages_toq(&free, true);
5955 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5956 " in pmap %p", va, pmap);
5957 return (KERN_RESOURCE_SHORTAGE);
5959 if ((newpde & PG_RW) != 0) {
5960 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5961 vm_page_aflag_set(mt, PGA_WRITEABLE);
5966 * Increment counters.
5968 if ((newpde & PG_W) != 0)
5969 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5970 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5973 * Map the superpage. (This is not a promoted mapping; there will not
5974 * be any lingering 4KB page mappings in the TLB.)
5976 pde_store(pde, newpde);
5978 atomic_add_long(&pmap_pde_mappings, 1);
5979 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5980 " in pmap %p", va, pmap);
5981 return (KERN_SUCCESS);
5985 * Maps a sequence of resident pages belonging to the same object.
5986 * The sequence begins with the given page m_start. This page is
5987 * mapped at the given virtual address start. Each subsequent page is
5988 * mapped at a virtual address that is offset from start by the same
5989 * amount as the page is offset from m_start within the object. The
5990 * last page in the sequence is the page with the largest offset from
5991 * m_start that can be mapped at a virtual address less than the given
5992 * virtual address end. Not every virtual page between start and end
5993 * is mapped; only those for which a resident page exists with the
5994 * corresponding offset from m_start are mapped.
5997 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5998 vm_page_t m_start, vm_prot_t prot)
6000 struct rwlock *lock;
6003 vm_pindex_t diff, psize;
6005 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6007 psize = atop(end - start);
6012 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6013 va = start + ptoa(diff);
6014 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6015 m->psind == 1 && pmap_ps_enabled(pmap) &&
6016 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6017 m = &m[NBPDR / PAGE_SIZE - 1];
6019 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6021 m = TAILQ_NEXT(m, listq);
6029 * this code makes some *MAJOR* assumptions:
6030 * 1. Current pmap & pmap exists.
6033 * 4. No page table pages.
6034 * but is *MUCH* faster than pmap_enter...
6038 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6040 struct rwlock *lock;
6044 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6051 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6052 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6054 struct spglist free;
6055 pt_entry_t newpte, *pte, PG_V;
6057 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6058 (m->oflags & VPO_UNMANAGED) != 0,
6059 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6060 PG_V = pmap_valid_bit(pmap);
6061 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6064 * In the case that a page table page is not
6065 * resident, we are creating it here.
6067 if (va < VM_MAXUSER_ADDRESS) {
6068 vm_pindex_t ptepindex;
6072 * Calculate pagetable page index
6074 ptepindex = pmap_pde_pindex(va);
6075 if (mpte && (mpte->pindex == ptepindex)) {
6079 * Get the page directory entry
6081 ptepa = pmap_pde(pmap, va);
6084 * If the page table page is mapped, we just increment
6085 * the hold count, and activate it. Otherwise, we
6086 * attempt to allocate a page table page. If this
6087 * attempt fails, we don't retry. Instead, we give up.
6089 if (ptepa && (*ptepa & PG_V) != 0) {
6092 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6096 * Pass NULL instead of the PV list lock
6097 * pointer, because we don't intend to sleep.
6099 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6104 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6105 pte = &pte[pmap_pte_index(va)];
6119 * Enter on the PV list if part of our managed memory.
6121 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6122 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6125 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6127 * Although "va" is not mapped, paging-
6128 * structure caches could nonetheless have
6129 * entries that refer to the freed page table
6130 * pages. Invalidate those entries.
6132 pmap_invalidate_page(pmap, va);
6133 vm_page_free_pages_toq(&free, true);
6141 * Increment counters
6143 pmap_resident_count_inc(pmap, 1);
6145 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6146 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6147 if ((m->oflags & VPO_UNMANAGED) == 0)
6148 newpte |= PG_MANAGED;
6149 if ((prot & VM_PROT_EXECUTE) == 0)
6151 if (va < VM_MAXUSER_ADDRESS)
6152 newpte |= PG_U | pmap_pkru_get(pmap, va);
6153 pte_store(pte, newpte);
6158 * Make a temporary mapping for a physical address. This is only intended
6159 * to be used for panic dumps.
6162 pmap_kenter_temporary(vm_paddr_t pa, int i)
6166 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6167 pmap_kenter(va, pa);
6169 return ((void *)crashdumpmap);
6173 * This code maps large physical mmap regions into the
6174 * processor address space. Note that some shortcuts
6175 * are taken, but the code works.
6178 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6179 vm_pindex_t pindex, vm_size_t size)
6182 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6183 vm_paddr_t pa, ptepa;
6187 PG_A = pmap_accessed_bit(pmap);
6188 PG_M = pmap_modified_bit(pmap);
6189 PG_V = pmap_valid_bit(pmap);
6190 PG_RW = pmap_rw_bit(pmap);
6192 VM_OBJECT_ASSERT_WLOCKED(object);
6193 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6194 ("pmap_object_init_pt: non-device object"));
6195 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6196 if (!pmap_ps_enabled(pmap))
6198 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6200 p = vm_page_lookup(object, pindex);
6201 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6202 ("pmap_object_init_pt: invalid page %p", p));
6203 pat_mode = p->md.pat_mode;
6206 * Abort the mapping if the first page is not physically
6207 * aligned to a 2MB page boundary.
6209 ptepa = VM_PAGE_TO_PHYS(p);
6210 if (ptepa & (NBPDR - 1))
6214 * Skip the first page. Abort the mapping if the rest of
6215 * the pages are not physically contiguous or have differing
6216 * memory attributes.
6218 p = TAILQ_NEXT(p, listq);
6219 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6221 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6222 ("pmap_object_init_pt: invalid page %p", p));
6223 if (pa != VM_PAGE_TO_PHYS(p) ||
6224 pat_mode != p->md.pat_mode)
6226 p = TAILQ_NEXT(p, listq);
6230 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6231 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6232 * will not affect the termination of this loop.
6235 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6236 pa < ptepa + size; pa += NBPDR) {
6237 pdpg = pmap_allocpde(pmap, addr, NULL);
6240 * The creation of mappings below is only an
6241 * optimization. If a page directory page
6242 * cannot be allocated without blocking,
6243 * continue on to the next mapping rather than
6249 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6250 pde = &pde[pmap_pde_index(addr)];
6251 if ((*pde & PG_V) == 0) {
6252 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6253 PG_U | PG_RW | PG_V);
6254 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6255 atomic_add_long(&pmap_pde_mappings, 1);
6257 /* Continue on if the PDE is already valid. */
6259 KASSERT(pdpg->wire_count > 0,
6260 ("pmap_object_init_pt: missing reference "
6261 "to page directory page, va: 0x%lx", addr));
6270 * Clear the wired attribute from the mappings for the specified range of
6271 * addresses in the given pmap. Every valid mapping within that range
6272 * must have the wired attribute set. In contrast, invalid mappings
6273 * cannot have the wired attribute set, so they are ignored.
6275 * The wired attribute of the page table entry is not a hardware
6276 * feature, so there is no need to invalidate any TLB entries.
6277 * Since pmap_demote_pde() for the wired entry must never fail,
6278 * pmap_delayed_invl_start()/finish() calls around the
6279 * function are not needed.
6282 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6284 vm_offset_t va_next;
6285 pml4_entry_t *pml4e;
6288 pt_entry_t *pte, PG_V;
6290 PG_V = pmap_valid_bit(pmap);
6292 for (; sva < eva; sva = va_next) {
6293 pml4e = pmap_pml4e(pmap, sva);
6294 if ((*pml4e & PG_V) == 0) {
6295 va_next = (sva + NBPML4) & ~PML4MASK;
6300 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6301 if ((*pdpe & PG_V) == 0) {
6302 va_next = (sva + NBPDP) & ~PDPMASK;
6307 va_next = (sva + NBPDR) & ~PDRMASK;
6310 pde = pmap_pdpe_to_pde(pdpe, sva);
6311 if ((*pde & PG_V) == 0)
6313 if ((*pde & PG_PS) != 0) {
6314 if ((*pde & PG_W) == 0)
6315 panic("pmap_unwire: pde %#jx is missing PG_W",
6319 * Are we unwiring the entire large page? If not,
6320 * demote the mapping and fall through.
6322 if (sva + NBPDR == va_next && eva >= va_next) {
6323 atomic_clear_long(pde, PG_W);
6324 pmap->pm_stats.wired_count -= NBPDR /
6327 } else if (!pmap_demote_pde(pmap, pde, sva))
6328 panic("pmap_unwire: demotion failed");
6332 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6334 if ((*pte & PG_V) == 0)
6336 if ((*pte & PG_W) == 0)
6337 panic("pmap_unwire: pte %#jx is missing PG_W",
6341 * PG_W must be cleared atomically. Although the pmap
6342 * lock synchronizes access to PG_W, another processor
6343 * could be setting PG_M and/or PG_A concurrently.
6345 atomic_clear_long(pte, PG_W);
6346 pmap->pm_stats.wired_count--;
6353 * Copy the range specified by src_addr/len
6354 * from the source map to the range dst_addr/len
6355 * in the destination map.
6357 * This routine is only advisory and need not do anything.
6361 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6362 vm_offset_t src_addr)
6364 struct rwlock *lock;
6365 struct spglist free;
6367 vm_offset_t end_addr = src_addr + len;
6368 vm_offset_t va_next;
6369 vm_page_t dst_pdpg, dstmpte, srcmpte;
6370 pt_entry_t PG_A, PG_M, PG_V;
6372 if (dst_addr != src_addr)
6375 if (dst_pmap->pm_type != src_pmap->pm_type)
6379 * EPT page table entries that require emulation of A/D bits are
6380 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6381 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6382 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6383 * implementations flag an EPT misconfiguration for exec-only
6384 * mappings we skip this function entirely for emulated pmaps.
6386 if (pmap_emulate_ad_bits(dst_pmap))
6390 if (dst_pmap < src_pmap) {
6391 PMAP_LOCK(dst_pmap);
6392 PMAP_LOCK(src_pmap);
6394 PMAP_LOCK(src_pmap);
6395 PMAP_LOCK(dst_pmap);
6398 PG_A = pmap_accessed_bit(dst_pmap);
6399 PG_M = pmap_modified_bit(dst_pmap);
6400 PG_V = pmap_valid_bit(dst_pmap);
6402 for (addr = src_addr; addr < end_addr; addr = va_next) {
6403 pt_entry_t *src_pte, *dst_pte;
6404 pml4_entry_t *pml4e;
6406 pd_entry_t srcptepaddr, *pde;
6408 KASSERT(addr < UPT_MIN_ADDRESS,
6409 ("pmap_copy: invalid to pmap_copy page tables"));
6411 pml4e = pmap_pml4e(src_pmap, addr);
6412 if ((*pml4e & PG_V) == 0) {
6413 va_next = (addr + NBPML4) & ~PML4MASK;
6419 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6420 if ((*pdpe & PG_V) == 0) {
6421 va_next = (addr + NBPDP) & ~PDPMASK;
6427 va_next = (addr + NBPDR) & ~PDRMASK;
6431 pde = pmap_pdpe_to_pde(pdpe, addr);
6433 if (srcptepaddr == 0)
6436 if (srcptepaddr & PG_PS) {
6437 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6439 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6440 if (dst_pdpg == NULL)
6442 pde = (pd_entry_t *)
6443 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6444 pde = &pde[pmap_pde_index(addr)];
6445 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6446 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6447 PMAP_ENTER_NORECLAIM, &lock))) {
6448 *pde = srcptepaddr & ~PG_W;
6449 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
6450 atomic_add_long(&pmap_pde_mappings, 1);
6452 dst_pdpg->wire_count--;
6456 srcptepaddr &= PG_FRAME;
6457 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6458 KASSERT(srcmpte->wire_count > 0,
6459 ("pmap_copy: source page table page is unused"));
6461 if (va_next > end_addr)
6464 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6465 src_pte = &src_pte[pmap_pte_index(addr)];
6467 while (addr < va_next) {
6471 * we only virtual copy managed pages
6473 if ((ptetemp & PG_MANAGED) != 0) {
6474 if (dstmpte != NULL &&
6475 dstmpte->pindex == pmap_pde_pindex(addr))
6476 dstmpte->wire_count++;
6477 else if ((dstmpte = pmap_allocpte(dst_pmap,
6478 addr, NULL)) == NULL)
6480 dst_pte = (pt_entry_t *)
6481 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6482 dst_pte = &dst_pte[pmap_pte_index(addr)];
6483 if (*dst_pte == 0 &&
6484 pmap_try_insert_pv_entry(dst_pmap, addr,
6485 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
6488 * Clear the wired, modified, and
6489 * accessed (referenced) bits
6492 *dst_pte = ptetemp & ~(PG_W | PG_M |
6494 pmap_resident_count_inc(dst_pmap, 1);
6497 if (pmap_unwire_ptp(dst_pmap, addr,
6500 * Although "addr" is not
6501 * mapped, paging-structure
6502 * caches could nonetheless
6503 * have entries that refer to
6504 * the freed page table pages.
6505 * Invalidate those entries.
6507 pmap_invalidate_page(dst_pmap,
6509 vm_page_free_pages_toq(&free,
6514 if (dstmpte->wire_count >= srcmpte->wire_count)
6524 PMAP_UNLOCK(src_pmap);
6525 PMAP_UNLOCK(dst_pmap);
6529 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6533 if (dst_pmap->pm_type != src_pmap->pm_type ||
6534 dst_pmap->pm_type != PT_X86 ||
6535 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6538 if (dst_pmap < src_pmap) {
6539 PMAP_LOCK(dst_pmap);
6540 PMAP_LOCK(src_pmap);
6542 PMAP_LOCK(src_pmap);
6543 PMAP_LOCK(dst_pmap);
6545 error = pmap_pkru_copy(dst_pmap, src_pmap);
6546 /* Clean up partial copy on failure due to no memory. */
6547 if (error == ENOMEM)
6548 pmap_pkru_deassign_all(dst_pmap);
6549 PMAP_UNLOCK(src_pmap);
6550 PMAP_UNLOCK(dst_pmap);
6551 if (error != ENOMEM)
6559 * Zero the specified hardware page.
6562 pmap_zero_page(vm_page_t m)
6564 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6566 pagezero((void *)va);
6570 * Zero an an area within a single hardware page. off and size must not
6571 * cover an area beyond a single hardware page.
6574 pmap_zero_page_area(vm_page_t m, int off, int size)
6576 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6578 if (off == 0 && size == PAGE_SIZE)
6579 pagezero((void *)va);
6581 bzero((char *)va + off, size);
6585 * Copy 1 specified hardware page to another.
6588 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6590 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6591 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6593 pagecopy((void *)src, (void *)dst);
6596 int unmapped_buf_allowed = 1;
6599 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6600 vm_offset_t b_offset, int xfersize)
6604 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6608 while (xfersize > 0) {
6609 a_pg_offset = a_offset & PAGE_MASK;
6610 pages[0] = ma[a_offset >> PAGE_SHIFT];
6611 b_pg_offset = b_offset & PAGE_MASK;
6612 pages[1] = mb[b_offset >> PAGE_SHIFT];
6613 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6614 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6615 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6616 a_cp = (char *)vaddr[0] + a_pg_offset;
6617 b_cp = (char *)vaddr[1] + b_pg_offset;
6618 bcopy(a_cp, b_cp, cnt);
6619 if (__predict_false(mapped))
6620 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6628 * Returns true if the pmap's pv is one of the first
6629 * 16 pvs linked to from this page. This count may
6630 * be changed upwards or downwards in the future; it
6631 * is only necessary that true be returned for a small
6632 * subset of pmaps for proper page aging.
6635 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6637 struct md_page *pvh;
6638 struct rwlock *lock;
6643 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6644 ("pmap_page_exists_quick: page %p is not managed", m));
6646 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6648 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6649 if (PV_PMAP(pv) == pmap) {
6657 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6658 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6659 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6660 if (PV_PMAP(pv) == pmap) {
6674 * pmap_page_wired_mappings:
6676 * Return the number of managed mappings to the given physical page
6680 pmap_page_wired_mappings(vm_page_t m)
6682 struct rwlock *lock;
6683 struct md_page *pvh;
6687 int count, md_gen, pvh_gen;
6689 if ((m->oflags & VPO_UNMANAGED) != 0)
6691 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6695 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6697 if (!PMAP_TRYLOCK(pmap)) {
6698 md_gen = m->md.pv_gen;
6702 if (md_gen != m->md.pv_gen) {
6707 pte = pmap_pte(pmap, pv->pv_va);
6708 if ((*pte & PG_W) != 0)
6712 if ((m->flags & PG_FICTITIOUS) == 0) {
6713 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6714 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6716 if (!PMAP_TRYLOCK(pmap)) {
6717 md_gen = m->md.pv_gen;
6718 pvh_gen = pvh->pv_gen;
6722 if (md_gen != m->md.pv_gen ||
6723 pvh_gen != pvh->pv_gen) {
6728 pte = pmap_pde(pmap, pv->pv_va);
6729 if ((*pte & PG_W) != 0)
6739 * Returns TRUE if the given page is mapped individually or as part of
6740 * a 2mpage. Otherwise, returns FALSE.
6743 pmap_page_is_mapped(vm_page_t m)
6745 struct rwlock *lock;
6748 if ((m->oflags & VPO_UNMANAGED) != 0)
6750 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6752 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6753 ((m->flags & PG_FICTITIOUS) == 0 &&
6754 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6760 * Destroy all managed, non-wired mappings in the given user-space
6761 * pmap. This pmap cannot be active on any processor besides the
6764 * This function cannot be applied to the kernel pmap. Moreover, it
6765 * is not intended for general use. It is only to be used during
6766 * process termination. Consequently, it can be implemented in ways
6767 * that make it faster than pmap_remove(). First, it can more quickly
6768 * destroy mappings by iterating over the pmap's collection of PV
6769 * entries, rather than searching the page table. Second, it doesn't
6770 * have to test and clear the page table entries atomically, because
6771 * no processor is currently accessing the user address space. In
6772 * particular, a page table entry's dirty bit won't change state once
6773 * this function starts.
6775 * Although this function destroys all of the pmap's managed,
6776 * non-wired mappings, it can delay and batch the invalidation of TLB
6777 * entries without calling pmap_delayed_invl_start() and
6778 * pmap_delayed_invl_finish(). Because the pmap is not active on
6779 * any other processor, none of these TLB entries will ever be used
6780 * before their eventual invalidation. Consequently, there is no need
6781 * for either pmap_remove_all() or pmap_remove_write() to wait for
6782 * that eventual TLB invalidation.
6785 pmap_remove_pages(pmap_t pmap)
6788 pt_entry_t *pte, tpte;
6789 pt_entry_t PG_M, PG_RW, PG_V;
6790 struct spglist free;
6791 vm_page_t m, mpte, mt;
6793 struct md_page *pvh;
6794 struct pv_chunk *pc, *npc;
6795 struct rwlock *lock;
6797 uint64_t inuse, bitmask;
6798 int allfree, field, freed, idx;
6799 boolean_t superpage;
6803 * Assert that the given pmap is only active on the current
6804 * CPU. Unfortunately, we cannot block another CPU from
6805 * activating the pmap while this function is executing.
6807 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6810 cpuset_t other_cpus;
6812 other_cpus = all_cpus;
6814 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6815 CPU_AND(&other_cpus, &pmap->pm_active);
6817 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6822 PG_M = pmap_modified_bit(pmap);
6823 PG_V = pmap_valid_bit(pmap);
6824 PG_RW = pmap_rw_bit(pmap);
6828 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6831 for (field = 0; field < _NPCM; field++) {
6832 inuse = ~pc->pc_map[field] & pc_freemask[field];
6833 while (inuse != 0) {
6835 bitmask = 1UL << bit;
6836 idx = field * 64 + bit;
6837 pv = &pc->pc_pventry[idx];
6840 pte = pmap_pdpe(pmap, pv->pv_va);
6842 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6844 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6847 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6849 pte = &pte[pmap_pte_index(pv->pv_va)];
6853 * Keep track whether 'tpte' is a
6854 * superpage explicitly instead of
6855 * relying on PG_PS being set.
6857 * This is because PG_PS is numerically
6858 * identical to PG_PTE_PAT and thus a
6859 * regular page could be mistaken for
6865 if ((tpte & PG_V) == 0) {
6866 panic("bad pte va %lx pte %lx",
6871 * We cannot remove wired pages from a process' mapping at this time
6879 pa = tpte & PG_PS_FRAME;
6881 pa = tpte & PG_FRAME;
6883 m = PHYS_TO_VM_PAGE(pa);
6884 KASSERT(m->phys_addr == pa,
6885 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6886 m, (uintmax_t)m->phys_addr,
6889 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6890 m < &vm_page_array[vm_page_array_size],
6891 ("pmap_remove_pages: bad tpte %#jx",
6897 * Update the vm_page_t clean/reference bits.
6899 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6901 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6907 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6910 pc->pc_map[field] |= bitmask;
6912 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6913 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6914 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6916 if (TAILQ_EMPTY(&pvh->pv_list)) {
6917 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6918 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6919 TAILQ_EMPTY(&mt->md.pv_list))
6920 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6922 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6924 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6925 ("pmap_remove_pages: pte page not promoted"));
6926 pmap_resident_count_dec(pmap, 1);
6927 KASSERT(mpte->wire_count == NPTEPG,
6928 ("pmap_remove_pages: pte page wire count error"));
6929 mpte->wire_count = 0;
6930 pmap_add_delayed_free_list(mpte, &free, FALSE);
6933 pmap_resident_count_dec(pmap, 1);
6934 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6936 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6937 TAILQ_EMPTY(&m->md.pv_list) &&
6938 (m->flags & PG_FICTITIOUS) == 0) {
6939 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6940 if (TAILQ_EMPTY(&pvh->pv_list))
6941 vm_page_aflag_clear(m, PGA_WRITEABLE);
6944 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6948 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6949 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6950 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6952 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6958 pmap_invalidate_all(pmap);
6959 pmap_pkru_deassign_all(pmap);
6961 vm_page_free_pages_toq(&free, true);
6965 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6967 struct rwlock *lock;
6969 struct md_page *pvh;
6970 pt_entry_t *pte, mask;
6971 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6973 int md_gen, pvh_gen;
6977 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6980 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6982 if (!PMAP_TRYLOCK(pmap)) {
6983 md_gen = m->md.pv_gen;
6987 if (md_gen != m->md.pv_gen) {
6992 pte = pmap_pte(pmap, pv->pv_va);
6995 PG_M = pmap_modified_bit(pmap);
6996 PG_RW = pmap_rw_bit(pmap);
6997 mask |= PG_RW | PG_M;
7000 PG_A = pmap_accessed_bit(pmap);
7001 PG_V = pmap_valid_bit(pmap);
7002 mask |= PG_V | PG_A;
7004 rv = (*pte & mask) == mask;
7009 if ((m->flags & PG_FICTITIOUS) == 0) {
7010 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7011 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7013 if (!PMAP_TRYLOCK(pmap)) {
7014 md_gen = m->md.pv_gen;
7015 pvh_gen = pvh->pv_gen;
7019 if (md_gen != m->md.pv_gen ||
7020 pvh_gen != pvh->pv_gen) {
7025 pte = pmap_pde(pmap, pv->pv_va);
7028 PG_M = pmap_modified_bit(pmap);
7029 PG_RW = pmap_rw_bit(pmap);
7030 mask |= PG_RW | PG_M;
7033 PG_A = pmap_accessed_bit(pmap);
7034 PG_V = pmap_valid_bit(pmap);
7035 mask |= PG_V | PG_A;
7037 rv = (*pte & mask) == mask;
7051 * Return whether or not the specified physical page was modified
7052 * in any physical maps.
7055 pmap_is_modified(vm_page_t m)
7058 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7059 ("pmap_is_modified: page %p is not managed", m));
7062 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7063 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
7064 * is clear, no PTEs can have PG_M set.
7066 VM_OBJECT_ASSERT_WLOCKED(m->object);
7067 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7069 return (pmap_page_test_mappings(m, FALSE, TRUE));
7073 * pmap_is_prefaultable:
7075 * Return whether or not the specified virtual address is eligible
7079 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7082 pt_entry_t *pte, PG_V;
7085 PG_V = pmap_valid_bit(pmap);
7088 pde = pmap_pde(pmap, addr);
7089 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7090 pte = pmap_pde_to_pte(pde, addr);
7091 rv = (*pte & PG_V) == 0;
7098 * pmap_is_referenced:
7100 * Return whether or not the specified physical page was referenced
7101 * in any physical maps.
7104 pmap_is_referenced(vm_page_t m)
7107 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7108 ("pmap_is_referenced: page %p is not managed", m));
7109 return (pmap_page_test_mappings(m, TRUE, FALSE));
7113 * Clear the write and modified bits in each of the given page's mappings.
7116 pmap_remove_write(vm_page_t m)
7118 struct md_page *pvh;
7120 struct rwlock *lock;
7121 pv_entry_t next_pv, pv;
7123 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7125 int pvh_gen, md_gen;
7127 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7128 ("pmap_remove_write: page %p is not managed", m));
7131 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7132 * set by another thread while the object is locked. Thus,
7133 * if PGA_WRITEABLE is clear, no page table entries need updating.
7135 VM_OBJECT_ASSERT_WLOCKED(m->object);
7136 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7138 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7139 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7140 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7143 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7145 if (!PMAP_TRYLOCK(pmap)) {
7146 pvh_gen = pvh->pv_gen;
7150 if (pvh_gen != pvh->pv_gen) {
7156 PG_RW = pmap_rw_bit(pmap);
7158 pde = pmap_pde(pmap, va);
7159 if ((*pde & PG_RW) != 0)
7160 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7161 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7162 ("inconsistent pv lock %p %p for page %p",
7163 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7166 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7168 if (!PMAP_TRYLOCK(pmap)) {
7169 pvh_gen = pvh->pv_gen;
7170 md_gen = m->md.pv_gen;
7174 if (pvh_gen != pvh->pv_gen ||
7175 md_gen != m->md.pv_gen) {
7181 PG_M = pmap_modified_bit(pmap);
7182 PG_RW = pmap_rw_bit(pmap);
7183 pde = pmap_pde(pmap, pv->pv_va);
7184 KASSERT((*pde & PG_PS) == 0,
7185 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7187 pte = pmap_pde_to_pte(pde, pv->pv_va);
7190 if (oldpte & PG_RW) {
7191 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7194 if ((oldpte & PG_M) != 0)
7196 pmap_invalidate_page(pmap, pv->pv_va);
7201 vm_page_aflag_clear(m, PGA_WRITEABLE);
7202 pmap_delayed_invl_wait(m);
7205 static __inline boolean_t
7206 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7209 if (!pmap_emulate_ad_bits(pmap))
7212 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7215 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7216 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7217 * if the EPT_PG_WRITE bit is set.
7219 if ((pte & EPT_PG_WRITE) != 0)
7223 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7225 if ((pte & EPT_PG_EXECUTE) == 0 ||
7226 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7233 * pmap_ts_referenced:
7235 * Return a count of reference bits for a page, clearing those bits.
7236 * It is not necessary for every reference bit to be cleared, but it
7237 * is necessary that 0 only be returned when there are truly no
7238 * reference bits set.
7240 * As an optimization, update the page's dirty field if a modified bit is
7241 * found while counting reference bits. This opportunistic update can be
7242 * performed at low cost and can eliminate the need for some future calls
7243 * to pmap_is_modified(). However, since this function stops after
7244 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7245 * dirty pages. Those dirty pages will only be detected by a future call
7246 * to pmap_is_modified().
7248 * A DI block is not needed within this function, because
7249 * invalidations are performed before the PV list lock is
7253 pmap_ts_referenced(vm_page_t m)
7255 struct md_page *pvh;
7258 struct rwlock *lock;
7259 pd_entry_t oldpde, *pde;
7260 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7263 int cleared, md_gen, not_cleared, pvh_gen;
7264 struct spglist free;
7267 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7268 ("pmap_ts_referenced: page %p is not managed", m));
7271 pa = VM_PAGE_TO_PHYS(m);
7272 lock = PHYS_TO_PV_LIST_LOCK(pa);
7273 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7277 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7278 goto small_mappings;
7284 if (!PMAP_TRYLOCK(pmap)) {
7285 pvh_gen = pvh->pv_gen;
7289 if (pvh_gen != pvh->pv_gen) {
7294 PG_A = pmap_accessed_bit(pmap);
7295 PG_M = pmap_modified_bit(pmap);
7296 PG_RW = pmap_rw_bit(pmap);
7298 pde = pmap_pde(pmap, pv->pv_va);
7300 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7302 * Although "oldpde" is mapping a 2MB page, because
7303 * this function is called at a 4KB page granularity,
7304 * we only update the 4KB page under test.
7308 if ((oldpde & PG_A) != 0) {
7310 * Since this reference bit is shared by 512 4KB
7311 * pages, it should not be cleared every time it is
7312 * tested. Apply a simple "hash" function on the
7313 * physical page number, the virtual superpage number,
7314 * and the pmap address to select one 4KB page out of
7315 * the 512 on which testing the reference bit will
7316 * result in clearing that reference bit. This
7317 * function is designed to avoid the selection of the
7318 * same 4KB page for every 2MB page mapping.
7320 * On demotion, a mapping that hasn't been referenced
7321 * is simply destroyed. To avoid the possibility of a
7322 * subsequent page fault on a demoted wired mapping,
7323 * always leave its reference bit set. Moreover,
7324 * since the superpage is wired, the current state of
7325 * its reference bit won't affect page replacement.
7327 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7328 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7329 (oldpde & PG_W) == 0) {
7330 if (safe_to_clear_referenced(pmap, oldpde)) {
7331 atomic_clear_long(pde, PG_A);
7332 pmap_invalidate_page(pmap, pv->pv_va);
7334 } else if (pmap_demote_pde_locked(pmap, pde,
7335 pv->pv_va, &lock)) {
7337 * Remove the mapping to a single page
7338 * so that a subsequent access may
7339 * repromote. Since the underlying
7340 * page table page is fully populated,
7341 * this removal never frees a page
7345 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7347 pte = pmap_pde_to_pte(pde, va);
7348 pmap_remove_pte(pmap, pte, va, *pde,
7350 pmap_invalidate_page(pmap, va);
7356 * The superpage mapping was removed
7357 * entirely and therefore 'pv' is no
7365 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7366 ("inconsistent pv lock %p %p for page %p",
7367 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7372 /* Rotate the PV list if it has more than one entry. */
7373 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7374 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7375 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7378 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7380 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7382 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7389 if (!PMAP_TRYLOCK(pmap)) {
7390 pvh_gen = pvh->pv_gen;
7391 md_gen = m->md.pv_gen;
7395 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7400 PG_A = pmap_accessed_bit(pmap);
7401 PG_M = pmap_modified_bit(pmap);
7402 PG_RW = pmap_rw_bit(pmap);
7403 pde = pmap_pde(pmap, pv->pv_va);
7404 KASSERT((*pde & PG_PS) == 0,
7405 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7407 pte = pmap_pde_to_pte(pde, pv->pv_va);
7408 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7410 if ((*pte & PG_A) != 0) {
7411 if (safe_to_clear_referenced(pmap, *pte)) {
7412 atomic_clear_long(pte, PG_A);
7413 pmap_invalidate_page(pmap, pv->pv_va);
7415 } else if ((*pte & PG_W) == 0) {
7417 * Wired pages cannot be paged out so
7418 * doing accessed bit emulation for
7419 * them is wasted effort. We do the
7420 * hard work for unwired pages only.
7422 pmap_remove_pte(pmap, pte, pv->pv_va,
7423 *pde, &free, &lock);
7424 pmap_invalidate_page(pmap, pv->pv_va);
7429 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7430 ("inconsistent pv lock %p %p for page %p",
7431 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7436 /* Rotate the PV list if it has more than one entry. */
7437 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7438 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7439 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7442 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7443 not_cleared < PMAP_TS_REFERENCED_MAX);
7446 vm_page_free_pages_toq(&free, true);
7447 return (cleared + not_cleared);
7451 * Apply the given advice to the specified range of addresses within the
7452 * given pmap. Depending on the advice, clear the referenced and/or
7453 * modified flags in each mapping and set the mapped page's dirty field.
7456 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7458 struct rwlock *lock;
7459 pml4_entry_t *pml4e;
7461 pd_entry_t oldpde, *pde;
7462 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7463 vm_offset_t va, va_next;
7465 boolean_t anychanged;
7467 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7471 * A/D bit emulation requires an alternate code path when clearing
7472 * the modified and accessed bits below. Since this function is
7473 * advisory in nature we skip it entirely for pmaps that require
7474 * A/D bit emulation.
7476 if (pmap_emulate_ad_bits(pmap))
7479 PG_A = pmap_accessed_bit(pmap);
7480 PG_G = pmap_global_bit(pmap);
7481 PG_M = pmap_modified_bit(pmap);
7482 PG_V = pmap_valid_bit(pmap);
7483 PG_RW = pmap_rw_bit(pmap);
7485 pmap_delayed_invl_start();
7487 for (; sva < eva; sva = va_next) {
7488 pml4e = pmap_pml4e(pmap, sva);
7489 if ((*pml4e & PG_V) == 0) {
7490 va_next = (sva + NBPML4) & ~PML4MASK;
7495 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7496 if ((*pdpe & PG_V) == 0) {
7497 va_next = (sva + NBPDP) & ~PDPMASK;
7502 va_next = (sva + NBPDR) & ~PDRMASK;
7505 pde = pmap_pdpe_to_pde(pdpe, sva);
7507 if ((oldpde & PG_V) == 0)
7509 else if ((oldpde & PG_PS) != 0) {
7510 if ((oldpde & PG_MANAGED) == 0)
7513 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7518 * The large page mapping was destroyed.
7524 * Unless the page mappings are wired, remove the
7525 * mapping to a single page so that a subsequent
7526 * access may repromote. Since the underlying page
7527 * table page is fully populated, this removal never
7528 * frees a page table page.
7530 if ((oldpde & PG_W) == 0) {
7531 pte = pmap_pde_to_pte(pde, sva);
7532 KASSERT((*pte & PG_V) != 0,
7533 ("pmap_advise: invalid PTE"));
7534 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
7544 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7546 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7548 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7549 if (advice == MADV_DONTNEED) {
7551 * Future calls to pmap_is_modified()
7552 * can be avoided by making the page
7555 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7558 atomic_clear_long(pte, PG_M | PG_A);
7559 } else if ((*pte & PG_A) != 0)
7560 atomic_clear_long(pte, PG_A);
7564 if ((*pte & PG_G) != 0) {
7571 if (va != va_next) {
7572 pmap_invalidate_range(pmap, va, sva);
7577 pmap_invalidate_range(pmap, va, sva);
7580 pmap_invalidate_all(pmap);
7582 pmap_delayed_invl_finish();
7586 * Clear the modify bits on the specified physical page.
7589 pmap_clear_modify(vm_page_t m)
7591 struct md_page *pvh;
7593 pv_entry_t next_pv, pv;
7594 pd_entry_t oldpde, *pde;
7595 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
7596 struct rwlock *lock;
7598 int md_gen, pvh_gen;
7600 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7601 ("pmap_clear_modify: page %p is not managed", m));
7602 VM_OBJECT_ASSERT_WLOCKED(m->object);
7603 KASSERT(!vm_page_xbusied(m),
7604 ("pmap_clear_modify: page %p is exclusive busied", m));
7607 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7608 * If the object containing the page is locked and the page is not
7609 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7611 if ((m->aflags & PGA_WRITEABLE) == 0)
7613 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7614 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7615 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7618 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7620 if (!PMAP_TRYLOCK(pmap)) {
7621 pvh_gen = pvh->pv_gen;
7625 if (pvh_gen != pvh->pv_gen) {
7630 PG_M = pmap_modified_bit(pmap);
7631 PG_V = pmap_valid_bit(pmap);
7632 PG_RW = pmap_rw_bit(pmap);
7634 pde = pmap_pde(pmap, va);
7636 if ((oldpde & PG_RW) != 0) {
7637 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
7638 if ((oldpde & PG_W) == 0) {
7640 * Write protect the mapping to a
7641 * single page so that a subsequent
7642 * write access may repromote.
7644 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7646 pte = pmap_pde_to_pte(pde, va);
7648 if ((oldpte & PG_V) != 0) {
7649 while (!atomic_cmpset_long(pte,
7651 oldpte & ~(PG_M | PG_RW)))
7654 pmap_invalidate_page(pmap, va);
7661 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7663 if (!PMAP_TRYLOCK(pmap)) {
7664 md_gen = m->md.pv_gen;
7665 pvh_gen = pvh->pv_gen;
7669 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7674 PG_M = pmap_modified_bit(pmap);
7675 PG_RW = pmap_rw_bit(pmap);
7676 pde = pmap_pde(pmap, pv->pv_va);
7677 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7678 " a 2mpage in page %p's pv list", m));
7679 pte = pmap_pde_to_pte(pde, pv->pv_va);
7680 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7681 atomic_clear_long(pte, PG_M);
7682 pmap_invalidate_page(pmap, pv->pv_va);
7690 * Miscellaneous support routines follow
7693 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7694 static __inline void
7695 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7700 * The cache mode bits are all in the low 32-bits of the
7701 * PTE, so we can just spin on updating the low 32-bits.
7704 opte = *(u_int *)pte;
7705 npte = opte & ~mask;
7707 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7710 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7711 static __inline void
7712 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7717 * The cache mode bits are all in the low 32-bits of the
7718 * PDE, so we can just spin on updating the low 32-bits.
7721 opde = *(u_int *)pde;
7722 npde = opde & ~mask;
7724 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7728 * Map a set of physical memory pages into the kernel virtual
7729 * address space. Return a pointer to where it is mapped. This
7730 * routine is intended to be used for mapping device memory,
7734 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
7736 struct pmap_preinit_mapping *ppim;
7737 vm_offset_t va, offset;
7741 offset = pa & PAGE_MASK;
7742 size = round_page(offset + size);
7743 pa = trunc_page(pa);
7745 if (!pmap_initialized) {
7747 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7748 ppim = pmap_preinit_mapping + i;
7749 if (ppim->va == 0) {
7753 ppim->va = virtual_avail;
7754 virtual_avail += size;
7760 panic("%s: too many preinit mappings", __func__);
7763 * If we have a preinit mapping, re-use it.
7765 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7766 ppim = pmap_preinit_mapping + i;
7767 if (ppim->pa == pa && ppim->sz == size &&
7768 (ppim->mode == mode ||
7769 (flags & MAPDEV_SETATTR) == 0))
7770 return ((void *)(ppim->va + offset));
7773 * If the specified range of physical addresses fits within
7774 * the direct map window, use the direct map.
7776 if (pa < dmaplimit && pa + size <= dmaplimit) {
7777 va = PHYS_TO_DMAP(pa);
7778 if ((flags & MAPDEV_SETATTR) != 0) {
7779 PMAP_LOCK(kernel_pmap);
7780 i = pmap_change_attr_locked(va, size, mode, flags);
7781 PMAP_UNLOCK(kernel_pmap);
7785 return ((void *)(va + offset));
7787 va = kva_alloc(size);
7789 panic("%s: Couldn't allocate KVA", __func__);
7791 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7792 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7793 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7794 if ((flags & MAPDEV_FLUSHCACHE) != 0)
7795 pmap_invalidate_cache_range(va, va + tmpsize);
7796 return ((void *)(va + offset));
7800 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7803 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
7808 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7811 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
7815 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7818 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
7823 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7826 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
7827 MAPDEV_FLUSHCACHE));
7831 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7833 struct pmap_preinit_mapping *ppim;
7837 /* If we gave a direct map region in pmap_mapdev, do nothing */
7838 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7840 offset = va & PAGE_MASK;
7841 size = round_page(offset + size);
7842 va = trunc_page(va);
7843 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7844 ppim = pmap_preinit_mapping + i;
7845 if (ppim->va == va && ppim->sz == size) {
7846 if (pmap_initialized)
7852 if (va + size == virtual_avail)
7857 if (pmap_initialized)
7862 * Tries to demote a 1GB page mapping.
7865 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7867 pdp_entry_t newpdpe, oldpdpe;
7868 pd_entry_t *firstpde, newpde, *pde;
7869 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7873 PG_A = pmap_accessed_bit(pmap);
7874 PG_M = pmap_modified_bit(pmap);
7875 PG_V = pmap_valid_bit(pmap);
7876 PG_RW = pmap_rw_bit(pmap);
7878 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7880 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7881 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7882 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7883 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7884 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7885 " in pmap %p", va, pmap);
7888 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7889 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7890 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7891 KASSERT((oldpdpe & PG_A) != 0,
7892 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7893 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7894 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7898 * Initialize the page directory page.
7900 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7906 * Demote the mapping.
7911 * Invalidate a stale recursive mapping of the page directory page.
7913 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7915 pmap_pdpe_demotions++;
7916 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7917 " in pmap %p", va, pmap);
7922 * Sets the memory attribute for the specified page.
7925 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7928 m->md.pat_mode = ma;
7931 * If "m" is a normal page, update its direct mapping. This update
7932 * can be relied upon to perform any cache operations that are
7933 * required for data coherence.
7935 if ((m->flags & PG_FICTITIOUS) == 0 &&
7936 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7938 panic("memory attribute change on the direct map failed");
7942 * Changes the specified virtual address range's memory type to that given by
7943 * the parameter "mode". The specified virtual address range must be
7944 * completely contained within either the direct map or the kernel map. If
7945 * the virtual address range is contained within the kernel map, then the
7946 * memory type for each of the corresponding ranges of the direct map is also
7947 * changed. (The corresponding ranges of the direct map are those ranges that
7948 * map the same physical pages as the specified virtual address range.) These
7949 * changes to the direct map are necessary because Intel describes the
7950 * behavior of their processors as "undefined" if two or more mappings to the
7951 * same physical page have different memory types.
7953 * Returns zero if the change completed successfully, and either EINVAL or
7954 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7955 * of the virtual address range was not mapped, and ENOMEM is returned if
7956 * there was insufficient memory available to complete the change. In the
7957 * latter case, the memory type may have been changed on some part of the
7958 * virtual address range or the direct map.
7961 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7965 PMAP_LOCK(kernel_pmap);
7966 error = pmap_change_attr_locked(va, size, mode, MAPDEV_FLUSHCACHE);
7967 PMAP_UNLOCK(kernel_pmap);
7972 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, int flags)
7974 vm_offset_t base, offset, tmpva;
7975 vm_paddr_t pa_start, pa_end, pa_end1;
7979 int cache_bits_pte, cache_bits_pde, error;
7982 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7983 base = trunc_page(va);
7984 offset = va & PAGE_MASK;
7985 size = round_page(offset + size);
7988 * Only supported on kernel virtual addresses, including the direct
7989 * map but excluding the recursive map.
7991 if (base < DMAP_MIN_ADDRESS)
7994 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7995 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7999 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8000 * into 4KB pages if required.
8002 for (tmpva = base; tmpva < base + size; ) {
8003 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8004 if (pdpe == NULL || *pdpe == 0)
8006 if (*pdpe & PG_PS) {
8008 * If the current 1GB page already has the required
8009 * memory type, then we need not demote this page. Just
8010 * increment tmpva to the next 1GB page frame.
8012 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
8013 tmpva = trunc_1gpage(tmpva) + NBPDP;
8018 * If the current offset aligns with a 1GB page frame
8019 * and there is at least 1GB left within the range, then
8020 * we need not break down this page into 2MB pages.
8022 if ((tmpva & PDPMASK) == 0 &&
8023 tmpva + PDPMASK < base + size) {
8027 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8030 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8035 * If the current 2MB page already has the required
8036 * memory type, then we need not demote this page. Just
8037 * increment tmpva to the next 2MB page frame.
8039 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
8040 tmpva = trunc_2mpage(tmpva) + NBPDR;
8045 * If the current offset aligns with a 2MB page frame
8046 * and there is at least 2MB left within the range, then
8047 * we need not break down this page into 4KB pages.
8049 if ((tmpva & PDRMASK) == 0 &&
8050 tmpva + PDRMASK < base + size) {
8054 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8057 pte = pmap_pde_to_pte(pde, tmpva);
8065 * Ok, all the pages exist, so run through them updating their
8066 * cache mode if required.
8068 pa_start = pa_end = 0;
8069 for (tmpva = base; tmpva < base + size; ) {
8070 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8071 if (*pdpe & PG_PS) {
8072 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
8073 pmap_pde_attr(pdpe, cache_bits_pde,
8077 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8078 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8079 if (pa_start == pa_end) {
8080 /* Start physical address run. */
8081 pa_start = *pdpe & PG_PS_FRAME;
8082 pa_end = pa_start + NBPDP;
8083 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8086 /* Run ended, update direct map. */
8087 error = pmap_change_attr_locked(
8088 PHYS_TO_DMAP(pa_start),
8089 pa_end - pa_start, mode, flags);
8092 /* Start physical address run. */
8093 pa_start = *pdpe & PG_PS_FRAME;
8094 pa_end = pa_start + NBPDP;
8097 tmpva = trunc_1gpage(tmpva) + NBPDP;
8100 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8102 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
8103 pmap_pde_attr(pde, cache_bits_pde,
8107 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8108 (*pde & PG_PS_FRAME) < dmaplimit) {
8109 if (pa_start == pa_end) {
8110 /* Start physical address run. */
8111 pa_start = *pde & PG_PS_FRAME;
8112 pa_end = pa_start + NBPDR;
8113 } else if (pa_end == (*pde & PG_PS_FRAME))
8116 /* Run ended, update direct map. */
8117 error = pmap_change_attr_locked(
8118 PHYS_TO_DMAP(pa_start),
8119 pa_end - pa_start, mode, flags);
8122 /* Start physical address run. */
8123 pa_start = *pde & PG_PS_FRAME;
8124 pa_end = pa_start + NBPDR;
8127 tmpva = trunc_2mpage(tmpva) + NBPDR;
8129 pte = pmap_pde_to_pte(pde, tmpva);
8130 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
8131 pmap_pte_attr(pte, cache_bits_pte,
8135 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8136 (*pte & PG_FRAME) < dmaplimit) {
8137 if (pa_start == pa_end) {
8138 /* Start physical address run. */
8139 pa_start = *pte & PG_FRAME;
8140 pa_end = pa_start + PAGE_SIZE;
8141 } else if (pa_end == (*pte & PG_FRAME))
8142 pa_end += PAGE_SIZE;
8144 /* Run ended, update direct map. */
8145 error = pmap_change_attr_locked(
8146 PHYS_TO_DMAP(pa_start),
8147 pa_end - pa_start, mode, flags);
8150 /* Start physical address run. */
8151 pa_start = *pte & PG_FRAME;
8152 pa_end = pa_start + PAGE_SIZE;
8158 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8159 pa_end1 = MIN(pa_end, dmaplimit);
8160 if (pa_start != pa_end1)
8161 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
8162 pa_end1 - pa_start, mode, flags);
8166 * Flush CPU caches if required to make sure any data isn't cached that
8167 * shouldn't be, etc.
8170 pmap_invalidate_range(kernel_pmap, base, tmpva);
8171 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8172 pmap_invalidate_cache_range(base, tmpva);
8178 * Demotes any mapping within the direct map region that covers more than the
8179 * specified range of physical addresses. This range's size must be a power
8180 * of two and its starting address must be a multiple of its size. Since the
8181 * demotion does not change any attributes of the mapping, a TLB invalidation
8182 * is not mandatory. The caller may, however, request a TLB invalidation.
8185 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8194 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8195 KASSERT((base & (len - 1)) == 0,
8196 ("pmap_demote_DMAP: base is not a multiple of len"));
8197 if (len < NBPDP && base < dmaplimit) {
8198 va = PHYS_TO_DMAP(base);
8200 PMAP_LOCK(kernel_pmap);
8201 pdpe = pmap_pdpe(kernel_pmap, va);
8202 if ((*pdpe & X86_PG_V) == 0)
8203 panic("pmap_demote_DMAP: invalid PDPE");
8204 if ((*pdpe & PG_PS) != 0) {
8205 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8206 panic("pmap_demote_DMAP: PDPE failed");
8210 pde = pmap_pdpe_to_pde(pdpe, va);
8211 if ((*pde & X86_PG_V) == 0)
8212 panic("pmap_demote_DMAP: invalid PDE");
8213 if ((*pde & PG_PS) != 0) {
8214 if (!pmap_demote_pde(kernel_pmap, pde, va))
8215 panic("pmap_demote_DMAP: PDE failed");
8219 if (changed && invalidate)
8220 pmap_invalidate_page(kernel_pmap, va);
8221 PMAP_UNLOCK(kernel_pmap);
8226 * perform the pmap work for mincore
8229 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8232 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8236 PG_A = pmap_accessed_bit(pmap);
8237 PG_M = pmap_modified_bit(pmap);
8238 PG_V = pmap_valid_bit(pmap);
8239 PG_RW = pmap_rw_bit(pmap);
8243 pdep = pmap_pde(pmap, addr);
8244 if (pdep != NULL && (*pdep & PG_V)) {
8245 if (*pdep & PG_PS) {
8247 /* Compute the physical address of the 4KB page. */
8248 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8250 val = MINCORE_SUPER;
8252 pte = *pmap_pde_to_pte(pdep, addr);
8253 pa = pte & PG_FRAME;
8261 if ((pte & PG_V) != 0) {
8262 val |= MINCORE_INCORE;
8263 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8264 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8265 if ((pte & PG_A) != 0)
8266 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8268 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8269 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8270 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8271 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8272 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8275 PA_UNLOCK_COND(*locked_pa);
8281 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8283 uint32_t gen, new_gen, pcid_next;
8285 CRITICAL_ASSERT(curthread);
8286 gen = PCPU_GET(pcid_gen);
8287 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8288 return (pti ? 0 : CR3_PCID_SAVE);
8289 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8290 return (CR3_PCID_SAVE);
8291 pcid_next = PCPU_GET(pcid_next);
8292 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8293 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8294 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8295 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8296 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8300 PCPU_SET(pcid_gen, new_gen);
8301 pcid_next = PMAP_PCID_KERN + 1;
8305 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8306 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8307 PCPU_SET(pcid_next, pcid_next + 1);
8312 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8316 cached = pmap_pcid_alloc(pmap, cpuid);
8317 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8318 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8319 pmap->pm_pcids[cpuid].pm_pcid));
8320 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8321 pmap == kernel_pmap,
8322 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8323 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8328 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8331 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8332 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
8336 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8338 struct invpcid_descr d;
8339 uint64_t cached, cr3, kcr3, ucr3;
8341 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8343 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8344 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8345 PCPU_SET(curpmap, pmap);
8346 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8347 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8350 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8352 * Explicitly invalidate translations cached from the
8353 * user page table. They are not automatically
8354 * flushed by reload of cr3 with the kernel page table
8357 * Note that the if() condition is resolved statically
8358 * by using the function argument instead of
8359 * runtime-evaluated invpcid_works value.
8361 if (invpcid_works1) {
8362 d.pcid = PMAP_PCID_USER_PT |
8363 pmap->pm_pcids[cpuid].pm_pcid;
8366 invpcid(&d, INVPCID_CTX);
8368 pmap_pti_pcid_invalidate(ucr3, kcr3);
8372 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8373 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8375 PCPU_INC(pm_save_cnt);
8379 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8382 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8383 pmap_activate_sw_pti_post(td, pmap);
8387 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8393 * If the INVPCID instruction is not available,
8394 * invltlb_pcid_handler() is used to handle an invalidate_all
8395 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8396 * sequence of operations has a window where %CR3 is loaded
8397 * with the new pmap's PML4 address, but the curpmap value has
8398 * not yet been updated. This causes the invltlb IPI handler,
8399 * which is called between the updates, to execute as a NOP,
8400 * which leaves stale TLB entries.
8402 * Note that the most typical use of pmap_activate_sw(), from
8403 * the context switch, is immune to this race, because
8404 * interrupts are disabled (while the thread lock is owned),
8405 * and the IPI happens after curpmap is updated. Protect
8406 * other callers in a similar way, by disabling interrupts
8407 * around the %cr3 register reload and curpmap assignment.
8409 rflags = intr_disable();
8410 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8411 intr_restore(rflags);
8412 pmap_activate_sw_pti_post(td, pmap);
8416 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8419 uint64_t cached, cr3;
8421 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8423 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8424 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8426 PCPU_SET(curpmap, pmap);
8428 PCPU_INC(pm_save_cnt);
8432 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8437 rflags = intr_disable();
8438 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8439 intr_restore(rflags);
8443 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8444 u_int cpuid __unused)
8447 load_cr3(pmap->pm_cr3);
8448 PCPU_SET(curpmap, pmap);
8452 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8453 u_int cpuid __unused)
8456 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8457 PCPU_SET(kcr3, pmap->pm_cr3);
8458 PCPU_SET(ucr3, pmap->pm_ucr3);
8459 pmap_activate_sw_pti_post(td, pmap);
8462 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8466 if (pmap_pcid_enabled && pti && invpcid_works)
8467 return (pmap_activate_sw_pcid_invpcid_pti);
8468 else if (pmap_pcid_enabled && pti && !invpcid_works)
8469 return (pmap_activate_sw_pcid_noinvpcid_pti);
8470 else if (pmap_pcid_enabled && !pti && invpcid_works)
8471 return (pmap_activate_sw_pcid_nopti);
8472 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8473 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8474 else if (!pmap_pcid_enabled && pti)
8475 return (pmap_activate_sw_nopcid_pti);
8476 else /* if (!pmap_pcid_enabled && !pti) */
8477 return (pmap_activate_sw_nopcid_nopti);
8481 pmap_activate_sw(struct thread *td)
8483 pmap_t oldpmap, pmap;
8486 oldpmap = PCPU_GET(curpmap);
8487 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8488 if (oldpmap == pmap)
8490 cpuid = PCPU_GET(cpuid);
8492 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8494 CPU_SET(cpuid, &pmap->pm_active);
8496 pmap_activate_sw_mode(td, pmap, cpuid);
8498 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8500 CPU_CLR(cpuid, &oldpmap->pm_active);
8505 pmap_activate(struct thread *td)
8509 pmap_activate_sw(td);
8514 pmap_activate_boot(pmap_t pmap)
8520 * kernel_pmap must be never deactivated, and we ensure that
8521 * by never activating it at all.
8523 MPASS(pmap != kernel_pmap);
8525 cpuid = PCPU_GET(cpuid);
8527 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8529 CPU_SET(cpuid, &pmap->pm_active);
8531 PCPU_SET(curpmap, pmap);
8533 kcr3 = pmap->pm_cr3;
8534 if (pmap_pcid_enabled)
8535 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8539 PCPU_SET(kcr3, kcr3);
8540 PCPU_SET(ucr3, PMAP_NO_CR3);
8544 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8549 * Increase the starting virtual address of the given mapping if a
8550 * different alignment might result in more superpage mappings.
8553 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8554 vm_offset_t *addr, vm_size_t size)
8556 vm_offset_t superpage_offset;
8560 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8561 offset += ptoa(object->pg_color);
8562 superpage_offset = offset & PDRMASK;
8563 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8564 (*addr & PDRMASK) == superpage_offset)
8566 if ((*addr & PDRMASK) < superpage_offset)
8567 *addr = (*addr & ~PDRMASK) + superpage_offset;
8569 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8573 static unsigned long num_dirty_emulations;
8574 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8575 &num_dirty_emulations, 0, NULL);
8577 static unsigned long num_accessed_emulations;
8578 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8579 &num_accessed_emulations, 0, NULL);
8581 static unsigned long num_superpage_accessed_emulations;
8582 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8583 &num_superpage_accessed_emulations, 0, NULL);
8585 static unsigned long ad_emulation_superpage_promotions;
8586 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8587 &ad_emulation_superpage_promotions, 0, NULL);
8588 #endif /* INVARIANTS */
8591 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8594 struct rwlock *lock;
8595 #if VM_NRESERVLEVEL > 0
8599 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8601 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8602 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8604 if (!pmap_emulate_ad_bits(pmap))
8607 PG_A = pmap_accessed_bit(pmap);
8608 PG_M = pmap_modified_bit(pmap);
8609 PG_V = pmap_valid_bit(pmap);
8610 PG_RW = pmap_rw_bit(pmap);
8616 pde = pmap_pde(pmap, va);
8617 if (pde == NULL || (*pde & PG_V) == 0)
8620 if ((*pde & PG_PS) != 0) {
8621 if (ftype == VM_PROT_READ) {
8623 atomic_add_long(&num_superpage_accessed_emulations, 1);
8631 pte = pmap_pde_to_pte(pde, va);
8632 if ((*pte & PG_V) == 0)
8635 if (ftype == VM_PROT_WRITE) {
8636 if ((*pte & PG_RW) == 0)
8639 * Set the modified and accessed bits simultaneously.
8641 * Intel EPT PTEs that do software emulation of A/D bits map
8642 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8643 * An EPT misconfiguration is triggered if the PTE is writable
8644 * but not readable (WR=10). This is avoided by setting PG_A
8645 * and PG_M simultaneously.
8647 *pte |= PG_M | PG_A;
8652 #if VM_NRESERVLEVEL > 0
8653 /* try to promote the mapping */
8654 if (va < VM_MAXUSER_ADDRESS)
8655 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8659 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8661 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8662 pmap_ps_enabled(pmap) &&
8663 (m->flags & PG_FICTITIOUS) == 0 &&
8664 vm_reserv_level_iffullpop(m) == 0) {
8665 pmap_promote_pde(pmap, pde, va, &lock);
8667 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8673 if (ftype == VM_PROT_WRITE)
8674 atomic_add_long(&num_dirty_emulations, 1);
8676 atomic_add_long(&num_accessed_emulations, 1);
8678 rv = 0; /* success */
8687 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8692 pt_entry_t *pte, PG_V;
8696 PG_V = pmap_valid_bit(pmap);
8699 pml4 = pmap_pml4e(pmap, va);
8701 if ((*pml4 & PG_V) == 0)
8704 pdp = pmap_pml4e_to_pdpe(pml4, va);
8706 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8709 pde = pmap_pdpe_to_pde(pdp, va);
8711 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8714 pte = pmap_pde_to_pte(pde, va);
8723 * Get the kernel virtual address of a set of physical pages. If there are
8724 * physical addresses not covered by the DMAP perform a transient mapping
8725 * that will be removed when calling pmap_unmap_io_transient.
8727 * \param page The pages the caller wishes to obtain the virtual
8728 * address on the kernel memory map.
8729 * \param vaddr On return contains the kernel virtual memory address
8730 * of the pages passed in the page parameter.
8731 * \param count Number of pages passed in.
8732 * \param can_fault TRUE if the thread using the mapped pages can take
8733 * page faults, FALSE otherwise.
8735 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8736 * finished or FALSE otherwise.
8740 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8741 boolean_t can_fault)
8744 boolean_t needs_mapping;
8746 int cache_bits, error __unused, i;
8749 * Allocate any KVA space that we need, this is done in a separate
8750 * loop to prevent calling vmem_alloc while pinned.
8752 needs_mapping = FALSE;
8753 for (i = 0; i < count; i++) {
8754 paddr = VM_PAGE_TO_PHYS(page[i]);
8755 if (__predict_false(paddr >= dmaplimit)) {
8756 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8757 M_BESTFIT | M_WAITOK, &vaddr[i]);
8758 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8759 needs_mapping = TRUE;
8761 vaddr[i] = PHYS_TO_DMAP(paddr);
8765 /* Exit early if everything is covered by the DMAP */
8770 * NB: The sequence of updating a page table followed by accesses
8771 * to the corresponding pages used in the !DMAP case is subject to
8772 * the situation described in the "AMD64 Architecture Programmer's
8773 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8774 * Coherency Considerations". Therefore, issuing the INVLPG right
8775 * after modifying the PTE bits is crucial.
8779 for (i = 0; i < count; i++) {
8780 paddr = VM_PAGE_TO_PHYS(page[i]);
8781 if (paddr >= dmaplimit) {
8784 * Slow path, since we can get page faults
8785 * while mappings are active don't pin the
8786 * thread to the CPU and instead add a global
8787 * mapping visible to all CPUs.
8789 pmap_qenter(vaddr[i], &page[i], 1);
8791 pte = vtopte(vaddr[i]);
8792 cache_bits = pmap_cache_bits(kernel_pmap,
8793 page[i]->md.pat_mode, 0);
8794 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8801 return (needs_mapping);
8805 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8806 boolean_t can_fault)
8813 for (i = 0; i < count; i++) {
8814 paddr = VM_PAGE_TO_PHYS(page[i]);
8815 if (paddr >= dmaplimit) {
8817 pmap_qremove(vaddr[i], 1);
8818 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8824 pmap_quick_enter_page(vm_page_t m)
8828 paddr = VM_PAGE_TO_PHYS(m);
8829 if (paddr < dmaplimit)
8830 return (PHYS_TO_DMAP(paddr));
8831 mtx_lock_spin(&qframe_mtx);
8832 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8833 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8834 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8839 pmap_quick_remove_page(vm_offset_t addr)
8844 pte_store(vtopte(qframe), 0);
8846 mtx_unlock_spin(&qframe_mtx);
8850 * Pdp pages from the large map are managed differently from either
8851 * kernel or user page table pages. They are permanently allocated at
8852 * initialization time, and their wire count is permanently set to
8853 * zero. The pml4 entries pointing to those pages are copied into
8854 * each allocated pmap.
8856 * In contrast, pd and pt pages are managed like user page table
8857 * pages. They are dynamically allocated, and their wire count
8858 * represents the number of valid entries within the page.
8861 pmap_large_map_getptp_unlocked(void)
8865 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8867 if (m != NULL && (m->flags & PG_ZERO) == 0)
8873 pmap_large_map_getptp(void)
8877 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8878 m = pmap_large_map_getptp_unlocked();
8880 PMAP_UNLOCK(kernel_pmap);
8882 PMAP_LOCK(kernel_pmap);
8883 /* Callers retry. */
8888 static pdp_entry_t *
8889 pmap_large_map_pdpe(vm_offset_t va)
8891 vm_pindex_t pml4_idx;
8894 pml4_idx = pmap_pml4e_index(va);
8895 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8896 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8898 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8899 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8900 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8901 "LMSPML4I %#jx lm_ents %d",
8902 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8903 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8904 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8908 pmap_large_map_pde(vm_offset_t va)
8915 pdpe = pmap_large_map_pdpe(va);
8917 m = pmap_large_map_getptp();
8920 mphys = VM_PAGE_TO_PHYS(m);
8921 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8923 MPASS((*pdpe & X86_PG_PS) == 0);
8924 mphys = *pdpe & PG_FRAME;
8926 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
8930 pmap_large_map_pte(vm_offset_t va)
8937 pde = pmap_large_map_pde(va);
8939 m = pmap_large_map_getptp();
8942 mphys = VM_PAGE_TO_PHYS(m);
8943 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8944 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
8946 MPASS((*pde & X86_PG_PS) == 0);
8947 mphys = *pde & PG_FRAME;
8949 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
8953 pmap_large_map_kextract(vm_offset_t va)
8955 pdp_entry_t *pdpe, pdp;
8956 pd_entry_t *pde, pd;
8957 pt_entry_t *pte, pt;
8959 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
8960 ("not largemap range %#lx", (u_long)va));
8961 pdpe = pmap_large_map_pdpe(va);
8963 KASSERT((pdp & X86_PG_V) != 0,
8964 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
8965 (u_long)pdpe, pdp));
8966 if ((pdp & X86_PG_PS) != 0) {
8967 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
8968 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
8969 (u_long)pdpe, pdp));
8970 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
8972 pde = pmap_pdpe_to_pde(pdpe, va);
8974 KASSERT((pd & X86_PG_V) != 0,
8975 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
8976 if ((pd & X86_PG_PS) != 0)
8977 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
8978 pte = pmap_pde_to_pte(pde, va);
8980 KASSERT((pt & X86_PG_V) != 0,
8981 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
8982 return ((pt & PG_FRAME) | (va & PAGE_MASK));
8986 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
8987 vmem_addr_t *vmem_res)
8991 * Large mappings are all but static. Consequently, there
8992 * is no point in waiting for an earlier allocation to be
8995 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
8996 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9000 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9006 vm_offset_t va, inc;
9007 vmem_addr_t vmem_res;
9011 if (len == 0 || spa + len < spa)
9014 /* See if DMAP can serve. */
9015 if (spa + len <= dmaplimit) {
9016 va = PHYS_TO_DMAP(spa);
9018 return (pmap_change_attr(va, len, mattr));
9022 * No, allocate KVA. Fit the address with best possible
9023 * alignment for superpages. Fall back to worse align if
9027 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9028 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9029 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9031 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9033 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9036 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9041 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9042 * in the pagetable to minimize flushing. No need to
9043 * invalidate TLB, since we only update invalid entries.
9045 PMAP_LOCK(kernel_pmap);
9046 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9048 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9049 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9050 pdpe = pmap_large_map_pdpe(va);
9052 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9053 X86_PG_V | X86_PG_A | pg_nx |
9054 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9056 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9057 (va & PDRMASK) == 0) {
9058 pde = pmap_large_map_pde(va);
9060 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9061 X86_PG_V | X86_PG_A | pg_nx |
9062 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9063 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9067 pte = pmap_large_map_pte(va);
9069 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9070 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9072 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9077 PMAP_UNLOCK(kernel_pmap);
9080 *addr = (void *)vmem_res;
9085 pmap_large_unmap(void *svaa, vm_size_t len)
9087 vm_offset_t sva, va;
9089 pdp_entry_t *pdpe, pdp;
9090 pd_entry_t *pde, pd;
9093 struct spglist spgf;
9095 sva = (vm_offset_t)svaa;
9096 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9097 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9101 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9102 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9103 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9104 PMAP_LOCK(kernel_pmap);
9105 for (va = sva; va < sva + len; va += inc) {
9106 pdpe = pmap_large_map_pdpe(va);
9108 KASSERT((pdp & X86_PG_V) != 0,
9109 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9110 (u_long)pdpe, pdp));
9111 if ((pdp & X86_PG_PS) != 0) {
9112 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9113 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9114 (u_long)pdpe, pdp));
9115 KASSERT((va & PDPMASK) == 0,
9116 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9117 (u_long)pdpe, pdp));
9118 KASSERT(va + NBPDP <= sva + len,
9119 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9120 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9121 (u_long)pdpe, pdp, len));
9126 pde = pmap_pdpe_to_pde(pdpe, va);
9128 KASSERT((pd & X86_PG_V) != 0,
9129 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9131 if ((pd & X86_PG_PS) != 0) {
9132 KASSERT((va & PDRMASK) == 0,
9133 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9135 KASSERT(va + NBPDR <= sva + len,
9136 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9137 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9141 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9143 if (m->wire_count == 0) {
9145 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9149 pte = pmap_pde_to_pte(pde, va);
9150 KASSERT((*pte & X86_PG_V) != 0,
9151 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9152 (u_long)pte, *pte));
9155 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9157 if (m->wire_count == 0) {
9159 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9160 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9162 if (m->wire_count == 0) {
9164 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9168 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9169 PMAP_UNLOCK(kernel_pmap);
9170 vm_page_free_pages_toq(&spgf, false);
9171 vmem_free(large_vmem, sva, len);
9175 pmap_large_map_wb_fence_mfence(void)
9182 pmap_large_map_wb_fence_sfence(void)
9189 pmap_large_map_wb_fence_nop(void)
9193 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void), static)
9196 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9197 return (pmap_large_map_wb_fence_mfence);
9198 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9199 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9200 return (pmap_large_map_wb_fence_sfence);
9202 /* clflush is strongly enough ordered */
9203 return (pmap_large_map_wb_fence_nop);
9207 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9210 for (; len > 0; len -= cpu_clflush_line_size,
9211 va += cpu_clflush_line_size)
9216 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9219 for (; len > 0; len -= cpu_clflush_line_size,
9220 va += cpu_clflush_line_size)
9225 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9228 for (; len > 0; len -= cpu_clflush_line_size,
9229 va += cpu_clflush_line_size)
9234 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9238 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t),
9242 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9243 return (pmap_large_map_flush_range_clwb);
9244 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9245 return (pmap_large_map_flush_range_clflushopt);
9246 else if ((cpu_feature & CPUID_CLFSH) != 0)
9247 return (pmap_large_map_flush_range_clflush);
9249 return (pmap_large_map_flush_range_nop);
9253 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9255 volatile u_long *pe;
9261 for (va = sva; va < eva; va += inc) {
9263 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9264 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9266 if ((p & X86_PG_PS) != 0)
9270 pe = (volatile u_long *)pmap_large_map_pde(va);
9272 if ((p & X86_PG_PS) != 0)
9276 pe = (volatile u_long *)pmap_large_map_pte(va);
9282 if ((p & X86_PG_AVAIL1) != 0) {
9284 * Spin-wait for the end of a parallel
9291 * If we saw other write-back
9292 * occuring, we cannot rely on PG_M to
9293 * indicate state of the cache. The
9294 * PG_M bit is cleared before the
9295 * flush to avoid ignoring new writes,
9296 * and writes which are relevant for
9297 * us might happen after.
9303 if ((p & X86_PG_M) != 0 || seen_other) {
9304 if (!atomic_fcmpset_long(pe, &p,
9305 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9307 * If we saw PG_M without
9308 * PG_AVAIL1, and then on the
9309 * next attempt we do not
9310 * observe either PG_M or
9311 * PG_AVAIL1, the other
9312 * write-back started after us
9313 * and finished before us. We
9314 * can rely on it doing our
9318 pmap_large_map_flush_range(va, inc);
9319 atomic_clear_long(pe, X86_PG_AVAIL1);
9328 * Write-back cache lines for the given address range.
9330 * Must be called only on the range or sub-range returned from
9331 * pmap_large_map(). Must not be called on the coalesced ranges.
9333 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9334 * instructions support.
9337 pmap_large_map_wb(void *svap, vm_size_t len)
9339 vm_offset_t eva, sva;
9341 sva = (vm_offset_t)svap;
9343 pmap_large_map_wb_fence();
9344 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9345 pmap_large_map_flush_range(sva, len);
9347 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9348 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9349 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9350 pmap_large_map_wb_large(sva, eva);
9352 pmap_large_map_wb_fence();
9356 pmap_pti_alloc_page(void)
9360 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9361 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9362 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9367 pmap_pti_free_page(vm_page_t m)
9370 KASSERT(m->wire_count > 0, ("page %p not wired", m));
9371 if (!vm_page_unwire_noq(m))
9373 vm_page_free_zero(m);
9387 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9388 VM_OBJECT_WLOCK(pti_obj);
9389 pml4_pg = pmap_pti_alloc_page();
9390 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9391 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9392 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9393 pdpe = pmap_pti_pdpe(va);
9394 pmap_pti_wire_pte(pdpe);
9396 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9397 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9398 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9399 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9400 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9401 sizeof(struct gate_descriptor) * NIDT, false);
9402 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9403 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9405 /* Doublefault stack IST 1 */
9406 va = common_tss[i].tss_ist1;
9407 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9408 /* NMI stack IST 2 */
9409 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9410 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9411 /* MC# stack IST 3 */
9412 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9413 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9414 /* DB# stack IST 4 */
9415 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9416 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9418 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9419 (vm_offset_t)etext, true);
9420 pti_finalized = true;
9421 VM_OBJECT_WUNLOCK(pti_obj);
9423 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9425 static pdp_entry_t *
9426 pmap_pti_pdpe(vm_offset_t va)
9428 pml4_entry_t *pml4e;
9431 vm_pindex_t pml4_idx;
9434 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9436 pml4_idx = pmap_pml4e_index(va);
9437 pml4e = &pti_pml4[pml4_idx];
9441 panic("pml4 alloc after finalization\n");
9442 m = pmap_pti_alloc_page();
9444 pmap_pti_free_page(m);
9445 mphys = *pml4e & ~PAGE_MASK;
9447 mphys = VM_PAGE_TO_PHYS(m);
9448 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9451 mphys = *pml4e & ~PAGE_MASK;
9453 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9458 pmap_pti_wire_pte(void *pte)
9462 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9463 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9468 pmap_pti_unwire_pde(void *pde, bool only_ref)
9472 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9473 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9474 MPASS(m->wire_count > 0);
9475 MPASS(only_ref || m->wire_count > 1);
9476 pmap_pti_free_page(m);
9480 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9485 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9486 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9487 MPASS(m->wire_count > 0);
9488 if (pmap_pti_free_page(m)) {
9489 pde = pmap_pti_pde(va);
9490 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9492 pmap_pti_unwire_pde(pde, false);
9497 pmap_pti_pde(vm_offset_t va)
9505 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9507 pdpe = pmap_pti_pdpe(va);
9509 m = pmap_pti_alloc_page();
9511 pmap_pti_free_page(m);
9512 MPASS((*pdpe & X86_PG_PS) == 0);
9513 mphys = *pdpe & ~PAGE_MASK;
9515 mphys = VM_PAGE_TO_PHYS(m);
9516 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9519 MPASS((*pdpe & X86_PG_PS) == 0);
9520 mphys = *pdpe & ~PAGE_MASK;
9523 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9524 pd_idx = pmap_pde_index(va);
9530 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9537 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9539 pde = pmap_pti_pde(va);
9540 if (unwire_pde != NULL) {
9542 pmap_pti_wire_pte(pde);
9545 m = pmap_pti_alloc_page();
9547 pmap_pti_free_page(m);
9548 MPASS((*pde & X86_PG_PS) == 0);
9549 mphys = *pde & ~(PAGE_MASK | pg_nx);
9551 mphys = VM_PAGE_TO_PHYS(m);
9552 *pde = mphys | X86_PG_RW | X86_PG_V;
9553 if (unwire_pde != NULL)
9554 *unwire_pde = false;
9557 MPASS((*pde & X86_PG_PS) == 0);
9558 mphys = *pde & ~(PAGE_MASK | pg_nx);
9561 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9562 pte += pmap_pte_index(va);
9568 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9572 pt_entry_t *pte, ptev;
9575 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9577 sva = trunc_page(sva);
9578 MPASS(sva > VM_MAXUSER_ADDRESS);
9579 eva = round_page(eva);
9581 for (; sva < eva; sva += PAGE_SIZE) {
9582 pte = pmap_pti_pte(sva, &unwire_pde);
9583 pa = pmap_kextract(sva);
9584 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9585 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9586 VM_MEMATTR_DEFAULT, FALSE);
9588 pte_store(pte, ptev);
9589 pmap_pti_wire_pte(pte);
9591 KASSERT(!pti_finalized,
9592 ("pti overlap after fin %#lx %#lx %#lx",
9594 KASSERT(*pte == ptev,
9595 ("pti non-identical pte after fin %#lx %#lx %#lx",
9599 pde = pmap_pti_pde(sva);
9600 pmap_pti_unwire_pde(pde, true);
9606 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9611 VM_OBJECT_WLOCK(pti_obj);
9612 pmap_pti_add_kva_locked(sva, eva, exec);
9613 VM_OBJECT_WUNLOCK(pti_obj);
9617 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9624 sva = rounddown2(sva, PAGE_SIZE);
9625 MPASS(sva > VM_MAXUSER_ADDRESS);
9626 eva = roundup2(eva, PAGE_SIZE);
9628 VM_OBJECT_WLOCK(pti_obj);
9629 for (va = sva; va < eva; va += PAGE_SIZE) {
9630 pte = pmap_pti_pte(va, NULL);
9631 KASSERT((*pte & X86_PG_V) != 0,
9632 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9633 (u_long)pte, *pte));
9635 pmap_pti_unwire_pte(pte, va);
9637 pmap_invalidate_range(kernel_pmap, sva, eva);
9638 VM_OBJECT_WUNLOCK(pti_obj);
9642 pkru_dup_range(void *ctx __unused, void *data)
9644 struct pmap_pkru_range *node, *new_node;
9646 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9647 if (new_node == NULL)
9650 memcpy(new_node, node, sizeof(*node));
9655 pkru_free_range(void *ctx __unused, void *node)
9658 uma_zfree(pmap_pkru_ranges_zone, node);
9662 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9665 struct pmap_pkru_range *ppr;
9668 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9669 MPASS(pmap->pm_type == PT_X86);
9670 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9671 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9672 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9674 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9677 ppr->pkru_keyidx = keyidx;
9678 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9679 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9681 uma_zfree(pmap_pkru_ranges_zone, ppr);
9686 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9689 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9690 MPASS(pmap->pm_type == PT_X86);
9691 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9692 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9696 pmap_pkru_deassign_all(pmap_t pmap)
9699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9700 if (pmap->pm_type == PT_X86 &&
9701 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9702 rangeset_remove_all(&pmap->pm_pkru);
9706 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9708 struct pmap_pkru_range *ppr, *prev_ppr;
9711 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9712 if (pmap->pm_type != PT_X86 ||
9713 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9714 sva >= VM_MAXUSER_ADDRESS)
9716 MPASS(eva <= VM_MAXUSER_ADDRESS);
9717 for (va = sva, prev_ppr = NULL; va < eva;) {
9718 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9719 if ((ppr == NULL) ^ (prev_ppr == NULL))
9725 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9727 va = ppr->pkru_rs_el.re_end;
9733 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9735 struct pmap_pkru_range *ppr;
9737 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9738 if (pmap->pm_type != PT_X86 ||
9739 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9740 va >= VM_MAXUSER_ADDRESS)
9742 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9744 return (X86_PG_PKU(ppr->pkru_keyidx));
9749 pred_pkru_on_remove(void *ctx __unused, void *r)
9751 struct pmap_pkru_range *ppr;
9754 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9758 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9761 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9762 if (pmap->pm_type == PT_X86 &&
9763 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9764 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9765 pred_pkru_on_remove);
9770 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9773 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9774 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9775 MPASS(dst_pmap->pm_type == PT_X86);
9776 MPASS(src_pmap->pm_type == PT_X86);
9777 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9778 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9780 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9784 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9787 pml4_entry_t *pml4e;
9789 pd_entry_t newpde, ptpaddr, *pde;
9790 pt_entry_t newpte, *ptep, pte;
9791 vm_offset_t va, va_next;
9794 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9795 MPASS(pmap->pm_type == PT_X86);
9796 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9798 for (changed = false, va = sva; va < eva; va = va_next) {
9799 pml4e = pmap_pml4e(pmap, va);
9800 if ((*pml4e & X86_PG_V) == 0) {
9801 va_next = (va + NBPML4) & ~PML4MASK;
9807 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9808 if ((*pdpe & X86_PG_V) == 0) {
9809 va_next = (va + NBPDP) & ~PDPMASK;
9815 va_next = (va + NBPDR) & ~PDRMASK;
9819 pde = pmap_pdpe_to_pde(pdpe, va);
9824 MPASS((ptpaddr & X86_PG_V) != 0);
9825 if ((ptpaddr & PG_PS) != 0) {
9826 if (va + NBPDR == va_next && eva >= va_next) {
9827 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9829 if (newpde != ptpaddr) {
9834 } else if (!pmap_demote_pde(pmap, pde, va)) {
9842 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9843 ptep++, va += PAGE_SIZE) {
9845 if ((pte & X86_PG_V) == 0)
9847 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9848 if (newpte != pte) {
9855 pmap_invalidate_range(pmap, sva, eva);
9859 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9860 u_int keyidx, int flags)
9863 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9864 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9866 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9868 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9874 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9879 sva = trunc_page(sva);
9880 eva = round_page(eva);
9881 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9886 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9888 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9890 if (error != ENOMEM)
9898 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9902 sva = trunc_page(sva);
9903 eva = round_page(eva);
9904 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9909 error = pmap_pkru_deassign(pmap, sva, eva);
9911 pmap_pkru_update_range(pmap, sva, eva, 0);
9913 if (error != ENOMEM)
9921 DB_SHOW_COMMAND(pte, pmap_print_pte)
9927 pt_entry_t *pte, PG_V;
9931 db_printf("show pte addr\n");
9934 va = (vm_offset_t)addr;
9936 if (kdb_thread != NULL)
9937 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
9939 pmap = PCPU_GET(curpmap);
9941 PG_V = pmap_valid_bit(pmap);
9942 pml4 = pmap_pml4e(pmap, va);
9943 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
9944 if ((*pml4 & PG_V) == 0) {
9948 pdp = pmap_pml4e_to_pdpe(pml4, va);
9949 db_printf(" pdpe %#016lx", *pdp);
9950 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
9954 pde = pmap_pdpe_to_pde(pdp, va);
9955 db_printf(" pde %#016lx", *pde);
9956 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
9960 pte = pmap_pde_to_pte(pde, va);
9961 db_printf(" pte %#016lx\n", *pte);
9964 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
9969 a = (vm_paddr_t)addr;
9970 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
9972 db_printf("show phys2dmap addr\n");