2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2018 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
126 #include <sys/turnstile.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/intr_machdep.h>
148 #include <x86/apicvar.h>
149 #include <machine/cpu.h>
150 #include <machine/cputypes.h>
151 #include <machine/md_var.h>
152 #include <machine/pcb.h>
153 #include <machine/specialreg.h>
155 #include <machine/smp.h>
157 #include <machine/tss.h>
159 static __inline boolean_t
160 pmap_type_guest(pmap_t pmap)
163 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
166 static __inline boolean_t
167 pmap_emulate_ad_bits(pmap_t pmap)
170 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
173 static __inline pt_entry_t
174 pmap_valid_bit(pmap_t pmap)
178 switch (pmap->pm_type) {
184 if (pmap_emulate_ad_bits(pmap))
185 mask = EPT_PG_EMUL_V;
190 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
196 static __inline pt_entry_t
197 pmap_rw_bit(pmap_t pmap)
201 switch (pmap->pm_type) {
207 if (pmap_emulate_ad_bits(pmap))
208 mask = EPT_PG_EMUL_RW;
213 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
219 static pt_entry_t pg_g;
221 static __inline pt_entry_t
222 pmap_global_bit(pmap_t pmap)
226 switch (pmap->pm_type) {
235 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
241 static __inline pt_entry_t
242 pmap_accessed_bit(pmap_t pmap)
246 switch (pmap->pm_type) {
252 if (pmap_emulate_ad_bits(pmap))
258 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
264 static __inline pt_entry_t
265 pmap_modified_bit(pmap_t pmap)
269 switch (pmap->pm_type) {
275 if (pmap_emulate_ad_bits(pmap))
281 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
287 #if !defined(DIAGNOSTIC)
288 #ifdef __GNUC_GNU_INLINE__
289 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
291 #define PMAP_INLINE extern inline
298 #define PV_STAT(x) do { x ; } while (0)
300 #define PV_STAT(x) do { } while (0)
303 #define pa_index(pa) ((pa) >> PDRSHIFT)
304 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
306 #define NPV_LIST_LOCKS MAXCPU
308 #define PHYS_TO_PV_LIST_LOCK(pa) \
309 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
311 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
312 struct rwlock **_lockp = (lockp); \
313 struct rwlock *_new_lock; \
315 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
316 if (_new_lock != *_lockp) { \
317 if (*_lockp != NULL) \
318 rw_wunlock(*_lockp); \
319 *_lockp = _new_lock; \
324 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
325 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
327 #define RELEASE_PV_LIST_LOCK(lockp) do { \
328 struct rwlock **_lockp = (lockp); \
330 if (*_lockp != NULL) { \
331 rw_wunlock(*_lockp); \
336 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
337 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
339 struct pmap kernel_pmap_store;
341 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
342 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
345 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
346 "Number of kernel page table pages allocated on bootup");
349 vm_paddr_t dmaplimit;
350 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
353 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
355 static int pat_works = 1;
356 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
357 "Is page attribute table fully functional?");
359 static int pg_ps_enabled = 1;
360 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
361 &pg_ps_enabled, 0, "Are large page mappings enabled?");
363 #define PAT_INDEX_SIZE 8
364 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
366 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
367 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
368 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
369 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
371 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
372 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
373 static int ndmpdpphys; /* number of DMPDPphys pages */
375 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
378 * pmap_mapdev support pre initialization (i.e. console)
380 #define PMAP_PREINIT_MAPPING_COUNT 8
381 static struct pmap_preinit_mapping {
386 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
387 static int pmap_initialized;
390 * Data for the pv entry allocation mechanism.
391 * Updates to pv_invl_gen are protected by the pv_list_locks[]
392 * elements, but reads are not.
394 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
395 static struct mtx __exclusive_cache_line pv_chunks_mutex;
396 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
397 static u_long pv_invl_gen[NPV_LIST_LOCKS];
398 static struct md_page *pv_table;
399 static struct md_page pv_dummy;
402 * All those kernel PT submaps that BSD is so fond of
404 pt_entry_t *CMAP1 = NULL;
406 static vm_offset_t qframe = 0;
407 static struct mtx qframe_mtx;
409 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
411 int pmap_pcid_enabled = 1;
412 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
413 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
414 int invpcid_works = 0;
415 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
416 "Is the invpcid instruction available ?");
418 int __read_frequently pti = 0;
419 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
421 "Page Table Isolation enabled");
422 static vm_object_t pti_obj;
423 static pml4_entry_t *pti_pml4;
424 static vm_pindex_t pti_pg_idx;
425 static bool pti_finalized;
428 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
435 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
437 return (sysctl_handle_64(oidp, &res, 0, req));
439 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
440 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
441 "Count of saved TLB context on switch");
443 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
444 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
445 static struct mtx invl_gen_mtx;
446 static u_long pmap_invl_gen = 0;
447 /* Fake lock object to satisfy turnstiles interface. */
448 static struct lock_object invl_gen_ts = {
456 return (curthread->td_md.md_invl_gen.gen == 0);
459 #define PMAP_ASSERT_NOT_IN_DI() \
460 KASSERT(pmap_not_in_di(), ("DI already started"))
463 * Start a new Delayed Invalidation (DI) block of code, executed by
464 * the current thread. Within a DI block, the current thread may
465 * destroy both the page table and PV list entries for a mapping and
466 * then release the corresponding PV list lock before ensuring that
467 * the mapping is flushed from the TLBs of any processors with the
471 pmap_delayed_invl_started(void)
473 struct pmap_invl_gen *invl_gen;
476 invl_gen = &curthread->td_md.md_invl_gen;
477 PMAP_ASSERT_NOT_IN_DI();
478 mtx_lock(&invl_gen_mtx);
479 if (LIST_EMPTY(&pmap_invl_gen_tracker))
480 currgen = pmap_invl_gen;
482 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
483 invl_gen->gen = currgen + 1;
484 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
485 mtx_unlock(&invl_gen_mtx);
489 * Finish the DI block, previously started by the current thread. All
490 * required TLB flushes for the pages marked by
491 * pmap_delayed_invl_page() must be finished before this function is
494 * This function works by bumping the global DI generation number to
495 * the generation number of the current thread's DI, unless there is a
496 * pending DI that started earlier. In the latter case, bumping the
497 * global DI generation number would incorrectly signal that the
498 * earlier DI had finished. Instead, this function bumps the earlier
499 * DI's generation number to match the generation number of the
500 * current thread's DI.
503 pmap_delayed_invl_finished(void)
505 struct pmap_invl_gen *invl_gen, *next;
506 struct turnstile *ts;
508 invl_gen = &curthread->td_md.md_invl_gen;
509 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
510 mtx_lock(&invl_gen_mtx);
511 next = LIST_NEXT(invl_gen, link);
513 turnstile_chain_lock(&invl_gen_ts);
514 ts = turnstile_lookup(&invl_gen_ts);
515 pmap_invl_gen = invl_gen->gen;
517 turnstile_broadcast(ts, TS_SHARED_QUEUE);
518 turnstile_unpend(ts);
520 turnstile_chain_unlock(&invl_gen_ts);
522 next->gen = invl_gen->gen;
524 LIST_REMOVE(invl_gen, link);
525 mtx_unlock(&invl_gen_mtx);
530 static long invl_wait;
531 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
532 "Number of times DI invalidation blocked pmap_remove_all/write");
536 pmap_delayed_invl_genp(vm_page_t m)
539 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
543 * Ensure that all currently executing DI blocks, that need to flush
544 * TLB for the given page m, actually flushed the TLB at the time the
545 * function returned. If the page m has an empty PV list and we call
546 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
547 * valid mapping for the page m in either its page table or TLB.
549 * This function works by blocking until the global DI generation
550 * number catches up with the generation number associated with the
551 * given page m and its PV list. Since this function's callers
552 * typically own an object lock and sometimes own a page lock, it
553 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
557 pmap_delayed_invl_wait(vm_page_t m)
559 struct turnstile *ts;
562 bool accounted = false;
565 m_gen = pmap_delayed_invl_genp(m);
566 while (*m_gen > pmap_invl_gen) {
569 atomic_add_long(&invl_wait, 1);
573 ts = turnstile_trywait(&invl_gen_ts);
574 if (*m_gen > pmap_invl_gen)
575 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
577 turnstile_cancel(ts);
582 * Mark the page m's PV list as participating in the current thread's
583 * DI block. Any threads concurrently using m's PV list to remove or
584 * restrict all mappings to m will wait for the current thread's DI
585 * block to complete before proceeding.
587 * The function works by setting the DI generation number for m's PV
588 * list to at least the DI generation number of the current thread.
589 * This forces a caller of pmap_delayed_invl_wait() to block until
590 * current thread calls pmap_delayed_invl_finished().
593 pmap_delayed_invl_page(vm_page_t m)
597 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
598 gen = curthread->td_md.md_invl_gen.gen;
601 m_gen = pmap_delayed_invl_genp(m);
609 static caddr_t crashdumpmap;
612 * Internal flags for pmap_enter()'s helper functions.
614 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
615 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
617 static void free_pv_chunk(struct pv_chunk *pc);
618 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
619 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
620 static int popcnt_pc_map_pq(uint64_t *map);
621 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
622 static void reserve_pv_entries(pmap_t pmap, int needed,
623 struct rwlock **lockp);
624 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
625 struct rwlock **lockp);
626 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
627 u_int flags, struct rwlock **lockp);
628 #if VM_NRESERVLEVEL > 0
629 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
630 struct rwlock **lockp);
632 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
633 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
636 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
637 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
638 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
639 vm_offset_t va, struct rwlock **lockp);
640 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
642 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
643 vm_prot_t prot, struct rwlock **lockp);
644 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
645 u_int flags, vm_page_t m, struct rwlock **lockp);
646 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
647 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
648 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
649 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
650 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
652 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
653 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
654 #if VM_NRESERVLEVEL > 0
655 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
656 struct rwlock **lockp);
658 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
660 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
661 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
663 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
664 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
665 static void pmap_pti_wire_pte(void *pte);
666 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
667 struct spglist *free, struct rwlock **lockp);
668 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
669 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
670 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
671 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
672 struct spglist *free);
673 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
674 pd_entry_t *pde, struct spglist *free,
675 struct rwlock **lockp);
676 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
677 vm_page_t m, struct rwlock **lockp);
678 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
680 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
682 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
683 struct rwlock **lockp);
684 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
685 struct rwlock **lockp);
686 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
687 struct rwlock **lockp);
689 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
690 struct spglist *free);
691 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
693 /********************/
694 /* Inline functions */
695 /********************/
697 /* Return a non-clipped PD index for a given VA */
698 static __inline vm_pindex_t
699 pmap_pde_pindex(vm_offset_t va)
701 return (va >> PDRSHIFT);
705 /* Return a pointer to the PML4 slot that corresponds to a VA */
706 static __inline pml4_entry_t *
707 pmap_pml4e(pmap_t pmap, vm_offset_t va)
710 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
713 /* Return a pointer to the PDP slot that corresponds to a VA */
714 static __inline pdp_entry_t *
715 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
719 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
720 return (&pdpe[pmap_pdpe_index(va)]);
723 /* Return a pointer to the PDP slot that corresponds to a VA */
724 static __inline pdp_entry_t *
725 pmap_pdpe(pmap_t pmap, vm_offset_t va)
730 PG_V = pmap_valid_bit(pmap);
731 pml4e = pmap_pml4e(pmap, va);
732 if ((*pml4e & PG_V) == 0)
734 return (pmap_pml4e_to_pdpe(pml4e, va));
737 /* Return a pointer to the PD slot that corresponds to a VA */
738 static __inline pd_entry_t *
739 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
743 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
744 return (&pde[pmap_pde_index(va)]);
747 /* Return a pointer to the PD slot that corresponds to a VA */
748 static __inline pd_entry_t *
749 pmap_pde(pmap_t pmap, vm_offset_t va)
754 PG_V = pmap_valid_bit(pmap);
755 pdpe = pmap_pdpe(pmap, va);
756 if (pdpe == NULL || (*pdpe & PG_V) == 0)
758 return (pmap_pdpe_to_pde(pdpe, va));
761 /* Return a pointer to the PT slot that corresponds to a VA */
762 static __inline pt_entry_t *
763 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
767 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
768 return (&pte[pmap_pte_index(va)]);
771 /* Return a pointer to the PT slot that corresponds to a VA */
772 static __inline pt_entry_t *
773 pmap_pte(pmap_t pmap, vm_offset_t va)
778 PG_V = pmap_valid_bit(pmap);
779 pde = pmap_pde(pmap, va);
780 if (pde == NULL || (*pde & PG_V) == 0)
782 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
783 return ((pt_entry_t *)pde);
784 return (pmap_pde_to_pte(pde, va));
788 pmap_resident_count_inc(pmap_t pmap, int count)
791 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
792 pmap->pm_stats.resident_count += count;
796 pmap_resident_count_dec(pmap_t pmap, int count)
799 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
800 KASSERT(pmap->pm_stats.resident_count >= count,
801 ("pmap %p resident count underflow %ld %d", pmap,
802 pmap->pm_stats.resident_count, count));
803 pmap->pm_stats.resident_count -= count;
806 PMAP_INLINE pt_entry_t *
807 vtopte(vm_offset_t va)
809 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
811 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
813 return (PTmap + ((va >> PAGE_SHIFT) & mask));
816 static __inline pd_entry_t *
817 vtopde(vm_offset_t va)
819 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
821 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
823 return (PDmap + ((va >> PDRSHIFT) & mask));
827 allocpages(vm_paddr_t *firstaddr, int n)
832 bzero((void *)ret, n * PAGE_SIZE);
833 *firstaddr += n * PAGE_SIZE;
837 CTASSERT(powerof2(NDMPML4E));
839 /* number of kernel PDP slots */
840 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
843 nkpt_init(vm_paddr_t addr)
850 pt_pages = howmany(addr, 1 << PDRSHIFT);
851 pt_pages += NKPDPE(pt_pages);
854 * Add some slop beyond the bare minimum required for bootstrapping
857 * This is quite important when allocating KVA for kernel modules.
858 * The modules are required to be linked in the negative 2GB of
859 * the address space. If we run out of KVA in this region then
860 * pmap_growkernel() will need to allocate page table pages to map
861 * the entire 512GB of KVA space which is an unnecessary tax on
864 * Secondly, device memory mapped as part of setting up the low-
865 * level console(s) is taken from KVA, starting at virtual_avail.
866 * This is because cninit() is called after pmap_bootstrap() but
867 * before vm_init() and pmap_init(). 20MB for a frame buffer is
870 pt_pages += 32; /* 64MB additional slop. */
876 * Returns the proper write/execute permission for a physical page that is
877 * part of the initial boot allocations.
879 * If the page has kernel text, it is marked as read-only. If the page has
880 * kernel read-only data, it is marked as read-only/not-executable. If the
881 * page has only read-write data, it is marked as read-write/not-executable.
882 * If the page is below/above the kernel range, it is marked as read-write.
884 * This function operates on 2M pages, since we map the kernel space that
887 * Note that this doesn't currently provide any protection for modules.
889 static inline pt_entry_t
890 bootaddr_rwx(vm_paddr_t pa)
894 * Everything in the same 2M page as the start of the kernel
895 * should be static. On the other hand, things in the same 2M
896 * page as the end of the kernel could be read-write/executable,
897 * as the kernel image is not guaranteed to end on a 2M boundary.
899 if (pa < trunc_2mpage(btext - KERNBASE) ||
900 pa >= trunc_2mpage(_end - KERNBASE))
903 * The linker should ensure that the read-only and read-write
904 * portions don't share the same 2M page, so this shouldn't
905 * impact read-only data. However, in any case, any page with
906 * read-write data needs to be read-write.
908 if (pa >= trunc_2mpage(brwsection - KERNBASE))
909 return (X86_PG_RW | pg_nx);
911 * Mark any 2M page containing kernel text as read-only. Mark
912 * other pages with read-only data as read-only and not executable.
913 * (It is likely a small portion of the read-only data section will
914 * be marked as read-only, but executable. This should be acceptable
915 * since the read-only protection will keep the data from changing.)
916 * Note that fixups to the .text section will still work until we
919 if (pa < round_2mpage(etext - KERNBASE))
925 create_pagetables(vm_paddr_t *firstaddr)
927 int i, j, ndm1g, nkpdpe, nkdmpde;
932 uint64_t DMPDkernphys;
934 /* Allocate page table pages for the direct map */
935 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
936 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
938 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
939 if (ndmpdpphys > NDMPML4E) {
941 * Each NDMPML4E allows 512 GB, so limit to that,
942 * and then readjust ndmpdp and ndmpdpphys.
944 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
945 Maxmem = atop(NDMPML4E * NBPML4);
946 ndmpdpphys = NDMPML4E;
947 ndmpdp = NDMPML4E * NPDEPG;
949 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
951 if ((amd_feature & AMDID_PAGE1GB) != 0) {
953 * Calculate the number of 1G pages that will fully fit in
956 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
959 * Allocate 2M pages for the kernel. These will be used in
960 * place of the first one or more 1G pages from ndm1g.
962 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
963 DMPDkernphys = allocpages(firstaddr, nkdmpde);
966 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
967 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
970 KPML4phys = allocpages(firstaddr, 1);
971 KPDPphys = allocpages(firstaddr, NKPML4E);
974 * Allocate the initial number of kernel page table pages required to
975 * bootstrap. We defer this until after all memory-size dependent
976 * allocations are done (e.g. direct map), so that we don't have to
977 * build in too much slop in our estimate.
979 * Note that when NKPML4E > 1, we have an empty page underneath
980 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
981 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
983 nkpt_init(*firstaddr);
984 nkpdpe = NKPDPE(nkpt);
986 KPTphys = allocpages(firstaddr, nkpt);
987 KPDphys = allocpages(firstaddr, nkpdpe);
989 /* Fill in the underlying page table pages */
990 /* XXX not fully used, underneath 2M pages */
991 pt_p = (pt_entry_t *)KPTphys;
992 for (i = 0; ptoa(i) < *firstaddr; i++)
993 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
995 /* Now map the page tables at their location within PTmap */
996 pd_p = (pd_entry_t *)KPDphys;
997 for (i = 0; i < nkpt; i++)
998 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1000 /* Map from zero to end of allocations under 2M pages */
1001 /* This replaces some of the KPTphys entries above */
1002 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1003 /* Preset PG_M and PG_A because demotion expects it. */
1004 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1005 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1008 * Because we map the physical blocks in 2M pages, adjust firstaddr
1009 * to record the physical blocks we've actually mapped into kernel
1010 * virtual address space.
1012 *firstaddr = round_2mpage(*firstaddr);
1014 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1015 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1016 for (i = 0; i < nkpdpe; i++)
1017 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1020 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1021 * the end of physical memory is not aligned to a 1GB page boundary,
1022 * then the residual physical memory is mapped with 2MB pages. Later,
1023 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1024 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1025 * that are partially used.
1027 pd_p = (pd_entry_t *)DMPDphys;
1028 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1029 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1030 /* Preset PG_M and PG_A because demotion expects it. */
1031 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1032 X86_PG_M | X86_PG_A | pg_nx;
1034 pdp_p = (pdp_entry_t *)DMPDPphys;
1035 for (i = 0; i < ndm1g; i++) {
1036 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1037 /* Preset PG_M and PG_A because demotion expects it. */
1038 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1039 X86_PG_M | X86_PG_A | pg_nx;
1041 for (j = 0; i < ndmpdp; i++, j++) {
1042 pdp_p[i] = DMPDphys + ptoa(j);
1043 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1047 * Instead of using a 1G page for the memory containing the kernel,
1048 * use 2M pages with appropriate permissions. (If using 1G pages,
1049 * this will partially overwrite the PDPEs above.)
1052 pd_p = (pd_entry_t *)DMPDkernphys;
1053 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1054 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1055 X86_PG_M | X86_PG_A | pg_nx |
1056 bootaddr_rwx(i << PDRSHIFT);
1057 for (i = 0; i < nkdmpde; i++)
1058 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1062 /* And recursively map PML4 to itself in order to get PTmap */
1063 p4_p = (pml4_entry_t *)KPML4phys;
1064 p4_p[PML4PML4I] = KPML4phys;
1065 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1067 /* Connect the Direct Map slot(s) up to the PML4. */
1068 for (i = 0; i < ndmpdpphys; i++) {
1069 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1070 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1073 /* Connect the KVA slots up to the PML4 */
1074 for (i = 0; i < NKPML4E; i++) {
1075 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1076 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1081 * Bootstrap the system enough to run with virtual memory.
1083 * On amd64 this is called after mapping has already been enabled
1084 * and just syncs the pmap module with what has already been done.
1085 * [We can't call it easily with mapping off since the kernel is not
1086 * mapped with PA == VA, hence we would have to relocate every address
1087 * from the linked base (virtual) address "KERNBASE" to the actual
1088 * (physical) address starting relative to 0]
1091 pmap_bootstrap(vm_paddr_t *firstaddr)
1098 KERNend = *firstaddr;
1104 * Create an initial set of page tables to run the kernel in.
1106 create_pagetables(firstaddr);
1109 * Add a physical memory segment (vm_phys_seg) corresponding to the
1110 * preallocated kernel page table pages so that vm_page structures
1111 * representing these pages will be created. The vm_page structures
1112 * are required for promotion of the corresponding kernel virtual
1113 * addresses to superpage mappings.
1115 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1117 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1119 virtual_end = VM_MAX_KERNEL_ADDRESS;
1123 * Enable PG_G global pages, then switch to the kernel page
1124 * table from the bootstrap page table. After the switch, it
1125 * is possible to enable SMEP and SMAP since PG_U bits are
1131 load_cr3(KPML4phys);
1132 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1134 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1139 * Initialize the kernel pmap (which is statically allocated).
1141 PMAP_LOCK_INIT(kernel_pmap);
1142 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1143 kernel_pmap->pm_cr3 = KPML4phys;
1144 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1145 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1146 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1147 kernel_pmap->pm_flags = pmap_flags;
1150 * Initialize the TLB invalidations generation number lock.
1152 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1155 * Reserve some special page table entries/VA space for temporary
1158 #define SYSMAP(c, p, v, n) \
1159 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1165 * Crashdump maps. The first page is reused as CMAP1 for the
1168 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1169 CADDR1 = crashdumpmap;
1174 * Initialize the PAT MSR.
1175 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1176 * side-effect, invalidates stale PG_G TLB entries that might
1177 * have been created in our pre-boot environment.
1181 /* Initialize TLB Context Id. */
1182 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
1183 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
1184 /* Check for INVPCID support */
1185 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
1187 for (i = 0; i < MAXCPU; i++) {
1188 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1189 kernel_pmap->pm_pcids[i].pm_gen = 1;
1193 * PMAP_PCID_KERN + 1 is used for initialization of
1194 * proc0 pmap. The pmap' pcid state might be used by
1195 * EFIRT entry before first context switch, so it
1196 * needs to be valid.
1198 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1199 PCPU_SET(pcid_gen, 1);
1202 * pcpu area for APs is zeroed during AP startup.
1203 * pc_pcid_next and pc_pcid_gen are initialized by AP
1204 * during pcpu setup.
1206 load_cr4(rcr4() | CR4_PCIDE);
1208 pmap_pcid_enabled = 0;
1213 * Setup the PAT MSR.
1218 int pat_table[PAT_INDEX_SIZE];
1223 /* Bail if this CPU doesn't implement PAT. */
1224 if ((cpu_feature & CPUID_PAT) == 0)
1227 /* Set default PAT index table. */
1228 for (i = 0; i < PAT_INDEX_SIZE; i++)
1230 pat_table[PAT_WRITE_BACK] = 0;
1231 pat_table[PAT_WRITE_THROUGH] = 1;
1232 pat_table[PAT_UNCACHEABLE] = 3;
1233 pat_table[PAT_WRITE_COMBINING] = 3;
1234 pat_table[PAT_WRITE_PROTECTED] = 3;
1235 pat_table[PAT_UNCACHED] = 3;
1237 /* Initialize default PAT entries. */
1238 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1239 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1240 PAT_VALUE(2, PAT_UNCACHED) |
1241 PAT_VALUE(3, PAT_UNCACHEABLE) |
1242 PAT_VALUE(4, PAT_WRITE_BACK) |
1243 PAT_VALUE(5, PAT_WRITE_THROUGH) |
1244 PAT_VALUE(6, PAT_UNCACHED) |
1245 PAT_VALUE(7, PAT_UNCACHEABLE);
1249 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1250 * Program 5 and 6 as WP and WC.
1251 * Leave 4 and 7 as WB and UC.
1253 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
1254 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1255 PAT_VALUE(6, PAT_WRITE_COMBINING);
1256 pat_table[PAT_UNCACHED] = 2;
1257 pat_table[PAT_WRITE_PROTECTED] = 5;
1258 pat_table[PAT_WRITE_COMBINING] = 6;
1261 * Just replace PAT Index 2 with WC instead of UC-.
1263 pat_msr &= ~PAT_MASK(2);
1264 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
1265 pat_table[PAT_WRITE_COMBINING] = 2;
1270 load_cr4(cr4 & ~CR4_PGE);
1272 /* Disable caches (CD = 1, NW = 0). */
1274 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1276 /* Flushes caches and TLBs. */
1280 /* Update PAT and index table. */
1281 wrmsr(MSR_PAT, pat_msr);
1282 for (i = 0; i < PAT_INDEX_SIZE; i++)
1283 pat_index[i] = pat_table[i];
1285 /* Flush caches and TLBs again. */
1289 /* Restore caches and PGE. */
1295 * Initialize a vm_page's machine-dependent fields.
1298 pmap_page_init(vm_page_t m)
1301 TAILQ_INIT(&m->md.pv_list);
1302 m->md.pat_mode = PAT_WRITE_BACK;
1306 * Initialize the pmap module.
1307 * Called by vm_init, to initialize any structures that the pmap
1308 * system needs to map virtual memory.
1313 struct pmap_preinit_mapping *ppim;
1316 int error, i, pv_npg, ret, skz63;
1318 /* L1TF, reserve page @0 unconditionally */
1319 vm_page_blacklist_add(0, bootverbose);
1321 /* Detect bare-metal Skylake Server and Skylake-X. */
1322 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1323 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1325 * Skylake-X errata SKZ63. Processor May Hang When
1326 * Executing Code In an HLE Transaction Region between
1327 * 40000000H and 403FFFFFH.
1329 * Mark the pages in the range as preallocated. It
1330 * seems to be impossible to distinguish between
1331 * Skylake Server and Skylake X.
1334 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1337 printf("SKZ63: skipping 4M RAM starting "
1338 "at physical 1G\n");
1339 for (i = 0; i < atop(0x400000); i++) {
1340 ret = vm_page_blacklist_add(0x40000000 +
1342 if (!ret && bootverbose)
1343 printf("page at %#lx already used\n",
1344 0x40000000 + ptoa(i));
1350 * Initialize the vm page array entries for the kernel pmap's
1353 PMAP_LOCK(kernel_pmap);
1354 for (i = 0; i < nkpt; i++) {
1355 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1356 KASSERT(mpte >= vm_page_array &&
1357 mpte < &vm_page_array[vm_page_array_size],
1358 ("pmap_init: page table page is out of range"));
1359 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1360 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1361 mpte->wire_count = 1;
1362 if (i << PDRSHIFT < KERNend &&
1363 pmap_insert_pt_page(kernel_pmap, mpte))
1364 panic("pmap_init: pmap_insert_pt_page failed");
1366 PMAP_UNLOCK(kernel_pmap);
1370 * If the kernel is running on a virtual machine, then it must assume
1371 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1372 * be prepared for the hypervisor changing the vendor and family that
1373 * are reported by CPUID. Consequently, the workaround for AMD Family
1374 * 10h Erratum 383 is enabled if the processor's feature set does not
1375 * include at least one feature that is only supported by older Intel
1376 * or newer AMD processors.
1378 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1379 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1380 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1382 workaround_erratum383 = 1;
1385 * Are large page mappings enabled?
1387 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1388 if (pg_ps_enabled) {
1389 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1390 ("pmap_init: can't assign to pagesizes[1]"));
1391 pagesizes[1] = NBPDR;
1395 * Initialize the pv chunk list mutex.
1397 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1400 * Initialize the pool of pv list locks.
1402 for (i = 0; i < NPV_LIST_LOCKS; i++)
1403 rw_init(&pv_list_locks[i], "pmap pv list");
1406 * Calculate the size of the pv head table for superpages.
1408 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1411 * Allocate memory for the pv head table for superpages.
1413 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1415 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1416 for (i = 0; i < pv_npg; i++)
1417 TAILQ_INIT(&pv_table[i].pv_list);
1418 TAILQ_INIT(&pv_dummy.pv_list);
1420 pmap_initialized = 1;
1421 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1422 ppim = pmap_preinit_mapping + i;
1425 /* Make the direct map consistent */
1426 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1427 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1428 ppim->sz, ppim->mode);
1432 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1433 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1436 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1437 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1438 (vmem_addr_t *)&qframe);
1440 panic("qframe allocation failed");
1443 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1444 "2MB page mapping counters");
1446 static u_long pmap_pde_demotions;
1447 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1448 &pmap_pde_demotions, 0, "2MB page demotions");
1450 static u_long pmap_pde_mappings;
1451 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1452 &pmap_pde_mappings, 0, "2MB page mappings");
1454 static u_long pmap_pde_p_failures;
1455 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1456 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1458 static u_long pmap_pde_promotions;
1459 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1460 &pmap_pde_promotions, 0, "2MB page promotions");
1462 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1463 "1GB page mapping counters");
1465 static u_long pmap_pdpe_demotions;
1466 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1467 &pmap_pdpe_demotions, 0, "1GB page demotions");
1469 /***************************************************
1470 * Low level helper routines.....
1471 ***************************************************/
1474 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1476 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1478 switch (pmap->pm_type) {
1481 /* Verify that both PAT bits are not set at the same time */
1482 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1483 ("Invalid PAT bits in entry %#lx", entry));
1485 /* Swap the PAT bits if one of them is set */
1486 if ((entry & x86_pat_bits) != 0)
1487 entry ^= x86_pat_bits;
1491 * Nothing to do - the memory attributes are represented
1492 * the same way for regular pages and superpages.
1496 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1503 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1506 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1507 pat_index[(int)mode] >= 0);
1511 * Determine the appropriate bits to set in a PTE or PDE for a specified
1515 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1517 int cache_bits, pat_flag, pat_idx;
1519 if (!pmap_is_valid_memattr(pmap, mode))
1520 panic("Unknown caching mode %d\n", mode);
1522 switch (pmap->pm_type) {
1525 /* The PAT bit is different for PTE's and PDE's. */
1526 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1528 /* Map the caching mode to a PAT index. */
1529 pat_idx = pat_index[mode];
1531 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1534 cache_bits |= pat_flag;
1536 cache_bits |= PG_NC_PCD;
1538 cache_bits |= PG_NC_PWT;
1542 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1546 panic("unsupported pmap type %d", pmap->pm_type);
1549 return (cache_bits);
1553 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1557 switch (pmap->pm_type) {
1560 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1563 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1566 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1573 pmap_ps_enabled(pmap_t pmap)
1576 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1580 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1583 switch (pmap->pm_type) {
1590 * This is a little bogus since the generation number is
1591 * supposed to be bumped up when a region of the address
1592 * space is invalidated in the page tables.
1594 * In this case the old PDE entry is valid but yet we want
1595 * to make sure that any mappings using the old entry are
1596 * invalidated in the TLB.
1598 * The reason this works as expected is because we rendezvous
1599 * "all" host cpus and force any vcpu context to exit as a
1602 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1605 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1607 pde_store(pde, newpde);
1611 * After changing the page size for the specified virtual address in the page
1612 * table, flush the corresponding entries from the processor's TLB. Only the
1613 * calling processor's TLB is affected.
1615 * The calling thread must be pinned to a processor.
1618 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1622 if (pmap_type_guest(pmap))
1625 KASSERT(pmap->pm_type == PT_X86,
1626 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1628 PG_G = pmap_global_bit(pmap);
1630 if ((newpde & PG_PS) == 0)
1631 /* Demotion: flush a specific 2MB page mapping. */
1633 else if ((newpde & PG_G) == 0)
1635 * Promotion: flush every 4KB page mapping from the TLB
1636 * because there are too many to flush individually.
1641 * Promotion: flush every 4KB page mapping from the TLB,
1642 * including any global (PG_G) mappings.
1650 * For SMP, these functions have to use the IPI mechanism for coherence.
1652 * N.B.: Before calling any of the following TLB invalidation functions,
1653 * the calling processor must ensure that all stores updating a non-
1654 * kernel page table are globally performed. Otherwise, another
1655 * processor could cache an old, pre-update entry without being
1656 * invalidated. This can happen one of two ways: (1) The pmap becomes
1657 * active on another processor after its pm_active field is checked by
1658 * one of the following functions but before a store updating the page
1659 * table is globally performed. (2) The pmap becomes active on another
1660 * processor before its pm_active field is checked but due to
1661 * speculative loads one of the following functions stills reads the
1662 * pmap as inactive on the other processor.
1664 * The kernel page table is exempt because its pm_active field is
1665 * immutable. The kernel page table is always active on every
1670 * Interrupt the cpus that are executing in the guest context.
1671 * This will force the vcpu to exit and the cached EPT mappings
1672 * will be invalidated by the host before the next vmresume.
1674 static __inline void
1675 pmap_invalidate_ept(pmap_t pmap)
1680 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1681 ("pmap_invalidate_ept: absurd pm_active"));
1684 * The TLB mappings associated with a vcpu context are not
1685 * flushed each time a different vcpu is chosen to execute.
1687 * This is in contrast with a process's vtop mappings that
1688 * are flushed from the TLB on each context switch.
1690 * Therefore we need to do more than just a TLB shootdown on
1691 * the active cpus in 'pmap->pm_active'. To do this we keep
1692 * track of the number of invalidations performed on this pmap.
1694 * Each vcpu keeps a cache of this counter and compares it
1695 * just before a vmresume. If the counter is out-of-date an
1696 * invept will be done to flush stale mappings from the TLB.
1698 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1701 * Force the vcpu to exit and trap back into the hypervisor.
1703 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1704 ipi_selected(pmap->pm_active, ipinum);
1709 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1712 struct invpcid_descr d;
1713 uint64_t kcr3, ucr3;
1717 if (pmap_type_guest(pmap)) {
1718 pmap_invalidate_ept(pmap);
1722 KASSERT(pmap->pm_type == PT_X86,
1723 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1726 if (pmap == kernel_pmap) {
1730 cpuid = PCPU_GET(cpuid);
1731 if (pmap == PCPU_GET(curpmap)) {
1733 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1735 * Disable context switching. pm_pcid
1736 * is recalculated on switch, which
1737 * might make us use wrong pcid below.
1740 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1742 if (invpcid_works) {
1743 d.pcid = pcid | PMAP_PCID_USER_PT;
1746 invpcid(&d, INVPCID_ADDR);
1748 kcr3 = pmap->pm_cr3 | pcid |
1750 ucr3 = pmap->pm_ucr3 | pcid |
1751 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1752 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1756 } else if (pmap_pcid_enabled)
1757 pmap->pm_pcids[cpuid].pm_gen = 0;
1758 if (pmap_pcid_enabled) {
1761 pmap->pm_pcids[i].pm_gen = 0;
1765 * The fence is between stores to pm_gen and the read of
1766 * the pm_active mask. We need to ensure that it is
1767 * impossible for us to miss the bit update in pm_active
1768 * and simultaneously observe a non-zero pm_gen in
1769 * pmap_activate_sw(), otherwise TLB update is missed.
1770 * Without the fence, IA32 allows such an outcome.
1771 * Note that pm_active is updated by a locked operation,
1772 * which provides the reciprocal fence.
1774 atomic_thread_fence_seq_cst();
1776 mask = &pmap->pm_active;
1778 smp_masked_invlpg(*mask, va, pmap);
1782 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1783 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1786 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1789 struct invpcid_descr d;
1791 uint64_t kcr3, ucr3;
1795 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1796 pmap_invalidate_all(pmap);
1800 if (pmap_type_guest(pmap)) {
1801 pmap_invalidate_ept(pmap);
1805 KASSERT(pmap->pm_type == PT_X86,
1806 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1809 cpuid = PCPU_GET(cpuid);
1810 if (pmap == kernel_pmap) {
1811 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1815 if (pmap == PCPU_GET(curpmap)) {
1816 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1818 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1820 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1821 if (invpcid_works) {
1822 d.pcid = pcid | PMAP_PCID_USER_PT;
1825 for (; d.addr < eva; d.addr +=
1827 invpcid(&d, INVPCID_ADDR);
1829 kcr3 = pmap->pm_cr3 | pcid |
1831 ucr3 = pmap->pm_ucr3 | pcid |
1832 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1833 pmap_pti_pcid_invlrng(ucr3, kcr3, sva,
1838 } else if (pmap_pcid_enabled) {
1839 pmap->pm_pcids[cpuid].pm_gen = 0;
1841 if (pmap_pcid_enabled) {
1844 pmap->pm_pcids[i].pm_gen = 0;
1846 /* See the comment in pmap_invalidate_page(). */
1847 atomic_thread_fence_seq_cst();
1849 mask = &pmap->pm_active;
1851 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1856 pmap_invalidate_all(pmap_t pmap)
1859 struct invpcid_descr d;
1860 uint64_t kcr3, ucr3;
1864 if (pmap_type_guest(pmap)) {
1865 pmap_invalidate_ept(pmap);
1869 KASSERT(pmap->pm_type == PT_X86,
1870 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1873 if (pmap == kernel_pmap) {
1874 if (pmap_pcid_enabled && invpcid_works) {
1875 bzero(&d, sizeof(d));
1876 invpcid(&d, INVPCID_CTXGLOB);
1882 cpuid = PCPU_GET(cpuid);
1883 if (pmap == PCPU_GET(curpmap)) {
1884 if (pmap_pcid_enabled) {
1886 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1887 if (invpcid_works) {
1891 invpcid(&d, INVPCID_CTX);
1892 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1893 d.pcid |= PMAP_PCID_USER_PT;
1894 invpcid(&d, INVPCID_CTX);
1897 kcr3 = pmap->pm_cr3 | pcid;
1898 ucr3 = pmap->pm_ucr3;
1899 if (ucr3 != PMAP_NO_CR3) {
1900 ucr3 |= pcid | PMAP_PCID_USER_PT;
1901 pmap_pti_pcid_invalidate(ucr3,
1911 } else if (pmap_pcid_enabled) {
1912 pmap->pm_pcids[cpuid].pm_gen = 0;
1914 if (pmap_pcid_enabled) {
1917 pmap->pm_pcids[i].pm_gen = 0;
1919 /* See the comment in pmap_invalidate_page(). */
1920 atomic_thread_fence_seq_cst();
1922 mask = &pmap->pm_active;
1924 smp_masked_invltlb(*mask, pmap);
1929 pmap_invalidate_cache(void)
1939 cpuset_t invalidate; /* processors that invalidate their TLB */
1944 u_int store; /* processor that updates the PDE */
1948 pmap_update_pde_action(void *arg)
1950 struct pde_action *act = arg;
1952 if (act->store == PCPU_GET(cpuid))
1953 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1957 pmap_update_pde_teardown(void *arg)
1959 struct pde_action *act = arg;
1961 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1962 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1966 * Change the page size for the specified virtual address in a way that
1967 * prevents any possibility of the TLB ever having two entries that map the
1968 * same virtual address using different page sizes. This is the recommended
1969 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1970 * machine check exception for a TLB state that is improperly diagnosed as a
1974 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1976 struct pde_action act;
1977 cpuset_t active, other_cpus;
1981 cpuid = PCPU_GET(cpuid);
1982 other_cpus = all_cpus;
1983 CPU_CLR(cpuid, &other_cpus);
1984 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1987 active = pmap->pm_active;
1989 if (CPU_OVERLAP(&active, &other_cpus)) {
1991 act.invalidate = active;
1995 act.newpde = newpde;
1996 CPU_SET(cpuid, &active);
1997 smp_rendezvous_cpus(active,
1998 smp_no_rendezvous_barrier, pmap_update_pde_action,
1999 pmap_update_pde_teardown, &act);
2001 pmap_update_pde_store(pmap, pde, newpde);
2002 if (CPU_ISSET(cpuid, &active))
2003 pmap_update_pde_invalidate(pmap, va, newpde);
2009 * Normal, non-SMP, invalidation functions.
2012 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2014 struct invpcid_descr d;
2015 uint64_t kcr3, ucr3;
2018 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2022 KASSERT(pmap->pm_type == PT_X86,
2023 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2025 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2027 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2028 pmap->pm_ucr3 != PMAP_NO_CR3) {
2030 pcid = pmap->pm_pcids[0].pm_pcid;
2031 if (invpcid_works) {
2032 d.pcid = pcid | PMAP_PCID_USER_PT;
2035 invpcid(&d, INVPCID_ADDR);
2037 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2038 ucr3 = pmap->pm_ucr3 | pcid |
2039 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2040 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2044 } else if (pmap_pcid_enabled)
2045 pmap->pm_pcids[0].pm_gen = 0;
2049 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2051 struct invpcid_descr d;
2053 uint64_t kcr3, ucr3;
2055 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2059 KASSERT(pmap->pm_type == PT_X86,
2060 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2062 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2063 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2065 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2066 pmap->pm_ucr3 != PMAP_NO_CR3) {
2068 if (invpcid_works) {
2069 d.pcid = pmap->pm_pcids[0].pm_pcid |
2073 for (; d.addr < eva; d.addr += PAGE_SIZE)
2074 invpcid(&d, INVPCID_ADDR);
2076 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2077 pm_pcid | CR3_PCID_SAVE;
2078 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2079 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2080 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2084 } else if (pmap_pcid_enabled) {
2085 pmap->pm_pcids[0].pm_gen = 0;
2090 pmap_invalidate_all(pmap_t pmap)
2092 struct invpcid_descr d;
2093 uint64_t kcr3, ucr3;
2095 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2099 KASSERT(pmap->pm_type == PT_X86,
2100 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2102 if (pmap == kernel_pmap) {
2103 if (pmap_pcid_enabled && invpcid_works) {
2104 bzero(&d, sizeof(d));
2105 invpcid(&d, INVPCID_CTXGLOB);
2109 } else if (pmap == PCPU_GET(curpmap)) {
2110 if (pmap_pcid_enabled) {
2112 if (invpcid_works) {
2113 d.pcid = pmap->pm_pcids[0].pm_pcid;
2116 invpcid(&d, INVPCID_CTX);
2117 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2118 d.pcid |= PMAP_PCID_USER_PT;
2119 invpcid(&d, INVPCID_CTX);
2122 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2123 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2124 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2125 0].pm_pcid | PMAP_PCID_USER_PT;
2126 pmap_pti_pcid_invalidate(ucr3, kcr3);
2134 } else if (pmap_pcid_enabled) {
2135 pmap->pm_pcids[0].pm_gen = 0;
2140 pmap_invalidate_cache(void)
2147 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2150 pmap_update_pde_store(pmap, pde, newpde);
2151 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2152 pmap_update_pde_invalidate(pmap, va, newpde);
2154 pmap->pm_pcids[0].pm_gen = 0;
2159 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2163 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2164 * by a promotion that did not invalidate the 512 4KB page mappings
2165 * that might exist in the TLB. Consequently, at this point, the TLB
2166 * may hold both 4KB and 2MB page mappings for the address range [va,
2167 * va + NBPDR). Therefore, the entire range must be invalidated here.
2168 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2169 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2170 * single INVLPG suffices to invalidate the 2MB page mapping from the
2173 if ((pde & PG_PROMOTED) != 0)
2174 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2176 pmap_invalidate_page(pmap, va);
2179 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2182 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
2186 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2188 KASSERT((sva & PAGE_MASK) == 0,
2189 ("pmap_invalidate_cache_range: sva not page-aligned"));
2190 KASSERT((eva & PAGE_MASK) == 0,
2191 ("pmap_invalidate_cache_range: eva not page-aligned"));
2194 if ((cpu_feature & CPUID_SS) != 0 && !force)
2195 ; /* If "Self Snoop" is supported and allowed, do nothing. */
2196 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
2197 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2199 * XXX: Some CPUs fault, hang, or trash the local APIC
2200 * registers if we use CLFLUSH on the local APIC
2201 * range. The local APIC is always uncached, so we
2202 * don't need to flush for that range anyway.
2204 if (pmap_kextract(sva) == lapic_paddr)
2208 * Otherwise, do per-cache line flush. Use the sfence
2209 * instruction to insure that previous stores are
2210 * included in the write-back. The processor
2211 * propagates flush to other processors in the cache
2215 for (; sva < eva; sva += cpu_clflush_line_size)
2218 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
2219 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2220 if (pmap_kextract(sva) == lapic_paddr)
2223 * Writes are ordered by CLFLUSH on Intel CPUs.
2225 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2227 for (; sva < eva; sva += cpu_clflush_line_size)
2229 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2234 * No targeted cache flush methods are supported by CPU,
2235 * or the supplied range is bigger than 2MB.
2236 * Globally invalidate cache.
2238 pmap_invalidate_cache();
2243 * Remove the specified set of pages from the data and instruction caches.
2245 * In contrast to pmap_invalidate_cache_range(), this function does not
2246 * rely on the CPU's self-snoop feature, because it is intended for use
2247 * when moving pages into a different cache domain.
2250 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2252 vm_offset_t daddr, eva;
2256 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2257 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2258 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2259 pmap_invalidate_cache();
2263 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2265 for (i = 0; i < count; i++) {
2266 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2267 eva = daddr + PAGE_SIZE;
2268 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2277 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2283 * Routine: pmap_extract
2285 * Extract the physical page address associated
2286 * with the given map/virtual_address pair.
2289 pmap_extract(pmap_t pmap, vm_offset_t va)
2293 pt_entry_t *pte, PG_V;
2297 PG_V = pmap_valid_bit(pmap);
2299 pdpe = pmap_pdpe(pmap, va);
2300 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2301 if ((*pdpe & PG_PS) != 0)
2302 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2304 pde = pmap_pdpe_to_pde(pdpe, va);
2305 if ((*pde & PG_V) != 0) {
2306 if ((*pde & PG_PS) != 0) {
2307 pa = (*pde & PG_PS_FRAME) |
2310 pte = pmap_pde_to_pte(pde, va);
2311 pa = (*pte & PG_FRAME) |
2322 * Routine: pmap_extract_and_hold
2324 * Atomically extract and hold the physical page
2325 * with the given pmap and virtual address pair
2326 * if that mapping permits the given protection.
2329 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2331 pd_entry_t pde, *pdep;
2332 pt_entry_t pte, PG_RW, PG_V;
2338 PG_RW = pmap_rw_bit(pmap);
2339 PG_V = pmap_valid_bit(pmap);
2342 pdep = pmap_pde(pmap, va);
2343 if (pdep != NULL && (pde = *pdep)) {
2345 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2346 if (vm_page_pa_tryrelock(pmap, (pde &
2347 PG_PS_FRAME) | (va & PDRMASK), &pa))
2349 m = PHYS_TO_VM_PAGE(pa);
2352 pte = *pmap_pde_to_pte(pdep, va);
2354 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2355 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2358 m = PHYS_TO_VM_PAGE(pa);
2370 pmap_kextract(vm_offset_t va)
2375 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2376 pa = DMAP_TO_PHYS(va);
2380 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2383 * Beware of a concurrent promotion that changes the
2384 * PDE at this point! For example, vtopte() must not
2385 * be used to access the PTE because it would use the
2386 * new PDE. It is, however, safe to use the old PDE
2387 * because the page table page is preserved by the
2390 pa = *pmap_pde_to_pte(&pde, va);
2391 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2397 /***************************************************
2398 * Low level mapping routines.....
2399 ***************************************************/
2402 * Add a wired page to the kva.
2403 * Note: not SMP coherent.
2406 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2411 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2414 static __inline void
2415 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2421 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2422 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2426 * Remove a page from the kernel pagetables.
2427 * Note: not SMP coherent.
2430 pmap_kremove(vm_offset_t va)
2439 * Used to map a range of physical addresses into kernel
2440 * virtual address space.
2442 * The value passed in '*virt' is a suggested virtual address for
2443 * the mapping. Architectures which can support a direct-mapped
2444 * physical to virtual region can return the appropriate address
2445 * within that region, leaving '*virt' unchanged. Other
2446 * architectures should map the pages starting at '*virt' and
2447 * update '*virt' with the first usable address after the mapped
2451 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2453 return PHYS_TO_DMAP(start);
2458 * Add a list of wired pages to the kva
2459 * this routine is only used for temporary
2460 * kernel mappings that do not need to have
2461 * page modification or references recorded.
2462 * Note that old mappings are simply written
2463 * over. The page *must* be wired.
2464 * Note: SMP coherent. Uses a ranged shootdown IPI.
2467 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2469 pt_entry_t *endpte, oldpte, pa, *pte;
2475 endpte = pte + count;
2476 while (pte < endpte) {
2478 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2479 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2480 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2482 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2486 if (__predict_false((oldpte & X86_PG_V) != 0))
2487 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2492 * This routine tears out page mappings from the
2493 * kernel -- it is meant only for temporary mappings.
2494 * Note: SMP coherent. Uses a ranged shootdown IPI.
2497 pmap_qremove(vm_offset_t sva, int count)
2502 while (count-- > 0) {
2503 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2507 pmap_invalidate_range(kernel_pmap, sva, va);
2510 /***************************************************
2511 * Page table page management routines.....
2512 ***************************************************/
2514 * Schedule the specified unused page table page to be freed. Specifically,
2515 * add the page to the specified list of pages that will be released to the
2516 * physical memory manager after the TLB has been updated.
2518 static __inline void
2519 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2520 boolean_t set_PG_ZERO)
2524 m->flags |= PG_ZERO;
2526 m->flags &= ~PG_ZERO;
2527 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2531 * Inserts the specified page table page into the specified pmap's collection
2532 * of idle page table pages. Each of a pmap's page table pages is responsible
2533 * for mapping a distinct range of virtual addresses. The pmap's collection is
2534 * ordered by this virtual address range.
2537 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2540 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2541 return (vm_radix_insert(&pmap->pm_root, mpte));
2545 * Removes the page table page mapping the specified virtual address from the
2546 * specified pmap's collection of idle page table pages, and returns it.
2547 * Otherwise, returns NULL if there is no page table page corresponding to the
2548 * specified virtual address.
2550 static __inline vm_page_t
2551 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2554 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2555 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2559 * Decrements a page table page's wire count, which is used to record the
2560 * number of valid page table entries within the page. If the wire count
2561 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2562 * page table page was unmapped and FALSE otherwise.
2564 static inline boolean_t
2565 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2569 if (m->wire_count == 0) {
2570 _pmap_unwire_ptp(pmap, va, m, free);
2577 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2580 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2582 * unmap the page table page
2584 if (m->pindex >= (NUPDE + NUPDPE)) {
2587 pml4 = pmap_pml4e(pmap, va);
2589 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2590 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2593 } else if (m->pindex >= NUPDE) {
2596 pdp = pmap_pdpe(pmap, va);
2601 pd = pmap_pde(pmap, va);
2604 pmap_resident_count_dec(pmap, 1);
2605 if (m->pindex < NUPDE) {
2606 /* We just released a PT, unhold the matching PD */
2609 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2610 pmap_unwire_ptp(pmap, va, pdpg, free);
2612 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2613 /* We just released a PD, unhold the matching PDP */
2616 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2617 pmap_unwire_ptp(pmap, va, pdppg, free);
2621 * Put page on a list so that it is released after
2622 * *ALL* TLB shootdown is done
2624 pmap_add_delayed_free_list(m, free, TRUE);
2628 * After removing a page table entry, this routine is used to
2629 * conditionally free the page, and manage the hold/wire counts.
2632 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2633 struct spglist *free)
2637 if (va >= VM_MAXUSER_ADDRESS)
2639 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2640 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2641 return (pmap_unwire_ptp(pmap, va, mpte, free));
2645 pmap_pinit0(pmap_t pmap)
2649 PMAP_LOCK_INIT(pmap);
2650 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2651 pmap->pm_pml4u = NULL;
2652 pmap->pm_cr3 = KPML4phys;
2653 /* hack to keep pmap_pti_pcid_invalidate() alive */
2654 pmap->pm_ucr3 = PMAP_NO_CR3;
2655 pmap->pm_root.rt_root = 0;
2656 CPU_ZERO(&pmap->pm_active);
2657 TAILQ_INIT(&pmap->pm_pvchunk);
2658 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2659 pmap->pm_flags = pmap_flags;
2661 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
2662 pmap->pm_pcids[i].pm_gen = 1;
2664 pmap_activate_boot(pmap);
2668 pmap_pinit_pml4(vm_page_t pml4pg)
2670 pml4_entry_t *pm_pml4;
2673 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2675 /* Wire in kernel global address entries. */
2676 for (i = 0; i < NKPML4E; i++) {
2677 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2680 for (i = 0; i < ndmpdpphys; i++) {
2681 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2685 /* install self-referential address mapping entry(s) */
2686 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2687 X86_PG_A | X86_PG_M;
2691 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2693 pml4_entry_t *pm_pml4;
2696 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2697 for (i = 0; i < NPML4EPG; i++)
2698 pm_pml4[i] = pti_pml4[i];
2702 * Initialize a preallocated and zeroed pmap structure,
2703 * such as one in a vmspace structure.
2706 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2708 vm_page_t pml4pg, pml4pgu;
2709 vm_paddr_t pml4phys;
2713 * allocate the page directory page
2715 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2716 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2718 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2719 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2721 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2722 pmap->pm_pcids[i].pm_gen = 0;
2724 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2725 pmap->pm_ucr3 = PMAP_NO_CR3;
2726 pmap->pm_pml4u = NULL;
2728 pmap->pm_type = pm_type;
2729 if ((pml4pg->flags & PG_ZERO) == 0)
2730 pagezero(pmap->pm_pml4);
2733 * Do not install the host kernel mappings in the nested page
2734 * tables. These mappings are meaningless in the guest physical
2736 * Install minimal kernel mappings in PTI case.
2738 if (pm_type == PT_X86) {
2739 pmap->pm_cr3 = pml4phys;
2740 pmap_pinit_pml4(pml4pg);
2742 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2743 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2744 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2745 VM_PAGE_TO_PHYS(pml4pgu));
2746 pmap_pinit_pml4_pti(pml4pgu);
2747 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2751 pmap->pm_root.rt_root = 0;
2752 CPU_ZERO(&pmap->pm_active);
2753 TAILQ_INIT(&pmap->pm_pvchunk);
2754 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2755 pmap->pm_flags = flags;
2756 pmap->pm_eptgen = 0;
2762 pmap_pinit(pmap_t pmap)
2765 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2769 * This routine is called if the desired page table page does not exist.
2771 * If page table page allocation fails, this routine may sleep before
2772 * returning NULL. It sleeps only if a lock pointer was given.
2774 * Note: If a page allocation fails at page table level two or three,
2775 * one or two pages may be held during the wait, only to be released
2776 * afterwards. This conservative approach is easily argued to avoid
2780 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2782 vm_page_t m, pdppg, pdpg;
2783 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2787 PG_A = pmap_accessed_bit(pmap);
2788 PG_M = pmap_modified_bit(pmap);
2789 PG_V = pmap_valid_bit(pmap);
2790 PG_RW = pmap_rw_bit(pmap);
2793 * Allocate a page table page.
2795 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2796 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2797 if (lockp != NULL) {
2798 RELEASE_PV_LIST_LOCK(lockp);
2800 PMAP_ASSERT_NOT_IN_DI();
2806 * Indicate the need to retry. While waiting, the page table
2807 * page may have been allocated.
2811 if ((m->flags & PG_ZERO) == 0)
2815 * Map the pagetable page into the process address space, if
2816 * it isn't already there.
2819 if (ptepindex >= (NUPDE + NUPDPE)) {
2820 pml4_entry_t *pml4, *pml4u;
2821 vm_pindex_t pml4index;
2823 /* Wire up a new PDPE page */
2824 pml4index = ptepindex - (NUPDE + NUPDPE);
2825 pml4 = &pmap->pm_pml4[pml4index];
2826 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2827 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
2829 * PTI: Make all user-space mappings in the
2830 * kernel-mode page table no-execute so that
2831 * we detect any programming errors that leave
2832 * the kernel-mode page table active on return
2835 if (pmap->pm_ucr3 != PMAP_NO_CR3)
2838 pml4u = &pmap->pm_pml4u[pml4index];
2839 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
2843 } else if (ptepindex >= NUPDE) {
2844 vm_pindex_t pml4index;
2845 vm_pindex_t pdpindex;
2849 /* Wire up a new PDE page */
2850 pdpindex = ptepindex - NUPDE;
2851 pml4index = pdpindex >> NPML4EPGSHIFT;
2853 pml4 = &pmap->pm_pml4[pml4index];
2854 if ((*pml4 & PG_V) == 0) {
2855 /* Have to allocate a new pdp, recurse */
2856 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2858 vm_page_unwire_noq(m);
2859 vm_page_free_zero(m);
2863 /* Add reference to pdp page */
2864 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2865 pdppg->wire_count++;
2867 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2869 /* Now find the pdp page */
2870 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2871 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2874 vm_pindex_t pml4index;
2875 vm_pindex_t pdpindex;
2880 /* Wire up a new PTE page */
2881 pdpindex = ptepindex >> NPDPEPGSHIFT;
2882 pml4index = pdpindex >> NPML4EPGSHIFT;
2884 /* First, find the pdp and check that its valid. */
2885 pml4 = &pmap->pm_pml4[pml4index];
2886 if ((*pml4 & PG_V) == 0) {
2887 /* Have to allocate a new pd, recurse */
2888 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2890 vm_page_unwire_noq(m);
2891 vm_page_free_zero(m);
2894 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2895 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2897 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2898 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2899 if ((*pdp & PG_V) == 0) {
2900 /* Have to allocate a new pd, recurse */
2901 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2903 vm_page_unwire_noq(m);
2904 vm_page_free_zero(m);
2908 /* Add reference to the pd page */
2909 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2913 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2915 /* Now we know where the page directory page is */
2916 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2917 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2920 pmap_resident_count_inc(pmap, 1);
2926 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2928 vm_pindex_t pdpindex, ptepindex;
2929 pdp_entry_t *pdpe, PG_V;
2932 PG_V = pmap_valid_bit(pmap);
2935 pdpe = pmap_pdpe(pmap, va);
2936 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2937 /* Add a reference to the pd page. */
2938 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2941 /* Allocate a pd page. */
2942 ptepindex = pmap_pde_pindex(va);
2943 pdpindex = ptepindex >> NPDPEPGSHIFT;
2944 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2945 if (pdpg == NULL && lockp != NULL)
2952 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2954 vm_pindex_t ptepindex;
2955 pd_entry_t *pd, PG_V;
2958 PG_V = pmap_valid_bit(pmap);
2961 * Calculate pagetable page index
2963 ptepindex = pmap_pde_pindex(va);
2966 * Get the page directory entry
2968 pd = pmap_pde(pmap, va);
2971 * This supports switching from a 2MB page to a
2974 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2975 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2977 * Invalidation of the 2MB page mapping may have caused
2978 * the deallocation of the underlying PD page.
2985 * If the page table page is mapped, we just increment the
2986 * hold count, and activate it.
2988 if (pd != NULL && (*pd & PG_V) != 0) {
2989 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2993 * Here if the pte page isn't mapped, or if it has been
2996 m = _pmap_allocpte(pmap, ptepindex, lockp);
2997 if (m == NULL && lockp != NULL)
3004 /***************************************************
3005 * Pmap allocation/deallocation routines.
3006 ***************************************************/
3009 * Release any resources held by the given physical map.
3010 * Called when a pmap initialized by pmap_pinit is being released.
3011 * Should only be called if the map contains no valid mappings.
3014 pmap_release(pmap_t pmap)
3019 KASSERT(pmap->pm_stats.resident_count == 0,
3020 ("pmap_release: pmap resident count %ld != 0",
3021 pmap->pm_stats.resident_count));
3022 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3023 ("pmap_release: pmap has reserved page table page(s)"));
3024 KASSERT(CPU_EMPTY(&pmap->pm_active),
3025 ("releasing active pmap %p", pmap));
3027 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3029 for (i = 0; i < NKPML4E; i++) /* KVA */
3030 pmap->pm_pml4[KPML4BASE + i] = 0;
3031 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3032 pmap->pm_pml4[DMPML4I + i] = 0;
3033 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3035 vm_page_unwire_noq(m);
3036 vm_page_free_zero(m);
3038 if (pmap->pm_pml4u != NULL) {
3039 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3040 vm_page_unwire_noq(m);
3046 kvm_size(SYSCTL_HANDLER_ARGS)
3048 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3050 return sysctl_handle_long(oidp, &ksize, 0, req);
3052 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3053 0, 0, kvm_size, "LU", "Size of KVM");
3056 kvm_free(SYSCTL_HANDLER_ARGS)
3058 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3060 return sysctl_handle_long(oidp, &kfree, 0, req);
3062 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3063 0, 0, kvm_free, "LU", "Amount of KVM free");
3066 * grow the number of kernel page table entries, if needed
3069 pmap_growkernel(vm_offset_t addr)
3073 pd_entry_t *pde, newpdir;
3076 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3079 * Return if "addr" is within the range of kernel page table pages
3080 * that were preallocated during pmap bootstrap. Moreover, leave
3081 * "kernel_vm_end" and the kernel page table as they were.
3083 * The correctness of this action is based on the following
3084 * argument: vm_map_insert() allocates contiguous ranges of the
3085 * kernel virtual address space. It calls this function if a range
3086 * ends after "kernel_vm_end". If the kernel is mapped between
3087 * "kernel_vm_end" and "addr", then the range cannot begin at
3088 * "kernel_vm_end". In fact, its beginning address cannot be less
3089 * than the kernel. Thus, there is no immediate need to allocate
3090 * any new kernel page table pages between "kernel_vm_end" and
3093 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3096 addr = roundup2(addr, NBPDR);
3097 if (addr - 1 >= vm_map_max(kernel_map))
3098 addr = vm_map_max(kernel_map);
3099 while (kernel_vm_end < addr) {
3100 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3101 if ((*pdpe & X86_PG_V) == 0) {
3102 /* We need a new PDP entry */
3103 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3104 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3105 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3107 panic("pmap_growkernel: no memory to grow kernel");
3108 if ((nkpg->flags & PG_ZERO) == 0)
3109 pmap_zero_page(nkpg);
3110 paddr = VM_PAGE_TO_PHYS(nkpg);
3111 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3112 X86_PG_A | X86_PG_M);
3113 continue; /* try again */
3115 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3116 if ((*pde & X86_PG_V) != 0) {
3117 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3118 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3119 kernel_vm_end = vm_map_max(kernel_map);
3125 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3126 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3129 panic("pmap_growkernel: no memory to grow kernel");
3130 if ((nkpg->flags & PG_ZERO) == 0)
3131 pmap_zero_page(nkpg);
3132 paddr = VM_PAGE_TO_PHYS(nkpg);
3133 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3134 pde_store(pde, newpdir);
3136 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3137 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3138 kernel_vm_end = vm_map_max(kernel_map);
3145 /***************************************************
3146 * page management routines.
3147 ***************************************************/
3149 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3150 CTASSERT(_NPCM == 3);
3151 CTASSERT(_NPCPV == 168);
3153 static __inline struct pv_chunk *
3154 pv_to_chunk(pv_entry_t pv)
3157 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3160 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3162 #define PC_FREE0 0xfffffffffffffffful
3163 #define PC_FREE1 0xfffffffffffffffful
3164 #define PC_FREE2 0x000000fffffffffful
3166 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3169 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3171 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3172 "Current number of pv entry chunks");
3173 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3174 "Current number of pv entry chunks allocated");
3175 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3176 "Current number of pv entry chunks frees");
3177 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3178 "Number of times tried to get a chunk page but failed.");
3180 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3181 static int pv_entry_spare;
3183 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3184 "Current number of pv entry frees");
3185 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3186 "Current number of pv entry allocs");
3187 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3188 "Current number of pv entries");
3189 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3190 "Current number of spare pv entries");
3194 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3199 pmap_invalidate_all(pmap);
3200 if (pmap != locked_pmap)
3203 pmap_delayed_invl_finished();
3207 * We are in a serious low memory condition. Resort to
3208 * drastic measures to free some pages so we can allocate
3209 * another pv entry chunk.
3211 * Returns NULL if PV entries were reclaimed from the specified pmap.
3213 * We do not, however, unmap 2mpages because subsequent accesses will
3214 * allocate per-page pv entries until repromotion occurs, thereby
3215 * exacerbating the shortage of free pv entries.
3218 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3220 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3221 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3222 struct md_page *pvh;
3224 pmap_t next_pmap, pmap;
3225 pt_entry_t *pte, tpte;
3226 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3230 struct spglist free;
3232 int bit, field, freed;
3234 static int active_reclaims = 0;
3236 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3237 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3240 PG_G = PG_A = PG_M = PG_RW = 0;
3242 bzero(&pc_marker_b, sizeof(pc_marker_b));
3243 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3244 pc_marker = (struct pv_chunk *)&pc_marker_b;
3245 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3248 * A delayed invalidation block should already be active if
3249 * pmap_advise() or pmap_remove() called this function by way
3250 * of pmap_demote_pde_locked().
3252 start_di = pmap_not_in_di();
3254 mtx_lock(&pv_chunks_mutex);
3256 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3257 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3258 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3259 SLIST_EMPTY(&free)) {
3260 next_pmap = pc->pc_pmap;
3261 if (next_pmap == NULL) {
3263 * The next chunk is a marker. However, it is
3264 * not our marker, so active_reclaims must be
3265 * > 1. Consequently, the next_chunk code
3266 * will not rotate the pv_chunks list.
3270 mtx_unlock(&pv_chunks_mutex);
3273 * A pv_chunk can only be removed from the pc_lru list
3274 * when both pc_chunks_mutex is owned and the
3275 * corresponding pmap is locked.
3277 if (pmap != next_pmap) {
3278 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3281 /* Avoid deadlock and lock recursion. */
3282 if (pmap > locked_pmap) {
3283 RELEASE_PV_LIST_LOCK(lockp);
3286 pmap_delayed_invl_started();
3287 mtx_lock(&pv_chunks_mutex);
3289 } else if (pmap != locked_pmap) {
3290 if (PMAP_TRYLOCK(pmap)) {
3292 pmap_delayed_invl_started();
3293 mtx_lock(&pv_chunks_mutex);
3296 pmap = NULL; /* pmap is not locked */
3297 mtx_lock(&pv_chunks_mutex);
3298 pc = TAILQ_NEXT(pc_marker, pc_lru);
3300 pc->pc_pmap != next_pmap)
3304 } else if (start_di)
3305 pmap_delayed_invl_started();
3306 PG_G = pmap_global_bit(pmap);
3307 PG_A = pmap_accessed_bit(pmap);
3308 PG_M = pmap_modified_bit(pmap);
3309 PG_RW = pmap_rw_bit(pmap);
3313 * Destroy every non-wired, 4 KB page mapping in the chunk.
3316 for (field = 0; field < _NPCM; field++) {
3317 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3318 inuse != 0; inuse &= ~(1UL << bit)) {
3320 pv = &pc->pc_pventry[field * 64 + bit];
3322 pde = pmap_pde(pmap, va);
3323 if ((*pde & PG_PS) != 0)
3325 pte = pmap_pde_to_pte(pde, va);
3326 if ((*pte & PG_W) != 0)
3328 tpte = pte_load_clear(pte);
3329 if ((tpte & PG_G) != 0)
3330 pmap_invalidate_page(pmap, va);
3331 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3332 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3334 if ((tpte & PG_A) != 0)
3335 vm_page_aflag_set(m, PGA_REFERENCED);
3336 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3337 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3339 if (TAILQ_EMPTY(&m->md.pv_list) &&
3340 (m->flags & PG_FICTITIOUS) == 0) {
3341 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3342 if (TAILQ_EMPTY(&pvh->pv_list)) {
3343 vm_page_aflag_clear(m,
3347 pmap_delayed_invl_page(m);
3348 pc->pc_map[field] |= 1UL << bit;
3349 pmap_unuse_pt(pmap, va, *pde, &free);
3354 mtx_lock(&pv_chunks_mutex);
3357 /* Every freed mapping is for a 4 KB page. */
3358 pmap_resident_count_dec(pmap, freed);
3359 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3360 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3361 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3362 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3363 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3364 pc->pc_map[2] == PC_FREE2) {
3365 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3366 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3367 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3368 /* Entire chunk is free; return it. */
3369 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3370 dump_drop_page(m_pc->phys_addr);
3371 mtx_lock(&pv_chunks_mutex);
3372 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3375 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3376 mtx_lock(&pv_chunks_mutex);
3377 /* One freed pv entry in locked_pmap is sufficient. */
3378 if (pmap == locked_pmap)
3381 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3382 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3383 if (active_reclaims == 1 && pmap != NULL) {
3385 * Rotate the pv chunks list so that we do not
3386 * scan the same pv chunks that could not be
3387 * freed (because they contained a wired
3388 * and/or superpage mapping) on every
3389 * invocation of reclaim_pv_chunk().
3391 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3392 MPASS(pc->pc_pmap != NULL);
3393 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3394 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3398 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3399 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3401 mtx_unlock(&pv_chunks_mutex);
3402 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3403 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3404 m_pc = SLIST_FIRST(&free);
3405 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3406 /* Recycle a freed page table page. */
3407 m_pc->wire_count = 1;
3409 vm_page_free_pages_toq(&free, true);
3414 * free the pv_entry back to the free list
3417 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3419 struct pv_chunk *pc;
3420 int idx, field, bit;
3422 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3423 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3424 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3425 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3426 pc = pv_to_chunk(pv);
3427 idx = pv - &pc->pc_pventry[0];
3430 pc->pc_map[field] |= 1ul << bit;
3431 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3432 pc->pc_map[2] != PC_FREE2) {
3433 /* 98% of the time, pc is already at the head of the list. */
3434 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3435 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3436 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3440 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3445 free_pv_chunk(struct pv_chunk *pc)
3449 mtx_lock(&pv_chunks_mutex);
3450 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3451 mtx_unlock(&pv_chunks_mutex);
3452 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3453 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3454 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3455 /* entire chunk is free, return it */
3456 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3457 dump_drop_page(m->phys_addr);
3458 vm_page_unwire(m, PQ_NONE);
3463 * Returns a new PV entry, allocating a new PV chunk from the system when
3464 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3465 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3468 * The given PV list lock may be released.
3471 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3475 struct pv_chunk *pc;
3478 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3479 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3481 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3483 for (field = 0; field < _NPCM; field++) {
3484 if (pc->pc_map[field]) {
3485 bit = bsfq(pc->pc_map[field]);
3489 if (field < _NPCM) {
3490 pv = &pc->pc_pventry[field * 64 + bit];
3491 pc->pc_map[field] &= ~(1ul << bit);
3492 /* If this was the last item, move it to tail */
3493 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3494 pc->pc_map[2] == 0) {
3495 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3496 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3499 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3500 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3504 /* No free items, allocate another chunk */
3505 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3508 if (lockp == NULL) {
3509 PV_STAT(pc_chunk_tryfail++);
3512 m = reclaim_pv_chunk(pmap, lockp);
3516 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3517 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3518 dump_add_page(m->phys_addr);
3519 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3521 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3522 pc->pc_map[1] = PC_FREE1;
3523 pc->pc_map[2] = PC_FREE2;
3524 mtx_lock(&pv_chunks_mutex);
3525 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3526 mtx_unlock(&pv_chunks_mutex);
3527 pv = &pc->pc_pventry[0];
3528 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3529 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3530 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3535 * Returns the number of one bits within the given PV chunk map.
3537 * The erratas for Intel processors state that "POPCNT Instruction May
3538 * Take Longer to Execute Than Expected". It is believed that the
3539 * issue is the spurious dependency on the destination register.
3540 * Provide a hint to the register rename logic that the destination
3541 * value is overwritten, by clearing it, as suggested in the
3542 * optimization manual. It should be cheap for unaffected processors
3545 * Reference numbers for erratas are
3546 * 4th Gen Core: HSD146
3547 * 5th Gen Core: BDM85
3548 * 6th Gen Core: SKL029
3551 popcnt_pc_map_pq(uint64_t *map)
3555 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3556 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3557 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3558 : "=&r" (result), "=&r" (tmp)
3559 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3564 * Ensure that the number of spare PV entries in the specified pmap meets or
3565 * exceeds the given count, "needed".
3567 * The given PV list lock may be released.
3570 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3572 struct pch new_tail;
3573 struct pv_chunk *pc;
3578 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3579 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3582 * Newly allocated PV chunks must be stored in a private list until
3583 * the required number of PV chunks have been allocated. Otherwise,
3584 * reclaim_pv_chunk() could recycle one of these chunks. In
3585 * contrast, these chunks must be added to the pmap upon allocation.
3587 TAILQ_INIT(&new_tail);
3590 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3592 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3593 bit_count((bitstr_t *)pc->pc_map, 0,
3594 sizeof(pc->pc_map) * NBBY, &free);
3597 free = popcnt_pc_map_pq(pc->pc_map);
3601 if (avail >= needed)
3604 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3605 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3608 m = reclaim_pv_chunk(pmap, lockp);
3613 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3614 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3615 dump_add_page(m->phys_addr);
3616 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3618 pc->pc_map[0] = PC_FREE0;
3619 pc->pc_map[1] = PC_FREE1;
3620 pc->pc_map[2] = PC_FREE2;
3621 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3622 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3623 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3626 * The reclaim might have freed a chunk from the current pmap.
3627 * If that chunk contained available entries, we need to
3628 * re-count the number of available entries.
3633 if (!TAILQ_EMPTY(&new_tail)) {
3634 mtx_lock(&pv_chunks_mutex);
3635 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3636 mtx_unlock(&pv_chunks_mutex);
3641 * First find and then remove the pv entry for the specified pmap and virtual
3642 * address from the specified pv list. Returns the pv entry if found and NULL
3643 * otherwise. This operation can be performed on pv lists for either 4KB or
3644 * 2MB page mappings.
3646 static __inline pv_entry_t
3647 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3651 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3652 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3653 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3662 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3663 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3664 * entries for each of the 4KB page mappings.
3667 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3668 struct rwlock **lockp)
3670 struct md_page *pvh;
3671 struct pv_chunk *pc;
3673 vm_offset_t va_last;
3677 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3678 KASSERT((pa & PDRMASK) == 0,
3679 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3680 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3683 * Transfer the 2mpage's pv entry for this mapping to the first
3684 * page's pv list. Once this transfer begins, the pv list lock
3685 * must not be released until the last pv entry is reinstantiated.
3687 pvh = pa_to_pvh(pa);
3688 va = trunc_2mpage(va);
3689 pv = pmap_pvh_remove(pvh, pmap, va);
3690 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3691 m = PHYS_TO_VM_PAGE(pa);
3692 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3694 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3695 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3696 va_last = va + NBPDR - PAGE_SIZE;
3698 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3699 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3700 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3701 for (field = 0; field < _NPCM; field++) {
3702 while (pc->pc_map[field]) {
3703 bit = bsfq(pc->pc_map[field]);
3704 pc->pc_map[field] &= ~(1ul << bit);
3705 pv = &pc->pc_pventry[field * 64 + bit];
3709 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3710 ("pmap_pv_demote_pde: page %p is not managed", m));
3711 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3717 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3718 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3721 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3722 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3723 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3725 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3726 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3729 #if VM_NRESERVLEVEL > 0
3731 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3732 * replace the many pv entries for the 4KB page mappings by a single pv entry
3733 * for the 2MB page mapping.
3736 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3737 struct rwlock **lockp)
3739 struct md_page *pvh;
3741 vm_offset_t va_last;
3744 KASSERT((pa & PDRMASK) == 0,
3745 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3746 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3749 * Transfer the first page's pv entry for this mapping to the 2mpage's
3750 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3751 * a transfer avoids the possibility that get_pv_entry() calls
3752 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3753 * mappings that is being promoted.
3755 m = PHYS_TO_VM_PAGE(pa);
3756 va = trunc_2mpage(va);
3757 pv = pmap_pvh_remove(&m->md, pmap, va);
3758 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3759 pvh = pa_to_pvh(pa);
3760 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3762 /* Free the remaining NPTEPG - 1 pv entries. */
3763 va_last = va + NBPDR - PAGE_SIZE;
3767 pmap_pvh_free(&m->md, pmap, va);
3768 } while (va < va_last);
3770 #endif /* VM_NRESERVLEVEL > 0 */
3773 * First find and then destroy the pv entry for the specified pmap and virtual
3774 * address. This operation can be performed on pv lists for either 4KB or 2MB
3778 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3782 pv = pmap_pvh_remove(pvh, pmap, va);
3783 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3784 free_pv_entry(pmap, pv);
3788 * Conditionally create the PV entry for a 4KB page mapping if the required
3789 * memory can be allocated without resorting to reclamation.
3792 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3793 struct rwlock **lockp)
3797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3798 /* Pass NULL instead of the lock pointer to disable reclamation. */
3799 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3801 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3802 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3810 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3811 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3812 * false if the PV entry cannot be allocated without resorting to reclamation.
3815 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
3816 struct rwlock **lockp)
3818 struct md_page *pvh;
3822 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3823 /* Pass NULL instead of the lock pointer to disable reclamation. */
3824 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3825 NULL : lockp)) == NULL)
3828 pa = pde & PG_PS_FRAME;
3829 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3830 pvh = pa_to_pvh(pa);
3831 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3837 * Fills a page table page with mappings to consecutive physical pages.
3840 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3844 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3846 newpte += PAGE_SIZE;
3851 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3852 * mapping is invalidated.
3855 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3857 struct rwlock *lock;
3861 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3868 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3869 struct rwlock **lockp)
3871 pd_entry_t newpde, oldpde;
3872 pt_entry_t *firstpte, newpte;
3873 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3876 struct spglist free;
3880 PG_G = pmap_global_bit(pmap);
3881 PG_A = pmap_accessed_bit(pmap);
3882 PG_M = pmap_modified_bit(pmap);
3883 PG_RW = pmap_rw_bit(pmap);
3884 PG_V = pmap_valid_bit(pmap);
3885 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3887 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3889 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3890 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3891 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
3893 KASSERT((oldpde & PG_W) == 0,
3894 ("pmap_demote_pde: page table page for a wired mapping"
3898 * Invalidate the 2MB page mapping and return "failure" if the
3899 * mapping was never accessed or the allocation of the new
3900 * page table page fails. If the 2MB page mapping belongs to
3901 * the direct map region of the kernel's address space, then
3902 * the page allocation request specifies the highest possible
3903 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3904 * normal. Page table pages are preallocated for every other
3905 * part of the kernel address space, so the direct map region
3906 * is the only part of the kernel address space that must be
3909 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3910 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3911 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3912 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3914 sva = trunc_2mpage(va);
3915 pmap_remove_pde(pmap, pde, sva, &free, lockp);
3916 if ((oldpde & PG_G) == 0)
3917 pmap_invalidate_pde_page(pmap, sva, oldpde);
3918 vm_page_free_pages_toq(&free, true);
3919 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3920 " in pmap %p", va, pmap);
3923 if (va < VM_MAXUSER_ADDRESS)
3924 pmap_resident_count_inc(pmap, 1);
3926 mptepa = VM_PAGE_TO_PHYS(mpte);
3927 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3928 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3929 KASSERT((oldpde & PG_A) != 0,
3930 ("pmap_demote_pde: oldpde is missing PG_A"));
3931 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3932 ("pmap_demote_pde: oldpde is missing PG_M"));
3933 newpte = oldpde & ~PG_PS;
3934 newpte = pmap_swap_pat(pmap, newpte);
3937 * If the page table page is new, initialize it.
3939 if (mpte->wire_count == 1) {
3940 mpte->wire_count = NPTEPG;
3941 pmap_fill_ptp(firstpte, newpte);
3943 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3944 ("pmap_demote_pde: firstpte and newpte map different physical"
3948 * If the mapping has changed attributes, update the page table
3951 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3952 pmap_fill_ptp(firstpte, newpte);
3955 * The spare PV entries must be reserved prior to demoting the
3956 * mapping, that is, prior to changing the PDE. Otherwise, the state
3957 * of the PDE and the PV lists will be inconsistent, which can result
3958 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3959 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3960 * PV entry for the 2MB page mapping that is being demoted.
3962 if ((oldpde & PG_MANAGED) != 0)
3963 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3966 * Demote the mapping. This pmap is locked. The old PDE has
3967 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3968 * set. Thus, there is no danger of a race with another
3969 * processor changing the setting of PG_A and/or PG_M between
3970 * the read above and the store below.
3972 if (workaround_erratum383)
3973 pmap_update_pde(pmap, va, pde, newpde);
3975 pde_store(pde, newpde);
3978 * Invalidate a stale recursive mapping of the page table page.
3980 if (va >= VM_MAXUSER_ADDRESS)
3981 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3984 * Demote the PV entry.
3986 if ((oldpde & PG_MANAGED) != 0)
3987 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3989 atomic_add_long(&pmap_pde_demotions, 1);
3990 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3991 " in pmap %p", va, pmap);
3996 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3999 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4005 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4006 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4007 mpte = pmap_remove_pt_page(pmap, va);
4009 panic("pmap_remove_kernel_pde: Missing pt page.");
4011 mptepa = VM_PAGE_TO_PHYS(mpte);
4012 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4015 * Initialize the page table page.
4017 pagezero((void *)PHYS_TO_DMAP(mptepa));
4020 * Demote the mapping.
4022 if (workaround_erratum383)
4023 pmap_update_pde(pmap, va, pde, newpde);
4025 pde_store(pde, newpde);
4028 * Invalidate a stale recursive mapping of the page table page.
4030 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4034 * pmap_remove_pde: do the things to unmap a superpage in a process
4037 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4038 struct spglist *free, struct rwlock **lockp)
4040 struct md_page *pvh;
4042 vm_offset_t eva, va;
4044 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4046 PG_G = pmap_global_bit(pmap);
4047 PG_A = pmap_accessed_bit(pmap);
4048 PG_M = pmap_modified_bit(pmap);
4049 PG_RW = pmap_rw_bit(pmap);
4051 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4052 KASSERT((sva & PDRMASK) == 0,
4053 ("pmap_remove_pde: sva is not 2mpage aligned"));
4054 oldpde = pte_load_clear(pdq);
4056 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4057 if ((oldpde & PG_G) != 0)
4058 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4059 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4060 if (oldpde & PG_MANAGED) {
4061 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4062 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4063 pmap_pvh_free(pvh, pmap, sva);
4065 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4066 va < eva; va += PAGE_SIZE, m++) {
4067 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4070 vm_page_aflag_set(m, PGA_REFERENCED);
4071 if (TAILQ_EMPTY(&m->md.pv_list) &&
4072 TAILQ_EMPTY(&pvh->pv_list))
4073 vm_page_aflag_clear(m, PGA_WRITEABLE);
4074 pmap_delayed_invl_page(m);
4077 if (pmap == kernel_pmap) {
4078 pmap_remove_kernel_pde(pmap, pdq, sva);
4080 mpte = pmap_remove_pt_page(pmap, sva);
4082 pmap_resident_count_dec(pmap, 1);
4083 KASSERT(mpte->wire_count == NPTEPG,
4084 ("pmap_remove_pde: pte page wire count error"));
4085 mpte->wire_count = 0;
4086 pmap_add_delayed_free_list(mpte, free, FALSE);
4089 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4093 * pmap_remove_pte: do the things to unmap a page in a process
4096 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4097 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4099 struct md_page *pvh;
4100 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4103 PG_A = pmap_accessed_bit(pmap);
4104 PG_M = pmap_modified_bit(pmap);
4105 PG_RW = pmap_rw_bit(pmap);
4107 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4108 oldpte = pte_load_clear(ptq);
4110 pmap->pm_stats.wired_count -= 1;
4111 pmap_resident_count_dec(pmap, 1);
4112 if (oldpte & PG_MANAGED) {
4113 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4114 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4117 vm_page_aflag_set(m, PGA_REFERENCED);
4118 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4119 pmap_pvh_free(&m->md, pmap, va);
4120 if (TAILQ_EMPTY(&m->md.pv_list) &&
4121 (m->flags & PG_FICTITIOUS) == 0) {
4122 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4123 if (TAILQ_EMPTY(&pvh->pv_list))
4124 vm_page_aflag_clear(m, PGA_WRITEABLE);
4126 pmap_delayed_invl_page(m);
4128 return (pmap_unuse_pt(pmap, va, ptepde, free));
4132 * Remove a single page from a process address space
4135 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4136 struct spglist *free)
4138 struct rwlock *lock;
4139 pt_entry_t *pte, PG_V;
4141 PG_V = pmap_valid_bit(pmap);
4142 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4143 if ((*pde & PG_V) == 0)
4145 pte = pmap_pde_to_pte(pde, va);
4146 if ((*pte & PG_V) == 0)
4149 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4152 pmap_invalidate_page(pmap, va);
4156 * Removes the specified range of addresses from the page table page.
4159 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4160 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4162 pt_entry_t PG_G, *pte;
4166 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4167 PG_G = pmap_global_bit(pmap);
4170 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4174 pmap_invalidate_range(pmap, va, sva);
4179 if ((*pte & PG_G) == 0)
4183 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4189 pmap_invalidate_range(pmap, va, sva);
4194 * Remove the given range of addresses from the specified map.
4196 * It is assumed that the start and end are properly
4197 * rounded to the page size.
4200 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4202 struct rwlock *lock;
4203 vm_offset_t va_next;
4204 pml4_entry_t *pml4e;
4206 pd_entry_t ptpaddr, *pde;
4207 pt_entry_t PG_G, PG_V;
4208 struct spglist free;
4211 PG_G = pmap_global_bit(pmap);
4212 PG_V = pmap_valid_bit(pmap);
4215 * Perform an unsynchronized read. This is, however, safe.
4217 if (pmap->pm_stats.resident_count == 0)
4223 pmap_delayed_invl_started();
4227 * special handling of removing one page. a very
4228 * common operation and easy to short circuit some
4231 if (sva + PAGE_SIZE == eva) {
4232 pde = pmap_pde(pmap, sva);
4233 if (pde && (*pde & PG_PS) == 0) {
4234 pmap_remove_page(pmap, sva, pde, &free);
4240 for (; sva < eva; sva = va_next) {
4242 if (pmap->pm_stats.resident_count == 0)
4245 pml4e = pmap_pml4e(pmap, sva);
4246 if ((*pml4e & PG_V) == 0) {
4247 va_next = (sva + NBPML4) & ~PML4MASK;
4253 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4254 if ((*pdpe & PG_V) == 0) {
4255 va_next = (sva + NBPDP) & ~PDPMASK;
4262 * Calculate index for next page table.
4264 va_next = (sva + NBPDR) & ~PDRMASK;
4268 pde = pmap_pdpe_to_pde(pdpe, sva);
4272 * Weed out invalid mappings.
4278 * Check for large page.
4280 if ((ptpaddr & PG_PS) != 0) {
4282 * Are we removing the entire large page? If not,
4283 * demote the mapping and fall through.
4285 if (sva + NBPDR == va_next && eva >= va_next) {
4287 * The TLB entry for a PG_G mapping is
4288 * invalidated by pmap_remove_pde().
4290 if ((ptpaddr & PG_G) == 0)
4292 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4294 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4296 /* The large page mapping was destroyed. */
4303 * Limit our scan to either the end of the va represented
4304 * by the current page table page, or to the end of the
4305 * range being removed.
4310 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4317 pmap_invalidate_all(pmap);
4319 pmap_delayed_invl_finished();
4320 vm_page_free_pages_toq(&free, true);
4324 * Routine: pmap_remove_all
4326 * Removes this physical page from
4327 * all physical maps in which it resides.
4328 * Reflects back modify bits to the pager.
4331 * Original versions of this routine were very
4332 * inefficient because they iteratively called
4333 * pmap_remove (slow...)
4337 pmap_remove_all(vm_page_t m)
4339 struct md_page *pvh;
4342 struct rwlock *lock;
4343 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4346 struct spglist free;
4347 int pvh_gen, md_gen;
4349 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4350 ("pmap_remove_all: page %p is not managed", m));
4352 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4353 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4354 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4357 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4359 if (!PMAP_TRYLOCK(pmap)) {
4360 pvh_gen = pvh->pv_gen;
4364 if (pvh_gen != pvh->pv_gen) {
4371 pde = pmap_pde(pmap, va);
4372 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4375 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4377 if (!PMAP_TRYLOCK(pmap)) {
4378 pvh_gen = pvh->pv_gen;
4379 md_gen = m->md.pv_gen;
4383 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4389 PG_A = pmap_accessed_bit(pmap);
4390 PG_M = pmap_modified_bit(pmap);
4391 PG_RW = pmap_rw_bit(pmap);
4392 pmap_resident_count_dec(pmap, 1);
4393 pde = pmap_pde(pmap, pv->pv_va);
4394 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4395 " a 2mpage in page %p's pv list", m));
4396 pte = pmap_pde_to_pte(pde, pv->pv_va);
4397 tpte = pte_load_clear(pte);
4399 pmap->pm_stats.wired_count--;
4401 vm_page_aflag_set(m, PGA_REFERENCED);
4404 * Update the vm_page_t clean and reference bits.
4406 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4408 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4409 pmap_invalidate_page(pmap, pv->pv_va);
4410 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4412 free_pv_entry(pmap, pv);
4415 vm_page_aflag_clear(m, PGA_WRITEABLE);
4417 pmap_delayed_invl_wait(m);
4418 vm_page_free_pages_toq(&free, true);
4422 * pmap_protect_pde: do the things to protect a 2mpage in a process
4425 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4427 pd_entry_t newpde, oldpde;
4428 vm_offset_t eva, va;
4430 boolean_t anychanged;
4431 pt_entry_t PG_G, PG_M, PG_RW;
4433 PG_G = pmap_global_bit(pmap);
4434 PG_M = pmap_modified_bit(pmap);
4435 PG_RW = pmap_rw_bit(pmap);
4437 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4438 KASSERT((sva & PDRMASK) == 0,
4439 ("pmap_protect_pde: sva is not 2mpage aligned"));
4442 oldpde = newpde = *pde;
4443 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4444 (PG_MANAGED | PG_M | PG_RW)) {
4446 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4447 va < eva; va += PAGE_SIZE, m++)
4450 if ((prot & VM_PROT_WRITE) == 0)
4451 newpde &= ~(PG_RW | PG_M);
4452 if ((prot & VM_PROT_EXECUTE) == 0)
4454 if (newpde != oldpde) {
4456 * As an optimization to future operations on this PDE, clear
4457 * PG_PROMOTED. The impending invalidation will remove any
4458 * lingering 4KB page mappings from the TLB.
4460 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4462 if ((oldpde & PG_G) != 0)
4463 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4467 return (anychanged);
4471 * Set the physical protection on the
4472 * specified range of this map as requested.
4475 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4477 vm_offset_t va_next;
4478 pml4_entry_t *pml4e;
4480 pd_entry_t ptpaddr, *pde;
4481 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4482 boolean_t anychanged;
4484 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4485 if (prot == VM_PROT_NONE) {
4486 pmap_remove(pmap, sva, eva);
4490 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4491 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4494 PG_G = pmap_global_bit(pmap);
4495 PG_M = pmap_modified_bit(pmap);
4496 PG_V = pmap_valid_bit(pmap);
4497 PG_RW = pmap_rw_bit(pmap);
4501 * Although this function delays and batches the invalidation
4502 * of stale TLB entries, it does not need to call
4503 * pmap_delayed_invl_started() and
4504 * pmap_delayed_invl_finished(), because it does not
4505 * ordinarily destroy mappings. Stale TLB entries from
4506 * protection-only changes need only be invalidated before the
4507 * pmap lock is released, because protection-only changes do
4508 * not destroy PV entries. Even operations that iterate over
4509 * a physical page's PV list of mappings, like
4510 * pmap_remove_write(), acquire the pmap lock for each
4511 * mapping. Consequently, for protection-only changes, the
4512 * pmap lock suffices to synchronize both page table and TLB
4515 * This function only destroys a mapping if pmap_demote_pde()
4516 * fails. In that case, stale TLB entries are immediately
4521 for (; sva < eva; sva = va_next) {
4523 pml4e = pmap_pml4e(pmap, sva);
4524 if ((*pml4e & PG_V) == 0) {
4525 va_next = (sva + NBPML4) & ~PML4MASK;
4531 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4532 if ((*pdpe & PG_V) == 0) {
4533 va_next = (sva + NBPDP) & ~PDPMASK;
4539 va_next = (sva + NBPDR) & ~PDRMASK;
4543 pde = pmap_pdpe_to_pde(pdpe, sva);
4547 * Weed out invalid mappings.
4553 * Check for large page.
4555 if ((ptpaddr & PG_PS) != 0) {
4557 * Are we protecting the entire large page? If not,
4558 * demote the mapping and fall through.
4560 if (sva + NBPDR == va_next && eva >= va_next) {
4562 * The TLB entry for a PG_G mapping is
4563 * invalidated by pmap_protect_pde().
4565 if (pmap_protect_pde(pmap, pde, sva, prot))
4568 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4570 * The large page mapping was destroyed.
4579 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4581 pt_entry_t obits, pbits;
4585 obits = pbits = *pte;
4586 if ((pbits & PG_V) == 0)
4589 if ((prot & VM_PROT_WRITE) == 0) {
4590 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4591 (PG_MANAGED | PG_M | PG_RW)) {
4592 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4595 pbits &= ~(PG_RW | PG_M);
4597 if ((prot & VM_PROT_EXECUTE) == 0)
4600 if (pbits != obits) {
4601 if (!atomic_cmpset_long(pte, obits, pbits))
4604 pmap_invalidate_page(pmap, sva);
4611 pmap_invalidate_all(pmap);
4615 #if VM_NRESERVLEVEL > 0
4617 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4618 * single page table page (PTP) to a single 2MB page mapping. For promotion
4619 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4620 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4621 * identical characteristics.
4624 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4625 struct rwlock **lockp)
4628 pt_entry_t *firstpte, oldpte, pa, *pte;
4629 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4633 PG_A = pmap_accessed_bit(pmap);
4634 PG_G = pmap_global_bit(pmap);
4635 PG_M = pmap_modified_bit(pmap);
4636 PG_V = pmap_valid_bit(pmap);
4637 PG_RW = pmap_rw_bit(pmap);
4638 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4640 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4643 * Examine the first PTE in the specified PTP. Abort if this PTE is
4644 * either invalid, unused, or does not map the first 4KB physical page
4645 * within a 2MB page.
4647 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4650 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4651 atomic_add_long(&pmap_pde_p_failures, 1);
4652 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4653 " in pmap %p", va, pmap);
4656 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4658 * When PG_M is already clear, PG_RW can be cleared without
4659 * a TLB invalidation.
4661 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4667 * Examine each of the other PTEs in the specified PTP. Abort if this
4668 * PTE maps an unexpected 4KB physical page or does not have identical
4669 * characteristics to the first PTE.
4671 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4672 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4675 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4676 atomic_add_long(&pmap_pde_p_failures, 1);
4677 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4678 " in pmap %p", va, pmap);
4681 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4683 * When PG_M is already clear, PG_RW can be cleared
4684 * without a TLB invalidation.
4686 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4689 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4690 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4691 (va & ~PDRMASK), pmap);
4693 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4694 atomic_add_long(&pmap_pde_p_failures, 1);
4695 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4696 " in pmap %p", va, pmap);
4703 * Save the page table page in its current state until the PDE
4704 * mapping the superpage is demoted by pmap_demote_pde() or
4705 * destroyed by pmap_remove_pde().
4707 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4708 KASSERT(mpte >= vm_page_array &&
4709 mpte < &vm_page_array[vm_page_array_size],
4710 ("pmap_promote_pde: page table page is out of range"));
4711 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4712 ("pmap_promote_pde: page table page's pindex is wrong"));
4713 if (pmap_insert_pt_page(pmap, mpte)) {
4714 atomic_add_long(&pmap_pde_p_failures, 1);
4716 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4722 * Promote the pv entries.
4724 if ((newpde & PG_MANAGED) != 0)
4725 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4728 * Propagate the PAT index to its proper position.
4730 newpde = pmap_swap_pat(pmap, newpde);
4733 * Map the superpage.
4735 if (workaround_erratum383)
4736 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4738 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4740 atomic_add_long(&pmap_pde_promotions, 1);
4741 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4742 " in pmap %p", va, pmap);
4744 #endif /* VM_NRESERVLEVEL > 0 */
4747 * Insert the given physical page (p) at
4748 * the specified virtual address (v) in the
4749 * target physical map with the protection requested.
4751 * If specified, the page will be wired down, meaning
4752 * that the related pte can not be reclaimed.
4754 * NB: This is the only routine which MAY NOT lazy-evaluate
4755 * or lose information. That is, this routine must actually
4756 * insert this page into the given map NOW.
4758 * When destroying both a page table and PV entry, this function
4759 * performs the TLB invalidation before releasing the PV list
4760 * lock, so we do not need pmap_delayed_invl_page() calls here.
4763 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4764 u_int flags, int8_t psind)
4766 struct rwlock *lock;
4768 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4769 pt_entry_t newpte, origpte;
4776 PG_A = pmap_accessed_bit(pmap);
4777 PG_G = pmap_global_bit(pmap);
4778 PG_M = pmap_modified_bit(pmap);
4779 PG_V = pmap_valid_bit(pmap);
4780 PG_RW = pmap_rw_bit(pmap);
4782 va = trunc_page(va);
4783 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4784 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4785 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4787 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4788 va >= kmi.clean_eva,
4789 ("pmap_enter: managed mapping within the clean submap"));
4790 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4791 VM_OBJECT_ASSERT_LOCKED(m->object);
4792 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
4793 ("pmap_enter: flags %u has reserved bits set", flags));
4794 pa = VM_PAGE_TO_PHYS(m);
4795 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4796 if ((flags & VM_PROT_WRITE) != 0)
4798 if ((prot & VM_PROT_WRITE) != 0)
4800 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4801 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4802 if ((prot & VM_PROT_EXECUTE) == 0)
4804 if ((flags & PMAP_ENTER_WIRED) != 0)
4806 if (va < VM_MAXUSER_ADDRESS)
4808 if (pmap == kernel_pmap)
4810 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
4813 * Set modified bit gratuitously for writeable mappings if
4814 * the page is unmanaged. We do not want to take a fault
4815 * to do the dirty bit accounting for these mappings.
4817 if ((m->oflags & VPO_UNMANAGED) != 0) {
4818 if ((newpte & PG_RW) != 0)
4821 newpte |= PG_MANAGED;
4826 /* Assert the required virtual and physical alignment. */
4827 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
4828 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4829 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
4835 * In the case that a page table page is not
4836 * resident, we are creating it here.
4839 pde = pmap_pde(pmap, va);
4840 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4841 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4842 pte = pmap_pde_to_pte(pde, va);
4843 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4844 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4847 } else if (va < VM_MAXUSER_ADDRESS) {
4849 * Here if the pte page isn't mapped, or if it has been
4852 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4853 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4854 nosleep ? NULL : &lock);
4855 if (mpte == NULL && nosleep) {
4856 rv = KERN_RESOURCE_SHORTAGE;
4861 panic("pmap_enter: invalid page directory va=%#lx", va);
4867 * Is the specified virtual address already mapped?
4869 if ((origpte & PG_V) != 0) {
4871 * Wiring change, just update stats. We don't worry about
4872 * wiring PT pages as they remain resident as long as there
4873 * are valid mappings in them. Hence, if a user page is wired,
4874 * the PT page will be also.
4876 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4877 pmap->pm_stats.wired_count++;
4878 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4879 pmap->pm_stats.wired_count--;
4882 * Remove the extra PT page reference.
4886 KASSERT(mpte->wire_count > 0,
4887 ("pmap_enter: missing reference to page table page,"
4892 * Has the physical page changed?
4894 opa = origpte & PG_FRAME;
4897 * No, might be a protection or wiring change.
4899 if ((origpte & PG_MANAGED) != 0 &&
4900 (newpte & PG_RW) != 0)
4901 vm_page_aflag_set(m, PGA_WRITEABLE);
4902 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4908 * The physical page has changed. Temporarily invalidate
4909 * the mapping. This ensures that all threads sharing the
4910 * pmap keep a consistent view of the mapping, which is
4911 * necessary for the correct handling of COW faults. It
4912 * also permits reuse of the old mapping's PV entry,
4913 * avoiding an allocation.
4915 * For consistency, handle unmanaged mappings the same way.
4917 origpte = pte_load_clear(pte);
4918 KASSERT((origpte & PG_FRAME) == opa,
4919 ("pmap_enter: unexpected pa update for %#lx", va));
4920 if ((origpte & PG_MANAGED) != 0) {
4921 om = PHYS_TO_VM_PAGE(opa);
4924 * The pmap lock is sufficient to synchronize with
4925 * concurrent calls to pmap_page_test_mappings() and
4926 * pmap_ts_referenced().
4928 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4930 if ((origpte & PG_A) != 0)
4931 vm_page_aflag_set(om, PGA_REFERENCED);
4932 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4933 pv = pmap_pvh_remove(&om->md, pmap, va);
4934 if ((newpte & PG_MANAGED) == 0)
4935 free_pv_entry(pmap, pv);
4936 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4937 TAILQ_EMPTY(&om->md.pv_list) &&
4938 ((om->flags & PG_FICTITIOUS) != 0 ||
4939 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4940 vm_page_aflag_clear(om, PGA_WRITEABLE);
4942 if ((origpte & PG_A) != 0)
4943 pmap_invalidate_page(pmap, va);
4947 * Increment the counters.
4949 if ((newpte & PG_W) != 0)
4950 pmap->pm_stats.wired_count++;
4951 pmap_resident_count_inc(pmap, 1);
4955 * Enter on the PV list if part of our managed memory.
4957 if ((newpte & PG_MANAGED) != 0) {
4959 pv = get_pv_entry(pmap, &lock);
4962 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4963 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4965 if ((newpte & PG_RW) != 0)
4966 vm_page_aflag_set(m, PGA_WRITEABLE);
4972 if ((origpte & PG_V) != 0) {
4974 origpte = pte_load_store(pte, newpte);
4975 KASSERT((origpte & PG_FRAME) == pa,
4976 ("pmap_enter: unexpected pa update for %#lx", va));
4977 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
4979 if ((origpte & PG_MANAGED) != 0)
4983 * Although the PTE may still have PG_RW set, TLB
4984 * invalidation may nonetheless be required because
4985 * the PTE no longer has PG_M set.
4987 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4989 * This PTE change does not require TLB invalidation.
4993 if ((origpte & PG_A) != 0)
4994 pmap_invalidate_page(pmap, va);
4996 pte_store(pte, newpte);
5000 #if VM_NRESERVLEVEL > 0
5002 * If both the page table page and the reservation are fully
5003 * populated, then attempt promotion.
5005 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5006 pmap_ps_enabled(pmap) &&
5007 (m->flags & PG_FICTITIOUS) == 0 &&
5008 vm_reserv_level_iffullpop(m) == 0)
5009 pmap_promote_pde(pmap, pde, va, &lock);
5021 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5022 * if successful. Returns false if (1) a page table page cannot be allocated
5023 * without sleeping, (2) a mapping already exists at the specified virtual
5024 * address, or (3) a PV entry cannot be allocated without reclaiming another
5028 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5029 struct rwlock **lockp)
5034 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5035 PG_V = pmap_valid_bit(pmap);
5036 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5038 if ((m->oflags & VPO_UNMANAGED) == 0)
5039 newpde |= PG_MANAGED;
5040 if ((prot & VM_PROT_EXECUTE) == 0)
5042 if (va < VM_MAXUSER_ADDRESS)
5044 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5045 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5050 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5051 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5052 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5053 * a mapping already exists at the specified virtual address. Returns
5054 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5055 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5056 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5058 * The parameter "m" is only used when creating a managed, writeable mapping.
5061 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5062 vm_page_t m, struct rwlock **lockp)
5064 struct spglist free;
5065 pd_entry_t oldpde, *pde;
5066 pt_entry_t PG_G, PG_RW, PG_V;
5069 PG_G = pmap_global_bit(pmap);
5070 PG_RW = pmap_rw_bit(pmap);
5071 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5072 ("pmap_enter_pde: newpde is missing PG_M"));
5073 PG_V = pmap_valid_bit(pmap);
5074 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5076 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5077 NULL : lockp)) == NULL) {
5078 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5079 " in pmap %p", va, pmap);
5080 return (KERN_RESOURCE_SHORTAGE);
5082 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5083 pde = &pde[pmap_pde_index(va)];
5085 if ((oldpde & PG_V) != 0) {
5086 KASSERT(pdpg->wire_count > 1,
5087 ("pmap_enter_pde: pdpg's wire count is too low"));
5088 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5090 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5091 " in pmap %p", va, pmap);
5092 return (KERN_FAILURE);
5094 /* Break the existing mapping(s). */
5096 if ((oldpde & PG_PS) != 0) {
5098 * The reference to the PD page that was acquired by
5099 * pmap_allocpde() ensures that it won't be freed.
5100 * However, if the PDE resulted from a promotion, then
5101 * a reserved PT page could be freed.
5103 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5104 if ((oldpde & PG_G) == 0)
5105 pmap_invalidate_pde_page(pmap, va, oldpde);
5107 pmap_delayed_invl_started();
5108 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5110 pmap_invalidate_all(pmap);
5111 pmap_delayed_invl_finished();
5113 vm_page_free_pages_toq(&free, true);
5114 if (va >= VM_MAXUSER_ADDRESS) {
5115 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5116 if (pmap_insert_pt_page(pmap, mt)) {
5118 * XXX Currently, this can't happen because
5119 * we do not perform pmap_enter(psind == 1)
5120 * on the kernel pmap.
5122 panic("pmap_enter_pde: trie insert failed");
5125 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5128 if ((newpde & PG_MANAGED) != 0) {
5130 * Abort this mapping if its PV entry could not be created.
5132 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5134 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5136 * Although "va" is not mapped, paging-
5137 * structure caches could nonetheless have
5138 * entries that refer to the freed page table
5139 * pages. Invalidate those entries.
5141 pmap_invalidate_page(pmap, va);
5142 vm_page_free_pages_toq(&free, true);
5144 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5145 " in pmap %p", va, pmap);
5146 return (KERN_RESOURCE_SHORTAGE);
5148 if ((newpde & PG_RW) != 0) {
5149 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5150 vm_page_aflag_set(mt, PGA_WRITEABLE);
5155 * Increment counters.
5157 if ((newpde & PG_W) != 0)
5158 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5159 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5162 * Map the superpage. (This is not a promoted mapping; there will not
5163 * be any lingering 4KB page mappings in the TLB.)
5165 pde_store(pde, newpde);
5167 atomic_add_long(&pmap_pde_mappings, 1);
5168 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5169 " in pmap %p", va, pmap);
5170 return (KERN_SUCCESS);
5174 * Maps a sequence of resident pages belonging to the same object.
5175 * The sequence begins with the given page m_start. This page is
5176 * mapped at the given virtual address start. Each subsequent page is
5177 * mapped at a virtual address that is offset from start by the same
5178 * amount as the page is offset from m_start within the object. The
5179 * last page in the sequence is the page with the largest offset from
5180 * m_start that can be mapped at a virtual address less than the given
5181 * virtual address end. Not every virtual page between start and end
5182 * is mapped; only those for which a resident page exists with the
5183 * corresponding offset from m_start are mapped.
5186 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5187 vm_page_t m_start, vm_prot_t prot)
5189 struct rwlock *lock;
5192 vm_pindex_t diff, psize;
5194 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5196 psize = atop(end - start);
5201 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5202 va = start + ptoa(diff);
5203 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5204 m->psind == 1 && pmap_ps_enabled(pmap) &&
5205 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5206 m = &m[NBPDR / PAGE_SIZE - 1];
5208 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5210 m = TAILQ_NEXT(m, listq);
5218 * this code makes some *MAJOR* assumptions:
5219 * 1. Current pmap & pmap exists.
5222 * 4. No page table pages.
5223 * but is *MUCH* faster than pmap_enter...
5227 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5229 struct rwlock *lock;
5233 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5240 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5241 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5243 struct spglist free;
5244 pt_entry_t *pte, PG_V;
5247 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5248 (m->oflags & VPO_UNMANAGED) != 0,
5249 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5250 PG_V = pmap_valid_bit(pmap);
5251 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5254 * In the case that a page table page is not
5255 * resident, we are creating it here.
5257 if (va < VM_MAXUSER_ADDRESS) {
5258 vm_pindex_t ptepindex;
5262 * Calculate pagetable page index
5264 ptepindex = pmap_pde_pindex(va);
5265 if (mpte && (mpte->pindex == ptepindex)) {
5269 * Get the page directory entry
5271 ptepa = pmap_pde(pmap, va);
5274 * If the page table page is mapped, we just increment
5275 * the hold count, and activate it. Otherwise, we
5276 * attempt to allocate a page table page. If this
5277 * attempt fails, we don't retry. Instead, we give up.
5279 if (ptepa && (*ptepa & PG_V) != 0) {
5282 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5286 * Pass NULL instead of the PV list lock
5287 * pointer, because we don't intend to sleep.
5289 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5294 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5295 pte = &pte[pmap_pte_index(va)];
5309 * Enter on the PV list if part of our managed memory.
5311 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5312 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5315 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5317 * Although "va" is not mapped, paging-
5318 * structure caches could nonetheless have
5319 * entries that refer to the freed page table
5320 * pages. Invalidate those entries.
5322 pmap_invalidate_page(pmap, va);
5323 vm_page_free_pages_toq(&free, true);
5331 * Increment counters
5333 pmap_resident_count_inc(pmap, 1);
5335 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
5336 if ((prot & VM_PROT_EXECUTE) == 0)
5340 * Now validate mapping with RO protection
5342 if ((m->oflags & VPO_UNMANAGED) != 0)
5343 pte_store(pte, pa | PG_V | PG_U);
5345 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
5350 * Make a temporary mapping for a physical address. This is only intended
5351 * to be used for panic dumps.
5354 pmap_kenter_temporary(vm_paddr_t pa, int i)
5358 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5359 pmap_kenter(va, pa);
5361 return ((void *)crashdumpmap);
5365 * This code maps large physical mmap regions into the
5366 * processor address space. Note that some shortcuts
5367 * are taken, but the code works.
5370 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5371 vm_pindex_t pindex, vm_size_t size)
5374 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5375 vm_paddr_t pa, ptepa;
5379 PG_A = pmap_accessed_bit(pmap);
5380 PG_M = pmap_modified_bit(pmap);
5381 PG_V = pmap_valid_bit(pmap);
5382 PG_RW = pmap_rw_bit(pmap);
5384 VM_OBJECT_ASSERT_WLOCKED(object);
5385 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5386 ("pmap_object_init_pt: non-device object"));
5387 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5388 if (!pmap_ps_enabled(pmap))
5390 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5392 p = vm_page_lookup(object, pindex);
5393 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5394 ("pmap_object_init_pt: invalid page %p", p));
5395 pat_mode = p->md.pat_mode;
5398 * Abort the mapping if the first page is not physically
5399 * aligned to a 2MB page boundary.
5401 ptepa = VM_PAGE_TO_PHYS(p);
5402 if (ptepa & (NBPDR - 1))
5406 * Skip the first page. Abort the mapping if the rest of
5407 * the pages are not physically contiguous or have differing
5408 * memory attributes.
5410 p = TAILQ_NEXT(p, listq);
5411 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5413 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5414 ("pmap_object_init_pt: invalid page %p", p));
5415 if (pa != VM_PAGE_TO_PHYS(p) ||
5416 pat_mode != p->md.pat_mode)
5418 p = TAILQ_NEXT(p, listq);
5422 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5423 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5424 * will not affect the termination of this loop.
5427 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5428 pa < ptepa + size; pa += NBPDR) {
5429 pdpg = pmap_allocpde(pmap, addr, NULL);
5432 * The creation of mappings below is only an
5433 * optimization. If a page directory page
5434 * cannot be allocated without blocking,
5435 * continue on to the next mapping rather than
5441 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5442 pde = &pde[pmap_pde_index(addr)];
5443 if ((*pde & PG_V) == 0) {
5444 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5445 PG_U | PG_RW | PG_V);
5446 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5447 atomic_add_long(&pmap_pde_mappings, 1);
5449 /* Continue on if the PDE is already valid. */
5451 KASSERT(pdpg->wire_count > 0,
5452 ("pmap_object_init_pt: missing reference "
5453 "to page directory page, va: 0x%lx", addr));
5462 * Clear the wired attribute from the mappings for the specified range of
5463 * addresses in the given pmap. Every valid mapping within that range
5464 * must have the wired attribute set. In contrast, invalid mappings
5465 * cannot have the wired attribute set, so they are ignored.
5467 * The wired attribute of the page table entry is not a hardware
5468 * feature, so there is no need to invalidate any TLB entries.
5469 * Since pmap_demote_pde() for the wired entry must never fail,
5470 * pmap_delayed_invl_started()/finished() calls around the
5471 * function are not needed.
5474 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5476 vm_offset_t va_next;
5477 pml4_entry_t *pml4e;
5480 pt_entry_t *pte, PG_V;
5482 PG_V = pmap_valid_bit(pmap);
5484 for (; sva < eva; sva = va_next) {
5485 pml4e = pmap_pml4e(pmap, sva);
5486 if ((*pml4e & PG_V) == 0) {
5487 va_next = (sva + NBPML4) & ~PML4MASK;
5492 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5493 if ((*pdpe & PG_V) == 0) {
5494 va_next = (sva + NBPDP) & ~PDPMASK;
5499 va_next = (sva + NBPDR) & ~PDRMASK;
5502 pde = pmap_pdpe_to_pde(pdpe, sva);
5503 if ((*pde & PG_V) == 0)
5505 if ((*pde & PG_PS) != 0) {
5506 if ((*pde & PG_W) == 0)
5507 panic("pmap_unwire: pde %#jx is missing PG_W",
5511 * Are we unwiring the entire large page? If not,
5512 * demote the mapping and fall through.
5514 if (sva + NBPDR == va_next && eva >= va_next) {
5515 atomic_clear_long(pde, PG_W);
5516 pmap->pm_stats.wired_count -= NBPDR /
5519 } else if (!pmap_demote_pde(pmap, pde, sva))
5520 panic("pmap_unwire: demotion failed");
5524 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5526 if ((*pte & PG_V) == 0)
5528 if ((*pte & PG_W) == 0)
5529 panic("pmap_unwire: pte %#jx is missing PG_W",
5533 * PG_W must be cleared atomically. Although the pmap
5534 * lock synchronizes access to PG_W, another processor
5535 * could be setting PG_M and/or PG_A concurrently.
5537 atomic_clear_long(pte, PG_W);
5538 pmap->pm_stats.wired_count--;
5545 * Copy the range specified by src_addr/len
5546 * from the source map to the range dst_addr/len
5547 * in the destination map.
5549 * This routine is only advisory and need not do anything.
5553 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5554 vm_offset_t src_addr)
5556 struct rwlock *lock;
5557 struct spglist free;
5559 vm_offset_t end_addr = src_addr + len;
5560 vm_offset_t va_next;
5561 vm_page_t dst_pdpg, dstmpte, srcmpte;
5562 pt_entry_t PG_A, PG_M, PG_V;
5564 if (dst_addr != src_addr)
5567 if (dst_pmap->pm_type != src_pmap->pm_type)
5571 * EPT page table entries that require emulation of A/D bits are
5572 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5573 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5574 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5575 * implementations flag an EPT misconfiguration for exec-only
5576 * mappings we skip this function entirely for emulated pmaps.
5578 if (pmap_emulate_ad_bits(dst_pmap))
5582 if (dst_pmap < src_pmap) {
5583 PMAP_LOCK(dst_pmap);
5584 PMAP_LOCK(src_pmap);
5586 PMAP_LOCK(src_pmap);
5587 PMAP_LOCK(dst_pmap);
5590 PG_A = pmap_accessed_bit(dst_pmap);
5591 PG_M = pmap_modified_bit(dst_pmap);
5592 PG_V = pmap_valid_bit(dst_pmap);
5594 for (addr = src_addr; addr < end_addr; addr = va_next) {
5595 pt_entry_t *src_pte, *dst_pte;
5596 pml4_entry_t *pml4e;
5598 pd_entry_t srcptepaddr, *pde;
5600 KASSERT(addr < UPT_MIN_ADDRESS,
5601 ("pmap_copy: invalid to pmap_copy page tables"));
5603 pml4e = pmap_pml4e(src_pmap, addr);
5604 if ((*pml4e & PG_V) == 0) {
5605 va_next = (addr + NBPML4) & ~PML4MASK;
5611 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5612 if ((*pdpe & PG_V) == 0) {
5613 va_next = (addr + NBPDP) & ~PDPMASK;
5619 va_next = (addr + NBPDR) & ~PDRMASK;
5623 pde = pmap_pdpe_to_pde(pdpe, addr);
5625 if (srcptepaddr == 0)
5628 if (srcptepaddr & PG_PS) {
5629 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5631 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5632 if (dst_pdpg == NULL)
5634 pde = (pd_entry_t *)
5635 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5636 pde = &pde[pmap_pde_index(addr)];
5637 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5638 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5639 PMAP_ENTER_NORECLAIM, &lock))) {
5640 *pde = srcptepaddr & ~PG_W;
5641 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5642 atomic_add_long(&pmap_pde_mappings, 1);
5644 dst_pdpg->wire_count--;
5648 srcptepaddr &= PG_FRAME;
5649 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5650 KASSERT(srcmpte->wire_count > 0,
5651 ("pmap_copy: source page table page is unused"));
5653 if (va_next > end_addr)
5656 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5657 src_pte = &src_pte[pmap_pte_index(addr)];
5659 while (addr < va_next) {
5663 * we only virtual copy managed pages
5665 if ((ptetemp & PG_MANAGED) != 0) {
5666 if (dstmpte != NULL &&
5667 dstmpte->pindex == pmap_pde_pindex(addr))
5668 dstmpte->wire_count++;
5669 else if ((dstmpte = pmap_allocpte(dst_pmap,
5670 addr, NULL)) == NULL)
5672 dst_pte = (pt_entry_t *)
5673 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5674 dst_pte = &dst_pte[pmap_pte_index(addr)];
5675 if (*dst_pte == 0 &&
5676 pmap_try_insert_pv_entry(dst_pmap, addr,
5677 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5680 * Clear the wired, modified, and
5681 * accessed (referenced) bits
5684 *dst_pte = ptetemp & ~(PG_W | PG_M |
5686 pmap_resident_count_inc(dst_pmap, 1);
5689 if (pmap_unwire_ptp(dst_pmap, addr,
5692 * Although "addr" is not
5693 * mapped, paging-structure
5694 * caches could nonetheless
5695 * have entries that refer to
5696 * the freed page table pages.
5697 * Invalidate those entries.
5699 pmap_invalidate_page(dst_pmap,
5701 vm_page_free_pages_toq(&free,
5706 if (dstmpte->wire_count >= srcmpte->wire_count)
5716 PMAP_UNLOCK(src_pmap);
5717 PMAP_UNLOCK(dst_pmap);
5721 * Zero the specified hardware page.
5724 pmap_zero_page(vm_page_t m)
5726 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5728 pagezero((void *)va);
5732 * Zero an an area within a single hardware page. off and size must not
5733 * cover an area beyond a single hardware page.
5736 pmap_zero_page_area(vm_page_t m, int off, int size)
5738 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5740 if (off == 0 && size == PAGE_SIZE)
5741 pagezero((void *)va);
5743 bzero((char *)va + off, size);
5747 * Copy 1 specified hardware page to another.
5750 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5752 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5753 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5755 pagecopy((void *)src, (void *)dst);
5758 int unmapped_buf_allowed = 1;
5761 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5762 vm_offset_t b_offset, int xfersize)
5766 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5770 while (xfersize > 0) {
5771 a_pg_offset = a_offset & PAGE_MASK;
5772 pages[0] = ma[a_offset >> PAGE_SHIFT];
5773 b_pg_offset = b_offset & PAGE_MASK;
5774 pages[1] = mb[b_offset >> PAGE_SHIFT];
5775 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5776 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5777 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5778 a_cp = (char *)vaddr[0] + a_pg_offset;
5779 b_cp = (char *)vaddr[1] + b_pg_offset;
5780 bcopy(a_cp, b_cp, cnt);
5781 if (__predict_false(mapped))
5782 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5790 * Returns true if the pmap's pv is one of the first
5791 * 16 pvs linked to from this page. This count may
5792 * be changed upwards or downwards in the future; it
5793 * is only necessary that true be returned for a small
5794 * subset of pmaps for proper page aging.
5797 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5799 struct md_page *pvh;
5800 struct rwlock *lock;
5805 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5806 ("pmap_page_exists_quick: page %p is not managed", m));
5808 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5810 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5811 if (PV_PMAP(pv) == pmap) {
5819 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5820 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5821 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5822 if (PV_PMAP(pv) == pmap) {
5836 * pmap_page_wired_mappings:
5838 * Return the number of managed mappings to the given physical page
5842 pmap_page_wired_mappings(vm_page_t m)
5844 struct rwlock *lock;
5845 struct md_page *pvh;
5849 int count, md_gen, pvh_gen;
5851 if ((m->oflags & VPO_UNMANAGED) != 0)
5853 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5857 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5859 if (!PMAP_TRYLOCK(pmap)) {
5860 md_gen = m->md.pv_gen;
5864 if (md_gen != m->md.pv_gen) {
5869 pte = pmap_pte(pmap, pv->pv_va);
5870 if ((*pte & PG_W) != 0)
5874 if ((m->flags & PG_FICTITIOUS) == 0) {
5875 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5876 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5878 if (!PMAP_TRYLOCK(pmap)) {
5879 md_gen = m->md.pv_gen;
5880 pvh_gen = pvh->pv_gen;
5884 if (md_gen != m->md.pv_gen ||
5885 pvh_gen != pvh->pv_gen) {
5890 pte = pmap_pde(pmap, pv->pv_va);
5891 if ((*pte & PG_W) != 0)
5901 * Returns TRUE if the given page is mapped individually or as part of
5902 * a 2mpage. Otherwise, returns FALSE.
5905 pmap_page_is_mapped(vm_page_t m)
5907 struct rwlock *lock;
5910 if ((m->oflags & VPO_UNMANAGED) != 0)
5912 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5914 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5915 ((m->flags & PG_FICTITIOUS) == 0 &&
5916 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5922 * Destroy all managed, non-wired mappings in the given user-space
5923 * pmap. This pmap cannot be active on any processor besides the
5926 * This function cannot be applied to the kernel pmap. Moreover, it
5927 * is not intended for general use. It is only to be used during
5928 * process termination. Consequently, it can be implemented in ways
5929 * that make it faster than pmap_remove(). First, it can more quickly
5930 * destroy mappings by iterating over the pmap's collection of PV
5931 * entries, rather than searching the page table. Second, it doesn't
5932 * have to test and clear the page table entries atomically, because
5933 * no processor is currently accessing the user address space. In
5934 * particular, a page table entry's dirty bit won't change state once
5935 * this function starts.
5937 * Although this function destroys all of the pmap's managed,
5938 * non-wired mappings, it can delay and batch the invalidation of TLB
5939 * entries without calling pmap_delayed_invl_started() and
5940 * pmap_delayed_invl_finished(). Because the pmap is not active on
5941 * any other processor, none of these TLB entries will ever be used
5942 * before their eventual invalidation. Consequently, there is no need
5943 * for either pmap_remove_all() or pmap_remove_write() to wait for
5944 * that eventual TLB invalidation.
5947 pmap_remove_pages(pmap_t pmap)
5950 pt_entry_t *pte, tpte;
5951 pt_entry_t PG_M, PG_RW, PG_V;
5952 struct spglist free;
5953 vm_page_t m, mpte, mt;
5955 struct md_page *pvh;
5956 struct pv_chunk *pc, *npc;
5957 struct rwlock *lock;
5959 uint64_t inuse, bitmask;
5960 int allfree, field, freed, idx;
5961 boolean_t superpage;
5965 * Assert that the given pmap is only active on the current
5966 * CPU. Unfortunately, we cannot block another CPU from
5967 * activating the pmap while this function is executing.
5969 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5972 cpuset_t other_cpus;
5974 other_cpus = all_cpus;
5976 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5977 CPU_AND(&other_cpus, &pmap->pm_active);
5979 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5984 PG_M = pmap_modified_bit(pmap);
5985 PG_V = pmap_valid_bit(pmap);
5986 PG_RW = pmap_rw_bit(pmap);
5990 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5993 for (field = 0; field < _NPCM; field++) {
5994 inuse = ~pc->pc_map[field] & pc_freemask[field];
5995 while (inuse != 0) {
5997 bitmask = 1UL << bit;
5998 idx = field * 64 + bit;
5999 pv = &pc->pc_pventry[idx];
6002 pte = pmap_pdpe(pmap, pv->pv_va);
6004 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6006 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6009 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6011 pte = &pte[pmap_pte_index(pv->pv_va)];
6015 * Keep track whether 'tpte' is a
6016 * superpage explicitly instead of
6017 * relying on PG_PS being set.
6019 * This is because PG_PS is numerically
6020 * identical to PG_PTE_PAT and thus a
6021 * regular page could be mistaken for
6027 if ((tpte & PG_V) == 0) {
6028 panic("bad pte va %lx pte %lx",
6033 * We cannot remove wired pages from a process' mapping at this time
6041 pa = tpte & PG_PS_FRAME;
6043 pa = tpte & PG_FRAME;
6045 m = PHYS_TO_VM_PAGE(pa);
6046 KASSERT(m->phys_addr == pa,
6047 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6048 m, (uintmax_t)m->phys_addr,
6051 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6052 m < &vm_page_array[vm_page_array_size],
6053 ("pmap_remove_pages: bad tpte %#jx",
6059 * Update the vm_page_t clean/reference bits.
6061 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6063 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6069 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6072 pc->pc_map[field] |= bitmask;
6074 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6075 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6076 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6078 if (TAILQ_EMPTY(&pvh->pv_list)) {
6079 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6080 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6081 TAILQ_EMPTY(&mt->md.pv_list))
6082 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6084 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6086 pmap_resident_count_dec(pmap, 1);
6087 KASSERT(mpte->wire_count == NPTEPG,
6088 ("pmap_remove_pages: pte page wire count error"));
6089 mpte->wire_count = 0;
6090 pmap_add_delayed_free_list(mpte, &free, FALSE);
6093 pmap_resident_count_dec(pmap, 1);
6094 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6096 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6097 TAILQ_EMPTY(&m->md.pv_list) &&
6098 (m->flags & PG_FICTITIOUS) == 0) {
6099 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6100 if (TAILQ_EMPTY(&pvh->pv_list))
6101 vm_page_aflag_clear(m, PGA_WRITEABLE);
6104 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6108 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6109 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6110 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6112 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6118 pmap_invalidate_all(pmap);
6120 vm_page_free_pages_toq(&free, true);
6124 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6126 struct rwlock *lock;
6128 struct md_page *pvh;
6129 pt_entry_t *pte, mask;
6130 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6132 int md_gen, pvh_gen;
6136 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6139 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6141 if (!PMAP_TRYLOCK(pmap)) {
6142 md_gen = m->md.pv_gen;
6146 if (md_gen != m->md.pv_gen) {
6151 pte = pmap_pte(pmap, pv->pv_va);
6154 PG_M = pmap_modified_bit(pmap);
6155 PG_RW = pmap_rw_bit(pmap);
6156 mask |= PG_RW | PG_M;
6159 PG_A = pmap_accessed_bit(pmap);
6160 PG_V = pmap_valid_bit(pmap);
6161 mask |= PG_V | PG_A;
6163 rv = (*pte & mask) == mask;
6168 if ((m->flags & PG_FICTITIOUS) == 0) {
6169 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6170 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6172 if (!PMAP_TRYLOCK(pmap)) {
6173 md_gen = m->md.pv_gen;
6174 pvh_gen = pvh->pv_gen;
6178 if (md_gen != m->md.pv_gen ||
6179 pvh_gen != pvh->pv_gen) {
6184 pte = pmap_pde(pmap, pv->pv_va);
6187 PG_M = pmap_modified_bit(pmap);
6188 PG_RW = pmap_rw_bit(pmap);
6189 mask |= PG_RW | PG_M;
6192 PG_A = pmap_accessed_bit(pmap);
6193 PG_V = pmap_valid_bit(pmap);
6194 mask |= PG_V | PG_A;
6196 rv = (*pte & mask) == mask;
6210 * Return whether or not the specified physical page was modified
6211 * in any physical maps.
6214 pmap_is_modified(vm_page_t m)
6217 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6218 ("pmap_is_modified: page %p is not managed", m));
6221 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6222 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6223 * is clear, no PTEs can have PG_M set.
6225 VM_OBJECT_ASSERT_WLOCKED(m->object);
6226 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6228 return (pmap_page_test_mappings(m, FALSE, TRUE));
6232 * pmap_is_prefaultable:
6234 * Return whether or not the specified virtual address is eligible
6238 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6241 pt_entry_t *pte, PG_V;
6244 PG_V = pmap_valid_bit(pmap);
6247 pde = pmap_pde(pmap, addr);
6248 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6249 pte = pmap_pde_to_pte(pde, addr);
6250 rv = (*pte & PG_V) == 0;
6257 * pmap_is_referenced:
6259 * Return whether or not the specified physical page was referenced
6260 * in any physical maps.
6263 pmap_is_referenced(vm_page_t m)
6266 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6267 ("pmap_is_referenced: page %p is not managed", m));
6268 return (pmap_page_test_mappings(m, TRUE, FALSE));
6272 * Clear the write and modified bits in each of the given page's mappings.
6275 pmap_remove_write(vm_page_t m)
6277 struct md_page *pvh;
6279 struct rwlock *lock;
6280 pv_entry_t next_pv, pv;
6282 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6284 int pvh_gen, md_gen;
6286 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6287 ("pmap_remove_write: page %p is not managed", m));
6290 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6291 * set by another thread while the object is locked. Thus,
6292 * if PGA_WRITEABLE is clear, no page table entries need updating.
6294 VM_OBJECT_ASSERT_WLOCKED(m->object);
6295 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6297 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6298 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6299 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6302 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6304 if (!PMAP_TRYLOCK(pmap)) {
6305 pvh_gen = pvh->pv_gen;
6309 if (pvh_gen != pvh->pv_gen) {
6315 PG_RW = pmap_rw_bit(pmap);
6317 pde = pmap_pde(pmap, va);
6318 if ((*pde & PG_RW) != 0)
6319 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6320 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6321 ("inconsistent pv lock %p %p for page %p",
6322 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6325 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6327 if (!PMAP_TRYLOCK(pmap)) {
6328 pvh_gen = pvh->pv_gen;
6329 md_gen = m->md.pv_gen;
6333 if (pvh_gen != pvh->pv_gen ||
6334 md_gen != m->md.pv_gen) {
6340 PG_M = pmap_modified_bit(pmap);
6341 PG_RW = pmap_rw_bit(pmap);
6342 pde = pmap_pde(pmap, pv->pv_va);
6343 KASSERT((*pde & PG_PS) == 0,
6344 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6346 pte = pmap_pde_to_pte(pde, pv->pv_va);
6349 if (oldpte & PG_RW) {
6350 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6353 if ((oldpte & PG_M) != 0)
6355 pmap_invalidate_page(pmap, pv->pv_va);
6360 vm_page_aflag_clear(m, PGA_WRITEABLE);
6361 pmap_delayed_invl_wait(m);
6364 static __inline boolean_t
6365 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6368 if (!pmap_emulate_ad_bits(pmap))
6371 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6374 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6375 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6376 * if the EPT_PG_WRITE bit is set.
6378 if ((pte & EPT_PG_WRITE) != 0)
6382 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6384 if ((pte & EPT_PG_EXECUTE) == 0 ||
6385 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6392 * pmap_ts_referenced:
6394 * Return a count of reference bits for a page, clearing those bits.
6395 * It is not necessary for every reference bit to be cleared, but it
6396 * is necessary that 0 only be returned when there are truly no
6397 * reference bits set.
6399 * As an optimization, update the page's dirty field if a modified bit is
6400 * found while counting reference bits. This opportunistic update can be
6401 * performed at low cost and can eliminate the need for some future calls
6402 * to pmap_is_modified(). However, since this function stops after
6403 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6404 * dirty pages. Those dirty pages will only be detected by a future call
6405 * to pmap_is_modified().
6407 * A DI block is not needed within this function, because
6408 * invalidations are performed before the PV list lock is
6412 pmap_ts_referenced(vm_page_t m)
6414 struct md_page *pvh;
6417 struct rwlock *lock;
6418 pd_entry_t oldpde, *pde;
6419 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6422 int cleared, md_gen, not_cleared, pvh_gen;
6423 struct spglist free;
6426 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6427 ("pmap_ts_referenced: page %p is not managed", m));
6430 pa = VM_PAGE_TO_PHYS(m);
6431 lock = PHYS_TO_PV_LIST_LOCK(pa);
6432 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6436 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6437 goto small_mappings;
6443 if (!PMAP_TRYLOCK(pmap)) {
6444 pvh_gen = pvh->pv_gen;
6448 if (pvh_gen != pvh->pv_gen) {
6453 PG_A = pmap_accessed_bit(pmap);
6454 PG_M = pmap_modified_bit(pmap);
6455 PG_RW = pmap_rw_bit(pmap);
6457 pde = pmap_pde(pmap, pv->pv_va);
6459 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6461 * Although "oldpde" is mapping a 2MB page, because
6462 * this function is called at a 4KB page granularity,
6463 * we only update the 4KB page under test.
6467 if ((oldpde & PG_A) != 0) {
6469 * Since this reference bit is shared by 512 4KB
6470 * pages, it should not be cleared every time it is
6471 * tested. Apply a simple "hash" function on the
6472 * physical page number, the virtual superpage number,
6473 * and the pmap address to select one 4KB page out of
6474 * the 512 on which testing the reference bit will
6475 * result in clearing that reference bit. This
6476 * function is designed to avoid the selection of the
6477 * same 4KB page for every 2MB page mapping.
6479 * On demotion, a mapping that hasn't been referenced
6480 * is simply destroyed. To avoid the possibility of a
6481 * subsequent page fault on a demoted wired mapping,
6482 * always leave its reference bit set. Moreover,
6483 * since the superpage is wired, the current state of
6484 * its reference bit won't affect page replacement.
6486 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6487 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6488 (oldpde & PG_W) == 0) {
6489 if (safe_to_clear_referenced(pmap, oldpde)) {
6490 atomic_clear_long(pde, PG_A);
6491 pmap_invalidate_page(pmap, pv->pv_va);
6493 } else if (pmap_demote_pde_locked(pmap, pde,
6494 pv->pv_va, &lock)) {
6496 * Remove the mapping to a single page
6497 * so that a subsequent access may
6498 * repromote. Since the underlying
6499 * page table page is fully populated,
6500 * this removal never frees a page
6504 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6506 pte = pmap_pde_to_pte(pde, va);
6507 pmap_remove_pte(pmap, pte, va, *pde,
6509 pmap_invalidate_page(pmap, va);
6515 * The superpage mapping was removed
6516 * entirely and therefore 'pv' is no
6524 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6525 ("inconsistent pv lock %p %p for page %p",
6526 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6531 /* Rotate the PV list if it has more than one entry. */
6532 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6533 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6534 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6537 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6539 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6541 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6548 if (!PMAP_TRYLOCK(pmap)) {
6549 pvh_gen = pvh->pv_gen;
6550 md_gen = m->md.pv_gen;
6554 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6559 PG_A = pmap_accessed_bit(pmap);
6560 PG_M = pmap_modified_bit(pmap);
6561 PG_RW = pmap_rw_bit(pmap);
6562 pde = pmap_pde(pmap, pv->pv_va);
6563 KASSERT((*pde & PG_PS) == 0,
6564 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6566 pte = pmap_pde_to_pte(pde, pv->pv_va);
6567 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6569 if ((*pte & PG_A) != 0) {
6570 if (safe_to_clear_referenced(pmap, *pte)) {
6571 atomic_clear_long(pte, PG_A);
6572 pmap_invalidate_page(pmap, pv->pv_va);
6574 } else if ((*pte & PG_W) == 0) {
6576 * Wired pages cannot be paged out so
6577 * doing accessed bit emulation for
6578 * them is wasted effort. We do the
6579 * hard work for unwired pages only.
6581 pmap_remove_pte(pmap, pte, pv->pv_va,
6582 *pde, &free, &lock);
6583 pmap_invalidate_page(pmap, pv->pv_va);
6588 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6589 ("inconsistent pv lock %p %p for page %p",
6590 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6595 /* Rotate the PV list if it has more than one entry. */
6596 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6597 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6598 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6601 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6602 not_cleared < PMAP_TS_REFERENCED_MAX);
6605 vm_page_free_pages_toq(&free, true);
6606 return (cleared + not_cleared);
6610 * Apply the given advice to the specified range of addresses within the
6611 * given pmap. Depending on the advice, clear the referenced and/or
6612 * modified flags in each mapping and set the mapped page's dirty field.
6615 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6617 struct rwlock *lock;
6618 pml4_entry_t *pml4e;
6620 pd_entry_t oldpde, *pde;
6621 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6622 vm_offset_t va, va_next;
6624 boolean_t anychanged;
6626 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6630 * A/D bit emulation requires an alternate code path when clearing
6631 * the modified and accessed bits below. Since this function is
6632 * advisory in nature we skip it entirely for pmaps that require
6633 * A/D bit emulation.
6635 if (pmap_emulate_ad_bits(pmap))
6638 PG_A = pmap_accessed_bit(pmap);
6639 PG_G = pmap_global_bit(pmap);
6640 PG_M = pmap_modified_bit(pmap);
6641 PG_V = pmap_valid_bit(pmap);
6642 PG_RW = pmap_rw_bit(pmap);
6644 pmap_delayed_invl_started();
6646 for (; sva < eva; sva = va_next) {
6647 pml4e = pmap_pml4e(pmap, sva);
6648 if ((*pml4e & PG_V) == 0) {
6649 va_next = (sva + NBPML4) & ~PML4MASK;
6654 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6655 if ((*pdpe & PG_V) == 0) {
6656 va_next = (sva + NBPDP) & ~PDPMASK;
6661 va_next = (sva + NBPDR) & ~PDRMASK;
6664 pde = pmap_pdpe_to_pde(pdpe, sva);
6666 if ((oldpde & PG_V) == 0)
6668 else if ((oldpde & PG_PS) != 0) {
6669 if ((oldpde & PG_MANAGED) == 0)
6672 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6677 * The large page mapping was destroyed.
6683 * Unless the page mappings are wired, remove the
6684 * mapping to a single page so that a subsequent
6685 * access may repromote. Since the underlying page
6686 * table page is fully populated, this removal never
6687 * frees a page table page.
6689 if ((oldpde & PG_W) == 0) {
6690 pte = pmap_pde_to_pte(pde, sva);
6691 KASSERT((*pte & PG_V) != 0,
6692 ("pmap_advise: invalid PTE"));
6693 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6703 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6705 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6707 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6708 if (advice == MADV_DONTNEED) {
6710 * Future calls to pmap_is_modified()
6711 * can be avoided by making the page
6714 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6717 atomic_clear_long(pte, PG_M | PG_A);
6718 } else if ((*pte & PG_A) != 0)
6719 atomic_clear_long(pte, PG_A);
6723 if ((*pte & PG_G) != 0) {
6730 if (va != va_next) {
6731 pmap_invalidate_range(pmap, va, sva);
6736 pmap_invalidate_range(pmap, va, sva);
6739 pmap_invalidate_all(pmap);
6741 pmap_delayed_invl_finished();
6745 * Clear the modify bits on the specified physical page.
6748 pmap_clear_modify(vm_page_t m)
6750 struct md_page *pvh;
6752 pv_entry_t next_pv, pv;
6753 pd_entry_t oldpde, *pde;
6754 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6755 struct rwlock *lock;
6757 int md_gen, pvh_gen;
6759 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6760 ("pmap_clear_modify: page %p is not managed", m));
6761 VM_OBJECT_ASSERT_WLOCKED(m->object);
6762 KASSERT(!vm_page_xbusied(m),
6763 ("pmap_clear_modify: page %p is exclusive busied", m));
6766 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6767 * If the object containing the page is locked and the page is not
6768 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6770 if ((m->aflags & PGA_WRITEABLE) == 0)
6772 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6773 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6774 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6777 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6779 if (!PMAP_TRYLOCK(pmap)) {
6780 pvh_gen = pvh->pv_gen;
6784 if (pvh_gen != pvh->pv_gen) {
6789 PG_M = pmap_modified_bit(pmap);
6790 PG_V = pmap_valid_bit(pmap);
6791 PG_RW = pmap_rw_bit(pmap);
6793 pde = pmap_pde(pmap, va);
6795 if ((oldpde & PG_RW) != 0) {
6796 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6797 if ((oldpde & PG_W) == 0) {
6799 * Write protect the mapping to a
6800 * single page so that a subsequent
6801 * write access may repromote.
6803 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6805 pte = pmap_pde_to_pte(pde, va);
6807 if ((oldpte & PG_V) != 0) {
6808 while (!atomic_cmpset_long(pte,
6810 oldpte & ~(PG_M | PG_RW)))
6813 pmap_invalidate_page(pmap, va);
6820 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6822 if (!PMAP_TRYLOCK(pmap)) {
6823 md_gen = m->md.pv_gen;
6824 pvh_gen = pvh->pv_gen;
6828 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6833 PG_M = pmap_modified_bit(pmap);
6834 PG_RW = pmap_rw_bit(pmap);
6835 pde = pmap_pde(pmap, pv->pv_va);
6836 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6837 " a 2mpage in page %p's pv list", m));
6838 pte = pmap_pde_to_pte(pde, pv->pv_va);
6839 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6840 atomic_clear_long(pte, PG_M);
6841 pmap_invalidate_page(pmap, pv->pv_va);
6849 * Miscellaneous support routines follow
6852 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6853 static __inline void
6854 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6859 * The cache mode bits are all in the low 32-bits of the
6860 * PTE, so we can just spin on updating the low 32-bits.
6863 opte = *(u_int *)pte;
6864 npte = opte & ~mask;
6866 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6869 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6870 static __inline void
6871 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6876 * The cache mode bits are all in the low 32-bits of the
6877 * PDE, so we can just spin on updating the low 32-bits.
6880 opde = *(u_int *)pde;
6881 npde = opde & ~mask;
6883 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6887 * Map a set of physical memory pages into the kernel virtual
6888 * address space. Return a pointer to where it is mapped. This
6889 * routine is intended to be used for mapping device memory,
6893 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6895 struct pmap_preinit_mapping *ppim;
6896 vm_offset_t va, offset;
6900 offset = pa & PAGE_MASK;
6901 size = round_page(offset + size);
6902 pa = trunc_page(pa);
6904 if (!pmap_initialized) {
6906 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6907 ppim = pmap_preinit_mapping + i;
6908 if (ppim->va == 0) {
6912 ppim->va = virtual_avail;
6913 virtual_avail += size;
6919 panic("%s: too many preinit mappings", __func__);
6922 * If we have a preinit mapping, re-use it.
6924 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6925 ppim = pmap_preinit_mapping + i;
6926 if (ppim->pa == pa && ppim->sz == size &&
6928 return ((void *)(ppim->va + offset));
6931 * If the specified range of physical addresses fits within
6932 * the direct map window, use the direct map.
6934 if (pa < dmaplimit && pa + size < dmaplimit) {
6935 va = PHYS_TO_DMAP(pa);
6936 if (!pmap_change_attr(va, size, mode))
6937 return ((void *)(va + offset));
6939 va = kva_alloc(size);
6941 panic("%s: Couldn't allocate KVA", __func__);
6943 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6944 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6945 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6946 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6947 return ((void *)(va + offset));
6951 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6954 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6958 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6961 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6965 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6967 struct pmap_preinit_mapping *ppim;
6971 /* If we gave a direct map region in pmap_mapdev, do nothing */
6972 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6974 offset = va & PAGE_MASK;
6975 size = round_page(offset + size);
6976 va = trunc_page(va);
6977 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6978 ppim = pmap_preinit_mapping + i;
6979 if (ppim->va == va && ppim->sz == size) {
6980 if (pmap_initialized)
6986 if (va + size == virtual_avail)
6991 if (pmap_initialized)
6996 * Tries to demote a 1GB page mapping.
6999 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7001 pdp_entry_t newpdpe, oldpdpe;
7002 pd_entry_t *firstpde, newpde, *pde;
7003 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7007 PG_A = pmap_accessed_bit(pmap);
7008 PG_M = pmap_modified_bit(pmap);
7009 PG_V = pmap_valid_bit(pmap);
7010 PG_RW = pmap_rw_bit(pmap);
7012 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7014 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7015 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7016 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7017 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7018 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7019 " in pmap %p", va, pmap);
7022 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7023 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7024 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7025 KASSERT((oldpdpe & PG_A) != 0,
7026 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7027 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7028 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7032 * Initialize the page directory page.
7034 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7040 * Demote the mapping.
7045 * Invalidate a stale recursive mapping of the page directory page.
7047 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7049 pmap_pdpe_demotions++;
7050 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7051 " in pmap %p", va, pmap);
7056 * Sets the memory attribute for the specified page.
7059 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7062 m->md.pat_mode = ma;
7065 * If "m" is a normal page, update its direct mapping. This update
7066 * can be relied upon to perform any cache operations that are
7067 * required for data coherence.
7069 if ((m->flags & PG_FICTITIOUS) == 0 &&
7070 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7072 panic("memory attribute change on the direct map failed");
7076 * Changes the specified virtual address range's memory type to that given by
7077 * the parameter "mode". The specified virtual address range must be
7078 * completely contained within either the direct map or the kernel map. If
7079 * the virtual address range is contained within the kernel map, then the
7080 * memory type for each of the corresponding ranges of the direct map is also
7081 * changed. (The corresponding ranges of the direct map are those ranges that
7082 * map the same physical pages as the specified virtual address range.) These
7083 * changes to the direct map are necessary because Intel describes the
7084 * behavior of their processors as "undefined" if two or more mappings to the
7085 * same physical page have different memory types.
7087 * Returns zero if the change completed successfully, and either EINVAL or
7088 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7089 * of the virtual address range was not mapped, and ENOMEM is returned if
7090 * there was insufficient memory available to complete the change. In the
7091 * latter case, the memory type may have been changed on some part of the
7092 * virtual address range or the direct map.
7095 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7099 PMAP_LOCK(kernel_pmap);
7100 error = pmap_change_attr_locked(va, size, mode);
7101 PMAP_UNLOCK(kernel_pmap);
7106 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
7108 vm_offset_t base, offset, tmpva;
7109 vm_paddr_t pa_start, pa_end, pa_end1;
7113 int cache_bits_pte, cache_bits_pde, error;
7116 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7117 base = trunc_page(va);
7118 offset = va & PAGE_MASK;
7119 size = round_page(offset + size);
7122 * Only supported on kernel virtual addresses, including the direct
7123 * map but excluding the recursive map.
7125 if (base < DMAP_MIN_ADDRESS)
7128 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7129 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7133 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7134 * into 4KB pages if required.
7136 for (tmpva = base; tmpva < base + size; ) {
7137 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7138 if (pdpe == NULL || *pdpe == 0)
7140 if (*pdpe & PG_PS) {
7142 * If the current 1GB page already has the required
7143 * memory type, then we need not demote this page. Just
7144 * increment tmpva to the next 1GB page frame.
7146 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7147 tmpva = trunc_1gpage(tmpva) + NBPDP;
7152 * If the current offset aligns with a 1GB page frame
7153 * and there is at least 1GB left within the range, then
7154 * we need not break down this page into 2MB pages.
7156 if ((tmpva & PDPMASK) == 0 &&
7157 tmpva + PDPMASK < base + size) {
7161 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7164 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7169 * If the current 2MB page already has the required
7170 * memory type, then we need not demote this page. Just
7171 * increment tmpva to the next 2MB page frame.
7173 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7174 tmpva = trunc_2mpage(tmpva) + NBPDR;
7179 * If the current offset aligns with a 2MB page frame
7180 * and there is at least 2MB left within the range, then
7181 * we need not break down this page into 4KB pages.
7183 if ((tmpva & PDRMASK) == 0 &&
7184 tmpva + PDRMASK < base + size) {
7188 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7191 pte = pmap_pde_to_pte(pde, tmpva);
7199 * Ok, all the pages exist, so run through them updating their
7200 * cache mode if required.
7202 pa_start = pa_end = 0;
7203 for (tmpva = base; tmpva < base + size; ) {
7204 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7205 if (*pdpe & PG_PS) {
7206 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7207 pmap_pde_attr(pdpe, cache_bits_pde,
7211 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7212 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7213 if (pa_start == pa_end) {
7214 /* Start physical address run. */
7215 pa_start = *pdpe & PG_PS_FRAME;
7216 pa_end = pa_start + NBPDP;
7217 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7220 /* Run ended, update direct map. */
7221 error = pmap_change_attr_locked(
7222 PHYS_TO_DMAP(pa_start),
7223 pa_end - pa_start, mode);
7226 /* Start physical address run. */
7227 pa_start = *pdpe & PG_PS_FRAME;
7228 pa_end = pa_start + NBPDP;
7231 tmpva = trunc_1gpage(tmpva) + NBPDP;
7234 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7236 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7237 pmap_pde_attr(pde, cache_bits_pde,
7241 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7242 (*pde & PG_PS_FRAME) < dmaplimit) {
7243 if (pa_start == pa_end) {
7244 /* Start physical address run. */
7245 pa_start = *pde & PG_PS_FRAME;
7246 pa_end = pa_start + NBPDR;
7247 } else if (pa_end == (*pde & PG_PS_FRAME))
7250 /* Run ended, update direct map. */
7251 error = pmap_change_attr_locked(
7252 PHYS_TO_DMAP(pa_start),
7253 pa_end - pa_start, mode);
7256 /* Start physical address run. */
7257 pa_start = *pde & PG_PS_FRAME;
7258 pa_end = pa_start + NBPDR;
7261 tmpva = trunc_2mpage(tmpva) + NBPDR;
7263 pte = pmap_pde_to_pte(pde, tmpva);
7264 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7265 pmap_pte_attr(pte, cache_bits_pte,
7269 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7270 (*pte & PG_FRAME) < dmaplimit) {
7271 if (pa_start == pa_end) {
7272 /* Start physical address run. */
7273 pa_start = *pte & PG_FRAME;
7274 pa_end = pa_start + PAGE_SIZE;
7275 } else if (pa_end == (*pte & PG_FRAME))
7276 pa_end += PAGE_SIZE;
7278 /* Run ended, update direct map. */
7279 error = pmap_change_attr_locked(
7280 PHYS_TO_DMAP(pa_start),
7281 pa_end - pa_start, mode);
7284 /* Start physical address run. */
7285 pa_start = *pte & PG_FRAME;
7286 pa_end = pa_start + PAGE_SIZE;
7292 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7293 pa_end1 = MIN(pa_end, dmaplimit);
7294 if (pa_start != pa_end1)
7295 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7296 pa_end1 - pa_start, mode);
7300 * Flush CPU caches if required to make sure any data isn't cached that
7301 * shouldn't be, etc.
7304 pmap_invalidate_range(kernel_pmap, base, tmpva);
7305 pmap_invalidate_cache_range(base, tmpva, FALSE);
7311 * Demotes any mapping within the direct map region that covers more than the
7312 * specified range of physical addresses. This range's size must be a power
7313 * of two and its starting address must be a multiple of its size. Since the
7314 * demotion does not change any attributes of the mapping, a TLB invalidation
7315 * is not mandatory. The caller may, however, request a TLB invalidation.
7318 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7327 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7328 KASSERT((base & (len - 1)) == 0,
7329 ("pmap_demote_DMAP: base is not a multiple of len"));
7330 if (len < NBPDP && base < dmaplimit) {
7331 va = PHYS_TO_DMAP(base);
7333 PMAP_LOCK(kernel_pmap);
7334 pdpe = pmap_pdpe(kernel_pmap, va);
7335 if ((*pdpe & X86_PG_V) == 0)
7336 panic("pmap_demote_DMAP: invalid PDPE");
7337 if ((*pdpe & PG_PS) != 0) {
7338 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7339 panic("pmap_demote_DMAP: PDPE failed");
7343 pde = pmap_pdpe_to_pde(pdpe, va);
7344 if ((*pde & X86_PG_V) == 0)
7345 panic("pmap_demote_DMAP: invalid PDE");
7346 if ((*pde & PG_PS) != 0) {
7347 if (!pmap_demote_pde(kernel_pmap, pde, va))
7348 panic("pmap_demote_DMAP: PDE failed");
7352 if (changed && invalidate)
7353 pmap_invalidate_page(kernel_pmap, va);
7354 PMAP_UNLOCK(kernel_pmap);
7359 * perform the pmap work for mincore
7362 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7365 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7369 PG_A = pmap_accessed_bit(pmap);
7370 PG_M = pmap_modified_bit(pmap);
7371 PG_V = pmap_valid_bit(pmap);
7372 PG_RW = pmap_rw_bit(pmap);
7376 pdep = pmap_pde(pmap, addr);
7377 if (pdep != NULL && (*pdep & PG_V)) {
7378 if (*pdep & PG_PS) {
7380 /* Compute the physical address of the 4KB page. */
7381 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7383 val = MINCORE_SUPER;
7385 pte = *pmap_pde_to_pte(pdep, addr);
7386 pa = pte & PG_FRAME;
7394 if ((pte & PG_V) != 0) {
7395 val |= MINCORE_INCORE;
7396 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7397 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7398 if ((pte & PG_A) != 0)
7399 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7401 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7402 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7403 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7404 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7405 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7408 PA_UNLOCK_COND(*locked_pa);
7414 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7416 uint32_t gen, new_gen, pcid_next;
7418 CRITICAL_ASSERT(curthread);
7419 gen = PCPU_GET(pcid_gen);
7420 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7421 return (pti ? 0 : CR3_PCID_SAVE);
7422 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7423 return (CR3_PCID_SAVE);
7424 pcid_next = PCPU_GET(pcid_next);
7425 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7426 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7427 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7428 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7429 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7433 PCPU_SET(pcid_gen, new_gen);
7434 pcid_next = PMAP_PCID_KERN + 1;
7438 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7439 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7440 PCPU_SET(pcid_next, pcid_next + 1);
7445 pmap_activate_sw(struct thread *td)
7447 pmap_t oldpmap, pmap;
7448 struct invpcid_descr d;
7449 uint64_t cached, cr3, kcr3, kern_pti_cached, rsp0, ucr3;
7452 struct amd64tss *tssp;
7455 oldpmap = PCPU_GET(curpmap);
7456 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7457 if (oldpmap == pmap)
7459 cpuid = PCPU_GET(cpuid);
7461 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7463 CPU_SET(cpuid, &pmap->pm_active);
7466 if (pmap_pcid_enabled) {
7467 cached = pmap_pcid_alloc(pmap, cpuid);
7468 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
7469 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7470 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7471 pmap->pm_pcids[cpuid].pm_pcid));
7472 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7473 pmap == kernel_pmap,
7474 ("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
7475 td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7478 * If the INVPCID instruction is not available,
7479 * invltlb_pcid_handler() is used for handle
7480 * invalidate_all IPI, which checks for curpmap ==
7481 * smp_tlb_pmap. Below operations sequence has a
7482 * window where %CR3 is loaded with the new pmap's
7483 * PML4 address, but curpmap value is not yet updated.
7484 * This causes invltlb IPI handler, called between the
7485 * updates, to execute as NOP, which leaves stale TLB
7488 * Note that the most typical use of
7489 * pmap_activate_sw(), from the context switch, is
7490 * immune to this race, because interrupts are
7491 * disabled (while the thread lock is owned), and IPI
7492 * happens after curpmap is updated. Protect other
7493 * callers in a similar way, by disabling interrupts
7494 * around the %cr3 register reload and curpmap
7498 rflags = intr_disable();
7500 kern_pti_cached = pti ? 0 : cached;
7501 if (!kern_pti_cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
7502 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7505 PCPU_SET(curpmap, pmap);
7507 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7508 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7511 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7513 * Manually invalidate translations cached
7514 * from the user page table. They are not
7515 * flushed by reload of cr3 with the kernel
7516 * page table pointer above.
7518 if (invpcid_works) {
7519 d.pcid = PMAP_PCID_USER_PT |
7520 pmap->pm_pcids[cpuid].pm_pcid;
7523 invpcid(&d, INVPCID_CTX);
7525 pmap_pti_pcid_invalidate(ucr3, kcr3);
7529 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7530 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7533 intr_restore(rflags);
7535 PCPU_INC(pm_save_cnt);
7537 load_cr3(pmap->pm_cr3);
7538 PCPU_SET(curpmap, pmap);
7540 PCPU_SET(kcr3, pmap->pm_cr3);
7541 PCPU_SET(ucr3, pmap->pm_ucr3);
7544 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
7545 rsp0 = ((vm_offset_t)PCPU_PTR(pti_stack) +
7546 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful;
7547 tssp = PCPU_GET(tssp);
7548 tssp->tss_rsp0 = rsp0;
7551 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7553 CPU_CLR(cpuid, &oldpmap->pm_active);
7558 pmap_activate(struct thread *td)
7562 pmap_activate_sw(td);
7567 pmap_activate_boot(pmap_t pmap)
7573 * kernel_pmap must be never deactivated, and we ensure that
7574 * by never activating it at all.
7576 MPASS(pmap != kernel_pmap);
7578 cpuid = PCPU_GET(cpuid);
7580 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7582 CPU_SET(cpuid, &pmap->pm_active);
7584 PCPU_SET(curpmap, pmap);
7586 kcr3 = pmap->pm_cr3;
7587 if (pmap_pcid_enabled)
7588 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
7592 PCPU_SET(kcr3, kcr3);
7593 PCPU_SET(ucr3, PMAP_NO_CR3);
7597 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7602 * Increase the starting virtual address of the given mapping if a
7603 * different alignment might result in more superpage mappings.
7606 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7607 vm_offset_t *addr, vm_size_t size)
7609 vm_offset_t superpage_offset;
7613 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7614 offset += ptoa(object->pg_color);
7615 superpage_offset = offset & PDRMASK;
7616 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
7617 (*addr & PDRMASK) == superpage_offset)
7619 if ((*addr & PDRMASK) < superpage_offset)
7620 *addr = (*addr & ~PDRMASK) + superpage_offset;
7622 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
7626 static unsigned long num_dirty_emulations;
7627 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
7628 &num_dirty_emulations, 0, NULL);
7630 static unsigned long num_accessed_emulations;
7631 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
7632 &num_accessed_emulations, 0, NULL);
7634 static unsigned long num_superpage_accessed_emulations;
7635 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
7636 &num_superpage_accessed_emulations, 0, NULL);
7638 static unsigned long ad_emulation_superpage_promotions;
7639 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
7640 &ad_emulation_superpage_promotions, 0, NULL);
7641 #endif /* INVARIANTS */
7644 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
7647 struct rwlock *lock;
7648 #if VM_NRESERVLEVEL > 0
7652 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
7654 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
7655 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
7657 if (!pmap_emulate_ad_bits(pmap))
7660 PG_A = pmap_accessed_bit(pmap);
7661 PG_M = pmap_modified_bit(pmap);
7662 PG_V = pmap_valid_bit(pmap);
7663 PG_RW = pmap_rw_bit(pmap);
7669 pde = pmap_pde(pmap, va);
7670 if (pde == NULL || (*pde & PG_V) == 0)
7673 if ((*pde & PG_PS) != 0) {
7674 if (ftype == VM_PROT_READ) {
7676 atomic_add_long(&num_superpage_accessed_emulations, 1);
7684 pte = pmap_pde_to_pte(pde, va);
7685 if ((*pte & PG_V) == 0)
7688 if (ftype == VM_PROT_WRITE) {
7689 if ((*pte & PG_RW) == 0)
7692 * Set the modified and accessed bits simultaneously.
7694 * Intel EPT PTEs that do software emulation of A/D bits map
7695 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
7696 * An EPT misconfiguration is triggered if the PTE is writable
7697 * but not readable (WR=10). This is avoided by setting PG_A
7698 * and PG_M simultaneously.
7700 *pte |= PG_M | PG_A;
7705 #if VM_NRESERVLEVEL > 0
7706 /* try to promote the mapping */
7707 if (va < VM_MAXUSER_ADDRESS)
7708 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7712 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7714 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
7715 pmap_ps_enabled(pmap) &&
7716 (m->flags & PG_FICTITIOUS) == 0 &&
7717 vm_reserv_level_iffullpop(m) == 0) {
7718 pmap_promote_pde(pmap, pde, va, &lock);
7720 atomic_add_long(&ad_emulation_superpage_promotions, 1);
7726 if (ftype == VM_PROT_WRITE)
7727 atomic_add_long(&num_dirty_emulations, 1);
7729 atomic_add_long(&num_accessed_emulations, 1);
7731 rv = 0; /* success */
7740 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
7745 pt_entry_t *pte, PG_V;
7749 PG_V = pmap_valid_bit(pmap);
7752 pml4 = pmap_pml4e(pmap, va);
7754 if ((*pml4 & PG_V) == 0)
7757 pdp = pmap_pml4e_to_pdpe(pml4, va);
7759 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
7762 pde = pmap_pdpe_to_pde(pdp, va);
7764 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
7767 pte = pmap_pde_to_pte(pde, va);
7776 * Get the kernel virtual address of a set of physical pages. If there are
7777 * physical addresses not covered by the DMAP perform a transient mapping
7778 * that will be removed when calling pmap_unmap_io_transient.
7780 * \param page The pages the caller wishes to obtain the virtual
7781 * address on the kernel memory map.
7782 * \param vaddr On return contains the kernel virtual memory address
7783 * of the pages passed in the page parameter.
7784 * \param count Number of pages passed in.
7785 * \param can_fault TRUE if the thread using the mapped pages can take
7786 * page faults, FALSE otherwise.
7788 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7789 * finished or FALSE otherwise.
7793 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7794 boolean_t can_fault)
7797 boolean_t needs_mapping;
7799 int cache_bits, error __unused, i;
7802 * Allocate any KVA space that we need, this is done in a separate
7803 * loop to prevent calling vmem_alloc while pinned.
7805 needs_mapping = FALSE;
7806 for (i = 0; i < count; i++) {
7807 paddr = VM_PAGE_TO_PHYS(page[i]);
7808 if (__predict_false(paddr >= dmaplimit)) {
7809 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7810 M_BESTFIT | M_WAITOK, &vaddr[i]);
7811 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7812 needs_mapping = TRUE;
7814 vaddr[i] = PHYS_TO_DMAP(paddr);
7818 /* Exit early if everything is covered by the DMAP */
7823 * NB: The sequence of updating a page table followed by accesses
7824 * to the corresponding pages used in the !DMAP case is subject to
7825 * the situation described in the "AMD64 Architecture Programmer's
7826 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7827 * Coherency Considerations". Therefore, issuing the INVLPG right
7828 * after modifying the PTE bits is crucial.
7832 for (i = 0; i < count; i++) {
7833 paddr = VM_PAGE_TO_PHYS(page[i]);
7834 if (paddr >= dmaplimit) {
7837 * Slow path, since we can get page faults
7838 * while mappings are active don't pin the
7839 * thread to the CPU and instead add a global
7840 * mapping visible to all CPUs.
7842 pmap_qenter(vaddr[i], &page[i], 1);
7844 pte = vtopte(vaddr[i]);
7845 cache_bits = pmap_cache_bits(kernel_pmap,
7846 page[i]->md.pat_mode, 0);
7847 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7854 return (needs_mapping);
7858 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7859 boolean_t can_fault)
7866 for (i = 0; i < count; i++) {
7867 paddr = VM_PAGE_TO_PHYS(page[i]);
7868 if (paddr >= dmaplimit) {
7870 pmap_qremove(vaddr[i], 1);
7871 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7877 pmap_quick_enter_page(vm_page_t m)
7881 paddr = VM_PAGE_TO_PHYS(m);
7882 if (paddr < dmaplimit)
7883 return (PHYS_TO_DMAP(paddr));
7884 mtx_lock_spin(&qframe_mtx);
7885 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7886 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7887 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7892 pmap_quick_remove_page(vm_offset_t addr)
7897 pte_store(vtopte(qframe), 0);
7899 mtx_unlock_spin(&qframe_mtx);
7903 pmap_pti_alloc_page(void)
7907 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7908 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
7909 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
7914 pmap_pti_free_page(vm_page_t m)
7917 KASSERT(m->wire_count > 0, ("page %p not wired", m));
7918 if (!vm_page_unwire_noq(m))
7920 vm_page_free_zero(m);
7934 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
7935 VM_OBJECT_WLOCK(pti_obj);
7936 pml4_pg = pmap_pti_alloc_page();
7937 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
7938 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
7939 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
7940 pdpe = pmap_pti_pdpe(va);
7941 pmap_pti_wire_pte(pdpe);
7943 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
7944 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
7945 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
7946 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
7947 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
7948 sizeof(struct gate_descriptor) * NIDT, false);
7949 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
7950 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
7952 /* Doublefault stack IST 1 */
7953 va = common_tss[i].tss_ist1;
7954 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7955 /* NMI stack IST 2 */
7956 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
7957 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7958 /* MC# stack IST 3 */
7959 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
7960 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7961 /* DB# stack IST 4 */
7962 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
7963 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7965 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
7966 (vm_offset_t)etext, true);
7967 pti_finalized = true;
7968 VM_OBJECT_WUNLOCK(pti_obj);
7970 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
7972 static pdp_entry_t *
7973 pmap_pti_pdpe(vm_offset_t va)
7975 pml4_entry_t *pml4e;
7978 vm_pindex_t pml4_idx;
7981 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7983 pml4_idx = pmap_pml4e_index(va);
7984 pml4e = &pti_pml4[pml4_idx];
7988 panic("pml4 alloc after finalization\n");
7989 m = pmap_pti_alloc_page();
7991 pmap_pti_free_page(m);
7992 mphys = *pml4e & ~PAGE_MASK;
7994 mphys = VM_PAGE_TO_PHYS(m);
7995 *pml4e = mphys | X86_PG_RW | X86_PG_V;
7998 mphys = *pml4e & ~PAGE_MASK;
8000 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
8005 pmap_pti_wire_pte(void *pte)
8009 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8010 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8015 pmap_pti_unwire_pde(void *pde, bool only_ref)
8019 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8020 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
8021 MPASS(m->wire_count > 0);
8022 MPASS(only_ref || m->wire_count > 1);
8023 pmap_pti_free_page(m);
8027 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
8032 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8033 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8034 MPASS(m->wire_count > 0);
8035 if (pmap_pti_free_page(m)) {
8036 pde = pmap_pti_pde(va);
8037 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
8039 pmap_pti_unwire_pde(pde, false);
8044 pmap_pti_pde(vm_offset_t va)
8052 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8054 pdpe = pmap_pti_pdpe(va);
8056 m = pmap_pti_alloc_page();
8058 pmap_pti_free_page(m);
8059 MPASS((*pdpe & X86_PG_PS) == 0);
8060 mphys = *pdpe & ~PAGE_MASK;
8062 mphys = VM_PAGE_TO_PHYS(m);
8063 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8066 MPASS((*pdpe & X86_PG_PS) == 0);
8067 mphys = *pdpe & ~PAGE_MASK;
8070 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8071 pd_idx = pmap_pde_index(va);
8077 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8084 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8086 pde = pmap_pti_pde(va);
8087 if (unwire_pde != NULL) {
8089 pmap_pti_wire_pte(pde);
8092 m = pmap_pti_alloc_page();
8094 pmap_pti_free_page(m);
8095 MPASS((*pde & X86_PG_PS) == 0);
8096 mphys = *pde & ~(PAGE_MASK | pg_nx);
8098 mphys = VM_PAGE_TO_PHYS(m);
8099 *pde = mphys | X86_PG_RW | X86_PG_V;
8100 if (unwire_pde != NULL)
8101 *unwire_pde = false;
8104 MPASS((*pde & X86_PG_PS) == 0);
8105 mphys = *pde & ~(PAGE_MASK | pg_nx);
8108 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8109 pte += pmap_pte_index(va);
8115 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8119 pt_entry_t *pte, ptev;
8122 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8124 sva = trunc_page(sva);
8125 MPASS(sva > VM_MAXUSER_ADDRESS);
8126 eva = round_page(eva);
8128 for (; sva < eva; sva += PAGE_SIZE) {
8129 pte = pmap_pti_pte(sva, &unwire_pde);
8130 pa = pmap_kextract(sva);
8131 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8132 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8133 VM_MEMATTR_DEFAULT, FALSE);
8135 pte_store(pte, ptev);
8136 pmap_pti_wire_pte(pte);
8138 KASSERT(!pti_finalized,
8139 ("pti overlap after fin %#lx %#lx %#lx",
8141 KASSERT(*pte == ptev,
8142 ("pti non-identical pte after fin %#lx %#lx %#lx",
8146 pde = pmap_pti_pde(sva);
8147 pmap_pti_unwire_pde(pde, true);
8153 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
8158 VM_OBJECT_WLOCK(pti_obj);
8159 pmap_pti_add_kva_locked(sva, eva, exec);
8160 VM_OBJECT_WUNLOCK(pti_obj);
8164 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
8171 sva = rounddown2(sva, PAGE_SIZE);
8172 MPASS(sva > VM_MAXUSER_ADDRESS);
8173 eva = roundup2(eva, PAGE_SIZE);
8175 VM_OBJECT_WLOCK(pti_obj);
8176 for (va = sva; va < eva; va += PAGE_SIZE) {
8177 pte = pmap_pti_pte(va, NULL);
8178 KASSERT((*pte & X86_PG_V) != 0,
8179 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8180 (u_long)pte, *pte));
8182 pmap_pti_unwire_pte(pte, va);
8184 pmap_invalidate_range(kernel_pmap, sva, eva);
8185 VM_OBJECT_WUNLOCK(pti_obj);
8188 #include "opt_ddb.h"
8190 #include <sys/kdb.h>
8191 #include <ddb/ddb.h>
8193 DB_SHOW_COMMAND(pte, pmap_print_pte)
8199 pt_entry_t *pte, PG_V;
8203 db_printf("show pte addr\n");
8206 va = (vm_offset_t)addr;
8208 if (kdb_thread != NULL)
8209 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
8211 pmap = PCPU_GET(curpmap);
8213 PG_V = pmap_valid_bit(pmap);
8214 pml4 = pmap_pml4e(pmap, va);
8215 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
8216 if ((*pml4 & PG_V) == 0) {
8220 pdp = pmap_pml4e_to_pdpe(pml4, va);
8221 db_printf(" pdpe %#016lx", *pdp);
8222 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
8226 pde = pmap_pdpe_to_pde(pdp, va);
8227 db_printf(" pde %#016lx", *pde);
8228 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
8232 pte = pmap_pde_to_pte(pde, va);
8233 db_printf(" pte %#016lx\n", *pte);
8236 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
8241 a = (vm_paddr_t)addr;
8242 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
8244 db_printf("show phys2dmap addr\n");