2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
326 #define pa_index(pa) ({ \
327 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
328 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
345 #define NPV_LIST_LOCKS MAXCPU
347 #define PHYS_TO_PV_LIST_LOCK(pa) \
348 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
351 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
352 struct rwlock **_lockp = (lockp); \
353 struct rwlock *_new_lock; \
355 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
356 if (_new_lock != *_lockp) { \
357 if (*_lockp != NULL) \
358 rw_wunlock(*_lockp); \
359 *_lockp = _new_lock; \
364 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
365 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
367 #define RELEASE_PV_LIST_LOCK(lockp) do { \
368 struct rwlock **_lockp = (lockp); \
370 if (*_lockp != NULL) { \
371 rw_wunlock(*_lockp); \
376 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
377 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
379 struct pmap kernel_pmap_store;
381 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
382 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
385 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
386 "Number of kernel page table pages allocated on bootup");
389 vm_paddr_t dmaplimit;
390 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
393 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
395 static int pg_ps_enabled = 1;
396 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
397 &pg_ps_enabled, 0, "Are large page mappings enabled?");
399 #define PAT_INDEX_SIZE 8
400 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
402 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
403 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
404 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
405 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
407 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
408 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
409 static int ndmpdpphys; /* number of DMPDPphys pages */
411 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
414 * pmap_mapdev support pre initialization (i.e. console)
416 #define PMAP_PREINIT_MAPPING_COUNT 8
417 static struct pmap_preinit_mapping {
422 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
423 static int pmap_initialized;
426 * Data for the pv entry allocation mechanism.
427 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
431 pc_to_domain(struct pv_chunk *pc)
434 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
438 pc_to_domain(struct pv_chunk *pc __unused)
445 struct pv_chunks_list {
447 TAILQ_HEAD(pch, pv_chunk) pvc_list;
449 } __aligned(CACHE_LINE_SIZE);
451 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
454 struct pmap_large_md_page {
455 struct rwlock pv_lock;
456 struct md_page pv_page;
459 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
460 #define pv_dummy pv_dummy_large.pv_page
461 __read_mostly static struct pmap_large_md_page *pv_table;
462 __read_mostly vm_paddr_t pmap_last_pa;
464 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
465 static u_long pv_invl_gen[NPV_LIST_LOCKS];
466 static struct md_page *pv_table;
467 static struct md_page pv_dummy;
471 * All those kernel PT submaps that BSD is so fond of
473 pt_entry_t *CMAP1 = NULL;
475 static vm_offset_t qframe = 0;
476 static struct mtx qframe_mtx;
478 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
480 static vmem_t *large_vmem;
481 static u_int lm_ents;
482 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
483 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
485 int pmap_pcid_enabled = 1;
486 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
487 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
488 int invpcid_works = 0;
489 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
490 "Is the invpcid instruction available ?");
492 int __read_frequently pti = 0;
493 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
495 "Page Table Isolation enabled");
496 static vm_object_t pti_obj;
497 static pml4_entry_t *pti_pml4;
498 static vm_pindex_t pti_pg_idx;
499 static bool pti_finalized;
501 struct pmap_pkru_range {
502 struct rs_el pkru_rs_el;
507 static uma_zone_t pmap_pkru_ranges_zone;
508 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
509 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
510 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
511 static void *pkru_dup_range(void *ctx, void *data);
512 static void pkru_free_range(void *ctx, void *node);
513 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
514 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
515 static void pmap_pkru_deassign_all(pmap_t pmap);
518 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
525 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
527 return (sysctl_handle_64(oidp, &res, 0, req));
529 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
530 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
531 "Count of saved TLB context on switch");
533 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
534 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
535 static struct mtx invl_gen_mtx;
536 /* Fake lock object to satisfy turnstiles interface. */
537 static struct lock_object invl_gen_ts = {
540 static struct pmap_invl_gen pmap_invl_gen_head = {
544 static u_long pmap_invl_gen = 1;
545 static int pmap_invl_waiters;
546 static struct callout pmap_invl_callout;
547 static bool pmap_invl_callout_inited;
549 #define PMAP_ASSERT_NOT_IN_DI() \
550 KASSERT(pmap_not_in_di(), ("DI already started"))
557 if ((cpu_feature2 & CPUID2_CX16) == 0)
560 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
565 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
569 locked = pmap_di_locked();
570 return (sysctl_handle_int(oidp, &locked, 0, req));
572 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
573 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
574 "Locked delayed invalidation");
576 static bool pmap_not_in_di_l(void);
577 static bool pmap_not_in_di_u(void);
578 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
581 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
585 pmap_not_in_di_l(void)
587 struct pmap_invl_gen *invl_gen;
589 invl_gen = &curthread->td_md.md_invl_gen;
590 return (invl_gen->gen == 0);
594 pmap_thread_init_invl_gen_l(struct thread *td)
596 struct pmap_invl_gen *invl_gen;
598 invl_gen = &td->td_md.md_invl_gen;
603 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
605 struct turnstile *ts;
607 ts = turnstile_trywait(&invl_gen_ts);
608 if (*m_gen > atomic_load_long(invl_gen))
609 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
611 turnstile_cancel(ts);
615 pmap_delayed_invl_finish_unblock(u_long new_gen)
617 struct turnstile *ts;
619 turnstile_chain_lock(&invl_gen_ts);
620 ts = turnstile_lookup(&invl_gen_ts);
622 pmap_invl_gen = new_gen;
624 turnstile_broadcast(ts, TS_SHARED_QUEUE);
625 turnstile_unpend(ts);
627 turnstile_chain_unlock(&invl_gen_ts);
631 * Start a new Delayed Invalidation (DI) block of code, executed by
632 * the current thread. Within a DI block, the current thread may
633 * destroy both the page table and PV list entries for a mapping and
634 * then release the corresponding PV list lock before ensuring that
635 * the mapping is flushed from the TLBs of any processors with the
639 pmap_delayed_invl_start_l(void)
641 struct pmap_invl_gen *invl_gen;
644 invl_gen = &curthread->td_md.md_invl_gen;
645 PMAP_ASSERT_NOT_IN_DI();
646 mtx_lock(&invl_gen_mtx);
647 if (LIST_EMPTY(&pmap_invl_gen_tracker))
648 currgen = pmap_invl_gen;
650 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
651 invl_gen->gen = currgen + 1;
652 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
653 mtx_unlock(&invl_gen_mtx);
657 * Finish the DI block, previously started by the current thread. All
658 * required TLB flushes for the pages marked by
659 * pmap_delayed_invl_page() must be finished before this function is
662 * This function works by bumping the global DI generation number to
663 * the generation number of the current thread's DI, unless there is a
664 * pending DI that started earlier. In the latter case, bumping the
665 * global DI generation number would incorrectly signal that the
666 * earlier DI had finished. Instead, this function bumps the earlier
667 * DI's generation number to match the generation number of the
668 * current thread's DI.
671 pmap_delayed_invl_finish_l(void)
673 struct pmap_invl_gen *invl_gen, *next;
675 invl_gen = &curthread->td_md.md_invl_gen;
676 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
677 mtx_lock(&invl_gen_mtx);
678 next = LIST_NEXT(invl_gen, link);
680 pmap_delayed_invl_finish_unblock(invl_gen->gen);
682 next->gen = invl_gen->gen;
683 LIST_REMOVE(invl_gen, link);
684 mtx_unlock(&invl_gen_mtx);
689 pmap_not_in_di_u(void)
691 struct pmap_invl_gen *invl_gen;
693 invl_gen = &curthread->td_md.md_invl_gen;
694 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
698 pmap_thread_init_invl_gen_u(struct thread *td)
700 struct pmap_invl_gen *invl_gen;
702 invl_gen = &td->td_md.md_invl_gen;
704 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
708 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
710 uint64_t new_high, new_low, old_high, old_low;
713 old_low = new_low = 0;
714 old_high = new_high = (uintptr_t)0;
716 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
717 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
718 : "b"(new_low), "c" (new_high)
721 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
724 out->next = (void *)old_high;
727 out->next = (void *)new_high;
733 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
734 struct pmap_invl_gen *new_val)
736 uint64_t new_high, new_low, old_high, old_low;
739 new_low = new_val->gen;
740 new_high = (uintptr_t)new_val->next;
741 old_low = old_val->gen;
742 old_high = (uintptr_t)old_val->next;
744 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
745 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
746 : "b"(new_low), "c" (new_high)
752 static long invl_start_restart;
753 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
754 &invl_start_restart, 0,
756 static long invl_finish_restart;
757 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
758 &invl_finish_restart, 0,
760 static int invl_max_qlen;
761 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
766 static struct lock_delay_config __read_frequently di_delay;
767 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
770 pmap_delayed_invl_start_u(void)
772 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
774 struct lock_delay_arg lda;
782 invl_gen = &td->td_md.md_invl_gen;
783 PMAP_ASSERT_NOT_IN_DI();
784 lock_delay_arg_init(&lda, &di_delay);
785 invl_gen->saved_pri = 0;
786 pri = td->td_base_pri;
789 pri = td->td_base_pri;
791 invl_gen->saved_pri = pri;
798 for (p = &pmap_invl_gen_head;; p = prev.next) {
800 prevl = atomic_load_ptr(&p->next);
801 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
802 PV_STAT(atomic_add_long(&invl_start_restart, 1));
808 prev.next = (void *)prevl;
811 if ((ii = invl_max_qlen) < i)
812 atomic_cmpset_int(&invl_max_qlen, ii, i);
815 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
816 PV_STAT(atomic_add_long(&invl_start_restart, 1));
821 new_prev.gen = prev.gen;
822 new_prev.next = invl_gen;
823 invl_gen->gen = prev.gen + 1;
825 /* Formal fence between store to invl->gen and updating *p. */
826 atomic_thread_fence_rel();
829 * After inserting an invl_gen element with invalid bit set,
830 * this thread blocks any other thread trying to enter the
831 * delayed invalidation block. Do not allow to remove us from
832 * the CPU, because it causes starvation for other threads.
837 * ABA for *p is not possible there, since p->gen can only
838 * increase. So if the *p thread finished its di, then
839 * started a new one and got inserted into the list at the
840 * same place, its gen will appear greater than the previously
843 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
845 PV_STAT(atomic_add_long(&invl_start_restart, 1));
851 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
852 * invl_gen->next, allowing other threads to iterate past us.
853 * pmap_di_store_invl() provides fence between the generation
854 * write and the update of next.
856 invl_gen->next = NULL;
861 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
862 struct pmap_invl_gen *p)
864 struct pmap_invl_gen prev, new_prev;
868 * Load invl_gen->gen after setting invl_gen->next
869 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
870 * generations to propagate to our invl_gen->gen. Lock prefix
871 * in atomic_set_ptr() worked as seq_cst fence.
873 mygen = atomic_load_long(&invl_gen->gen);
875 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
878 KASSERT(prev.gen < mygen,
879 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
880 new_prev.gen = mygen;
881 new_prev.next = (void *)((uintptr_t)invl_gen->next &
882 ~PMAP_INVL_GEN_NEXT_INVALID);
884 /* Formal fence between load of prev and storing update to it. */
885 atomic_thread_fence_rel();
887 return (pmap_di_store_invl(p, &prev, &new_prev));
891 pmap_delayed_invl_finish_u(void)
893 struct pmap_invl_gen *invl_gen, *p;
895 struct lock_delay_arg lda;
899 invl_gen = &td->td_md.md_invl_gen;
900 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
901 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
902 ("missed invl_start: INVALID"));
903 lock_delay_arg_init(&lda, &di_delay);
906 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
907 prevl = atomic_load_ptr(&p->next);
908 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
909 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
913 if ((void *)prevl == invl_gen)
918 * It is legitimate to not find ourself on the list if a
919 * thread before us finished its DI and started it again.
921 if (__predict_false(p == NULL)) {
922 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
928 atomic_set_ptr((uintptr_t *)&invl_gen->next,
929 PMAP_INVL_GEN_NEXT_INVALID);
930 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
931 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
932 PMAP_INVL_GEN_NEXT_INVALID);
934 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
939 if (atomic_load_int(&pmap_invl_waiters) > 0)
940 pmap_delayed_invl_finish_unblock(0);
941 if (invl_gen->saved_pri != 0) {
943 sched_prio(td, invl_gen->saved_pri);
949 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
951 struct pmap_invl_gen *p, *pn;
956 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
958 nextl = atomic_load_ptr(&p->next);
959 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
960 td = first ? NULL : __containerof(p, struct thread,
962 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
963 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
964 td != NULL ? td->td_tid : -1);
970 static long invl_wait;
971 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
972 "Number of times DI invalidation blocked pmap_remove_all/write");
973 static long invl_wait_slow;
974 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
975 "Number of slow invalidation waits for lockless DI");
980 pmap_delayed_invl_genp(vm_page_t m)
985 pa = VM_PAGE_TO_PHYS(m);
986 if (__predict_false((pa) > pmap_last_pa))
987 gen = &pv_dummy_large.pv_invl_gen;
989 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
995 pmap_delayed_invl_genp(vm_page_t m)
998 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1003 pmap_delayed_invl_callout_func(void *arg __unused)
1006 if (atomic_load_int(&pmap_invl_waiters) == 0)
1008 pmap_delayed_invl_finish_unblock(0);
1012 pmap_delayed_invl_callout_init(void *arg __unused)
1015 if (pmap_di_locked())
1017 callout_init(&pmap_invl_callout, 1);
1018 pmap_invl_callout_inited = true;
1020 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1021 pmap_delayed_invl_callout_init, NULL);
1024 * Ensure that all currently executing DI blocks, that need to flush
1025 * TLB for the given page m, actually flushed the TLB at the time the
1026 * function returned. If the page m has an empty PV list and we call
1027 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1028 * valid mapping for the page m in either its page table or TLB.
1030 * This function works by blocking until the global DI generation
1031 * number catches up with the generation number associated with the
1032 * given page m and its PV list. Since this function's callers
1033 * typically own an object lock and sometimes own a page lock, it
1034 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1038 pmap_delayed_invl_wait_l(vm_page_t m)
1042 bool accounted = false;
1045 m_gen = pmap_delayed_invl_genp(m);
1046 while (*m_gen > pmap_invl_gen) {
1049 atomic_add_long(&invl_wait, 1);
1053 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1058 pmap_delayed_invl_wait_u(vm_page_t m)
1061 struct lock_delay_arg lda;
1065 m_gen = pmap_delayed_invl_genp(m);
1066 lock_delay_arg_init(&lda, &di_delay);
1067 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1068 if (fast || !pmap_invl_callout_inited) {
1069 PV_STAT(atomic_add_long(&invl_wait, 1));
1074 * The page's invalidation generation number
1075 * is still below the current thread's number.
1076 * Prepare to block so that we do not waste
1077 * CPU cycles or worse, suffer livelock.
1079 * Since it is impossible to block without
1080 * racing with pmap_delayed_invl_finish_u(),
1081 * prepare for the race by incrementing
1082 * pmap_invl_waiters and arming a 1-tick
1083 * callout which will unblock us if we lose
1086 atomic_add_int(&pmap_invl_waiters, 1);
1089 * Re-check the current thread's invalidation
1090 * generation after incrementing
1091 * pmap_invl_waiters, so that there is no race
1092 * with pmap_delayed_invl_finish_u() setting
1093 * the page generation and checking
1094 * pmap_invl_waiters. The only race allowed
1095 * is for a missed unblock, which is handled
1099 atomic_load_long(&pmap_invl_gen_head.gen)) {
1100 callout_reset(&pmap_invl_callout, 1,
1101 pmap_delayed_invl_callout_func, NULL);
1102 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1103 pmap_delayed_invl_wait_block(m_gen,
1104 &pmap_invl_gen_head.gen);
1106 atomic_add_int(&pmap_invl_waiters, -1);
1111 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1114 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1115 pmap_thread_init_invl_gen_u);
1118 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1121 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1122 pmap_delayed_invl_start_u);
1125 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1128 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1129 pmap_delayed_invl_finish_u);
1132 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1135 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1136 pmap_delayed_invl_wait_u);
1140 * Mark the page m's PV list as participating in the current thread's
1141 * DI block. Any threads concurrently using m's PV list to remove or
1142 * restrict all mappings to m will wait for the current thread's DI
1143 * block to complete before proceeding.
1145 * The function works by setting the DI generation number for m's PV
1146 * list to at least the DI generation number of the current thread.
1147 * This forces a caller of pmap_delayed_invl_wait() to block until
1148 * current thread calls pmap_delayed_invl_finish().
1151 pmap_delayed_invl_page(vm_page_t m)
1155 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1156 gen = curthread->td_md.md_invl_gen.gen;
1159 m_gen = pmap_delayed_invl_genp(m);
1167 static caddr_t crashdumpmap;
1170 * Internal flags for pmap_enter()'s helper functions.
1172 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1173 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1176 * Internal flags for pmap_mapdev_internal() and
1177 * pmap_change_props_locked().
1179 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1180 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1181 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1183 TAILQ_HEAD(pv_chunklist, pv_chunk);
1185 static void free_pv_chunk(struct pv_chunk *pc);
1186 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1187 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1188 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1189 static int popcnt_pc_map_pq(uint64_t *map);
1190 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1191 static void reserve_pv_entries(pmap_t pmap, int needed,
1192 struct rwlock **lockp);
1193 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1194 struct rwlock **lockp);
1195 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1196 u_int flags, struct rwlock **lockp);
1197 #if VM_NRESERVLEVEL > 0
1198 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1199 struct rwlock **lockp);
1201 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1202 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1205 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1206 vm_prot_t prot, int mode, int flags);
1207 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1208 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1209 vm_offset_t va, struct rwlock **lockp);
1210 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1212 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1213 vm_prot_t prot, struct rwlock **lockp);
1214 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1215 u_int flags, vm_page_t m, struct rwlock **lockp);
1216 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1217 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1218 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1219 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1220 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1222 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1224 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1226 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1227 static vm_page_t pmap_large_map_getptp_unlocked(void);
1228 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1229 #if VM_NRESERVLEVEL > 0
1230 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1231 struct rwlock **lockp);
1233 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1235 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1236 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1238 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1239 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1240 static void pmap_pti_wire_pte(void *pte);
1241 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1242 struct spglist *free, struct rwlock **lockp);
1243 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1244 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1245 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1246 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1247 struct spglist *free);
1248 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1249 pd_entry_t *pde, struct spglist *free,
1250 struct rwlock **lockp);
1251 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1252 vm_page_t m, struct rwlock **lockp);
1253 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1255 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1257 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1258 struct rwlock **lockp);
1259 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1260 struct rwlock **lockp);
1261 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1262 struct rwlock **lockp);
1264 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1265 struct spglist *free);
1266 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1268 /********************/
1269 /* Inline functions */
1270 /********************/
1272 /* Return a non-clipped PD index for a given VA */
1273 static __inline vm_pindex_t
1274 pmap_pde_pindex(vm_offset_t va)
1276 return (va >> PDRSHIFT);
1280 /* Return a pointer to the PML4 slot that corresponds to a VA */
1281 static __inline pml4_entry_t *
1282 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1285 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1288 /* Return a pointer to the PDP slot that corresponds to a VA */
1289 static __inline pdp_entry_t *
1290 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1294 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1295 return (&pdpe[pmap_pdpe_index(va)]);
1298 /* Return a pointer to the PDP slot that corresponds to a VA */
1299 static __inline pdp_entry_t *
1300 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1302 pml4_entry_t *pml4e;
1305 PG_V = pmap_valid_bit(pmap);
1306 pml4e = pmap_pml4e(pmap, va);
1307 if ((*pml4e & PG_V) == 0)
1309 return (pmap_pml4e_to_pdpe(pml4e, va));
1312 /* Return a pointer to the PD slot that corresponds to a VA */
1313 static __inline pd_entry_t *
1314 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1318 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1319 return (&pde[pmap_pde_index(va)]);
1322 /* Return a pointer to the PD slot that corresponds to a VA */
1323 static __inline pd_entry_t *
1324 pmap_pde(pmap_t pmap, vm_offset_t va)
1329 PG_V = pmap_valid_bit(pmap);
1330 pdpe = pmap_pdpe(pmap, va);
1331 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1333 return (pmap_pdpe_to_pde(pdpe, va));
1336 /* Return a pointer to the PT slot that corresponds to a VA */
1337 static __inline pt_entry_t *
1338 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1342 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1343 return (&pte[pmap_pte_index(va)]);
1346 /* Return a pointer to the PT slot that corresponds to a VA */
1347 static __inline pt_entry_t *
1348 pmap_pte(pmap_t pmap, vm_offset_t va)
1353 PG_V = pmap_valid_bit(pmap);
1354 pde = pmap_pde(pmap, va);
1355 if (pde == NULL || (*pde & PG_V) == 0)
1357 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1358 return ((pt_entry_t *)pde);
1359 return (pmap_pde_to_pte(pde, va));
1362 static __inline void
1363 pmap_resident_count_inc(pmap_t pmap, int count)
1366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1367 pmap->pm_stats.resident_count += count;
1370 static __inline void
1371 pmap_resident_count_dec(pmap_t pmap, int count)
1374 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1375 KASSERT(pmap->pm_stats.resident_count >= count,
1376 ("pmap %p resident count underflow %ld %d", pmap,
1377 pmap->pm_stats.resident_count, count));
1378 pmap->pm_stats.resident_count -= count;
1381 PMAP_INLINE pt_entry_t *
1382 vtopte(vm_offset_t va)
1384 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1386 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1388 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1391 static __inline pd_entry_t *
1392 vtopde(vm_offset_t va)
1394 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1396 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1398 return (PDmap + ((va >> PDRSHIFT) & mask));
1402 allocpages(vm_paddr_t *firstaddr, int n)
1407 bzero((void *)ret, n * PAGE_SIZE);
1408 *firstaddr += n * PAGE_SIZE;
1412 CTASSERT(powerof2(NDMPML4E));
1414 /* number of kernel PDP slots */
1415 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1418 nkpt_init(vm_paddr_t addr)
1425 pt_pages = howmany(addr, 1 << PDRSHIFT);
1426 pt_pages += NKPDPE(pt_pages);
1429 * Add some slop beyond the bare minimum required for bootstrapping
1432 * This is quite important when allocating KVA for kernel modules.
1433 * The modules are required to be linked in the negative 2GB of
1434 * the address space. If we run out of KVA in this region then
1435 * pmap_growkernel() will need to allocate page table pages to map
1436 * the entire 512GB of KVA space which is an unnecessary tax on
1439 * Secondly, device memory mapped as part of setting up the low-
1440 * level console(s) is taken from KVA, starting at virtual_avail.
1441 * This is because cninit() is called after pmap_bootstrap() but
1442 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1445 pt_pages += 32; /* 64MB additional slop. */
1451 * Returns the proper write/execute permission for a physical page that is
1452 * part of the initial boot allocations.
1454 * If the page has kernel text, it is marked as read-only. If the page has
1455 * kernel read-only data, it is marked as read-only/not-executable. If the
1456 * page has only read-write data, it is marked as read-write/not-executable.
1457 * If the page is below/above the kernel range, it is marked as read-write.
1459 * This function operates on 2M pages, since we map the kernel space that
1462 static inline pt_entry_t
1463 bootaddr_rwx(vm_paddr_t pa)
1467 * The kernel is loaded at a 2MB-aligned address, and memory below that
1468 * need not be executable. The .bss section is padded to a 2MB
1469 * boundary, so memory following the kernel need not be executable
1470 * either. Preloaded kernel modules have their mapping permissions
1471 * fixed up by the linker.
1473 if (pa < trunc_2mpage(btext - KERNBASE) ||
1474 pa >= trunc_2mpage(_end - KERNBASE))
1475 return (X86_PG_RW | pg_nx);
1478 * The linker should ensure that the read-only and read-write
1479 * portions don't share the same 2M page, so this shouldn't
1480 * impact read-only data. However, in any case, any page with
1481 * read-write data needs to be read-write.
1483 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1484 return (X86_PG_RW | pg_nx);
1487 * Mark any 2M page containing kernel text as read-only. Mark
1488 * other pages with read-only data as read-only and not executable.
1489 * (It is likely a small portion of the read-only data section will
1490 * be marked as read-only, but executable. This should be acceptable
1491 * since the read-only protection will keep the data from changing.)
1492 * Note that fixups to the .text section will still work until we
1495 if (pa < round_2mpage(etext - KERNBASE))
1501 create_pagetables(vm_paddr_t *firstaddr)
1503 int i, j, ndm1g, nkpdpe, nkdmpde;
1507 uint64_t DMPDkernphys;
1509 /* Allocate page table pages for the direct map */
1510 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1511 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1513 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1514 if (ndmpdpphys > NDMPML4E) {
1516 * Each NDMPML4E allows 512 GB, so limit to that,
1517 * and then readjust ndmpdp and ndmpdpphys.
1519 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1520 Maxmem = atop(NDMPML4E * NBPML4);
1521 ndmpdpphys = NDMPML4E;
1522 ndmpdp = NDMPML4E * NPDEPG;
1524 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1526 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1528 * Calculate the number of 1G pages that will fully fit in
1531 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1534 * Allocate 2M pages for the kernel. These will be used in
1535 * place of the first one or more 1G pages from ndm1g.
1537 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1538 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1541 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1542 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1544 /* Allocate pages */
1545 KPML4phys = allocpages(firstaddr, 1);
1546 KPDPphys = allocpages(firstaddr, NKPML4E);
1549 * Allocate the initial number of kernel page table pages required to
1550 * bootstrap. We defer this until after all memory-size dependent
1551 * allocations are done (e.g. direct map), so that we don't have to
1552 * build in too much slop in our estimate.
1554 * Note that when NKPML4E > 1, we have an empty page underneath
1555 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1556 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1558 nkpt_init(*firstaddr);
1559 nkpdpe = NKPDPE(nkpt);
1561 KPTphys = allocpages(firstaddr, nkpt);
1562 KPDphys = allocpages(firstaddr, nkpdpe);
1565 * Connect the zero-filled PT pages to their PD entries. This
1566 * implicitly maps the PT pages at their correct locations within
1569 pd_p = (pd_entry_t *)KPDphys;
1570 for (i = 0; i < nkpt; i++)
1571 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1574 * Map from physical address zero to the end of loader preallocated
1575 * memory using 2MB pages. This replaces some of the PD entries
1578 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1579 /* Preset PG_M and PG_A because demotion expects it. */
1580 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1581 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1584 * Because we map the physical blocks in 2M pages, adjust firstaddr
1585 * to record the physical blocks we've actually mapped into kernel
1586 * virtual address space.
1588 if (*firstaddr < round_2mpage(KERNend))
1589 *firstaddr = round_2mpage(KERNend);
1591 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1592 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1593 for (i = 0; i < nkpdpe; i++)
1594 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1597 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1598 * the end of physical memory is not aligned to a 1GB page boundary,
1599 * then the residual physical memory is mapped with 2MB pages. Later,
1600 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1601 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1602 * that are partially used.
1604 pd_p = (pd_entry_t *)DMPDphys;
1605 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1606 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1607 /* Preset PG_M and PG_A because demotion expects it. */
1608 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1609 X86_PG_M | X86_PG_A | pg_nx;
1611 pdp_p = (pdp_entry_t *)DMPDPphys;
1612 for (i = 0; i < ndm1g; i++) {
1613 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1614 /* Preset PG_M and PG_A because demotion expects it. */
1615 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1616 X86_PG_M | X86_PG_A | pg_nx;
1618 for (j = 0; i < ndmpdp; i++, j++) {
1619 pdp_p[i] = DMPDphys + ptoa(j);
1620 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1624 * Instead of using a 1G page for the memory containing the kernel,
1625 * use 2M pages with read-only and no-execute permissions. (If using 1G
1626 * pages, this will partially overwrite the PDPEs above.)
1629 pd_p = (pd_entry_t *)DMPDkernphys;
1630 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1631 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1632 X86_PG_M | X86_PG_A | pg_nx |
1633 bootaddr_rwx(i << PDRSHIFT);
1634 for (i = 0; i < nkdmpde; i++)
1635 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1639 /* And recursively map PML4 to itself in order to get PTmap */
1640 p4_p = (pml4_entry_t *)KPML4phys;
1641 p4_p[PML4PML4I] = KPML4phys;
1642 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1644 /* Connect the Direct Map slot(s) up to the PML4. */
1645 for (i = 0; i < ndmpdpphys; i++) {
1646 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1647 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1650 /* Connect the KVA slots up to the PML4 */
1651 for (i = 0; i < NKPML4E; i++) {
1652 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1653 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1658 * Bootstrap the system enough to run with virtual memory.
1660 * On amd64 this is called after mapping has already been enabled
1661 * and just syncs the pmap module with what has already been done.
1662 * [We can't call it easily with mapping off since the kernel is not
1663 * mapped with PA == VA, hence we would have to relocate every address
1664 * from the linked base (virtual) address "KERNBASE" to the actual
1665 * (physical) address starting relative to 0]
1668 pmap_bootstrap(vm_paddr_t *firstaddr)
1671 pt_entry_t *pte, *pcpu_pte;
1672 struct region_descriptor r_gdt;
1673 uint64_t cr4, pcpu_phys;
1677 KERNend = *firstaddr;
1678 res = atop(KERNend - (vm_paddr_t)kernphys);
1684 * Create an initial set of page tables to run the kernel in.
1686 create_pagetables(firstaddr);
1688 pcpu_phys = allocpages(firstaddr, MAXCPU);
1691 * Add a physical memory segment (vm_phys_seg) corresponding to the
1692 * preallocated kernel page table pages so that vm_page structures
1693 * representing these pages will be created. The vm_page structures
1694 * are required for promotion of the corresponding kernel virtual
1695 * addresses to superpage mappings.
1697 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1700 * Account for the virtual addresses mapped by create_pagetables().
1702 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1703 virtual_end = VM_MAX_KERNEL_ADDRESS;
1706 * Enable PG_G global pages, then switch to the kernel page
1707 * table from the bootstrap page table. After the switch, it
1708 * is possible to enable SMEP and SMAP since PG_U bits are
1714 load_cr3(KPML4phys);
1715 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1717 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1722 * Initialize the kernel pmap (which is statically allocated).
1723 * Count bootstrap data as being resident in case any of this data is
1724 * later unmapped (using pmap_remove()) and freed.
1726 PMAP_LOCK_INIT(kernel_pmap);
1727 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1728 kernel_pmap->pm_cr3 = KPML4phys;
1729 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1730 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1731 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1732 kernel_pmap->pm_stats.resident_count = res;
1733 kernel_pmap->pm_flags = pmap_flags;
1736 * Initialize the TLB invalidations generation number lock.
1738 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1741 * Reserve some special page table entries/VA space for temporary
1744 #define SYSMAP(c, p, v, n) \
1745 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1751 * Crashdump maps. The first page is reused as CMAP1 for the
1754 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1755 CADDR1 = crashdumpmap;
1757 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1760 for (i = 0; i < MAXCPU; i++) {
1761 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1762 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1766 * Re-initialize PCPU area for BSP after switching.
1767 * Make hardware use gdt and common_tss from the new PCPU.
1769 STAILQ_INIT(&cpuhead);
1770 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1771 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1772 amd64_bsp_pcpu_init1(&__pcpu[0]);
1773 amd64_bsp_ist_init(&__pcpu[0]);
1774 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1775 sizeof(struct user_segment_descriptor));
1776 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1777 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1778 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1779 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1780 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1782 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1783 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1784 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1785 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1788 * Initialize the PAT MSR.
1789 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1790 * side-effect, invalidates stale PG_G TLB entries that might
1791 * have been created in our pre-boot environment.
1795 /* Initialize TLB Context Id. */
1796 if (pmap_pcid_enabled) {
1797 for (i = 0; i < MAXCPU; i++) {
1798 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1799 kernel_pmap->pm_pcids[i].pm_gen = 1;
1803 * PMAP_PCID_KERN + 1 is used for initialization of
1804 * proc0 pmap. The pmap' pcid state might be used by
1805 * EFIRT entry before first context switch, so it
1806 * needs to be valid.
1808 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1809 PCPU_SET(pcid_gen, 1);
1812 * pcpu area for APs is zeroed during AP startup.
1813 * pc_pcid_next and pc_pcid_gen are initialized by AP
1814 * during pcpu setup.
1816 load_cr4(rcr4() | CR4_PCIDE);
1821 * Setup the PAT MSR.
1830 /* Bail if this CPU doesn't implement PAT. */
1831 if ((cpu_feature & CPUID_PAT) == 0)
1834 /* Set default PAT index table. */
1835 for (i = 0; i < PAT_INDEX_SIZE; i++)
1837 pat_index[PAT_WRITE_BACK] = 0;
1838 pat_index[PAT_WRITE_THROUGH] = 1;
1839 pat_index[PAT_UNCACHEABLE] = 3;
1840 pat_index[PAT_WRITE_COMBINING] = 6;
1841 pat_index[PAT_WRITE_PROTECTED] = 5;
1842 pat_index[PAT_UNCACHED] = 2;
1845 * Initialize default PAT entries.
1846 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1847 * Program 5 and 6 as WP and WC.
1849 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1850 * mapping for a 2M page uses a PAT value with the bit 3 set due
1851 * to its overload with PG_PS.
1853 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1854 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1855 PAT_VALUE(2, PAT_UNCACHED) |
1856 PAT_VALUE(3, PAT_UNCACHEABLE) |
1857 PAT_VALUE(4, PAT_WRITE_BACK) |
1858 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1859 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1860 PAT_VALUE(7, PAT_UNCACHEABLE);
1864 load_cr4(cr4 & ~CR4_PGE);
1866 /* Disable caches (CD = 1, NW = 0). */
1868 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1870 /* Flushes caches and TLBs. */
1874 /* Update PAT and index table. */
1875 wrmsr(MSR_PAT, pat_msr);
1877 /* Flush caches and TLBs again. */
1881 /* Restore caches and PGE. */
1887 * Initialize a vm_page's machine-dependent fields.
1890 pmap_page_init(vm_page_t m)
1893 TAILQ_INIT(&m->md.pv_list);
1894 m->md.pat_mode = PAT_WRITE_BACK;
1897 static int pmap_allow_2m_x_ept;
1898 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1899 &pmap_allow_2m_x_ept, 0,
1900 "Allow executable superpage mappings in EPT");
1903 pmap_allow_2m_x_ept_recalculate(void)
1906 * SKL002, SKL012S. Since the EPT format is only used by
1907 * Intel CPUs, the vendor check is merely a formality.
1909 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1910 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1911 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1912 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1913 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1914 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1915 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1916 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1917 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1918 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1919 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1920 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1921 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1922 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1923 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1924 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1925 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1926 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1927 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1928 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1929 CPUID_TO_MODEL(cpu_id) == 0x85))))
1930 pmap_allow_2m_x_ept = 1;
1931 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1935 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1938 return (pmap->pm_type != PT_EPT || !executable ||
1939 !pmap_allow_2m_x_ept);
1944 pmap_init_pv_table(void)
1946 struct pmap_large_md_page *pvd;
1948 long start, end, highest, pv_npg;
1949 int domain, i, j, pages;
1952 * We strongly depend on the size being a power of two, so the assert
1953 * is overzealous. However, should the struct be resized to a
1954 * different power of two, the code below needs to be revisited.
1956 CTASSERT((sizeof(*pvd) == 64));
1959 * Calculate the size of the array.
1961 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
1962 pv_npg = howmany(pmap_last_pa, NBPDR);
1963 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
1965 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1966 if (pv_table == NULL)
1967 panic("%s: kva_alloc failed\n", __func__);
1970 * Iterate physical segments to allocate space for respective pages.
1974 for (i = 0; i < vm_phys_nsegs; i++) {
1975 end = vm_phys_segs[i].end / NBPDR;
1976 domain = vm_phys_segs[i].domain;
1981 start = highest + 1;
1982 pvd = &pv_table[start];
1984 pages = end - start + 1;
1985 s = round_page(pages * sizeof(*pvd));
1986 highest = start + (s / sizeof(*pvd)) - 1;
1988 for (j = 0; j < s; j += PAGE_SIZE) {
1989 vm_page_t m = vm_page_alloc_domain(NULL, 0,
1990 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
1992 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
1993 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
1996 for (j = 0; j < s / sizeof(*pvd); j++) {
1997 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
1998 TAILQ_INIT(&pvd->pv_page.pv_list);
1999 pvd->pv_page.pv_gen = 0;
2000 pvd->pv_page.pat_mode = 0;
2001 pvd->pv_invl_gen = 0;
2005 pvd = &pv_dummy_large;
2006 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2007 TAILQ_INIT(&pvd->pv_page.pv_list);
2008 pvd->pv_page.pv_gen = 0;
2009 pvd->pv_page.pat_mode = 0;
2010 pvd->pv_invl_gen = 0;
2014 pmap_init_pv_table(void)
2020 * Initialize the pool of pv list locks.
2022 for (i = 0; i < NPV_LIST_LOCKS; i++)
2023 rw_init(&pv_list_locks[i], "pmap pv list");
2026 * Calculate the size of the pv head table for superpages.
2028 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2031 * Allocate memory for the pv head table for superpages.
2033 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2035 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2036 for (i = 0; i < pv_npg; i++)
2037 TAILQ_INIT(&pv_table[i].pv_list);
2038 TAILQ_INIT(&pv_dummy.pv_list);
2043 * Initialize the pmap module.
2044 * Called by vm_init, to initialize any structures that the pmap
2045 * system needs to map virtual memory.
2050 struct pmap_preinit_mapping *ppim;
2052 int error, i, ret, skz63;
2054 /* L1TF, reserve page @0 unconditionally */
2055 vm_page_blacklist_add(0, bootverbose);
2057 /* Detect bare-metal Skylake Server and Skylake-X. */
2058 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2059 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2061 * Skylake-X errata SKZ63. Processor May Hang When
2062 * Executing Code In an HLE Transaction Region between
2063 * 40000000H and 403FFFFFH.
2065 * Mark the pages in the range as preallocated. It
2066 * seems to be impossible to distinguish between
2067 * Skylake Server and Skylake X.
2070 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2073 printf("SKZ63: skipping 4M RAM starting "
2074 "at physical 1G\n");
2075 for (i = 0; i < atop(0x400000); i++) {
2076 ret = vm_page_blacklist_add(0x40000000 +
2078 if (!ret && bootverbose)
2079 printf("page at %#lx already used\n",
2080 0x40000000 + ptoa(i));
2086 pmap_allow_2m_x_ept_recalculate();
2089 * Initialize the vm page array entries for the kernel pmap's
2092 PMAP_LOCK(kernel_pmap);
2093 for (i = 0; i < nkpt; i++) {
2094 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2095 KASSERT(mpte >= vm_page_array &&
2096 mpte < &vm_page_array[vm_page_array_size],
2097 ("pmap_init: page table page is out of range"));
2098 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2099 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2100 mpte->ref_count = 1;
2103 * Collect the page table pages that were replaced by a 2MB
2104 * page in create_pagetables(). They are zero filled.
2106 if (i << PDRSHIFT < KERNend &&
2107 pmap_insert_pt_page(kernel_pmap, mpte, false))
2108 panic("pmap_init: pmap_insert_pt_page failed");
2110 PMAP_UNLOCK(kernel_pmap);
2114 * If the kernel is running on a virtual machine, then it must assume
2115 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2116 * be prepared for the hypervisor changing the vendor and family that
2117 * are reported by CPUID. Consequently, the workaround for AMD Family
2118 * 10h Erratum 383 is enabled if the processor's feature set does not
2119 * include at least one feature that is only supported by older Intel
2120 * or newer AMD processors.
2122 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2123 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2124 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2126 workaround_erratum383 = 1;
2129 * Are large page mappings enabled?
2131 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2132 if (pg_ps_enabled) {
2133 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2134 ("pmap_init: can't assign to pagesizes[1]"));
2135 pagesizes[1] = NBPDR;
2139 * Initialize pv chunk lists.
2141 for (i = 0; i < PMAP_MEMDOM; i++) {
2142 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2143 TAILQ_INIT(&pv_chunks[i].pvc_list);
2145 pmap_init_pv_table();
2147 pmap_initialized = 1;
2148 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2149 ppim = pmap_preinit_mapping + i;
2152 /* Make the direct map consistent */
2153 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2154 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2155 ppim->sz, ppim->mode);
2159 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2160 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2163 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2164 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2165 (vmem_addr_t *)&qframe);
2167 panic("qframe allocation failed");
2170 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2171 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2172 lm_ents = LMEPML4I - LMSPML4I + 1;
2174 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2175 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2177 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2178 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2179 if (large_vmem == NULL) {
2180 printf("pmap: cannot create large map\n");
2183 for (i = 0; i < lm_ents; i++) {
2184 m = pmap_large_map_getptp_unlocked();
2185 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
2186 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2192 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2193 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2194 "Maximum number of PML4 entries for use by large map (tunable). "
2195 "Each entry corresponds to 512GB of address space.");
2197 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
2198 "2MB page mapping counters");
2200 static u_long pmap_pde_demotions;
2201 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2202 &pmap_pde_demotions, 0, "2MB page demotions");
2204 static u_long pmap_pde_mappings;
2205 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2206 &pmap_pde_mappings, 0, "2MB page mappings");
2208 static u_long pmap_pde_p_failures;
2209 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2210 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2212 static u_long pmap_pde_promotions;
2213 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2214 &pmap_pde_promotions, 0, "2MB page promotions");
2216 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
2217 "1GB page mapping counters");
2219 static u_long pmap_pdpe_demotions;
2220 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2221 &pmap_pdpe_demotions, 0, "1GB page demotions");
2223 /***************************************************
2224 * Low level helper routines.....
2225 ***************************************************/
2228 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2230 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2232 switch (pmap->pm_type) {
2235 /* Verify that both PAT bits are not set at the same time */
2236 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2237 ("Invalid PAT bits in entry %#lx", entry));
2239 /* Swap the PAT bits if one of them is set */
2240 if ((entry & x86_pat_bits) != 0)
2241 entry ^= x86_pat_bits;
2245 * Nothing to do - the memory attributes are represented
2246 * the same way for regular pages and superpages.
2250 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2257 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2260 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2261 pat_index[(int)mode] >= 0);
2265 * Determine the appropriate bits to set in a PTE or PDE for a specified
2269 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2271 int cache_bits, pat_flag, pat_idx;
2273 if (!pmap_is_valid_memattr(pmap, mode))
2274 panic("Unknown caching mode %d\n", mode);
2276 switch (pmap->pm_type) {
2279 /* The PAT bit is different for PTE's and PDE's. */
2280 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2282 /* Map the caching mode to a PAT index. */
2283 pat_idx = pat_index[mode];
2285 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2288 cache_bits |= pat_flag;
2290 cache_bits |= PG_NC_PCD;
2292 cache_bits |= PG_NC_PWT;
2296 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2300 panic("unsupported pmap type %d", pmap->pm_type);
2303 return (cache_bits);
2307 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2311 switch (pmap->pm_type) {
2314 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2317 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2320 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2327 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2329 int pat_flag, pat_idx;
2332 switch (pmap->pm_type) {
2335 /* The PAT bit is different for PTE's and PDE's. */
2336 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2338 if ((pte & pat_flag) != 0)
2340 if ((pte & PG_NC_PCD) != 0)
2342 if ((pte & PG_NC_PWT) != 0)
2346 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2347 panic("EPT PTE %#lx has no PAT memory type", pte);
2348 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2352 /* See pmap_init_pat(). */
2362 pmap_ps_enabled(pmap_t pmap)
2365 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2369 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2372 switch (pmap->pm_type) {
2379 * This is a little bogus since the generation number is
2380 * supposed to be bumped up when a region of the address
2381 * space is invalidated in the page tables.
2383 * In this case the old PDE entry is valid but yet we want
2384 * to make sure that any mappings using the old entry are
2385 * invalidated in the TLB.
2387 * The reason this works as expected is because we rendezvous
2388 * "all" host cpus and force any vcpu context to exit as a
2391 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2394 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2396 pde_store(pde, newpde);
2400 * After changing the page size for the specified virtual address in the page
2401 * table, flush the corresponding entries from the processor's TLB. Only the
2402 * calling processor's TLB is affected.
2404 * The calling thread must be pinned to a processor.
2407 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2411 if (pmap_type_guest(pmap))
2414 KASSERT(pmap->pm_type == PT_X86,
2415 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2417 PG_G = pmap_global_bit(pmap);
2419 if ((newpde & PG_PS) == 0)
2420 /* Demotion: flush a specific 2MB page mapping. */
2422 else if ((newpde & PG_G) == 0)
2424 * Promotion: flush every 4KB page mapping from the TLB
2425 * because there are too many to flush individually.
2430 * Promotion: flush every 4KB page mapping from the TLB,
2431 * including any global (PG_G) mappings.
2439 * For SMP, these functions have to use the IPI mechanism for coherence.
2441 * N.B.: Before calling any of the following TLB invalidation functions,
2442 * the calling processor must ensure that all stores updating a non-
2443 * kernel page table are globally performed. Otherwise, another
2444 * processor could cache an old, pre-update entry without being
2445 * invalidated. This can happen one of two ways: (1) The pmap becomes
2446 * active on another processor after its pm_active field is checked by
2447 * one of the following functions but before a store updating the page
2448 * table is globally performed. (2) The pmap becomes active on another
2449 * processor before its pm_active field is checked but due to
2450 * speculative loads one of the following functions stills reads the
2451 * pmap as inactive on the other processor.
2453 * The kernel page table is exempt because its pm_active field is
2454 * immutable. The kernel page table is always active on every
2459 * Interrupt the cpus that are executing in the guest context.
2460 * This will force the vcpu to exit and the cached EPT mappings
2461 * will be invalidated by the host before the next vmresume.
2463 static __inline void
2464 pmap_invalidate_ept(pmap_t pmap)
2469 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2470 ("pmap_invalidate_ept: absurd pm_active"));
2473 * The TLB mappings associated with a vcpu context are not
2474 * flushed each time a different vcpu is chosen to execute.
2476 * This is in contrast with a process's vtop mappings that
2477 * are flushed from the TLB on each context switch.
2479 * Therefore we need to do more than just a TLB shootdown on
2480 * the active cpus in 'pmap->pm_active'. To do this we keep
2481 * track of the number of invalidations performed on this pmap.
2483 * Each vcpu keeps a cache of this counter and compares it
2484 * just before a vmresume. If the counter is out-of-date an
2485 * invept will be done to flush stale mappings from the TLB.
2487 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2490 * Force the vcpu to exit and trap back into the hypervisor.
2492 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2493 ipi_selected(pmap->pm_active, ipinum);
2498 pmap_invalidate_cpu_mask(pmap_t pmap)
2501 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2505 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2506 const bool invpcid_works1)
2508 struct invpcid_descr d;
2509 uint64_t kcr3, ucr3;
2513 cpuid = PCPU_GET(cpuid);
2514 if (pmap == PCPU_GET(curpmap)) {
2515 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2517 * Because pm_pcid is recalculated on a
2518 * context switch, we must disable switching.
2519 * Otherwise, we might use a stale value
2523 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2524 if (invpcid_works1) {
2525 d.pcid = pcid | PMAP_PCID_USER_PT;
2528 invpcid(&d, INVPCID_ADDR);
2530 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2531 ucr3 = pmap->pm_ucr3 | pcid |
2532 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2533 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2538 pmap->pm_pcids[cpuid].pm_gen = 0;
2542 pmap->pm_pcids[i].pm_gen = 0;
2546 * The fence is between stores to pm_gen and the read of the
2547 * pm_active mask. We need to ensure that it is impossible
2548 * for us to miss the bit update in pm_active and
2549 * simultaneously observe a non-zero pm_gen in
2550 * pmap_activate_sw(), otherwise TLB update is missed.
2551 * Without the fence, IA32 allows such an outcome. Note that
2552 * pm_active is updated by a locked operation, which provides
2553 * the reciprocal fence.
2555 atomic_thread_fence_seq_cst();
2559 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2562 pmap_invalidate_page_pcid(pmap, va, true);
2566 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2569 pmap_invalidate_page_pcid(pmap, va, false);
2573 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2577 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2580 if (pmap_pcid_enabled)
2581 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2582 pmap_invalidate_page_pcid_noinvpcid);
2583 return (pmap_invalidate_page_nopcid);
2587 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2590 if (pmap_type_guest(pmap)) {
2591 pmap_invalidate_ept(pmap);
2595 KASSERT(pmap->pm_type == PT_X86,
2596 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2599 if (pmap == kernel_pmap) {
2602 if (pmap == PCPU_GET(curpmap))
2604 pmap_invalidate_page_mode(pmap, va);
2606 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2610 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2611 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2614 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2615 const bool invpcid_works1)
2617 struct invpcid_descr d;
2618 uint64_t kcr3, ucr3;
2622 cpuid = PCPU_GET(cpuid);
2623 if (pmap == PCPU_GET(curpmap)) {
2624 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2626 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2627 if (invpcid_works1) {
2628 d.pcid = pcid | PMAP_PCID_USER_PT;
2631 for (; d.addr < eva; d.addr += PAGE_SIZE)
2632 invpcid(&d, INVPCID_ADDR);
2634 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2635 ucr3 = pmap->pm_ucr3 | pcid |
2636 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2637 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2642 pmap->pm_pcids[cpuid].pm_gen = 0;
2646 pmap->pm_pcids[i].pm_gen = 0;
2648 /* See the comment in pmap_invalidate_page_pcid(). */
2649 atomic_thread_fence_seq_cst();
2653 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2657 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2661 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2665 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2669 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2673 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2677 if (pmap_pcid_enabled)
2678 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2679 pmap_invalidate_range_pcid_noinvpcid);
2680 return (pmap_invalidate_range_nopcid);
2684 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2688 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2689 pmap_invalidate_all(pmap);
2693 if (pmap_type_guest(pmap)) {
2694 pmap_invalidate_ept(pmap);
2698 KASSERT(pmap->pm_type == PT_X86,
2699 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2702 if (pmap == kernel_pmap) {
2703 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2706 if (pmap == PCPU_GET(curpmap)) {
2707 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2710 pmap_invalidate_range_mode(pmap, sva, eva);
2712 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2717 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2719 struct invpcid_descr d;
2720 uint64_t kcr3, ucr3;
2724 if (pmap == kernel_pmap) {
2725 if (invpcid_works1) {
2726 bzero(&d, sizeof(d));
2727 invpcid(&d, INVPCID_CTXGLOB);
2732 cpuid = PCPU_GET(cpuid);
2733 if (pmap == PCPU_GET(curpmap)) {
2735 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2736 if (invpcid_works1) {
2740 invpcid(&d, INVPCID_CTX);
2741 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2742 d.pcid |= PMAP_PCID_USER_PT;
2743 invpcid(&d, INVPCID_CTX);
2746 kcr3 = pmap->pm_cr3 | pcid;
2747 ucr3 = pmap->pm_ucr3;
2748 if (ucr3 != PMAP_NO_CR3) {
2749 ucr3 |= pcid | PMAP_PCID_USER_PT;
2750 pmap_pti_pcid_invalidate(ucr3, kcr3);
2757 pmap->pm_pcids[cpuid].pm_gen = 0;
2760 pmap->pm_pcids[i].pm_gen = 0;
2763 /* See the comment in pmap_invalidate_page_pcid(). */
2764 atomic_thread_fence_seq_cst();
2768 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2771 pmap_invalidate_all_pcid(pmap, true);
2775 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2778 pmap_invalidate_all_pcid(pmap, false);
2782 pmap_invalidate_all_nopcid(pmap_t pmap)
2785 if (pmap == kernel_pmap)
2787 else if (pmap == PCPU_GET(curpmap))
2791 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2794 if (pmap_pcid_enabled)
2795 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2796 pmap_invalidate_all_pcid_noinvpcid);
2797 return (pmap_invalidate_all_nopcid);
2801 pmap_invalidate_all(pmap_t pmap)
2804 if (pmap_type_guest(pmap)) {
2805 pmap_invalidate_ept(pmap);
2809 KASSERT(pmap->pm_type == PT_X86,
2810 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2813 pmap_invalidate_all_mode(pmap);
2814 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2819 pmap_invalidate_cache(void)
2829 cpuset_t invalidate; /* processors that invalidate their TLB */
2834 u_int store; /* processor that updates the PDE */
2838 pmap_update_pde_action(void *arg)
2840 struct pde_action *act = arg;
2842 if (act->store == PCPU_GET(cpuid))
2843 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2847 pmap_update_pde_teardown(void *arg)
2849 struct pde_action *act = arg;
2851 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2852 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2856 * Change the page size for the specified virtual address in a way that
2857 * prevents any possibility of the TLB ever having two entries that map the
2858 * same virtual address using different page sizes. This is the recommended
2859 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2860 * machine check exception for a TLB state that is improperly diagnosed as a
2864 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2866 struct pde_action act;
2867 cpuset_t active, other_cpus;
2871 cpuid = PCPU_GET(cpuid);
2872 other_cpus = all_cpus;
2873 CPU_CLR(cpuid, &other_cpus);
2874 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2877 active = pmap->pm_active;
2879 if (CPU_OVERLAP(&active, &other_cpus)) {
2881 act.invalidate = active;
2885 act.newpde = newpde;
2886 CPU_SET(cpuid, &active);
2887 smp_rendezvous_cpus(active,
2888 smp_no_rendezvous_barrier, pmap_update_pde_action,
2889 pmap_update_pde_teardown, &act);
2891 pmap_update_pde_store(pmap, pde, newpde);
2892 if (CPU_ISSET(cpuid, &active))
2893 pmap_update_pde_invalidate(pmap, va, newpde);
2899 * Normal, non-SMP, invalidation functions.
2902 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2904 struct invpcid_descr d;
2905 uint64_t kcr3, ucr3;
2908 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2912 KASSERT(pmap->pm_type == PT_X86,
2913 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2915 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2917 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2918 pmap->pm_ucr3 != PMAP_NO_CR3) {
2920 pcid = pmap->pm_pcids[0].pm_pcid;
2921 if (invpcid_works) {
2922 d.pcid = pcid | PMAP_PCID_USER_PT;
2925 invpcid(&d, INVPCID_ADDR);
2927 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2928 ucr3 = pmap->pm_ucr3 | pcid |
2929 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2930 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2934 } else if (pmap_pcid_enabled)
2935 pmap->pm_pcids[0].pm_gen = 0;
2939 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2941 struct invpcid_descr d;
2943 uint64_t kcr3, ucr3;
2945 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2949 KASSERT(pmap->pm_type == PT_X86,
2950 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2952 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2953 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2955 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2956 pmap->pm_ucr3 != PMAP_NO_CR3) {
2958 if (invpcid_works) {
2959 d.pcid = pmap->pm_pcids[0].pm_pcid |
2963 for (; d.addr < eva; d.addr += PAGE_SIZE)
2964 invpcid(&d, INVPCID_ADDR);
2966 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2967 pm_pcid | CR3_PCID_SAVE;
2968 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2969 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2970 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2974 } else if (pmap_pcid_enabled) {
2975 pmap->pm_pcids[0].pm_gen = 0;
2980 pmap_invalidate_all(pmap_t pmap)
2982 struct invpcid_descr d;
2983 uint64_t kcr3, ucr3;
2985 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2989 KASSERT(pmap->pm_type == PT_X86,
2990 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2992 if (pmap == kernel_pmap) {
2993 if (pmap_pcid_enabled && invpcid_works) {
2994 bzero(&d, sizeof(d));
2995 invpcid(&d, INVPCID_CTXGLOB);
2999 } else if (pmap == PCPU_GET(curpmap)) {
3000 if (pmap_pcid_enabled) {
3002 if (invpcid_works) {
3003 d.pcid = pmap->pm_pcids[0].pm_pcid;
3006 invpcid(&d, INVPCID_CTX);
3007 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3008 d.pcid |= PMAP_PCID_USER_PT;
3009 invpcid(&d, INVPCID_CTX);
3012 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3013 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3014 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3015 0].pm_pcid | PMAP_PCID_USER_PT;
3016 pmap_pti_pcid_invalidate(ucr3, kcr3);
3024 } else if (pmap_pcid_enabled) {
3025 pmap->pm_pcids[0].pm_gen = 0;
3030 pmap_invalidate_cache(void)
3037 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3040 pmap_update_pde_store(pmap, pde, newpde);
3041 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3042 pmap_update_pde_invalidate(pmap, va, newpde);
3044 pmap->pm_pcids[0].pm_gen = 0;
3049 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3053 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3054 * by a promotion that did not invalidate the 512 4KB page mappings
3055 * that might exist in the TLB. Consequently, at this point, the TLB
3056 * may hold both 4KB and 2MB page mappings for the address range [va,
3057 * va + NBPDR). Therefore, the entire range must be invalidated here.
3058 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3059 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3060 * single INVLPG suffices to invalidate the 2MB page mapping from the
3063 if ((pde & PG_PROMOTED) != 0)
3064 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3066 pmap_invalidate_page(pmap, va);
3069 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3070 (vm_offset_t sva, vm_offset_t eva))
3073 if ((cpu_feature & CPUID_SS) != 0)
3074 return (pmap_invalidate_cache_range_selfsnoop);
3075 if ((cpu_feature & CPUID_CLFSH) != 0)
3076 return (pmap_force_invalidate_cache_range);
3077 return (pmap_invalidate_cache_range_all);
3080 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3083 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3086 KASSERT((sva & PAGE_MASK) == 0,
3087 ("pmap_invalidate_cache_range: sva not page-aligned"));
3088 KASSERT((eva & PAGE_MASK) == 0,
3089 ("pmap_invalidate_cache_range: eva not page-aligned"));
3093 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3096 pmap_invalidate_cache_range_check_align(sva, eva);
3100 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3103 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3106 * XXX: Some CPUs fault, hang, or trash the local APIC
3107 * registers if we use CLFLUSH on the local APIC range. The
3108 * local APIC is always uncached, so we don't need to flush
3109 * for that range anyway.
3111 if (pmap_kextract(sva) == lapic_paddr)
3114 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3116 * Do per-cache line flush. Use a locked
3117 * instruction to insure that previous stores are
3118 * included in the write-back. The processor
3119 * propagates flush to other processors in the cache
3122 atomic_thread_fence_seq_cst();
3123 for (; sva < eva; sva += cpu_clflush_line_size)
3125 atomic_thread_fence_seq_cst();
3128 * Writes are ordered by CLFLUSH on Intel CPUs.
3130 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3132 for (; sva < eva; sva += cpu_clflush_line_size)
3134 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3140 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3143 pmap_invalidate_cache_range_check_align(sva, eva);
3144 pmap_invalidate_cache();
3148 * Remove the specified set of pages from the data and instruction caches.
3150 * In contrast to pmap_invalidate_cache_range(), this function does not
3151 * rely on the CPU's self-snoop feature, because it is intended for use
3152 * when moving pages into a different cache domain.
3155 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3157 vm_offset_t daddr, eva;
3161 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3162 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3163 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3164 pmap_invalidate_cache();
3167 atomic_thread_fence_seq_cst();
3168 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3170 for (i = 0; i < count; i++) {
3171 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3172 eva = daddr + PAGE_SIZE;
3173 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3181 atomic_thread_fence_seq_cst();
3182 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3188 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3191 pmap_invalidate_cache_range_check_align(sva, eva);
3193 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3194 pmap_force_invalidate_cache_range(sva, eva);
3198 /* See comment in pmap_force_invalidate_cache_range(). */
3199 if (pmap_kextract(sva) == lapic_paddr)
3202 atomic_thread_fence_seq_cst();
3203 for (; sva < eva; sva += cpu_clflush_line_size)
3205 atomic_thread_fence_seq_cst();
3209 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3213 int error, pte_bits;
3215 KASSERT((spa & PAGE_MASK) == 0,
3216 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3217 KASSERT((epa & PAGE_MASK) == 0,
3218 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3220 if (spa < dmaplimit) {
3221 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3223 if (dmaplimit >= epa)
3228 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3230 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3232 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3233 pte = vtopte(vaddr);
3234 for (; spa < epa; spa += PAGE_SIZE) {
3236 pte_store(pte, spa | pte_bits);
3238 /* XXXKIB atomic inside flush_cache_range are excessive */
3239 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3242 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3246 * Routine: pmap_extract
3248 * Extract the physical page address associated
3249 * with the given map/virtual_address pair.
3252 pmap_extract(pmap_t pmap, vm_offset_t va)
3256 pt_entry_t *pte, PG_V;
3260 PG_V = pmap_valid_bit(pmap);
3262 pdpe = pmap_pdpe(pmap, va);
3263 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3264 if ((*pdpe & PG_PS) != 0)
3265 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3267 pde = pmap_pdpe_to_pde(pdpe, va);
3268 if ((*pde & PG_V) != 0) {
3269 if ((*pde & PG_PS) != 0) {
3270 pa = (*pde & PG_PS_FRAME) |
3273 pte = pmap_pde_to_pte(pde, va);
3274 pa = (*pte & PG_FRAME) |
3285 * Routine: pmap_extract_and_hold
3287 * Atomically extract and hold the physical page
3288 * with the given pmap and virtual address pair
3289 * if that mapping permits the given protection.
3292 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3294 pd_entry_t pde, *pdep;
3295 pt_entry_t pte, PG_RW, PG_V;
3299 PG_RW = pmap_rw_bit(pmap);
3300 PG_V = pmap_valid_bit(pmap);
3303 pdep = pmap_pde(pmap, va);
3304 if (pdep != NULL && (pde = *pdep)) {
3306 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3307 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3310 pte = *pmap_pde_to_pte(pdep, va);
3311 if ((pte & PG_V) != 0 &&
3312 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3313 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3315 if (m != NULL && !vm_page_wire_mapped(m))
3323 pmap_kextract(vm_offset_t va)
3328 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3329 pa = DMAP_TO_PHYS(va);
3330 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3331 pa = pmap_large_map_kextract(va);
3335 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3338 * Beware of a concurrent promotion that changes the
3339 * PDE at this point! For example, vtopte() must not
3340 * be used to access the PTE because it would use the
3341 * new PDE. It is, however, safe to use the old PDE
3342 * because the page table page is preserved by the
3345 pa = *pmap_pde_to_pte(&pde, va);
3346 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3352 /***************************************************
3353 * Low level mapping routines.....
3354 ***************************************************/
3357 * Add a wired page to the kva.
3358 * Note: not SMP coherent.
3361 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3366 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3369 static __inline void
3370 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3376 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3377 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3381 * Remove a page from the kernel pagetables.
3382 * Note: not SMP coherent.
3385 pmap_kremove(vm_offset_t va)
3394 * Used to map a range of physical addresses into kernel
3395 * virtual address space.
3397 * The value passed in '*virt' is a suggested virtual address for
3398 * the mapping. Architectures which can support a direct-mapped
3399 * physical to virtual region can return the appropriate address
3400 * within that region, leaving '*virt' unchanged. Other
3401 * architectures should map the pages starting at '*virt' and
3402 * update '*virt' with the first usable address after the mapped
3406 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3408 return PHYS_TO_DMAP(start);
3413 * Add a list of wired pages to the kva
3414 * this routine is only used for temporary
3415 * kernel mappings that do not need to have
3416 * page modification or references recorded.
3417 * Note that old mappings are simply written
3418 * over. The page *must* be wired.
3419 * Note: SMP coherent. Uses a ranged shootdown IPI.
3422 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3424 pt_entry_t *endpte, oldpte, pa, *pte;
3430 endpte = pte + count;
3431 while (pte < endpte) {
3433 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3434 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3435 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3437 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3441 if (__predict_false((oldpte & X86_PG_V) != 0))
3442 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3447 * This routine tears out page mappings from the
3448 * kernel -- it is meant only for temporary mappings.
3449 * Note: SMP coherent. Uses a ranged shootdown IPI.
3452 pmap_qremove(vm_offset_t sva, int count)
3457 while (count-- > 0) {
3458 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3462 pmap_invalidate_range(kernel_pmap, sva, va);
3465 /***************************************************
3466 * Page table page management routines.....
3467 ***************************************************/
3469 * Schedule the specified unused page table page to be freed. Specifically,
3470 * add the page to the specified list of pages that will be released to the
3471 * physical memory manager after the TLB has been updated.
3473 static __inline void
3474 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3475 boolean_t set_PG_ZERO)
3479 m->flags |= PG_ZERO;
3481 m->flags &= ~PG_ZERO;
3482 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3486 * Inserts the specified page table page into the specified pmap's collection
3487 * of idle page table pages. Each of a pmap's page table pages is responsible
3488 * for mapping a distinct range of virtual addresses. The pmap's collection is
3489 * ordered by this virtual address range.
3491 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3494 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3497 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3498 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3499 return (vm_radix_insert(&pmap->pm_root, mpte));
3503 * Removes the page table page mapping the specified virtual address from the
3504 * specified pmap's collection of idle page table pages, and returns it.
3505 * Otherwise, returns NULL if there is no page table page corresponding to the
3506 * specified virtual address.
3508 static __inline vm_page_t
3509 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3512 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3513 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3517 * Decrements a page table page's reference count, which is used to record the
3518 * number of valid page table entries within the page. If the reference count
3519 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3520 * page table page was unmapped and FALSE otherwise.
3522 static inline boolean_t
3523 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3527 if (m->ref_count == 0) {
3528 _pmap_unwire_ptp(pmap, va, m, free);
3535 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3538 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3540 * unmap the page table page
3542 if (m->pindex >= (NUPDE + NUPDPE)) {
3545 pml4 = pmap_pml4e(pmap, va);
3547 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3548 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3551 } else if (m->pindex >= NUPDE) {
3554 pdp = pmap_pdpe(pmap, va);
3559 pd = pmap_pde(pmap, va);
3562 pmap_resident_count_dec(pmap, 1);
3563 if (m->pindex < NUPDE) {
3564 /* We just released a PT, unhold the matching PD */
3567 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3568 pmap_unwire_ptp(pmap, va, pdpg, free);
3570 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3571 /* We just released a PD, unhold the matching PDP */
3574 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3575 pmap_unwire_ptp(pmap, va, pdppg, free);
3579 * Put page on a list so that it is released after
3580 * *ALL* TLB shootdown is done
3582 pmap_add_delayed_free_list(m, free, TRUE);
3586 * After removing a page table entry, this routine is used to
3587 * conditionally free the page, and manage the reference count.
3590 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3591 struct spglist *free)
3595 if (va >= VM_MAXUSER_ADDRESS)
3597 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3598 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3599 return (pmap_unwire_ptp(pmap, va, mpte, free));
3603 pmap_pinit0(pmap_t pmap)
3609 PMAP_LOCK_INIT(pmap);
3610 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3611 pmap->pm_pml4u = NULL;
3612 pmap->pm_cr3 = KPML4phys;
3613 /* hack to keep pmap_pti_pcid_invalidate() alive */
3614 pmap->pm_ucr3 = PMAP_NO_CR3;
3615 pmap->pm_root.rt_root = 0;
3616 CPU_ZERO(&pmap->pm_active);
3617 TAILQ_INIT(&pmap->pm_pvchunk);
3618 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3619 pmap->pm_flags = pmap_flags;
3621 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3622 pmap->pm_pcids[i].pm_gen = 1;
3624 pmap_activate_boot(pmap);
3629 p->p_md.md_flags |= P_MD_KPTI;
3632 pmap_thread_init_invl_gen(td);
3634 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3635 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3636 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3642 pmap_pinit_pml4(vm_page_t pml4pg)
3644 pml4_entry_t *pm_pml4;
3647 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3649 /* Wire in kernel global address entries. */
3650 for (i = 0; i < NKPML4E; i++) {
3651 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3654 for (i = 0; i < ndmpdpphys; i++) {
3655 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3659 /* install self-referential address mapping entry(s) */
3660 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3661 X86_PG_A | X86_PG_M;
3663 /* install large map entries if configured */
3664 for (i = 0; i < lm_ents; i++)
3665 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3669 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3671 pml4_entry_t *pm_pml4;
3674 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3675 for (i = 0; i < NPML4EPG; i++)
3676 pm_pml4[i] = pti_pml4[i];
3680 * Initialize a preallocated and zeroed pmap structure,
3681 * such as one in a vmspace structure.
3684 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3686 vm_page_t pml4pg, pml4pgu;
3687 vm_paddr_t pml4phys;
3691 * allocate the page directory page
3693 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3694 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3696 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3697 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3699 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3700 pmap->pm_pcids[i].pm_gen = 0;
3702 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3703 pmap->pm_ucr3 = PMAP_NO_CR3;
3704 pmap->pm_pml4u = NULL;
3706 pmap->pm_type = pm_type;
3707 if ((pml4pg->flags & PG_ZERO) == 0)
3708 pagezero(pmap->pm_pml4);
3711 * Do not install the host kernel mappings in the nested page
3712 * tables. These mappings are meaningless in the guest physical
3714 * Install minimal kernel mappings in PTI case.
3716 if (pm_type == PT_X86) {
3717 pmap->pm_cr3 = pml4phys;
3718 pmap_pinit_pml4(pml4pg);
3719 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3720 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3721 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3722 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3723 VM_PAGE_TO_PHYS(pml4pgu));
3724 pmap_pinit_pml4_pti(pml4pgu);
3725 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3727 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3728 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3729 pkru_free_range, pmap, M_NOWAIT);
3733 pmap->pm_root.rt_root = 0;
3734 CPU_ZERO(&pmap->pm_active);
3735 TAILQ_INIT(&pmap->pm_pvchunk);
3736 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3737 pmap->pm_flags = flags;
3738 pmap->pm_eptgen = 0;
3744 pmap_pinit(pmap_t pmap)
3747 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3751 * This routine is called if the desired page table page does not exist.
3753 * If page table page allocation fails, this routine may sleep before
3754 * returning NULL. It sleeps only if a lock pointer was given.
3756 * Note: If a page allocation fails at page table level two or three,
3757 * one or two pages may be held during the wait, only to be released
3758 * afterwards. This conservative approach is easily argued to avoid
3762 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3764 vm_page_t m, pdppg, pdpg;
3765 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3767 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3769 PG_A = pmap_accessed_bit(pmap);
3770 PG_M = pmap_modified_bit(pmap);
3771 PG_V = pmap_valid_bit(pmap);
3772 PG_RW = pmap_rw_bit(pmap);
3775 * Allocate a page table page.
3777 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3778 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3779 if (lockp != NULL) {
3780 RELEASE_PV_LIST_LOCK(lockp);
3782 PMAP_ASSERT_NOT_IN_DI();
3788 * Indicate the need to retry. While waiting, the page table
3789 * page may have been allocated.
3793 if ((m->flags & PG_ZERO) == 0)
3797 * Map the pagetable page into the process address space, if
3798 * it isn't already there.
3801 if (ptepindex >= (NUPDE + NUPDPE)) {
3802 pml4_entry_t *pml4, *pml4u;
3803 vm_pindex_t pml4index;
3805 /* Wire up a new PDPE page */
3806 pml4index = ptepindex - (NUPDE + NUPDPE);
3807 pml4 = &pmap->pm_pml4[pml4index];
3808 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3809 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3811 * PTI: Make all user-space mappings in the
3812 * kernel-mode page table no-execute so that
3813 * we detect any programming errors that leave
3814 * the kernel-mode page table active on return
3817 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3820 pml4u = &pmap->pm_pml4u[pml4index];
3821 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3825 } else if (ptepindex >= NUPDE) {
3826 vm_pindex_t pml4index;
3827 vm_pindex_t pdpindex;
3831 /* Wire up a new PDE page */
3832 pdpindex = ptepindex - NUPDE;
3833 pml4index = pdpindex >> NPML4EPGSHIFT;
3835 pml4 = &pmap->pm_pml4[pml4index];
3836 if ((*pml4 & PG_V) == 0) {
3837 /* Have to allocate a new pdp, recurse */
3838 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3840 vm_page_unwire_noq(m);
3841 vm_page_free_zero(m);
3845 /* Add reference to pdp page */
3846 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3849 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3851 /* Now find the pdp page */
3852 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3853 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3856 vm_pindex_t pml4index;
3857 vm_pindex_t pdpindex;
3862 /* Wire up a new PTE page */
3863 pdpindex = ptepindex >> NPDPEPGSHIFT;
3864 pml4index = pdpindex >> NPML4EPGSHIFT;
3866 /* First, find the pdp and check that its valid. */
3867 pml4 = &pmap->pm_pml4[pml4index];
3868 if ((*pml4 & PG_V) == 0) {
3869 /* Have to allocate a new pd, recurse */
3870 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3872 vm_page_unwire_noq(m);
3873 vm_page_free_zero(m);
3876 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3877 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3879 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3880 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3881 if ((*pdp & PG_V) == 0) {
3882 /* Have to allocate a new pd, recurse */
3883 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3885 vm_page_unwire_noq(m);
3886 vm_page_free_zero(m);
3890 /* Add reference to the pd page */
3891 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3895 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3897 /* Now we know where the page directory page is */
3898 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3899 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3902 pmap_resident_count_inc(pmap, 1);
3908 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3910 vm_pindex_t pdpindex, ptepindex;
3911 pdp_entry_t *pdpe, PG_V;
3914 PG_V = pmap_valid_bit(pmap);
3917 pdpe = pmap_pdpe(pmap, va);
3918 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3919 /* Add a reference to the pd page. */
3920 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3923 /* Allocate a pd page. */
3924 ptepindex = pmap_pde_pindex(va);
3925 pdpindex = ptepindex >> NPDPEPGSHIFT;
3926 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3927 if (pdpg == NULL && lockp != NULL)
3934 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3936 vm_pindex_t ptepindex;
3937 pd_entry_t *pd, PG_V;
3940 PG_V = pmap_valid_bit(pmap);
3943 * Calculate pagetable page index
3945 ptepindex = pmap_pde_pindex(va);
3948 * Get the page directory entry
3950 pd = pmap_pde(pmap, va);
3953 * This supports switching from a 2MB page to a
3956 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3957 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3959 * Invalidation of the 2MB page mapping may have caused
3960 * the deallocation of the underlying PD page.
3967 * If the page table page is mapped, we just increment the
3968 * hold count, and activate it.
3970 if (pd != NULL && (*pd & PG_V) != 0) {
3971 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3975 * Here if the pte page isn't mapped, or if it has been
3978 m = _pmap_allocpte(pmap, ptepindex, lockp);
3979 if (m == NULL && lockp != NULL)
3986 /***************************************************
3987 * Pmap allocation/deallocation routines.
3988 ***************************************************/
3991 * Release any resources held by the given physical map.
3992 * Called when a pmap initialized by pmap_pinit is being released.
3993 * Should only be called if the map contains no valid mappings.
3996 pmap_release(pmap_t pmap)
4001 KASSERT(pmap->pm_stats.resident_count == 0,
4002 ("pmap_release: pmap resident count %ld != 0",
4003 pmap->pm_stats.resident_count));
4004 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4005 ("pmap_release: pmap has reserved page table page(s)"));
4006 KASSERT(CPU_EMPTY(&pmap->pm_active),
4007 ("releasing active pmap %p", pmap));
4009 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
4011 for (i = 0; i < NKPML4E; i++) /* KVA */
4012 pmap->pm_pml4[KPML4BASE + i] = 0;
4013 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4014 pmap->pm_pml4[DMPML4I + i] = 0;
4015 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
4016 for (i = 0; i < lm_ents; i++) /* Large Map */
4017 pmap->pm_pml4[LMSPML4I + i] = 0;
4019 vm_page_unwire_noq(m);
4020 vm_page_free_zero(m);
4022 if (pmap->pm_pml4u != NULL) {
4023 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
4024 vm_page_unwire_noq(m);
4027 if (pmap->pm_type == PT_X86 &&
4028 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4029 rangeset_fini(&pmap->pm_pkru);
4033 kvm_size(SYSCTL_HANDLER_ARGS)
4035 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4037 return sysctl_handle_long(oidp, &ksize, 0, req);
4039 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
4040 0, 0, kvm_size, "LU", "Size of KVM");
4043 kvm_free(SYSCTL_HANDLER_ARGS)
4045 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4047 return sysctl_handle_long(oidp, &kfree, 0, req);
4049 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
4050 0, 0, kvm_free, "LU", "Amount of KVM free");
4053 * Allocate physical memory for the vm_page array and map it into KVA,
4054 * attempting to back the vm_pages with domain-local memory.
4057 pmap_page_array_startup(long pages)
4060 pd_entry_t *pde, newpdir;
4061 vm_offset_t va, start, end;
4066 vm_page_array_size = pages;
4068 start = VM_MIN_KERNEL_ADDRESS;
4069 end = start + pages * sizeof(struct vm_page);
4070 for (va = start; va < end; va += NBPDR) {
4071 pfn = first_page + (va - start) / sizeof(struct vm_page);
4072 domain = _vm_phys_domain(ptoa(pfn));
4073 pdpe = pmap_pdpe(kernel_pmap, va);
4074 if ((*pdpe & X86_PG_V) == 0) {
4075 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4077 pagezero((void *)PHYS_TO_DMAP(pa));
4078 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4079 X86_PG_A | X86_PG_M);
4081 pde = pmap_pdpe_to_pde(pdpe, va);
4082 if ((*pde & X86_PG_V) != 0)
4083 panic("Unexpected pde");
4084 pa = vm_phys_early_alloc(domain, NBPDR);
4085 for (i = 0; i < NPDEPG; i++)
4086 dump_add_page(pa + i * PAGE_SIZE);
4087 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4088 X86_PG_M | PG_PS | pg_g | pg_nx);
4089 pde_store(pde, newpdir);
4091 vm_page_array = (vm_page_t)start;
4095 * grow the number of kernel page table entries, if needed
4098 pmap_growkernel(vm_offset_t addr)
4102 pd_entry_t *pde, newpdir;
4105 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4108 * Return if "addr" is within the range of kernel page table pages
4109 * that were preallocated during pmap bootstrap. Moreover, leave
4110 * "kernel_vm_end" and the kernel page table as they were.
4112 * The correctness of this action is based on the following
4113 * argument: vm_map_insert() allocates contiguous ranges of the
4114 * kernel virtual address space. It calls this function if a range
4115 * ends after "kernel_vm_end". If the kernel is mapped between
4116 * "kernel_vm_end" and "addr", then the range cannot begin at
4117 * "kernel_vm_end". In fact, its beginning address cannot be less
4118 * than the kernel. Thus, there is no immediate need to allocate
4119 * any new kernel page table pages between "kernel_vm_end" and
4122 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4125 addr = roundup2(addr, NBPDR);
4126 if (addr - 1 >= vm_map_max(kernel_map))
4127 addr = vm_map_max(kernel_map);
4128 while (kernel_vm_end < addr) {
4129 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4130 if ((*pdpe & X86_PG_V) == 0) {
4131 /* We need a new PDP entry */
4132 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4133 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4134 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4136 panic("pmap_growkernel: no memory to grow kernel");
4137 if ((nkpg->flags & PG_ZERO) == 0)
4138 pmap_zero_page(nkpg);
4139 paddr = VM_PAGE_TO_PHYS(nkpg);
4140 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4141 X86_PG_A | X86_PG_M);
4142 continue; /* try again */
4144 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4145 if ((*pde & X86_PG_V) != 0) {
4146 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4147 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4148 kernel_vm_end = vm_map_max(kernel_map);
4154 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4155 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4158 panic("pmap_growkernel: no memory to grow kernel");
4159 if ((nkpg->flags & PG_ZERO) == 0)
4160 pmap_zero_page(nkpg);
4161 paddr = VM_PAGE_TO_PHYS(nkpg);
4162 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4163 pde_store(pde, newpdir);
4165 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4166 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4167 kernel_vm_end = vm_map_max(kernel_map);
4174 /***************************************************
4175 * page management routines.
4176 ***************************************************/
4178 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4179 CTASSERT(_NPCM == 3);
4180 CTASSERT(_NPCPV == 168);
4182 static __inline struct pv_chunk *
4183 pv_to_chunk(pv_entry_t pv)
4186 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4189 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4191 #define PC_FREE0 0xfffffffffffffffful
4192 #define PC_FREE1 0xfffffffffffffffful
4193 #define PC_FREE2 0x000000fffffffffful
4195 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4198 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4200 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4201 "Current number of pv entry chunks");
4202 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4203 "Current number of pv entry chunks allocated");
4204 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4205 "Current number of pv entry chunks frees");
4206 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4207 "Number of times tried to get a chunk page but failed.");
4209 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4210 static int pv_entry_spare;
4212 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4213 "Current number of pv entry frees");
4214 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4215 "Current number of pv entry allocs");
4216 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4217 "Current number of pv entries");
4218 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4219 "Current number of spare pv entries");
4223 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4228 pmap_invalidate_all(pmap);
4229 if (pmap != locked_pmap)
4232 pmap_delayed_invl_finish();
4236 * We are in a serious low memory condition. Resort to
4237 * drastic measures to free some pages so we can allocate
4238 * another pv entry chunk.
4240 * Returns NULL if PV entries were reclaimed from the specified pmap.
4242 * We do not, however, unmap 2mpages because subsequent accesses will
4243 * allocate per-page pv entries until repromotion occurs, thereby
4244 * exacerbating the shortage of free pv entries.
4247 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4249 struct pv_chunks_list *pvc;
4250 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4251 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4252 struct md_page *pvh;
4254 pmap_t next_pmap, pmap;
4255 pt_entry_t *pte, tpte;
4256 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4260 struct spglist free;
4262 int bit, field, freed;
4265 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4266 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4269 PG_G = PG_A = PG_M = PG_RW = 0;
4271 bzero(&pc_marker_b, sizeof(pc_marker_b));
4272 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4273 pc_marker = (struct pv_chunk *)&pc_marker_b;
4274 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4277 * A delayed invalidation block should already be active if
4278 * pmap_advise() or pmap_remove() called this function by way
4279 * of pmap_demote_pde_locked().
4281 start_di = pmap_not_in_di();
4283 pvc = &pv_chunks[domain];
4284 mtx_lock(&pvc->pvc_lock);
4285 pvc->active_reclaims++;
4286 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4287 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4288 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4289 SLIST_EMPTY(&free)) {
4290 next_pmap = pc->pc_pmap;
4291 if (next_pmap == NULL) {
4293 * The next chunk is a marker. However, it is
4294 * not our marker, so active_reclaims must be
4295 * > 1. Consequently, the next_chunk code
4296 * will not rotate the pv_chunks list.
4300 mtx_unlock(&pvc->pvc_lock);
4303 * A pv_chunk can only be removed from the pc_lru list
4304 * when both pc_chunks_mutex is owned and the
4305 * corresponding pmap is locked.
4307 if (pmap != next_pmap) {
4308 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4311 /* Avoid deadlock and lock recursion. */
4312 if (pmap > locked_pmap) {
4313 RELEASE_PV_LIST_LOCK(lockp);
4316 pmap_delayed_invl_start();
4317 mtx_lock(&pvc->pvc_lock);
4319 } else if (pmap != locked_pmap) {
4320 if (PMAP_TRYLOCK(pmap)) {
4322 pmap_delayed_invl_start();
4323 mtx_lock(&pvc->pvc_lock);
4326 pmap = NULL; /* pmap is not locked */
4327 mtx_lock(&pvc->pvc_lock);
4328 pc = TAILQ_NEXT(pc_marker, pc_lru);
4330 pc->pc_pmap != next_pmap)
4334 } else if (start_di)
4335 pmap_delayed_invl_start();
4336 PG_G = pmap_global_bit(pmap);
4337 PG_A = pmap_accessed_bit(pmap);
4338 PG_M = pmap_modified_bit(pmap);
4339 PG_RW = pmap_rw_bit(pmap);
4343 * Destroy every non-wired, 4 KB page mapping in the chunk.
4346 for (field = 0; field < _NPCM; field++) {
4347 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4348 inuse != 0; inuse &= ~(1UL << bit)) {
4350 pv = &pc->pc_pventry[field * 64 + bit];
4352 pde = pmap_pde(pmap, va);
4353 if ((*pde & PG_PS) != 0)
4355 pte = pmap_pde_to_pte(pde, va);
4356 if ((*pte & PG_W) != 0)
4358 tpte = pte_load_clear(pte);
4359 if ((tpte & PG_G) != 0)
4360 pmap_invalidate_page(pmap, va);
4361 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4362 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4364 if ((tpte & PG_A) != 0)
4365 vm_page_aflag_set(m, PGA_REFERENCED);
4366 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4367 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4369 if (TAILQ_EMPTY(&m->md.pv_list) &&
4370 (m->flags & PG_FICTITIOUS) == 0) {
4371 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4372 if (TAILQ_EMPTY(&pvh->pv_list)) {
4373 vm_page_aflag_clear(m,
4377 pmap_delayed_invl_page(m);
4378 pc->pc_map[field] |= 1UL << bit;
4379 pmap_unuse_pt(pmap, va, *pde, &free);
4384 mtx_lock(&pvc->pvc_lock);
4387 /* Every freed mapping is for a 4 KB page. */
4388 pmap_resident_count_dec(pmap, freed);
4389 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4390 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4391 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4392 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4393 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4394 pc->pc_map[2] == PC_FREE2) {
4395 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4396 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4397 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4398 /* Entire chunk is free; return it. */
4399 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4400 dump_drop_page(m_pc->phys_addr);
4401 mtx_lock(&pvc->pvc_lock);
4402 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4405 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4406 mtx_lock(&pvc->pvc_lock);
4407 /* One freed pv entry in locked_pmap is sufficient. */
4408 if (pmap == locked_pmap)
4411 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4412 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4413 if (pvc->active_reclaims == 1 && pmap != NULL) {
4415 * Rotate the pv chunks list so that we do not
4416 * scan the same pv chunks that could not be
4417 * freed (because they contained a wired
4418 * and/or superpage mapping) on every
4419 * invocation of reclaim_pv_chunk().
4421 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4422 MPASS(pc->pc_pmap != NULL);
4423 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4424 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4428 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4429 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4430 pvc->active_reclaims--;
4431 mtx_unlock(&pvc->pvc_lock);
4432 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4433 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4434 m_pc = SLIST_FIRST(&free);
4435 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4436 /* Recycle a freed page table page. */
4437 m_pc->ref_count = 1;
4439 vm_page_free_pages_toq(&free, true);
4444 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4449 domain = PCPU_GET(domain);
4450 for (i = 0; i < vm_ndomains; i++) {
4451 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4454 domain = (domain + 1) % vm_ndomains;
4461 * free the pv_entry back to the free list
4464 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4466 struct pv_chunk *pc;
4467 int idx, field, bit;
4469 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4470 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4471 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4472 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4473 pc = pv_to_chunk(pv);
4474 idx = pv - &pc->pc_pventry[0];
4477 pc->pc_map[field] |= 1ul << bit;
4478 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4479 pc->pc_map[2] != PC_FREE2) {
4480 /* 98% of the time, pc is already at the head of the list. */
4481 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4482 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4483 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4487 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4492 free_pv_chunk_dequeued(struct pv_chunk *pc)
4496 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4497 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4498 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4499 /* entire chunk is free, return it */
4500 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4501 dump_drop_page(m->phys_addr);
4502 vm_page_unwire_noq(m);
4507 free_pv_chunk(struct pv_chunk *pc)
4509 struct pv_chunks_list *pvc;
4511 pvc = &pv_chunks[pc_to_domain(pc)];
4512 mtx_lock(&pvc->pvc_lock);
4513 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4514 mtx_unlock(&pvc->pvc_lock);
4515 free_pv_chunk_dequeued(pc);
4519 free_pv_chunk_batch(struct pv_chunklist *batch)
4521 struct pv_chunks_list *pvc;
4522 struct pv_chunk *pc, *npc;
4525 for (i = 0; i < vm_ndomains; i++) {
4526 if (TAILQ_EMPTY(&batch[i]))
4528 pvc = &pv_chunks[i];
4529 mtx_lock(&pvc->pvc_lock);
4530 TAILQ_FOREACH(pc, &batch[i], pc_list) {
4531 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4533 mtx_unlock(&pvc->pvc_lock);
4536 for (i = 0; i < vm_ndomains; i++) {
4537 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
4538 free_pv_chunk_dequeued(pc);
4544 * Returns a new PV entry, allocating a new PV chunk from the system when
4545 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4546 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4549 * The given PV list lock may be released.
4552 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4554 struct pv_chunks_list *pvc;
4557 struct pv_chunk *pc;
4560 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4561 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4563 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4565 for (field = 0; field < _NPCM; field++) {
4566 if (pc->pc_map[field]) {
4567 bit = bsfq(pc->pc_map[field]);
4571 if (field < _NPCM) {
4572 pv = &pc->pc_pventry[field * 64 + bit];
4573 pc->pc_map[field] &= ~(1ul << bit);
4574 /* If this was the last item, move it to tail */
4575 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4576 pc->pc_map[2] == 0) {
4577 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4578 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4581 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4582 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4586 /* No free items, allocate another chunk */
4587 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4590 if (lockp == NULL) {
4591 PV_STAT(pc_chunk_tryfail++);
4594 m = reclaim_pv_chunk(pmap, lockp);
4598 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4599 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4600 dump_add_page(m->phys_addr);
4601 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4603 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4604 pc->pc_map[1] = PC_FREE1;
4605 pc->pc_map[2] = PC_FREE2;
4606 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
4607 mtx_lock(&pvc->pvc_lock);
4608 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4609 mtx_unlock(&pvc->pvc_lock);
4610 pv = &pc->pc_pventry[0];
4611 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4612 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4613 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4618 * Returns the number of one bits within the given PV chunk map.
4620 * The erratas for Intel processors state that "POPCNT Instruction May
4621 * Take Longer to Execute Than Expected". It is believed that the
4622 * issue is the spurious dependency on the destination register.
4623 * Provide a hint to the register rename logic that the destination
4624 * value is overwritten, by clearing it, as suggested in the
4625 * optimization manual. It should be cheap for unaffected processors
4628 * Reference numbers for erratas are
4629 * 4th Gen Core: HSD146
4630 * 5th Gen Core: BDM85
4631 * 6th Gen Core: SKL029
4634 popcnt_pc_map_pq(uint64_t *map)
4638 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4639 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4640 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4641 : "=&r" (result), "=&r" (tmp)
4642 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4647 * Ensure that the number of spare PV entries in the specified pmap meets or
4648 * exceeds the given count, "needed".
4650 * The given PV list lock may be released.
4653 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4655 struct pv_chunks_list *pvc;
4656 struct pch new_tail[PMAP_MEMDOM];
4657 struct pv_chunk *pc;
4662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4663 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4666 * Newly allocated PV chunks must be stored in a private list until
4667 * the required number of PV chunks have been allocated. Otherwise,
4668 * reclaim_pv_chunk() could recycle one of these chunks. In
4669 * contrast, these chunks must be added to the pmap upon allocation.
4671 for (i = 0; i < PMAP_MEMDOM; i++)
4672 TAILQ_INIT(&new_tail[i]);
4675 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4677 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4678 bit_count((bitstr_t *)pc->pc_map, 0,
4679 sizeof(pc->pc_map) * NBBY, &free);
4682 free = popcnt_pc_map_pq(pc->pc_map);
4686 if (avail >= needed)
4689 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4690 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4693 m = reclaim_pv_chunk(pmap, lockp);
4698 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4699 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4700 dump_add_page(m->phys_addr);
4701 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4703 pc->pc_map[0] = PC_FREE0;
4704 pc->pc_map[1] = PC_FREE1;
4705 pc->pc_map[2] = PC_FREE2;
4706 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4707 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
4708 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4711 * The reclaim might have freed a chunk from the current pmap.
4712 * If that chunk contained available entries, we need to
4713 * re-count the number of available entries.
4718 for (i = 0; i < vm_ndomains; i++) {
4719 if (TAILQ_EMPTY(&new_tail[i]))
4721 pvc = &pv_chunks[i];
4722 mtx_lock(&pvc->pvc_lock);
4723 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
4724 mtx_unlock(&pvc->pvc_lock);
4729 * First find and then remove the pv entry for the specified pmap and virtual
4730 * address from the specified pv list. Returns the pv entry if found and NULL
4731 * otherwise. This operation can be performed on pv lists for either 4KB or
4732 * 2MB page mappings.
4734 static __inline pv_entry_t
4735 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4739 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4740 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4741 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4750 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4751 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4752 * entries for each of the 4KB page mappings.
4755 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4756 struct rwlock **lockp)
4758 struct md_page *pvh;
4759 struct pv_chunk *pc;
4761 vm_offset_t va_last;
4765 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4766 KASSERT((pa & PDRMASK) == 0,
4767 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4768 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4771 * Transfer the 2mpage's pv entry for this mapping to the first
4772 * page's pv list. Once this transfer begins, the pv list lock
4773 * must not be released until the last pv entry is reinstantiated.
4775 pvh = pa_to_pvh(pa);
4776 va = trunc_2mpage(va);
4777 pv = pmap_pvh_remove(pvh, pmap, va);
4778 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4779 m = PHYS_TO_VM_PAGE(pa);
4780 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4782 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4783 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4784 va_last = va + NBPDR - PAGE_SIZE;
4786 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4787 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4788 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4789 for (field = 0; field < _NPCM; field++) {
4790 while (pc->pc_map[field]) {
4791 bit = bsfq(pc->pc_map[field]);
4792 pc->pc_map[field] &= ~(1ul << bit);
4793 pv = &pc->pc_pventry[field * 64 + bit];
4797 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4798 ("pmap_pv_demote_pde: page %p is not managed", m));
4799 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4805 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4806 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4809 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4810 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4811 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4813 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4814 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4817 #if VM_NRESERVLEVEL > 0
4819 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4820 * replace the many pv entries for the 4KB page mappings by a single pv entry
4821 * for the 2MB page mapping.
4824 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4825 struct rwlock **lockp)
4827 struct md_page *pvh;
4829 vm_offset_t va_last;
4832 KASSERT((pa & PDRMASK) == 0,
4833 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4834 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4837 * Transfer the first page's pv entry for this mapping to the 2mpage's
4838 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4839 * a transfer avoids the possibility that get_pv_entry() calls
4840 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4841 * mappings that is being promoted.
4843 m = PHYS_TO_VM_PAGE(pa);
4844 va = trunc_2mpage(va);
4845 pv = pmap_pvh_remove(&m->md, pmap, va);
4846 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4847 pvh = pa_to_pvh(pa);
4848 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4850 /* Free the remaining NPTEPG - 1 pv entries. */
4851 va_last = va + NBPDR - PAGE_SIZE;
4855 pmap_pvh_free(&m->md, pmap, va);
4856 } while (va < va_last);
4858 #endif /* VM_NRESERVLEVEL > 0 */
4861 * First find and then destroy the pv entry for the specified pmap and virtual
4862 * address. This operation can be performed on pv lists for either 4KB or 2MB
4866 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4870 pv = pmap_pvh_remove(pvh, pmap, va);
4871 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4872 free_pv_entry(pmap, pv);
4876 * Conditionally create the PV entry for a 4KB page mapping if the required
4877 * memory can be allocated without resorting to reclamation.
4880 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4881 struct rwlock **lockp)
4885 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4886 /* Pass NULL instead of the lock pointer to disable reclamation. */
4887 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4889 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4890 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4898 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4899 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4900 * false if the PV entry cannot be allocated without resorting to reclamation.
4903 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4904 struct rwlock **lockp)
4906 struct md_page *pvh;
4910 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4911 /* Pass NULL instead of the lock pointer to disable reclamation. */
4912 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4913 NULL : lockp)) == NULL)
4916 pa = pde & PG_PS_FRAME;
4917 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4918 pvh = pa_to_pvh(pa);
4919 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4925 * Fills a page table page with mappings to consecutive physical pages.
4928 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4932 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4934 newpte += PAGE_SIZE;
4939 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4940 * mapping is invalidated.
4943 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4945 struct rwlock *lock;
4949 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4956 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4960 pt_entry_t *xpte, *ypte;
4962 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4963 xpte++, newpte += PAGE_SIZE) {
4964 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4965 printf("pmap_demote_pde: xpte %zd and newpte map "
4966 "different pages: found %#lx, expected %#lx\n",
4967 xpte - firstpte, *xpte, newpte);
4968 printf("page table dump\n");
4969 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4970 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4975 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4976 ("pmap_demote_pde: firstpte and newpte map different physical"
4983 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4984 pd_entry_t oldpde, struct rwlock **lockp)
4986 struct spglist free;
4990 sva = trunc_2mpage(va);
4991 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4992 if ((oldpde & pmap_global_bit(pmap)) == 0)
4993 pmap_invalidate_pde_page(pmap, sva, oldpde);
4994 vm_page_free_pages_toq(&free, true);
4995 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5000 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5001 struct rwlock **lockp)
5003 pd_entry_t newpde, oldpde;
5004 pt_entry_t *firstpte, newpte;
5005 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5011 PG_A = pmap_accessed_bit(pmap);
5012 PG_G = pmap_global_bit(pmap);
5013 PG_M = pmap_modified_bit(pmap);
5014 PG_RW = pmap_rw_bit(pmap);
5015 PG_V = pmap_valid_bit(pmap);
5016 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5017 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5019 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5020 in_kernel = va >= VM_MAXUSER_ADDRESS;
5022 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5023 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5026 * Invalidate the 2MB page mapping and return "failure" if the
5027 * mapping was never accessed.
5029 if ((oldpde & PG_A) == 0) {
5030 KASSERT((oldpde & PG_W) == 0,
5031 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5032 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5036 mpte = pmap_remove_pt_page(pmap, va);
5038 KASSERT((oldpde & PG_W) == 0,
5039 ("pmap_demote_pde: page table page for a wired mapping"
5043 * If the page table page is missing and the mapping
5044 * is for a kernel address, the mapping must belong to
5045 * the direct map. Page table pages are preallocated
5046 * for every other part of the kernel address space,
5047 * so the direct map region is the only part of the
5048 * kernel address space that must be handled here.
5050 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5051 va < DMAP_MAX_ADDRESS),
5052 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5055 * If the 2MB page mapping belongs to the direct map
5056 * region of the kernel's address space, then the page
5057 * allocation request specifies the highest possible
5058 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5059 * priority is normal.
5061 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5062 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5063 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5066 * If the allocation of the new page table page fails,
5067 * invalidate the 2MB page mapping and return "failure".
5070 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5075 mpte->ref_count = NPTEPG;
5076 pmap_resident_count_inc(pmap, 1);
5079 mptepa = VM_PAGE_TO_PHYS(mpte);
5080 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5081 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5082 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5083 ("pmap_demote_pde: oldpde is missing PG_M"));
5084 newpte = oldpde & ~PG_PS;
5085 newpte = pmap_swap_pat(pmap, newpte);
5088 * If the page table page is not leftover from an earlier promotion,
5091 if (mpte->valid == 0)
5092 pmap_fill_ptp(firstpte, newpte);
5094 pmap_demote_pde_check(firstpte, newpte);
5097 * If the mapping has changed attributes, update the page table
5100 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5101 pmap_fill_ptp(firstpte, newpte);
5104 * The spare PV entries must be reserved prior to demoting the
5105 * mapping, that is, prior to changing the PDE. Otherwise, the state
5106 * of the PDE and the PV lists will be inconsistent, which can result
5107 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5108 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5109 * PV entry for the 2MB page mapping that is being demoted.
5111 if ((oldpde & PG_MANAGED) != 0)
5112 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5115 * Demote the mapping. This pmap is locked. The old PDE has
5116 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5117 * set. Thus, there is no danger of a race with another
5118 * processor changing the setting of PG_A and/or PG_M between
5119 * the read above and the store below.
5121 if (workaround_erratum383)
5122 pmap_update_pde(pmap, va, pde, newpde);
5124 pde_store(pde, newpde);
5127 * Invalidate a stale recursive mapping of the page table page.
5130 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5133 * Demote the PV entry.
5135 if ((oldpde & PG_MANAGED) != 0)
5136 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5138 atomic_add_long(&pmap_pde_demotions, 1);
5139 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5145 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5148 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5154 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5155 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5156 mpte = pmap_remove_pt_page(pmap, va);
5158 panic("pmap_remove_kernel_pde: Missing pt page.");
5160 mptepa = VM_PAGE_TO_PHYS(mpte);
5161 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5164 * If this page table page was unmapped by a promotion, then it
5165 * contains valid mappings. Zero it to invalidate those mappings.
5167 if (mpte->valid != 0)
5168 pagezero((void *)PHYS_TO_DMAP(mptepa));
5171 * Demote the mapping.
5173 if (workaround_erratum383)
5174 pmap_update_pde(pmap, va, pde, newpde);
5176 pde_store(pde, newpde);
5179 * Invalidate a stale recursive mapping of the page table page.
5181 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5185 * pmap_remove_pde: do the things to unmap a superpage in a process
5188 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5189 struct spglist *free, struct rwlock **lockp)
5191 struct md_page *pvh;
5193 vm_offset_t eva, va;
5195 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5197 PG_G = pmap_global_bit(pmap);
5198 PG_A = pmap_accessed_bit(pmap);
5199 PG_M = pmap_modified_bit(pmap);
5200 PG_RW = pmap_rw_bit(pmap);
5202 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5203 KASSERT((sva & PDRMASK) == 0,
5204 ("pmap_remove_pde: sva is not 2mpage aligned"));
5205 oldpde = pte_load_clear(pdq);
5207 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5208 if ((oldpde & PG_G) != 0)
5209 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5210 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5211 if (oldpde & PG_MANAGED) {
5212 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5213 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5214 pmap_pvh_free(pvh, pmap, sva);
5216 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5217 va < eva; va += PAGE_SIZE, m++) {
5218 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5221 vm_page_aflag_set(m, PGA_REFERENCED);
5222 if (TAILQ_EMPTY(&m->md.pv_list) &&
5223 TAILQ_EMPTY(&pvh->pv_list))
5224 vm_page_aflag_clear(m, PGA_WRITEABLE);
5225 pmap_delayed_invl_page(m);
5228 if (pmap == kernel_pmap) {
5229 pmap_remove_kernel_pde(pmap, pdq, sva);
5231 mpte = pmap_remove_pt_page(pmap, sva);
5233 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5234 ("pmap_remove_pde: pte page not promoted"));
5235 pmap_resident_count_dec(pmap, 1);
5236 KASSERT(mpte->ref_count == NPTEPG,
5237 ("pmap_remove_pde: pte page ref count error"));
5238 mpte->ref_count = 0;
5239 pmap_add_delayed_free_list(mpte, free, FALSE);
5242 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5246 * pmap_remove_pte: do the things to unmap a page in a process
5249 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5250 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5252 struct md_page *pvh;
5253 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5256 PG_A = pmap_accessed_bit(pmap);
5257 PG_M = pmap_modified_bit(pmap);
5258 PG_RW = pmap_rw_bit(pmap);
5260 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5261 oldpte = pte_load_clear(ptq);
5263 pmap->pm_stats.wired_count -= 1;
5264 pmap_resident_count_dec(pmap, 1);
5265 if (oldpte & PG_MANAGED) {
5266 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5267 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5270 vm_page_aflag_set(m, PGA_REFERENCED);
5271 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5272 pmap_pvh_free(&m->md, pmap, va);
5273 if (TAILQ_EMPTY(&m->md.pv_list) &&
5274 (m->flags & PG_FICTITIOUS) == 0) {
5275 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5276 if (TAILQ_EMPTY(&pvh->pv_list))
5277 vm_page_aflag_clear(m, PGA_WRITEABLE);
5279 pmap_delayed_invl_page(m);
5281 return (pmap_unuse_pt(pmap, va, ptepde, free));
5285 * Remove a single page from a process address space
5288 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5289 struct spglist *free)
5291 struct rwlock *lock;
5292 pt_entry_t *pte, PG_V;
5294 PG_V = pmap_valid_bit(pmap);
5295 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5296 if ((*pde & PG_V) == 0)
5298 pte = pmap_pde_to_pte(pde, va);
5299 if ((*pte & PG_V) == 0)
5302 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5305 pmap_invalidate_page(pmap, va);
5309 * Removes the specified range of addresses from the page table page.
5312 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5313 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5315 pt_entry_t PG_G, *pte;
5319 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5320 PG_G = pmap_global_bit(pmap);
5323 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5327 pmap_invalidate_range(pmap, va, sva);
5332 if ((*pte & PG_G) == 0)
5336 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5342 pmap_invalidate_range(pmap, va, sva);
5347 * Remove the given range of addresses from the specified map.
5349 * It is assumed that the start and end are properly
5350 * rounded to the page size.
5353 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5355 struct rwlock *lock;
5356 vm_offset_t va_next;
5357 pml4_entry_t *pml4e;
5359 pd_entry_t ptpaddr, *pde;
5360 pt_entry_t PG_G, PG_V;
5361 struct spglist free;
5364 PG_G = pmap_global_bit(pmap);
5365 PG_V = pmap_valid_bit(pmap);
5368 * Perform an unsynchronized read. This is, however, safe.
5370 if (pmap->pm_stats.resident_count == 0)
5376 pmap_delayed_invl_start();
5378 pmap_pkru_on_remove(pmap, sva, eva);
5381 * special handling of removing one page. a very
5382 * common operation and easy to short circuit some
5385 if (sva + PAGE_SIZE == eva) {
5386 pde = pmap_pde(pmap, sva);
5387 if (pde && (*pde & PG_PS) == 0) {
5388 pmap_remove_page(pmap, sva, pde, &free);
5394 for (; sva < eva; sva = va_next) {
5396 if (pmap->pm_stats.resident_count == 0)
5399 pml4e = pmap_pml4e(pmap, sva);
5400 if ((*pml4e & PG_V) == 0) {
5401 va_next = (sva + NBPML4) & ~PML4MASK;
5407 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5408 if ((*pdpe & PG_V) == 0) {
5409 va_next = (sva + NBPDP) & ~PDPMASK;
5416 * Calculate index for next page table.
5418 va_next = (sva + NBPDR) & ~PDRMASK;
5422 pde = pmap_pdpe_to_pde(pdpe, sva);
5426 * Weed out invalid mappings.
5432 * Check for large page.
5434 if ((ptpaddr & PG_PS) != 0) {
5436 * Are we removing the entire large page? If not,
5437 * demote the mapping and fall through.
5439 if (sva + NBPDR == va_next && eva >= va_next) {
5441 * The TLB entry for a PG_G mapping is
5442 * invalidated by pmap_remove_pde().
5444 if ((ptpaddr & PG_G) == 0)
5446 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5448 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5450 /* The large page mapping was destroyed. */
5457 * Limit our scan to either the end of the va represented
5458 * by the current page table page, or to the end of the
5459 * range being removed.
5464 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5471 pmap_invalidate_all(pmap);
5473 pmap_delayed_invl_finish();
5474 vm_page_free_pages_toq(&free, true);
5478 * Routine: pmap_remove_all
5480 * Removes this physical page from
5481 * all physical maps in which it resides.
5482 * Reflects back modify bits to the pager.
5485 * Original versions of this routine were very
5486 * inefficient because they iteratively called
5487 * pmap_remove (slow...)
5491 pmap_remove_all(vm_page_t m)
5493 struct md_page *pvh;
5496 struct rwlock *lock;
5497 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5500 struct spglist free;
5501 int pvh_gen, md_gen;
5503 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5504 ("pmap_remove_all: page %p is not managed", m));
5506 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5507 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5508 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5511 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5513 if (!PMAP_TRYLOCK(pmap)) {
5514 pvh_gen = pvh->pv_gen;
5518 if (pvh_gen != pvh->pv_gen) {
5525 pde = pmap_pde(pmap, va);
5526 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5529 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5531 if (!PMAP_TRYLOCK(pmap)) {
5532 pvh_gen = pvh->pv_gen;
5533 md_gen = m->md.pv_gen;
5537 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5543 PG_A = pmap_accessed_bit(pmap);
5544 PG_M = pmap_modified_bit(pmap);
5545 PG_RW = pmap_rw_bit(pmap);
5546 pmap_resident_count_dec(pmap, 1);
5547 pde = pmap_pde(pmap, pv->pv_va);
5548 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5549 " a 2mpage in page %p's pv list", m));
5550 pte = pmap_pde_to_pte(pde, pv->pv_va);
5551 tpte = pte_load_clear(pte);
5553 pmap->pm_stats.wired_count--;
5555 vm_page_aflag_set(m, PGA_REFERENCED);
5558 * Update the vm_page_t clean and reference bits.
5560 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5562 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5563 pmap_invalidate_page(pmap, pv->pv_va);
5564 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5566 free_pv_entry(pmap, pv);
5569 vm_page_aflag_clear(m, PGA_WRITEABLE);
5571 pmap_delayed_invl_wait(m);
5572 vm_page_free_pages_toq(&free, true);
5576 * pmap_protect_pde: do the things to protect a 2mpage in a process
5579 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5581 pd_entry_t newpde, oldpde;
5583 boolean_t anychanged;
5584 pt_entry_t PG_G, PG_M, PG_RW;
5586 PG_G = pmap_global_bit(pmap);
5587 PG_M = pmap_modified_bit(pmap);
5588 PG_RW = pmap_rw_bit(pmap);
5590 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5591 KASSERT((sva & PDRMASK) == 0,
5592 ("pmap_protect_pde: sva is not 2mpage aligned"));
5595 oldpde = newpde = *pde;
5596 if ((prot & VM_PROT_WRITE) == 0) {
5597 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5598 (PG_MANAGED | PG_M | PG_RW)) {
5599 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5600 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5603 newpde &= ~(PG_RW | PG_M);
5605 if ((prot & VM_PROT_EXECUTE) == 0)
5607 if (newpde != oldpde) {
5609 * As an optimization to future operations on this PDE, clear
5610 * PG_PROMOTED. The impending invalidation will remove any
5611 * lingering 4KB page mappings from the TLB.
5613 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5615 if ((oldpde & PG_G) != 0)
5616 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5620 return (anychanged);
5624 * Set the physical protection on the
5625 * specified range of this map as requested.
5628 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5630 vm_offset_t va_next;
5631 pml4_entry_t *pml4e;
5633 pd_entry_t ptpaddr, *pde;
5634 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5635 boolean_t anychanged;
5637 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5638 if (prot == VM_PROT_NONE) {
5639 pmap_remove(pmap, sva, eva);
5643 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5644 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5647 PG_G = pmap_global_bit(pmap);
5648 PG_M = pmap_modified_bit(pmap);
5649 PG_V = pmap_valid_bit(pmap);
5650 PG_RW = pmap_rw_bit(pmap);
5654 * Although this function delays and batches the invalidation
5655 * of stale TLB entries, it does not need to call
5656 * pmap_delayed_invl_start() and
5657 * pmap_delayed_invl_finish(), because it does not
5658 * ordinarily destroy mappings. Stale TLB entries from
5659 * protection-only changes need only be invalidated before the
5660 * pmap lock is released, because protection-only changes do
5661 * not destroy PV entries. Even operations that iterate over
5662 * a physical page's PV list of mappings, like
5663 * pmap_remove_write(), acquire the pmap lock for each
5664 * mapping. Consequently, for protection-only changes, the
5665 * pmap lock suffices to synchronize both page table and TLB
5668 * This function only destroys a mapping if pmap_demote_pde()
5669 * fails. In that case, stale TLB entries are immediately
5674 for (; sva < eva; sva = va_next) {
5676 pml4e = pmap_pml4e(pmap, sva);
5677 if ((*pml4e & PG_V) == 0) {
5678 va_next = (sva + NBPML4) & ~PML4MASK;
5684 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5685 if ((*pdpe & PG_V) == 0) {
5686 va_next = (sva + NBPDP) & ~PDPMASK;
5692 va_next = (sva + NBPDR) & ~PDRMASK;
5696 pde = pmap_pdpe_to_pde(pdpe, sva);
5700 * Weed out invalid mappings.
5706 * Check for large page.
5708 if ((ptpaddr & PG_PS) != 0) {
5710 * Are we protecting the entire large page? If not,
5711 * demote the mapping and fall through.
5713 if (sva + NBPDR == va_next && eva >= va_next) {
5715 * The TLB entry for a PG_G mapping is
5716 * invalidated by pmap_protect_pde().
5718 if (pmap_protect_pde(pmap, pde, sva, prot))
5721 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5723 * The large page mapping was destroyed.
5732 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5734 pt_entry_t obits, pbits;
5738 obits = pbits = *pte;
5739 if ((pbits & PG_V) == 0)
5742 if ((prot & VM_PROT_WRITE) == 0) {
5743 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5744 (PG_MANAGED | PG_M | PG_RW)) {
5745 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5748 pbits &= ~(PG_RW | PG_M);
5750 if ((prot & VM_PROT_EXECUTE) == 0)
5753 if (pbits != obits) {
5754 if (!atomic_cmpset_long(pte, obits, pbits))
5757 pmap_invalidate_page(pmap, sva);
5764 pmap_invalidate_all(pmap);
5768 #if VM_NRESERVLEVEL > 0
5770 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5773 if (pmap->pm_type != PT_EPT)
5775 return ((pde & EPT_PG_EXECUTE) != 0);
5779 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5780 * single page table page (PTP) to a single 2MB page mapping. For promotion
5781 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5782 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5783 * identical characteristics.
5786 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5787 struct rwlock **lockp)
5790 pt_entry_t *firstpte, oldpte, pa, *pte;
5791 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5795 PG_A = pmap_accessed_bit(pmap);
5796 PG_G = pmap_global_bit(pmap);
5797 PG_M = pmap_modified_bit(pmap);
5798 PG_V = pmap_valid_bit(pmap);
5799 PG_RW = pmap_rw_bit(pmap);
5800 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5801 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5803 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5806 * Examine the first PTE in the specified PTP. Abort if this PTE is
5807 * either invalid, unused, or does not map the first 4KB physical page
5808 * within a 2MB page.
5810 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5813 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5814 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5816 atomic_add_long(&pmap_pde_p_failures, 1);
5817 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5818 " in pmap %p", va, pmap);
5821 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5823 * When PG_M is already clear, PG_RW can be cleared without
5824 * a TLB invalidation.
5826 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5832 * Examine each of the other PTEs in the specified PTP. Abort if this
5833 * PTE maps an unexpected 4KB physical page or does not have identical
5834 * characteristics to the first PTE.
5836 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5837 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5840 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5841 atomic_add_long(&pmap_pde_p_failures, 1);
5842 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5843 " in pmap %p", va, pmap);
5846 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5848 * When PG_M is already clear, PG_RW can be cleared
5849 * without a TLB invalidation.
5851 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5854 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5855 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5856 (va & ~PDRMASK), pmap);
5858 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5859 atomic_add_long(&pmap_pde_p_failures, 1);
5860 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5861 " in pmap %p", va, pmap);
5868 * Save the page table page in its current state until the PDE
5869 * mapping the superpage is demoted by pmap_demote_pde() or
5870 * destroyed by pmap_remove_pde().
5872 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5873 KASSERT(mpte >= vm_page_array &&
5874 mpte < &vm_page_array[vm_page_array_size],
5875 ("pmap_promote_pde: page table page is out of range"));
5876 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5877 ("pmap_promote_pde: page table page's pindex is wrong"));
5878 if (pmap_insert_pt_page(pmap, mpte, true)) {
5879 atomic_add_long(&pmap_pde_p_failures, 1);
5881 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5887 * Promote the pv entries.
5889 if ((newpde & PG_MANAGED) != 0)
5890 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5893 * Propagate the PAT index to its proper position.
5895 newpde = pmap_swap_pat(pmap, newpde);
5898 * Map the superpage.
5900 if (workaround_erratum383)
5901 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5903 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5905 atomic_add_long(&pmap_pde_promotions, 1);
5906 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5907 " in pmap %p", va, pmap);
5909 #endif /* VM_NRESERVLEVEL > 0 */
5912 * Insert the given physical page (p) at
5913 * the specified virtual address (v) in the
5914 * target physical map with the protection requested.
5916 * If specified, the page will be wired down, meaning
5917 * that the related pte can not be reclaimed.
5919 * NB: This is the only routine which MAY NOT lazy-evaluate
5920 * or lose information. That is, this routine must actually
5921 * insert this page into the given map NOW.
5923 * When destroying both a page table and PV entry, this function
5924 * performs the TLB invalidation before releasing the PV list
5925 * lock, so we do not need pmap_delayed_invl_page() calls here.
5928 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5929 u_int flags, int8_t psind)
5931 struct rwlock *lock;
5933 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5934 pt_entry_t newpte, origpte;
5941 PG_A = pmap_accessed_bit(pmap);
5942 PG_G = pmap_global_bit(pmap);
5943 PG_M = pmap_modified_bit(pmap);
5944 PG_V = pmap_valid_bit(pmap);
5945 PG_RW = pmap_rw_bit(pmap);
5947 va = trunc_page(va);
5948 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5949 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5950 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5952 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5953 va >= kmi.clean_eva,
5954 ("pmap_enter: managed mapping within the clean submap"));
5955 if ((m->oflags & VPO_UNMANAGED) == 0)
5956 VM_PAGE_OBJECT_BUSY_ASSERT(m);
5957 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5958 ("pmap_enter: flags %u has reserved bits set", flags));
5959 pa = VM_PAGE_TO_PHYS(m);
5960 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5961 if ((flags & VM_PROT_WRITE) != 0)
5963 if ((prot & VM_PROT_WRITE) != 0)
5965 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5966 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5967 if ((prot & VM_PROT_EXECUTE) == 0)
5969 if ((flags & PMAP_ENTER_WIRED) != 0)
5971 if (va < VM_MAXUSER_ADDRESS)
5973 if (pmap == kernel_pmap)
5975 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5978 * Set modified bit gratuitously for writeable mappings if
5979 * the page is unmanaged. We do not want to take a fault
5980 * to do the dirty bit accounting for these mappings.
5982 if ((m->oflags & VPO_UNMANAGED) != 0) {
5983 if ((newpte & PG_RW) != 0)
5986 newpte |= PG_MANAGED;
5991 /* Assert the required virtual and physical alignment. */
5992 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5993 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5994 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6000 * In the case that a page table page is not
6001 * resident, we are creating it here.
6004 pde = pmap_pde(pmap, va);
6005 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6006 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6007 pte = pmap_pde_to_pte(pde, va);
6008 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6009 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6012 } else if (va < VM_MAXUSER_ADDRESS) {
6014 * Here if the pte page isn't mapped, or if it has been
6017 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6018 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6019 nosleep ? NULL : &lock);
6020 if (mpte == NULL && nosleep) {
6021 rv = KERN_RESOURCE_SHORTAGE;
6026 panic("pmap_enter: invalid page directory va=%#lx", va);
6030 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6031 newpte |= pmap_pkru_get(pmap, va);
6034 * Is the specified virtual address already mapped?
6036 if ((origpte & PG_V) != 0) {
6038 * Wiring change, just update stats. We don't worry about
6039 * wiring PT pages as they remain resident as long as there
6040 * are valid mappings in them. Hence, if a user page is wired,
6041 * the PT page will be also.
6043 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6044 pmap->pm_stats.wired_count++;
6045 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6046 pmap->pm_stats.wired_count--;
6049 * Remove the extra PT page reference.
6053 KASSERT(mpte->ref_count > 0,
6054 ("pmap_enter: missing reference to page table page,"
6059 * Has the physical page changed?
6061 opa = origpte & PG_FRAME;
6064 * No, might be a protection or wiring change.
6066 if ((origpte & PG_MANAGED) != 0 &&
6067 (newpte & PG_RW) != 0)
6068 vm_page_aflag_set(m, PGA_WRITEABLE);
6069 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6075 * The physical page has changed. Temporarily invalidate
6076 * the mapping. This ensures that all threads sharing the
6077 * pmap keep a consistent view of the mapping, which is
6078 * necessary for the correct handling of COW faults. It
6079 * also permits reuse of the old mapping's PV entry,
6080 * avoiding an allocation.
6082 * For consistency, handle unmanaged mappings the same way.
6084 origpte = pte_load_clear(pte);
6085 KASSERT((origpte & PG_FRAME) == opa,
6086 ("pmap_enter: unexpected pa update for %#lx", va));
6087 if ((origpte & PG_MANAGED) != 0) {
6088 om = PHYS_TO_VM_PAGE(opa);
6091 * The pmap lock is sufficient to synchronize with
6092 * concurrent calls to pmap_page_test_mappings() and
6093 * pmap_ts_referenced().
6095 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6097 if ((origpte & PG_A) != 0)
6098 vm_page_aflag_set(om, PGA_REFERENCED);
6099 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6100 pv = pmap_pvh_remove(&om->md, pmap, va);
6102 ("pmap_enter: no PV entry for %#lx", va));
6103 if ((newpte & PG_MANAGED) == 0)
6104 free_pv_entry(pmap, pv);
6105 if ((om->aflags & PGA_WRITEABLE) != 0 &&
6106 TAILQ_EMPTY(&om->md.pv_list) &&
6107 ((om->flags & PG_FICTITIOUS) != 0 ||
6108 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6109 vm_page_aflag_clear(om, PGA_WRITEABLE);
6111 if ((origpte & PG_A) != 0)
6112 pmap_invalidate_page(pmap, va);
6116 * Increment the counters.
6118 if ((newpte & PG_W) != 0)
6119 pmap->pm_stats.wired_count++;
6120 pmap_resident_count_inc(pmap, 1);
6124 * Enter on the PV list if part of our managed memory.
6126 if ((newpte & PG_MANAGED) != 0) {
6128 pv = get_pv_entry(pmap, &lock);
6131 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6132 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6134 if ((newpte & PG_RW) != 0)
6135 vm_page_aflag_set(m, PGA_WRITEABLE);
6141 if ((origpte & PG_V) != 0) {
6143 origpte = pte_load_store(pte, newpte);
6144 KASSERT((origpte & PG_FRAME) == pa,
6145 ("pmap_enter: unexpected pa update for %#lx", va));
6146 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6148 if ((origpte & PG_MANAGED) != 0)
6152 * Although the PTE may still have PG_RW set, TLB
6153 * invalidation may nonetheless be required because
6154 * the PTE no longer has PG_M set.
6156 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6158 * This PTE change does not require TLB invalidation.
6162 if ((origpte & PG_A) != 0)
6163 pmap_invalidate_page(pmap, va);
6165 pte_store(pte, newpte);
6169 #if VM_NRESERVLEVEL > 0
6171 * If both the page table page and the reservation are fully
6172 * populated, then attempt promotion.
6174 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6175 pmap_ps_enabled(pmap) &&
6176 (m->flags & PG_FICTITIOUS) == 0 &&
6177 vm_reserv_level_iffullpop(m) == 0)
6178 pmap_promote_pde(pmap, pde, va, &lock);
6190 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6191 * if successful. Returns false if (1) a page table page cannot be allocated
6192 * without sleeping, (2) a mapping already exists at the specified virtual
6193 * address, or (3) a PV entry cannot be allocated without reclaiming another
6197 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6198 struct rwlock **lockp)
6203 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6204 PG_V = pmap_valid_bit(pmap);
6205 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6207 if ((m->oflags & VPO_UNMANAGED) == 0)
6208 newpde |= PG_MANAGED;
6209 if ((prot & VM_PROT_EXECUTE) == 0)
6211 if (va < VM_MAXUSER_ADDRESS)
6213 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6214 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6219 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6220 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6221 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6222 * a mapping already exists at the specified virtual address. Returns
6223 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6224 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6225 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6227 * The parameter "m" is only used when creating a managed, writeable mapping.
6230 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6231 vm_page_t m, struct rwlock **lockp)
6233 struct spglist free;
6234 pd_entry_t oldpde, *pde;
6235 pt_entry_t PG_G, PG_RW, PG_V;
6238 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6239 ("pmap_enter_pde: cannot create wired user mapping"));
6240 PG_G = pmap_global_bit(pmap);
6241 PG_RW = pmap_rw_bit(pmap);
6242 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6243 ("pmap_enter_pde: newpde is missing PG_M"));
6244 PG_V = pmap_valid_bit(pmap);
6245 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6247 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6249 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6250 " in pmap %p", va, pmap);
6251 return (KERN_FAILURE);
6253 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
6254 NULL : lockp)) == NULL) {
6255 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6256 " in pmap %p", va, pmap);
6257 return (KERN_RESOURCE_SHORTAGE);
6261 * If pkru is not same for the whole pde range, return failure
6262 * and let vm_fault() cope. Check after pde allocation, since
6265 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6267 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6268 pmap_invalidate_page(pmap, va);
6269 vm_page_free_pages_toq(&free, true);
6271 return (KERN_FAILURE);
6273 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6274 newpde &= ~X86_PG_PKU_MASK;
6275 newpde |= pmap_pkru_get(pmap, va);
6278 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6279 pde = &pde[pmap_pde_index(va)];
6281 if ((oldpde & PG_V) != 0) {
6282 KASSERT(pdpg->ref_count > 1,
6283 ("pmap_enter_pde: pdpg's reference count is too low"));
6284 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
6286 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6287 " in pmap %p", va, pmap);
6288 return (KERN_FAILURE);
6290 /* Break the existing mapping(s). */
6292 if ((oldpde & PG_PS) != 0) {
6294 * The reference to the PD page that was acquired by
6295 * pmap_allocpde() ensures that it won't be freed.
6296 * However, if the PDE resulted from a promotion, then
6297 * a reserved PT page could be freed.
6299 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6300 if ((oldpde & PG_G) == 0)
6301 pmap_invalidate_pde_page(pmap, va, oldpde);
6303 pmap_delayed_invl_start();
6304 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6306 pmap_invalidate_all(pmap);
6307 pmap_delayed_invl_finish();
6309 vm_page_free_pages_toq(&free, true);
6310 if (va >= VM_MAXUSER_ADDRESS) {
6312 * Both pmap_remove_pde() and pmap_remove_ptes() will
6313 * leave the kernel page table page zero filled.
6315 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6316 if (pmap_insert_pt_page(pmap, mt, false))
6317 panic("pmap_enter_pde: trie insert failed");
6319 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6322 if ((newpde & PG_MANAGED) != 0) {
6324 * Abort this mapping if its PV entry could not be created.
6326 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6328 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6330 * Although "va" is not mapped, paging-
6331 * structure caches could nonetheless have
6332 * entries that refer to the freed page table
6333 * pages. Invalidate those entries.
6335 pmap_invalidate_page(pmap, va);
6336 vm_page_free_pages_toq(&free, true);
6338 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6339 " in pmap %p", va, pmap);
6340 return (KERN_RESOURCE_SHORTAGE);
6342 if ((newpde & PG_RW) != 0) {
6343 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6344 vm_page_aflag_set(mt, PGA_WRITEABLE);
6349 * Increment counters.
6351 if ((newpde & PG_W) != 0)
6352 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6353 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6356 * Map the superpage. (This is not a promoted mapping; there will not
6357 * be any lingering 4KB page mappings in the TLB.)
6359 pde_store(pde, newpde);
6361 atomic_add_long(&pmap_pde_mappings, 1);
6362 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
6363 " in pmap %p", va, pmap);
6364 return (KERN_SUCCESS);
6368 * Maps a sequence of resident pages belonging to the same object.
6369 * The sequence begins with the given page m_start. This page is
6370 * mapped at the given virtual address start. Each subsequent page is
6371 * mapped at a virtual address that is offset from start by the same
6372 * amount as the page is offset from m_start within the object. The
6373 * last page in the sequence is the page with the largest offset from
6374 * m_start that can be mapped at a virtual address less than the given
6375 * virtual address end. Not every virtual page between start and end
6376 * is mapped; only those for which a resident page exists with the
6377 * corresponding offset from m_start are mapped.
6380 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6381 vm_page_t m_start, vm_prot_t prot)
6383 struct rwlock *lock;
6386 vm_pindex_t diff, psize;
6388 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6390 psize = atop(end - start);
6395 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6396 va = start + ptoa(diff);
6397 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6398 m->psind == 1 && pmap_ps_enabled(pmap) &&
6399 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6400 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6401 m = &m[NBPDR / PAGE_SIZE - 1];
6403 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6405 m = TAILQ_NEXT(m, listq);
6413 * this code makes some *MAJOR* assumptions:
6414 * 1. Current pmap & pmap exists.
6417 * 4. No page table pages.
6418 * but is *MUCH* faster than pmap_enter...
6422 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6424 struct rwlock *lock;
6428 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6435 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6436 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6438 struct spglist free;
6439 pt_entry_t newpte, *pte, PG_V;
6441 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6442 (m->oflags & VPO_UNMANAGED) != 0,
6443 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6444 PG_V = pmap_valid_bit(pmap);
6445 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6448 * In the case that a page table page is not
6449 * resident, we are creating it here.
6451 if (va < VM_MAXUSER_ADDRESS) {
6452 vm_pindex_t ptepindex;
6456 * Calculate pagetable page index
6458 ptepindex = pmap_pde_pindex(va);
6459 if (mpte && (mpte->pindex == ptepindex)) {
6463 * Get the page directory entry
6465 ptepa = pmap_pde(pmap, va);
6468 * If the page table page is mapped, we just increment
6469 * the hold count, and activate it. Otherwise, we
6470 * attempt to allocate a page table page. If this
6471 * attempt fails, we don't retry. Instead, we give up.
6473 if (ptepa && (*ptepa & PG_V) != 0) {
6476 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6480 * Pass NULL instead of the PV list lock
6481 * pointer, because we don't intend to sleep.
6483 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6488 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6489 pte = &pte[pmap_pte_index(va)];
6503 * Enter on the PV list if part of our managed memory.
6505 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6506 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6509 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6511 * Although "va" is not mapped, paging-
6512 * structure caches could nonetheless have
6513 * entries that refer to the freed page table
6514 * pages. Invalidate those entries.
6516 pmap_invalidate_page(pmap, va);
6517 vm_page_free_pages_toq(&free, true);
6525 * Increment counters
6527 pmap_resident_count_inc(pmap, 1);
6529 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6530 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6531 if ((m->oflags & VPO_UNMANAGED) == 0)
6532 newpte |= PG_MANAGED;
6533 if ((prot & VM_PROT_EXECUTE) == 0)
6535 if (va < VM_MAXUSER_ADDRESS)
6536 newpte |= PG_U | pmap_pkru_get(pmap, va);
6537 pte_store(pte, newpte);
6542 * Make a temporary mapping for a physical address. This is only intended
6543 * to be used for panic dumps.
6546 pmap_kenter_temporary(vm_paddr_t pa, int i)
6550 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6551 pmap_kenter(va, pa);
6553 return ((void *)crashdumpmap);
6557 * This code maps large physical mmap regions into the
6558 * processor address space. Note that some shortcuts
6559 * are taken, but the code works.
6562 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6563 vm_pindex_t pindex, vm_size_t size)
6566 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6567 vm_paddr_t pa, ptepa;
6571 PG_A = pmap_accessed_bit(pmap);
6572 PG_M = pmap_modified_bit(pmap);
6573 PG_V = pmap_valid_bit(pmap);
6574 PG_RW = pmap_rw_bit(pmap);
6576 VM_OBJECT_ASSERT_WLOCKED(object);
6577 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6578 ("pmap_object_init_pt: non-device object"));
6579 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6580 if (!pmap_ps_enabled(pmap))
6582 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6584 p = vm_page_lookup(object, pindex);
6585 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6586 ("pmap_object_init_pt: invalid page %p", p));
6587 pat_mode = p->md.pat_mode;
6590 * Abort the mapping if the first page is not physically
6591 * aligned to a 2MB page boundary.
6593 ptepa = VM_PAGE_TO_PHYS(p);
6594 if (ptepa & (NBPDR - 1))
6598 * Skip the first page. Abort the mapping if the rest of
6599 * the pages are not physically contiguous or have differing
6600 * memory attributes.
6602 p = TAILQ_NEXT(p, listq);
6603 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6605 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6606 ("pmap_object_init_pt: invalid page %p", p));
6607 if (pa != VM_PAGE_TO_PHYS(p) ||
6608 pat_mode != p->md.pat_mode)
6610 p = TAILQ_NEXT(p, listq);
6614 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6615 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6616 * will not affect the termination of this loop.
6619 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6620 pa < ptepa + size; pa += NBPDR) {
6621 pdpg = pmap_allocpde(pmap, addr, NULL);
6624 * The creation of mappings below is only an
6625 * optimization. If a page directory page
6626 * cannot be allocated without blocking,
6627 * continue on to the next mapping rather than
6633 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6634 pde = &pde[pmap_pde_index(addr)];
6635 if ((*pde & PG_V) == 0) {
6636 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6637 PG_U | PG_RW | PG_V);
6638 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6639 atomic_add_long(&pmap_pde_mappings, 1);
6641 /* Continue on if the PDE is already valid. */
6643 KASSERT(pdpg->ref_count > 0,
6644 ("pmap_object_init_pt: missing reference "
6645 "to page directory page, va: 0x%lx", addr));
6654 * Clear the wired attribute from the mappings for the specified range of
6655 * addresses in the given pmap. Every valid mapping within that range
6656 * must have the wired attribute set. In contrast, invalid mappings
6657 * cannot have the wired attribute set, so they are ignored.
6659 * The wired attribute of the page table entry is not a hardware
6660 * feature, so there is no need to invalidate any TLB entries.
6661 * Since pmap_demote_pde() for the wired entry must never fail,
6662 * pmap_delayed_invl_start()/finish() calls around the
6663 * function are not needed.
6666 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6668 vm_offset_t va_next;
6669 pml4_entry_t *pml4e;
6672 pt_entry_t *pte, PG_V;
6674 PG_V = pmap_valid_bit(pmap);
6676 for (; sva < eva; sva = va_next) {
6677 pml4e = pmap_pml4e(pmap, sva);
6678 if ((*pml4e & PG_V) == 0) {
6679 va_next = (sva + NBPML4) & ~PML4MASK;
6684 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6685 if ((*pdpe & PG_V) == 0) {
6686 va_next = (sva + NBPDP) & ~PDPMASK;
6691 va_next = (sva + NBPDR) & ~PDRMASK;
6694 pde = pmap_pdpe_to_pde(pdpe, sva);
6695 if ((*pde & PG_V) == 0)
6697 if ((*pde & PG_PS) != 0) {
6698 if ((*pde & PG_W) == 0)
6699 panic("pmap_unwire: pde %#jx is missing PG_W",
6703 * Are we unwiring the entire large page? If not,
6704 * demote the mapping and fall through.
6706 if (sva + NBPDR == va_next && eva >= va_next) {
6707 atomic_clear_long(pde, PG_W);
6708 pmap->pm_stats.wired_count -= NBPDR /
6711 } else if (!pmap_demote_pde(pmap, pde, sva))
6712 panic("pmap_unwire: demotion failed");
6716 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6718 if ((*pte & PG_V) == 0)
6720 if ((*pte & PG_W) == 0)
6721 panic("pmap_unwire: pte %#jx is missing PG_W",
6725 * PG_W must be cleared atomically. Although the pmap
6726 * lock synchronizes access to PG_W, another processor
6727 * could be setting PG_M and/or PG_A concurrently.
6729 atomic_clear_long(pte, PG_W);
6730 pmap->pm_stats.wired_count--;
6737 * Copy the range specified by src_addr/len
6738 * from the source map to the range dst_addr/len
6739 * in the destination map.
6741 * This routine is only advisory and need not do anything.
6744 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6745 vm_offset_t src_addr)
6747 struct rwlock *lock;
6748 struct spglist free;
6749 pml4_entry_t *pml4e;
6751 pd_entry_t *pde, srcptepaddr;
6752 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6753 vm_offset_t addr, end_addr, va_next;
6754 vm_page_t dst_pdpg, dstmpte, srcmpte;
6756 if (dst_addr != src_addr)
6759 if (dst_pmap->pm_type != src_pmap->pm_type)
6763 * EPT page table entries that require emulation of A/D bits are
6764 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6765 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6766 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6767 * implementations flag an EPT misconfiguration for exec-only
6768 * mappings we skip this function entirely for emulated pmaps.
6770 if (pmap_emulate_ad_bits(dst_pmap))
6773 end_addr = src_addr + len;
6775 if (dst_pmap < src_pmap) {
6776 PMAP_LOCK(dst_pmap);
6777 PMAP_LOCK(src_pmap);
6779 PMAP_LOCK(src_pmap);
6780 PMAP_LOCK(dst_pmap);
6783 PG_A = pmap_accessed_bit(dst_pmap);
6784 PG_M = pmap_modified_bit(dst_pmap);
6785 PG_V = pmap_valid_bit(dst_pmap);
6787 for (addr = src_addr; addr < end_addr; addr = va_next) {
6788 KASSERT(addr < UPT_MIN_ADDRESS,
6789 ("pmap_copy: invalid to pmap_copy page tables"));
6791 pml4e = pmap_pml4e(src_pmap, addr);
6792 if ((*pml4e & PG_V) == 0) {
6793 va_next = (addr + NBPML4) & ~PML4MASK;
6799 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6800 if ((*pdpe & PG_V) == 0) {
6801 va_next = (addr + NBPDP) & ~PDPMASK;
6807 va_next = (addr + NBPDR) & ~PDRMASK;
6811 pde = pmap_pdpe_to_pde(pdpe, addr);
6813 if (srcptepaddr == 0)
6816 if (srcptepaddr & PG_PS) {
6817 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6819 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6820 if (dst_pdpg == NULL)
6822 pde = (pd_entry_t *)
6823 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6824 pde = &pde[pmap_pde_index(addr)];
6825 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6826 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6827 PMAP_ENTER_NORECLAIM, &lock))) {
6828 *pde = srcptepaddr & ~PG_W;
6829 pmap_resident_count_inc(dst_pmap, NBPDR /
6831 atomic_add_long(&pmap_pde_mappings, 1);
6833 dst_pdpg->ref_count--;
6837 srcptepaddr &= PG_FRAME;
6838 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6839 KASSERT(srcmpte->ref_count > 0,
6840 ("pmap_copy: source page table page is unused"));
6842 if (va_next > end_addr)
6845 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6846 src_pte = &src_pte[pmap_pte_index(addr)];
6848 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6852 * We only virtual copy managed pages.
6854 if ((ptetemp & PG_MANAGED) == 0)
6857 if (dstmpte != NULL) {
6858 KASSERT(dstmpte->pindex ==
6859 pmap_pde_pindex(addr),
6860 ("dstmpte pindex/addr mismatch"));
6861 dstmpte->ref_count++;
6862 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6865 dst_pte = (pt_entry_t *)
6866 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6867 dst_pte = &dst_pte[pmap_pte_index(addr)];
6868 if (*dst_pte == 0 &&
6869 pmap_try_insert_pv_entry(dst_pmap, addr,
6870 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6872 * Clear the wired, modified, and accessed
6873 * (referenced) bits during the copy.
6875 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6876 pmap_resident_count_inc(dst_pmap, 1);
6879 if (pmap_unwire_ptp(dst_pmap, addr, dstmpte,
6882 * Although "addr" is not mapped,
6883 * paging-structure caches could
6884 * nonetheless have entries that refer
6885 * to the freed page table pages.
6886 * Invalidate those entries.
6888 pmap_invalidate_page(dst_pmap, addr);
6889 vm_page_free_pages_toq(&free, true);
6893 /* Have we copied all of the valid mappings? */
6894 if (dstmpte->ref_count >= srcmpte->ref_count)
6901 PMAP_UNLOCK(src_pmap);
6902 PMAP_UNLOCK(dst_pmap);
6906 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6910 if (dst_pmap->pm_type != src_pmap->pm_type ||
6911 dst_pmap->pm_type != PT_X86 ||
6912 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6915 if (dst_pmap < src_pmap) {
6916 PMAP_LOCK(dst_pmap);
6917 PMAP_LOCK(src_pmap);
6919 PMAP_LOCK(src_pmap);
6920 PMAP_LOCK(dst_pmap);
6922 error = pmap_pkru_copy(dst_pmap, src_pmap);
6923 /* Clean up partial copy on failure due to no memory. */
6924 if (error == ENOMEM)
6925 pmap_pkru_deassign_all(dst_pmap);
6926 PMAP_UNLOCK(src_pmap);
6927 PMAP_UNLOCK(dst_pmap);
6928 if (error != ENOMEM)
6936 * Zero the specified hardware page.
6939 pmap_zero_page(vm_page_t m)
6941 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6943 pagezero((void *)va);
6947 * Zero an an area within a single hardware page. off and size must not
6948 * cover an area beyond a single hardware page.
6951 pmap_zero_page_area(vm_page_t m, int off, int size)
6953 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6955 if (off == 0 && size == PAGE_SIZE)
6956 pagezero((void *)va);
6958 bzero((char *)va + off, size);
6962 * Copy 1 specified hardware page to another.
6965 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6967 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6968 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6970 pagecopy((void *)src, (void *)dst);
6973 int unmapped_buf_allowed = 1;
6976 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6977 vm_offset_t b_offset, int xfersize)
6981 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6985 while (xfersize > 0) {
6986 a_pg_offset = a_offset & PAGE_MASK;
6987 pages[0] = ma[a_offset >> PAGE_SHIFT];
6988 b_pg_offset = b_offset & PAGE_MASK;
6989 pages[1] = mb[b_offset >> PAGE_SHIFT];
6990 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6991 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6992 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6993 a_cp = (char *)vaddr[0] + a_pg_offset;
6994 b_cp = (char *)vaddr[1] + b_pg_offset;
6995 bcopy(a_cp, b_cp, cnt);
6996 if (__predict_false(mapped))
6997 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7005 * Returns true if the pmap's pv is one of the first
7006 * 16 pvs linked to from this page. This count may
7007 * be changed upwards or downwards in the future; it
7008 * is only necessary that true be returned for a small
7009 * subset of pmaps for proper page aging.
7012 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7014 struct md_page *pvh;
7015 struct rwlock *lock;
7020 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7021 ("pmap_page_exists_quick: page %p is not managed", m));
7023 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7025 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7026 if (PV_PMAP(pv) == pmap) {
7034 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7035 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7036 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7037 if (PV_PMAP(pv) == pmap) {
7051 * pmap_page_wired_mappings:
7053 * Return the number of managed mappings to the given physical page
7057 pmap_page_wired_mappings(vm_page_t m)
7059 struct rwlock *lock;
7060 struct md_page *pvh;
7064 int count, md_gen, pvh_gen;
7066 if ((m->oflags & VPO_UNMANAGED) != 0)
7068 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7072 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7074 if (!PMAP_TRYLOCK(pmap)) {
7075 md_gen = m->md.pv_gen;
7079 if (md_gen != m->md.pv_gen) {
7084 pte = pmap_pte(pmap, pv->pv_va);
7085 if ((*pte & PG_W) != 0)
7089 if ((m->flags & PG_FICTITIOUS) == 0) {
7090 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7091 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7093 if (!PMAP_TRYLOCK(pmap)) {
7094 md_gen = m->md.pv_gen;
7095 pvh_gen = pvh->pv_gen;
7099 if (md_gen != m->md.pv_gen ||
7100 pvh_gen != pvh->pv_gen) {
7105 pte = pmap_pde(pmap, pv->pv_va);
7106 if ((*pte & PG_W) != 0)
7116 * Returns TRUE if the given page is mapped individually or as part of
7117 * a 2mpage. Otherwise, returns FALSE.
7120 pmap_page_is_mapped(vm_page_t m)
7122 struct rwlock *lock;
7125 if ((m->oflags & VPO_UNMANAGED) != 0)
7127 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7129 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7130 ((m->flags & PG_FICTITIOUS) == 0 &&
7131 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7137 * Destroy all managed, non-wired mappings in the given user-space
7138 * pmap. This pmap cannot be active on any processor besides the
7141 * This function cannot be applied to the kernel pmap. Moreover, it
7142 * is not intended for general use. It is only to be used during
7143 * process termination. Consequently, it can be implemented in ways
7144 * that make it faster than pmap_remove(). First, it can more quickly
7145 * destroy mappings by iterating over the pmap's collection of PV
7146 * entries, rather than searching the page table. Second, it doesn't
7147 * have to test and clear the page table entries atomically, because
7148 * no processor is currently accessing the user address space. In
7149 * particular, a page table entry's dirty bit won't change state once
7150 * this function starts.
7152 * Although this function destroys all of the pmap's managed,
7153 * non-wired mappings, it can delay and batch the invalidation of TLB
7154 * entries without calling pmap_delayed_invl_start() and
7155 * pmap_delayed_invl_finish(). Because the pmap is not active on
7156 * any other processor, none of these TLB entries will ever be used
7157 * before their eventual invalidation. Consequently, there is no need
7158 * for either pmap_remove_all() or pmap_remove_write() to wait for
7159 * that eventual TLB invalidation.
7162 pmap_remove_pages(pmap_t pmap)
7165 pt_entry_t *pte, tpte;
7166 pt_entry_t PG_M, PG_RW, PG_V;
7167 struct spglist free;
7168 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7169 vm_page_t m, mpte, mt;
7171 struct md_page *pvh;
7172 struct pv_chunk *pc, *npc;
7173 struct rwlock *lock;
7175 uint64_t inuse, bitmask;
7176 int allfree, field, freed, i, idx;
7177 boolean_t superpage;
7181 * Assert that the given pmap is only active on the current
7182 * CPU. Unfortunately, we cannot block another CPU from
7183 * activating the pmap while this function is executing.
7185 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7188 cpuset_t other_cpus;
7190 other_cpus = all_cpus;
7192 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7193 CPU_AND(&other_cpus, &pmap->pm_active);
7195 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7200 PG_M = pmap_modified_bit(pmap);
7201 PG_V = pmap_valid_bit(pmap);
7202 PG_RW = pmap_rw_bit(pmap);
7204 for (i = 0; i < PMAP_MEMDOM; i++)
7205 TAILQ_INIT(&free_chunks[i]);
7208 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7211 for (field = 0; field < _NPCM; field++) {
7212 inuse = ~pc->pc_map[field] & pc_freemask[field];
7213 while (inuse != 0) {
7215 bitmask = 1UL << bit;
7216 idx = field * 64 + bit;
7217 pv = &pc->pc_pventry[idx];
7220 pte = pmap_pdpe(pmap, pv->pv_va);
7222 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7224 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7227 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7229 pte = &pte[pmap_pte_index(pv->pv_va)];
7233 * Keep track whether 'tpte' is a
7234 * superpage explicitly instead of
7235 * relying on PG_PS being set.
7237 * This is because PG_PS is numerically
7238 * identical to PG_PTE_PAT and thus a
7239 * regular page could be mistaken for
7245 if ((tpte & PG_V) == 0) {
7246 panic("bad pte va %lx pte %lx",
7251 * We cannot remove wired pages from a process' mapping at this time
7259 pa = tpte & PG_PS_FRAME;
7261 pa = tpte & PG_FRAME;
7263 m = PHYS_TO_VM_PAGE(pa);
7264 KASSERT(m->phys_addr == pa,
7265 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7266 m, (uintmax_t)m->phys_addr,
7269 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7270 m < &vm_page_array[vm_page_array_size],
7271 ("pmap_remove_pages: bad tpte %#jx",
7277 * Update the vm_page_t clean/reference bits.
7279 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7281 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7287 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7290 pc->pc_map[field] |= bitmask;
7292 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7293 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7294 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7296 if (TAILQ_EMPTY(&pvh->pv_list)) {
7297 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7298 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
7299 TAILQ_EMPTY(&mt->md.pv_list))
7300 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7302 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7304 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7305 ("pmap_remove_pages: pte page not promoted"));
7306 pmap_resident_count_dec(pmap, 1);
7307 KASSERT(mpte->ref_count == NPTEPG,
7308 ("pmap_remove_pages: pte page reference count error"));
7309 mpte->ref_count = 0;
7310 pmap_add_delayed_free_list(mpte, &free, FALSE);
7313 pmap_resident_count_dec(pmap, 1);
7314 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7316 if ((m->aflags & PGA_WRITEABLE) != 0 &&
7317 TAILQ_EMPTY(&m->md.pv_list) &&
7318 (m->flags & PG_FICTITIOUS) == 0) {
7319 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7320 if (TAILQ_EMPTY(&pvh->pv_list))
7321 vm_page_aflag_clear(m, PGA_WRITEABLE);
7324 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7328 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7329 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7330 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7332 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7333 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7338 pmap_invalidate_all(pmap);
7339 pmap_pkru_deassign_all(pmap);
7340 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7342 vm_page_free_pages_toq(&free, true);
7346 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7348 struct rwlock *lock;
7350 struct md_page *pvh;
7351 pt_entry_t *pte, mask;
7352 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7354 int md_gen, pvh_gen;
7358 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7361 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7363 if (!PMAP_TRYLOCK(pmap)) {
7364 md_gen = m->md.pv_gen;
7368 if (md_gen != m->md.pv_gen) {
7373 pte = pmap_pte(pmap, pv->pv_va);
7376 PG_M = pmap_modified_bit(pmap);
7377 PG_RW = pmap_rw_bit(pmap);
7378 mask |= PG_RW | PG_M;
7381 PG_A = pmap_accessed_bit(pmap);
7382 PG_V = pmap_valid_bit(pmap);
7383 mask |= PG_V | PG_A;
7385 rv = (*pte & mask) == mask;
7390 if ((m->flags & PG_FICTITIOUS) == 0) {
7391 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7392 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7394 if (!PMAP_TRYLOCK(pmap)) {
7395 md_gen = m->md.pv_gen;
7396 pvh_gen = pvh->pv_gen;
7400 if (md_gen != m->md.pv_gen ||
7401 pvh_gen != pvh->pv_gen) {
7406 pte = pmap_pde(pmap, pv->pv_va);
7409 PG_M = pmap_modified_bit(pmap);
7410 PG_RW = pmap_rw_bit(pmap);
7411 mask |= PG_RW | PG_M;
7414 PG_A = pmap_accessed_bit(pmap);
7415 PG_V = pmap_valid_bit(pmap);
7416 mask |= PG_V | PG_A;
7418 rv = (*pte & mask) == mask;
7432 * Return whether or not the specified physical page was modified
7433 * in any physical maps.
7436 pmap_is_modified(vm_page_t m)
7439 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7440 ("pmap_is_modified: page %p is not managed", m));
7443 * If the page is not busied then this check is racy.
7445 if (!pmap_page_is_write_mapped(m))
7447 return (pmap_page_test_mappings(m, FALSE, TRUE));
7451 * pmap_is_prefaultable:
7453 * Return whether or not the specified virtual address is eligible
7457 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7460 pt_entry_t *pte, PG_V;
7463 PG_V = pmap_valid_bit(pmap);
7466 pde = pmap_pde(pmap, addr);
7467 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7468 pte = pmap_pde_to_pte(pde, addr);
7469 rv = (*pte & PG_V) == 0;
7476 * pmap_is_referenced:
7478 * Return whether or not the specified physical page was referenced
7479 * in any physical maps.
7482 pmap_is_referenced(vm_page_t m)
7485 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7486 ("pmap_is_referenced: page %p is not managed", m));
7487 return (pmap_page_test_mappings(m, TRUE, FALSE));
7491 * Clear the write and modified bits in each of the given page's mappings.
7494 pmap_remove_write(vm_page_t m)
7496 struct md_page *pvh;
7498 struct rwlock *lock;
7499 pv_entry_t next_pv, pv;
7501 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7503 int pvh_gen, md_gen;
7505 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7506 ("pmap_remove_write: page %p is not managed", m));
7508 vm_page_assert_busied(m);
7509 if (!pmap_page_is_write_mapped(m))
7512 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7513 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7514 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7517 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7519 if (!PMAP_TRYLOCK(pmap)) {
7520 pvh_gen = pvh->pv_gen;
7524 if (pvh_gen != pvh->pv_gen) {
7530 PG_RW = pmap_rw_bit(pmap);
7532 pde = pmap_pde(pmap, va);
7533 if ((*pde & PG_RW) != 0)
7534 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7535 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7536 ("inconsistent pv lock %p %p for page %p",
7537 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7540 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7542 if (!PMAP_TRYLOCK(pmap)) {
7543 pvh_gen = pvh->pv_gen;
7544 md_gen = m->md.pv_gen;
7548 if (pvh_gen != pvh->pv_gen ||
7549 md_gen != m->md.pv_gen) {
7555 PG_M = pmap_modified_bit(pmap);
7556 PG_RW = pmap_rw_bit(pmap);
7557 pde = pmap_pde(pmap, pv->pv_va);
7558 KASSERT((*pde & PG_PS) == 0,
7559 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7561 pte = pmap_pde_to_pte(pde, pv->pv_va);
7564 if (oldpte & PG_RW) {
7565 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7568 if ((oldpte & PG_M) != 0)
7570 pmap_invalidate_page(pmap, pv->pv_va);
7575 vm_page_aflag_clear(m, PGA_WRITEABLE);
7576 pmap_delayed_invl_wait(m);
7579 static __inline boolean_t
7580 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7583 if (!pmap_emulate_ad_bits(pmap))
7586 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7589 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7590 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7591 * if the EPT_PG_WRITE bit is set.
7593 if ((pte & EPT_PG_WRITE) != 0)
7597 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7599 if ((pte & EPT_PG_EXECUTE) == 0 ||
7600 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7607 * pmap_ts_referenced:
7609 * Return a count of reference bits for a page, clearing those bits.
7610 * It is not necessary for every reference bit to be cleared, but it
7611 * is necessary that 0 only be returned when there are truly no
7612 * reference bits set.
7614 * As an optimization, update the page's dirty field if a modified bit is
7615 * found while counting reference bits. This opportunistic update can be
7616 * performed at low cost and can eliminate the need for some future calls
7617 * to pmap_is_modified(). However, since this function stops after
7618 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7619 * dirty pages. Those dirty pages will only be detected by a future call
7620 * to pmap_is_modified().
7622 * A DI block is not needed within this function, because
7623 * invalidations are performed before the PV list lock is
7627 pmap_ts_referenced(vm_page_t m)
7629 struct md_page *pvh;
7632 struct rwlock *lock;
7633 pd_entry_t oldpde, *pde;
7634 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7637 int cleared, md_gen, not_cleared, pvh_gen;
7638 struct spglist free;
7641 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7642 ("pmap_ts_referenced: page %p is not managed", m));
7645 pa = VM_PAGE_TO_PHYS(m);
7646 lock = PHYS_TO_PV_LIST_LOCK(pa);
7647 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7651 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7652 goto small_mappings;
7658 if (!PMAP_TRYLOCK(pmap)) {
7659 pvh_gen = pvh->pv_gen;
7663 if (pvh_gen != pvh->pv_gen) {
7668 PG_A = pmap_accessed_bit(pmap);
7669 PG_M = pmap_modified_bit(pmap);
7670 PG_RW = pmap_rw_bit(pmap);
7672 pde = pmap_pde(pmap, pv->pv_va);
7674 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7676 * Although "oldpde" is mapping a 2MB page, because
7677 * this function is called at a 4KB page granularity,
7678 * we only update the 4KB page under test.
7682 if ((oldpde & PG_A) != 0) {
7684 * Since this reference bit is shared by 512 4KB
7685 * pages, it should not be cleared every time it is
7686 * tested. Apply a simple "hash" function on the
7687 * physical page number, the virtual superpage number,
7688 * and the pmap address to select one 4KB page out of
7689 * the 512 on which testing the reference bit will
7690 * result in clearing that reference bit. This
7691 * function is designed to avoid the selection of the
7692 * same 4KB page for every 2MB page mapping.
7694 * On demotion, a mapping that hasn't been referenced
7695 * is simply destroyed. To avoid the possibility of a
7696 * subsequent page fault on a demoted wired mapping,
7697 * always leave its reference bit set. Moreover,
7698 * since the superpage is wired, the current state of
7699 * its reference bit won't affect page replacement.
7701 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7702 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7703 (oldpde & PG_W) == 0) {
7704 if (safe_to_clear_referenced(pmap, oldpde)) {
7705 atomic_clear_long(pde, PG_A);
7706 pmap_invalidate_page(pmap, pv->pv_va);
7708 } else if (pmap_demote_pde_locked(pmap, pde,
7709 pv->pv_va, &lock)) {
7711 * Remove the mapping to a single page
7712 * so that a subsequent access may
7713 * repromote. Since the underlying
7714 * page table page is fully populated,
7715 * this removal never frees a page
7719 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7721 pte = pmap_pde_to_pte(pde, va);
7722 pmap_remove_pte(pmap, pte, va, *pde,
7724 pmap_invalidate_page(pmap, va);
7730 * The superpage mapping was removed
7731 * entirely and therefore 'pv' is no
7739 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7740 ("inconsistent pv lock %p %p for page %p",
7741 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7746 /* Rotate the PV list if it has more than one entry. */
7747 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7748 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7749 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7752 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7754 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7756 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7763 if (!PMAP_TRYLOCK(pmap)) {
7764 pvh_gen = pvh->pv_gen;
7765 md_gen = m->md.pv_gen;
7769 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7774 PG_A = pmap_accessed_bit(pmap);
7775 PG_M = pmap_modified_bit(pmap);
7776 PG_RW = pmap_rw_bit(pmap);
7777 pde = pmap_pde(pmap, pv->pv_va);
7778 KASSERT((*pde & PG_PS) == 0,
7779 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7781 pte = pmap_pde_to_pte(pde, pv->pv_va);
7782 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7784 if ((*pte & PG_A) != 0) {
7785 if (safe_to_clear_referenced(pmap, *pte)) {
7786 atomic_clear_long(pte, PG_A);
7787 pmap_invalidate_page(pmap, pv->pv_va);
7789 } else if ((*pte & PG_W) == 0) {
7791 * Wired pages cannot be paged out so
7792 * doing accessed bit emulation for
7793 * them is wasted effort. We do the
7794 * hard work for unwired pages only.
7796 pmap_remove_pte(pmap, pte, pv->pv_va,
7797 *pde, &free, &lock);
7798 pmap_invalidate_page(pmap, pv->pv_va);
7803 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7804 ("inconsistent pv lock %p %p for page %p",
7805 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7810 /* Rotate the PV list if it has more than one entry. */
7811 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7812 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7813 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7816 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7817 not_cleared < PMAP_TS_REFERENCED_MAX);
7820 vm_page_free_pages_toq(&free, true);
7821 return (cleared + not_cleared);
7825 * Apply the given advice to the specified range of addresses within the
7826 * given pmap. Depending on the advice, clear the referenced and/or
7827 * modified flags in each mapping and set the mapped page's dirty field.
7830 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7832 struct rwlock *lock;
7833 pml4_entry_t *pml4e;
7835 pd_entry_t oldpde, *pde;
7836 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7837 vm_offset_t va, va_next;
7841 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7845 * A/D bit emulation requires an alternate code path when clearing
7846 * the modified and accessed bits below. Since this function is
7847 * advisory in nature we skip it entirely for pmaps that require
7848 * A/D bit emulation.
7850 if (pmap_emulate_ad_bits(pmap))
7853 PG_A = pmap_accessed_bit(pmap);
7854 PG_G = pmap_global_bit(pmap);
7855 PG_M = pmap_modified_bit(pmap);
7856 PG_V = pmap_valid_bit(pmap);
7857 PG_RW = pmap_rw_bit(pmap);
7859 pmap_delayed_invl_start();
7861 for (; sva < eva; sva = va_next) {
7862 pml4e = pmap_pml4e(pmap, sva);
7863 if ((*pml4e & PG_V) == 0) {
7864 va_next = (sva + NBPML4) & ~PML4MASK;
7869 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7870 if ((*pdpe & PG_V) == 0) {
7871 va_next = (sva + NBPDP) & ~PDPMASK;
7876 va_next = (sva + NBPDR) & ~PDRMASK;
7879 pde = pmap_pdpe_to_pde(pdpe, sva);
7881 if ((oldpde & PG_V) == 0)
7883 else if ((oldpde & PG_PS) != 0) {
7884 if ((oldpde & PG_MANAGED) == 0)
7887 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7892 * The large page mapping was destroyed.
7898 * Unless the page mappings are wired, remove the
7899 * mapping to a single page so that a subsequent
7900 * access may repromote. Choosing the last page
7901 * within the address range [sva, min(va_next, eva))
7902 * generally results in more repromotions. Since the
7903 * underlying page table page is fully populated, this
7904 * removal never frees a page table page.
7906 if ((oldpde & PG_W) == 0) {
7912 ("pmap_advise: no address gap"));
7913 pte = pmap_pde_to_pte(pde, va);
7914 KASSERT((*pte & PG_V) != 0,
7915 ("pmap_advise: invalid PTE"));
7916 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7926 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7928 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7930 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7931 if (advice == MADV_DONTNEED) {
7933 * Future calls to pmap_is_modified()
7934 * can be avoided by making the page
7937 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7940 atomic_clear_long(pte, PG_M | PG_A);
7941 } else if ((*pte & PG_A) != 0)
7942 atomic_clear_long(pte, PG_A);
7946 if ((*pte & PG_G) != 0) {
7953 if (va != va_next) {
7954 pmap_invalidate_range(pmap, va, sva);
7959 pmap_invalidate_range(pmap, va, sva);
7962 pmap_invalidate_all(pmap);
7964 pmap_delayed_invl_finish();
7968 * Clear the modify bits on the specified physical page.
7971 pmap_clear_modify(vm_page_t m)
7973 struct md_page *pvh;
7975 pv_entry_t next_pv, pv;
7976 pd_entry_t oldpde, *pde;
7977 pt_entry_t *pte, PG_M, PG_RW;
7978 struct rwlock *lock;
7980 int md_gen, pvh_gen;
7982 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7983 ("pmap_clear_modify: page %p is not managed", m));
7984 vm_page_assert_busied(m);
7986 if (!pmap_page_is_write_mapped(m))
7988 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7989 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7990 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7993 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7995 if (!PMAP_TRYLOCK(pmap)) {
7996 pvh_gen = pvh->pv_gen;
8000 if (pvh_gen != pvh->pv_gen) {
8005 PG_M = pmap_modified_bit(pmap);
8006 PG_RW = pmap_rw_bit(pmap);
8008 pde = pmap_pde(pmap, va);
8010 /* If oldpde has PG_RW set, then it also has PG_M set. */
8011 if ((oldpde & PG_RW) != 0 &&
8012 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8013 (oldpde & PG_W) == 0) {
8015 * Write protect the mapping to a single page so that
8016 * a subsequent write access may repromote.
8018 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8019 pte = pmap_pde_to_pte(pde, va);
8020 atomic_clear_long(pte, PG_M | PG_RW);
8022 pmap_invalidate_page(pmap, va);
8026 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8028 if (!PMAP_TRYLOCK(pmap)) {
8029 md_gen = m->md.pv_gen;
8030 pvh_gen = pvh->pv_gen;
8034 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8039 PG_M = pmap_modified_bit(pmap);
8040 PG_RW = pmap_rw_bit(pmap);
8041 pde = pmap_pde(pmap, pv->pv_va);
8042 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8043 " a 2mpage in page %p's pv list", m));
8044 pte = pmap_pde_to_pte(pde, pv->pv_va);
8045 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8046 atomic_clear_long(pte, PG_M);
8047 pmap_invalidate_page(pmap, pv->pv_va);
8055 * Miscellaneous support routines follow
8058 /* Adjust the properties for a leaf page table entry. */
8059 static __inline void
8060 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8064 opte = *(u_long *)pte;
8066 npte = opte & ~mask;
8068 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8073 * Map a set of physical memory pages into the kernel virtual
8074 * address space. Return a pointer to where it is mapped. This
8075 * routine is intended to be used for mapping device memory,
8079 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8081 struct pmap_preinit_mapping *ppim;
8082 vm_offset_t va, offset;
8086 offset = pa & PAGE_MASK;
8087 size = round_page(offset + size);
8088 pa = trunc_page(pa);
8090 if (!pmap_initialized) {
8092 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8093 ppim = pmap_preinit_mapping + i;
8094 if (ppim->va == 0) {
8098 ppim->va = virtual_avail;
8099 virtual_avail += size;
8105 panic("%s: too many preinit mappings", __func__);
8108 * If we have a preinit mapping, re-use it.
8110 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8111 ppim = pmap_preinit_mapping + i;
8112 if (ppim->pa == pa && ppim->sz == size &&
8113 (ppim->mode == mode ||
8114 (flags & MAPDEV_SETATTR) == 0))
8115 return ((void *)(ppim->va + offset));
8118 * If the specified range of physical addresses fits within
8119 * the direct map window, use the direct map.
8121 if (pa < dmaplimit && pa + size <= dmaplimit) {
8122 va = PHYS_TO_DMAP(pa);
8123 if ((flags & MAPDEV_SETATTR) != 0) {
8124 PMAP_LOCK(kernel_pmap);
8125 i = pmap_change_props_locked(va, size,
8126 PROT_NONE, mode, flags);
8127 PMAP_UNLOCK(kernel_pmap);
8131 return ((void *)(va + offset));
8133 va = kva_alloc(size);
8135 panic("%s: Couldn't allocate KVA", __func__);
8137 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8138 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8139 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8140 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8141 pmap_invalidate_cache_range(va, va + tmpsize);
8142 return ((void *)(va + offset));
8146 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8149 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8154 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8157 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8161 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8164 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8169 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8172 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8173 MAPDEV_FLUSHCACHE));
8177 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8179 struct pmap_preinit_mapping *ppim;
8183 /* If we gave a direct map region in pmap_mapdev, do nothing */
8184 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8186 offset = va & PAGE_MASK;
8187 size = round_page(offset + size);
8188 va = trunc_page(va);
8189 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8190 ppim = pmap_preinit_mapping + i;
8191 if (ppim->va == va && ppim->sz == size) {
8192 if (pmap_initialized)
8198 if (va + size == virtual_avail)
8203 if (pmap_initialized)
8208 * Tries to demote a 1GB page mapping.
8211 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8213 pdp_entry_t newpdpe, oldpdpe;
8214 pd_entry_t *firstpde, newpde, *pde;
8215 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8219 PG_A = pmap_accessed_bit(pmap);
8220 PG_M = pmap_modified_bit(pmap);
8221 PG_V = pmap_valid_bit(pmap);
8222 PG_RW = pmap_rw_bit(pmap);
8224 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8226 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8227 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8228 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8229 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8230 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8231 " in pmap %p", va, pmap);
8234 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8235 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8236 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8237 KASSERT((oldpdpe & PG_A) != 0,
8238 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8239 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8240 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8244 * Initialize the page directory page.
8246 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8252 * Demote the mapping.
8257 * Invalidate a stale recursive mapping of the page directory page.
8259 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8261 pmap_pdpe_demotions++;
8262 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8263 " in pmap %p", va, pmap);
8268 * Sets the memory attribute for the specified page.
8271 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8274 m->md.pat_mode = ma;
8277 * If "m" is a normal page, update its direct mapping. This update
8278 * can be relied upon to perform any cache operations that are
8279 * required for data coherence.
8281 if ((m->flags & PG_FICTITIOUS) == 0 &&
8282 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8284 panic("memory attribute change on the direct map failed");
8288 * Changes the specified virtual address range's memory type to that given by
8289 * the parameter "mode". The specified virtual address range must be
8290 * completely contained within either the direct map or the kernel map. If
8291 * the virtual address range is contained within the kernel map, then the
8292 * memory type for each of the corresponding ranges of the direct map is also
8293 * changed. (The corresponding ranges of the direct map are those ranges that
8294 * map the same physical pages as the specified virtual address range.) These
8295 * changes to the direct map are necessary because Intel describes the
8296 * behavior of their processors as "undefined" if two or more mappings to the
8297 * same physical page have different memory types.
8299 * Returns zero if the change completed successfully, and either EINVAL or
8300 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8301 * of the virtual address range was not mapped, and ENOMEM is returned if
8302 * there was insufficient memory available to complete the change. In the
8303 * latter case, the memory type may have been changed on some part of the
8304 * virtual address range or the direct map.
8307 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8311 PMAP_LOCK(kernel_pmap);
8312 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8314 PMAP_UNLOCK(kernel_pmap);
8319 * Changes the specified virtual address range's protections to those
8320 * specified by "prot". Like pmap_change_attr(), protections for aliases
8321 * in the direct map are updated as well. Protections on aliasing mappings may
8322 * be a subset of the requested protections; for example, mappings in the direct
8323 * map are never executable.
8326 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8330 /* Only supported within the kernel map. */
8331 if (va < VM_MIN_KERNEL_ADDRESS)
8334 PMAP_LOCK(kernel_pmap);
8335 error = pmap_change_props_locked(va, size, prot, -1,
8336 MAPDEV_ASSERTVALID);
8337 PMAP_UNLOCK(kernel_pmap);
8342 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8343 int mode, int flags)
8345 vm_offset_t base, offset, tmpva;
8346 vm_paddr_t pa_start, pa_end, pa_end1;
8348 pd_entry_t *pde, pde_bits, pde_mask;
8349 pt_entry_t *pte, pte_bits, pte_mask;
8353 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8354 base = trunc_page(va);
8355 offset = va & PAGE_MASK;
8356 size = round_page(offset + size);
8359 * Only supported on kernel virtual addresses, including the direct
8360 * map but excluding the recursive map.
8362 if (base < DMAP_MIN_ADDRESS)
8366 * Construct our flag sets and masks. "bits" is the subset of
8367 * "mask" that will be set in each modified PTE.
8369 * Mappings in the direct map are never allowed to be executable.
8371 pde_bits = pte_bits = 0;
8372 pde_mask = pte_mask = 0;
8374 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8375 pde_mask |= X86_PG_PDE_CACHE;
8376 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8377 pte_mask |= X86_PG_PTE_CACHE;
8379 if (prot != VM_PROT_NONE) {
8380 if ((prot & VM_PROT_WRITE) != 0) {
8381 pde_bits |= X86_PG_RW;
8382 pte_bits |= X86_PG_RW;
8384 if ((prot & VM_PROT_EXECUTE) == 0 ||
8385 va < VM_MIN_KERNEL_ADDRESS) {
8389 pde_mask |= X86_PG_RW | pg_nx;
8390 pte_mask |= X86_PG_RW | pg_nx;
8394 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8395 * into 4KB pages if required.
8397 for (tmpva = base; tmpva < base + size; ) {
8398 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8399 if (pdpe == NULL || *pdpe == 0) {
8400 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8401 ("%s: addr %#lx is not mapped", __func__, tmpva));
8404 if (*pdpe & PG_PS) {
8406 * If the current 1GB page already has the required
8407 * properties, then we need not demote this page. Just
8408 * increment tmpva to the next 1GB page frame.
8410 if ((*pdpe & pde_mask) == pde_bits) {
8411 tmpva = trunc_1gpage(tmpva) + NBPDP;
8416 * If the current offset aligns with a 1GB page frame
8417 * and there is at least 1GB left within the range, then
8418 * we need not break down this page into 2MB pages.
8420 if ((tmpva & PDPMASK) == 0 &&
8421 tmpva + PDPMASK < base + size) {
8425 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8428 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8430 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8431 ("%s: addr %#lx is not mapped", __func__, tmpva));
8436 * If the current 2MB page already has the required
8437 * properties, then we need not demote this page. Just
8438 * increment tmpva to the next 2MB page frame.
8440 if ((*pde & pde_mask) == pde_bits) {
8441 tmpva = trunc_2mpage(tmpva) + NBPDR;
8446 * If the current offset aligns with a 2MB page frame
8447 * and there is at least 2MB left within the range, then
8448 * we need not break down this page into 4KB pages.
8450 if ((tmpva & PDRMASK) == 0 &&
8451 tmpva + PDRMASK < base + size) {
8455 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8458 pte = pmap_pde_to_pte(pde, tmpva);
8460 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8461 ("%s: addr %#lx is not mapped", __func__, tmpva));
8469 * Ok, all the pages exist, so run through them updating their
8470 * properties if required.
8473 pa_start = pa_end = 0;
8474 for (tmpva = base; tmpva < base + size; ) {
8475 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8476 if (*pdpe & PG_PS) {
8477 if ((*pdpe & pde_mask) != pde_bits) {
8478 pmap_pte_props(pdpe, pde_bits, pde_mask);
8481 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8482 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8483 if (pa_start == pa_end) {
8484 /* Start physical address run. */
8485 pa_start = *pdpe & PG_PS_FRAME;
8486 pa_end = pa_start + NBPDP;
8487 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8490 /* Run ended, update direct map. */
8491 error = pmap_change_props_locked(
8492 PHYS_TO_DMAP(pa_start),
8493 pa_end - pa_start, prot, mode,
8497 /* Start physical address run. */
8498 pa_start = *pdpe & PG_PS_FRAME;
8499 pa_end = pa_start + NBPDP;
8502 tmpva = trunc_1gpage(tmpva) + NBPDP;
8505 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8507 if ((*pde & pde_mask) != pde_bits) {
8508 pmap_pte_props(pde, pde_bits, pde_mask);
8511 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8512 (*pde & PG_PS_FRAME) < dmaplimit) {
8513 if (pa_start == pa_end) {
8514 /* Start physical address run. */
8515 pa_start = *pde & PG_PS_FRAME;
8516 pa_end = pa_start + NBPDR;
8517 } else if (pa_end == (*pde & PG_PS_FRAME))
8520 /* Run ended, update direct map. */
8521 error = pmap_change_props_locked(
8522 PHYS_TO_DMAP(pa_start),
8523 pa_end - pa_start, prot, mode,
8527 /* Start physical address run. */
8528 pa_start = *pde & PG_PS_FRAME;
8529 pa_end = pa_start + NBPDR;
8532 tmpva = trunc_2mpage(tmpva) + NBPDR;
8534 pte = pmap_pde_to_pte(pde, tmpva);
8535 if ((*pte & pte_mask) != pte_bits) {
8536 pmap_pte_props(pte, pte_bits, pte_mask);
8539 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8540 (*pte & PG_FRAME) < dmaplimit) {
8541 if (pa_start == pa_end) {
8542 /* Start physical address run. */
8543 pa_start = *pte & PG_FRAME;
8544 pa_end = pa_start + PAGE_SIZE;
8545 } else if (pa_end == (*pte & PG_FRAME))
8546 pa_end += PAGE_SIZE;
8548 /* Run ended, update direct map. */
8549 error = pmap_change_props_locked(
8550 PHYS_TO_DMAP(pa_start),
8551 pa_end - pa_start, prot, mode,
8555 /* Start physical address run. */
8556 pa_start = *pte & PG_FRAME;
8557 pa_end = pa_start + PAGE_SIZE;
8563 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8564 pa_end1 = MIN(pa_end, dmaplimit);
8565 if (pa_start != pa_end1)
8566 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
8567 pa_end1 - pa_start, prot, mode, flags);
8571 * Flush CPU caches if required to make sure any data isn't cached that
8572 * shouldn't be, etc.
8575 pmap_invalidate_range(kernel_pmap, base, tmpva);
8576 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8577 pmap_invalidate_cache_range(base, tmpva);
8583 * Demotes any mapping within the direct map region that covers more than the
8584 * specified range of physical addresses. This range's size must be a power
8585 * of two and its starting address must be a multiple of its size. Since the
8586 * demotion does not change any attributes of the mapping, a TLB invalidation
8587 * is not mandatory. The caller may, however, request a TLB invalidation.
8590 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8599 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8600 KASSERT((base & (len - 1)) == 0,
8601 ("pmap_demote_DMAP: base is not a multiple of len"));
8602 if (len < NBPDP && base < dmaplimit) {
8603 va = PHYS_TO_DMAP(base);
8605 PMAP_LOCK(kernel_pmap);
8606 pdpe = pmap_pdpe(kernel_pmap, va);
8607 if ((*pdpe & X86_PG_V) == 0)
8608 panic("pmap_demote_DMAP: invalid PDPE");
8609 if ((*pdpe & PG_PS) != 0) {
8610 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8611 panic("pmap_demote_DMAP: PDPE failed");
8615 pde = pmap_pdpe_to_pde(pdpe, va);
8616 if ((*pde & X86_PG_V) == 0)
8617 panic("pmap_demote_DMAP: invalid PDE");
8618 if ((*pde & PG_PS) != 0) {
8619 if (!pmap_demote_pde(kernel_pmap, pde, va))
8620 panic("pmap_demote_DMAP: PDE failed");
8624 if (changed && invalidate)
8625 pmap_invalidate_page(kernel_pmap, va);
8626 PMAP_UNLOCK(kernel_pmap);
8631 * Perform the pmap work for mincore(2). If the page is not both referenced and
8632 * modified by this pmap, returns its physical address so that the caller can
8633 * find other mappings.
8636 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
8639 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8643 PG_A = pmap_accessed_bit(pmap);
8644 PG_M = pmap_modified_bit(pmap);
8645 PG_V = pmap_valid_bit(pmap);
8646 PG_RW = pmap_rw_bit(pmap);
8649 pdep = pmap_pde(pmap, addr);
8650 if (pdep != NULL && (*pdep & PG_V)) {
8651 if (*pdep & PG_PS) {
8653 /* Compute the physical address of the 4KB page. */
8654 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8656 val = MINCORE_SUPER;
8658 pte = *pmap_pde_to_pte(pdep, addr);
8659 pa = pte & PG_FRAME;
8667 if ((pte & PG_V) != 0) {
8668 val |= MINCORE_INCORE;
8669 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8670 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8671 if ((pte & PG_A) != 0)
8672 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8674 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8675 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8676 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8684 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8686 uint32_t gen, new_gen, pcid_next;
8688 CRITICAL_ASSERT(curthread);
8689 gen = PCPU_GET(pcid_gen);
8690 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8691 return (pti ? 0 : CR3_PCID_SAVE);
8692 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8693 return (CR3_PCID_SAVE);
8694 pcid_next = PCPU_GET(pcid_next);
8695 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8696 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8697 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8698 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8699 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8703 PCPU_SET(pcid_gen, new_gen);
8704 pcid_next = PMAP_PCID_KERN + 1;
8708 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8709 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8710 PCPU_SET(pcid_next, pcid_next + 1);
8715 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8719 cached = pmap_pcid_alloc(pmap, cpuid);
8720 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8721 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8722 pmap->pm_pcids[cpuid].pm_pcid));
8723 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8724 pmap == kernel_pmap,
8725 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8726 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8731 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8734 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8735 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
8739 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8741 struct invpcid_descr d;
8742 uint64_t cached, cr3, kcr3, ucr3;
8744 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8746 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8747 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8748 PCPU_SET(curpmap, pmap);
8749 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8750 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8753 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8755 * Explicitly invalidate translations cached from the
8756 * user page table. They are not automatically
8757 * flushed by reload of cr3 with the kernel page table
8760 * Note that the if() condition is resolved statically
8761 * by using the function argument instead of
8762 * runtime-evaluated invpcid_works value.
8764 if (invpcid_works1) {
8765 d.pcid = PMAP_PCID_USER_PT |
8766 pmap->pm_pcids[cpuid].pm_pcid;
8769 invpcid(&d, INVPCID_CTX);
8771 pmap_pti_pcid_invalidate(ucr3, kcr3);
8775 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8776 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8778 PCPU_INC(pm_save_cnt);
8782 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8785 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8786 pmap_activate_sw_pti_post(td, pmap);
8790 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8796 * If the INVPCID instruction is not available,
8797 * invltlb_pcid_handler() is used to handle an invalidate_all
8798 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8799 * sequence of operations has a window where %CR3 is loaded
8800 * with the new pmap's PML4 address, but the curpmap value has
8801 * not yet been updated. This causes the invltlb IPI handler,
8802 * which is called between the updates, to execute as a NOP,
8803 * which leaves stale TLB entries.
8805 * Note that the most typical use of pmap_activate_sw(), from
8806 * the context switch, is immune to this race, because
8807 * interrupts are disabled (while the thread lock is owned),
8808 * and the IPI happens after curpmap is updated. Protect
8809 * other callers in a similar way, by disabling interrupts
8810 * around the %cr3 register reload and curpmap assignment.
8812 rflags = intr_disable();
8813 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8814 intr_restore(rflags);
8815 pmap_activate_sw_pti_post(td, pmap);
8819 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8822 uint64_t cached, cr3;
8824 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8826 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8827 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8829 PCPU_SET(curpmap, pmap);
8831 PCPU_INC(pm_save_cnt);
8835 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8840 rflags = intr_disable();
8841 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8842 intr_restore(rflags);
8846 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8847 u_int cpuid __unused)
8850 load_cr3(pmap->pm_cr3);
8851 PCPU_SET(curpmap, pmap);
8855 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8856 u_int cpuid __unused)
8859 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8860 PCPU_SET(kcr3, pmap->pm_cr3);
8861 PCPU_SET(ucr3, pmap->pm_ucr3);
8862 pmap_activate_sw_pti_post(td, pmap);
8865 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8869 if (pmap_pcid_enabled && pti && invpcid_works)
8870 return (pmap_activate_sw_pcid_invpcid_pti);
8871 else if (pmap_pcid_enabled && pti && !invpcid_works)
8872 return (pmap_activate_sw_pcid_noinvpcid_pti);
8873 else if (pmap_pcid_enabled && !pti && invpcid_works)
8874 return (pmap_activate_sw_pcid_nopti);
8875 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8876 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8877 else if (!pmap_pcid_enabled && pti)
8878 return (pmap_activate_sw_nopcid_pti);
8879 else /* if (!pmap_pcid_enabled && !pti) */
8880 return (pmap_activate_sw_nopcid_nopti);
8884 pmap_activate_sw(struct thread *td)
8886 pmap_t oldpmap, pmap;
8889 oldpmap = PCPU_GET(curpmap);
8890 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8891 if (oldpmap == pmap) {
8892 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8896 cpuid = PCPU_GET(cpuid);
8898 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8900 CPU_SET(cpuid, &pmap->pm_active);
8902 pmap_activate_sw_mode(td, pmap, cpuid);
8904 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8906 CPU_CLR(cpuid, &oldpmap->pm_active);
8911 pmap_activate(struct thread *td)
8915 pmap_activate_sw(td);
8920 pmap_activate_boot(pmap_t pmap)
8926 * kernel_pmap must be never deactivated, and we ensure that
8927 * by never activating it at all.
8929 MPASS(pmap != kernel_pmap);
8931 cpuid = PCPU_GET(cpuid);
8933 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8935 CPU_SET(cpuid, &pmap->pm_active);
8937 PCPU_SET(curpmap, pmap);
8939 kcr3 = pmap->pm_cr3;
8940 if (pmap_pcid_enabled)
8941 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8945 PCPU_SET(kcr3, kcr3);
8946 PCPU_SET(ucr3, PMAP_NO_CR3);
8950 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8955 * Increase the starting virtual address of the given mapping if a
8956 * different alignment might result in more superpage mappings.
8959 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8960 vm_offset_t *addr, vm_size_t size)
8962 vm_offset_t superpage_offset;
8966 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8967 offset += ptoa(object->pg_color);
8968 superpage_offset = offset & PDRMASK;
8969 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8970 (*addr & PDRMASK) == superpage_offset)
8972 if ((*addr & PDRMASK) < superpage_offset)
8973 *addr = (*addr & ~PDRMASK) + superpage_offset;
8975 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8979 static unsigned long num_dirty_emulations;
8980 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8981 &num_dirty_emulations, 0, NULL);
8983 static unsigned long num_accessed_emulations;
8984 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8985 &num_accessed_emulations, 0, NULL);
8987 static unsigned long num_superpage_accessed_emulations;
8988 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8989 &num_superpage_accessed_emulations, 0, NULL);
8991 static unsigned long ad_emulation_superpage_promotions;
8992 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8993 &ad_emulation_superpage_promotions, 0, NULL);
8994 #endif /* INVARIANTS */
8997 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9000 struct rwlock *lock;
9001 #if VM_NRESERVLEVEL > 0
9005 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9007 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9008 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9010 if (!pmap_emulate_ad_bits(pmap))
9013 PG_A = pmap_accessed_bit(pmap);
9014 PG_M = pmap_modified_bit(pmap);
9015 PG_V = pmap_valid_bit(pmap);
9016 PG_RW = pmap_rw_bit(pmap);
9022 pde = pmap_pde(pmap, va);
9023 if (pde == NULL || (*pde & PG_V) == 0)
9026 if ((*pde & PG_PS) != 0) {
9027 if (ftype == VM_PROT_READ) {
9029 atomic_add_long(&num_superpage_accessed_emulations, 1);
9037 pte = pmap_pde_to_pte(pde, va);
9038 if ((*pte & PG_V) == 0)
9041 if (ftype == VM_PROT_WRITE) {
9042 if ((*pte & PG_RW) == 0)
9045 * Set the modified and accessed bits simultaneously.
9047 * Intel EPT PTEs that do software emulation of A/D bits map
9048 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9049 * An EPT misconfiguration is triggered if the PTE is writable
9050 * but not readable (WR=10). This is avoided by setting PG_A
9051 * and PG_M simultaneously.
9053 *pte |= PG_M | PG_A;
9058 #if VM_NRESERVLEVEL > 0
9059 /* try to promote the mapping */
9060 if (va < VM_MAXUSER_ADDRESS)
9061 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9065 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9067 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9068 pmap_ps_enabled(pmap) &&
9069 (m->flags & PG_FICTITIOUS) == 0 &&
9070 vm_reserv_level_iffullpop(m) == 0) {
9071 pmap_promote_pde(pmap, pde, va, &lock);
9073 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9079 if (ftype == VM_PROT_WRITE)
9080 atomic_add_long(&num_dirty_emulations, 1);
9082 atomic_add_long(&num_accessed_emulations, 1);
9084 rv = 0; /* success */
9093 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9098 pt_entry_t *pte, PG_V;
9102 PG_V = pmap_valid_bit(pmap);
9105 pml4 = pmap_pml4e(pmap, va);
9107 if ((*pml4 & PG_V) == 0)
9110 pdp = pmap_pml4e_to_pdpe(pml4, va);
9112 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9115 pde = pmap_pdpe_to_pde(pdp, va);
9117 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9120 pte = pmap_pde_to_pte(pde, va);
9129 * Get the kernel virtual address of a set of physical pages. If there are
9130 * physical addresses not covered by the DMAP perform a transient mapping
9131 * that will be removed when calling pmap_unmap_io_transient.
9133 * \param page The pages the caller wishes to obtain the virtual
9134 * address on the kernel memory map.
9135 * \param vaddr On return contains the kernel virtual memory address
9136 * of the pages passed in the page parameter.
9137 * \param count Number of pages passed in.
9138 * \param can_fault TRUE if the thread using the mapped pages can take
9139 * page faults, FALSE otherwise.
9141 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9142 * finished or FALSE otherwise.
9146 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9147 boolean_t can_fault)
9150 boolean_t needs_mapping;
9152 int cache_bits, error __unused, i;
9155 * Allocate any KVA space that we need, this is done in a separate
9156 * loop to prevent calling vmem_alloc while pinned.
9158 needs_mapping = FALSE;
9159 for (i = 0; i < count; i++) {
9160 paddr = VM_PAGE_TO_PHYS(page[i]);
9161 if (__predict_false(paddr >= dmaplimit)) {
9162 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9163 M_BESTFIT | M_WAITOK, &vaddr[i]);
9164 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9165 needs_mapping = TRUE;
9167 vaddr[i] = PHYS_TO_DMAP(paddr);
9171 /* Exit early if everything is covered by the DMAP */
9176 * NB: The sequence of updating a page table followed by accesses
9177 * to the corresponding pages used in the !DMAP case is subject to
9178 * the situation described in the "AMD64 Architecture Programmer's
9179 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9180 * Coherency Considerations". Therefore, issuing the INVLPG right
9181 * after modifying the PTE bits is crucial.
9185 for (i = 0; i < count; i++) {
9186 paddr = VM_PAGE_TO_PHYS(page[i]);
9187 if (paddr >= dmaplimit) {
9190 * Slow path, since we can get page faults
9191 * while mappings are active don't pin the
9192 * thread to the CPU and instead add a global
9193 * mapping visible to all CPUs.
9195 pmap_qenter(vaddr[i], &page[i], 1);
9197 pte = vtopte(vaddr[i]);
9198 cache_bits = pmap_cache_bits(kernel_pmap,
9199 page[i]->md.pat_mode, 0);
9200 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9207 return (needs_mapping);
9211 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9212 boolean_t can_fault)
9219 for (i = 0; i < count; i++) {
9220 paddr = VM_PAGE_TO_PHYS(page[i]);
9221 if (paddr >= dmaplimit) {
9223 pmap_qremove(vaddr[i], 1);
9224 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9230 pmap_quick_enter_page(vm_page_t m)
9234 paddr = VM_PAGE_TO_PHYS(m);
9235 if (paddr < dmaplimit)
9236 return (PHYS_TO_DMAP(paddr));
9237 mtx_lock_spin(&qframe_mtx);
9238 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9239 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9240 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9245 pmap_quick_remove_page(vm_offset_t addr)
9250 pte_store(vtopte(qframe), 0);
9252 mtx_unlock_spin(&qframe_mtx);
9256 * Pdp pages from the large map are managed differently from either
9257 * kernel or user page table pages. They are permanently allocated at
9258 * initialization time, and their reference count is permanently set to
9259 * zero. The pml4 entries pointing to those pages are copied into
9260 * each allocated pmap.
9262 * In contrast, pd and pt pages are managed like user page table
9263 * pages. They are dynamically allocated, and their reference count
9264 * represents the number of valid entries within the page.
9267 pmap_large_map_getptp_unlocked(void)
9271 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9273 if (m != NULL && (m->flags & PG_ZERO) == 0)
9279 pmap_large_map_getptp(void)
9283 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9284 m = pmap_large_map_getptp_unlocked();
9286 PMAP_UNLOCK(kernel_pmap);
9288 PMAP_LOCK(kernel_pmap);
9289 /* Callers retry. */
9294 static pdp_entry_t *
9295 pmap_large_map_pdpe(vm_offset_t va)
9297 vm_pindex_t pml4_idx;
9300 pml4_idx = pmap_pml4e_index(va);
9301 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9302 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9304 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9305 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
9306 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9307 "LMSPML4I %#jx lm_ents %d",
9308 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9309 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
9310 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9314 pmap_large_map_pde(vm_offset_t va)
9321 pdpe = pmap_large_map_pdpe(va);
9323 m = pmap_large_map_getptp();
9326 mphys = VM_PAGE_TO_PHYS(m);
9327 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9329 MPASS((*pdpe & X86_PG_PS) == 0);
9330 mphys = *pdpe & PG_FRAME;
9332 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9336 pmap_large_map_pte(vm_offset_t va)
9343 pde = pmap_large_map_pde(va);
9345 m = pmap_large_map_getptp();
9348 mphys = VM_PAGE_TO_PHYS(m);
9349 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9350 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9352 MPASS((*pde & X86_PG_PS) == 0);
9353 mphys = *pde & PG_FRAME;
9355 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9359 pmap_large_map_kextract(vm_offset_t va)
9361 pdp_entry_t *pdpe, pdp;
9362 pd_entry_t *pde, pd;
9363 pt_entry_t *pte, pt;
9365 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9366 ("not largemap range %#lx", (u_long)va));
9367 pdpe = pmap_large_map_pdpe(va);
9369 KASSERT((pdp & X86_PG_V) != 0,
9370 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9371 (u_long)pdpe, pdp));
9372 if ((pdp & X86_PG_PS) != 0) {
9373 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9374 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9375 (u_long)pdpe, pdp));
9376 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9378 pde = pmap_pdpe_to_pde(pdpe, va);
9380 KASSERT((pd & X86_PG_V) != 0,
9381 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9382 if ((pd & X86_PG_PS) != 0)
9383 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9384 pte = pmap_pde_to_pte(pde, va);
9386 KASSERT((pt & X86_PG_V) != 0,
9387 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9388 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9392 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9393 vmem_addr_t *vmem_res)
9397 * Large mappings are all but static. Consequently, there
9398 * is no point in waiting for an earlier allocation to be
9401 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9402 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9406 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9412 vm_offset_t va, inc;
9413 vmem_addr_t vmem_res;
9417 if (len == 0 || spa + len < spa)
9420 /* See if DMAP can serve. */
9421 if (spa + len <= dmaplimit) {
9422 va = PHYS_TO_DMAP(spa);
9424 return (pmap_change_attr(va, len, mattr));
9428 * No, allocate KVA. Fit the address with best possible
9429 * alignment for superpages. Fall back to worse align if
9433 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9434 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9435 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9437 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9439 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9442 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9447 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9448 * in the pagetable to minimize flushing. No need to
9449 * invalidate TLB, since we only update invalid entries.
9451 PMAP_LOCK(kernel_pmap);
9452 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9454 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9455 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9456 pdpe = pmap_large_map_pdpe(va);
9458 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9459 X86_PG_V | X86_PG_A | pg_nx |
9460 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9462 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9463 (va & PDRMASK) == 0) {
9464 pde = pmap_large_map_pde(va);
9466 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9467 X86_PG_V | X86_PG_A | pg_nx |
9468 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9469 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9473 pte = pmap_large_map_pte(va);
9475 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9476 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9478 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9483 PMAP_UNLOCK(kernel_pmap);
9486 *addr = (void *)vmem_res;
9491 pmap_large_unmap(void *svaa, vm_size_t len)
9493 vm_offset_t sva, va;
9495 pdp_entry_t *pdpe, pdp;
9496 pd_entry_t *pde, pd;
9499 struct spglist spgf;
9501 sva = (vm_offset_t)svaa;
9502 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9503 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9507 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9508 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9509 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9510 PMAP_LOCK(kernel_pmap);
9511 for (va = sva; va < sva + len; va += inc) {
9512 pdpe = pmap_large_map_pdpe(va);
9514 KASSERT((pdp & X86_PG_V) != 0,
9515 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9516 (u_long)pdpe, pdp));
9517 if ((pdp & X86_PG_PS) != 0) {
9518 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9519 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9520 (u_long)pdpe, pdp));
9521 KASSERT((va & PDPMASK) == 0,
9522 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9523 (u_long)pdpe, pdp));
9524 KASSERT(va + NBPDP <= sva + len,
9525 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9526 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9527 (u_long)pdpe, pdp, len));
9532 pde = pmap_pdpe_to_pde(pdpe, va);
9534 KASSERT((pd & X86_PG_V) != 0,
9535 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9537 if ((pd & X86_PG_PS) != 0) {
9538 KASSERT((va & PDRMASK) == 0,
9539 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9541 KASSERT(va + NBPDR <= sva + len,
9542 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9543 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9547 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9549 if (m->ref_count == 0) {
9551 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9555 pte = pmap_pde_to_pte(pde, va);
9556 KASSERT((*pte & X86_PG_V) != 0,
9557 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9558 (u_long)pte, *pte));
9561 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9563 if (m->ref_count == 0) {
9565 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9566 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9568 if (m->ref_count == 0) {
9570 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9574 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9575 PMAP_UNLOCK(kernel_pmap);
9576 vm_page_free_pages_toq(&spgf, false);
9577 vmem_free(large_vmem, sva, len);
9581 pmap_large_map_wb_fence_mfence(void)
9588 pmap_large_map_wb_fence_atomic(void)
9591 atomic_thread_fence_seq_cst();
9595 pmap_large_map_wb_fence_nop(void)
9599 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9602 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9603 return (pmap_large_map_wb_fence_mfence);
9604 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9605 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9606 return (pmap_large_map_wb_fence_atomic);
9608 /* clflush is strongly enough ordered */
9609 return (pmap_large_map_wb_fence_nop);
9613 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9616 for (; len > 0; len -= cpu_clflush_line_size,
9617 va += cpu_clflush_line_size)
9622 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9625 for (; len > 0; len -= cpu_clflush_line_size,
9626 va += cpu_clflush_line_size)
9631 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9634 for (; len > 0; len -= cpu_clflush_line_size,
9635 va += cpu_clflush_line_size)
9640 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9644 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9647 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9648 return (pmap_large_map_flush_range_clwb);
9649 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9650 return (pmap_large_map_flush_range_clflushopt);
9651 else if ((cpu_feature & CPUID_CLFSH) != 0)
9652 return (pmap_large_map_flush_range_clflush);
9654 return (pmap_large_map_flush_range_nop);
9658 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9660 volatile u_long *pe;
9666 for (va = sva; va < eva; va += inc) {
9668 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9669 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9671 if ((p & X86_PG_PS) != 0)
9675 pe = (volatile u_long *)pmap_large_map_pde(va);
9677 if ((p & X86_PG_PS) != 0)
9681 pe = (volatile u_long *)pmap_large_map_pte(va);
9687 if ((p & X86_PG_AVAIL1) != 0) {
9689 * Spin-wait for the end of a parallel
9696 * If we saw other write-back
9697 * occuring, we cannot rely on PG_M to
9698 * indicate state of the cache. The
9699 * PG_M bit is cleared before the
9700 * flush to avoid ignoring new writes,
9701 * and writes which are relevant for
9702 * us might happen after.
9708 if ((p & X86_PG_M) != 0 || seen_other) {
9709 if (!atomic_fcmpset_long(pe, &p,
9710 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9712 * If we saw PG_M without
9713 * PG_AVAIL1, and then on the
9714 * next attempt we do not
9715 * observe either PG_M or
9716 * PG_AVAIL1, the other
9717 * write-back started after us
9718 * and finished before us. We
9719 * can rely on it doing our
9723 pmap_large_map_flush_range(va, inc);
9724 atomic_clear_long(pe, X86_PG_AVAIL1);
9733 * Write-back cache lines for the given address range.
9735 * Must be called only on the range or sub-range returned from
9736 * pmap_large_map(). Must not be called on the coalesced ranges.
9738 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9739 * instructions support.
9742 pmap_large_map_wb(void *svap, vm_size_t len)
9744 vm_offset_t eva, sva;
9746 sva = (vm_offset_t)svap;
9748 pmap_large_map_wb_fence();
9749 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9750 pmap_large_map_flush_range(sva, len);
9752 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9753 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9754 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9755 pmap_large_map_wb_large(sva, eva);
9757 pmap_large_map_wb_fence();
9761 pmap_pti_alloc_page(void)
9765 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9766 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9767 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9772 pmap_pti_free_page(vm_page_t m)
9775 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
9776 if (!vm_page_unwire_noq(m))
9778 vm_page_free_zero(m);
9792 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9793 VM_OBJECT_WLOCK(pti_obj);
9794 pml4_pg = pmap_pti_alloc_page();
9795 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9796 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9797 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9798 pdpe = pmap_pti_pdpe(va);
9799 pmap_pti_wire_pte(pdpe);
9801 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9802 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9803 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9804 sizeof(struct gate_descriptor) * NIDT, false);
9806 /* Doublefault stack IST 1 */
9807 va = __pcpu[i].pc_common_tss.tss_ist1;
9808 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9809 /* NMI stack IST 2 */
9810 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
9811 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9812 /* MC# stack IST 3 */
9813 va = __pcpu[i].pc_common_tss.tss_ist3 +
9814 sizeof(struct nmi_pcpu);
9815 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9816 /* DB# stack IST 4 */
9817 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
9818 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9820 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9821 (vm_offset_t)etext, true);
9822 pti_finalized = true;
9823 VM_OBJECT_WUNLOCK(pti_obj);
9825 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9827 static pdp_entry_t *
9828 pmap_pti_pdpe(vm_offset_t va)
9830 pml4_entry_t *pml4e;
9833 vm_pindex_t pml4_idx;
9836 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9838 pml4_idx = pmap_pml4e_index(va);
9839 pml4e = &pti_pml4[pml4_idx];
9843 panic("pml4 alloc after finalization\n");
9844 m = pmap_pti_alloc_page();
9846 pmap_pti_free_page(m);
9847 mphys = *pml4e & ~PAGE_MASK;
9849 mphys = VM_PAGE_TO_PHYS(m);
9850 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9853 mphys = *pml4e & ~PAGE_MASK;
9855 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9860 pmap_pti_wire_pte(void *pte)
9864 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9865 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9870 pmap_pti_unwire_pde(void *pde, bool only_ref)
9874 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9875 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9876 MPASS(m->ref_count > 0);
9877 MPASS(only_ref || m->ref_count > 1);
9878 pmap_pti_free_page(m);
9882 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9887 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9888 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9889 MPASS(m->ref_count > 0);
9890 if (pmap_pti_free_page(m)) {
9891 pde = pmap_pti_pde(va);
9892 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9894 pmap_pti_unwire_pde(pde, false);
9899 pmap_pti_pde(vm_offset_t va)
9907 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9909 pdpe = pmap_pti_pdpe(va);
9911 m = pmap_pti_alloc_page();
9913 pmap_pti_free_page(m);
9914 MPASS((*pdpe & X86_PG_PS) == 0);
9915 mphys = *pdpe & ~PAGE_MASK;
9917 mphys = VM_PAGE_TO_PHYS(m);
9918 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9921 MPASS((*pdpe & X86_PG_PS) == 0);
9922 mphys = *pdpe & ~PAGE_MASK;
9925 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9926 pd_idx = pmap_pde_index(va);
9932 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9939 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9941 pde = pmap_pti_pde(va);
9942 if (unwire_pde != NULL) {
9944 pmap_pti_wire_pte(pde);
9947 m = pmap_pti_alloc_page();
9949 pmap_pti_free_page(m);
9950 MPASS((*pde & X86_PG_PS) == 0);
9951 mphys = *pde & ~(PAGE_MASK | pg_nx);
9953 mphys = VM_PAGE_TO_PHYS(m);
9954 *pde = mphys | X86_PG_RW | X86_PG_V;
9955 if (unwire_pde != NULL)
9956 *unwire_pde = false;
9959 MPASS((*pde & X86_PG_PS) == 0);
9960 mphys = *pde & ~(PAGE_MASK | pg_nx);
9963 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9964 pte += pmap_pte_index(va);
9970 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9974 pt_entry_t *pte, ptev;
9977 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9979 sva = trunc_page(sva);
9980 MPASS(sva > VM_MAXUSER_ADDRESS);
9981 eva = round_page(eva);
9983 for (; sva < eva; sva += PAGE_SIZE) {
9984 pte = pmap_pti_pte(sva, &unwire_pde);
9985 pa = pmap_kextract(sva);
9986 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9987 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9988 VM_MEMATTR_DEFAULT, FALSE);
9990 pte_store(pte, ptev);
9991 pmap_pti_wire_pte(pte);
9993 KASSERT(!pti_finalized,
9994 ("pti overlap after fin %#lx %#lx %#lx",
9996 KASSERT(*pte == ptev,
9997 ("pti non-identical pte after fin %#lx %#lx %#lx",
10001 pde = pmap_pti_pde(sva);
10002 pmap_pti_unwire_pde(pde, true);
10008 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10013 VM_OBJECT_WLOCK(pti_obj);
10014 pmap_pti_add_kva_locked(sva, eva, exec);
10015 VM_OBJECT_WUNLOCK(pti_obj);
10019 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10026 sva = rounddown2(sva, PAGE_SIZE);
10027 MPASS(sva > VM_MAXUSER_ADDRESS);
10028 eva = roundup2(eva, PAGE_SIZE);
10030 VM_OBJECT_WLOCK(pti_obj);
10031 for (va = sva; va < eva; va += PAGE_SIZE) {
10032 pte = pmap_pti_pte(va, NULL);
10033 KASSERT((*pte & X86_PG_V) != 0,
10034 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10035 (u_long)pte, *pte));
10037 pmap_pti_unwire_pte(pte, va);
10039 pmap_invalidate_range(kernel_pmap, sva, eva);
10040 VM_OBJECT_WUNLOCK(pti_obj);
10044 pkru_dup_range(void *ctx __unused, void *data)
10046 struct pmap_pkru_range *node, *new_node;
10048 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10049 if (new_node == NULL)
10052 memcpy(new_node, node, sizeof(*node));
10057 pkru_free_range(void *ctx __unused, void *node)
10060 uma_zfree(pmap_pkru_ranges_zone, node);
10064 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10067 struct pmap_pkru_range *ppr;
10070 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10071 MPASS(pmap->pm_type == PT_X86);
10072 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10073 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10074 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10076 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10079 ppr->pkru_keyidx = keyidx;
10080 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10081 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10083 uma_zfree(pmap_pkru_ranges_zone, ppr);
10088 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10091 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10092 MPASS(pmap->pm_type == PT_X86);
10093 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10094 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10098 pmap_pkru_deassign_all(pmap_t pmap)
10101 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10102 if (pmap->pm_type == PT_X86 &&
10103 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10104 rangeset_remove_all(&pmap->pm_pkru);
10108 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10110 struct pmap_pkru_range *ppr, *prev_ppr;
10113 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10114 if (pmap->pm_type != PT_X86 ||
10115 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10116 sva >= VM_MAXUSER_ADDRESS)
10118 MPASS(eva <= VM_MAXUSER_ADDRESS);
10119 for (va = sva, prev_ppr = NULL; va < eva;) {
10120 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10121 if ((ppr == NULL) ^ (prev_ppr == NULL))
10127 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10129 va = ppr->pkru_rs_el.re_end;
10135 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10137 struct pmap_pkru_range *ppr;
10139 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10140 if (pmap->pm_type != PT_X86 ||
10141 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10142 va >= VM_MAXUSER_ADDRESS)
10144 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10146 return (X86_PG_PKU(ppr->pkru_keyidx));
10151 pred_pkru_on_remove(void *ctx __unused, void *r)
10153 struct pmap_pkru_range *ppr;
10156 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10160 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10163 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10164 if (pmap->pm_type == PT_X86 &&
10165 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10166 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10167 pred_pkru_on_remove);
10172 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10175 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10176 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10177 MPASS(dst_pmap->pm_type == PT_X86);
10178 MPASS(src_pmap->pm_type == PT_X86);
10179 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10180 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10182 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10186 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10189 pml4_entry_t *pml4e;
10191 pd_entry_t newpde, ptpaddr, *pde;
10192 pt_entry_t newpte, *ptep, pte;
10193 vm_offset_t va, va_next;
10196 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10197 MPASS(pmap->pm_type == PT_X86);
10198 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10200 for (changed = false, va = sva; va < eva; va = va_next) {
10201 pml4e = pmap_pml4e(pmap, va);
10202 if ((*pml4e & X86_PG_V) == 0) {
10203 va_next = (va + NBPML4) & ~PML4MASK;
10209 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10210 if ((*pdpe & X86_PG_V) == 0) {
10211 va_next = (va + NBPDP) & ~PDPMASK;
10217 va_next = (va + NBPDR) & ~PDRMASK;
10221 pde = pmap_pdpe_to_pde(pdpe, va);
10226 MPASS((ptpaddr & X86_PG_V) != 0);
10227 if ((ptpaddr & PG_PS) != 0) {
10228 if (va + NBPDR == va_next && eva >= va_next) {
10229 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10230 X86_PG_PKU(keyidx);
10231 if (newpde != ptpaddr) {
10236 } else if (!pmap_demote_pde(pmap, pde, va)) {
10244 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10245 ptep++, va += PAGE_SIZE) {
10247 if ((pte & X86_PG_V) == 0)
10249 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10250 if (newpte != pte) {
10257 pmap_invalidate_range(pmap, sva, eva);
10261 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10262 u_int keyidx, int flags)
10265 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10266 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10268 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10270 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10276 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10281 sva = trunc_page(sva);
10282 eva = round_page(eva);
10283 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10288 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10290 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10292 if (error != ENOMEM)
10300 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10304 sva = trunc_page(sva);
10305 eva = round_page(eva);
10306 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10311 error = pmap_pkru_deassign(pmap, sva, eva);
10313 pmap_pkru_update_range(pmap, sva, eva, 0);
10315 if (error != ENOMEM)
10323 * Track a range of the kernel's virtual address space that is contiguous
10324 * in various mapping attributes.
10326 struct pmap_kernel_map_range {
10335 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10341 if (eva <= range->sva)
10344 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10345 for (i = 0; i < PAT_INDEX_SIZE; i++)
10346 if (pat_index[i] == pat_idx)
10350 case PAT_WRITE_BACK:
10353 case PAT_WRITE_THROUGH:
10356 case PAT_UNCACHEABLE:
10362 case PAT_WRITE_PROTECTED:
10365 case PAT_WRITE_COMBINING:
10369 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10370 __func__, pat_idx, range->sva, eva);
10375 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10377 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10378 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10379 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10380 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10381 mode, range->pdpes, range->pdes, range->ptes);
10383 /* Reset to sentinel value. */
10384 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10388 * Determine whether the attributes specified by a page table entry match those
10389 * being tracked by the current range. This is not quite as simple as a direct
10390 * flag comparison since some PAT modes have multiple representations.
10393 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10395 pt_entry_t diff, mask;
10397 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10398 diff = (range->attrs ^ attrs) & mask;
10401 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10402 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10403 pmap_pat_index(kernel_pmap, attrs, true))
10409 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10413 memset(range, 0, sizeof(*range));
10415 range->attrs = attrs;
10419 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10420 * those of the current run, dump the address range and its attributes, and
10424 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10425 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10430 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10432 attrs |= pdpe & pg_nx;
10433 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10434 if ((pdpe & PG_PS) != 0) {
10435 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10436 } else if (pde != 0) {
10437 attrs |= pde & pg_nx;
10438 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10440 if ((pde & PG_PS) != 0) {
10441 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10442 } else if (pte != 0) {
10443 attrs |= pte & pg_nx;
10444 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10445 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10447 /* Canonicalize by always using the PDE PAT bit. */
10448 if ((attrs & X86_PG_PTE_PAT) != 0)
10449 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10452 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10453 sysctl_kmaps_dump(sb, range, va);
10454 sysctl_kmaps_reinit(range, va, attrs);
10459 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10461 struct pmap_kernel_map_range range;
10462 struct sbuf sbuf, *sb;
10463 pml4_entry_t pml4e;
10464 pdp_entry_t *pdp, pdpe;
10465 pd_entry_t *pd, pde;
10466 pt_entry_t *pt, pte;
10469 int error, i, j, k, l;
10471 error = sysctl_wire_old_buffer(req, 0);
10475 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10477 /* Sentinel value. */
10478 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10481 * Iterate over the kernel page tables without holding the kernel pmap
10482 * lock. Outside of the large map, kernel page table pages are never
10483 * freed, so at worst we will observe inconsistencies in the output.
10484 * Within the large map, ensure that PDP and PD page addresses are
10485 * valid before descending.
10487 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10490 sbuf_printf(sb, "\nRecursive map:\n");
10493 sbuf_printf(sb, "\nDirect map:\n");
10496 sbuf_printf(sb, "\nKernel map:\n");
10499 sbuf_printf(sb, "\nLarge map:\n");
10503 /* Convert to canonical form. */
10504 if (sva == 1ul << 47)
10508 pml4e = kernel_pmap->pm_pml4[i];
10509 if ((pml4e & X86_PG_V) == 0) {
10510 sva = rounddown2(sva, NBPML4);
10511 sysctl_kmaps_dump(sb, &range, sva);
10515 pa = pml4e & PG_FRAME;
10516 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10518 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10520 if ((pdpe & X86_PG_V) == 0) {
10521 sva = rounddown2(sva, NBPDP);
10522 sysctl_kmaps_dump(sb, &range, sva);
10526 pa = pdpe & PG_FRAME;
10527 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10528 vm_phys_paddr_to_vm_page(pa) == NULL)
10530 if ((pdpe & PG_PS) != 0) {
10531 sva = rounddown2(sva, NBPDP);
10532 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10538 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10540 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10542 if ((pde & X86_PG_V) == 0) {
10543 sva = rounddown2(sva, NBPDR);
10544 sysctl_kmaps_dump(sb, &range, sva);
10548 pa = pde & PG_FRAME;
10549 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10550 vm_phys_paddr_to_vm_page(pa) == NULL)
10552 if ((pde & PG_PS) != 0) {
10553 sva = rounddown2(sva, NBPDR);
10554 sysctl_kmaps_check(sb, &range, sva,
10555 pml4e, pdpe, pde, 0);
10560 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10562 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10563 sva += PAGE_SIZE) {
10565 if ((pte & X86_PG_V) == 0) {
10566 sysctl_kmaps_dump(sb, &range,
10570 sysctl_kmaps_check(sb, &range, sva,
10571 pml4e, pdpe, pde, pte);
10578 error = sbuf_finish(sb);
10582 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10583 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10584 NULL, 0, sysctl_kmaps, "A",
10585 "Dump kernel address layout");
10588 DB_SHOW_COMMAND(pte, pmap_print_pte)
10591 pml4_entry_t *pml4;
10594 pt_entry_t *pte, PG_V;
10598 db_printf("show pte addr\n");
10601 va = (vm_offset_t)addr;
10603 if (kdb_thread != NULL)
10604 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10606 pmap = PCPU_GET(curpmap);
10608 PG_V = pmap_valid_bit(pmap);
10609 pml4 = pmap_pml4e(pmap, va);
10610 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10611 if ((*pml4 & PG_V) == 0) {
10615 pdp = pmap_pml4e_to_pdpe(pml4, va);
10616 db_printf(" pdpe 0x%016lx", *pdp);
10617 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10621 pde = pmap_pdpe_to_pde(pdp, va);
10622 db_printf(" pde 0x%016lx", *pde);
10623 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10627 pte = pmap_pde_to_pte(pde, va);
10628 db_printf(" pte 0x%016lx\n", *pte);
10631 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10636 a = (vm_paddr_t)addr;
10637 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10639 db_printf("show phys2dmap addr\n");