2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2018 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
126 #include <sys/turnstile.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/intr_machdep.h>
148 #include <x86/apicvar.h>
149 #include <machine/cpu.h>
150 #include <machine/cputypes.h>
151 #include <machine/md_var.h>
152 #include <machine/pcb.h>
153 #include <machine/specialreg.h>
155 #include <machine/smp.h>
157 #include <machine/tss.h>
159 static __inline boolean_t
160 pmap_type_guest(pmap_t pmap)
163 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
166 static __inline boolean_t
167 pmap_emulate_ad_bits(pmap_t pmap)
170 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
173 static __inline pt_entry_t
174 pmap_valid_bit(pmap_t pmap)
178 switch (pmap->pm_type) {
184 if (pmap_emulate_ad_bits(pmap))
185 mask = EPT_PG_EMUL_V;
190 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
196 static __inline pt_entry_t
197 pmap_rw_bit(pmap_t pmap)
201 switch (pmap->pm_type) {
207 if (pmap_emulate_ad_bits(pmap))
208 mask = EPT_PG_EMUL_RW;
213 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
219 static pt_entry_t pg_g;
221 static __inline pt_entry_t
222 pmap_global_bit(pmap_t pmap)
226 switch (pmap->pm_type) {
235 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
241 static __inline pt_entry_t
242 pmap_accessed_bit(pmap_t pmap)
246 switch (pmap->pm_type) {
252 if (pmap_emulate_ad_bits(pmap))
258 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
264 static __inline pt_entry_t
265 pmap_modified_bit(pmap_t pmap)
269 switch (pmap->pm_type) {
275 if (pmap_emulate_ad_bits(pmap))
281 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
287 #if !defined(DIAGNOSTIC)
288 #ifdef __GNUC_GNU_INLINE__
289 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
291 #define PMAP_INLINE extern inline
298 #define PV_STAT(x) do { x ; } while (0)
300 #define PV_STAT(x) do { } while (0)
303 #define pa_index(pa) ((pa) >> PDRSHIFT)
304 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
306 #define NPV_LIST_LOCKS MAXCPU
308 #define PHYS_TO_PV_LIST_LOCK(pa) \
309 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
311 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
312 struct rwlock **_lockp = (lockp); \
313 struct rwlock *_new_lock; \
315 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
316 if (_new_lock != *_lockp) { \
317 if (*_lockp != NULL) \
318 rw_wunlock(*_lockp); \
319 *_lockp = _new_lock; \
324 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
325 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
327 #define RELEASE_PV_LIST_LOCK(lockp) do { \
328 struct rwlock **_lockp = (lockp); \
330 if (*_lockp != NULL) { \
331 rw_wunlock(*_lockp); \
336 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
337 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
339 struct pmap kernel_pmap_store;
341 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
342 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
345 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
346 "Number of kernel page table pages allocated on bootup");
349 vm_paddr_t dmaplimit;
350 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
353 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
355 static int pat_works = 1;
356 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
357 "Is page attribute table fully functional?");
359 static int pg_ps_enabled = 1;
360 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
361 &pg_ps_enabled, 0, "Are large page mappings enabled?");
363 #define PAT_INDEX_SIZE 8
364 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
366 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
367 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
368 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
369 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
371 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
372 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
373 static int ndmpdpphys; /* number of DMPDPphys pages */
375 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
378 * pmap_mapdev support pre initialization (i.e. console)
380 #define PMAP_PREINIT_MAPPING_COUNT 8
381 static struct pmap_preinit_mapping {
386 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
387 static int pmap_initialized;
390 * Data for the pv entry allocation mechanism.
391 * Updates to pv_invl_gen are protected by the pv_list_locks[]
392 * elements, but reads are not.
394 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
395 static struct mtx __exclusive_cache_line pv_chunks_mutex;
396 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
397 static u_long pv_invl_gen[NPV_LIST_LOCKS];
398 static struct md_page *pv_table;
399 static struct md_page pv_dummy;
402 * All those kernel PT submaps that BSD is so fond of
404 pt_entry_t *CMAP1 = NULL;
406 static vm_offset_t qframe = 0;
407 static struct mtx qframe_mtx;
409 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
411 int pmap_pcid_enabled = 1;
412 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
413 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
414 int invpcid_works = 0;
415 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
416 "Is the invpcid instruction available ?");
418 int __read_frequently pti = 0;
419 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
421 "Page Table Isolation enabled");
422 static vm_object_t pti_obj;
423 static pml4_entry_t *pti_pml4;
424 static vm_pindex_t pti_pg_idx;
425 static bool pti_finalized;
428 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
435 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
437 return (sysctl_handle_64(oidp, &res, 0, req));
439 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
440 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
441 "Count of saved TLB context on switch");
443 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
444 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
445 static struct mtx invl_gen_mtx;
446 static u_long pmap_invl_gen = 0;
447 /* Fake lock object to satisfy turnstiles interface. */
448 static struct lock_object invl_gen_ts = {
456 return (curthread->td_md.md_invl_gen.gen == 0);
459 #define PMAP_ASSERT_NOT_IN_DI() \
460 KASSERT(pmap_not_in_di(), ("DI already started"))
463 * Start a new Delayed Invalidation (DI) block of code, executed by
464 * the current thread. Within a DI block, the current thread may
465 * destroy both the page table and PV list entries for a mapping and
466 * then release the corresponding PV list lock before ensuring that
467 * the mapping is flushed from the TLBs of any processors with the
471 pmap_delayed_invl_started(void)
473 struct pmap_invl_gen *invl_gen;
476 invl_gen = &curthread->td_md.md_invl_gen;
477 PMAP_ASSERT_NOT_IN_DI();
478 mtx_lock(&invl_gen_mtx);
479 if (LIST_EMPTY(&pmap_invl_gen_tracker))
480 currgen = pmap_invl_gen;
482 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
483 invl_gen->gen = currgen + 1;
484 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
485 mtx_unlock(&invl_gen_mtx);
489 * Finish the DI block, previously started by the current thread. All
490 * required TLB flushes for the pages marked by
491 * pmap_delayed_invl_page() must be finished before this function is
494 * This function works by bumping the global DI generation number to
495 * the generation number of the current thread's DI, unless there is a
496 * pending DI that started earlier. In the latter case, bumping the
497 * global DI generation number would incorrectly signal that the
498 * earlier DI had finished. Instead, this function bumps the earlier
499 * DI's generation number to match the generation number of the
500 * current thread's DI.
503 pmap_delayed_invl_finished(void)
505 struct pmap_invl_gen *invl_gen, *next;
506 struct turnstile *ts;
508 invl_gen = &curthread->td_md.md_invl_gen;
509 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
510 mtx_lock(&invl_gen_mtx);
511 next = LIST_NEXT(invl_gen, link);
513 turnstile_chain_lock(&invl_gen_ts);
514 ts = turnstile_lookup(&invl_gen_ts);
515 pmap_invl_gen = invl_gen->gen;
517 turnstile_broadcast(ts, TS_SHARED_QUEUE);
518 turnstile_unpend(ts);
520 turnstile_chain_unlock(&invl_gen_ts);
522 next->gen = invl_gen->gen;
524 LIST_REMOVE(invl_gen, link);
525 mtx_unlock(&invl_gen_mtx);
530 static long invl_wait;
531 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
532 "Number of times DI invalidation blocked pmap_remove_all/write");
536 pmap_delayed_invl_genp(vm_page_t m)
539 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
543 * Ensure that all currently executing DI blocks, that need to flush
544 * TLB for the given page m, actually flushed the TLB at the time the
545 * function returned. If the page m has an empty PV list and we call
546 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
547 * valid mapping for the page m in either its page table or TLB.
549 * This function works by blocking until the global DI generation
550 * number catches up with the generation number associated with the
551 * given page m and its PV list. Since this function's callers
552 * typically own an object lock and sometimes own a page lock, it
553 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
557 pmap_delayed_invl_wait(vm_page_t m)
559 struct turnstile *ts;
562 bool accounted = false;
565 m_gen = pmap_delayed_invl_genp(m);
566 while (*m_gen > pmap_invl_gen) {
569 atomic_add_long(&invl_wait, 1);
573 ts = turnstile_trywait(&invl_gen_ts);
574 if (*m_gen > pmap_invl_gen)
575 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
577 turnstile_cancel(ts);
582 * Mark the page m's PV list as participating in the current thread's
583 * DI block. Any threads concurrently using m's PV list to remove or
584 * restrict all mappings to m will wait for the current thread's DI
585 * block to complete before proceeding.
587 * The function works by setting the DI generation number for m's PV
588 * list to at least the DI generation number of the current thread.
589 * This forces a caller of pmap_delayed_invl_wait() to block until
590 * current thread calls pmap_delayed_invl_finished().
593 pmap_delayed_invl_page(vm_page_t m)
597 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
598 gen = curthread->td_md.md_invl_gen.gen;
601 m_gen = pmap_delayed_invl_genp(m);
609 static caddr_t crashdumpmap;
612 * Internal flags for pmap_enter()'s helper functions.
614 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
615 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
617 static void free_pv_chunk(struct pv_chunk *pc);
618 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
619 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
620 static int popcnt_pc_map_pq(uint64_t *map);
621 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
622 static void reserve_pv_entries(pmap_t pmap, int needed,
623 struct rwlock **lockp);
624 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
625 struct rwlock **lockp);
626 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
627 u_int flags, struct rwlock **lockp);
628 #if VM_NRESERVLEVEL > 0
629 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
630 struct rwlock **lockp);
632 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
633 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
636 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
637 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
638 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
639 vm_offset_t va, struct rwlock **lockp);
640 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
642 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
643 vm_prot_t prot, struct rwlock **lockp);
644 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
645 u_int flags, vm_page_t m, struct rwlock **lockp);
646 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
647 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
648 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
649 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
650 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
652 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
653 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
654 #if VM_NRESERVLEVEL > 0
655 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
656 struct rwlock **lockp);
658 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
660 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
661 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
663 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
664 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
665 static void pmap_pti_wire_pte(void *pte);
666 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
667 struct spglist *free, struct rwlock **lockp);
668 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
669 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
670 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
671 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
672 struct spglist *free);
673 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
674 pd_entry_t *pde, struct spglist *free,
675 struct rwlock **lockp);
676 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
677 vm_page_t m, struct rwlock **lockp);
678 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
680 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
682 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
683 struct rwlock **lockp);
684 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
685 struct rwlock **lockp);
686 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
687 struct rwlock **lockp);
689 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
690 struct spglist *free);
691 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
693 /********************/
694 /* Inline functions */
695 /********************/
697 /* Return a non-clipped PD index for a given VA */
698 static __inline vm_pindex_t
699 pmap_pde_pindex(vm_offset_t va)
701 return (va >> PDRSHIFT);
705 /* Return a pointer to the PML4 slot that corresponds to a VA */
706 static __inline pml4_entry_t *
707 pmap_pml4e(pmap_t pmap, vm_offset_t va)
710 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
713 /* Return a pointer to the PDP slot that corresponds to a VA */
714 static __inline pdp_entry_t *
715 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
719 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
720 return (&pdpe[pmap_pdpe_index(va)]);
723 /* Return a pointer to the PDP slot that corresponds to a VA */
724 static __inline pdp_entry_t *
725 pmap_pdpe(pmap_t pmap, vm_offset_t va)
730 PG_V = pmap_valid_bit(pmap);
731 pml4e = pmap_pml4e(pmap, va);
732 if ((*pml4e & PG_V) == 0)
734 return (pmap_pml4e_to_pdpe(pml4e, va));
737 /* Return a pointer to the PD slot that corresponds to a VA */
738 static __inline pd_entry_t *
739 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
743 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
744 return (&pde[pmap_pde_index(va)]);
747 /* Return a pointer to the PD slot that corresponds to a VA */
748 static __inline pd_entry_t *
749 pmap_pde(pmap_t pmap, vm_offset_t va)
754 PG_V = pmap_valid_bit(pmap);
755 pdpe = pmap_pdpe(pmap, va);
756 if (pdpe == NULL || (*pdpe & PG_V) == 0)
758 return (pmap_pdpe_to_pde(pdpe, va));
761 /* Return a pointer to the PT slot that corresponds to a VA */
762 static __inline pt_entry_t *
763 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
767 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
768 return (&pte[pmap_pte_index(va)]);
771 /* Return a pointer to the PT slot that corresponds to a VA */
772 static __inline pt_entry_t *
773 pmap_pte(pmap_t pmap, vm_offset_t va)
778 PG_V = pmap_valid_bit(pmap);
779 pde = pmap_pde(pmap, va);
780 if (pde == NULL || (*pde & PG_V) == 0)
782 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
783 return ((pt_entry_t *)pde);
784 return (pmap_pde_to_pte(pde, va));
788 pmap_resident_count_inc(pmap_t pmap, int count)
791 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
792 pmap->pm_stats.resident_count += count;
796 pmap_resident_count_dec(pmap_t pmap, int count)
799 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
800 KASSERT(pmap->pm_stats.resident_count >= count,
801 ("pmap %p resident count underflow %ld %d", pmap,
802 pmap->pm_stats.resident_count, count));
803 pmap->pm_stats.resident_count -= count;
806 PMAP_INLINE pt_entry_t *
807 vtopte(vm_offset_t va)
809 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
811 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
813 return (PTmap + ((va >> PAGE_SHIFT) & mask));
816 static __inline pd_entry_t *
817 vtopde(vm_offset_t va)
819 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
821 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
823 return (PDmap + ((va >> PDRSHIFT) & mask));
827 allocpages(vm_paddr_t *firstaddr, int n)
832 bzero((void *)ret, n * PAGE_SIZE);
833 *firstaddr += n * PAGE_SIZE;
837 CTASSERT(powerof2(NDMPML4E));
839 /* number of kernel PDP slots */
840 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
843 nkpt_init(vm_paddr_t addr)
850 pt_pages = howmany(addr, 1 << PDRSHIFT);
851 pt_pages += NKPDPE(pt_pages);
854 * Add some slop beyond the bare minimum required for bootstrapping
857 * This is quite important when allocating KVA for kernel modules.
858 * The modules are required to be linked in the negative 2GB of
859 * the address space. If we run out of KVA in this region then
860 * pmap_growkernel() will need to allocate page table pages to map
861 * the entire 512GB of KVA space which is an unnecessary tax on
864 * Secondly, device memory mapped as part of setting up the low-
865 * level console(s) is taken from KVA, starting at virtual_avail.
866 * This is because cninit() is called after pmap_bootstrap() but
867 * before vm_init() and pmap_init(). 20MB for a frame buffer is
870 pt_pages += 32; /* 64MB additional slop. */
876 * Returns the proper write/execute permission for a physical page that is
877 * part of the initial boot allocations.
879 * If the page has kernel text, it is marked as read-only. If the page has
880 * kernel read-only data, it is marked as read-only/not-executable. If the
881 * page has only read-write data, it is marked as read-write/not-executable.
882 * If the page is below/above the kernel range, it is marked as read-write.
884 * This function operates on 2M pages, since we map the kernel space that
887 * Note that this doesn't currently provide any protection for modules.
889 static inline pt_entry_t
890 bootaddr_rwx(vm_paddr_t pa)
894 * Everything in the same 2M page as the start of the kernel
895 * should be static. On the other hand, things in the same 2M
896 * page as the end of the kernel could be read-write/executable,
897 * as the kernel image is not guaranteed to end on a 2M boundary.
899 if (pa < trunc_2mpage(btext - KERNBASE) ||
900 pa >= trunc_2mpage(_end - KERNBASE))
903 * The linker should ensure that the read-only and read-write
904 * portions don't share the same 2M page, so this shouldn't
905 * impact read-only data. However, in any case, any page with
906 * read-write data needs to be read-write.
908 if (pa >= trunc_2mpage(brwsection - KERNBASE))
909 return (X86_PG_RW | pg_nx);
911 * Mark any 2M page containing kernel text as read-only. Mark
912 * other pages with read-only data as read-only and not executable.
913 * (It is likely a small portion of the read-only data section will
914 * be marked as read-only, but executable. This should be acceptable
915 * since the read-only protection will keep the data from changing.)
916 * Note that fixups to the .text section will still work until we
919 if (pa < round_2mpage(etext - KERNBASE))
925 create_pagetables(vm_paddr_t *firstaddr)
927 int i, j, ndm1g, nkpdpe, nkdmpde;
932 uint64_t DMPDkernphys;
934 /* Allocate page table pages for the direct map */
935 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
936 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
938 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
939 if (ndmpdpphys > NDMPML4E) {
941 * Each NDMPML4E allows 512 GB, so limit to that,
942 * and then readjust ndmpdp and ndmpdpphys.
944 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
945 Maxmem = atop(NDMPML4E * NBPML4);
946 ndmpdpphys = NDMPML4E;
947 ndmpdp = NDMPML4E * NPDEPG;
949 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
951 if ((amd_feature & AMDID_PAGE1GB) != 0) {
953 * Calculate the number of 1G pages that will fully fit in
956 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
959 * Allocate 2M pages for the kernel. These will be used in
960 * place of the first one or more 1G pages from ndm1g.
962 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
963 DMPDkernphys = allocpages(firstaddr, nkdmpde);
966 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
967 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
970 KPML4phys = allocpages(firstaddr, 1);
971 KPDPphys = allocpages(firstaddr, NKPML4E);
974 * Allocate the initial number of kernel page table pages required to
975 * bootstrap. We defer this until after all memory-size dependent
976 * allocations are done (e.g. direct map), so that we don't have to
977 * build in too much slop in our estimate.
979 * Note that when NKPML4E > 1, we have an empty page underneath
980 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
981 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
983 nkpt_init(*firstaddr);
984 nkpdpe = NKPDPE(nkpt);
986 KPTphys = allocpages(firstaddr, nkpt);
987 KPDphys = allocpages(firstaddr, nkpdpe);
989 /* Fill in the underlying page table pages */
990 /* XXX not fully used, underneath 2M pages */
991 pt_p = (pt_entry_t *)KPTphys;
992 for (i = 0; ptoa(i) < *firstaddr; i++)
993 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
995 /* Now map the page tables at their location within PTmap */
996 pd_p = (pd_entry_t *)KPDphys;
997 for (i = 0; i < nkpt; i++)
998 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1000 /* Map from zero to end of allocations under 2M pages */
1001 /* This replaces some of the KPTphys entries above */
1002 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1003 /* Preset PG_M and PG_A because demotion expects it. */
1004 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1005 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1008 * Because we map the physical blocks in 2M pages, adjust firstaddr
1009 * to record the physical blocks we've actually mapped into kernel
1010 * virtual address space.
1012 *firstaddr = round_2mpage(*firstaddr);
1014 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1015 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1016 for (i = 0; i < nkpdpe; i++)
1017 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1020 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1021 * the end of physical memory is not aligned to a 1GB page boundary,
1022 * then the residual physical memory is mapped with 2MB pages. Later,
1023 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1024 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1025 * that are partially used.
1027 pd_p = (pd_entry_t *)DMPDphys;
1028 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1029 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1030 /* Preset PG_M and PG_A because demotion expects it. */
1031 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1032 X86_PG_M | X86_PG_A | pg_nx;
1034 pdp_p = (pdp_entry_t *)DMPDPphys;
1035 for (i = 0; i < ndm1g; i++) {
1036 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1037 /* Preset PG_M and PG_A because demotion expects it. */
1038 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1039 X86_PG_M | X86_PG_A | pg_nx;
1041 for (j = 0; i < ndmpdp; i++, j++) {
1042 pdp_p[i] = DMPDphys + ptoa(j);
1043 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1047 * Instead of using a 1G page for the memory containing the kernel,
1048 * use 2M pages with appropriate permissions. (If using 1G pages,
1049 * this will partially overwrite the PDPEs above.)
1052 pd_p = (pd_entry_t *)DMPDkernphys;
1053 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1054 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1055 X86_PG_M | X86_PG_A | pg_nx |
1056 bootaddr_rwx(i << PDRSHIFT);
1057 for (i = 0; i < nkdmpde; i++)
1058 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1062 /* And recursively map PML4 to itself in order to get PTmap */
1063 p4_p = (pml4_entry_t *)KPML4phys;
1064 p4_p[PML4PML4I] = KPML4phys;
1065 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1067 /* Connect the Direct Map slot(s) up to the PML4. */
1068 for (i = 0; i < ndmpdpphys; i++) {
1069 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1070 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1073 /* Connect the KVA slots up to the PML4 */
1074 for (i = 0; i < NKPML4E; i++) {
1075 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1076 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1081 * Bootstrap the system enough to run with virtual memory.
1083 * On amd64 this is called after mapping has already been enabled
1084 * and just syncs the pmap module with what has already been done.
1085 * [We can't call it easily with mapping off since the kernel is not
1086 * mapped with PA == VA, hence we would have to relocate every address
1087 * from the linked base (virtual) address "KERNBASE" to the actual
1088 * (physical) address starting relative to 0]
1091 pmap_bootstrap(vm_paddr_t *firstaddr)
1098 KERNend = *firstaddr;
1104 * Create an initial set of page tables to run the kernel in.
1106 create_pagetables(firstaddr);
1109 * Add a physical memory segment (vm_phys_seg) corresponding to the
1110 * preallocated kernel page table pages so that vm_page structures
1111 * representing these pages will be created. The vm_page structures
1112 * are required for promotion of the corresponding kernel virtual
1113 * addresses to superpage mappings.
1115 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1117 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1119 virtual_end = VM_MAX_KERNEL_ADDRESS;
1123 * Enable PG_G global pages, then switch to the kernel page
1124 * table from the bootstrap page table. After the switch, it
1125 * is possible to enable SMEP and SMAP since PG_U bits are
1131 load_cr3(KPML4phys);
1132 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1134 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1139 * Initialize the kernel pmap (which is statically allocated).
1141 PMAP_LOCK_INIT(kernel_pmap);
1142 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1143 kernel_pmap->pm_cr3 = KPML4phys;
1144 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1145 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1146 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1147 kernel_pmap->pm_flags = pmap_flags;
1150 * Initialize the TLB invalidations generation number lock.
1152 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1155 * Reserve some special page table entries/VA space for temporary
1158 #define SYSMAP(c, p, v, n) \
1159 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1165 * Crashdump maps. The first page is reused as CMAP1 for the
1168 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1169 CADDR1 = crashdumpmap;
1174 * Initialize the PAT MSR.
1175 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1176 * side-effect, invalidates stale PG_G TLB entries that might
1177 * have been created in our pre-boot environment.
1181 /* Initialize TLB Context Id. */
1182 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
1183 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
1184 /* Check for INVPCID support */
1185 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
1187 for (i = 0; i < MAXCPU; i++) {
1188 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1189 kernel_pmap->pm_pcids[i].pm_gen = 1;
1193 * PMAP_PCID_KERN + 1 is used for initialization of
1194 * proc0 pmap. The pmap' pcid state might be used by
1195 * EFIRT entry before first context switch, so it
1196 * needs to be valid.
1198 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1199 PCPU_SET(pcid_gen, 1);
1202 * pcpu area for APs is zeroed during AP startup.
1203 * pc_pcid_next and pc_pcid_gen are initialized by AP
1204 * during pcpu setup.
1206 load_cr4(rcr4() | CR4_PCIDE);
1208 pmap_pcid_enabled = 0;
1213 * Setup the PAT MSR.
1218 int pat_table[PAT_INDEX_SIZE];
1223 /* Bail if this CPU doesn't implement PAT. */
1224 if ((cpu_feature & CPUID_PAT) == 0)
1227 /* Set default PAT index table. */
1228 for (i = 0; i < PAT_INDEX_SIZE; i++)
1230 pat_table[PAT_WRITE_BACK] = 0;
1231 pat_table[PAT_WRITE_THROUGH] = 1;
1232 pat_table[PAT_UNCACHEABLE] = 3;
1233 pat_table[PAT_WRITE_COMBINING] = 3;
1234 pat_table[PAT_WRITE_PROTECTED] = 3;
1235 pat_table[PAT_UNCACHED] = 3;
1237 /* Initialize default PAT entries. */
1238 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1239 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1240 PAT_VALUE(2, PAT_UNCACHED) |
1241 PAT_VALUE(3, PAT_UNCACHEABLE) |
1242 PAT_VALUE(4, PAT_WRITE_BACK) |
1243 PAT_VALUE(5, PAT_WRITE_THROUGH) |
1244 PAT_VALUE(6, PAT_UNCACHED) |
1245 PAT_VALUE(7, PAT_UNCACHEABLE);
1249 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1250 * Program 5 and 6 as WP and WC.
1251 * Leave 4 and 7 as WB and UC.
1253 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
1254 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1255 PAT_VALUE(6, PAT_WRITE_COMBINING);
1256 pat_table[PAT_UNCACHED] = 2;
1257 pat_table[PAT_WRITE_PROTECTED] = 5;
1258 pat_table[PAT_WRITE_COMBINING] = 6;
1261 * Just replace PAT Index 2 with WC instead of UC-.
1263 pat_msr &= ~PAT_MASK(2);
1264 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
1265 pat_table[PAT_WRITE_COMBINING] = 2;
1270 load_cr4(cr4 & ~CR4_PGE);
1272 /* Disable caches (CD = 1, NW = 0). */
1274 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1276 /* Flushes caches and TLBs. */
1280 /* Update PAT and index table. */
1281 wrmsr(MSR_PAT, pat_msr);
1282 for (i = 0; i < PAT_INDEX_SIZE; i++)
1283 pat_index[i] = pat_table[i];
1285 /* Flush caches and TLBs again. */
1289 /* Restore caches and PGE. */
1295 * Initialize a vm_page's machine-dependent fields.
1298 pmap_page_init(vm_page_t m)
1301 TAILQ_INIT(&m->md.pv_list);
1302 m->md.pat_mode = PAT_WRITE_BACK;
1306 * Initialize the pmap module.
1307 * Called by vm_init, to initialize any structures that the pmap
1308 * system needs to map virtual memory.
1313 struct pmap_preinit_mapping *ppim;
1316 int error, i, pv_npg, ret, skz63;
1318 /* L1TF, reserve page @0 unconditionally */
1319 vm_page_blacklist_add(0, bootverbose);
1321 /* Detect bare-metal Skylake Server and Skylake-X. */
1322 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1323 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1325 * Skylake-X errata SKZ63. Processor May Hang When
1326 * Executing Code In an HLE Transaction Region between
1327 * 40000000H and 403FFFFFH.
1329 * Mark the pages in the range as preallocated. It
1330 * seems to be impossible to distinguish between
1331 * Skylake Server and Skylake X.
1334 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1337 printf("SKZ63: skipping 4M RAM starting "
1338 "at physical 1G\n");
1339 for (i = 0; i < atop(0x400000); i++) {
1340 ret = vm_page_blacklist_add(0x40000000 +
1342 if (!ret && bootverbose)
1343 printf("page at %#lx already used\n",
1344 0x40000000 + ptoa(i));
1350 * Initialize the vm page array entries for the kernel pmap's
1353 PMAP_LOCK(kernel_pmap);
1354 for (i = 0; i < nkpt; i++) {
1355 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1356 KASSERT(mpte >= vm_page_array &&
1357 mpte < &vm_page_array[vm_page_array_size],
1358 ("pmap_init: page table page is out of range"));
1359 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1360 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1361 mpte->wire_count = 1;
1362 if (i << PDRSHIFT < KERNend &&
1363 pmap_insert_pt_page(kernel_pmap, mpte))
1364 panic("pmap_init: pmap_insert_pt_page failed");
1366 PMAP_UNLOCK(kernel_pmap);
1370 * If the kernel is running on a virtual machine, then it must assume
1371 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1372 * be prepared for the hypervisor changing the vendor and family that
1373 * are reported by CPUID. Consequently, the workaround for AMD Family
1374 * 10h Erratum 383 is enabled if the processor's feature set does not
1375 * include at least one feature that is only supported by older Intel
1376 * or newer AMD processors.
1378 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1379 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1380 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1382 workaround_erratum383 = 1;
1385 * Are large page mappings enabled?
1387 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1388 if (pg_ps_enabled) {
1389 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1390 ("pmap_init: can't assign to pagesizes[1]"));
1391 pagesizes[1] = NBPDR;
1395 * Initialize the pv chunk list mutex.
1397 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1400 * Initialize the pool of pv list locks.
1402 for (i = 0; i < NPV_LIST_LOCKS; i++)
1403 rw_init(&pv_list_locks[i], "pmap pv list");
1406 * Calculate the size of the pv head table for superpages.
1408 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1411 * Allocate memory for the pv head table for superpages.
1413 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1415 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1417 for (i = 0; i < pv_npg; i++)
1418 TAILQ_INIT(&pv_table[i].pv_list);
1419 TAILQ_INIT(&pv_dummy.pv_list);
1421 pmap_initialized = 1;
1422 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1423 ppim = pmap_preinit_mapping + i;
1426 /* Make the direct map consistent */
1427 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1428 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1429 ppim->sz, ppim->mode);
1433 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1434 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1437 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1438 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1439 (vmem_addr_t *)&qframe);
1441 panic("qframe allocation failed");
1444 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1445 "2MB page mapping counters");
1447 static u_long pmap_pde_demotions;
1448 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1449 &pmap_pde_demotions, 0, "2MB page demotions");
1451 static u_long pmap_pde_mappings;
1452 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1453 &pmap_pde_mappings, 0, "2MB page mappings");
1455 static u_long pmap_pde_p_failures;
1456 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1457 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1459 static u_long pmap_pde_promotions;
1460 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1461 &pmap_pde_promotions, 0, "2MB page promotions");
1463 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1464 "1GB page mapping counters");
1466 static u_long pmap_pdpe_demotions;
1467 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1468 &pmap_pdpe_demotions, 0, "1GB page demotions");
1470 /***************************************************
1471 * Low level helper routines.....
1472 ***************************************************/
1475 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1477 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1479 switch (pmap->pm_type) {
1482 /* Verify that both PAT bits are not set at the same time */
1483 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1484 ("Invalid PAT bits in entry %#lx", entry));
1486 /* Swap the PAT bits if one of them is set */
1487 if ((entry & x86_pat_bits) != 0)
1488 entry ^= x86_pat_bits;
1492 * Nothing to do - the memory attributes are represented
1493 * the same way for regular pages and superpages.
1497 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1504 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1507 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1508 pat_index[(int)mode] >= 0);
1512 * Determine the appropriate bits to set in a PTE or PDE for a specified
1516 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1518 int cache_bits, pat_flag, pat_idx;
1520 if (!pmap_is_valid_memattr(pmap, mode))
1521 panic("Unknown caching mode %d\n", mode);
1523 switch (pmap->pm_type) {
1526 /* The PAT bit is different for PTE's and PDE's. */
1527 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1529 /* Map the caching mode to a PAT index. */
1530 pat_idx = pat_index[mode];
1532 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1535 cache_bits |= pat_flag;
1537 cache_bits |= PG_NC_PCD;
1539 cache_bits |= PG_NC_PWT;
1543 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1547 panic("unsupported pmap type %d", pmap->pm_type);
1550 return (cache_bits);
1554 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1558 switch (pmap->pm_type) {
1561 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1564 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1567 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1574 pmap_ps_enabled(pmap_t pmap)
1577 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1581 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1584 switch (pmap->pm_type) {
1591 * This is a little bogus since the generation number is
1592 * supposed to be bumped up when a region of the address
1593 * space is invalidated in the page tables.
1595 * In this case the old PDE entry is valid but yet we want
1596 * to make sure that any mappings using the old entry are
1597 * invalidated in the TLB.
1599 * The reason this works as expected is because we rendezvous
1600 * "all" host cpus and force any vcpu context to exit as a
1603 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1606 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1608 pde_store(pde, newpde);
1612 * After changing the page size for the specified virtual address in the page
1613 * table, flush the corresponding entries from the processor's TLB. Only the
1614 * calling processor's TLB is affected.
1616 * The calling thread must be pinned to a processor.
1619 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1623 if (pmap_type_guest(pmap))
1626 KASSERT(pmap->pm_type == PT_X86,
1627 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1629 PG_G = pmap_global_bit(pmap);
1631 if ((newpde & PG_PS) == 0)
1632 /* Demotion: flush a specific 2MB page mapping. */
1634 else if ((newpde & PG_G) == 0)
1636 * Promotion: flush every 4KB page mapping from the TLB
1637 * because there are too many to flush individually.
1642 * Promotion: flush every 4KB page mapping from the TLB,
1643 * including any global (PG_G) mappings.
1651 * For SMP, these functions have to use the IPI mechanism for coherence.
1653 * N.B.: Before calling any of the following TLB invalidation functions,
1654 * the calling processor must ensure that all stores updating a non-
1655 * kernel page table are globally performed. Otherwise, another
1656 * processor could cache an old, pre-update entry without being
1657 * invalidated. This can happen one of two ways: (1) The pmap becomes
1658 * active on another processor after its pm_active field is checked by
1659 * one of the following functions but before a store updating the page
1660 * table is globally performed. (2) The pmap becomes active on another
1661 * processor before its pm_active field is checked but due to
1662 * speculative loads one of the following functions stills reads the
1663 * pmap as inactive on the other processor.
1665 * The kernel page table is exempt because its pm_active field is
1666 * immutable. The kernel page table is always active on every
1671 * Interrupt the cpus that are executing in the guest context.
1672 * This will force the vcpu to exit and the cached EPT mappings
1673 * will be invalidated by the host before the next vmresume.
1675 static __inline void
1676 pmap_invalidate_ept(pmap_t pmap)
1681 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1682 ("pmap_invalidate_ept: absurd pm_active"));
1685 * The TLB mappings associated with a vcpu context are not
1686 * flushed each time a different vcpu is chosen to execute.
1688 * This is in contrast with a process's vtop mappings that
1689 * are flushed from the TLB on each context switch.
1691 * Therefore we need to do more than just a TLB shootdown on
1692 * the active cpus in 'pmap->pm_active'. To do this we keep
1693 * track of the number of invalidations performed on this pmap.
1695 * Each vcpu keeps a cache of this counter and compares it
1696 * just before a vmresume. If the counter is out-of-date an
1697 * invept will be done to flush stale mappings from the TLB.
1699 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1702 * Force the vcpu to exit and trap back into the hypervisor.
1704 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1705 ipi_selected(pmap->pm_active, ipinum);
1710 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1713 struct invpcid_descr d;
1714 uint64_t kcr3, ucr3;
1718 if (pmap_type_guest(pmap)) {
1719 pmap_invalidate_ept(pmap);
1723 KASSERT(pmap->pm_type == PT_X86,
1724 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1727 if (pmap == kernel_pmap) {
1731 cpuid = PCPU_GET(cpuid);
1732 if (pmap == PCPU_GET(curpmap)) {
1734 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1736 * Disable context switching. pm_pcid
1737 * is recalculated on switch, which
1738 * might make us use wrong pcid below.
1741 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1743 if (invpcid_works) {
1744 d.pcid = pcid | PMAP_PCID_USER_PT;
1747 invpcid(&d, INVPCID_ADDR);
1749 kcr3 = pmap->pm_cr3 | pcid |
1751 ucr3 = pmap->pm_ucr3 | pcid |
1752 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1753 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1757 } else if (pmap_pcid_enabled)
1758 pmap->pm_pcids[cpuid].pm_gen = 0;
1759 if (pmap_pcid_enabled) {
1762 pmap->pm_pcids[i].pm_gen = 0;
1766 * The fence is between stores to pm_gen and the read of
1767 * the pm_active mask. We need to ensure that it is
1768 * impossible for us to miss the bit update in pm_active
1769 * and simultaneously observe a non-zero pm_gen in
1770 * pmap_activate_sw(), otherwise TLB update is missed.
1771 * Without the fence, IA32 allows such an outcome.
1772 * Note that pm_active is updated by a locked operation,
1773 * which provides the reciprocal fence.
1775 atomic_thread_fence_seq_cst();
1777 mask = &pmap->pm_active;
1779 smp_masked_invlpg(*mask, va, pmap);
1783 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1784 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1787 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1790 struct invpcid_descr d;
1792 uint64_t kcr3, ucr3;
1796 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1797 pmap_invalidate_all(pmap);
1801 if (pmap_type_guest(pmap)) {
1802 pmap_invalidate_ept(pmap);
1806 KASSERT(pmap->pm_type == PT_X86,
1807 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1810 cpuid = PCPU_GET(cpuid);
1811 if (pmap == kernel_pmap) {
1812 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1816 if (pmap == PCPU_GET(curpmap)) {
1817 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1819 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1821 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1822 if (invpcid_works) {
1823 d.pcid = pcid | PMAP_PCID_USER_PT;
1826 for (; d.addr < eva; d.addr +=
1828 invpcid(&d, INVPCID_ADDR);
1830 kcr3 = pmap->pm_cr3 | pcid |
1832 ucr3 = pmap->pm_ucr3 | pcid |
1833 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1834 pmap_pti_pcid_invlrng(ucr3, kcr3, sva,
1839 } else if (pmap_pcid_enabled) {
1840 pmap->pm_pcids[cpuid].pm_gen = 0;
1842 if (pmap_pcid_enabled) {
1845 pmap->pm_pcids[i].pm_gen = 0;
1847 /* See the comment in pmap_invalidate_page(). */
1848 atomic_thread_fence_seq_cst();
1850 mask = &pmap->pm_active;
1852 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1857 pmap_invalidate_all(pmap_t pmap)
1860 struct invpcid_descr d;
1861 uint64_t kcr3, ucr3;
1865 if (pmap_type_guest(pmap)) {
1866 pmap_invalidate_ept(pmap);
1870 KASSERT(pmap->pm_type == PT_X86,
1871 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1874 if (pmap == kernel_pmap) {
1875 if (pmap_pcid_enabled && invpcid_works) {
1876 bzero(&d, sizeof(d));
1877 invpcid(&d, INVPCID_CTXGLOB);
1883 cpuid = PCPU_GET(cpuid);
1884 if (pmap == PCPU_GET(curpmap)) {
1885 if (pmap_pcid_enabled) {
1887 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1888 if (invpcid_works) {
1892 invpcid(&d, INVPCID_CTX);
1893 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1894 d.pcid |= PMAP_PCID_USER_PT;
1895 invpcid(&d, INVPCID_CTX);
1898 kcr3 = pmap->pm_cr3 | pcid;
1899 ucr3 = pmap->pm_ucr3;
1900 if (ucr3 != PMAP_NO_CR3) {
1901 ucr3 |= pcid | PMAP_PCID_USER_PT;
1902 pmap_pti_pcid_invalidate(ucr3,
1912 } else if (pmap_pcid_enabled) {
1913 pmap->pm_pcids[cpuid].pm_gen = 0;
1915 if (pmap_pcid_enabled) {
1918 pmap->pm_pcids[i].pm_gen = 0;
1920 /* See the comment in pmap_invalidate_page(). */
1921 atomic_thread_fence_seq_cst();
1923 mask = &pmap->pm_active;
1925 smp_masked_invltlb(*mask, pmap);
1930 pmap_invalidate_cache(void)
1940 cpuset_t invalidate; /* processors that invalidate their TLB */
1945 u_int store; /* processor that updates the PDE */
1949 pmap_update_pde_action(void *arg)
1951 struct pde_action *act = arg;
1953 if (act->store == PCPU_GET(cpuid))
1954 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1958 pmap_update_pde_teardown(void *arg)
1960 struct pde_action *act = arg;
1962 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1963 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1967 * Change the page size for the specified virtual address in a way that
1968 * prevents any possibility of the TLB ever having two entries that map the
1969 * same virtual address using different page sizes. This is the recommended
1970 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1971 * machine check exception for a TLB state that is improperly diagnosed as a
1975 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1977 struct pde_action act;
1978 cpuset_t active, other_cpus;
1982 cpuid = PCPU_GET(cpuid);
1983 other_cpus = all_cpus;
1984 CPU_CLR(cpuid, &other_cpus);
1985 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1988 active = pmap->pm_active;
1990 if (CPU_OVERLAP(&active, &other_cpus)) {
1992 act.invalidate = active;
1996 act.newpde = newpde;
1997 CPU_SET(cpuid, &active);
1998 smp_rendezvous_cpus(active,
1999 smp_no_rendezvous_barrier, pmap_update_pde_action,
2000 pmap_update_pde_teardown, &act);
2002 pmap_update_pde_store(pmap, pde, newpde);
2003 if (CPU_ISSET(cpuid, &active))
2004 pmap_update_pde_invalidate(pmap, va, newpde);
2010 * Normal, non-SMP, invalidation functions.
2013 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2015 struct invpcid_descr d;
2016 uint64_t kcr3, ucr3;
2019 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2023 KASSERT(pmap->pm_type == PT_X86,
2024 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2026 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2028 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2029 pmap->pm_ucr3 != PMAP_NO_CR3) {
2031 pcid = pmap->pm_pcids[0].pm_pcid;
2032 if (invpcid_works) {
2033 d.pcid = pcid | PMAP_PCID_USER_PT;
2036 invpcid(&d, INVPCID_ADDR);
2038 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2039 ucr3 = pmap->pm_ucr3 | pcid |
2040 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2041 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2045 } else if (pmap_pcid_enabled)
2046 pmap->pm_pcids[0].pm_gen = 0;
2050 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2052 struct invpcid_descr d;
2054 uint64_t kcr3, ucr3;
2056 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2060 KASSERT(pmap->pm_type == PT_X86,
2061 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2063 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2064 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2066 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2067 pmap->pm_ucr3 != PMAP_NO_CR3) {
2069 if (invpcid_works) {
2070 d.pcid = pmap->pm_pcids[0].pm_pcid |
2074 for (; d.addr < eva; d.addr += PAGE_SIZE)
2075 invpcid(&d, INVPCID_ADDR);
2077 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2078 pm_pcid | CR3_PCID_SAVE;
2079 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2080 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2081 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2085 } else if (pmap_pcid_enabled) {
2086 pmap->pm_pcids[0].pm_gen = 0;
2091 pmap_invalidate_all(pmap_t pmap)
2093 struct invpcid_descr d;
2094 uint64_t kcr3, ucr3;
2096 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2100 KASSERT(pmap->pm_type == PT_X86,
2101 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2103 if (pmap == kernel_pmap) {
2104 if (pmap_pcid_enabled && invpcid_works) {
2105 bzero(&d, sizeof(d));
2106 invpcid(&d, INVPCID_CTXGLOB);
2110 } else if (pmap == PCPU_GET(curpmap)) {
2111 if (pmap_pcid_enabled) {
2113 if (invpcid_works) {
2114 d.pcid = pmap->pm_pcids[0].pm_pcid;
2117 invpcid(&d, INVPCID_CTX);
2118 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2119 d.pcid |= PMAP_PCID_USER_PT;
2120 invpcid(&d, INVPCID_CTX);
2123 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2124 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2125 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2126 0].pm_pcid | PMAP_PCID_USER_PT;
2127 pmap_pti_pcid_invalidate(ucr3, kcr3);
2135 } else if (pmap_pcid_enabled) {
2136 pmap->pm_pcids[0].pm_gen = 0;
2141 pmap_invalidate_cache(void)
2148 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2151 pmap_update_pde_store(pmap, pde, newpde);
2152 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2153 pmap_update_pde_invalidate(pmap, va, newpde);
2155 pmap->pm_pcids[0].pm_gen = 0;
2160 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2164 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2165 * by a promotion that did not invalidate the 512 4KB page mappings
2166 * that might exist in the TLB. Consequently, at this point, the TLB
2167 * may hold both 4KB and 2MB page mappings for the address range [va,
2168 * va + NBPDR). Therefore, the entire range must be invalidated here.
2169 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2170 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2171 * single INVLPG suffices to invalidate the 2MB page mapping from the
2174 if ((pde & PG_PROMOTED) != 0)
2175 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2177 pmap_invalidate_page(pmap, va);
2180 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2183 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
2187 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2189 KASSERT((sva & PAGE_MASK) == 0,
2190 ("pmap_invalidate_cache_range: sva not page-aligned"));
2191 KASSERT((eva & PAGE_MASK) == 0,
2192 ("pmap_invalidate_cache_range: eva not page-aligned"));
2195 if ((cpu_feature & CPUID_SS) != 0 && !force)
2196 ; /* If "Self Snoop" is supported and allowed, do nothing. */
2197 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
2198 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2200 * XXX: Some CPUs fault, hang, or trash the local APIC
2201 * registers if we use CLFLUSH on the local APIC
2202 * range. The local APIC is always uncached, so we
2203 * don't need to flush for that range anyway.
2205 if (pmap_kextract(sva) == lapic_paddr)
2209 * Otherwise, do per-cache line flush. Use the sfence
2210 * instruction to insure that previous stores are
2211 * included in the write-back. The processor
2212 * propagates flush to other processors in the cache
2216 for (; sva < eva; sva += cpu_clflush_line_size)
2219 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
2220 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2221 if (pmap_kextract(sva) == lapic_paddr)
2224 * Writes are ordered by CLFLUSH on Intel CPUs.
2226 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2228 for (; sva < eva; sva += cpu_clflush_line_size)
2230 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2235 * No targeted cache flush methods are supported by CPU,
2236 * or the supplied range is bigger than 2MB.
2237 * Globally invalidate cache.
2239 pmap_invalidate_cache();
2244 * Remove the specified set of pages from the data and instruction caches.
2246 * In contrast to pmap_invalidate_cache_range(), this function does not
2247 * rely on the CPU's self-snoop feature, because it is intended for use
2248 * when moving pages into a different cache domain.
2251 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2253 vm_offset_t daddr, eva;
2257 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2258 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2259 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2260 pmap_invalidate_cache();
2264 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2266 for (i = 0; i < count; i++) {
2267 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2268 eva = daddr + PAGE_SIZE;
2269 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2278 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2284 * Routine: pmap_extract
2286 * Extract the physical page address associated
2287 * with the given map/virtual_address pair.
2290 pmap_extract(pmap_t pmap, vm_offset_t va)
2294 pt_entry_t *pte, PG_V;
2298 PG_V = pmap_valid_bit(pmap);
2300 pdpe = pmap_pdpe(pmap, va);
2301 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2302 if ((*pdpe & PG_PS) != 0)
2303 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2305 pde = pmap_pdpe_to_pde(pdpe, va);
2306 if ((*pde & PG_V) != 0) {
2307 if ((*pde & PG_PS) != 0) {
2308 pa = (*pde & PG_PS_FRAME) |
2311 pte = pmap_pde_to_pte(pde, va);
2312 pa = (*pte & PG_FRAME) |
2323 * Routine: pmap_extract_and_hold
2325 * Atomically extract and hold the physical page
2326 * with the given pmap and virtual address pair
2327 * if that mapping permits the given protection.
2330 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2332 pd_entry_t pde, *pdep;
2333 pt_entry_t pte, PG_RW, PG_V;
2339 PG_RW = pmap_rw_bit(pmap);
2340 PG_V = pmap_valid_bit(pmap);
2343 pdep = pmap_pde(pmap, va);
2344 if (pdep != NULL && (pde = *pdep)) {
2346 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2347 if (vm_page_pa_tryrelock(pmap, (pde &
2348 PG_PS_FRAME) | (va & PDRMASK), &pa))
2350 m = PHYS_TO_VM_PAGE(pa);
2353 pte = *pmap_pde_to_pte(pdep, va);
2355 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2356 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2359 m = PHYS_TO_VM_PAGE(pa);
2371 pmap_kextract(vm_offset_t va)
2376 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2377 pa = DMAP_TO_PHYS(va);
2381 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2384 * Beware of a concurrent promotion that changes the
2385 * PDE at this point! For example, vtopte() must not
2386 * be used to access the PTE because it would use the
2387 * new PDE. It is, however, safe to use the old PDE
2388 * because the page table page is preserved by the
2391 pa = *pmap_pde_to_pte(&pde, va);
2392 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2398 /***************************************************
2399 * Low level mapping routines.....
2400 ***************************************************/
2403 * Add a wired page to the kva.
2404 * Note: not SMP coherent.
2407 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2412 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2415 static __inline void
2416 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2422 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2423 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2427 * Remove a page from the kernel pagetables.
2428 * Note: not SMP coherent.
2431 pmap_kremove(vm_offset_t va)
2440 * Used to map a range of physical addresses into kernel
2441 * virtual address space.
2443 * The value passed in '*virt' is a suggested virtual address for
2444 * the mapping. Architectures which can support a direct-mapped
2445 * physical to virtual region can return the appropriate address
2446 * within that region, leaving '*virt' unchanged. Other
2447 * architectures should map the pages starting at '*virt' and
2448 * update '*virt' with the first usable address after the mapped
2452 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2454 return PHYS_TO_DMAP(start);
2459 * Add a list of wired pages to the kva
2460 * this routine is only used for temporary
2461 * kernel mappings that do not need to have
2462 * page modification or references recorded.
2463 * Note that old mappings are simply written
2464 * over. The page *must* be wired.
2465 * Note: SMP coherent. Uses a ranged shootdown IPI.
2468 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2470 pt_entry_t *endpte, oldpte, pa, *pte;
2476 endpte = pte + count;
2477 while (pte < endpte) {
2479 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2480 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2481 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2483 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2487 if (__predict_false((oldpte & X86_PG_V) != 0))
2488 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2493 * This routine tears out page mappings from the
2494 * kernel -- it is meant only for temporary mappings.
2495 * Note: SMP coherent. Uses a ranged shootdown IPI.
2498 pmap_qremove(vm_offset_t sva, int count)
2503 while (count-- > 0) {
2504 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2508 pmap_invalidate_range(kernel_pmap, sva, va);
2511 /***************************************************
2512 * Page table page management routines.....
2513 ***************************************************/
2515 * Schedule the specified unused page table page to be freed. Specifically,
2516 * add the page to the specified list of pages that will be released to the
2517 * physical memory manager after the TLB has been updated.
2519 static __inline void
2520 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2521 boolean_t set_PG_ZERO)
2525 m->flags |= PG_ZERO;
2527 m->flags &= ~PG_ZERO;
2528 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2532 * Inserts the specified page table page into the specified pmap's collection
2533 * of idle page table pages. Each of a pmap's page table pages is responsible
2534 * for mapping a distinct range of virtual addresses. The pmap's collection is
2535 * ordered by this virtual address range.
2538 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2541 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2542 return (vm_radix_insert(&pmap->pm_root, mpte));
2546 * Removes the page table page mapping the specified virtual address from the
2547 * specified pmap's collection of idle page table pages, and returns it.
2548 * Otherwise, returns NULL if there is no page table page corresponding to the
2549 * specified virtual address.
2551 static __inline vm_page_t
2552 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2555 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2556 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2560 * Decrements a page table page's wire count, which is used to record the
2561 * number of valid page table entries within the page. If the wire count
2562 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2563 * page table page was unmapped and FALSE otherwise.
2565 static inline boolean_t
2566 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2570 if (m->wire_count == 0) {
2571 _pmap_unwire_ptp(pmap, va, m, free);
2578 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2583 * unmap the page table page
2585 if (m->pindex >= (NUPDE + NUPDPE)) {
2588 pml4 = pmap_pml4e(pmap, va);
2590 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2591 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2594 } else if (m->pindex >= NUPDE) {
2597 pdp = pmap_pdpe(pmap, va);
2602 pd = pmap_pde(pmap, va);
2605 pmap_resident_count_dec(pmap, 1);
2606 if (m->pindex < NUPDE) {
2607 /* We just released a PT, unhold the matching PD */
2610 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2611 pmap_unwire_ptp(pmap, va, pdpg, free);
2613 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2614 /* We just released a PD, unhold the matching PDP */
2617 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2618 pmap_unwire_ptp(pmap, va, pdppg, free);
2622 * Put page on a list so that it is released after
2623 * *ALL* TLB shootdown is done
2625 pmap_add_delayed_free_list(m, free, TRUE);
2629 * After removing a page table entry, this routine is used to
2630 * conditionally free the page, and manage the hold/wire counts.
2633 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2634 struct spglist *free)
2638 if (va >= VM_MAXUSER_ADDRESS)
2640 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2641 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2642 return (pmap_unwire_ptp(pmap, va, mpte, free));
2646 pmap_pinit0(pmap_t pmap)
2650 PMAP_LOCK_INIT(pmap);
2651 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2652 pmap->pm_pml4u = NULL;
2653 pmap->pm_cr3 = KPML4phys;
2654 /* hack to keep pmap_pti_pcid_invalidate() alive */
2655 pmap->pm_ucr3 = PMAP_NO_CR3;
2656 pmap->pm_root.rt_root = 0;
2657 CPU_ZERO(&pmap->pm_active);
2658 TAILQ_INIT(&pmap->pm_pvchunk);
2659 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2660 pmap->pm_flags = pmap_flags;
2662 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
2663 pmap->pm_pcids[i].pm_gen = 1;
2665 pmap_activate_boot(pmap);
2669 pmap_pinit_pml4(vm_page_t pml4pg)
2671 pml4_entry_t *pm_pml4;
2674 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2676 /* Wire in kernel global address entries. */
2677 for (i = 0; i < NKPML4E; i++) {
2678 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2681 for (i = 0; i < ndmpdpphys; i++) {
2682 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2686 /* install self-referential address mapping entry(s) */
2687 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2688 X86_PG_A | X86_PG_M;
2692 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2694 pml4_entry_t *pm_pml4;
2697 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2698 for (i = 0; i < NPML4EPG; i++)
2699 pm_pml4[i] = pti_pml4[i];
2703 * Initialize a preallocated and zeroed pmap structure,
2704 * such as one in a vmspace structure.
2707 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2709 vm_page_t pml4pg, pml4pgu;
2710 vm_paddr_t pml4phys;
2714 * allocate the page directory page
2716 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2717 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2719 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2720 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2722 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2723 pmap->pm_pcids[i].pm_gen = 0;
2725 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2726 pmap->pm_ucr3 = PMAP_NO_CR3;
2727 pmap->pm_pml4u = NULL;
2729 pmap->pm_type = pm_type;
2730 if ((pml4pg->flags & PG_ZERO) == 0)
2731 pagezero(pmap->pm_pml4);
2734 * Do not install the host kernel mappings in the nested page
2735 * tables. These mappings are meaningless in the guest physical
2737 * Install minimal kernel mappings in PTI case.
2739 if (pm_type == PT_X86) {
2740 pmap->pm_cr3 = pml4phys;
2741 pmap_pinit_pml4(pml4pg);
2743 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2744 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2745 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2746 VM_PAGE_TO_PHYS(pml4pgu));
2747 pmap_pinit_pml4_pti(pml4pgu);
2748 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2752 pmap->pm_root.rt_root = 0;
2753 CPU_ZERO(&pmap->pm_active);
2754 TAILQ_INIT(&pmap->pm_pvchunk);
2755 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2756 pmap->pm_flags = flags;
2757 pmap->pm_eptgen = 0;
2763 pmap_pinit(pmap_t pmap)
2766 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2770 * This routine is called if the desired page table page does not exist.
2772 * If page table page allocation fails, this routine may sleep before
2773 * returning NULL. It sleeps only if a lock pointer was given.
2775 * Note: If a page allocation fails at page table level two or three,
2776 * one or two pages may be held during the wait, only to be released
2777 * afterwards. This conservative approach is easily argued to avoid
2781 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2783 vm_page_t m, pdppg, pdpg;
2784 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2786 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2788 PG_A = pmap_accessed_bit(pmap);
2789 PG_M = pmap_modified_bit(pmap);
2790 PG_V = pmap_valid_bit(pmap);
2791 PG_RW = pmap_rw_bit(pmap);
2794 * Allocate a page table page.
2796 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2797 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2798 if (lockp != NULL) {
2799 RELEASE_PV_LIST_LOCK(lockp);
2801 PMAP_ASSERT_NOT_IN_DI();
2807 * Indicate the need to retry. While waiting, the page table
2808 * page may have been allocated.
2812 if ((m->flags & PG_ZERO) == 0)
2816 * Map the pagetable page into the process address space, if
2817 * it isn't already there.
2820 if (ptepindex >= (NUPDE + NUPDPE)) {
2821 pml4_entry_t *pml4, *pml4u;
2822 vm_pindex_t pml4index;
2824 /* Wire up a new PDPE page */
2825 pml4index = ptepindex - (NUPDE + NUPDPE);
2826 pml4 = &pmap->pm_pml4[pml4index];
2827 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2828 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
2830 * PTI: Make all user-space mappings in the
2831 * kernel-mode page table no-execute so that
2832 * we detect any programming errors that leave
2833 * the kernel-mode page table active on return
2836 if (pmap->pm_ucr3 != PMAP_NO_CR3)
2839 pml4u = &pmap->pm_pml4u[pml4index];
2840 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
2844 } else if (ptepindex >= NUPDE) {
2845 vm_pindex_t pml4index;
2846 vm_pindex_t pdpindex;
2850 /* Wire up a new PDE page */
2851 pdpindex = ptepindex - NUPDE;
2852 pml4index = pdpindex >> NPML4EPGSHIFT;
2854 pml4 = &pmap->pm_pml4[pml4index];
2855 if ((*pml4 & PG_V) == 0) {
2856 /* Have to allocate a new pdp, recurse */
2857 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2859 vm_page_unwire_noq(m);
2860 vm_page_free_zero(m);
2864 /* Add reference to pdp page */
2865 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2866 pdppg->wire_count++;
2868 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2870 /* Now find the pdp page */
2871 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2872 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2875 vm_pindex_t pml4index;
2876 vm_pindex_t pdpindex;
2881 /* Wire up a new PTE page */
2882 pdpindex = ptepindex >> NPDPEPGSHIFT;
2883 pml4index = pdpindex >> NPML4EPGSHIFT;
2885 /* First, find the pdp and check that its valid. */
2886 pml4 = &pmap->pm_pml4[pml4index];
2887 if ((*pml4 & PG_V) == 0) {
2888 /* Have to allocate a new pd, recurse */
2889 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2891 vm_page_unwire_noq(m);
2892 vm_page_free_zero(m);
2895 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2896 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2898 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2899 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2900 if ((*pdp & PG_V) == 0) {
2901 /* Have to allocate a new pd, recurse */
2902 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2904 vm_page_unwire_noq(m);
2905 vm_page_free_zero(m);
2909 /* Add reference to the pd page */
2910 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2914 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2916 /* Now we know where the page directory page is */
2917 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2918 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2921 pmap_resident_count_inc(pmap, 1);
2927 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2929 vm_pindex_t pdpindex, ptepindex;
2930 pdp_entry_t *pdpe, PG_V;
2933 PG_V = pmap_valid_bit(pmap);
2936 pdpe = pmap_pdpe(pmap, va);
2937 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2938 /* Add a reference to the pd page. */
2939 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2942 /* Allocate a pd page. */
2943 ptepindex = pmap_pde_pindex(va);
2944 pdpindex = ptepindex >> NPDPEPGSHIFT;
2945 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2946 if (pdpg == NULL && lockp != NULL)
2953 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2955 vm_pindex_t ptepindex;
2956 pd_entry_t *pd, PG_V;
2959 PG_V = pmap_valid_bit(pmap);
2962 * Calculate pagetable page index
2964 ptepindex = pmap_pde_pindex(va);
2967 * Get the page directory entry
2969 pd = pmap_pde(pmap, va);
2972 * This supports switching from a 2MB page to a
2975 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2976 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2978 * Invalidation of the 2MB page mapping may have caused
2979 * the deallocation of the underlying PD page.
2986 * If the page table page is mapped, we just increment the
2987 * hold count, and activate it.
2989 if (pd != NULL && (*pd & PG_V) != 0) {
2990 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2994 * Here if the pte page isn't mapped, or if it has been
2997 m = _pmap_allocpte(pmap, ptepindex, lockp);
2998 if (m == NULL && lockp != NULL)
3005 /***************************************************
3006 * Pmap allocation/deallocation routines.
3007 ***************************************************/
3010 * Release any resources held by the given physical map.
3011 * Called when a pmap initialized by pmap_pinit is being released.
3012 * Should only be called if the map contains no valid mappings.
3015 pmap_release(pmap_t pmap)
3020 KASSERT(pmap->pm_stats.resident_count == 0,
3021 ("pmap_release: pmap resident count %ld != 0",
3022 pmap->pm_stats.resident_count));
3023 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3024 ("pmap_release: pmap has reserved page table page(s)"));
3025 KASSERT(CPU_EMPTY(&pmap->pm_active),
3026 ("releasing active pmap %p", pmap));
3028 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3030 for (i = 0; i < NKPML4E; i++) /* KVA */
3031 pmap->pm_pml4[KPML4BASE + i] = 0;
3032 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3033 pmap->pm_pml4[DMPML4I + i] = 0;
3034 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3036 vm_page_unwire_noq(m);
3037 vm_page_free_zero(m);
3039 if (pmap->pm_pml4u != NULL) {
3040 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3041 vm_page_unwire_noq(m);
3047 kvm_size(SYSCTL_HANDLER_ARGS)
3049 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3051 return sysctl_handle_long(oidp, &ksize, 0, req);
3053 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3054 0, 0, kvm_size, "LU", "Size of KVM");
3057 kvm_free(SYSCTL_HANDLER_ARGS)
3059 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3061 return sysctl_handle_long(oidp, &kfree, 0, req);
3063 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3064 0, 0, kvm_free, "LU", "Amount of KVM free");
3067 * grow the number of kernel page table entries, if needed
3070 pmap_growkernel(vm_offset_t addr)
3074 pd_entry_t *pde, newpdir;
3077 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3080 * Return if "addr" is within the range of kernel page table pages
3081 * that were preallocated during pmap bootstrap. Moreover, leave
3082 * "kernel_vm_end" and the kernel page table as they were.
3084 * The correctness of this action is based on the following
3085 * argument: vm_map_insert() allocates contiguous ranges of the
3086 * kernel virtual address space. It calls this function if a range
3087 * ends after "kernel_vm_end". If the kernel is mapped between
3088 * "kernel_vm_end" and "addr", then the range cannot begin at
3089 * "kernel_vm_end". In fact, its beginning address cannot be less
3090 * than the kernel. Thus, there is no immediate need to allocate
3091 * any new kernel page table pages between "kernel_vm_end" and
3094 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3097 addr = roundup2(addr, NBPDR);
3098 if (addr - 1 >= kernel_map->max_offset)
3099 addr = kernel_map->max_offset;
3100 while (kernel_vm_end < addr) {
3101 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3102 if ((*pdpe & X86_PG_V) == 0) {
3103 /* We need a new PDP entry */
3104 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3105 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3106 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3108 panic("pmap_growkernel: no memory to grow kernel");
3109 if ((nkpg->flags & PG_ZERO) == 0)
3110 pmap_zero_page(nkpg);
3111 paddr = VM_PAGE_TO_PHYS(nkpg);
3112 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3113 X86_PG_A | X86_PG_M);
3114 continue; /* try again */
3116 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3117 if ((*pde & X86_PG_V) != 0) {
3118 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3119 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
3120 kernel_vm_end = kernel_map->max_offset;
3126 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3127 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3130 panic("pmap_growkernel: no memory to grow kernel");
3131 if ((nkpg->flags & PG_ZERO) == 0)
3132 pmap_zero_page(nkpg);
3133 paddr = VM_PAGE_TO_PHYS(nkpg);
3134 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3135 pde_store(pde, newpdir);
3137 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3138 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
3139 kernel_vm_end = kernel_map->max_offset;
3146 /***************************************************
3147 * page management routines.
3148 ***************************************************/
3150 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3151 CTASSERT(_NPCM == 3);
3152 CTASSERT(_NPCPV == 168);
3154 static __inline struct pv_chunk *
3155 pv_to_chunk(pv_entry_t pv)
3158 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3161 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3163 #define PC_FREE0 0xfffffffffffffffful
3164 #define PC_FREE1 0xfffffffffffffffful
3165 #define PC_FREE2 0x000000fffffffffful
3167 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3170 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3172 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3173 "Current number of pv entry chunks");
3174 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3175 "Current number of pv entry chunks allocated");
3176 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3177 "Current number of pv entry chunks frees");
3178 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3179 "Number of times tried to get a chunk page but failed.");
3181 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3182 static int pv_entry_spare;
3184 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3185 "Current number of pv entry frees");
3186 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3187 "Current number of pv entry allocs");
3188 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3189 "Current number of pv entries");
3190 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3191 "Current number of spare pv entries");
3195 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3200 pmap_invalidate_all(pmap);
3201 if (pmap != locked_pmap)
3204 pmap_delayed_invl_finished();
3208 * We are in a serious low memory condition. Resort to
3209 * drastic measures to free some pages so we can allocate
3210 * another pv entry chunk.
3212 * Returns NULL if PV entries were reclaimed from the specified pmap.
3214 * We do not, however, unmap 2mpages because subsequent accesses will
3215 * allocate per-page pv entries until repromotion occurs, thereby
3216 * exacerbating the shortage of free pv entries.
3219 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3221 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3222 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3223 struct md_page *pvh;
3225 pmap_t next_pmap, pmap;
3226 pt_entry_t *pte, tpte;
3227 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3231 struct spglist free;
3233 int bit, field, freed;
3235 static int active_reclaims = 0;
3237 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3238 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3241 PG_G = PG_A = PG_M = PG_RW = 0;
3243 bzero(&pc_marker_b, sizeof(pc_marker_b));
3244 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3245 pc_marker = (struct pv_chunk *)&pc_marker_b;
3246 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3249 * A delayed invalidation block should already be active if
3250 * pmap_advise() or pmap_remove() called this function by way
3251 * of pmap_demote_pde_locked().
3253 start_di = pmap_not_in_di();
3255 mtx_lock(&pv_chunks_mutex);
3257 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3258 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3259 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3260 SLIST_EMPTY(&free)) {
3261 next_pmap = pc->pc_pmap;
3262 if (next_pmap == NULL) {
3264 * The next chunk is a marker. However, it is
3265 * not our marker, so active_reclaims must be
3266 * > 1. Consequently, the next_chunk code
3267 * will not rotate the pv_chunks list.
3271 mtx_unlock(&pv_chunks_mutex);
3274 * A pv_chunk can only be removed from the pc_lru list
3275 * when both pc_chunks_mutex is owned and the
3276 * corresponding pmap is locked.
3278 if (pmap != next_pmap) {
3279 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3282 /* Avoid deadlock and lock recursion. */
3283 if (pmap > locked_pmap) {
3284 RELEASE_PV_LIST_LOCK(lockp);
3287 pmap_delayed_invl_started();
3288 mtx_lock(&pv_chunks_mutex);
3290 } else if (pmap != locked_pmap) {
3291 if (PMAP_TRYLOCK(pmap)) {
3293 pmap_delayed_invl_started();
3294 mtx_lock(&pv_chunks_mutex);
3297 pmap = NULL; /* pmap is not locked */
3298 mtx_lock(&pv_chunks_mutex);
3299 pc = TAILQ_NEXT(pc_marker, pc_lru);
3301 pc->pc_pmap != next_pmap)
3305 } else if (start_di)
3306 pmap_delayed_invl_started();
3307 PG_G = pmap_global_bit(pmap);
3308 PG_A = pmap_accessed_bit(pmap);
3309 PG_M = pmap_modified_bit(pmap);
3310 PG_RW = pmap_rw_bit(pmap);
3314 * Destroy every non-wired, 4 KB page mapping in the chunk.
3317 for (field = 0; field < _NPCM; field++) {
3318 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3319 inuse != 0; inuse &= ~(1UL << bit)) {
3321 pv = &pc->pc_pventry[field * 64 + bit];
3323 pde = pmap_pde(pmap, va);
3324 if ((*pde & PG_PS) != 0)
3326 pte = pmap_pde_to_pte(pde, va);
3327 if ((*pte & PG_W) != 0)
3329 tpte = pte_load_clear(pte);
3330 if ((tpte & PG_G) != 0)
3331 pmap_invalidate_page(pmap, va);
3332 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3333 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3335 if ((tpte & PG_A) != 0)
3336 vm_page_aflag_set(m, PGA_REFERENCED);
3337 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3338 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3340 if (TAILQ_EMPTY(&m->md.pv_list) &&
3341 (m->flags & PG_FICTITIOUS) == 0) {
3342 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3343 if (TAILQ_EMPTY(&pvh->pv_list)) {
3344 vm_page_aflag_clear(m,
3348 pmap_delayed_invl_page(m);
3349 pc->pc_map[field] |= 1UL << bit;
3350 pmap_unuse_pt(pmap, va, *pde, &free);
3355 mtx_lock(&pv_chunks_mutex);
3358 /* Every freed mapping is for a 4 KB page. */
3359 pmap_resident_count_dec(pmap, freed);
3360 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3361 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3362 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3363 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3364 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3365 pc->pc_map[2] == PC_FREE2) {
3366 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3367 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3368 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3369 /* Entire chunk is free; return it. */
3370 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3371 dump_drop_page(m_pc->phys_addr);
3372 mtx_lock(&pv_chunks_mutex);
3373 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3376 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3377 mtx_lock(&pv_chunks_mutex);
3378 /* One freed pv entry in locked_pmap is sufficient. */
3379 if (pmap == locked_pmap)
3382 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3383 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3384 if (active_reclaims == 1 && pmap != NULL) {
3386 * Rotate the pv chunks list so that we do not
3387 * scan the same pv chunks that could not be
3388 * freed (because they contained a wired
3389 * and/or superpage mapping) on every
3390 * invocation of reclaim_pv_chunk().
3392 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3393 MPASS(pc->pc_pmap != NULL);
3394 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3395 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3399 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3400 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3402 mtx_unlock(&pv_chunks_mutex);
3403 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3404 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3405 m_pc = SLIST_FIRST(&free);
3406 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3407 /* Recycle a freed page table page. */
3408 m_pc->wire_count = 1;
3410 vm_page_free_pages_toq(&free, true);
3415 * free the pv_entry back to the free list
3418 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3420 struct pv_chunk *pc;
3421 int idx, field, bit;
3423 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3424 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3425 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3426 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3427 pc = pv_to_chunk(pv);
3428 idx = pv - &pc->pc_pventry[0];
3431 pc->pc_map[field] |= 1ul << bit;
3432 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3433 pc->pc_map[2] != PC_FREE2) {
3434 /* 98% of the time, pc is already at the head of the list. */
3435 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3436 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3437 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3441 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3446 free_pv_chunk(struct pv_chunk *pc)
3450 mtx_lock(&pv_chunks_mutex);
3451 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3452 mtx_unlock(&pv_chunks_mutex);
3453 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3454 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3455 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3456 /* entire chunk is free, return it */
3457 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3458 dump_drop_page(m->phys_addr);
3459 vm_page_unwire(m, PQ_NONE);
3464 * Returns a new PV entry, allocating a new PV chunk from the system when
3465 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3466 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3469 * The given PV list lock may be released.
3472 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3476 struct pv_chunk *pc;
3479 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3480 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3482 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3484 for (field = 0; field < _NPCM; field++) {
3485 if (pc->pc_map[field]) {
3486 bit = bsfq(pc->pc_map[field]);
3490 if (field < _NPCM) {
3491 pv = &pc->pc_pventry[field * 64 + bit];
3492 pc->pc_map[field] &= ~(1ul << bit);
3493 /* If this was the last item, move it to tail */
3494 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3495 pc->pc_map[2] == 0) {
3496 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3497 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3500 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3501 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3505 /* No free items, allocate another chunk */
3506 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3509 if (lockp == NULL) {
3510 PV_STAT(pc_chunk_tryfail++);
3513 m = reclaim_pv_chunk(pmap, lockp);
3517 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3518 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3519 dump_add_page(m->phys_addr);
3520 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3522 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3523 pc->pc_map[1] = PC_FREE1;
3524 pc->pc_map[2] = PC_FREE2;
3525 mtx_lock(&pv_chunks_mutex);
3526 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3527 mtx_unlock(&pv_chunks_mutex);
3528 pv = &pc->pc_pventry[0];
3529 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3530 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3531 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3536 * Returns the number of one bits within the given PV chunk map.
3538 * The erratas for Intel processors state that "POPCNT Instruction May
3539 * Take Longer to Execute Than Expected". It is believed that the
3540 * issue is the spurious dependency on the destination register.
3541 * Provide a hint to the register rename logic that the destination
3542 * value is overwritten, by clearing it, as suggested in the
3543 * optimization manual. It should be cheap for unaffected processors
3546 * Reference numbers for erratas are
3547 * 4th Gen Core: HSD146
3548 * 5th Gen Core: BDM85
3549 * 6th Gen Core: SKL029
3552 popcnt_pc_map_pq(uint64_t *map)
3556 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3557 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3558 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3559 : "=&r" (result), "=&r" (tmp)
3560 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3565 * Ensure that the number of spare PV entries in the specified pmap meets or
3566 * exceeds the given count, "needed".
3568 * The given PV list lock may be released.
3571 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3573 struct pch new_tail;
3574 struct pv_chunk *pc;
3579 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3580 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3583 * Newly allocated PV chunks must be stored in a private list until
3584 * the required number of PV chunks have been allocated. Otherwise,
3585 * reclaim_pv_chunk() could recycle one of these chunks. In
3586 * contrast, these chunks must be added to the pmap upon allocation.
3588 TAILQ_INIT(&new_tail);
3591 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3593 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3594 bit_count((bitstr_t *)pc->pc_map, 0,
3595 sizeof(pc->pc_map) * NBBY, &free);
3598 free = popcnt_pc_map_pq(pc->pc_map);
3602 if (avail >= needed)
3605 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3606 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3609 m = reclaim_pv_chunk(pmap, lockp);
3614 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3615 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3616 dump_add_page(m->phys_addr);
3617 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3619 pc->pc_map[0] = PC_FREE0;
3620 pc->pc_map[1] = PC_FREE1;
3621 pc->pc_map[2] = PC_FREE2;
3622 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3623 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3624 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3627 * The reclaim might have freed a chunk from the current pmap.
3628 * If that chunk contained available entries, we need to
3629 * re-count the number of available entries.
3634 if (!TAILQ_EMPTY(&new_tail)) {
3635 mtx_lock(&pv_chunks_mutex);
3636 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3637 mtx_unlock(&pv_chunks_mutex);
3642 * First find and then remove the pv entry for the specified pmap and virtual
3643 * address from the specified pv list. Returns the pv entry if found and NULL
3644 * otherwise. This operation can be performed on pv lists for either 4KB or
3645 * 2MB page mappings.
3647 static __inline pv_entry_t
3648 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3652 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3653 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3654 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3663 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3664 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3665 * entries for each of the 4KB page mappings.
3668 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3669 struct rwlock **lockp)
3671 struct md_page *pvh;
3672 struct pv_chunk *pc;
3674 vm_offset_t va_last;
3678 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3679 KASSERT((pa & PDRMASK) == 0,
3680 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3681 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3684 * Transfer the 2mpage's pv entry for this mapping to the first
3685 * page's pv list. Once this transfer begins, the pv list lock
3686 * must not be released until the last pv entry is reinstantiated.
3688 pvh = pa_to_pvh(pa);
3689 va = trunc_2mpage(va);
3690 pv = pmap_pvh_remove(pvh, pmap, va);
3691 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3692 m = PHYS_TO_VM_PAGE(pa);
3693 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3695 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3696 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3697 va_last = va + NBPDR - PAGE_SIZE;
3699 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3700 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3701 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3702 for (field = 0; field < _NPCM; field++) {
3703 while (pc->pc_map[field]) {
3704 bit = bsfq(pc->pc_map[field]);
3705 pc->pc_map[field] &= ~(1ul << bit);
3706 pv = &pc->pc_pventry[field * 64 + bit];
3710 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3711 ("pmap_pv_demote_pde: page %p is not managed", m));
3712 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3718 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3719 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3722 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3723 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3724 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3726 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3727 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3730 #if VM_NRESERVLEVEL > 0
3732 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3733 * replace the many pv entries for the 4KB page mappings by a single pv entry
3734 * for the 2MB page mapping.
3737 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3738 struct rwlock **lockp)
3740 struct md_page *pvh;
3742 vm_offset_t va_last;
3745 KASSERT((pa & PDRMASK) == 0,
3746 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3747 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3750 * Transfer the first page's pv entry for this mapping to the 2mpage's
3751 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3752 * a transfer avoids the possibility that get_pv_entry() calls
3753 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3754 * mappings that is being promoted.
3756 m = PHYS_TO_VM_PAGE(pa);
3757 va = trunc_2mpage(va);
3758 pv = pmap_pvh_remove(&m->md, pmap, va);
3759 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3760 pvh = pa_to_pvh(pa);
3761 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3763 /* Free the remaining NPTEPG - 1 pv entries. */
3764 va_last = va + NBPDR - PAGE_SIZE;
3768 pmap_pvh_free(&m->md, pmap, va);
3769 } while (va < va_last);
3771 #endif /* VM_NRESERVLEVEL > 0 */
3774 * First find and then destroy the pv entry for the specified pmap and virtual
3775 * address. This operation can be performed on pv lists for either 4KB or 2MB
3779 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3783 pv = pmap_pvh_remove(pvh, pmap, va);
3784 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3785 free_pv_entry(pmap, pv);
3789 * Conditionally create the PV entry for a 4KB page mapping if the required
3790 * memory can be allocated without resorting to reclamation.
3793 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3794 struct rwlock **lockp)
3798 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3799 /* Pass NULL instead of the lock pointer to disable reclamation. */
3800 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3802 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3803 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3811 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3812 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3813 * false if the PV entry cannot be allocated without resorting to reclamation.
3816 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
3817 struct rwlock **lockp)
3819 struct md_page *pvh;
3823 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3824 /* Pass NULL instead of the lock pointer to disable reclamation. */
3825 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3826 NULL : lockp)) == NULL)
3829 pa = pde & PG_PS_FRAME;
3830 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3831 pvh = pa_to_pvh(pa);
3832 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3838 * Fills a page table page with mappings to consecutive physical pages.
3841 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3845 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3847 newpte += PAGE_SIZE;
3852 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3853 * mapping is invalidated.
3856 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3858 struct rwlock *lock;
3862 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3869 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3870 struct rwlock **lockp)
3872 pd_entry_t newpde, oldpde;
3873 pt_entry_t *firstpte, newpte;
3874 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3877 struct spglist free;
3881 PG_G = pmap_global_bit(pmap);
3882 PG_A = pmap_accessed_bit(pmap);
3883 PG_M = pmap_modified_bit(pmap);
3884 PG_RW = pmap_rw_bit(pmap);
3885 PG_V = pmap_valid_bit(pmap);
3886 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3888 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3890 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3891 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3892 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
3894 KASSERT((oldpde & PG_W) == 0,
3895 ("pmap_demote_pde: page table page for a wired mapping"
3899 * Invalidate the 2MB page mapping and return "failure" if the
3900 * mapping was never accessed or the allocation of the new
3901 * page table page fails. If the 2MB page mapping belongs to
3902 * the direct map region of the kernel's address space, then
3903 * the page allocation request specifies the highest possible
3904 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3905 * normal. Page table pages are preallocated for every other
3906 * part of the kernel address space, so the direct map region
3907 * is the only part of the kernel address space that must be
3910 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3911 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3912 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3913 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3915 sva = trunc_2mpage(va);
3916 pmap_remove_pde(pmap, pde, sva, &free, lockp);
3917 if ((oldpde & PG_G) == 0)
3918 pmap_invalidate_pde_page(pmap, sva, oldpde);
3919 vm_page_free_pages_toq(&free, true);
3920 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3921 " in pmap %p", va, pmap);
3924 if (va < VM_MAXUSER_ADDRESS)
3925 pmap_resident_count_inc(pmap, 1);
3927 mptepa = VM_PAGE_TO_PHYS(mpte);
3928 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3929 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3930 KASSERT((oldpde & PG_A) != 0,
3931 ("pmap_demote_pde: oldpde is missing PG_A"));
3932 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3933 ("pmap_demote_pde: oldpde is missing PG_M"));
3934 newpte = oldpde & ~PG_PS;
3935 newpte = pmap_swap_pat(pmap, newpte);
3938 * If the page table page is new, initialize it.
3940 if (mpte->wire_count == 1) {
3941 mpte->wire_count = NPTEPG;
3942 pmap_fill_ptp(firstpte, newpte);
3944 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3945 ("pmap_demote_pde: firstpte and newpte map different physical"
3949 * If the mapping has changed attributes, update the page table
3952 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3953 pmap_fill_ptp(firstpte, newpte);
3956 * The spare PV entries must be reserved prior to demoting the
3957 * mapping, that is, prior to changing the PDE. Otherwise, the state
3958 * of the PDE and the PV lists will be inconsistent, which can result
3959 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3960 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3961 * PV entry for the 2MB page mapping that is being demoted.
3963 if ((oldpde & PG_MANAGED) != 0)
3964 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3967 * Demote the mapping. This pmap is locked. The old PDE has
3968 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3969 * set. Thus, there is no danger of a race with another
3970 * processor changing the setting of PG_A and/or PG_M between
3971 * the read above and the store below.
3973 if (workaround_erratum383)
3974 pmap_update_pde(pmap, va, pde, newpde);
3976 pde_store(pde, newpde);
3979 * Invalidate a stale recursive mapping of the page table page.
3981 if (va >= VM_MAXUSER_ADDRESS)
3982 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3985 * Demote the PV entry.
3987 if ((oldpde & PG_MANAGED) != 0)
3988 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3990 atomic_add_long(&pmap_pde_demotions, 1);
3991 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3992 " in pmap %p", va, pmap);
3997 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4000 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4006 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4007 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4008 mpte = pmap_remove_pt_page(pmap, va);
4010 panic("pmap_remove_kernel_pde: Missing pt page.");
4012 mptepa = VM_PAGE_TO_PHYS(mpte);
4013 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4016 * Initialize the page table page.
4018 pagezero((void *)PHYS_TO_DMAP(mptepa));
4021 * Demote the mapping.
4023 if (workaround_erratum383)
4024 pmap_update_pde(pmap, va, pde, newpde);
4026 pde_store(pde, newpde);
4029 * Invalidate a stale recursive mapping of the page table page.
4031 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4035 * pmap_remove_pde: do the things to unmap a superpage in a process
4038 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4039 struct spglist *free, struct rwlock **lockp)
4041 struct md_page *pvh;
4043 vm_offset_t eva, va;
4045 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4047 PG_G = pmap_global_bit(pmap);
4048 PG_A = pmap_accessed_bit(pmap);
4049 PG_M = pmap_modified_bit(pmap);
4050 PG_RW = pmap_rw_bit(pmap);
4052 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4053 KASSERT((sva & PDRMASK) == 0,
4054 ("pmap_remove_pde: sva is not 2mpage aligned"));
4055 oldpde = pte_load_clear(pdq);
4057 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4058 if ((oldpde & PG_G) != 0)
4059 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4060 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4061 if (oldpde & PG_MANAGED) {
4062 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4063 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4064 pmap_pvh_free(pvh, pmap, sva);
4066 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4067 va < eva; va += PAGE_SIZE, m++) {
4068 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4071 vm_page_aflag_set(m, PGA_REFERENCED);
4072 if (TAILQ_EMPTY(&m->md.pv_list) &&
4073 TAILQ_EMPTY(&pvh->pv_list))
4074 vm_page_aflag_clear(m, PGA_WRITEABLE);
4075 pmap_delayed_invl_page(m);
4078 if (pmap == kernel_pmap) {
4079 pmap_remove_kernel_pde(pmap, pdq, sva);
4081 mpte = pmap_remove_pt_page(pmap, sva);
4083 pmap_resident_count_dec(pmap, 1);
4084 KASSERT(mpte->wire_count == NPTEPG,
4085 ("pmap_remove_pde: pte page wire count error"));
4086 mpte->wire_count = 0;
4087 pmap_add_delayed_free_list(mpte, free, FALSE);
4090 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4094 * pmap_remove_pte: do the things to unmap a page in a process
4097 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4098 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4100 struct md_page *pvh;
4101 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4104 PG_A = pmap_accessed_bit(pmap);
4105 PG_M = pmap_modified_bit(pmap);
4106 PG_RW = pmap_rw_bit(pmap);
4108 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4109 oldpte = pte_load_clear(ptq);
4111 pmap->pm_stats.wired_count -= 1;
4112 pmap_resident_count_dec(pmap, 1);
4113 if (oldpte & PG_MANAGED) {
4114 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4115 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4118 vm_page_aflag_set(m, PGA_REFERENCED);
4119 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4120 pmap_pvh_free(&m->md, pmap, va);
4121 if (TAILQ_EMPTY(&m->md.pv_list) &&
4122 (m->flags & PG_FICTITIOUS) == 0) {
4123 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4124 if (TAILQ_EMPTY(&pvh->pv_list))
4125 vm_page_aflag_clear(m, PGA_WRITEABLE);
4127 pmap_delayed_invl_page(m);
4129 return (pmap_unuse_pt(pmap, va, ptepde, free));
4133 * Remove a single page from a process address space
4136 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4137 struct spglist *free)
4139 struct rwlock *lock;
4140 pt_entry_t *pte, PG_V;
4142 PG_V = pmap_valid_bit(pmap);
4143 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4144 if ((*pde & PG_V) == 0)
4146 pte = pmap_pde_to_pte(pde, va);
4147 if ((*pte & PG_V) == 0)
4150 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4153 pmap_invalidate_page(pmap, va);
4157 * Removes the specified range of addresses from the page table page.
4160 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4161 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4163 pt_entry_t PG_G, *pte;
4167 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4168 PG_G = pmap_global_bit(pmap);
4171 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4175 pmap_invalidate_range(pmap, va, sva);
4180 if ((*pte & PG_G) == 0)
4184 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4190 pmap_invalidate_range(pmap, va, sva);
4195 * Remove the given range of addresses from the specified map.
4197 * It is assumed that the start and end are properly
4198 * rounded to the page size.
4201 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4203 struct rwlock *lock;
4204 vm_offset_t va_next;
4205 pml4_entry_t *pml4e;
4207 pd_entry_t ptpaddr, *pde;
4208 pt_entry_t PG_G, PG_V;
4209 struct spglist free;
4212 PG_G = pmap_global_bit(pmap);
4213 PG_V = pmap_valid_bit(pmap);
4216 * Perform an unsynchronized read. This is, however, safe.
4218 if (pmap->pm_stats.resident_count == 0)
4224 pmap_delayed_invl_started();
4228 * special handling of removing one page. a very
4229 * common operation and easy to short circuit some
4232 if (sva + PAGE_SIZE == eva) {
4233 pde = pmap_pde(pmap, sva);
4234 if (pde && (*pde & PG_PS) == 0) {
4235 pmap_remove_page(pmap, sva, pde, &free);
4241 for (; sva < eva; sva = va_next) {
4243 if (pmap->pm_stats.resident_count == 0)
4246 pml4e = pmap_pml4e(pmap, sva);
4247 if ((*pml4e & PG_V) == 0) {
4248 va_next = (sva + NBPML4) & ~PML4MASK;
4254 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4255 if ((*pdpe & PG_V) == 0) {
4256 va_next = (sva + NBPDP) & ~PDPMASK;
4263 * Calculate index for next page table.
4265 va_next = (sva + NBPDR) & ~PDRMASK;
4269 pde = pmap_pdpe_to_pde(pdpe, sva);
4273 * Weed out invalid mappings.
4279 * Check for large page.
4281 if ((ptpaddr & PG_PS) != 0) {
4283 * Are we removing the entire large page? If not,
4284 * demote the mapping and fall through.
4286 if (sva + NBPDR == va_next && eva >= va_next) {
4288 * The TLB entry for a PG_G mapping is
4289 * invalidated by pmap_remove_pde().
4291 if ((ptpaddr & PG_G) == 0)
4293 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4295 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4297 /* The large page mapping was destroyed. */
4304 * Limit our scan to either the end of the va represented
4305 * by the current page table page, or to the end of the
4306 * range being removed.
4311 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4318 pmap_invalidate_all(pmap);
4320 pmap_delayed_invl_finished();
4321 vm_page_free_pages_toq(&free, true);
4325 * Routine: pmap_remove_all
4327 * Removes this physical page from
4328 * all physical maps in which it resides.
4329 * Reflects back modify bits to the pager.
4332 * Original versions of this routine were very
4333 * inefficient because they iteratively called
4334 * pmap_remove (slow...)
4338 pmap_remove_all(vm_page_t m)
4340 struct md_page *pvh;
4343 struct rwlock *lock;
4344 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4347 struct spglist free;
4348 int pvh_gen, md_gen;
4350 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4351 ("pmap_remove_all: page %p is not managed", m));
4353 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4354 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4355 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4358 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4360 if (!PMAP_TRYLOCK(pmap)) {
4361 pvh_gen = pvh->pv_gen;
4365 if (pvh_gen != pvh->pv_gen) {
4372 pde = pmap_pde(pmap, va);
4373 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4376 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4378 if (!PMAP_TRYLOCK(pmap)) {
4379 pvh_gen = pvh->pv_gen;
4380 md_gen = m->md.pv_gen;
4384 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4390 PG_A = pmap_accessed_bit(pmap);
4391 PG_M = pmap_modified_bit(pmap);
4392 PG_RW = pmap_rw_bit(pmap);
4393 pmap_resident_count_dec(pmap, 1);
4394 pde = pmap_pde(pmap, pv->pv_va);
4395 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4396 " a 2mpage in page %p's pv list", m));
4397 pte = pmap_pde_to_pte(pde, pv->pv_va);
4398 tpte = pte_load_clear(pte);
4400 pmap->pm_stats.wired_count--;
4402 vm_page_aflag_set(m, PGA_REFERENCED);
4405 * Update the vm_page_t clean and reference bits.
4407 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4409 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4410 pmap_invalidate_page(pmap, pv->pv_va);
4411 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4413 free_pv_entry(pmap, pv);
4416 vm_page_aflag_clear(m, PGA_WRITEABLE);
4418 pmap_delayed_invl_wait(m);
4419 vm_page_free_pages_toq(&free, true);
4423 * pmap_protect_pde: do the things to protect a 2mpage in a process
4426 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4428 pd_entry_t newpde, oldpde;
4429 vm_offset_t eva, va;
4431 boolean_t anychanged;
4432 pt_entry_t PG_G, PG_M, PG_RW;
4434 PG_G = pmap_global_bit(pmap);
4435 PG_M = pmap_modified_bit(pmap);
4436 PG_RW = pmap_rw_bit(pmap);
4438 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4439 KASSERT((sva & PDRMASK) == 0,
4440 ("pmap_protect_pde: sva is not 2mpage aligned"));
4443 oldpde = newpde = *pde;
4444 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4445 (PG_MANAGED | PG_M | PG_RW)) {
4447 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4448 va < eva; va += PAGE_SIZE, m++)
4451 if ((prot & VM_PROT_WRITE) == 0)
4452 newpde &= ~(PG_RW | PG_M);
4453 if ((prot & VM_PROT_EXECUTE) == 0)
4455 if (newpde != oldpde) {
4457 * As an optimization to future operations on this PDE, clear
4458 * PG_PROMOTED. The impending invalidation will remove any
4459 * lingering 4KB page mappings from the TLB.
4461 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4463 if ((oldpde & PG_G) != 0)
4464 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4468 return (anychanged);
4472 * Set the physical protection on the
4473 * specified range of this map as requested.
4476 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4478 vm_offset_t va_next;
4479 pml4_entry_t *pml4e;
4481 pd_entry_t ptpaddr, *pde;
4482 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4483 boolean_t anychanged;
4485 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4486 if (prot == VM_PROT_NONE) {
4487 pmap_remove(pmap, sva, eva);
4491 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4492 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4495 PG_G = pmap_global_bit(pmap);
4496 PG_M = pmap_modified_bit(pmap);
4497 PG_V = pmap_valid_bit(pmap);
4498 PG_RW = pmap_rw_bit(pmap);
4502 * Although this function delays and batches the invalidation
4503 * of stale TLB entries, it does not need to call
4504 * pmap_delayed_invl_started() and
4505 * pmap_delayed_invl_finished(), because it does not
4506 * ordinarily destroy mappings. Stale TLB entries from
4507 * protection-only changes need only be invalidated before the
4508 * pmap lock is released, because protection-only changes do
4509 * not destroy PV entries. Even operations that iterate over
4510 * a physical page's PV list of mappings, like
4511 * pmap_remove_write(), acquire the pmap lock for each
4512 * mapping. Consequently, for protection-only changes, the
4513 * pmap lock suffices to synchronize both page table and TLB
4516 * This function only destroys a mapping if pmap_demote_pde()
4517 * fails. In that case, stale TLB entries are immediately
4522 for (; sva < eva; sva = va_next) {
4524 pml4e = pmap_pml4e(pmap, sva);
4525 if ((*pml4e & PG_V) == 0) {
4526 va_next = (sva + NBPML4) & ~PML4MASK;
4532 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4533 if ((*pdpe & PG_V) == 0) {
4534 va_next = (sva + NBPDP) & ~PDPMASK;
4540 va_next = (sva + NBPDR) & ~PDRMASK;
4544 pde = pmap_pdpe_to_pde(pdpe, sva);
4548 * Weed out invalid mappings.
4554 * Check for large page.
4556 if ((ptpaddr & PG_PS) != 0) {
4558 * Are we protecting the entire large page? If not,
4559 * demote the mapping and fall through.
4561 if (sva + NBPDR == va_next && eva >= va_next) {
4563 * The TLB entry for a PG_G mapping is
4564 * invalidated by pmap_protect_pde().
4566 if (pmap_protect_pde(pmap, pde, sva, prot))
4569 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4571 * The large page mapping was destroyed.
4580 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4582 pt_entry_t obits, pbits;
4586 obits = pbits = *pte;
4587 if ((pbits & PG_V) == 0)
4590 if ((prot & VM_PROT_WRITE) == 0) {
4591 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4592 (PG_MANAGED | PG_M | PG_RW)) {
4593 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4596 pbits &= ~(PG_RW | PG_M);
4598 if ((prot & VM_PROT_EXECUTE) == 0)
4601 if (pbits != obits) {
4602 if (!atomic_cmpset_long(pte, obits, pbits))
4605 pmap_invalidate_page(pmap, sva);
4612 pmap_invalidate_all(pmap);
4616 #if VM_NRESERVLEVEL > 0
4618 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4619 * single page table page (PTP) to a single 2MB page mapping. For promotion
4620 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4621 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4622 * identical characteristics.
4625 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4626 struct rwlock **lockp)
4629 pt_entry_t *firstpte, oldpte, pa, *pte;
4630 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4634 PG_A = pmap_accessed_bit(pmap);
4635 PG_G = pmap_global_bit(pmap);
4636 PG_M = pmap_modified_bit(pmap);
4637 PG_V = pmap_valid_bit(pmap);
4638 PG_RW = pmap_rw_bit(pmap);
4639 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4641 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4644 * Examine the first PTE in the specified PTP. Abort if this PTE is
4645 * either invalid, unused, or does not map the first 4KB physical page
4646 * within a 2MB page.
4648 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4651 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4652 atomic_add_long(&pmap_pde_p_failures, 1);
4653 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4654 " in pmap %p", va, pmap);
4657 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4659 * When PG_M is already clear, PG_RW can be cleared without
4660 * a TLB invalidation.
4662 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4668 * Examine each of the other PTEs in the specified PTP. Abort if this
4669 * PTE maps an unexpected 4KB physical page or does not have identical
4670 * characteristics to the first PTE.
4672 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4673 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4676 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4677 atomic_add_long(&pmap_pde_p_failures, 1);
4678 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4679 " in pmap %p", va, pmap);
4682 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4684 * When PG_M is already clear, PG_RW can be cleared
4685 * without a TLB invalidation.
4687 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4690 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4691 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4692 (va & ~PDRMASK), pmap);
4694 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4695 atomic_add_long(&pmap_pde_p_failures, 1);
4696 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4697 " in pmap %p", va, pmap);
4704 * Save the page table page in its current state until the PDE
4705 * mapping the superpage is demoted by pmap_demote_pde() or
4706 * destroyed by pmap_remove_pde().
4708 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4709 KASSERT(mpte >= vm_page_array &&
4710 mpte < &vm_page_array[vm_page_array_size],
4711 ("pmap_promote_pde: page table page is out of range"));
4712 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4713 ("pmap_promote_pde: page table page's pindex is wrong"));
4714 if (pmap_insert_pt_page(pmap, mpte)) {
4715 atomic_add_long(&pmap_pde_p_failures, 1);
4717 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4723 * Promote the pv entries.
4725 if ((newpde & PG_MANAGED) != 0)
4726 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4729 * Propagate the PAT index to its proper position.
4731 newpde = pmap_swap_pat(pmap, newpde);
4734 * Map the superpage.
4736 if (workaround_erratum383)
4737 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4739 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4741 atomic_add_long(&pmap_pde_promotions, 1);
4742 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4743 " in pmap %p", va, pmap);
4745 #endif /* VM_NRESERVLEVEL > 0 */
4748 * Insert the given physical page (p) at
4749 * the specified virtual address (v) in the
4750 * target physical map with the protection requested.
4752 * If specified, the page will be wired down, meaning
4753 * that the related pte can not be reclaimed.
4755 * NB: This is the only routine which MAY NOT lazy-evaluate
4756 * or lose information. That is, this routine must actually
4757 * insert this page into the given map NOW.
4759 * When destroying both a page table and PV entry, this function
4760 * performs the TLB invalidation before releasing the PV list
4761 * lock, so we do not need pmap_delayed_invl_page() calls here.
4764 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4765 u_int flags, int8_t psind)
4767 struct rwlock *lock;
4769 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4770 pt_entry_t newpte, origpte;
4777 PG_A = pmap_accessed_bit(pmap);
4778 PG_G = pmap_global_bit(pmap);
4779 PG_M = pmap_modified_bit(pmap);
4780 PG_V = pmap_valid_bit(pmap);
4781 PG_RW = pmap_rw_bit(pmap);
4783 va = trunc_page(va);
4784 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4785 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4786 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4788 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4789 va >= kmi.clean_eva,
4790 ("pmap_enter: managed mapping within the clean submap"));
4791 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4792 VM_OBJECT_ASSERT_LOCKED(m->object);
4793 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
4794 ("pmap_enter: flags %u has reserved bits set", flags));
4795 pa = VM_PAGE_TO_PHYS(m);
4796 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4797 if ((flags & VM_PROT_WRITE) != 0)
4799 if ((prot & VM_PROT_WRITE) != 0)
4801 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4802 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4803 if ((prot & VM_PROT_EXECUTE) == 0)
4805 if ((flags & PMAP_ENTER_WIRED) != 0)
4807 if (va < VM_MAXUSER_ADDRESS)
4809 if (pmap == kernel_pmap)
4811 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
4814 * Set modified bit gratuitously for writeable mappings if
4815 * the page is unmanaged. We do not want to take a fault
4816 * to do the dirty bit accounting for these mappings.
4818 if ((m->oflags & VPO_UNMANAGED) != 0) {
4819 if ((newpte & PG_RW) != 0)
4822 newpte |= PG_MANAGED;
4827 /* Assert the required virtual and physical alignment. */
4828 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
4829 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4830 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
4836 * In the case that a page table page is not
4837 * resident, we are creating it here.
4840 pde = pmap_pde(pmap, va);
4841 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4842 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4843 pte = pmap_pde_to_pte(pde, va);
4844 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4845 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4848 } else if (va < VM_MAXUSER_ADDRESS) {
4850 * Here if the pte page isn't mapped, or if it has been
4853 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4854 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4855 nosleep ? NULL : &lock);
4856 if (mpte == NULL && nosleep) {
4857 rv = KERN_RESOURCE_SHORTAGE;
4862 panic("pmap_enter: invalid page directory va=%#lx", va);
4868 * Is the specified virtual address already mapped?
4870 if ((origpte & PG_V) != 0) {
4872 * Wiring change, just update stats. We don't worry about
4873 * wiring PT pages as they remain resident as long as there
4874 * are valid mappings in them. Hence, if a user page is wired,
4875 * the PT page will be also.
4877 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4878 pmap->pm_stats.wired_count++;
4879 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4880 pmap->pm_stats.wired_count--;
4883 * Remove the extra PT page reference.
4887 KASSERT(mpte->wire_count > 0,
4888 ("pmap_enter: missing reference to page table page,"
4893 * Has the physical page changed?
4895 opa = origpte & PG_FRAME;
4898 * No, might be a protection or wiring change.
4900 if ((origpte & PG_MANAGED) != 0 &&
4901 (newpte & PG_RW) != 0)
4902 vm_page_aflag_set(m, PGA_WRITEABLE);
4903 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4909 * The physical page has changed. Temporarily invalidate
4910 * the mapping. This ensures that all threads sharing the
4911 * pmap keep a consistent view of the mapping, which is
4912 * necessary for the correct handling of COW faults. It
4913 * also permits reuse of the old mapping's PV entry,
4914 * avoiding an allocation.
4916 * For consistency, handle unmanaged mappings the same way.
4918 origpte = pte_load_clear(pte);
4919 KASSERT((origpte & PG_FRAME) == opa,
4920 ("pmap_enter: unexpected pa update for %#lx", va));
4921 if ((origpte & PG_MANAGED) != 0) {
4922 om = PHYS_TO_VM_PAGE(opa);
4925 * The pmap lock is sufficient to synchronize with
4926 * concurrent calls to pmap_page_test_mappings() and
4927 * pmap_ts_referenced().
4929 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4931 if ((origpte & PG_A) != 0)
4932 vm_page_aflag_set(om, PGA_REFERENCED);
4933 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4934 pv = pmap_pvh_remove(&om->md, pmap, va);
4935 if ((newpte & PG_MANAGED) == 0)
4936 free_pv_entry(pmap, pv);
4937 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4938 TAILQ_EMPTY(&om->md.pv_list) &&
4939 ((om->flags & PG_FICTITIOUS) != 0 ||
4940 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4941 vm_page_aflag_clear(om, PGA_WRITEABLE);
4943 if ((origpte & PG_A) != 0)
4944 pmap_invalidate_page(pmap, va);
4948 * Increment the counters.
4950 if ((newpte & PG_W) != 0)
4951 pmap->pm_stats.wired_count++;
4952 pmap_resident_count_inc(pmap, 1);
4956 * Enter on the PV list if part of our managed memory.
4958 if ((newpte & PG_MANAGED) != 0) {
4960 pv = get_pv_entry(pmap, &lock);
4963 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4964 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4966 if ((newpte & PG_RW) != 0)
4967 vm_page_aflag_set(m, PGA_WRITEABLE);
4973 if ((origpte & PG_V) != 0) {
4975 origpte = pte_load_store(pte, newpte);
4976 KASSERT((origpte & PG_FRAME) == pa,
4977 ("pmap_enter: unexpected pa update for %#lx", va));
4978 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
4980 if ((origpte & PG_MANAGED) != 0)
4984 * Although the PTE may still have PG_RW set, TLB
4985 * invalidation may nonetheless be required because
4986 * the PTE no longer has PG_M set.
4988 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4990 * This PTE change does not require TLB invalidation.
4994 if ((origpte & PG_A) != 0)
4995 pmap_invalidate_page(pmap, va);
4997 pte_store(pte, newpte);
5001 #if VM_NRESERVLEVEL > 0
5003 * If both the page table page and the reservation are fully
5004 * populated, then attempt promotion.
5006 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5007 pmap_ps_enabled(pmap) &&
5008 (m->flags & PG_FICTITIOUS) == 0 &&
5009 vm_reserv_level_iffullpop(m) == 0)
5010 pmap_promote_pde(pmap, pde, va, &lock);
5022 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5023 * if successful. Returns false if (1) a page table page cannot be allocated
5024 * without sleeping, (2) a mapping already exists at the specified virtual
5025 * address, or (3) a PV entry cannot be allocated without reclaiming another
5029 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5030 struct rwlock **lockp)
5035 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5036 PG_V = pmap_valid_bit(pmap);
5037 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5039 if ((m->oflags & VPO_UNMANAGED) == 0)
5040 newpde |= PG_MANAGED;
5041 if ((prot & VM_PROT_EXECUTE) == 0)
5043 if (va < VM_MAXUSER_ADDRESS)
5045 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5046 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5051 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5052 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5053 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5054 * a mapping already exists at the specified virtual address. Returns
5055 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5056 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5057 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5059 * The parameter "m" is only used when creating a managed, writeable mapping.
5062 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5063 vm_page_t m, struct rwlock **lockp)
5065 struct spglist free;
5066 pd_entry_t oldpde, *pde;
5067 pt_entry_t PG_G, PG_RW, PG_V;
5070 PG_G = pmap_global_bit(pmap);
5071 PG_RW = pmap_rw_bit(pmap);
5072 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5073 ("pmap_enter_pde: newpde is missing PG_M"));
5074 PG_V = pmap_valid_bit(pmap);
5075 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5077 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5078 NULL : lockp)) == NULL) {
5079 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5080 " in pmap %p", va, pmap);
5081 return (KERN_RESOURCE_SHORTAGE);
5083 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5084 pde = &pde[pmap_pde_index(va)];
5086 if ((oldpde & PG_V) != 0) {
5087 KASSERT(pdpg->wire_count > 1,
5088 ("pmap_enter_pde: pdpg's wire count is too low"));
5089 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5091 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5092 " in pmap %p", va, pmap);
5093 return (KERN_FAILURE);
5095 /* Break the existing mapping(s). */
5097 if ((oldpde & PG_PS) != 0) {
5099 * The reference to the PD page that was acquired by
5100 * pmap_allocpde() ensures that it won't be freed.
5101 * However, if the PDE resulted from a promotion, then
5102 * a reserved PT page could be freed.
5104 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5105 if ((oldpde & PG_G) == 0)
5106 pmap_invalidate_pde_page(pmap, va, oldpde);
5108 pmap_delayed_invl_started();
5109 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5111 pmap_invalidate_all(pmap);
5112 pmap_delayed_invl_finished();
5114 vm_page_free_pages_toq(&free, true);
5115 if (va >= VM_MAXUSER_ADDRESS) {
5116 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5117 if (pmap_insert_pt_page(pmap, mt)) {
5119 * XXX Currently, this can't happen because
5120 * we do not perform pmap_enter(psind == 1)
5121 * on the kernel pmap.
5123 panic("pmap_enter_pde: trie insert failed");
5126 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5129 if ((newpde & PG_MANAGED) != 0) {
5131 * Abort this mapping if its PV entry could not be created.
5133 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5135 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5137 * Although "va" is not mapped, paging-
5138 * structure caches could nonetheless have
5139 * entries that refer to the freed page table
5140 * pages. Invalidate those entries.
5142 pmap_invalidate_page(pmap, va);
5143 vm_page_free_pages_toq(&free, true);
5145 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5146 " in pmap %p", va, pmap);
5147 return (KERN_RESOURCE_SHORTAGE);
5149 if ((newpde & PG_RW) != 0) {
5150 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5151 vm_page_aflag_set(mt, PGA_WRITEABLE);
5156 * Increment counters.
5158 if ((newpde & PG_W) != 0)
5159 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5160 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5163 * Map the superpage. (This is not a promoted mapping; there will not
5164 * be any lingering 4KB page mappings in the TLB.)
5166 pde_store(pde, newpde);
5168 atomic_add_long(&pmap_pde_mappings, 1);
5169 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5170 " in pmap %p", va, pmap);
5171 return (KERN_SUCCESS);
5175 * Maps a sequence of resident pages belonging to the same object.
5176 * The sequence begins with the given page m_start. This page is
5177 * mapped at the given virtual address start. Each subsequent page is
5178 * mapped at a virtual address that is offset from start by the same
5179 * amount as the page is offset from m_start within the object. The
5180 * last page in the sequence is the page with the largest offset from
5181 * m_start that can be mapped at a virtual address less than the given
5182 * virtual address end. Not every virtual page between start and end
5183 * is mapped; only those for which a resident page exists with the
5184 * corresponding offset from m_start are mapped.
5187 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5188 vm_page_t m_start, vm_prot_t prot)
5190 struct rwlock *lock;
5193 vm_pindex_t diff, psize;
5195 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5197 psize = atop(end - start);
5202 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5203 va = start + ptoa(diff);
5204 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5205 m->psind == 1 && pmap_ps_enabled(pmap) &&
5206 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5207 m = &m[NBPDR / PAGE_SIZE - 1];
5209 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5211 m = TAILQ_NEXT(m, listq);
5219 * this code makes some *MAJOR* assumptions:
5220 * 1. Current pmap & pmap exists.
5223 * 4. No page table pages.
5224 * but is *MUCH* faster than pmap_enter...
5228 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5230 struct rwlock *lock;
5234 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5241 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5242 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5244 struct spglist free;
5245 pt_entry_t *pte, PG_V;
5248 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5249 (m->oflags & VPO_UNMANAGED) != 0,
5250 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5251 PG_V = pmap_valid_bit(pmap);
5252 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5255 * In the case that a page table page is not
5256 * resident, we are creating it here.
5258 if (va < VM_MAXUSER_ADDRESS) {
5259 vm_pindex_t ptepindex;
5263 * Calculate pagetable page index
5265 ptepindex = pmap_pde_pindex(va);
5266 if (mpte && (mpte->pindex == ptepindex)) {
5270 * Get the page directory entry
5272 ptepa = pmap_pde(pmap, va);
5275 * If the page table page is mapped, we just increment
5276 * the hold count, and activate it. Otherwise, we
5277 * attempt to allocate a page table page. If this
5278 * attempt fails, we don't retry. Instead, we give up.
5280 if (ptepa && (*ptepa & PG_V) != 0) {
5283 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5287 * Pass NULL instead of the PV list lock
5288 * pointer, because we don't intend to sleep.
5290 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5295 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5296 pte = &pte[pmap_pte_index(va)];
5310 * Enter on the PV list if part of our managed memory.
5312 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5313 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5316 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5318 * Although "va" is not mapped, paging-
5319 * structure caches could nonetheless have
5320 * entries that refer to the freed page table
5321 * pages. Invalidate those entries.
5323 pmap_invalidate_page(pmap, va);
5324 vm_page_free_pages_toq(&free, true);
5332 * Increment counters
5334 pmap_resident_count_inc(pmap, 1);
5336 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
5337 if ((prot & VM_PROT_EXECUTE) == 0)
5341 * Now validate mapping with RO protection
5343 if ((m->oflags & VPO_UNMANAGED) != 0)
5344 pte_store(pte, pa | PG_V | PG_U);
5346 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
5351 * Make a temporary mapping for a physical address. This is only intended
5352 * to be used for panic dumps.
5355 pmap_kenter_temporary(vm_paddr_t pa, int i)
5359 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5360 pmap_kenter(va, pa);
5362 return ((void *)crashdumpmap);
5366 * This code maps large physical mmap regions into the
5367 * processor address space. Note that some shortcuts
5368 * are taken, but the code works.
5371 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5372 vm_pindex_t pindex, vm_size_t size)
5375 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5376 vm_paddr_t pa, ptepa;
5380 PG_A = pmap_accessed_bit(pmap);
5381 PG_M = pmap_modified_bit(pmap);
5382 PG_V = pmap_valid_bit(pmap);
5383 PG_RW = pmap_rw_bit(pmap);
5385 VM_OBJECT_ASSERT_WLOCKED(object);
5386 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5387 ("pmap_object_init_pt: non-device object"));
5388 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5389 if (!pmap_ps_enabled(pmap))
5391 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5393 p = vm_page_lookup(object, pindex);
5394 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5395 ("pmap_object_init_pt: invalid page %p", p));
5396 pat_mode = p->md.pat_mode;
5399 * Abort the mapping if the first page is not physically
5400 * aligned to a 2MB page boundary.
5402 ptepa = VM_PAGE_TO_PHYS(p);
5403 if (ptepa & (NBPDR - 1))
5407 * Skip the first page. Abort the mapping if the rest of
5408 * the pages are not physically contiguous or have differing
5409 * memory attributes.
5411 p = TAILQ_NEXT(p, listq);
5412 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5414 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5415 ("pmap_object_init_pt: invalid page %p", p));
5416 if (pa != VM_PAGE_TO_PHYS(p) ||
5417 pat_mode != p->md.pat_mode)
5419 p = TAILQ_NEXT(p, listq);
5423 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5424 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5425 * will not affect the termination of this loop.
5428 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5429 pa < ptepa + size; pa += NBPDR) {
5430 pdpg = pmap_allocpde(pmap, addr, NULL);
5433 * The creation of mappings below is only an
5434 * optimization. If a page directory page
5435 * cannot be allocated without blocking,
5436 * continue on to the next mapping rather than
5442 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5443 pde = &pde[pmap_pde_index(addr)];
5444 if ((*pde & PG_V) == 0) {
5445 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5446 PG_U | PG_RW | PG_V);
5447 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5448 atomic_add_long(&pmap_pde_mappings, 1);
5450 /* Continue on if the PDE is already valid. */
5452 KASSERT(pdpg->wire_count > 0,
5453 ("pmap_object_init_pt: missing reference "
5454 "to page directory page, va: 0x%lx", addr));
5463 * Clear the wired attribute from the mappings for the specified range of
5464 * addresses in the given pmap. Every valid mapping within that range
5465 * must have the wired attribute set. In contrast, invalid mappings
5466 * cannot have the wired attribute set, so they are ignored.
5468 * The wired attribute of the page table entry is not a hardware
5469 * feature, so there is no need to invalidate any TLB entries.
5470 * Since pmap_demote_pde() for the wired entry must never fail,
5471 * pmap_delayed_invl_started()/finished() calls around the
5472 * function are not needed.
5475 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5477 vm_offset_t va_next;
5478 pml4_entry_t *pml4e;
5481 pt_entry_t *pte, PG_V;
5483 PG_V = pmap_valid_bit(pmap);
5485 for (; sva < eva; sva = va_next) {
5486 pml4e = pmap_pml4e(pmap, sva);
5487 if ((*pml4e & PG_V) == 0) {
5488 va_next = (sva + NBPML4) & ~PML4MASK;
5493 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5494 if ((*pdpe & PG_V) == 0) {
5495 va_next = (sva + NBPDP) & ~PDPMASK;
5500 va_next = (sva + NBPDR) & ~PDRMASK;
5503 pde = pmap_pdpe_to_pde(pdpe, sva);
5504 if ((*pde & PG_V) == 0)
5506 if ((*pde & PG_PS) != 0) {
5507 if ((*pde & PG_W) == 0)
5508 panic("pmap_unwire: pde %#jx is missing PG_W",
5512 * Are we unwiring the entire large page? If not,
5513 * demote the mapping and fall through.
5515 if (sva + NBPDR == va_next && eva >= va_next) {
5516 atomic_clear_long(pde, PG_W);
5517 pmap->pm_stats.wired_count -= NBPDR /
5520 } else if (!pmap_demote_pde(pmap, pde, sva))
5521 panic("pmap_unwire: demotion failed");
5525 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5527 if ((*pte & PG_V) == 0)
5529 if ((*pte & PG_W) == 0)
5530 panic("pmap_unwire: pte %#jx is missing PG_W",
5534 * PG_W must be cleared atomically. Although the pmap
5535 * lock synchronizes access to PG_W, another processor
5536 * could be setting PG_M and/or PG_A concurrently.
5538 atomic_clear_long(pte, PG_W);
5539 pmap->pm_stats.wired_count--;
5546 * Copy the range specified by src_addr/len
5547 * from the source map to the range dst_addr/len
5548 * in the destination map.
5550 * This routine is only advisory and need not do anything.
5554 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5555 vm_offset_t src_addr)
5557 struct rwlock *lock;
5558 struct spglist free;
5560 vm_offset_t end_addr = src_addr + len;
5561 vm_offset_t va_next;
5562 vm_page_t dst_pdpg, dstmpte, srcmpte;
5563 pt_entry_t PG_A, PG_M, PG_V;
5565 if (dst_addr != src_addr)
5568 if (dst_pmap->pm_type != src_pmap->pm_type)
5572 * EPT page table entries that require emulation of A/D bits are
5573 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5574 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5575 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5576 * implementations flag an EPT misconfiguration for exec-only
5577 * mappings we skip this function entirely for emulated pmaps.
5579 if (pmap_emulate_ad_bits(dst_pmap))
5583 if (dst_pmap < src_pmap) {
5584 PMAP_LOCK(dst_pmap);
5585 PMAP_LOCK(src_pmap);
5587 PMAP_LOCK(src_pmap);
5588 PMAP_LOCK(dst_pmap);
5591 PG_A = pmap_accessed_bit(dst_pmap);
5592 PG_M = pmap_modified_bit(dst_pmap);
5593 PG_V = pmap_valid_bit(dst_pmap);
5595 for (addr = src_addr; addr < end_addr; addr = va_next) {
5596 pt_entry_t *src_pte, *dst_pte;
5597 pml4_entry_t *pml4e;
5599 pd_entry_t srcptepaddr, *pde;
5601 KASSERT(addr < UPT_MIN_ADDRESS,
5602 ("pmap_copy: invalid to pmap_copy page tables"));
5604 pml4e = pmap_pml4e(src_pmap, addr);
5605 if ((*pml4e & PG_V) == 0) {
5606 va_next = (addr + NBPML4) & ~PML4MASK;
5612 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5613 if ((*pdpe & PG_V) == 0) {
5614 va_next = (addr + NBPDP) & ~PDPMASK;
5620 va_next = (addr + NBPDR) & ~PDRMASK;
5624 pde = pmap_pdpe_to_pde(pdpe, addr);
5626 if (srcptepaddr == 0)
5629 if (srcptepaddr & PG_PS) {
5630 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5632 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5633 if (dst_pdpg == NULL)
5635 pde = (pd_entry_t *)
5636 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5637 pde = &pde[pmap_pde_index(addr)];
5638 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5639 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5640 PMAP_ENTER_NORECLAIM, &lock))) {
5641 *pde = srcptepaddr & ~PG_W;
5642 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5643 atomic_add_long(&pmap_pde_mappings, 1);
5645 dst_pdpg->wire_count--;
5649 srcptepaddr &= PG_FRAME;
5650 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5651 KASSERT(srcmpte->wire_count > 0,
5652 ("pmap_copy: source page table page is unused"));
5654 if (va_next > end_addr)
5657 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5658 src_pte = &src_pte[pmap_pte_index(addr)];
5660 while (addr < va_next) {
5664 * we only virtual copy managed pages
5666 if ((ptetemp & PG_MANAGED) != 0) {
5667 if (dstmpte != NULL &&
5668 dstmpte->pindex == pmap_pde_pindex(addr))
5669 dstmpte->wire_count++;
5670 else if ((dstmpte = pmap_allocpte(dst_pmap,
5671 addr, NULL)) == NULL)
5673 dst_pte = (pt_entry_t *)
5674 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5675 dst_pte = &dst_pte[pmap_pte_index(addr)];
5676 if (*dst_pte == 0 &&
5677 pmap_try_insert_pv_entry(dst_pmap, addr,
5678 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5681 * Clear the wired, modified, and
5682 * accessed (referenced) bits
5685 *dst_pte = ptetemp & ~(PG_W | PG_M |
5687 pmap_resident_count_inc(dst_pmap, 1);
5690 if (pmap_unwire_ptp(dst_pmap, addr,
5693 * Although "addr" is not
5694 * mapped, paging-structure
5695 * caches could nonetheless
5696 * have entries that refer to
5697 * the freed page table pages.
5698 * Invalidate those entries.
5700 pmap_invalidate_page(dst_pmap,
5702 vm_page_free_pages_toq(&free,
5707 if (dstmpte->wire_count >= srcmpte->wire_count)
5717 PMAP_UNLOCK(src_pmap);
5718 PMAP_UNLOCK(dst_pmap);
5722 * Zero the specified hardware page.
5725 pmap_zero_page(vm_page_t m)
5727 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5729 pagezero((void *)va);
5733 * Zero an an area within a single hardware page. off and size must not
5734 * cover an area beyond a single hardware page.
5737 pmap_zero_page_area(vm_page_t m, int off, int size)
5739 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5741 if (off == 0 && size == PAGE_SIZE)
5742 pagezero((void *)va);
5744 bzero((char *)va + off, size);
5748 * Copy 1 specified hardware page to another.
5751 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5753 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5754 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5756 pagecopy((void *)src, (void *)dst);
5759 int unmapped_buf_allowed = 1;
5762 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5763 vm_offset_t b_offset, int xfersize)
5767 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5771 while (xfersize > 0) {
5772 a_pg_offset = a_offset & PAGE_MASK;
5773 pages[0] = ma[a_offset >> PAGE_SHIFT];
5774 b_pg_offset = b_offset & PAGE_MASK;
5775 pages[1] = mb[b_offset >> PAGE_SHIFT];
5776 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5777 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5778 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5779 a_cp = (char *)vaddr[0] + a_pg_offset;
5780 b_cp = (char *)vaddr[1] + b_pg_offset;
5781 bcopy(a_cp, b_cp, cnt);
5782 if (__predict_false(mapped))
5783 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5791 * Returns true if the pmap's pv is one of the first
5792 * 16 pvs linked to from this page. This count may
5793 * be changed upwards or downwards in the future; it
5794 * is only necessary that true be returned for a small
5795 * subset of pmaps for proper page aging.
5798 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5800 struct md_page *pvh;
5801 struct rwlock *lock;
5806 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5807 ("pmap_page_exists_quick: page %p is not managed", m));
5809 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5811 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5812 if (PV_PMAP(pv) == pmap) {
5820 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5821 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5822 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5823 if (PV_PMAP(pv) == pmap) {
5837 * pmap_page_wired_mappings:
5839 * Return the number of managed mappings to the given physical page
5843 pmap_page_wired_mappings(vm_page_t m)
5845 struct rwlock *lock;
5846 struct md_page *pvh;
5850 int count, md_gen, pvh_gen;
5852 if ((m->oflags & VPO_UNMANAGED) != 0)
5854 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5858 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5860 if (!PMAP_TRYLOCK(pmap)) {
5861 md_gen = m->md.pv_gen;
5865 if (md_gen != m->md.pv_gen) {
5870 pte = pmap_pte(pmap, pv->pv_va);
5871 if ((*pte & PG_W) != 0)
5875 if ((m->flags & PG_FICTITIOUS) == 0) {
5876 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5877 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5879 if (!PMAP_TRYLOCK(pmap)) {
5880 md_gen = m->md.pv_gen;
5881 pvh_gen = pvh->pv_gen;
5885 if (md_gen != m->md.pv_gen ||
5886 pvh_gen != pvh->pv_gen) {
5891 pte = pmap_pde(pmap, pv->pv_va);
5892 if ((*pte & PG_W) != 0)
5902 * Returns TRUE if the given page is mapped individually or as part of
5903 * a 2mpage. Otherwise, returns FALSE.
5906 pmap_page_is_mapped(vm_page_t m)
5908 struct rwlock *lock;
5911 if ((m->oflags & VPO_UNMANAGED) != 0)
5913 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5915 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5916 ((m->flags & PG_FICTITIOUS) == 0 &&
5917 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5923 * Destroy all managed, non-wired mappings in the given user-space
5924 * pmap. This pmap cannot be active on any processor besides the
5927 * This function cannot be applied to the kernel pmap. Moreover, it
5928 * is not intended for general use. It is only to be used during
5929 * process termination. Consequently, it can be implemented in ways
5930 * that make it faster than pmap_remove(). First, it can more quickly
5931 * destroy mappings by iterating over the pmap's collection of PV
5932 * entries, rather than searching the page table. Second, it doesn't
5933 * have to test and clear the page table entries atomically, because
5934 * no processor is currently accessing the user address space. In
5935 * particular, a page table entry's dirty bit won't change state once
5936 * this function starts.
5938 * Although this function destroys all of the pmap's managed,
5939 * non-wired mappings, it can delay and batch the invalidation of TLB
5940 * entries without calling pmap_delayed_invl_started() and
5941 * pmap_delayed_invl_finished(). Because the pmap is not active on
5942 * any other processor, none of these TLB entries will ever be used
5943 * before their eventual invalidation. Consequently, there is no need
5944 * for either pmap_remove_all() or pmap_remove_write() to wait for
5945 * that eventual TLB invalidation.
5948 pmap_remove_pages(pmap_t pmap)
5951 pt_entry_t *pte, tpte;
5952 pt_entry_t PG_M, PG_RW, PG_V;
5953 struct spglist free;
5954 vm_page_t m, mpte, mt;
5956 struct md_page *pvh;
5957 struct pv_chunk *pc, *npc;
5958 struct rwlock *lock;
5960 uint64_t inuse, bitmask;
5961 int allfree, field, freed, idx;
5962 boolean_t superpage;
5966 * Assert that the given pmap is only active on the current
5967 * CPU. Unfortunately, we cannot block another CPU from
5968 * activating the pmap while this function is executing.
5970 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5973 cpuset_t other_cpus;
5975 other_cpus = all_cpus;
5977 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5978 CPU_AND(&other_cpus, &pmap->pm_active);
5980 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5985 PG_M = pmap_modified_bit(pmap);
5986 PG_V = pmap_valid_bit(pmap);
5987 PG_RW = pmap_rw_bit(pmap);
5991 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5994 for (field = 0; field < _NPCM; field++) {
5995 inuse = ~pc->pc_map[field] & pc_freemask[field];
5996 while (inuse != 0) {
5998 bitmask = 1UL << bit;
5999 idx = field * 64 + bit;
6000 pv = &pc->pc_pventry[idx];
6003 pte = pmap_pdpe(pmap, pv->pv_va);
6005 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6007 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6010 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6012 pte = &pte[pmap_pte_index(pv->pv_va)];
6016 * Keep track whether 'tpte' is a
6017 * superpage explicitly instead of
6018 * relying on PG_PS being set.
6020 * This is because PG_PS is numerically
6021 * identical to PG_PTE_PAT and thus a
6022 * regular page could be mistaken for
6028 if ((tpte & PG_V) == 0) {
6029 panic("bad pte va %lx pte %lx",
6034 * We cannot remove wired pages from a process' mapping at this time
6042 pa = tpte & PG_PS_FRAME;
6044 pa = tpte & PG_FRAME;
6046 m = PHYS_TO_VM_PAGE(pa);
6047 KASSERT(m->phys_addr == pa,
6048 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6049 m, (uintmax_t)m->phys_addr,
6052 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6053 m < &vm_page_array[vm_page_array_size],
6054 ("pmap_remove_pages: bad tpte %#jx",
6060 * Update the vm_page_t clean/reference bits.
6062 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6064 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6070 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6073 pc->pc_map[field] |= bitmask;
6075 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6076 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6077 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6079 if (TAILQ_EMPTY(&pvh->pv_list)) {
6080 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6081 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6082 TAILQ_EMPTY(&mt->md.pv_list))
6083 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6085 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6087 pmap_resident_count_dec(pmap, 1);
6088 KASSERT(mpte->wire_count == NPTEPG,
6089 ("pmap_remove_pages: pte page wire count error"));
6090 mpte->wire_count = 0;
6091 pmap_add_delayed_free_list(mpte, &free, FALSE);
6094 pmap_resident_count_dec(pmap, 1);
6095 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6097 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6098 TAILQ_EMPTY(&m->md.pv_list) &&
6099 (m->flags & PG_FICTITIOUS) == 0) {
6100 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6101 if (TAILQ_EMPTY(&pvh->pv_list))
6102 vm_page_aflag_clear(m, PGA_WRITEABLE);
6105 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6109 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6110 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6111 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6113 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6119 pmap_invalidate_all(pmap);
6121 vm_page_free_pages_toq(&free, true);
6125 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6127 struct rwlock *lock;
6129 struct md_page *pvh;
6130 pt_entry_t *pte, mask;
6131 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6133 int md_gen, pvh_gen;
6137 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6140 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6142 if (!PMAP_TRYLOCK(pmap)) {
6143 md_gen = m->md.pv_gen;
6147 if (md_gen != m->md.pv_gen) {
6152 pte = pmap_pte(pmap, pv->pv_va);
6155 PG_M = pmap_modified_bit(pmap);
6156 PG_RW = pmap_rw_bit(pmap);
6157 mask |= PG_RW | PG_M;
6160 PG_A = pmap_accessed_bit(pmap);
6161 PG_V = pmap_valid_bit(pmap);
6162 mask |= PG_V | PG_A;
6164 rv = (*pte & mask) == mask;
6169 if ((m->flags & PG_FICTITIOUS) == 0) {
6170 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6171 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6173 if (!PMAP_TRYLOCK(pmap)) {
6174 md_gen = m->md.pv_gen;
6175 pvh_gen = pvh->pv_gen;
6179 if (md_gen != m->md.pv_gen ||
6180 pvh_gen != pvh->pv_gen) {
6185 pte = pmap_pde(pmap, pv->pv_va);
6188 PG_M = pmap_modified_bit(pmap);
6189 PG_RW = pmap_rw_bit(pmap);
6190 mask |= PG_RW | PG_M;
6193 PG_A = pmap_accessed_bit(pmap);
6194 PG_V = pmap_valid_bit(pmap);
6195 mask |= PG_V | PG_A;
6197 rv = (*pte & mask) == mask;
6211 * Return whether or not the specified physical page was modified
6212 * in any physical maps.
6215 pmap_is_modified(vm_page_t m)
6218 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6219 ("pmap_is_modified: page %p is not managed", m));
6222 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6223 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6224 * is clear, no PTEs can have PG_M set.
6226 VM_OBJECT_ASSERT_WLOCKED(m->object);
6227 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6229 return (pmap_page_test_mappings(m, FALSE, TRUE));
6233 * pmap_is_prefaultable:
6235 * Return whether or not the specified virtual address is eligible
6239 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6242 pt_entry_t *pte, PG_V;
6245 PG_V = pmap_valid_bit(pmap);
6248 pde = pmap_pde(pmap, addr);
6249 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6250 pte = pmap_pde_to_pte(pde, addr);
6251 rv = (*pte & PG_V) == 0;
6258 * pmap_is_referenced:
6260 * Return whether or not the specified physical page was referenced
6261 * in any physical maps.
6264 pmap_is_referenced(vm_page_t m)
6267 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6268 ("pmap_is_referenced: page %p is not managed", m));
6269 return (pmap_page_test_mappings(m, TRUE, FALSE));
6273 * Clear the write and modified bits in each of the given page's mappings.
6276 pmap_remove_write(vm_page_t m)
6278 struct md_page *pvh;
6280 struct rwlock *lock;
6281 pv_entry_t next_pv, pv;
6283 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6285 int pvh_gen, md_gen;
6287 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6288 ("pmap_remove_write: page %p is not managed", m));
6291 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6292 * set by another thread while the object is locked. Thus,
6293 * if PGA_WRITEABLE is clear, no page table entries need updating.
6295 VM_OBJECT_ASSERT_WLOCKED(m->object);
6296 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6298 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6299 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6300 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6303 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6305 if (!PMAP_TRYLOCK(pmap)) {
6306 pvh_gen = pvh->pv_gen;
6310 if (pvh_gen != pvh->pv_gen) {
6316 PG_RW = pmap_rw_bit(pmap);
6318 pde = pmap_pde(pmap, va);
6319 if ((*pde & PG_RW) != 0)
6320 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6321 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6322 ("inconsistent pv lock %p %p for page %p",
6323 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6326 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6328 if (!PMAP_TRYLOCK(pmap)) {
6329 pvh_gen = pvh->pv_gen;
6330 md_gen = m->md.pv_gen;
6334 if (pvh_gen != pvh->pv_gen ||
6335 md_gen != m->md.pv_gen) {
6341 PG_M = pmap_modified_bit(pmap);
6342 PG_RW = pmap_rw_bit(pmap);
6343 pde = pmap_pde(pmap, pv->pv_va);
6344 KASSERT((*pde & PG_PS) == 0,
6345 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6347 pte = pmap_pde_to_pte(pde, pv->pv_va);
6350 if (oldpte & PG_RW) {
6351 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6354 if ((oldpte & PG_M) != 0)
6356 pmap_invalidate_page(pmap, pv->pv_va);
6361 vm_page_aflag_clear(m, PGA_WRITEABLE);
6362 pmap_delayed_invl_wait(m);
6365 static __inline boolean_t
6366 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6369 if (!pmap_emulate_ad_bits(pmap))
6372 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6375 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6376 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6377 * if the EPT_PG_WRITE bit is set.
6379 if ((pte & EPT_PG_WRITE) != 0)
6383 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6385 if ((pte & EPT_PG_EXECUTE) == 0 ||
6386 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6393 * pmap_ts_referenced:
6395 * Return a count of reference bits for a page, clearing those bits.
6396 * It is not necessary for every reference bit to be cleared, but it
6397 * is necessary that 0 only be returned when there are truly no
6398 * reference bits set.
6400 * As an optimization, update the page's dirty field if a modified bit is
6401 * found while counting reference bits. This opportunistic update can be
6402 * performed at low cost and can eliminate the need for some future calls
6403 * to pmap_is_modified(). However, since this function stops after
6404 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6405 * dirty pages. Those dirty pages will only be detected by a future call
6406 * to pmap_is_modified().
6408 * A DI block is not needed within this function, because
6409 * invalidations are performed before the PV list lock is
6413 pmap_ts_referenced(vm_page_t m)
6415 struct md_page *pvh;
6418 struct rwlock *lock;
6419 pd_entry_t oldpde, *pde;
6420 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6423 int cleared, md_gen, not_cleared, pvh_gen;
6424 struct spglist free;
6427 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6428 ("pmap_ts_referenced: page %p is not managed", m));
6431 pa = VM_PAGE_TO_PHYS(m);
6432 lock = PHYS_TO_PV_LIST_LOCK(pa);
6433 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6437 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6438 goto small_mappings;
6444 if (!PMAP_TRYLOCK(pmap)) {
6445 pvh_gen = pvh->pv_gen;
6449 if (pvh_gen != pvh->pv_gen) {
6454 PG_A = pmap_accessed_bit(pmap);
6455 PG_M = pmap_modified_bit(pmap);
6456 PG_RW = pmap_rw_bit(pmap);
6458 pde = pmap_pde(pmap, pv->pv_va);
6460 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6462 * Although "oldpde" is mapping a 2MB page, because
6463 * this function is called at a 4KB page granularity,
6464 * we only update the 4KB page under test.
6468 if ((oldpde & PG_A) != 0) {
6470 * Since this reference bit is shared by 512 4KB
6471 * pages, it should not be cleared every time it is
6472 * tested. Apply a simple "hash" function on the
6473 * physical page number, the virtual superpage number,
6474 * and the pmap address to select one 4KB page out of
6475 * the 512 on which testing the reference bit will
6476 * result in clearing that reference bit. This
6477 * function is designed to avoid the selection of the
6478 * same 4KB page for every 2MB page mapping.
6480 * On demotion, a mapping that hasn't been referenced
6481 * is simply destroyed. To avoid the possibility of a
6482 * subsequent page fault on a demoted wired mapping,
6483 * always leave its reference bit set. Moreover,
6484 * since the superpage is wired, the current state of
6485 * its reference bit won't affect page replacement.
6487 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6488 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6489 (oldpde & PG_W) == 0) {
6490 if (safe_to_clear_referenced(pmap, oldpde)) {
6491 atomic_clear_long(pde, PG_A);
6492 pmap_invalidate_page(pmap, pv->pv_va);
6494 } else if (pmap_demote_pde_locked(pmap, pde,
6495 pv->pv_va, &lock)) {
6497 * Remove the mapping to a single page
6498 * so that a subsequent access may
6499 * repromote. Since the underlying
6500 * page table page is fully populated,
6501 * this removal never frees a page
6505 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6507 pte = pmap_pde_to_pte(pde, va);
6508 pmap_remove_pte(pmap, pte, va, *pde,
6510 pmap_invalidate_page(pmap, va);
6516 * The superpage mapping was removed
6517 * entirely and therefore 'pv' is no
6525 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6526 ("inconsistent pv lock %p %p for page %p",
6527 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6532 /* Rotate the PV list if it has more than one entry. */
6533 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6534 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6535 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6538 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6540 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6542 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6549 if (!PMAP_TRYLOCK(pmap)) {
6550 pvh_gen = pvh->pv_gen;
6551 md_gen = m->md.pv_gen;
6555 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6560 PG_A = pmap_accessed_bit(pmap);
6561 PG_M = pmap_modified_bit(pmap);
6562 PG_RW = pmap_rw_bit(pmap);
6563 pde = pmap_pde(pmap, pv->pv_va);
6564 KASSERT((*pde & PG_PS) == 0,
6565 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6567 pte = pmap_pde_to_pte(pde, pv->pv_va);
6568 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6570 if ((*pte & PG_A) != 0) {
6571 if (safe_to_clear_referenced(pmap, *pte)) {
6572 atomic_clear_long(pte, PG_A);
6573 pmap_invalidate_page(pmap, pv->pv_va);
6575 } else if ((*pte & PG_W) == 0) {
6577 * Wired pages cannot be paged out so
6578 * doing accessed bit emulation for
6579 * them is wasted effort. We do the
6580 * hard work for unwired pages only.
6582 pmap_remove_pte(pmap, pte, pv->pv_va,
6583 *pde, &free, &lock);
6584 pmap_invalidate_page(pmap, pv->pv_va);
6589 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6590 ("inconsistent pv lock %p %p for page %p",
6591 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6596 /* Rotate the PV list if it has more than one entry. */
6597 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6598 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6599 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6602 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6603 not_cleared < PMAP_TS_REFERENCED_MAX);
6606 vm_page_free_pages_toq(&free, true);
6607 return (cleared + not_cleared);
6611 * Apply the given advice to the specified range of addresses within the
6612 * given pmap. Depending on the advice, clear the referenced and/or
6613 * modified flags in each mapping and set the mapped page's dirty field.
6616 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6618 struct rwlock *lock;
6619 pml4_entry_t *pml4e;
6621 pd_entry_t oldpde, *pde;
6622 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6623 vm_offset_t va, va_next;
6625 boolean_t anychanged;
6627 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6631 * A/D bit emulation requires an alternate code path when clearing
6632 * the modified and accessed bits below. Since this function is
6633 * advisory in nature we skip it entirely for pmaps that require
6634 * A/D bit emulation.
6636 if (pmap_emulate_ad_bits(pmap))
6639 PG_A = pmap_accessed_bit(pmap);
6640 PG_G = pmap_global_bit(pmap);
6641 PG_M = pmap_modified_bit(pmap);
6642 PG_V = pmap_valid_bit(pmap);
6643 PG_RW = pmap_rw_bit(pmap);
6645 pmap_delayed_invl_started();
6647 for (; sva < eva; sva = va_next) {
6648 pml4e = pmap_pml4e(pmap, sva);
6649 if ((*pml4e & PG_V) == 0) {
6650 va_next = (sva + NBPML4) & ~PML4MASK;
6655 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6656 if ((*pdpe & PG_V) == 0) {
6657 va_next = (sva + NBPDP) & ~PDPMASK;
6662 va_next = (sva + NBPDR) & ~PDRMASK;
6665 pde = pmap_pdpe_to_pde(pdpe, sva);
6667 if ((oldpde & PG_V) == 0)
6669 else if ((oldpde & PG_PS) != 0) {
6670 if ((oldpde & PG_MANAGED) == 0)
6673 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6678 * The large page mapping was destroyed.
6684 * Unless the page mappings are wired, remove the
6685 * mapping to a single page so that a subsequent
6686 * access may repromote. Since the underlying page
6687 * table page is fully populated, this removal never
6688 * frees a page table page.
6690 if ((oldpde & PG_W) == 0) {
6691 pte = pmap_pde_to_pte(pde, sva);
6692 KASSERT((*pte & PG_V) != 0,
6693 ("pmap_advise: invalid PTE"));
6694 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6704 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6706 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6708 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6709 if (advice == MADV_DONTNEED) {
6711 * Future calls to pmap_is_modified()
6712 * can be avoided by making the page
6715 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6718 atomic_clear_long(pte, PG_M | PG_A);
6719 } else if ((*pte & PG_A) != 0)
6720 atomic_clear_long(pte, PG_A);
6724 if ((*pte & PG_G) != 0) {
6731 if (va != va_next) {
6732 pmap_invalidate_range(pmap, va, sva);
6737 pmap_invalidate_range(pmap, va, sva);
6740 pmap_invalidate_all(pmap);
6742 pmap_delayed_invl_finished();
6746 * Clear the modify bits on the specified physical page.
6749 pmap_clear_modify(vm_page_t m)
6751 struct md_page *pvh;
6753 pv_entry_t next_pv, pv;
6754 pd_entry_t oldpde, *pde;
6755 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6756 struct rwlock *lock;
6758 int md_gen, pvh_gen;
6760 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6761 ("pmap_clear_modify: page %p is not managed", m));
6762 VM_OBJECT_ASSERT_WLOCKED(m->object);
6763 KASSERT(!vm_page_xbusied(m),
6764 ("pmap_clear_modify: page %p is exclusive busied", m));
6767 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6768 * If the object containing the page is locked and the page is not
6769 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6771 if ((m->aflags & PGA_WRITEABLE) == 0)
6773 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6774 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6775 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6778 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6780 if (!PMAP_TRYLOCK(pmap)) {
6781 pvh_gen = pvh->pv_gen;
6785 if (pvh_gen != pvh->pv_gen) {
6790 PG_M = pmap_modified_bit(pmap);
6791 PG_V = pmap_valid_bit(pmap);
6792 PG_RW = pmap_rw_bit(pmap);
6794 pde = pmap_pde(pmap, va);
6796 if ((oldpde & PG_RW) != 0) {
6797 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6798 if ((oldpde & PG_W) == 0) {
6800 * Write protect the mapping to a
6801 * single page so that a subsequent
6802 * write access may repromote.
6804 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6806 pte = pmap_pde_to_pte(pde, va);
6808 if ((oldpte & PG_V) != 0) {
6809 while (!atomic_cmpset_long(pte,
6811 oldpte & ~(PG_M | PG_RW)))
6814 pmap_invalidate_page(pmap, va);
6821 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6823 if (!PMAP_TRYLOCK(pmap)) {
6824 md_gen = m->md.pv_gen;
6825 pvh_gen = pvh->pv_gen;
6829 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6834 PG_M = pmap_modified_bit(pmap);
6835 PG_RW = pmap_rw_bit(pmap);
6836 pde = pmap_pde(pmap, pv->pv_va);
6837 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6838 " a 2mpage in page %p's pv list", m));
6839 pte = pmap_pde_to_pte(pde, pv->pv_va);
6840 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6841 atomic_clear_long(pte, PG_M);
6842 pmap_invalidate_page(pmap, pv->pv_va);
6850 * Miscellaneous support routines follow
6853 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6854 static __inline void
6855 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6860 * The cache mode bits are all in the low 32-bits of the
6861 * PTE, so we can just spin on updating the low 32-bits.
6864 opte = *(u_int *)pte;
6865 npte = opte & ~mask;
6867 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6870 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6871 static __inline void
6872 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6877 * The cache mode bits are all in the low 32-bits of the
6878 * PDE, so we can just spin on updating the low 32-bits.
6881 opde = *(u_int *)pde;
6882 npde = opde & ~mask;
6884 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6888 * Map a set of physical memory pages into the kernel virtual
6889 * address space. Return a pointer to where it is mapped. This
6890 * routine is intended to be used for mapping device memory,
6894 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6896 struct pmap_preinit_mapping *ppim;
6897 vm_offset_t va, offset;
6901 offset = pa & PAGE_MASK;
6902 size = round_page(offset + size);
6903 pa = trunc_page(pa);
6905 if (!pmap_initialized) {
6907 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6908 ppim = pmap_preinit_mapping + i;
6909 if (ppim->va == 0) {
6913 ppim->va = virtual_avail;
6914 virtual_avail += size;
6920 panic("%s: too many preinit mappings", __func__);
6923 * If we have a preinit mapping, re-use it.
6925 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6926 ppim = pmap_preinit_mapping + i;
6927 if (ppim->pa == pa && ppim->sz == size &&
6929 return ((void *)(ppim->va + offset));
6932 * If the specified range of physical addresses fits within
6933 * the direct map window, use the direct map.
6935 if (pa < dmaplimit && pa + size < dmaplimit) {
6936 va = PHYS_TO_DMAP(pa);
6937 if (!pmap_change_attr(va, size, mode))
6938 return ((void *)(va + offset));
6940 va = kva_alloc(size);
6942 panic("%s: Couldn't allocate KVA", __func__);
6944 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6945 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6946 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6947 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6948 return ((void *)(va + offset));
6952 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6955 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6959 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6962 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6966 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6968 struct pmap_preinit_mapping *ppim;
6972 /* If we gave a direct map region in pmap_mapdev, do nothing */
6973 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6975 offset = va & PAGE_MASK;
6976 size = round_page(offset + size);
6977 va = trunc_page(va);
6978 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6979 ppim = pmap_preinit_mapping + i;
6980 if (ppim->va == va && ppim->sz == size) {
6981 if (pmap_initialized)
6987 if (va + size == virtual_avail)
6992 if (pmap_initialized)
6997 * Tries to demote a 1GB page mapping.
7000 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7002 pdp_entry_t newpdpe, oldpdpe;
7003 pd_entry_t *firstpde, newpde, *pde;
7004 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7008 PG_A = pmap_accessed_bit(pmap);
7009 PG_M = pmap_modified_bit(pmap);
7010 PG_V = pmap_valid_bit(pmap);
7011 PG_RW = pmap_rw_bit(pmap);
7013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7015 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7016 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7017 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7018 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7019 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7020 " in pmap %p", va, pmap);
7023 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7024 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7025 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7026 KASSERT((oldpdpe & PG_A) != 0,
7027 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7028 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7029 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7033 * Initialize the page directory page.
7035 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7041 * Demote the mapping.
7046 * Invalidate a stale recursive mapping of the page directory page.
7048 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7050 pmap_pdpe_demotions++;
7051 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7052 " in pmap %p", va, pmap);
7057 * Sets the memory attribute for the specified page.
7060 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7063 m->md.pat_mode = ma;
7066 * If "m" is a normal page, update its direct mapping. This update
7067 * can be relied upon to perform any cache operations that are
7068 * required for data coherence.
7070 if ((m->flags & PG_FICTITIOUS) == 0 &&
7071 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7073 panic("memory attribute change on the direct map failed");
7077 * Changes the specified virtual address range's memory type to that given by
7078 * the parameter "mode". The specified virtual address range must be
7079 * completely contained within either the direct map or the kernel map. If
7080 * the virtual address range is contained within the kernel map, then the
7081 * memory type for each of the corresponding ranges of the direct map is also
7082 * changed. (The corresponding ranges of the direct map are those ranges that
7083 * map the same physical pages as the specified virtual address range.) These
7084 * changes to the direct map are necessary because Intel describes the
7085 * behavior of their processors as "undefined" if two or more mappings to the
7086 * same physical page have different memory types.
7088 * Returns zero if the change completed successfully, and either EINVAL or
7089 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7090 * of the virtual address range was not mapped, and ENOMEM is returned if
7091 * there was insufficient memory available to complete the change. In the
7092 * latter case, the memory type may have been changed on some part of the
7093 * virtual address range or the direct map.
7096 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7100 PMAP_LOCK(kernel_pmap);
7101 error = pmap_change_attr_locked(va, size, mode);
7102 PMAP_UNLOCK(kernel_pmap);
7107 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
7109 vm_offset_t base, offset, tmpva;
7110 vm_paddr_t pa_start, pa_end, pa_end1;
7114 int cache_bits_pte, cache_bits_pde, error;
7117 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7118 base = trunc_page(va);
7119 offset = va & PAGE_MASK;
7120 size = round_page(offset + size);
7123 * Only supported on kernel virtual addresses, including the direct
7124 * map but excluding the recursive map.
7126 if (base < DMAP_MIN_ADDRESS)
7129 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7130 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7134 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7135 * into 4KB pages if required.
7137 for (tmpva = base; tmpva < base + size; ) {
7138 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7139 if (pdpe == NULL || *pdpe == 0)
7141 if (*pdpe & PG_PS) {
7143 * If the current 1GB page already has the required
7144 * memory type, then we need not demote this page. Just
7145 * increment tmpva to the next 1GB page frame.
7147 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7148 tmpva = trunc_1gpage(tmpva) + NBPDP;
7153 * If the current offset aligns with a 1GB page frame
7154 * and there is at least 1GB left within the range, then
7155 * we need not break down this page into 2MB pages.
7157 if ((tmpva & PDPMASK) == 0 &&
7158 tmpva + PDPMASK < base + size) {
7162 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7165 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7170 * If the current 2MB page already has the required
7171 * memory type, then we need not demote this page. Just
7172 * increment tmpva to the next 2MB page frame.
7174 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7175 tmpva = trunc_2mpage(tmpva) + NBPDR;
7180 * If the current offset aligns with a 2MB page frame
7181 * and there is at least 2MB left within the range, then
7182 * we need not break down this page into 4KB pages.
7184 if ((tmpva & PDRMASK) == 0 &&
7185 tmpva + PDRMASK < base + size) {
7189 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7192 pte = pmap_pde_to_pte(pde, tmpva);
7200 * Ok, all the pages exist, so run through them updating their
7201 * cache mode if required.
7203 pa_start = pa_end = 0;
7204 for (tmpva = base; tmpva < base + size; ) {
7205 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7206 if (*pdpe & PG_PS) {
7207 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7208 pmap_pde_attr(pdpe, cache_bits_pde,
7212 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7213 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7214 if (pa_start == pa_end) {
7215 /* Start physical address run. */
7216 pa_start = *pdpe & PG_PS_FRAME;
7217 pa_end = pa_start + NBPDP;
7218 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7221 /* Run ended, update direct map. */
7222 error = pmap_change_attr_locked(
7223 PHYS_TO_DMAP(pa_start),
7224 pa_end - pa_start, mode);
7227 /* Start physical address run. */
7228 pa_start = *pdpe & PG_PS_FRAME;
7229 pa_end = pa_start + NBPDP;
7232 tmpva = trunc_1gpage(tmpva) + NBPDP;
7235 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7237 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7238 pmap_pde_attr(pde, cache_bits_pde,
7242 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7243 (*pde & PG_PS_FRAME) < dmaplimit) {
7244 if (pa_start == pa_end) {
7245 /* Start physical address run. */
7246 pa_start = *pde & PG_PS_FRAME;
7247 pa_end = pa_start + NBPDR;
7248 } else if (pa_end == (*pde & PG_PS_FRAME))
7251 /* Run ended, update direct map. */
7252 error = pmap_change_attr_locked(
7253 PHYS_TO_DMAP(pa_start),
7254 pa_end - pa_start, mode);
7257 /* Start physical address run. */
7258 pa_start = *pde & PG_PS_FRAME;
7259 pa_end = pa_start + NBPDR;
7262 tmpva = trunc_2mpage(tmpva) + NBPDR;
7264 pte = pmap_pde_to_pte(pde, tmpva);
7265 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7266 pmap_pte_attr(pte, cache_bits_pte,
7270 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7271 (*pte & PG_FRAME) < dmaplimit) {
7272 if (pa_start == pa_end) {
7273 /* Start physical address run. */
7274 pa_start = *pte & PG_FRAME;
7275 pa_end = pa_start + PAGE_SIZE;
7276 } else if (pa_end == (*pte & PG_FRAME))
7277 pa_end += PAGE_SIZE;
7279 /* Run ended, update direct map. */
7280 error = pmap_change_attr_locked(
7281 PHYS_TO_DMAP(pa_start),
7282 pa_end - pa_start, mode);
7285 /* Start physical address run. */
7286 pa_start = *pte & PG_FRAME;
7287 pa_end = pa_start + PAGE_SIZE;
7293 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7294 pa_end1 = MIN(pa_end, dmaplimit);
7295 if (pa_start != pa_end1)
7296 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7297 pa_end1 - pa_start, mode);
7301 * Flush CPU caches if required to make sure any data isn't cached that
7302 * shouldn't be, etc.
7305 pmap_invalidate_range(kernel_pmap, base, tmpva);
7306 pmap_invalidate_cache_range(base, tmpva, FALSE);
7312 * Demotes any mapping within the direct map region that covers more than the
7313 * specified range of physical addresses. This range's size must be a power
7314 * of two and its starting address must be a multiple of its size. Since the
7315 * demotion does not change any attributes of the mapping, a TLB invalidation
7316 * is not mandatory. The caller may, however, request a TLB invalidation.
7319 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7328 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7329 KASSERT((base & (len - 1)) == 0,
7330 ("pmap_demote_DMAP: base is not a multiple of len"));
7331 if (len < NBPDP && base < dmaplimit) {
7332 va = PHYS_TO_DMAP(base);
7334 PMAP_LOCK(kernel_pmap);
7335 pdpe = pmap_pdpe(kernel_pmap, va);
7336 if ((*pdpe & X86_PG_V) == 0)
7337 panic("pmap_demote_DMAP: invalid PDPE");
7338 if ((*pdpe & PG_PS) != 0) {
7339 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7340 panic("pmap_demote_DMAP: PDPE failed");
7344 pde = pmap_pdpe_to_pde(pdpe, va);
7345 if ((*pde & X86_PG_V) == 0)
7346 panic("pmap_demote_DMAP: invalid PDE");
7347 if ((*pde & PG_PS) != 0) {
7348 if (!pmap_demote_pde(kernel_pmap, pde, va))
7349 panic("pmap_demote_DMAP: PDE failed");
7353 if (changed && invalidate)
7354 pmap_invalidate_page(kernel_pmap, va);
7355 PMAP_UNLOCK(kernel_pmap);
7360 * perform the pmap work for mincore
7363 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7366 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7370 PG_A = pmap_accessed_bit(pmap);
7371 PG_M = pmap_modified_bit(pmap);
7372 PG_V = pmap_valid_bit(pmap);
7373 PG_RW = pmap_rw_bit(pmap);
7377 pdep = pmap_pde(pmap, addr);
7378 if (pdep != NULL && (*pdep & PG_V)) {
7379 if (*pdep & PG_PS) {
7381 /* Compute the physical address of the 4KB page. */
7382 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7384 val = MINCORE_SUPER;
7386 pte = *pmap_pde_to_pte(pdep, addr);
7387 pa = pte & PG_FRAME;
7395 if ((pte & PG_V) != 0) {
7396 val |= MINCORE_INCORE;
7397 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7398 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7399 if ((pte & PG_A) != 0)
7400 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7402 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7403 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7404 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7405 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7406 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7409 PA_UNLOCK_COND(*locked_pa);
7415 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7417 uint32_t gen, new_gen, pcid_next;
7419 CRITICAL_ASSERT(curthread);
7420 gen = PCPU_GET(pcid_gen);
7421 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7422 return (pti ? 0 : CR3_PCID_SAVE);
7423 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7424 return (CR3_PCID_SAVE);
7425 pcid_next = PCPU_GET(pcid_next);
7426 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7427 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7428 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7429 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7430 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7434 PCPU_SET(pcid_gen, new_gen);
7435 pcid_next = PMAP_PCID_KERN + 1;
7439 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7440 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7441 PCPU_SET(pcid_next, pcid_next + 1);
7446 pmap_activate_sw(struct thread *td)
7448 pmap_t oldpmap, pmap;
7449 struct invpcid_descr d;
7450 uint64_t cached, cr3, kcr3, kern_pti_cached, rsp0, ucr3;
7453 struct amd64tss *tssp;
7456 oldpmap = PCPU_GET(curpmap);
7457 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7458 if (oldpmap == pmap)
7460 cpuid = PCPU_GET(cpuid);
7462 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7464 CPU_SET(cpuid, &pmap->pm_active);
7467 if (pmap_pcid_enabled) {
7468 cached = pmap_pcid_alloc(pmap, cpuid);
7469 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
7470 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7471 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7472 pmap->pm_pcids[cpuid].pm_pcid));
7473 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7474 pmap == kernel_pmap,
7475 ("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
7476 td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7479 * If the INVPCID instruction is not available,
7480 * invltlb_pcid_handler() is used for handle
7481 * invalidate_all IPI, which checks for curpmap ==
7482 * smp_tlb_pmap. Below operations sequence has a
7483 * window where %CR3 is loaded with the new pmap's
7484 * PML4 address, but curpmap value is not yet updated.
7485 * This causes invltlb IPI handler, called between the
7486 * updates, to execute as NOP, which leaves stale TLB
7489 * Note that the most typical use of
7490 * pmap_activate_sw(), from the context switch, is
7491 * immune to this race, because interrupts are
7492 * disabled (while the thread lock is owned), and IPI
7493 * happens after curpmap is updated. Protect other
7494 * callers in a similar way, by disabling interrupts
7495 * around the %cr3 register reload and curpmap
7499 rflags = intr_disable();
7501 kern_pti_cached = pti ? 0 : cached;
7502 if (!kern_pti_cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
7503 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7506 PCPU_SET(curpmap, pmap);
7508 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7509 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7512 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7514 * Manually invalidate translations cached
7515 * from the user page table. They are not
7516 * flushed by reload of cr3 with the kernel
7517 * page table pointer above.
7519 if (invpcid_works) {
7520 d.pcid = PMAP_PCID_USER_PT |
7521 pmap->pm_pcids[cpuid].pm_pcid;
7524 invpcid(&d, INVPCID_CTX);
7526 pmap_pti_pcid_invalidate(ucr3, kcr3);
7530 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7531 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7534 intr_restore(rflags);
7536 PCPU_INC(pm_save_cnt);
7538 load_cr3(pmap->pm_cr3);
7539 PCPU_SET(curpmap, pmap);
7541 PCPU_SET(kcr3, pmap->pm_cr3);
7542 PCPU_SET(ucr3, pmap->pm_ucr3);
7545 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
7546 rsp0 = ((vm_offset_t)PCPU_PTR(pti_stack) +
7547 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful;
7548 tssp = PCPU_GET(tssp);
7549 tssp->tss_rsp0 = rsp0;
7552 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7554 CPU_CLR(cpuid, &oldpmap->pm_active);
7559 pmap_activate(struct thread *td)
7563 pmap_activate_sw(td);
7568 pmap_activate_boot(pmap_t pmap)
7574 * kernel_pmap must be never deactivated, and we ensure that
7575 * by never activating it at all.
7577 MPASS(pmap != kernel_pmap);
7579 cpuid = PCPU_GET(cpuid);
7581 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7583 CPU_SET(cpuid, &pmap->pm_active);
7585 PCPU_SET(curpmap, pmap);
7586 kcr3 = pmap->pm_cr3;
7587 if (pmap_pcid_enabled)
7588 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
7589 PCPU_SET(kcr3, kcr3);
7590 PCPU_SET(ucr3, PMAP_NO_CR3);
7594 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7599 * Increase the starting virtual address of the given mapping if a
7600 * different alignment might result in more superpage mappings.
7603 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7604 vm_offset_t *addr, vm_size_t size)
7606 vm_offset_t superpage_offset;
7610 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7611 offset += ptoa(object->pg_color);
7612 superpage_offset = offset & PDRMASK;
7613 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
7614 (*addr & PDRMASK) == superpage_offset)
7616 if ((*addr & PDRMASK) < superpage_offset)
7617 *addr = (*addr & ~PDRMASK) + superpage_offset;
7619 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
7623 static unsigned long num_dirty_emulations;
7624 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
7625 &num_dirty_emulations, 0, NULL);
7627 static unsigned long num_accessed_emulations;
7628 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
7629 &num_accessed_emulations, 0, NULL);
7631 static unsigned long num_superpage_accessed_emulations;
7632 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
7633 &num_superpage_accessed_emulations, 0, NULL);
7635 static unsigned long ad_emulation_superpage_promotions;
7636 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
7637 &ad_emulation_superpage_promotions, 0, NULL);
7638 #endif /* INVARIANTS */
7641 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
7644 struct rwlock *lock;
7645 #if VM_NRESERVLEVEL > 0
7649 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
7651 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
7652 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
7654 if (!pmap_emulate_ad_bits(pmap))
7657 PG_A = pmap_accessed_bit(pmap);
7658 PG_M = pmap_modified_bit(pmap);
7659 PG_V = pmap_valid_bit(pmap);
7660 PG_RW = pmap_rw_bit(pmap);
7666 pde = pmap_pde(pmap, va);
7667 if (pde == NULL || (*pde & PG_V) == 0)
7670 if ((*pde & PG_PS) != 0) {
7671 if (ftype == VM_PROT_READ) {
7673 atomic_add_long(&num_superpage_accessed_emulations, 1);
7681 pte = pmap_pde_to_pte(pde, va);
7682 if ((*pte & PG_V) == 0)
7685 if (ftype == VM_PROT_WRITE) {
7686 if ((*pte & PG_RW) == 0)
7689 * Set the modified and accessed bits simultaneously.
7691 * Intel EPT PTEs that do software emulation of A/D bits map
7692 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
7693 * An EPT misconfiguration is triggered if the PTE is writable
7694 * but not readable (WR=10). This is avoided by setting PG_A
7695 * and PG_M simultaneously.
7697 *pte |= PG_M | PG_A;
7702 #if VM_NRESERVLEVEL > 0
7703 /* try to promote the mapping */
7704 if (va < VM_MAXUSER_ADDRESS)
7705 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7709 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7711 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
7712 pmap_ps_enabled(pmap) &&
7713 (m->flags & PG_FICTITIOUS) == 0 &&
7714 vm_reserv_level_iffullpop(m) == 0) {
7715 pmap_promote_pde(pmap, pde, va, &lock);
7717 atomic_add_long(&ad_emulation_superpage_promotions, 1);
7723 if (ftype == VM_PROT_WRITE)
7724 atomic_add_long(&num_dirty_emulations, 1);
7726 atomic_add_long(&num_accessed_emulations, 1);
7728 rv = 0; /* success */
7737 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
7742 pt_entry_t *pte, PG_V;
7746 PG_V = pmap_valid_bit(pmap);
7749 pml4 = pmap_pml4e(pmap, va);
7751 if ((*pml4 & PG_V) == 0)
7754 pdp = pmap_pml4e_to_pdpe(pml4, va);
7756 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
7759 pde = pmap_pdpe_to_pde(pdp, va);
7761 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
7764 pte = pmap_pde_to_pte(pde, va);
7773 * Get the kernel virtual address of a set of physical pages. If there are
7774 * physical addresses not covered by the DMAP perform a transient mapping
7775 * that will be removed when calling pmap_unmap_io_transient.
7777 * \param page The pages the caller wishes to obtain the virtual
7778 * address on the kernel memory map.
7779 * \param vaddr On return contains the kernel virtual memory address
7780 * of the pages passed in the page parameter.
7781 * \param count Number of pages passed in.
7782 * \param can_fault TRUE if the thread using the mapped pages can take
7783 * page faults, FALSE otherwise.
7785 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7786 * finished or FALSE otherwise.
7790 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7791 boolean_t can_fault)
7794 boolean_t needs_mapping;
7796 int cache_bits, error __unused, i;
7799 * Allocate any KVA space that we need, this is done in a separate
7800 * loop to prevent calling vmem_alloc while pinned.
7802 needs_mapping = FALSE;
7803 for (i = 0; i < count; i++) {
7804 paddr = VM_PAGE_TO_PHYS(page[i]);
7805 if (__predict_false(paddr >= dmaplimit)) {
7806 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7807 M_BESTFIT | M_WAITOK, &vaddr[i]);
7808 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7809 needs_mapping = TRUE;
7811 vaddr[i] = PHYS_TO_DMAP(paddr);
7815 /* Exit early if everything is covered by the DMAP */
7820 * NB: The sequence of updating a page table followed by accesses
7821 * to the corresponding pages used in the !DMAP case is subject to
7822 * the situation described in the "AMD64 Architecture Programmer's
7823 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7824 * Coherency Considerations". Therefore, issuing the INVLPG right
7825 * after modifying the PTE bits is crucial.
7829 for (i = 0; i < count; i++) {
7830 paddr = VM_PAGE_TO_PHYS(page[i]);
7831 if (paddr >= dmaplimit) {
7834 * Slow path, since we can get page faults
7835 * while mappings are active don't pin the
7836 * thread to the CPU and instead add a global
7837 * mapping visible to all CPUs.
7839 pmap_qenter(vaddr[i], &page[i], 1);
7841 pte = vtopte(vaddr[i]);
7842 cache_bits = pmap_cache_bits(kernel_pmap,
7843 page[i]->md.pat_mode, 0);
7844 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7851 return (needs_mapping);
7855 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7856 boolean_t can_fault)
7863 for (i = 0; i < count; i++) {
7864 paddr = VM_PAGE_TO_PHYS(page[i]);
7865 if (paddr >= dmaplimit) {
7867 pmap_qremove(vaddr[i], 1);
7868 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7874 pmap_quick_enter_page(vm_page_t m)
7878 paddr = VM_PAGE_TO_PHYS(m);
7879 if (paddr < dmaplimit)
7880 return (PHYS_TO_DMAP(paddr));
7881 mtx_lock_spin(&qframe_mtx);
7882 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7883 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7884 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7889 pmap_quick_remove_page(vm_offset_t addr)
7894 pte_store(vtopte(qframe), 0);
7896 mtx_unlock_spin(&qframe_mtx);
7900 pmap_pti_alloc_page(void)
7904 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7905 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
7906 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
7911 pmap_pti_free_page(vm_page_t m)
7914 KASSERT(m->wire_count > 0, ("page %p not wired", m));
7915 if (!vm_page_unwire_noq(m))
7917 vm_page_free_zero(m);
7931 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
7932 VM_OBJECT_WLOCK(pti_obj);
7933 pml4_pg = pmap_pti_alloc_page();
7934 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
7935 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
7936 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
7937 pdpe = pmap_pti_pdpe(va);
7938 pmap_pti_wire_pte(pdpe);
7940 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
7941 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
7942 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
7943 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
7944 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
7945 sizeof(struct gate_descriptor) * NIDT, false);
7946 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
7947 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
7949 /* Doublefault stack IST 1 */
7950 va = common_tss[i].tss_ist1;
7951 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7952 /* NMI stack IST 2 */
7953 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
7954 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7955 /* MC# stack IST 3 */
7956 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
7957 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7958 /* DB# stack IST 4 */
7959 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
7960 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7962 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
7963 (vm_offset_t)etext, true);
7964 pti_finalized = true;
7965 VM_OBJECT_WUNLOCK(pti_obj);
7967 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
7969 static pdp_entry_t *
7970 pmap_pti_pdpe(vm_offset_t va)
7972 pml4_entry_t *pml4e;
7975 vm_pindex_t pml4_idx;
7978 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7980 pml4_idx = pmap_pml4e_index(va);
7981 pml4e = &pti_pml4[pml4_idx];
7985 panic("pml4 alloc after finalization\n");
7986 m = pmap_pti_alloc_page();
7988 pmap_pti_free_page(m);
7989 mphys = *pml4e & ~PAGE_MASK;
7991 mphys = VM_PAGE_TO_PHYS(m);
7992 *pml4e = mphys | X86_PG_RW | X86_PG_V;
7995 mphys = *pml4e & ~PAGE_MASK;
7997 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
8002 pmap_pti_wire_pte(void *pte)
8006 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8007 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8012 pmap_pti_unwire_pde(void *pde, bool only_ref)
8016 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8017 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
8018 MPASS(m->wire_count > 0);
8019 MPASS(only_ref || m->wire_count > 1);
8020 pmap_pti_free_page(m);
8024 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
8029 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8030 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8031 MPASS(m->wire_count > 0);
8032 if (pmap_pti_free_page(m)) {
8033 pde = pmap_pti_pde(va);
8034 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
8036 pmap_pti_unwire_pde(pde, false);
8041 pmap_pti_pde(vm_offset_t va)
8049 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8051 pdpe = pmap_pti_pdpe(va);
8053 m = pmap_pti_alloc_page();
8055 pmap_pti_free_page(m);
8056 MPASS((*pdpe & X86_PG_PS) == 0);
8057 mphys = *pdpe & ~PAGE_MASK;
8059 mphys = VM_PAGE_TO_PHYS(m);
8060 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8063 MPASS((*pdpe & X86_PG_PS) == 0);
8064 mphys = *pdpe & ~PAGE_MASK;
8067 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8068 pd_idx = pmap_pde_index(va);
8074 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8081 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8083 pde = pmap_pti_pde(va);
8084 if (unwire_pde != NULL) {
8086 pmap_pti_wire_pte(pde);
8089 m = pmap_pti_alloc_page();
8091 pmap_pti_free_page(m);
8092 MPASS((*pde & X86_PG_PS) == 0);
8093 mphys = *pde & ~(PAGE_MASK | pg_nx);
8095 mphys = VM_PAGE_TO_PHYS(m);
8096 *pde = mphys | X86_PG_RW | X86_PG_V;
8097 if (unwire_pde != NULL)
8098 *unwire_pde = false;
8101 MPASS((*pde & X86_PG_PS) == 0);
8102 mphys = *pde & ~(PAGE_MASK | pg_nx);
8105 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8106 pte += pmap_pte_index(va);
8112 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8116 pt_entry_t *pte, ptev;
8119 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8121 sva = trunc_page(sva);
8122 MPASS(sva > VM_MAXUSER_ADDRESS);
8123 eva = round_page(eva);
8125 for (; sva < eva; sva += PAGE_SIZE) {
8126 pte = pmap_pti_pte(sva, &unwire_pde);
8127 pa = pmap_kextract(sva);
8128 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8129 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8130 VM_MEMATTR_DEFAULT, FALSE);
8132 pte_store(pte, ptev);
8133 pmap_pti_wire_pte(pte);
8135 KASSERT(!pti_finalized,
8136 ("pti overlap after fin %#lx %#lx %#lx",
8138 KASSERT(*pte == ptev,
8139 ("pti non-identical pte after fin %#lx %#lx %#lx",
8143 pde = pmap_pti_pde(sva);
8144 pmap_pti_unwire_pde(pde, true);
8150 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
8155 VM_OBJECT_WLOCK(pti_obj);
8156 pmap_pti_add_kva_locked(sva, eva, exec);
8157 VM_OBJECT_WUNLOCK(pti_obj);
8161 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
8168 sva = rounddown2(sva, PAGE_SIZE);
8169 MPASS(sva > VM_MAXUSER_ADDRESS);
8170 eva = roundup2(eva, PAGE_SIZE);
8172 VM_OBJECT_WLOCK(pti_obj);
8173 for (va = sva; va < eva; va += PAGE_SIZE) {
8174 pte = pmap_pti_pte(va, NULL);
8175 KASSERT((*pte & X86_PG_V) != 0,
8176 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8177 (u_long)pte, *pte));
8179 pmap_pti_unwire_pte(pte, va);
8181 pmap_invalidate_range(kernel_pmap, sva, eva);
8182 VM_OBJECT_WUNLOCK(pti_obj);
8185 #include "opt_ddb.h"
8187 #include <sys/kdb.h>
8188 #include <ddb/ddb.h>
8190 DB_SHOW_COMMAND(pte, pmap_print_pte)
8196 pt_entry_t *pte, PG_V;
8200 db_printf("show pte addr\n");
8203 va = (vm_offset_t)addr;
8205 if (kdb_thread != NULL)
8206 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
8208 pmap = PCPU_GET(curpmap);
8210 PG_V = pmap_valid_bit(pmap);
8211 pml4 = pmap_pml4e(pmap, va);
8212 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
8213 if ((*pml4 & PG_V) == 0) {
8217 pdp = pmap_pml4e_to_pdpe(pml4, va);
8218 db_printf(" pdpe %#016lx", *pdp);
8219 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
8223 pde = pmap_pdpe_to_pde(pdp, va);
8224 db_printf(" pde %#016lx", *pde);
8225 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
8229 pte = pmap_pde_to_pte(pde, va);
8230 db_printf(" pte %#016lx\n", *pte);
8233 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
8238 a = (vm_paddr_t)addr;
8239 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
8241 db_printf("show phys2dmap addr\n");