2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/asan.h>
116 #include <sys/bitstring.h>
118 #include <sys/systm.h>
119 #include <sys/counter.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/malloc.h>
124 #include <sys/mman.h>
125 #include <sys/mutex.h>
126 #include <sys/proc.h>
127 #include <sys/rangeset.h>
128 #include <sys/rwlock.h>
129 #include <sys/sbuf.h>
132 #include <sys/turnstile.h>
133 #include <sys/vmem.h>
134 #include <sys/vmmeter.h>
135 #include <sys/sched.h>
136 #include <sys/sysctl.h>
144 #include <vm/vm_param.h>
145 #include <vm/vm_kern.h>
146 #include <vm/vm_page.h>
147 #include <vm/vm_map.h>
148 #include <vm/vm_object.h>
149 #include <vm/vm_extern.h>
150 #include <vm/vm_pageout.h>
151 #include <vm/vm_pager.h>
152 #include <vm/vm_phys.h>
153 #include <vm/vm_radix.h>
154 #include <vm/vm_reserv.h>
155 #include <vm/vm_dumpset.h>
158 #include <machine/asan.h>
159 #include <machine/intr_machdep.h>
160 #include <x86/apicvar.h>
161 #include <x86/ifunc.h>
162 #include <machine/cpu.h>
163 #include <machine/cputypes.h>
164 #include <machine/intr_machdep.h>
165 #include <machine/md_var.h>
166 #include <machine/pcb.h>
167 #include <machine/specialreg.h>
169 #include <machine/smp.h>
171 #include <machine/sysarch.h>
172 #include <machine/tss.h>
175 #define PMAP_MEMDOM MAXMEMDOM
177 #define PMAP_MEMDOM 1
180 static __inline boolean_t
181 pmap_type_guest(pmap_t pmap)
184 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
187 static __inline boolean_t
188 pmap_emulate_ad_bits(pmap_t pmap)
191 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
194 static __inline pt_entry_t
195 pmap_valid_bit(pmap_t pmap)
199 switch (pmap->pm_type) {
205 if (pmap_emulate_ad_bits(pmap))
206 mask = EPT_PG_EMUL_V;
211 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
217 static __inline pt_entry_t
218 pmap_rw_bit(pmap_t pmap)
222 switch (pmap->pm_type) {
228 if (pmap_emulate_ad_bits(pmap))
229 mask = EPT_PG_EMUL_RW;
234 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
240 static pt_entry_t pg_g;
242 static __inline pt_entry_t
243 pmap_global_bit(pmap_t pmap)
247 switch (pmap->pm_type) {
256 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
262 static __inline pt_entry_t
263 pmap_accessed_bit(pmap_t pmap)
267 switch (pmap->pm_type) {
273 if (pmap_emulate_ad_bits(pmap))
279 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
285 static __inline pt_entry_t
286 pmap_modified_bit(pmap_t pmap)
290 switch (pmap->pm_type) {
296 if (pmap_emulate_ad_bits(pmap))
302 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
308 static __inline pt_entry_t
309 pmap_pku_mask_bit(pmap_t pmap)
312 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
315 #if !defined(DIAGNOSTIC)
316 #ifdef __GNUC_GNU_INLINE__
317 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
319 #define PMAP_INLINE extern inline
326 #define PV_STAT(x) do { x ; } while (0)
328 #define PV_STAT(x) do { } while (0)
333 #define pa_index(pa) ({ \
334 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
335 ("address %lx beyond the last segment", (pa))); \
338 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
339 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
340 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
341 struct rwlock *_lock; \
342 if (__predict_false((pa) > pmap_last_pa)) \
343 _lock = &pv_dummy_large.pv_lock; \
345 _lock = &(pa_to_pmdp(pa)->pv_lock); \
349 #define pa_index(pa) ((pa) >> PDRSHIFT)
350 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
352 #define NPV_LIST_LOCKS MAXCPU
354 #define PHYS_TO_PV_LIST_LOCK(pa) \
355 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
358 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
359 struct rwlock **_lockp = (lockp); \
360 struct rwlock *_new_lock; \
362 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
363 if (_new_lock != *_lockp) { \
364 if (*_lockp != NULL) \
365 rw_wunlock(*_lockp); \
366 *_lockp = _new_lock; \
371 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
372 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
374 #define RELEASE_PV_LIST_LOCK(lockp) do { \
375 struct rwlock **_lockp = (lockp); \
377 if (*_lockp != NULL) { \
378 rw_wunlock(*_lockp); \
383 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
384 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
386 struct pmap kernel_pmap_store;
388 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
389 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
392 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
393 "Number of kernel page table pages allocated on bootup");
396 vm_paddr_t dmaplimit;
397 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
400 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
401 "VM/pmap parameters");
403 static int pg_ps_enabled = 1;
404 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
405 &pg_ps_enabled, 0, "Are large page mappings enabled?");
407 int __read_frequently la57 = 0;
408 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
410 "5-level paging for host is enabled");
413 pmap_is_la57(pmap_t pmap)
415 if (pmap->pm_type == PT_X86)
417 return (false); /* XXXKIB handle EPT */
420 #define PAT_INDEX_SIZE 8
421 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
423 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
424 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
425 static u_int64_t KPDPphys; /* phys addr of kernel level 3 */
426 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
427 u_int64_t KPML5phys; /* phys addr of kernel level 5,
431 static uint64_t KASANPDPphys;
434 static pml4_entry_t *kernel_pml4;
435 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
436 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
437 static int ndmpdpphys; /* number of DMPDPphys pages */
439 vm_paddr_t kernphys; /* phys addr of start of bootstrap data */
440 vm_paddr_t KERNend; /* and the end */
443 * pmap_mapdev support pre initialization (i.e. console)
445 #define PMAP_PREINIT_MAPPING_COUNT 8
446 static struct pmap_preinit_mapping {
451 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
452 static int pmap_initialized;
455 * Data for the pv entry allocation mechanism.
456 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
460 pc_to_domain(struct pv_chunk *pc)
463 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
467 pc_to_domain(struct pv_chunk *pc __unused)
474 struct pv_chunks_list {
476 TAILQ_HEAD(pch, pv_chunk) pvc_list;
478 } __aligned(CACHE_LINE_SIZE);
480 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
483 struct pmap_large_md_page {
484 struct rwlock pv_lock;
485 struct md_page pv_page;
488 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
489 #define pv_dummy pv_dummy_large.pv_page
490 __read_mostly static struct pmap_large_md_page *pv_table;
491 __read_mostly vm_paddr_t pmap_last_pa;
493 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
494 static u_long pv_invl_gen[NPV_LIST_LOCKS];
495 static struct md_page *pv_table;
496 static struct md_page pv_dummy;
500 * All those kernel PT submaps that BSD is so fond of
502 pt_entry_t *CMAP1 = NULL;
504 static vm_offset_t qframe = 0;
505 static struct mtx qframe_mtx;
507 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
509 static vmem_t *large_vmem;
510 static u_int lm_ents;
511 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
512 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
514 int pmap_pcid_enabled = 1;
515 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
516 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
517 int invpcid_works = 0;
518 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
519 "Is the invpcid instruction available ?");
521 int __read_frequently pti = 0;
522 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
524 "Page Table Isolation enabled");
525 static vm_object_t pti_obj;
526 static pml4_entry_t *pti_pml4;
527 static vm_pindex_t pti_pg_idx;
528 static bool pti_finalized;
530 struct pmap_pkru_range {
531 struct rs_el pkru_rs_el;
536 static uma_zone_t pmap_pkru_ranges_zone;
537 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
538 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
539 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
540 static void *pkru_dup_range(void *ctx, void *data);
541 static void pkru_free_range(void *ctx, void *node);
542 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
543 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
544 static void pmap_pkru_deassign_all(pmap_t pmap);
546 static COUNTER_U64_DEFINE_EARLY(pcid_save_cnt);
547 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLFLAG_RD,
548 &pcid_save_cnt, "Count of saved TLB context on switch");
550 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
551 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
552 static struct mtx invl_gen_mtx;
553 /* Fake lock object to satisfy turnstiles interface. */
554 static struct lock_object invl_gen_ts = {
557 static struct pmap_invl_gen pmap_invl_gen_head = {
561 static u_long pmap_invl_gen = 1;
562 static int pmap_invl_waiters;
563 static struct callout pmap_invl_callout;
564 static bool pmap_invl_callout_inited;
566 #define PMAP_ASSERT_NOT_IN_DI() \
567 KASSERT(pmap_not_in_di(), ("DI already started"))
574 if ((cpu_feature2 & CPUID2_CX16) == 0)
577 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
582 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
586 locked = pmap_di_locked();
587 return (sysctl_handle_int(oidp, &locked, 0, req));
589 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
590 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
591 "Locked delayed invalidation");
593 static bool pmap_not_in_di_l(void);
594 static bool pmap_not_in_di_u(void);
595 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
598 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
602 pmap_not_in_di_l(void)
604 struct pmap_invl_gen *invl_gen;
606 invl_gen = &curthread->td_md.md_invl_gen;
607 return (invl_gen->gen == 0);
611 pmap_thread_init_invl_gen_l(struct thread *td)
613 struct pmap_invl_gen *invl_gen;
615 invl_gen = &td->td_md.md_invl_gen;
620 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
622 struct turnstile *ts;
624 ts = turnstile_trywait(&invl_gen_ts);
625 if (*m_gen > atomic_load_long(invl_gen))
626 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
628 turnstile_cancel(ts);
632 pmap_delayed_invl_finish_unblock(u_long new_gen)
634 struct turnstile *ts;
636 turnstile_chain_lock(&invl_gen_ts);
637 ts = turnstile_lookup(&invl_gen_ts);
639 pmap_invl_gen = new_gen;
641 turnstile_broadcast(ts, TS_SHARED_QUEUE);
642 turnstile_unpend(ts);
644 turnstile_chain_unlock(&invl_gen_ts);
648 * Start a new Delayed Invalidation (DI) block of code, executed by
649 * the current thread. Within a DI block, the current thread may
650 * destroy both the page table and PV list entries for a mapping and
651 * then release the corresponding PV list lock before ensuring that
652 * the mapping is flushed from the TLBs of any processors with the
656 pmap_delayed_invl_start_l(void)
658 struct pmap_invl_gen *invl_gen;
661 invl_gen = &curthread->td_md.md_invl_gen;
662 PMAP_ASSERT_NOT_IN_DI();
663 mtx_lock(&invl_gen_mtx);
664 if (LIST_EMPTY(&pmap_invl_gen_tracker))
665 currgen = pmap_invl_gen;
667 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
668 invl_gen->gen = currgen + 1;
669 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
670 mtx_unlock(&invl_gen_mtx);
674 * Finish the DI block, previously started by the current thread. All
675 * required TLB flushes for the pages marked by
676 * pmap_delayed_invl_page() must be finished before this function is
679 * This function works by bumping the global DI generation number to
680 * the generation number of the current thread's DI, unless there is a
681 * pending DI that started earlier. In the latter case, bumping the
682 * global DI generation number would incorrectly signal that the
683 * earlier DI had finished. Instead, this function bumps the earlier
684 * DI's generation number to match the generation number of the
685 * current thread's DI.
688 pmap_delayed_invl_finish_l(void)
690 struct pmap_invl_gen *invl_gen, *next;
692 invl_gen = &curthread->td_md.md_invl_gen;
693 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
694 mtx_lock(&invl_gen_mtx);
695 next = LIST_NEXT(invl_gen, link);
697 pmap_delayed_invl_finish_unblock(invl_gen->gen);
699 next->gen = invl_gen->gen;
700 LIST_REMOVE(invl_gen, link);
701 mtx_unlock(&invl_gen_mtx);
706 pmap_not_in_di_u(void)
708 struct pmap_invl_gen *invl_gen;
710 invl_gen = &curthread->td_md.md_invl_gen;
711 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
715 pmap_thread_init_invl_gen_u(struct thread *td)
717 struct pmap_invl_gen *invl_gen;
719 invl_gen = &td->td_md.md_invl_gen;
721 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
725 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
727 uint64_t new_high, new_low, old_high, old_low;
730 old_low = new_low = 0;
731 old_high = new_high = (uintptr_t)0;
733 __asm volatile("lock;cmpxchg16b\t%1"
734 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
735 : "b"(new_low), "c" (new_high)
738 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
741 out->next = (void *)old_high;
744 out->next = (void *)new_high;
750 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
751 struct pmap_invl_gen *new_val)
753 uint64_t new_high, new_low, old_high, old_low;
756 new_low = new_val->gen;
757 new_high = (uintptr_t)new_val->next;
758 old_low = old_val->gen;
759 old_high = (uintptr_t)old_val->next;
761 __asm volatile("lock;cmpxchg16b\t%1"
762 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
763 : "b"(new_low), "c" (new_high)
768 static COUNTER_U64_DEFINE_EARLY(pv_page_count);
769 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_page_count, CTLFLAG_RD,
770 &pv_page_count, "Current number of allocated pv pages");
772 static COUNTER_U64_DEFINE_EARLY(user_pt_page_count);
773 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, user_pt_page_count, CTLFLAG_RD,
775 "Current number of allocated page table pages for userspace");
777 static COUNTER_U64_DEFINE_EARLY(kernel_pt_page_count);
778 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, kernel_pt_page_count, CTLFLAG_RD,
779 &kernel_pt_page_count,
780 "Current number of allocated page table pages for the kernel");
784 static COUNTER_U64_DEFINE_EARLY(invl_start_restart);
785 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_start_restart,
786 CTLFLAG_RD, &invl_start_restart,
787 "Number of delayed TLB invalidation request restarts");
789 static COUNTER_U64_DEFINE_EARLY(invl_finish_restart);
790 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
791 &invl_finish_restart,
792 "Number of delayed TLB invalidation completion restarts");
794 static int invl_max_qlen;
795 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
797 "Maximum delayed TLB invalidation request queue length");
800 #define di_delay locks_delay
803 pmap_delayed_invl_start_u(void)
805 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
807 struct lock_delay_arg lda;
815 invl_gen = &td->td_md.md_invl_gen;
816 PMAP_ASSERT_NOT_IN_DI();
817 lock_delay_arg_init(&lda, &di_delay);
818 invl_gen->saved_pri = 0;
819 pri = td->td_base_pri;
822 pri = td->td_base_pri;
824 invl_gen->saved_pri = pri;
831 for (p = &pmap_invl_gen_head;; p = prev.next) {
833 prevl = (uintptr_t)atomic_load_ptr(&p->next);
834 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
835 PV_STAT(counter_u64_add(invl_start_restart, 1));
841 prev.next = (void *)prevl;
844 if ((ii = invl_max_qlen) < i)
845 atomic_cmpset_int(&invl_max_qlen, ii, i);
848 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
849 PV_STAT(counter_u64_add(invl_start_restart, 1));
854 new_prev.gen = prev.gen;
855 new_prev.next = invl_gen;
856 invl_gen->gen = prev.gen + 1;
858 /* Formal fence between store to invl->gen and updating *p. */
859 atomic_thread_fence_rel();
862 * After inserting an invl_gen element with invalid bit set,
863 * this thread blocks any other thread trying to enter the
864 * delayed invalidation block. Do not allow to remove us from
865 * the CPU, because it causes starvation for other threads.
870 * ABA for *p is not possible there, since p->gen can only
871 * increase. So if the *p thread finished its di, then
872 * started a new one and got inserted into the list at the
873 * same place, its gen will appear greater than the previously
876 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
878 PV_STAT(counter_u64_add(invl_start_restart, 1));
884 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
885 * invl_gen->next, allowing other threads to iterate past us.
886 * pmap_di_store_invl() provides fence between the generation
887 * write and the update of next.
889 invl_gen->next = NULL;
894 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
895 struct pmap_invl_gen *p)
897 struct pmap_invl_gen prev, new_prev;
901 * Load invl_gen->gen after setting invl_gen->next
902 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
903 * generations to propagate to our invl_gen->gen. Lock prefix
904 * in atomic_set_ptr() worked as seq_cst fence.
906 mygen = atomic_load_long(&invl_gen->gen);
908 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
911 KASSERT(prev.gen < mygen,
912 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
913 new_prev.gen = mygen;
914 new_prev.next = (void *)((uintptr_t)invl_gen->next &
915 ~PMAP_INVL_GEN_NEXT_INVALID);
917 /* Formal fence between load of prev and storing update to it. */
918 atomic_thread_fence_rel();
920 return (pmap_di_store_invl(p, &prev, &new_prev));
924 pmap_delayed_invl_finish_u(void)
926 struct pmap_invl_gen *invl_gen, *p;
928 struct lock_delay_arg lda;
932 invl_gen = &td->td_md.md_invl_gen;
933 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
934 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
935 ("missed invl_start: INVALID"));
936 lock_delay_arg_init(&lda, &di_delay);
939 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
940 prevl = (uintptr_t)atomic_load_ptr(&p->next);
941 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
942 PV_STAT(counter_u64_add(invl_finish_restart, 1));
946 if ((void *)prevl == invl_gen)
951 * It is legitimate to not find ourself on the list if a
952 * thread before us finished its DI and started it again.
954 if (__predict_false(p == NULL)) {
955 PV_STAT(counter_u64_add(invl_finish_restart, 1));
961 atomic_set_ptr((uintptr_t *)&invl_gen->next,
962 PMAP_INVL_GEN_NEXT_INVALID);
963 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
964 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
965 PMAP_INVL_GEN_NEXT_INVALID);
967 PV_STAT(counter_u64_add(invl_finish_restart, 1));
972 if (atomic_load_int(&pmap_invl_waiters) > 0)
973 pmap_delayed_invl_finish_unblock(0);
974 if (invl_gen->saved_pri != 0) {
976 sched_prio(td, invl_gen->saved_pri);
982 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
984 struct pmap_invl_gen *p, *pn;
989 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
991 nextl = (uintptr_t)atomic_load_ptr(&p->next);
992 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
993 td = first ? NULL : __containerof(p, struct thread,
995 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
996 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
997 td != NULL ? td->td_tid : -1);
1003 static COUNTER_U64_DEFINE_EARLY(invl_wait);
1004 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait,
1005 CTLFLAG_RD, &invl_wait,
1006 "Number of times DI invalidation blocked pmap_remove_all/write");
1008 static COUNTER_U64_DEFINE_EARLY(invl_wait_slow);
1009 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD,
1010 &invl_wait_slow, "Number of slow invalidation waits for lockless DI");
1016 pmap_delayed_invl_genp(vm_page_t m)
1021 pa = VM_PAGE_TO_PHYS(m);
1022 if (__predict_false((pa) > pmap_last_pa))
1023 gen = &pv_dummy_large.pv_invl_gen;
1025 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1031 pmap_delayed_invl_genp(vm_page_t m)
1034 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1039 pmap_delayed_invl_callout_func(void *arg __unused)
1042 if (atomic_load_int(&pmap_invl_waiters) == 0)
1044 pmap_delayed_invl_finish_unblock(0);
1048 pmap_delayed_invl_callout_init(void *arg __unused)
1051 if (pmap_di_locked())
1053 callout_init(&pmap_invl_callout, 1);
1054 pmap_invl_callout_inited = true;
1056 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1057 pmap_delayed_invl_callout_init, NULL);
1060 * Ensure that all currently executing DI blocks, that need to flush
1061 * TLB for the given page m, actually flushed the TLB at the time the
1062 * function returned. If the page m has an empty PV list and we call
1063 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1064 * valid mapping for the page m in either its page table or TLB.
1066 * This function works by blocking until the global DI generation
1067 * number catches up with the generation number associated with the
1068 * given page m and its PV list. Since this function's callers
1069 * typically own an object lock and sometimes own a page lock, it
1070 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1074 pmap_delayed_invl_wait_l(vm_page_t m)
1078 bool accounted = false;
1081 m_gen = pmap_delayed_invl_genp(m);
1082 while (*m_gen > pmap_invl_gen) {
1085 counter_u64_add(invl_wait, 1);
1089 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1094 pmap_delayed_invl_wait_u(vm_page_t m)
1097 struct lock_delay_arg lda;
1101 m_gen = pmap_delayed_invl_genp(m);
1102 lock_delay_arg_init(&lda, &di_delay);
1103 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1104 if (fast || !pmap_invl_callout_inited) {
1105 PV_STAT(counter_u64_add(invl_wait, 1));
1110 * The page's invalidation generation number
1111 * is still below the current thread's number.
1112 * Prepare to block so that we do not waste
1113 * CPU cycles or worse, suffer livelock.
1115 * Since it is impossible to block without
1116 * racing with pmap_delayed_invl_finish_u(),
1117 * prepare for the race by incrementing
1118 * pmap_invl_waiters and arming a 1-tick
1119 * callout which will unblock us if we lose
1122 atomic_add_int(&pmap_invl_waiters, 1);
1125 * Re-check the current thread's invalidation
1126 * generation after incrementing
1127 * pmap_invl_waiters, so that there is no race
1128 * with pmap_delayed_invl_finish_u() setting
1129 * the page generation and checking
1130 * pmap_invl_waiters. The only race allowed
1131 * is for a missed unblock, which is handled
1135 atomic_load_long(&pmap_invl_gen_head.gen)) {
1136 callout_reset(&pmap_invl_callout, 1,
1137 pmap_delayed_invl_callout_func, NULL);
1138 PV_STAT(counter_u64_add(invl_wait_slow, 1));
1139 pmap_delayed_invl_wait_block(m_gen,
1140 &pmap_invl_gen_head.gen);
1142 atomic_add_int(&pmap_invl_waiters, -1);
1147 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1150 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1151 pmap_thread_init_invl_gen_u);
1154 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1157 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1158 pmap_delayed_invl_start_u);
1161 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1164 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1165 pmap_delayed_invl_finish_u);
1168 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1171 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1172 pmap_delayed_invl_wait_u);
1176 * Mark the page m's PV list as participating in the current thread's
1177 * DI block. Any threads concurrently using m's PV list to remove or
1178 * restrict all mappings to m will wait for the current thread's DI
1179 * block to complete before proceeding.
1181 * The function works by setting the DI generation number for m's PV
1182 * list to at least the DI generation number of the current thread.
1183 * This forces a caller of pmap_delayed_invl_wait() to block until
1184 * current thread calls pmap_delayed_invl_finish().
1187 pmap_delayed_invl_page(vm_page_t m)
1191 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1192 gen = curthread->td_md.md_invl_gen.gen;
1195 m_gen = pmap_delayed_invl_genp(m);
1203 static caddr_t crashdumpmap;
1206 * Internal flags for pmap_enter()'s helper functions.
1208 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1209 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1212 * Internal flags for pmap_mapdev_internal() and
1213 * pmap_change_props_locked().
1215 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1216 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1217 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1219 TAILQ_HEAD(pv_chunklist, pv_chunk);
1221 static void free_pv_chunk(struct pv_chunk *pc);
1222 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1223 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1224 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1225 static int popcnt_pc_map_pq(uint64_t *map);
1226 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1227 static void reserve_pv_entries(pmap_t pmap, int needed,
1228 struct rwlock **lockp);
1229 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1230 struct rwlock **lockp);
1231 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1232 u_int flags, struct rwlock **lockp);
1233 #if VM_NRESERVLEVEL > 0
1234 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1235 struct rwlock **lockp);
1237 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1238 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1241 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1242 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1243 vm_prot_t prot, int mode, int flags);
1244 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1245 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1246 vm_offset_t va, struct rwlock **lockp);
1247 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1249 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1250 vm_prot_t prot, struct rwlock **lockp);
1251 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1252 u_int flags, vm_page_t m, struct rwlock **lockp);
1253 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1254 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1255 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1256 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1257 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1259 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1261 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1263 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1264 static vm_page_t pmap_large_map_getptp_unlocked(void);
1265 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1266 #if VM_NRESERVLEVEL > 0
1267 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1268 struct rwlock **lockp);
1270 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1272 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1273 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1275 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1276 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1277 static void pmap_pti_wire_pte(void *pte);
1278 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1279 struct spglist *free, struct rwlock **lockp);
1280 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1281 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1282 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1283 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1284 struct spglist *free);
1285 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1286 pd_entry_t *pde, struct spglist *free,
1287 struct rwlock **lockp);
1288 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1289 vm_page_t m, struct rwlock **lockp);
1290 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1292 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1294 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1295 struct rwlock **lockp);
1296 static vm_page_t pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex,
1297 struct rwlock **lockp, vm_offset_t va);
1298 static vm_page_t pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex,
1299 struct rwlock **lockp, vm_offset_t va);
1300 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1301 struct rwlock **lockp);
1303 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1304 struct spglist *free);
1305 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1307 static vm_page_t pmap_alloc_pt_page(pmap_t, vm_pindex_t, int);
1308 static void pmap_free_pt_page(pmap_t, vm_page_t, bool);
1310 /********************/
1311 /* Inline functions */
1312 /********************/
1315 * Return a non-clipped indexes for a given VA, which are page table
1316 * pages indexes at the corresponding level.
1318 static __inline vm_pindex_t
1319 pmap_pde_pindex(vm_offset_t va)
1321 return (va >> PDRSHIFT);
1324 static __inline vm_pindex_t
1325 pmap_pdpe_pindex(vm_offset_t va)
1327 return (NUPDE + (va >> PDPSHIFT));
1330 static __inline vm_pindex_t
1331 pmap_pml4e_pindex(vm_offset_t va)
1333 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1336 static __inline vm_pindex_t
1337 pmap_pml5e_pindex(vm_offset_t va)
1339 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1342 static __inline pml4_entry_t *
1343 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1346 MPASS(pmap_is_la57(pmap));
1347 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1350 static __inline pml4_entry_t *
1351 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1354 MPASS(pmap_is_la57(pmap));
1355 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1358 static __inline pml4_entry_t *
1359 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1361 pml4_entry_t *pml4e;
1363 /* XXX MPASS(pmap_is_la57(pmap); */
1364 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1365 return (&pml4e[pmap_pml4e_index(va)]);
1368 /* Return a pointer to the PML4 slot that corresponds to a VA */
1369 static __inline pml4_entry_t *
1370 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1372 pml5_entry_t *pml5e;
1373 pml4_entry_t *pml4e;
1376 if (pmap_is_la57(pmap)) {
1377 pml5e = pmap_pml5e(pmap, va);
1378 PG_V = pmap_valid_bit(pmap);
1379 if ((*pml5e & PG_V) == 0)
1381 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1383 pml4e = pmap->pm_pmltop;
1385 return (&pml4e[pmap_pml4e_index(va)]);
1388 static __inline pml4_entry_t *
1389 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1391 MPASS(!pmap_is_la57(pmap));
1392 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1395 /* Return a pointer to the PDP slot that corresponds to a VA */
1396 static __inline pdp_entry_t *
1397 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1401 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1402 return (&pdpe[pmap_pdpe_index(va)]);
1405 /* Return a pointer to the PDP slot that corresponds to a VA */
1406 static __inline pdp_entry_t *
1407 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1409 pml4_entry_t *pml4e;
1412 PG_V = pmap_valid_bit(pmap);
1413 pml4e = pmap_pml4e(pmap, va);
1414 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1416 return (pmap_pml4e_to_pdpe(pml4e, va));
1419 /* Return a pointer to the PD slot that corresponds to a VA */
1420 static __inline pd_entry_t *
1421 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1425 KASSERT((*pdpe & PG_PS) == 0,
1426 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1427 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1428 return (&pde[pmap_pde_index(va)]);
1431 /* Return a pointer to the PD slot that corresponds to a VA */
1432 static __inline pd_entry_t *
1433 pmap_pde(pmap_t pmap, vm_offset_t va)
1438 PG_V = pmap_valid_bit(pmap);
1439 pdpe = pmap_pdpe(pmap, va);
1440 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1442 KASSERT((*pdpe & PG_PS) == 0,
1443 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1444 return (pmap_pdpe_to_pde(pdpe, va));
1447 /* Return a pointer to the PT slot that corresponds to a VA */
1448 static __inline pt_entry_t *
1449 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1453 KASSERT((*pde & PG_PS) == 0,
1454 ("%s: pde %#lx is a leaf", __func__, *pde));
1455 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1456 return (&pte[pmap_pte_index(va)]);
1459 /* Return a pointer to the PT slot that corresponds to a VA */
1460 static __inline pt_entry_t *
1461 pmap_pte(pmap_t pmap, vm_offset_t va)
1466 PG_V = pmap_valid_bit(pmap);
1467 pde = pmap_pde(pmap, va);
1468 if (pde == NULL || (*pde & PG_V) == 0)
1470 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1471 return ((pt_entry_t *)pde);
1472 return (pmap_pde_to_pte(pde, va));
1475 static __inline void
1476 pmap_resident_count_adj(pmap_t pmap, int count)
1479 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1480 KASSERT(pmap->pm_stats.resident_count + count >= 0,
1481 ("pmap %p resident count underflow %ld %d", pmap,
1482 pmap->pm_stats.resident_count, count));
1483 pmap->pm_stats.resident_count += count;
1486 static __inline void
1487 pmap_pt_page_count_pinit(pmap_t pmap, int count)
1489 KASSERT(pmap->pm_stats.resident_count + count >= 0,
1490 ("pmap %p resident count underflow %ld %d", pmap,
1491 pmap->pm_stats.resident_count, count));
1492 pmap->pm_stats.resident_count += count;
1495 static __inline void
1496 pmap_pt_page_count_adj(pmap_t pmap, int count)
1498 if (pmap == kernel_pmap)
1499 counter_u64_add(kernel_pt_page_count, count);
1502 pmap_resident_count_adj(pmap, count);
1503 counter_u64_add(user_pt_page_count, count);
1507 pt_entry_t vtoptem __read_mostly = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT +
1508 NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1) << 3;
1509 vm_offset_t PTmap __read_mostly = (vm_offset_t)P4Tmap;
1511 PMAP_INLINE pt_entry_t *
1512 vtopte(vm_offset_t va)
1514 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1516 return ((pt_entry_t *)(PTmap + ((va >> (PAGE_SHIFT - 3)) & vtoptem)));
1519 pd_entry_t vtopdem __read_mostly = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1520 NPML4EPGSHIFT)) - 1) << 3;
1521 vm_offset_t PDmap __read_mostly = (vm_offset_t)P4Dmap;
1523 static __inline pd_entry_t *
1524 vtopde(vm_offset_t va)
1526 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1528 return ((pt_entry_t *)(PDmap + ((va >> (PDRSHIFT - 3)) & vtopdem)));
1532 allocpages(vm_paddr_t *firstaddr, int n)
1537 bzero((void *)ret, n * PAGE_SIZE);
1538 *firstaddr += n * PAGE_SIZE;
1542 CTASSERT(powerof2(NDMPML4E));
1544 /* number of kernel PDP slots */
1545 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1548 nkpt_init(vm_paddr_t addr)
1555 pt_pages = howmany(addr - kernphys, NBPDR) + 1; /* +1 for 2M hole @0 */
1556 pt_pages += NKPDPE(pt_pages);
1559 * Add some slop beyond the bare minimum required for bootstrapping
1562 * This is quite important when allocating KVA for kernel modules.
1563 * The modules are required to be linked in the negative 2GB of
1564 * the address space. If we run out of KVA in this region then
1565 * pmap_growkernel() will need to allocate page table pages to map
1566 * the entire 512GB of KVA space which is an unnecessary tax on
1569 * Secondly, device memory mapped as part of setting up the low-
1570 * level console(s) is taken from KVA, starting at virtual_avail.
1571 * This is because cninit() is called after pmap_bootstrap() but
1572 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1575 pt_pages += 32; /* 64MB additional slop. */
1581 * Returns the proper write/execute permission for a physical page that is
1582 * part of the initial boot allocations.
1584 * If the page has kernel text, it is marked as read-only. If the page has
1585 * kernel read-only data, it is marked as read-only/not-executable. If the
1586 * page has only read-write data, it is marked as read-write/not-executable.
1587 * If the page is below/above the kernel range, it is marked as read-write.
1589 * This function operates on 2M pages, since we map the kernel space that
1592 static inline pt_entry_t
1593 bootaddr_rwx(vm_paddr_t pa)
1596 * The kernel is loaded at a 2MB-aligned address, and memory below that
1597 * need not be executable. The .bss section is padded to a 2MB
1598 * boundary, so memory following the kernel need not be executable
1599 * either. Preloaded kernel modules have their mapping permissions
1600 * fixed up by the linker.
1602 if (pa < trunc_2mpage(kernphys + btext - KERNSTART) ||
1603 pa >= trunc_2mpage(kernphys + _end - KERNSTART))
1604 return (X86_PG_RW | pg_nx);
1607 * The linker should ensure that the read-only and read-write
1608 * portions don't share the same 2M page, so this shouldn't
1609 * impact read-only data. However, in any case, any page with
1610 * read-write data needs to be read-write.
1612 if (pa >= trunc_2mpage(kernphys + brwsection - KERNSTART))
1613 return (X86_PG_RW | pg_nx);
1616 * Mark any 2M page containing kernel text as read-only. Mark
1617 * other pages with read-only data as read-only and not executable.
1618 * (It is likely a small portion of the read-only data section will
1619 * be marked as read-only, but executable. This should be acceptable
1620 * since the read-only protection will keep the data from changing.)
1621 * Note that fixups to the .text section will still work until we
1624 if (pa < round_2mpage(kernphys + etext - KERNSTART))
1630 create_pagetables(vm_paddr_t *firstaddr)
1635 uint64_t DMPDkernphys;
1639 uint64_t KASANPDphys, KASANPTphys, KASANphys;
1640 vm_offset_t kasankernbase;
1641 int kasankpdpi, kasankpdi, nkasanpte;
1643 int i, j, ndm1g, nkpdpe, nkdmpde;
1645 /* Allocate page table pages for the direct map */
1646 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1647 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1649 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1650 if (ndmpdpphys > NDMPML4E) {
1652 * Each NDMPML4E allows 512 GB, so limit to that,
1653 * and then readjust ndmpdp and ndmpdpphys.
1655 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1656 Maxmem = atop(NDMPML4E * NBPML4);
1657 ndmpdpphys = NDMPML4E;
1658 ndmpdp = NDMPML4E * NPDEPG;
1660 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1662 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1664 * Calculate the number of 1G pages that will fully fit in
1667 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1670 * Allocate 2M pages for the kernel. These will be used in
1671 * place of the one or more 1G pages from ndm1g that maps
1672 * kernel memory into DMAP.
1674 nkdmpde = howmany((vm_offset_t)brwsection - KERNSTART +
1675 kernphys - rounddown2(kernphys, NBPDP), NBPDP);
1676 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1679 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1680 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1682 /* Allocate pages */
1683 KPML4phys = allocpages(firstaddr, 1);
1684 KPDPphys = allocpages(firstaddr, NKPML4E);
1686 KASANPDPphys = allocpages(firstaddr, NKASANPML4E);
1687 KASANPDphys = allocpages(firstaddr, 1);
1691 * Allocate the initial number of kernel page table pages required to
1692 * bootstrap. We defer this until after all memory-size dependent
1693 * allocations are done (e.g. direct map), so that we don't have to
1694 * build in too much slop in our estimate.
1696 * Note that when NKPML4E > 1, we have an empty page underneath
1697 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1698 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1700 nkpt_init(*firstaddr);
1701 nkpdpe = NKPDPE(nkpt);
1703 KPTphys = allocpages(firstaddr, nkpt);
1704 KPDphys = allocpages(firstaddr, nkpdpe);
1707 nkasanpte = howmany(nkpt, KASAN_SHADOW_SCALE);
1708 KASANPTphys = allocpages(firstaddr, nkasanpte);
1709 KASANphys = allocpages(firstaddr, nkasanpte * NPTEPG);
1713 * Connect the zero-filled PT pages to their PD entries. This
1714 * implicitly maps the PT pages at their correct locations within
1717 pd_p = (pd_entry_t *)KPDphys;
1718 for (i = 0; i < nkpt; i++)
1719 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1722 * Map from start of the kernel in physical memory (staging
1723 * area) to the end of loader preallocated memory using 2MB
1724 * pages. This replaces some of the PD entries created above.
1725 * For compatibility, identity map 2M at the start.
1727 pd_p[0] = X86_PG_V | PG_PS | pg_g | X86_PG_M | X86_PG_A |
1729 for (i = 1, pax = kernphys; pax < KERNend; i++, pax += NBPDR) {
1730 /* Preset PG_M and PG_A because demotion expects it. */
1731 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M |
1732 X86_PG_A | bootaddr_rwx(pax);
1736 * Because we map the physical blocks in 2M pages, adjust firstaddr
1737 * to record the physical blocks we've actually mapped into kernel
1738 * virtual address space.
1740 if (*firstaddr < round_2mpage(KERNend))
1741 *firstaddr = round_2mpage(KERNend);
1743 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1744 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1745 for (i = 0; i < nkpdpe; i++)
1746 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1749 kasankernbase = kasan_md_addr_to_shad(KERNBASE);
1750 kasankpdpi = pmap_pdpe_index(kasankernbase);
1751 kasankpdi = pmap_pde_index(kasankernbase);
1753 pdp_p = (pdp_entry_t *)KASANPDPphys;
1754 pdp_p[kasankpdpi] = (KASANPDphys | X86_PG_RW | X86_PG_V | pg_nx);
1756 pd_p = (pd_entry_t *)KASANPDphys;
1757 for (i = 0; i < nkasanpte; i++)
1758 pd_p[i + kasankpdi] = (KASANPTphys + ptoa(i)) | X86_PG_RW |
1761 pt_p = (pt_entry_t *)KASANPTphys;
1762 for (i = 0; i < nkasanpte * NPTEPG; i++)
1763 pt_p[i] = (KASANphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
1764 X86_PG_M | X86_PG_A | pg_nx;
1768 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1769 * the end of physical memory is not aligned to a 1GB page boundary,
1770 * then the residual physical memory is mapped with 2MB pages. Later,
1771 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1772 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1773 * that are partially used.
1775 pd_p = (pd_entry_t *)DMPDphys;
1776 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1777 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1778 /* Preset PG_M and PG_A because demotion expects it. */
1779 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1780 X86_PG_M | X86_PG_A | pg_nx;
1782 pdp_p = (pdp_entry_t *)DMPDPphys;
1783 for (i = 0; i < ndm1g; i++) {
1784 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1785 /* Preset PG_M and PG_A because demotion expects it. */
1786 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1787 X86_PG_M | X86_PG_A | pg_nx;
1789 for (j = 0; i < ndmpdp; i++, j++) {
1790 pdp_p[i] = DMPDphys + ptoa(j);
1791 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1795 * Instead of using a 1G page for the memory containing the kernel,
1796 * use 2M pages with read-only and no-execute permissions. (If using 1G
1797 * pages, this will partially overwrite the PDPEs above.)
1800 pd_p = (pd_entry_t *)DMPDkernphys;
1801 for (i = 0, pax = rounddown2(kernphys, NBPDP);
1802 i < NPDEPG * nkdmpde; i++, pax += NBPDR) {
1803 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M |
1804 X86_PG_A | pg_nx | bootaddr_rwx(pax);
1806 j = rounddown2(kernphys, NBPDP) >> PDPSHIFT;
1807 for (i = 0; i < nkdmpde; i++) {
1808 pdp_p[i + j] = (DMPDkernphys + ptoa(i)) |
1809 X86_PG_RW | X86_PG_V | pg_nx;
1813 /* And recursively map PML4 to itself in order to get PTmap */
1814 p4_p = (pml4_entry_t *)KPML4phys;
1815 p4_p[PML4PML4I] = KPML4phys;
1816 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1819 /* Connect the KASAN shadow map slots up to the PML4. */
1820 for (i = 0; i < NKASANPML4E; i++) {
1821 p4_p[KASANPML4I + i] = KASANPDPphys + ptoa(i);
1822 p4_p[KASANPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1826 /* Connect the Direct Map slots up to the PML4. */
1827 for (i = 0; i < ndmpdpphys; i++) {
1828 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1829 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1832 /* Connect the KVA slots up to the PML4 */
1833 for (i = 0; i < NKPML4E; i++) {
1834 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1835 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1838 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1842 * Bootstrap the system enough to run with virtual memory.
1844 * On amd64 this is called after mapping has already been enabled
1845 * and just syncs the pmap module with what has already been done.
1846 * [We can't call it easily with mapping off since the kernel is not
1847 * mapped with PA == VA, hence we would have to relocate every address
1848 * from the linked base (virtual) address "KERNBASE" to the actual
1849 * (physical) address starting relative to 0]
1852 pmap_bootstrap(vm_paddr_t *firstaddr)
1855 pt_entry_t *pte, *pcpu_pte;
1856 struct region_descriptor r_gdt;
1857 uint64_t cr4, pcpu_phys;
1861 KERNend = *firstaddr;
1862 res = atop(KERNend - (vm_paddr_t)kernphys);
1868 * Create an initial set of page tables to run the kernel in.
1870 create_pagetables(firstaddr);
1872 pcpu_phys = allocpages(firstaddr, MAXCPU);
1875 * Add a physical memory segment (vm_phys_seg) corresponding to the
1876 * preallocated kernel page table pages so that vm_page structures
1877 * representing these pages will be created. The vm_page structures
1878 * are required for promotion of the corresponding kernel virtual
1879 * addresses to superpage mappings.
1881 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1884 * Account for the virtual addresses mapped by create_pagetables().
1886 virtual_avail = (vm_offset_t)KERNSTART + round_2mpage(KERNend -
1887 (vm_paddr_t)kernphys);
1888 virtual_end = VM_MAX_KERNEL_ADDRESS;
1891 * Enable PG_G global pages, then switch to the kernel page
1892 * table from the bootstrap page table. After the switch, it
1893 * is possible to enable SMEP and SMAP since PG_U bits are
1899 load_cr3(KPML4phys);
1900 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1902 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1907 * Initialize the kernel pmap (which is statically allocated).
1908 * Count bootstrap data as being resident in case any of this data is
1909 * later unmapped (using pmap_remove()) and freed.
1911 PMAP_LOCK_INIT(kernel_pmap);
1912 kernel_pmap->pm_pmltop = kernel_pml4;
1913 kernel_pmap->pm_cr3 = KPML4phys;
1914 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1915 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1916 kernel_pmap->pm_stats.resident_count = res;
1917 kernel_pmap->pm_flags = pmap_flags;
1920 * The kernel pmap is always active on all CPUs. Once CPUs are
1921 * enumerated, the mask will be set equal to all_cpus.
1923 CPU_FILL(&kernel_pmap->pm_active);
1926 * Initialize the TLB invalidations generation number lock.
1928 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1931 * Reserve some special page table entries/VA space for temporary
1934 #define SYSMAP(c, p, v, n) \
1935 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1941 * Crashdump maps. The first page is reused as CMAP1 for the
1944 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1945 CADDR1 = crashdumpmap;
1947 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1950 for (i = 0; i < MAXCPU; i++) {
1951 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1952 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1956 * Re-initialize PCPU area for BSP after switching.
1957 * Make hardware use gdt and common_tss from the new PCPU.
1959 STAILQ_INIT(&cpuhead);
1960 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1961 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1962 amd64_bsp_pcpu_init1(&__pcpu[0]);
1963 amd64_bsp_ist_init(&__pcpu[0]);
1964 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1966 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1967 sizeof(struct user_segment_descriptor));
1968 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1969 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1970 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1971 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1972 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1974 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1975 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1976 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1977 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1980 * Initialize the PAT MSR.
1981 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1982 * side-effect, invalidates stale PG_G TLB entries that might
1983 * have been created in our pre-boot environment.
1987 /* Initialize TLB Context Id. */
1988 if (pmap_pcid_enabled) {
1989 for (i = 0; i < MAXCPU; i++) {
1990 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1991 kernel_pmap->pm_pcids[i].pm_gen = 1;
1995 * PMAP_PCID_KERN + 1 is used for initialization of
1996 * proc0 pmap. The pmap' pcid state might be used by
1997 * EFIRT entry before first context switch, so it
1998 * needs to be valid.
2000 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
2001 PCPU_SET(pcid_gen, 1);
2004 * pcpu area for APs is zeroed during AP startup.
2005 * pc_pcid_next and pc_pcid_gen are initialized by AP
2006 * during pcpu setup.
2008 load_cr4(rcr4() | CR4_PCIDE);
2013 * Setup the PAT MSR.
2022 /* Bail if this CPU doesn't implement PAT. */
2023 if ((cpu_feature & CPUID_PAT) == 0)
2026 /* Set default PAT index table. */
2027 for (i = 0; i < PAT_INDEX_SIZE; i++)
2029 pat_index[PAT_WRITE_BACK] = 0;
2030 pat_index[PAT_WRITE_THROUGH] = 1;
2031 pat_index[PAT_UNCACHEABLE] = 3;
2032 pat_index[PAT_WRITE_COMBINING] = 6;
2033 pat_index[PAT_WRITE_PROTECTED] = 5;
2034 pat_index[PAT_UNCACHED] = 2;
2037 * Initialize default PAT entries.
2038 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
2039 * Program 5 and 6 as WP and WC.
2041 * Leave 4 and 7 as WB and UC. Note that a recursive page table
2042 * mapping for a 2M page uses a PAT value with the bit 3 set due
2043 * to its overload with PG_PS.
2045 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
2046 PAT_VALUE(1, PAT_WRITE_THROUGH) |
2047 PAT_VALUE(2, PAT_UNCACHED) |
2048 PAT_VALUE(3, PAT_UNCACHEABLE) |
2049 PAT_VALUE(4, PAT_WRITE_BACK) |
2050 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
2051 PAT_VALUE(6, PAT_WRITE_COMBINING) |
2052 PAT_VALUE(7, PAT_UNCACHEABLE);
2056 load_cr4(cr4 & ~CR4_PGE);
2058 /* Disable caches (CD = 1, NW = 0). */
2060 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
2062 /* Flushes caches and TLBs. */
2066 /* Update PAT and index table. */
2067 wrmsr(MSR_PAT, pat_msr);
2069 /* Flush caches and TLBs again. */
2073 /* Restore caches and PGE. */
2079 pmap_page_alloc_below_4g(bool zeroed)
2081 return (vm_page_alloc_noobj_contig((zeroed ? VM_ALLOC_ZERO : 0),
2082 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT));
2085 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
2086 la57_trampoline_gdt[], la57_trampoline_end[];
2089 pmap_bootstrap_la57(void *arg __unused)
2092 pml5_entry_t *v_pml5;
2093 pml4_entry_t *v_pml4;
2097 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2098 void (*la57_tramp)(uint64_t pml5);
2099 struct region_descriptor r_gdt;
2101 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2103 TUNABLE_INT_FETCH("vm.pmap.la57", &la57);
2107 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2108 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2110 m_code = pmap_page_alloc_below_4g(true);
2111 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2112 m_pml5 = pmap_page_alloc_below_4g(true);
2113 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2114 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2115 m_pml4 = pmap_page_alloc_below_4g(true);
2116 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2117 m_pdp = pmap_page_alloc_below_4g(true);
2118 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2119 m_pd = pmap_page_alloc_below_4g(true);
2120 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2121 m_pt = pmap_page_alloc_below_4g(true);
2122 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2125 * Map m_code 1:1, it appears below 4G in KVA due to physical
2126 * address being below 4G. Since kernel KVA is in upper half,
2127 * the pml4e should be zero and free for temporary use.
2129 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2130 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2132 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2133 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2135 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2136 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2138 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2139 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2143 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2144 * entering all existing kernel mappings into level 5 table.
2146 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2147 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2150 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2152 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2153 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2155 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2156 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2160 * Copy and call the 48->57 trampoline, hope we return there, alive.
2162 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2163 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2164 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2165 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2166 invlpg((vm_offset_t)la57_tramp);
2167 la57_tramp(KPML5phys);
2170 * gdt was necessary reset, switch back to our gdt.
2173 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2177 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2178 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2179 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2182 * Now unmap the trampoline, and free the pages.
2183 * Clear pml5 entry used for 1:1 trampoline mapping.
2185 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2186 invlpg((vm_offset_t)v_code);
2187 vm_page_free(m_code);
2188 vm_page_free(m_pdp);
2193 * Recursively map PML5 to itself in order to get PTmap and
2196 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2198 vtoptem = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
2199 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1) << 3;
2200 PTmap = (vm_offset_t)P5Tmap;
2201 vtopdem = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
2202 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1) << 3;
2203 PDmap = (vm_offset_t)P5Dmap;
2205 kernel_pmap->pm_cr3 = KPML5phys;
2206 kernel_pmap->pm_pmltop = v_pml5;
2207 pmap_pt_page_count_adj(kernel_pmap, 1);
2209 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2212 * Initialize a vm_page's machine-dependent fields.
2215 pmap_page_init(vm_page_t m)
2218 TAILQ_INIT(&m->md.pv_list);
2219 m->md.pat_mode = PAT_WRITE_BACK;
2222 static int pmap_allow_2m_x_ept;
2223 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2224 &pmap_allow_2m_x_ept, 0,
2225 "Allow executable superpage mappings in EPT");
2228 pmap_allow_2m_x_ept_recalculate(void)
2231 * SKL002, SKL012S. Since the EPT format is only used by
2232 * Intel CPUs, the vendor check is merely a formality.
2234 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2235 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2236 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2237 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2238 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2239 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2240 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2241 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2242 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2243 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2244 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2245 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2246 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2247 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2248 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2249 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2250 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2251 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2252 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2253 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2254 CPUID_TO_MODEL(cpu_id) == 0x85))))
2255 pmap_allow_2m_x_ept = 1;
2256 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2260 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2263 return (pmap->pm_type != PT_EPT || !executable ||
2264 !pmap_allow_2m_x_ept);
2269 pmap_init_pv_table(void)
2271 struct pmap_large_md_page *pvd;
2273 long start, end, highest, pv_npg;
2274 int domain, i, j, pages;
2277 * We strongly depend on the size being a power of two, so the assert
2278 * is overzealous. However, should the struct be resized to a
2279 * different power of two, the code below needs to be revisited.
2281 CTASSERT((sizeof(*pvd) == 64));
2284 * Calculate the size of the array.
2286 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2287 pv_npg = howmany(pmap_last_pa, NBPDR);
2288 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2290 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2291 if (pv_table == NULL)
2292 panic("%s: kva_alloc failed\n", __func__);
2295 * Iterate physical segments to allocate space for respective pages.
2299 for (i = 0; i < vm_phys_nsegs; i++) {
2300 end = vm_phys_segs[i].end / NBPDR;
2301 domain = vm_phys_segs[i].domain;
2306 start = highest + 1;
2307 pvd = &pv_table[start];
2309 pages = end - start + 1;
2310 s = round_page(pages * sizeof(*pvd));
2311 highest = start + (s / sizeof(*pvd)) - 1;
2313 for (j = 0; j < s; j += PAGE_SIZE) {
2314 vm_page_t m = vm_page_alloc_noobj_domain(domain, 0);
2316 panic("failed to allocate PV table page");
2317 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2320 for (j = 0; j < s / sizeof(*pvd); j++) {
2321 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2322 TAILQ_INIT(&pvd->pv_page.pv_list);
2323 pvd->pv_page.pv_gen = 0;
2324 pvd->pv_page.pat_mode = 0;
2325 pvd->pv_invl_gen = 0;
2329 pvd = &pv_dummy_large;
2330 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2331 TAILQ_INIT(&pvd->pv_page.pv_list);
2332 pvd->pv_page.pv_gen = 0;
2333 pvd->pv_page.pat_mode = 0;
2334 pvd->pv_invl_gen = 0;
2338 pmap_init_pv_table(void)
2344 * Initialize the pool of pv list locks.
2346 for (i = 0; i < NPV_LIST_LOCKS; i++)
2347 rw_init(&pv_list_locks[i], "pmap pv list");
2350 * Calculate the size of the pv head table for superpages.
2352 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2355 * Allocate memory for the pv head table for superpages.
2357 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2359 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2360 for (i = 0; i < pv_npg; i++)
2361 TAILQ_INIT(&pv_table[i].pv_list);
2362 TAILQ_INIT(&pv_dummy.pv_list);
2367 * Initialize the pmap module.
2368 * Called by vm_init, to initialize any structures that the pmap
2369 * system needs to map virtual memory.
2374 struct pmap_preinit_mapping *ppim;
2376 int error, i, ret, skz63;
2378 /* L1TF, reserve page @0 unconditionally */
2379 vm_page_blacklist_add(0, bootverbose);
2381 /* Detect bare-metal Skylake Server and Skylake-X. */
2382 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2383 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2385 * Skylake-X errata SKZ63. Processor May Hang When
2386 * Executing Code In an HLE Transaction Region between
2387 * 40000000H and 403FFFFFH.
2389 * Mark the pages in the range as preallocated. It
2390 * seems to be impossible to distinguish between
2391 * Skylake Server and Skylake X.
2394 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2397 printf("SKZ63: skipping 4M RAM starting "
2398 "at physical 1G\n");
2399 for (i = 0; i < atop(0x400000); i++) {
2400 ret = vm_page_blacklist_add(0x40000000 +
2402 if (!ret && bootverbose)
2403 printf("page at %#lx already used\n",
2404 0x40000000 + ptoa(i));
2410 pmap_allow_2m_x_ept_recalculate();
2413 * Initialize the vm page array entries for the kernel pmap's
2416 PMAP_LOCK(kernel_pmap);
2417 for (i = 0; i < nkpt; i++) {
2418 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2419 KASSERT(mpte >= vm_page_array &&
2420 mpte < &vm_page_array[vm_page_array_size],
2421 ("pmap_init: page table page is out of range"));
2422 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2423 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2424 mpte->ref_count = 1;
2427 * Collect the page table pages that were replaced by a 2MB
2428 * page in create_pagetables(). They are zero filled.
2431 kernphys + ((vm_paddr_t)(i - 1) << PDRSHIFT) < KERNend) &&
2432 pmap_insert_pt_page(kernel_pmap, mpte, false))
2433 panic("pmap_init: pmap_insert_pt_page failed");
2435 PMAP_UNLOCK(kernel_pmap);
2439 * If the kernel is running on a virtual machine, then it must assume
2440 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2441 * be prepared for the hypervisor changing the vendor and family that
2442 * are reported by CPUID. Consequently, the workaround for AMD Family
2443 * 10h Erratum 383 is enabled if the processor's feature set does not
2444 * include at least one feature that is only supported by older Intel
2445 * or newer AMD processors.
2447 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2448 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2449 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2451 workaround_erratum383 = 1;
2454 * Are large page mappings enabled?
2456 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2457 if (pg_ps_enabled) {
2458 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2459 ("pmap_init: can't assign to pagesizes[1]"));
2460 pagesizes[1] = NBPDR;
2461 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2462 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2463 ("pmap_init: can't assign to pagesizes[2]"));
2464 pagesizes[2] = NBPDP;
2469 * Initialize pv chunk lists.
2471 for (i = 0; i < PMAP_MEMDOM; i++) {
2472 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2473 TAILQ_INIT(&pv_chunks[i].pvc_list);
2475 pmap_init_pv_table();
2477 pmap_initialized = 1;
2478 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2479 ppim = pmap_preinit_mapping + i;
2482 /* Make the direct map consistent */
2483 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2484 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2485 ppim->sz, ppim->mode);
2489 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2490 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2493 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2494 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2495 (vmem_addr_t *)&qframe);
2497 panic("qframe allocation failed");
2500 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2501 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2502 lm_ents = LMEPML4I - LMSPML4I + 1;
2504 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2505 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2507 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2508 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2509 if (large_vmem == NULL) {
2510 printf("pmap: cannot create large map\n");
2513 for (i = 0; i < lm_ents; i++) {
2514 m = pmap_large_map_getptp_unlocked();
2516 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2517 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2523 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2524 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2525 "Maximum number of PML4 entries for use by large map (tunable). "
2526 "Each entry corresponds to 512GB of address space.");
2528 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2529 "2MB page mapping counters");
2531 static COUNTER_U64_DEFINE_EARLY(pmap_pde_demotions);
2532 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, demotions,
2533 CTLFLAG_RD, &pmap_pde_demotions, "2MB page demotions");
2535 static COUNTER_U64_DEFINE_EARLY(pmap_pde_mappings);
2536 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2537 &pmap_pde_mappings, "2MB page mappings");
2539 static COUNTER_U64_DEFINE_EARLY(pmap_pde_p_failures);
2540 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2541 &pmap_pde_p_failures, "2MB page promotion failures");
2543 static COUNTER_U64_DEFINE_EARLY(pmap_pde_promotions);
2544 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2545 &pmap_pde_promotions, "2MB page promotions");
2547 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2548 "1GB page mapping counters");
2550 static COUNTER_U64_DEFINE_EARLY(pmap_pdpe_demotions);
2551 SYSCTL_COUNTER_U64(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2552 &pmap_pdpe_demotions, "1GB page demotions");
2554 /***************************************************
2555 * Low level helper routines.....
2556 ***************************************************/
2559 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2561 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2563 switch (pmap->pm_type) {
2566 /* Verify that both PAT bits are not set at the same time */
2567 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2568 ("Invalid PAT bits in entry %#lx", entry));
2570 /* Swap the PAT bits if one of them is set */
2571 if ((entry & x86_pat_bits) != 0)
2572 entry ^= x86_pat_bits;
2576 * Nothing to do - the memory attributes are represented
2577 * the same way for regular pages and superpages.
2581 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2588 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2591 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2592 pat_index[(int)mode] >= 0);
2596 * Determine the appropriate bits to set in a PTE or PDE for a specified
2600 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2602 int cache_bits, pat_flag, pat_idx;
2604 if (!pmap_is_valid_memattr(pmap, mode))
2605 panic("Unknown caching mode %d\n", mode);
2607 switch (pmap->pm_type) {
2610 /* The PAT bit is different for PTE's and PDE's. */
2611 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2613 /* Map the caching mode to a PAT index. */
2614 pat_idx = pat_index[mode];
2616 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2619 cache_bits |= pat_flag;
2621 cache_bits |= PG_NC_PCD;
2623 cache_bits |= PG_NC_PWT;
2627 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2631 panic("unsupported pmap type %d", pmap->pm_type);
2634 return (cache_bits);
2638 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2642 switch (pmap->pm_type) {
2645 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2648 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2651 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2658 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2660 int pat_flag, pat_idx;
2663 switch (pmap->pm_type) {
2666 /* The PAT bit is different for PTE's and PDE's. */
2667 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2669 if ((pte & pat_flag) != 0)
2671 if ((pte & PG_NC_PCD) != 0)
2673 if ((pte & PG_NC_PWT) != 0)
2677 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2678 panic("EPT PTE %#lx has no PAT memory type", pte);
2679 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2683 /* See pmap_init_pat(). */
2693 pmap_ps_enabled(pmap_t pmap)
2696 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2700 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2703 switch (pmap->pm_type) {
2710 * This is a little bogus since the generation number is
2711 * supposed to be bumped up when a region of the address
2712 * space is invalidated in the page tables.
2714 * In this case the old PDE entry is valid but yet we want
2715 * to make sure that any mappings using the old entry are
2716 * invalidated in the TLB.
2718 * The reason this works as expected is because we rendezvous
2719 * "all" host cpus and force any vcpu context to exit as a
2722 atomic_add_long(&pmap->pm_eptgen, 1);
2725 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2727 pde_store(pde, newpde);
2731 * After changing the page size for the specified virtual address in the page
2732 * table, flush the corresponding entries from the processor's TLB. Only the
2733 * calling processor's TLB is affected.
2735 * The calling thread must be pinned to a processor.
2738 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2742 if (pmap_type_guest(pmap))
2745 KASSERT(pmap->pm_type == PT_X86,
2746 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2748 PG_G = pmap_global_bit(pmap);
2750 if ((newpde & PG_PS) == 0)
2751 /* Demotion: flush a specific 2MB page mapping. */
2753 else if ((newpde & PG_G) == 0)
2755 * Promotion: flush every 4KB page mapping from the TLB
2756 * because there are too many to flush individually.
2761 * Promotion: flush every 4KB page mapping from the TLB,
2762 * including any global (PG_G) mappings.
2769 * The amd64 pmap uses different approaches to TLB invalidation
2770 * depending on the kernel configuration, available hardware features,
2771 * and known hardware errata. The kernel configuration option that
2772 * has the greatest operational impact on TLB invalidation is PTI,
2773 * which is enabled automatically on affected Intel CPUs. The most
2774 * impactful hardware features are first PCID, and then INVPCID
2775 * instruction presence. PCID usage is quite different for PTI
2778 * * Kernel Page Table Isolation (PTI or KPTI) is used to mitigate
2779 * the Meltdown bug in some Intel CPUs. Under PTI, each user address
2780 * space is served by two page tables, user and kernel. The user
2781 * page table only maps user space and a kernel trampoline. The
2782 * kernel trampoline includes the entirety of the kernel text but
2783 * only the kernel data that is needed to switch from user to kernel
2784 * mode. The kernel page table maps the user and kernel address
2785 * spaces in their entirety. It is identical to the per-process
2786 * page table used in non-PTI mode.
2788 * User page tables are only used when the CPU is in user mode.
2789 * Consequently, some TLB invalidations can be postponed until the
2790 * switch from kernel to user mode. In contrast, the user
2791 * space part of the kernel page table is used for copyout(9), so
2792 * TLB invalidations on this page table cannot be similarly postponed.
2794 * The existence of a user mode page table for the given pmap is
2795 * indicated by a pm_ucr3 value that differs from PMAP_NO_CR3, in
2796 * which case pm_ucr3 contains the %cr3 register value for the user
2797 * mode page table's root.
2799 * * The pm_active bitmask indicates which CPUs currently have the
2800 * pmap active. A CPU's bit is set on context switch to the pmap, and
2801 * cleared on switching off this CPU. For the kernel page table,
2802 * the pm_active field is immutable and contains all CPUs. The
2803 * kernel page table is always logically active on every processor,
2804 * but not necessarily in use by the hardware, e.g., in PTI mode.
2806 * When requesting invalidation of virtual addresses with
2807 * pmap_invalidate_XXX() functions, the pmap sends shootdown IPIs to
2808 * all CPUs recorded as active in pm_active. Updates to and reads
2809 * from pm_active are not synchronized, and so they may race with
2810 * each other. Shootdown handlers are prepared to handle the race.
2812 * * PCID is an optional feature of the long mode x86 MMU where TLB
2813 * entries are tagged with the 'Process ID' of the address space
2814 * they belong to. This feature provides a limited namespace for
2815 * process identifiers, 12 bits, supporting 4095 simultaneous IDs
2818 * Allocation of a PCID to a pmap is done by an algorithm described
2819 * in section 15.12, "Other TLB Consistency Algorithms", of
2820 * Vahalia's book "Unix Internals". A PCID cannot be allocated for
2821 * the whole lifetime of a pmap in pmap_pinit() due to the limited
2822 * namespace. Instead, a per-CPU, per-pmap PCID is assigned when
2823 * the CPU is about to start caching TLB entries from a pmap,
2824 * i.e., on the context switch that activates the pmap on the CPU.
2826 * The PCID allocator maintains a per-CPU, per-pmap generation
2827 * count, pm_gen, which is incremented each time a new PCID is
2828 * allocated. On TLB invalidation, the generation counters for the
2829 * pmap are zeroed, which signals the context switch code that the
2830 * previously allocated PCID is no longer valid. Effectively,
2831 * zeroing any of these counters triggers a TLB shootdown for the
2832 * given CPU/address space, due to the allocation of a new PCID.
2834 * Zeroing can be performed remotely. Consequently, if a pmap is
2835 * inactive on a CPU, then a TLB shootdown for that pmap and CPU can
2836 * be initiated by an ordinary memory access to reset the target
2837 * CPU's generation count within the pmap. The CPU initiating the
2838 * TLB shootdown does not need to send an IPI to the target CPU.
2840 * * PTI + PCID. The available PCIDs are divided into two sets: PCIDs
2841 * for complete (kernel) page tables, and PCIDs for user mode page
2842 * tables. A user PCID value is obtained from the kernel PCID value
2843 * by setting the highest bit, 11, to 1 (0x800 == PMAP_PCID_USER_PT).
2845 * User space page tables are activated on return to user mode, by
2846 * loading pm_ucr3 into %cr3. If the PCPU(ucr3_load_mask) requests
2847 * clearing bit 63 of the loaded ucr3, this effectively causes
2848 * complete invalidation of the user mode TLB entries for the
2849 * current pmap. In which case, local invalidations of individual
2850 * pages in the user page table are skipped.
2852 * * Local invalidation, all modes. If the requested invalidation is
2853 * for a specific address or the total invalidation of a currently
2854 * active pmap, then the TLB is flushed using INVLPG for a kernel
2855 * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a
2856 * user space page table(s).
2858 * If the INVPCID instruction is available, it is used to flush entries
2859 * from the kernel page table.
2861 * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its
2862 * address space, all other 4095 PCIDs are used for user mode spaces
2863 * as described above. A context switch allocates a new PCID if
2864 * the recorded PCID is zero or the recorded generation does not match
2865 * the CPU's generation, effectively flushing the TLB for this address space.
2866 * Total remote invalidation is performed by zeroing pm_gen for all CPUs.
2867 * local user page: INVLPG
2868 * local kernel page: INVLPG
2869 * local user total: INVPCID(CTX)
2870 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2871 * remote user page, inactive pmap: zero pm_gen
2872 * remote user page, active pmap: zero pm_gen + IPI:INVLPG
2873 * (Both actions are required to handle the aforementioned pm_active races.)
2874 * remote kernel page: IPI:INVLPG
2875 * remote user total, inactive pmap: zero pm_gen
2876 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) or
2878 * (See note above about pm_active races.)
2879 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2881 * PTI enabled, PCID present.
2882 * local user page: INVLPG for kpt, INVPCID(ADDR) or (INVLPG for ucr3)
2884 * local kernel page: INVLPG
2885 * local user total: INVPCID(CTX) or reload %cr3 for kpt, clear PCID_SAVE
2886 * on loading UCR3 into %cr3 for upt
2887 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2888 * remote user page, inactive pmap: zero pm_gen
2889 * remote user page, active pmap: zero pm_gen + IPI:(INVLPG for kpt,
2890 * INVPCID(ADDR) for upt)
2891 * remote kernel page: IPI:INVLPG
2892 * remote user total, inactive pmap: zero pm_gen
2893 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) for kpt,
2894 * clear PCID_SAVE on loading UCR3 into $cr3 for upt)
2895 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2898 * local user page: INVLPG
2899 * local kernel page: INVLPG
2900 * local user total: reload %cr3
2901 * local kernel total: invltlb_glob()
2902 * remote user page, inactive pmap: -
2903 * remote user page, active pmap: IPI:INVLPG
2904 * remote kernel page: IPI:INVLPG
2905 * remote user total, inactive pmap: -
2906 * remote user total, active pmap: IPI:(reload %cr3)
2907 * remote kernel total: IPI:invltlb_glob()
2908 * Since on return to user mode, the reload of %cr3 with ucr3 causes
2909 * TLB invalidation, no specific action is required for user page table.
2911 * EPT. EPT pmaps do not map KVA, all mappings are userspace.
2917 * Interrupt the cpus that are executing in the guest context.
2918 * This will force the vcpu to exit and the cached EPT mappings
2919 * will be invalidated by the host before the next vmresume.
2921 static __inline void
2922 pmap_invalidate_ept(pmap_t pmap)
2928 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2929 ("pmap_invalidate_ept: absurd pm_active"));
2932 * The TLB mappings associated with a vcpu context are not
2933 * flushed each time a different vcpu is chosen to execute.
2935 * This is in contrast with a process's vtop mappings that
2936 * are flushed from the TLB on each context switch.
2938 * Therefore we need to do more than just a TLB shootdown on
2939 * the active cpus in 'pmap->pm_active'. To do this we keep
2940 * track of the number of invalidations performed on this pmap.
2942 * Each vcpu keeps a cache of this counter and compares it
2943 * just before a vmresume. If the counter is out-of-date an
2944 * invept will be done to flush stale mappings from the TLB.
2946 * To ensure that all vCPU threads have observed the new counter
2947 * value before returning, we use SMR. Ordering is important here:
2948 * the VMM enters an SMR read section before loading the counter
2949 * and after updating the pm_active bit set. Thus, pm_active is
2950 * a superset of active readers, and any reader that has observed
2951 * the goal has observed the new counter value.
2953 atomic_add_long(&pmap->pm_eptgen, 1);
2955 goal = smr_advance(pmap->pm_eptsmr);
2958 * Force the vcpu to exit and trap back into the hypervisor.
2960 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2961 ipi_selected(pmap->pm_active, ipinum);
2965 * Ensure that all active vCPUs will observe the new generation counter
2966 * value before executing any more guest instructions.
2968 smr_wait(pmap->pm_eptsmr, goal);
2972 pmap_invalidate_preipi_pcid(pmap_t pmap)
2978 cpuid = PCPU_GET(cpuid);
2979 if (pmap != PCPU_GET(curpmap))
2980 cpuid = 0xffffffff; /* An impossible value */
2984 pmap->pm_pcids[i].pm_gen = 0;
2988 * The fence is between stores to pm_gen and the read of the
2989 * pm_active mask. We need to ensure that it is impossible
2990 * for us to miss the bit update in pm_active and
2991 * simultaneously observe a non-zero pm_gen in
2992 * pmap_activate_sw(), otherwise TLB update is missed.
2993 * Without the fence, IA32 allows such an outcome. Note that
2994 * pm_active is updated by a locked operation, which provides
2995 * the reciprocal fence.
2997 atomic_thread_fence_seq_cst();
3001 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
3006 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t))
3008 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
3009 pmap_invalidate_preipi_nopcid);
3013 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
3014 const bool invpcid_works1)
3016 struct invpcid_descr d;
3017 uint64_t kcr3, ucr3;
3022 * Because pm_pcid is recalculated on a context switch, we
3023 * must ensure there is no preemption, not just pinning.
3024 * Otherwise, we might use a stale value below.
3026 CRITICAL_ASSERT(curthread);
3029 * No need to do anything with user page tables invalidation
3030 * if there is no user page table, or invalidation is deferred
3031 * until the return to userspace. ucr3_load_mask is stable
3032 * because we have preemption disabled.
3034 if (pmap->pm_ucr3 == PMAP_NO_CR3 ||
3035 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3038 cpuid = PCPU_GET(cpuid);
3040 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3041 if (invpcid_works1) {
3042 d.pcid = pcid | PMAP_PCID_USER_PT;
3045 invpcid(&d, INVPCID_ADDR);
3047 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3048 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3049 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3054 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
3056 pmap_invalidate_page_pcid_cb(pmap, va, true);
3060 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
3062 pmap_invalidate_page_pcid_cb(pmap, va, false);
3066 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
3070 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t))
3072 if (pmap_pcid_enabled)
3073 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
3074 pmap_invalidate_page_pcid_noinvpcid_cb);
3075 return (pmap_invalidate_page_nopcid_cb);
3079 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
3080 vm_offset_t addr2 __unused)
3082 if (pmap == kernel_pmap) {
3084 } else if (pmap == PCPU_GET(curpmap)) {
3086 pmap_invalidate_page_cb(pmap, va);
3091 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3093 if (pmap_type_guest(pmap)) {
3094 pmap_invalidate_ept(pmap);
3098 KASSERT(pmap->pm_type == PT_X86,
3099 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
3101 pmap_invalidate_preipi(pmap);
3102 smp_masked_invlpg(va, pmap, pmap_invalidate_page_curcpu_cb);
3105 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
3106 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
3109 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3110 const bool invpcid_works1)
3112 struct invpcid_descr d;
3113 uint64_t kcr3, ucr3;
3117 CRITICAL_ASSERT(curthread);
3119 if (pmap != PCPU_GET(curpmap) ||
3120 pmap->pm_ucr3 == PMAP_NO_CR3 ||
3121 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3124 cpuid = PCPU_GET(cpuid);
3126 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3127 if (invpcid_works1) {
3128 d.pcid = pcid | PMAP_PCID_USER_PT;
3130 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
3131 invpcid(&d, INVPCID_ADDR);
3133 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3134 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3135 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3140 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
3143 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
3147 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
3150 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
3154 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
3155 vm_offset_t eva __unused)
3159 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
3162 if (pmap_pcid_enabled)
3163 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
3164 pmap_invalidate_range_pcid_noinvpcid_cb);
3165 return (pmap_invalidate_range_nopcid_cb);
3169 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3173 if (pmap == kernel_pmap) {
3174 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3176 } else if (pmap == PCPU_GET(curpmap)) {
3177 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3179 pmap_invalidate_range_cb(pmap, sva, eva);
3184 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3186 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
3187 pmap_invalidate_all(pmap);
3191 if (pmap_type_guest(pmap)) {
3192 pmap_invalidate_ept(pmap);
3196 KASSERT(pmap->pm_type == PT_X86,
3197 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3199 pmap_invalidate_preipi(pmap);
3200 smp_masked_invlpg_range(sva, eva, pmap,
3201 pmap_invalidate_range_curcpu_cb);
3205 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
3207 struct invpcid_descr d;
3212 if (pmap == kernel_pmap) {
3213 if (invpcid_works1) {
3214 bzero(&d, sizeof(d));
3215 invpcid(&d, INVPCID_CTXGLOB);
3219 } else if (pmap == PCPU_GET(curpmap)) {
3220 CRITICAL_ASSERT(curthread);
3221 cpuid = PCPU_GET(cpuid);
3223 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3224 if (invpcid_works1) {
3228 invpcid(&d, INVPCID_CTX);
3230 kcr3 = pmap->pm_cr3 | pcid;
3233 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3234 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3239 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
3241 pmap_invalidate_all_pcid_cb(pmap, true);
3245 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
3247 pmap_invalidate_all_pcid_cb(pmap, false);
3251 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
3253 if (pmap == kernel_pmap)
3255 else if (pmap == PCPU_GET(curpmap))
3259 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t))
3261 if (pmap_pcid_enabled)
3262 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
3263 pmap_invalidate_all_pcid_noinvpcid_cb);
3264 return (pmap_invalidate_all_nopcid_cb);
3268 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3269 vm_offset_t addr2 __unused)
3271 pmap_invalidate_all_cb(pmap);
3275 pmap_invalidate_all(pmap_t pmap)
3277 if (pmap_type_guest(pmap)) {
3278 pmap_invalidate_ept(pmap);
3282 KASSERT(pmap->pm_type == PT_X86,
3283 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3285 pmap_invalidate_preipi(pmap);
3286 smp_masked_invltlb(pmap, pmap_invalidate_all_curcpu_cb);
3290 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3291 vm_offset_t addr2 __unused)
3297 pmap_invalidate_cache(void)
3300 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3304 cpuset_t invalidate; /* processors that invalidate their TLB */
3309 u_int store; /* processor that updates the PDE */
3313 pmap_update_pde_action(void *arg)
3315 struct pde_action *act = arg;
3317 if (act->store == PCPU_GET(cpuid))
3318 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3322 pmap_update_pde_teardown(void *arg)
3324 struct pde_action *act = arg;
3326 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3327 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3331 * Change the page size for the specified virtual address in a way that
3332 * prevents any possibility of the TLB ever having two entries that map the
3333 * same virtual address using different page sizes. This is the recommended
3334 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3335 * machine check exception for a TLB state that is improperly diagnosed as a
3339 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3341 struct pde_action act;
3342 cpuset_t active, other_cpus;
3346 cpuid = PCPU_GET(cpuid);
3347 other_cpus = all_cpus;
3348 CPU_CLR(cpuid, &other_cpus);
3349 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3352 active = pmap->pm_active;
3354 if (CPU_OVERLAP(&active, &other_cpus)) {
3356 act.invalidate = active;
3360 act.newpde = newpde;
3361 CPU_SET(cpuid, &active);
3362 smp_rendezvous_cpus(active,
3363 smp_no_rendezvous_barrier, pmap_update_pde_action,
3364 pmap_update_pde_teardown, &act);
3366 pmap_update_pde_store(pmap, pde, newpde);
3367 if (CPU_ISSET(cpuid, &active))
3368 pmap_update_pde_invalidate(pmap, va, newpde);
3374 * Normal, non-SMP, invalidation functions.
3377 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3379 struct invpcid_descr d;
3380 uint64_t kcr3, ucr3;
3383 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3387 KASSERT(pmap->pm_type == PT_X86,
3388 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3390 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3392 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3393 pmap->pm_ucr3 != PMAP_NO_CR3) {
3395 pcid = pmap->pm_pcids[0].pm_pcid;
3396 if (invpcid_works) {
3397 d.pcid = pcid | PMAP_PCID_USER_PT;
3400 invpcid(&d, INVPCID_ADDR);
3402 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3403 ucr3 = pmap->pm_ucr3 | pcid |
3404 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3405 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3409 } else if (pmap_pcid_enabled)
3410 pmap->pm_pcids[0].pm_gen = 0;
3414 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3416 struct invpcid_descr d;
3418 uint64_t kcr3, ucr3;
3420 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3424 KASSERT(pmap->pm_type == PT_X86,
3425 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3427 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3428 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3430 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3431 pmap->pm_ucr3 != PMAP_NO_CR3) {
3433 if (invpcid_works) {
3434 d.pcid = pmap->pm_pcids[0].pm_pcid |
3438 for (; d.addr < eva; d.addr += PAGE_SIZE)
3439 invpcid(&d, INVPCID_ADDR);
3441 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3442 pm_pcid | CR3_PCID_SAVE;
3443 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3444 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3445 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3449 } else if (pmap_pcid_enabled) {
3450 pmap->pm_pcids[0].pm_gen = 0;
3455 pmap_invalidate_all(pmap_t pmap)
3457 struct invpcid_descr d;
3458 uint64_t kcr3, ucr3;
3460 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3464 KASSERT(pmap->pm_type == PT_X86,
3465 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3467 if (pmap == kernel_pmap) {
3468 if (pmap_pcid_enabled && invpcid_works) {
3469 bzero(&d, sizeof(d));
3470 invpcid(&d, INVPCID_CTXGLOB);
3474 } else if (pmap == PCPU_GET(curpmap)) {
3475 if (pmap_pcid_enabled) {
3477 if (invpcid_works) {
3478 d.pcid = pmap->pm_pcids[0].pm_pcid;
3481 invpcid(&d, INVPCID_CTX);
3482 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3483 d.pcid |= PMAP_PCID_USER_PT;
3484 invpcid(&d, INVPCID_CTX);
3487 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3488 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3489 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3490 0].pm_pcid | PMAP_PCID_USER_PT;
3491 pmap_pti_pcid_invalidate(ucr3, kcr3);
3499 } else if (pmap_pcid_enabled) {
3500 pmap->pm_pcids[0].pm_gen = 0;
3505 pmap_invalidate_cache(void)
3512 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3515 pmap_update_pde_store(pmap, pde, newpde);
3516 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3517 pmap_update_pde_invalidate(pmap, va, newpde);
3519 pmap->pm_pcids[0].pm_gen = 0;
3524 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3528 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3529 * by a promotion that did not invalidate the 512 4KB page mappings
3530 * that might exist in the TLB. Consequently, at this point, the TLB
3531 * may hold both 4KB and 2MB page mappings for the address range [va,
3532 * va + NBPDR). Therefore, the entire range must be invalidated here.
3533 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3534 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3535 * single INVLPG suffices to invalidate the 2MB page mapping from the
3538 if ((pde & PG_PROMOTED) != 0)
3539 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3541 pmap_invalidate_page(pmap, va);
3544 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3545 (vm_offset_t sva, vm_offset_t eva))
3548 if ((cpu_feature & CPUID_SS) != 0)
3549 return (pmap_invalidate_cache_range_selfsnoop);
3550 if ((cpu_feature & CPUID_CLFSH) != 0)
3551 return (pmap_force_invalidate_cache_range);
3552 return (pmap_invalidate_cache_range_all);
3555 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3558 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3561 KASSERT((sva & PAGE_MASK) == 0,
3562 ("pmap_invalidate_cache_range: sva not page-aligned"));
3563 KASSERT((eva & PAGE_MASK) == 0,
3564 ("pmap_invalidate_cache_range: eva not page-aligned"));
3568 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3571 pmap_invalidate_cache_range_check_align(sva, eva);
3575 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3578 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3581 * XXX: Some CPUs fault, hang, or trash the local APIC
3582 * registers if we use CLFLUSH on the local APIC range. The
3583 * local APIC is always uncached, so we don't need to flush
3584 * for that range anyway.
3586 if (pmap_kextract(sva) == lapic_paddr)
3589 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3591 * Do per-cache line flush. Use a locked
3592 * instruction to insure that previous stores are
3593 * included in the write-back. The processor
3594 * propagates flush to other processors in the cache
3597 atomic_thread_fence_seq_cst();
3598 for (; sva < eva; sva += cpu_clflush_line_size)
3600 atomic_thread_fence_seq_cst();
3603 * Writes are ordered by CLFLUSH on Intel CPUs.
3605 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3607 for (; sva < eva; sva += cpu_clflush_line_size)
3609 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3615 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3618 pmap_invalidate_cache_range_check_align(sva, eva);
3619 pmap_invalidate_cache();
3623 * Remove the specified set of pages from the data and instruction caches.
3625 * In contrast to pmap_invalidate_cache_range(), this function does not
3626 * rely on the CPU's self-snoop feature, because it is intended for use
3627 * when moving pages into a different cache domain.
3630 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3632 vm_offset_t daddr, eva;
3636 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3637 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3638 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3639 pmap_invalidate_cache();
3642 atomic_thread_fence_seq_cst();
3643 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3645 for (i = 0; i < count; i++) {
3646 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3647 eva = daddr + PAGE_SIZE;
3648 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3656 atomic_thread_fence_seq_cst();
3657 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3663 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3666 pmap_invalidate_cache_range_check_align(sva, eva);
3668 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3669 pmap_force_invalidate_cache_range(sva, eva);
3673 /* See comment in pmap_force_invalidate_cache_range(). */
3674 if (pmap_kextract(sva) == lapic_paddr)
3677 atomic_thread_fence_seq_cst();
3678 for (; sva < eva; sva += cpu_clflush_line_size)
3680 atomic_thread_fence_seq_cst();
3684 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3688 int error, pte_bits;
3690 KASSERT((spa & PAGE_MASK) == 0,
3691 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3692 KASSERT((epa & PAGE_MASK) == 0,
3693 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3695 if (spa < dmaplimit) {
3696 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3698 if (dmaplimit >= epa)
3703 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3705 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3707 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3708 pte = vtopte(vaddr);
3709 for (; spa < epa; spa += PAGE_SIZE) {
3711 pte_store(pte, spa | pte_bits);
3713 /* XXXKIB atomic inside flush_cache_range are excessive */
3714 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3717 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3721 * Routine: pmap_extract
3723 * Extract the physical page address associated
3724 * with the given map/virtual_address pair.
3727 pmap_extract(pmap_t pmap, vm_offset_t va)
3731 pt_entry_t *pte, PG_V;
3735 PG_V = pmap_valid_bit(pmap);
3737 pdpe = pmap_pdpe(pmap, va);
3738 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3739 if ((*pdpe & PG_PS) != 0)
3740 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3742 pde = pmap_pdpe_to_pde(pdpe, va);
3743 if ((*pde & PG_V) != 0) {
3744 if ((*pde & PG_PS) != 0) {
3745 pa = (*pde & PG_PS_FRAME) |
3748 pte = pmap_pde_to_pte(pde, va);
3749 pa = (*pte & PG_FRAME) |
3760 * Routine: pmap_extract_and_hold
3762 * Atomically extract and hold the physical page
3763 * with the given pmap and virtual address pair
3764 * if that mapping permits the given protection.
3767 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3769 pdp_entry_t pdpe, *pdpep;
3770 pd_entry_t pde, *pdep;
3771 pt_entry_t pte, PG_RW, PG_V;
3775 PG_RW = pmap_rw_bit(pmap);
3776 PG_V = pmap_valid_bit(pmap);
3779 pdpep = pmap_pdpe(pmap, va);
3780 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3782 if ((pdpe & PG_PS) != 0) {
3783 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3785 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3789 pdep = pmap_pdpe_to_pde(pdpep, va);
3790 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3792 if ((pde & PG_PS) != 0) {
3793 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3795 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3799 pte = *pmap_pde_to_pte(pdep, va);
3800 if ((pte & PG_V) == 0 ||
3801 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3803 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3806 if (m != NULL && !vm_page_wire_mapped(m))
3814 pmap_kextract(vm_offset_t va)
3819 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3820 pa = DMAP_TO_PHYS(va);
3821 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3822 pa = pmap_large_map_kextract(va);
3826 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3829 * Beware of a concurrent promotion that changes the
3830 * PDE at this point! For example, vtopte() must not
3831 * be used to access the PTE because it would use the
3832 * new PDE. It is, however, safe to use the old PDE
3833 * because the page table page is preserved by the
3836 pa = *pmap_pde_to_pte(&pde, va);
3837 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3843 /***************************************************
3844 * Low level mapping routines.....
3845 ***************************************************/
3848 * Add a wired page to the kva.
3849 * Note: not SMP coherent.
3852 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3857 pte_store(pte, pa | pg_g | pg_nx | X86_PG_A | X86_PG_M |
3858 X86_PG_RW | X86_PG_V);
3861 static __inline void
3862 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3868 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3869 pte_store(pte, pa | pg_g | pg_nx | X86_PG_A | X86_PG_M |
3870 X86_PG_RW | X86_PG_V | cache_bits);
3874 * Remove a page from the kernel pagetables.
3875 * Note: not SMP coherent.
3878 pmap_kremove(vm_offset_t va)
3887 * Used to map a range of physical addresses into kernel
3888 * virtual address space.
3890 * The value passed in '*virt' is a suggested virtual address for
3891 * the mapping. Architectures which can support a direct-mapped
3892 * physical to virtual region can return the appropriate address
3893 * within that region, leaving '*virt' unchanged. Other
3894 * architectures should map the pages starting at '*virt' and
3895 * update '*virt' with the first usable address after the mapped
3899 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3901 return PHYS_TO_DMAP(start);
3905 * Add a list of wired pages to the kva
3906 * this routine is only used for temporary
3907 * kernel mappings that do not need to have
3908 * page modification or references recorded.
3909 * Note that old mappings are simply written
3910 * over. The page *must* be wired.
3911 * Note: SMP coherent. Uses a ranged shootdown IPI.
3914 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3916 pt_entry_t *endpte, oldpte, pa, *pte;
3922 endpte = pte + count;
3923 while (pte < endpte) {
3925 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3926 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3927 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3929 pte_store(pte, pa | pg_g | pg_nx | X86_PG_A |
3930 X86_PG_M | X86_PG_RW | X86_PG_V);
3934 if (__predict_false((oldpte & X86_PG_V) != 0))
3935 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3940 * This routine tears out page mappings from the
3941 * kernel -- it is meant only for temporary mappings.
3942 * Note: SMP coherent. Uses a ranged shootdown IPI.
3945 pmap_qremove(vm_offset_t sva, int count)
3950 while (count-- > 0) {
3951 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3955 pmap_invalidate_range(kernel_pmap, sva, va);
3958 /***************************************************
3959 * Page table page management routines.....
3960 ***************************************************/
3962 * Schedule the specified unused page table page to be freed. Specifically,
3963 * add the page to the specified list of pages that will be released to the
3964 * physical memory manager after the TLB has been updated.
3966 static __inline void
3967 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3968 boolean_t set_PG_ZERO)
3972 m->flags |= PG_ZERO;
3974 m->flags &= ~PG_ZERO;
3975 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3979 * Inserts the specified page table page into the specified pmap's collection
3980 * of idle page table pages. Each of a pmap's page table pages is responsible
3981 * for mapping a distinct range of virtual addresses. The pmap's collection is
3982 * ordered by this virtual address range.
3984 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3987 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3990 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3991 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3992 return (vm_radix_insert(&pmap->pm_root, mpte));
3996 * Removes the page table page mapping the specified virtual address from the
3997 * specified pmap's collection of idle page table pages, and returns it.
3998 * Otherwise, returns NULL if there is no page table page corresponding to the
3999 * specified virtual address.
4001 static __inline vm_page_t
4002 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
4005 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4006 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
4010 * Decrements a page table page's reference count, which is used to record the
4011 * number of valid page table entries within the page. If the reference count
4012 * drops to zero, then the page table page is unmapped. Returns TRUE if the
4013 * page table page was unmapped and FALSE otherwise.
4015 static inline boolean_t
4016 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4020 if (m->ref_count == 0) {
4021 _pmap_unwire_ptp(pmap, va, m, free);
4028 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4034 vm_page_t pdpg, pdppg, pml4pg;
4036 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4039 * unmap the page table page
4041 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
4043 MPASS(pmap_is_la57(pmap));
4044 pml5 = pmap_pml5e(pmap, va);
4046 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
4047 pml5 = pmap_pml5e_u(pmap, va);
4050 } else if (m->pindex >= NUPDE + NUPDPE) {
4052 pml4 = pmap_pml4e(pmap, va);
4054 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4055 va <= VM_MAXUSER_ADDRESS) {
4056 pml4 = pmap_pml4e_u(pmap, va);
4059 } else if (m->pindex >= NUPDE) {
4061 pdp = pmap_pdpe(pmap, va);
4065 pd = pmap_pde(pmap, va);
4068 if (m->pindex < NUPDE) {
4069 /* We just released a PT, unhold the matching PD */
4070 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
4071 pmap_unwire_ptp(pmap, va, pdpg, free);
4072 } else if (m->pindex < NUPDE + NUPDPE) {
4073 /* We just released a PD, unhold the matching PDP */
4074 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
4075 pmap_unwire_ptp(pmap, va, pdppg, free);
4076 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
4077 /* We just released a PDP, unhold the matching PML4 */
4078 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
4079 pmap_unwire_ptp(pmap, va, pml4pg, free);
4082 pmap_pt_page_count_adj(pmap, -1);
4085 * Put page on a list so that it is released after
4086 * *ALL* TLB shootdown is done
4088 pmap_add_delayed_free_list(m, free, TRUE);
4092 * After removing a page table entry, this routine is used to
4093 * conditionally free the page, and manage the reference count.
4096 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
4097 struct spglist *free)
4101 if (va >= VM_MAXUSER_ADDRESS)
4103 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
4104 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
4105 return (pmap_unwire_ptp(pmap, va, mpte, free));
4109 * Release a page table page reference after a failed attempt to create a
4113 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
4115 struct spglist free;
4118 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4120 * Although "va" was never mapped, paging-structure caches
4121 * could nonetheless have entries that refer to the freed
4122 * page table pages. Invalidate those entries.
4124 pmap_invalidate_page(pmap, va);
4125 vm_page_free_pages_toq(&free, true);
4130 pmap_pinit0(pmap_t pmap)
4136 PMAP_LOCK_INIT(pmap);
4137 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
4138 pmap->pm_pmltopu = NULL;
4139 pmap->pm_cr3 = kernel_pmap->pm_cr3;
4140 /* hack to keep pmap_pti_pcid_invalidate() alive */
4141 pmap->pm_ucr3 = PMAP_NO_CR3;
4142 vm_radix_init(&pmap->pm_root);
4143 CPU_ZERO(&pmap->pm_active);
4144 TAILQ_INIT(&pmap->pm_pvchunk);
4145 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4146 pmap->pm_flags = pmap_flags;
4148 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
4149 pmap->pm_pcids[i].pm_gen = 1;
4151 pmap_activate_boot(pmap);
4156 p->p_md.md_flags |= P_MD_KPTI;
4159 pmap_thread_init_invl_gen(td);
4161 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4162 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
4163 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
4169 pmap_pinit_pml4(vm_page_t pml4pg)
4171 pml4_entry_t *pm_pml4;
4174 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
4176 /* Wire in kernel global address entries. */
4177 for (i = 0; i < NKPML4E; i++) {
4178 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
4182 for (i = 0; i < NKASANPML4E; i++) {
4183 pm_pml4[KASANPML4I + i] = (KASANPDPphys + ptoa(i)) | X86_PG_RW |
4187 for (i = 0; i < ndmpdpphys; i++) {
4188 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
4192 /* install self-referential address mapping entry(s) */
4193 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
4194 X86_PG_A | X86_PG_M;
4196 /* install large map entries if configured */
4197 for (i = 0; i < lm_ents; i++)
4198 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4202 pmap_pinit_pml5(vm_page_t pml5pg)
4204 pml5_entry_t *pm_pml5;
4206 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4209 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4210 * entering all existing kernel mappings into level 5 table.
4212 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4213 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4214 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4217 * Install self-referential address mapping entry.
4219 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4220 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4221 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4225 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4227 pml4_entry_t *pm_pml4u;
4230 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4231 for (i = 0; i < NPML4EPG; i++)
4232 pm_pml4u[i] = pti_pml4[i];
4236 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4238 pml5_entry_t *pm_pml5u;
4240 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4244 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4245 * table, entering all kernel mappings needed for usermode
4246 * into level 5 table.
4248 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4249 pmap_kextract((vm_offset_t)pti_pml4) |
4250 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4251 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4254 /* Allocate a page table page and do related bookkeeping */
4256 pmap_alloc_pt_page(pmap_t pmap, vm_pindex_t pindex, int flags)
4260 m = vm_page_alloc_noobj(flags);
4261 if (__predict_false(m == NULL))
4264 pmap_pt_page_count_adj(pmap, 1);
4269 pmap_free_pt_page(pmap_t pmap, vm_page_t m, bool zerofilled)
4272 * This function assumes the page will need to be unwired,
4273 * even though the counterpart allocation in pmap_alloc_pt_page()
4274 * doesn't enforce VM_ALLOC_WIRED. However, all current uses
4275 * of pmap_free_pt_page() require unwiring. The case in which
4276 * a PT page doesn't require unwiring because its ref_count has
4277 * naturally reached 0 is handled through _pmap_unwire_ptp().
4279 vm_page_unwire_noq(m);
4281 vm_page_free_zero(m);
4285 pmap_pt_page_count_adj(pmap, -1);
4289 * Initialize a preallocated and zeroed pmap structure,
4290 * such as one in a vmspace structure.
4293 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4295 vm_page_t pmltop_pg, pmltop_pgu;
4296 vm_paddr_t pmltop_phys;
4299 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4302 * Allocate the page directory page. Pass NULL instead of a
4303 * pointer to the pmap here to avoid calling
4304 * pmap_resident_count_adj() through pmap_pt_page_count_adj(),
4305 * since that requires pmap lock. Instead do the accounting
4308 * Note that final call to pmap_remove() optimization that
4309 * checks for zero resident_count is basically disabled by
4310 * accounting for top-level page. But the optimization was
4311 * not effective since we started using non-managed mapping of
4314 pmltop_pg = pmap_alloc_pt_page(NULL, 0, VM_ALLOC_WIRED | VM_ALLOC_ZERO |
4316 pmap_pt_page_count_pinit(pmap, 1);
4318 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4319 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4322 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4323 pmap->pm_pcids[i].pm_gen = 0;
4325 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4326 pmap->pm_ucr3 = PMAP_NO_CR3;
4327 pmap->pm_pmltopu = NULL;
4329 pmap->pm_type = pm_type;
4332 * Do not install the host kernel mappings in the nested page
4333 * tables. These mappings are meaningless in the guest physical
4335 * Install minimal kernel mappings in PTI case.
4339 pmap->pm_cr3 = pmltop_phys;
4340 if (pmap_is_la57(pmap))
4341 pmap_pinit_pml5(pmltop_pg);
4343 pmap_pinit_pml4(pmltop_pg);
4344 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4346 * As with pmltop_pg, pass NULL instead of a
4347 * pointer to the pmap to ensure that the PTI
4348 * page counted explicitly.
4350 pmltop_pgu = pmap_alloc_pt_page(NULL, 0,
4351 VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4352 pmap_pt_page_count_pinit(pmap, 1);
4353 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4354 VM_PAGE_TO_PHYS(pmltop_pgu));
4355 if (pmap_is_la57(pmap))
4356 pmap_pinit_pml5_pti(pmltop_pgu);
4358 pmap_pinit_pml4_pti(pmltop_pgu);
4359 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4361 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4362 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4363 pkru_free_range, pmap, M_NOWAIT);
4368 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4372 vm_radix_init(&pmap->pm_root);
4373 CPU_ZERO(&pmap->pm_active);
4374 TAILQ_INIT(&pmap->pm_pvchunk);
4375 pmap->pm_flags = flags;
4376 pmap->pm_eptgen = 0;
4382 pmap_pinit(pmap_t pmap)
4385 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4389 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4392 struct spglist free;
4394 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4395 if (mpg->ref_count != 0)
4398 _pmap_unwire_ptp(pmap, va, mpg, &free);
4399 pmap_invalidate_page(pmap, va);
4400 vm_page_free_pages_toq(&free, true);
4403 static pml4_entry_t *
4404 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4407 vm_pindex_t pml5index;
4414 if (!pmap_is_la57(pmap))
4415 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4417 PG_V = pmap_valid_bit(pmap);
4418 pml5index = pmap_pml5e_index(va);
4419 pml5 = &pmap->pm_pmltop[pml5index];
4420 if ((*pml5 & PG_V) == 0) {
4421 if (pmap_allocpte_nosleep(pmap, pmap_pml5e_pindex(va), lockp,
4428 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4429 pml4 = &pml4[pmap_pml4e_index(va)];
4430 if ((*pml4 & PG_V) == 0) {
4431 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4432 if (allocated && !addref)
4433 pml4pg->ref_count--;
4434 else if (!allocated && addref)
4435 pml4pg->ref_count++;
4440 static pdp_entry_t *
4441 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4450 PG_V = pmap_valid_bit(pmap);
4452 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4456 if ((*pml4 & PG_V) == 0) {
4457 /* Have to allocate a new pdp, recurse */
4458 if (pmap_allocpte_nosleep(pmap, pmap_pml4e_pindex(va), lockp,
4460 if (pmap_is_la57(pmap))
4461 pmap_allocpte_free_unref(pmap, va,
4462 pmap_pml5e(pmap, va));
4469 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4470 pdp = &pdp[pmap_pdpe_index(va)];
4471 if ((*pdp & PG_V) == 0) {
4472 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4473 if (allocated && !addref)
4475 else if (!allocated && addref)
4482 * The ptepindexes, i.e. page indices, of the page table pages encountered
4483 * while translating virtual address va are defined as follows:
4484 * - for the page table page (last level),
4485 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4486 * in other words, it is just the index of the PDE that maps the page
4488 * - for the page directory page,
4489 * ptepindex = NUPDE (number of userland PD entries) +
4490 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4491 * i.e. index of PDPE is put after the last index of PDE,
4492 * - for the page directory pointer page,
4493 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4495 * i.e. index of pml4e is put after the last index of PDPE,
4496 * - for the PML4 page (if LA57 mode is enabled),
4497 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4498 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4499 * i.e. index of pml5e is put after the last index of PML4E.
4501 * Define an order on the paging entries, where all entries of the
4502 * same height are put together, then heights are put from deepest to
4503 * root. Then ptexpindex is the sequential number of the
4504 * corresponding paging entry in this order.
4506 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4507 * LA57 paging structures even in LA48 paging mode. Moreover, the
4508 * ptepindexes are calculated as if the paging structures were 5-level
4509 * regardless of the actual mode of operation.
4511 * The root page at PML4/PML5 does not participate in this indexing scheme,
4512 * since it is statically allocated by pmap_pinit() and not by pmap_allocpte().
4515 pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4518 vm_pindex_t pml5index, pml4index;
4519 pml5_entry_t *pml5, *pml5u;
4520 pml4_entry_t *pml4, *pml4u;
4524 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4526 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4528 PG_A = pmap_accessed_bit(pmap);
4529 PG_M = pmap_modified_bit(pmap);
4530 PG_V = pmap_valid_bit(pmap);
4531 PG_RW = pmap_rw_bit(pmap);
4534 * Allocate a page table page.
4536 m = pmap_alloc_pt_page(pmap, ptepindex,
4537 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4542 * Map the pagetable page into the process address space, if
4543 * it isn't already there.
4545 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4546 MPASS(pmap_is_la57(pmap));
4548 pml5index = pmap_pml5e_index(va);
4549 pml5 = &pmap->pm_pmltop[pml5index];
4550 KASSERT((*pml5 & PG_V) == 0,
4551 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4552 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4554 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4555 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4558 pml5u = &pmap->pm_pmltopu[pml5index];
4559 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4562 } else if (ptepindex >= NUPDE + NUPDPE) {
4563 pml4index = pmap_pml4e_index(va);
4564 /* Wire up a new PDPE page */
4565 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4567 pmap_free_pt_page(pmap, m, true);
4570 KASSERT((*pml4 & PG_V) == 0,
4571 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4572 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4574 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4575 pml4index < NUPML4E) {
4577 * PTI: Make all user-space mappings in the
4578 * kernel-mode page table no-execute so that
4579 * we detect any programming errors that leave
4580 * the kernel-mode page table active on return
4583 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4586 pml4u = &pmap->pm_pmltopu[pml4index];
4587 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4590 } else if (ptepindex >= NUPDE) {
4591 /* Wire up a new PDE page */
4592 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4594 pmap_free_pt_page(pmap, m, true);
4597 KASSERT((*pdp & PG_V) == 0,
4598 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4599 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4601 /* Wire up a new PTE page */
4602 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4604 pmap_free_pt_page(pmap, m, true);
4607 if ((*pdp & PG_V) == 0) {
4608 /* Have to allocate a new pd, recurse */
4609 if (pmap_allocpte_nosleep(pmap, pmap_pdpe_pindex(va),
4610 lockp, va) == NULL) {
4611 pmap_allocpte_free_unref(pmap, va,
4612 pmap_pml4e(pmap, va));
4613 pmap_free_pt_page(pmap, m, true);
4617 /* Add reference to the pd page */
4618 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4621 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4623 /* Now we know where the page directory page is */
4624 pd = &pd[pmap_pde_index(va)];
4625 KASSERT((*pd & PG_V) == 0,
4626 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4627 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4634 * This routine is called if the desired page table page does not exist.
4636 * If page table page allocation fails, this routine may sleep before
4637 * returning NULL. It sleeps only if a lock pointer was given. Sleep
4638 * occurs right before returning to the caller. This way, we never
4639 * drop pmap lock to sleep while a page table page has ref_count == 0,
4640 * which prevents the page from being freed under us.
4643 pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4648 m = pmap_allocpte_nosleep(pmap, ptepindex, lockp, va);
4649 if (m == NULL && lockp != NULL) {
4650 RELEASE_PV_LIST_LOCK(lockp);
4652 PMAP_ASSERT_NOT_IN_DI();
4660 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4661 struct rwlock **lockp)
4663 pdp_entry_t *pdpe, PG_V;
4666 vm_pindex_t pdpindex;
4668 PG_V = pmap_valid_bit(pmap);
4671 pdpe = pmap_pdpe(pmap, va);
4672 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4673 pde = pmap_pdpe_to_pde(pdpe, va);
4674 if (va < VM_MAXUSER_ADDRESS) {
4675 /* Add a reference to the pd page. */
4676 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4680 } else if (va < VM_MAXUSER_ADDRESS) {
4681 /* Allocate a pd page. */
4682 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4683 pdpg = pmap_allocpte_alloc(pmap, NUPDE + pdpindex, lockp, va);
4690 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4691 pde = &pde[pmap_pde_index(va)];
4693 panic("pmap_alloc_pde: missing page table page for va %#lx",
4700 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4702 vm_pindex_t ptepindex;
4703 pd_entry_t *pd, PG_V;
4706 PG_V = pmap_valid_bit(pmap);
4709 * Calculate pagetable page index
4711 ptepindex = pmap_pde_pindex(va);
4714 * Get the page directory entry
4716 pd = pmap_pde(pmap, va);
4719 * This supports switching from a 2MB page to a
4722 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4723 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4725 * Invalidation of the 2MB page mapping may have caused
4726 * the deallocation of the underlying PD page.
4733 * If the page table page is mapped, we just increment the
4734 * hold count, and activate it.
4736 if (pd != NULL && (*pd & PG_V) != 0) {
4737 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4741 * Here if the pte page isn't mapped, or if it has been
4744 m = pmap_allocpte_alloc(pmap, ptepindex, lockp, va);
4745 if (m == NULL && lockp != NULL)
4751 /***************************************************
4752 * Pmap allocation/deallocation routines.
4753 ***************************************************/
4756 * Release any resources held by the given physical map.
4757 * Called when a pmap initialized by pmap_pinit is being released.
4758 * Should only be called if the map contains no valid mappings.
4761 pmap_release(pmap_t pmap)
4766 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4767 ("pmap_release: pmap %p has reserved page table page(s)",
4769 KASSERT(CPU_EMPTY(&pmap->pm_active),
4770 ("releasing active pmap %p", pmap));
4772 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4774 if (pmap_is_la57(pmap)) {
4775 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4776 pmap->pm_pmltop[PML5PML5I] = 0;
4778 for (i = 0; i < NKPML4E; i++) /* KVA */
4779 pmap->pm_pmltop[KPML4BASE + i] = 0;
4781 for (i = 0; i < NKASANPML4E; i++) /* KASAN shadow map */
4782 pmap->pm_pmltop[KASANPML4I + i] = 0;
4784 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4785 pmap->pm_pmltop[DMPML4I + i] = 0;
4786 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4787 for (i = 0; i < lm_ents; i++) /* Large Map */
4788 pmap->pm_pmltop[LMSPML4I + i] = 0;
4791 pmap_free_pt_page(NULL, m, true);
4792 pmap_pt_page_count_pinit(pmap, -1);
4794 if (pmap->pm_pmltopu != NULL) {
4795 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4797 pmap_free_pt_page(NULL, m, false);
4798 pmap_pt_page_count_pinit(pmap, -1);
4800 if (pmap->pm_type == PT_X86 &&
4801 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4802 rangeset_fini(&pmap->pm_pkru);
4804 KASSERT(pmap->pm_stats.resident_count == 0,
4805 ("pmap_release: pmap %p resident count %ld != 0",
4806 pmap, pmap->pm_stats.resident_count));
4810 kvm_size(SYSCTL_HANDLER_ARGS)
4812 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4814 return sysctl_handle_long(oidp, &ksize, 0, req);
4816 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4817 0, 0, kvm_size, "LU",
4821 kvm_free(SYSCTL_HANDLER_ARGS)
4823 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4825 return sysctl_handle_long(oidp, &kfree, 0, req);
4827 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4828 0, 0, kvm_free, "LU",
4829 "Amount of KVM free");
4832 * Allocate physical memory for the vm_page array and map it into KVA,
4833 * attempting to back the vm_pages with domain-local memory.
4836 pmap_page_array_startup(long pages)
4839 pd_entry_t *pde, newpdir;
4840 vm_offset_t va, start, end;
4845 vm_page_array_size = pages;
4847 start = VM_MIN_KERNEL_ADDRESS;
4848 end = start + pages * sizeof(struct vm_page);
4849 for (va = start; va < end; va += NBPDR) {
4850 pfn = first_page + (va - start) / sizeof(struct vm_page);
4851 domain = vm_phys_domain(ptoa(pfn));
4852 pdpe = pmap_pdpe(kernel_pmap, va);
4853 if ((*pdpe & X86_PG_V) == 0) {
4854 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4856 pagezero((void *)PHYS_TO_DMAP(pa));
4857 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4858 X86_PG_A | X86_PG_M);
4860 pde = pmap_pdpe_to_pde(pdpe, va);
4861 if ((*pde & X86_PG_V) != 0)
4862 panic("Unexpected pde");
4863 pa = vm_phys_early_alloc(domain, NBPDR);
4864 for (i = 0; i < NPDEPG; i++)
4865 dump_add_page(pa + i * PAGE_SIZE);
4866 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4867 X86_PG_M | PG_PS | pg_g | pg_nx);
4868 pde_store(pde, newpdir);
4870 vm_page_array = (vm_page_t)start;
4874 * grow the number of kernel page table entries, if needed
4877 pmap_growkernel(vm_offset_t addr)
4881 pd_entry_t *pde, newpdir;
4884 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4887 * Return if "addr" is within the range of kernel page table pages
4888 * that were preallocated during pmap bootstrap. Moreover, leave
4889 * "kernel_vm_end" and the kernel page table as they were.
4891 * The correctness of this action is based on the following
4892 * argument: vm_map_insert() allocates contiguous ranges of the
4893 * kernel virtual address space. It calls this function if a range
4894 * ends after "kernel_vm_end". If the kernel is mapped between
4895 * "kernel_vm_end" and "addr", then the range cannot begin at
4896 * "kernel_vm_end". In fact, its beginning address cannot be less
4897 * than the kernel. Thus, there is no immediate need to allocate
4898 * any new kernel page table pages between "kernel_vm_end" and
4901 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4904 addr = roundup2(addr, NBPDR);
4905 if (addr - 1 >= vm_map_max(kernel_map))
4906 addr = vm_map_max(kernel_map);
4907 if (kernel_vm_end < addr)
4908 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
4909 while (kernel_vm_end < addr) {
4910 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4911 if ((*pdpe & X86_PG_V) == 0) {
4912 /* We need a new PDP entry */
4913 nkpg = pmap_alloc_pt_page(kernel_pmap,
4914 kernel_vm_end >> PDPSHIFT, VM_ALLOC_WIRED |
4915 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
4917 panic("pmap_growkernel: no memory to grow kernel");
4918 paddr = VM_PAGE_TO_PHYS(nkpg);
4919 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4920 X86_PG_A | X86_PG_M);
4921 continue; /* try again */
4923 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4924 if ((*pde & X86_PG_V) != 0) {
4925 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4926 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4927 kernel_vm_end = vm_map_max(kernel_map);
4933 nkpg = pmap_alloc_pt_page(kernel_pmap,
4934 pmap_pde_pindex(kernel_vm_end), VM_ALLOC_WIRED |
4935 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
4937 panic("pmap_growkernel: no memory to grow kernel");
4938 paddr = VM_PAGE_TO_PHYS(nkpg);
4939 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4940 pde_store(pde, newpdir);
4942 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4943 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4944 kernel_vm_end = vm_map_max(kernel_map);
4950 /***************************************************
4951 * page management routines.
4952 ***************************************************/
4954 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4955 CTASSERT(_NPCM == 3);
4956 CTASSERT(_NPCPV == 168);
4958 static __inline struct pv_chunk *
4959 pv_to_chunk(pv_entry_t pv)
4962 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4965 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4967 #define PC_FREE0 0xfffffffffffffffful
4968 #define PC_FREE1 0xfffffffffffffffful
4969 #define PC_FREE2 0x000000fffffffffful
4971 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4975 static COUNTER_U64_DEFINE_EARLY(pc_chunk_count);
4976 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD,
4977 &pc_chunk_count, "Current number of pv entry cnunks");
4979 static COUNTER_U64_DEFINE_EARLY(pc_chunk_allocs);
4980 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD,
4981 &pc_chunk_allocs, "Total number of pv entry chunks allocated");
4983 static COUNTER_U64_DEFINE_EARLY(pc_chunk_frees);
4984 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD,
4985 &pc_chunk_frees, "Total number of pv entry chunks freed");
4987 static COUNTER_U64_DEFINE_EARLY(pc_chunk_tryfail);
4988 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD,
4990 "Number of failed attempts to get a pv entry chunk page");
4992 static COUNTER_U64_DEFINE_EARLY(pv_entry_frees);
4993 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD,
4994 &pv_entry_frees, "Total number of pv entries freed");
4996 static COUNTER_U64_DEFINE_EARLY(pv_entry_allocs);
4997 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD,
4998 &pv_entry_allocs, "Total number of pv entries allocated");
5000 static COUNTER_U64_DEFINE_EARLY(pv_entry_count);
5001 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD,
5002 &pv_entry_count, "Current number of pv entries");
5004 static COUNTER_U64_DEFINE_EARLY(pv_entry_spare);
5005 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD,
5006 &pv_entry_spare, "Current number of spare pv entries");
5010 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
5015 pmap_invalidate_all(pmap);
5016 if (pmap != locked_pmap)
5019 pmap_delayed_invl_finish();
5023 * We are in a serious low memory condition. Resort to
5024 * drastic measures to free some pages so we can allocate
5025 * another pv entry chunk.
5027 * Returns NULL if PV entries were reclaimed from the specified pmap.
5029 * We do not, however, unmap 2mpages because subsequent accesses will
5030 * allocate per-page pv entries until repromotion occurs, thereby
5031 * exacerbating the shortage of free pv entries.
5034 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
5036 struct pv_chunks_list *pvc;
5037 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
5038 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
5039 struct md_page *pvh;
5041 pmap_t next_pmap, pmap;
5042 pt_entry_t *pte, tpte;
5043 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5047 struct spglist free;
5049 int bit, field, freed;
5050 bool start_di, restart;
5052 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
5053 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
5056 PG_G = PG_A = PG_M = PG_RW = 0;
5058 bzero(&pc_marker_b, sizeof(pc_marker_b));
5059 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
5060 pc_marker = (struct pv_chunk *)&pc_marker_b;
5061 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
5064 * A delayed invalidation block should already be active if
5065 * pmap_advise() or pmap_remove() called this function by way
5066 * of pmap_demote_pde_locked().
5068 start_di = pmap_not_in_di();
5070 pvc = &pv_chunks[domain];
5071 mtx_lock(&pvc->pvc_lock);
5072 pvc->active_reclaims++;
5073 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
5074 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
5075 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
5076 SLIST_EMPTY(&free)) {
5077 next_pmap = pc->pc_pmap;
5078 if (next_pmap == NULL) {
5080 * The next chunk is a marker. However, it is
5081 * not our marker, so active_reclaims must be
5082 * > 1. Consequently, the next_chunk code
5083 * will not rotate the pv_chunks list.
5087 mtx_unlock(&pvc->pvc_lock);
5090 * A pv_chunk can only be removed from the pc_lru list
5091 * when both pc_chunks_mutex is owned and the
5092 * corresponding pmap is locked.
5094 if (pmap != next_pmap) {
5096 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
5099 /* Avoid deadlock and lock recursion. */
5100 if (pmap > locked_pmap) {
5101 RELEASE_PV_LIST_LOCK(lockp);
5104 pmap_delayed_invl_start();
5105 mtx_lock(&pvc->pvc_lock);
5107 } else if (pmap != locked_pmap) {
5108 if (PMAP_TRYLOCK(pmap)) {
5110 pmap_delayed_invl_start();
5111 mtx_lock(&pvc->pvc_lock);
5114 pmap = NULL; /* pmap is not locked */
5115 mtx_lock(&pvc->pvc_lock);
5116 pc = TAILQ_NEXT(pc_marker, pc_lru);
5118 pc->pc_pmap != next_pmap)
5122 } else if (start_di)
5123 pmap_delayed_invl_start();
5124 PG_G = pmap_global_bit(pmap);
5125 PG_A = pmap_accessed_bit(pmap);
5126 PG_M = pmap_modified_bit(pmap);
5127 PG_RW = pmap_rw_bit(pmap);
5133 * Destroy every non-wired, 4 KB page mapping in the chunk.
5136 for (field = 0; field < _NPCM; field++) {
5137 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
5138 inuse != 0; inuse &= ~(1UL << bit)) {
5140 pv = &pc->pc_pventry[field * 64 + bit];
5142 pde = pmap_pde(pmap, va);
5143 if ((*pde & PG_PS) != 0)
5145 pte = pmap_pde_to_pte(pde, va);
5146 if ((*pte & PG_W) != 0)
5148 tpte = pte_load_clear(pte);
5149 if ((tpte & PG_G) != 0)
5150 pmap_invalidate_page(pmap, va);
5151 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
5152 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5154 if ((tpte & PG_A) != 0)
5155 vm_page_aflag_set(m, PGA_REFERENCED);
5156 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5157 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5159 if (TAILQ_EMPTY(&m->md.pv_list) &&
5160 (m->flags & PG_FICTITIOUS) == 0) {
5161 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5162 if (TAILQ_EMPTY(&pvh->pv_list)) {
5163 vm_page_aflag_clear(m,
5167 pmap_delayed_invl_page(m);
5168 pc->pc_map[field] |= 1UL << bit;
5169 pmap_unuse_pt(pmap, va, *pde, &free);
5174 mtx_lock(&pvc->pvc_lock);
5177 /* Every freed mapping is for a 4 KB page. */
5178 pmap_resident_count_adj(pmap, -freed);
5179 PV_STAT(counter_u64_add(pv_entry_frees, freed));
5180 PV_STAT(counter_u64_add(pv_entry_spare, freed));
5181 PV_STAT(counter_u64_add(pv_entry_count, -freed));
5182 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5183 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
5184 pc->pc_map[2] == PC_FREE2) {
5185 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5186 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5187 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5188 /* Entire chunk is free; return it. */
5189 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5190 dump_drop_page(m_pc->phys_addr);
5191 mtx_lock(&pvc->pvc_lock);
5192 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5195 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5196 mtx_lock(&pvc->pvc_lock);
5197 /* One freed pv entry in locked_pmap is sufficient. */
5198 if (pmap == locked_pmap)
5201 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5202 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
5203 if (pvc->active_reclaims == 1 && pmap != NULL) {
5205 * Rotate the pv chunks list so that we do not
5206 * scan the same pv chunks that could not be
5207 * freed (because they contained a wired
5208 * and/or superpage mapping) on every
5209 * invocation of reclaim_pv_chunk().
5211 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
5212 MPASS(pc->pc_pmap != NULL);
5213 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5214 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5218 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5219 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
5220 pvc->active_reclaims--;
5221 mtx_unlock(&pvc->pvc_lock);
5222 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
5223 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
5224 m_pc = SLIST_FIRST(&free);
5225 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
5226 /* Recycle a freed page table page. */
5227 m_pc->ref_count = 1;
5229 vm_page_free_pages_toq(&free, true);
5234 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
5239 domain = PCPU_GET(domain);
5240 for (i = 0; i < vm_ndomains; i++) {
5241 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
5244 domain = (domain + 1) % vm_ndomains;
5251 * free the pv_entry back to the free list
5254 free_pv_entry(pmap_t pmap, pv_entry_t pv)
5256 struct pv_chunk *pc;
5257 int idx, field, bit;
5259 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5260 PV_STAT(counter_u64_add(pv_entry_frees, 1));
5261 PV_STAT(counter_u64_add(pv_entry_spare, 1));
5262 PV_STAT(counter_u64_add(pv_entry_count, -1));
5263 pc = pv_to_chunk(pv);
5264 idx = pv - &pc->pc_pventry[0];
5267 pc->pc_map[field] |= 1ul << bit;
5268 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5269 pc->pc_map[2] != PC_FREE2) {
5270 /* 98% of the time, pc is already at the head of the list. */
5271 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5272 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5273 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5277 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5282 free_pv_chunk_dequeued(struct pv_chunk *pc)
5286 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5287 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5288 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5289 counter_u64_add(pv_page_count, -1);
5290 /* entire chunk is free, return it */
5291 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5292 dump_drop_page(m->phys_addr);
5293 vm_page_unwire_noq(m);
5298 free_pv_chunk(struct pv_chunk *pc)
5300 struct pv_chunks_list *pvc;
5302 pvc = &pv_chunks[pc_to_domain(pc)];
5303 mtx_lock(&pvc->pvc_lock);
5304 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5305 mtx_unlock(&pvc->pvc_lock);
5306 free_pv_chunk_dequeued(pc);
5310 free_pv_chunk_batch(struct pv_chunklist *batch)
5312 struct pv_chunks_list *pvc;
5313 struct pv_chunk *pc, *npc;
5316 for (i = 0; i < vm_ndomains; i++) {
5317 if (TAILQ_EMPTY(&batch[i]))
5319 pvc = &pv_chunks[i];
5320 mtx_lock(&pvc->pvc_lock);
5321 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5322 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5324 mtx_unlock(&pvc->pvc_lock);
5327 for (i = 0; i < vm_ndomains; i++) {
5328 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5329 free_pv_chunk_dequeued(pc);
5335 * Returns a new PV entry, allocating a new PV chunk from the system when
5336 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5337 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5340 * The given PV list lock may be released.
5343 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5345 struct pv_chunks_list *pvc;
5348 struct pv_chunk *pc;
5351 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5352 PV_STAT(counter_u64_add(pv_entry_allocs, 1));
5354 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5356 for (field = 0; field < _NPCM; field++) {
5357 if (pc->pc_map[field]) {
5358 bit = bsfq(pc->pc_map[field]);
5362 if (field < _NPCM) {
5363 pv = &pc->pc_pventry[field * 64 + bit];
5364 pc->pc_map[field] &= ~(1ul << bit);
5365 /* If this was the last item, move it to tail */
5366 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5367 pc->pc_map[2] == 0) {
5368 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5369 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5372 PV_STAT(counter_u64_add(pv_entry_count, 1));
5373 PV_STAT(counter_u64_add(pv_entry_spare, -1));
5377 /* No free items, allocate another chunk */
5378 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
5380 if (lockp == NULL) {
5381 PV_STAT(counter_u64_add(pc_chunk_tryfail, 1));
5384 m = reclaim_pv_chunk(pmap, lockp);
5388 counter_u64_add(pv_page_count, 1);
5389 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5390 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5391 dump_add_page(m->phys_addr);
5392 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5394 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5395 pc->pc_map[1] = PC_FREE1;
5396 pc->pc_map[2] = PC_FREE2;
5397 pvc = &pv_chunks[vm_page_domain(m)];
5398 mtx_lock(&pvc->pvc_lock);
5399 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5400 mtx_unlock(&pvc->pvc_lock);
5401 pv = &pc->pc_pventry[0];
5402 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5403 PV_STAT(counter_u64_add(pv_entry_count, 1));
5404 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV - 1));
5409 * Returns the number of one bits within the given PV chunk map.
5411 * The erratas for Intel processors state that "POPCNT Instruction May
5412 * Take Longer to Execute Than Expected". It is believed that the
5413 * issue is the spurious dependency on the destination register.
5414 * Provide a hint to the register rename logic that the destination
5415 * value is overwritten, by clearing it, as suggested in the
5416 * optimization manual. It should be cheap for unaffected processors
5419 * Reference numbers for erratas are
5420 * 4th Gen Core: HSD146
5421 * 5th Gen Core: BDM85
5422 * 6th Gen Core: SKL029
5425 popcnt_pc_map_pq(uint64_t *map)
5429 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5430 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5431 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5432 : "=&r" (result), "=&r" (tmp)
5433 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5438 * Ensure that the number of spare PV entries in the specified pmap meets or
5439 * exceeds the given count, "needed".
5441 * The given PV list lock may be released.
5444 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5446 struct pv_chunks_list *pvc;
5447 struct pch new_tail[PMAP_MEMDOM];
5448 struct pv_chunk *pc;
5453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5454 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5457 * Newly allocated PV chunks must be stored in a private list until
5458 * the required number of PV chunks have been allocated. Otherwise,
5459 * reclaim_pv_chunk() could recycle one of these chunks. In
5460 * contrast, these chunks must be added to the pmap upon allocation.
5462 for (i = 0; i < PMAP_MEMDOM; i++)
5463 TAILQ_INIT(&new_tail[i]);
5466 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5468 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5469 bit_count((bitstr_t *)pc->pc_map, 0,
5470 sizeof(pc->pc_map) * NBBY, &free);
5473 free = popcnt_pc_map_pq(pc->pc_map);
5477 if (avail >= needed)
5480 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5481 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
5483 m = reclaim_pv_chunk(pmap, lockp);
5488 counter_u64_add(pv_page_count, 1);
5489 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5490 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5491 dump_add_page(m->phys_addr);
5492 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5494 pc->pc_map[0] = PC_FREE0;
5495 pc->pc_map[1] = PC_FREE1;
5496 pc->pc_map[2] = PC_FREE2;
5497 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5498 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
5499 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV));
5502 * The reclaim might have freed a chunk from the current pmap.
5503 * If that chunk contained available entries, we need to
5504 * re-count the number of available entries.
5509 for (i = 0; i < vm_ndomains; i++) {
5510 if (TAILQ_EMPTY(&new_tail[i]))
5512 pvc = &pv_chunks[i];
5513 mtx_lock(&pvc->pvc_lock);
5514 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5515 mtx_unlock(&pvc->pvc_lock);
5520 * First find and then remove the pv entry for the specified pmap and virtual
5521 * address from the specified pv list. Returns the pv entry if found and NULL
5522 * otherwise. This operation can be performed on pv lists for either 4KB or
5523 * 2MB page mappings.
5525 static __inline pv_entry_t
5526 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5530 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5531 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5532 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5541 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5542 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5543 * entries for each of the 4KB page mappings.
5546 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5547 struct rwlock **lockp)
5549 struct md_page *pvh;
5550 struct pv_chunk *pc;
5552 vm_offset_t va_last;
5556 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5557 KASSERT((pa & PDRMASK) == 0,
5558 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5559 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5562 * Transfer the 2mpage's pv entry for this mapping to the first
5563 * page's pv list. Once this transfer begins, the pv list lock
5564 * must not be released until the last pv entry is reinstantiated.
5566 pvh = pa_to_pvh(pa);
5567 va = trunc_2mpage(va);
5568 pv = pmap_pvh_remove(pvh, pmap, va);
5569 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5570 m = PHYS_TO_VM_PAGE(pa);
5571 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5573 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5574 PV_STAT(counter_u64_add(pv_entry_allocs, NPTEPG - 1));
5575 va_last = va + NBPDR - PAGE_SIZE;
5577 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5578 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5579 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5580 for (field = 0; field < _NPCM; field++) {
5581 while (pc->pc_map[field]) {
5582 bit = bsfq(pc->pc_map[field]);
5583 pc->pc_map[field] &= ~(1ul << bit);
5584 pv = &pc->pc_pventry[field * 64 + bit];
5588 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5589 ("pmap_pv_demote_pde: page %p is not managed", m));
5590 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5596 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5597 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5600 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5601 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5602 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5604 PV_STAT(counter_u64_add(pv_entry_count, NPTEPG - 1));
5605 PV_STAT(counter_u64_add(pv_entry_spare, -(NPTEPG - 1)));
5608 #if VM_NRESERVLEVEL > 0
5610 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5611 * replace the many pv entries for the 4KB page mappings by a single pv entry
5612 * for the 2MB page mapping.
5615 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5616 struct rwlock **lockp)
5618 struct md_page *pvh;
5620 vm_offset_t va_last;
5623 KASSERT((pa & PDRMASK) == 0,
5624 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5625 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5628 * Transfer the first page's pv entry for this mapping to the 2mpage's
5629 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5630 * a transfer avoids the possibility that get_pv_entry() calls
5631 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5632 * mappings that is being promoted.
5634 m = PHYS_TO_VM_PAGE(pa);
5635 va = trunc_2mpage(va);
5636 pv = pmap_pvh_remove(&m->md, pmap, va);
5637 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5638 pvh = pa_to_pvh(pa);
5639 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5641 /* Free the remaining NPTEPG - 1 pv entries. */
5642 va_last = va + NBPDR - PAGE_SIZE;
5646 pmap_pvh_free(&m->md, pmap, va);
5647 } while (va < va_last);
5649 #endif /* VM_NRESERVLEVEL > 0 */
5652 * First find and then destroy the pv entry for the specified pmap and virtual
5653 * address. This operation can be performed on pv lists for either 4KB or 2MB
5657 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5661 pv = pmap_pvh_remove(pvh, pmap, va);
5662 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5663 free_pv_entry(pmap, pv);
5667 * Conditionally create the PV entry for a 4KB page mapping if the required
5668 * memory can be allocated without resorting to reclamation.
5671 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5672 struct rwlock **lockp)
5676 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5677 /* Pass NULL instead of the lock pointer to disable reclamation. */
5678 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5680 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5681 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5689 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5690 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5691 * false if the PV entry cannot be allocated without resorting to reclamation.
5694 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5695 struct rwlock **lockp)
5697 struct md_page *pvh;
5701 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5702 /* Pass NULL instead of the lock pointer to disable reclamation. */
5703 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5704 NULL : lockp)) == NULL)
5707 pa = pde & PG_PS_FRAME;
5708 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5709 pvh = pa_to_pvh(pa);
5710 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5716 * Fills a page table page with mappings to consecutive physical pages.
5719 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5723 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5725 newpte += PAGE_SIZE;
5730 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5731 * mapping is invalidated.
5734 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5736 struct rwlock *lock;
5740 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5747 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5751 pt_entry_t *xpte, *ypte;
5753 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5754 xpte++, newpte += PAGE_SIZE) {
5755 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5756 printf("pmap_demote_pde: xpte %zd and newpte map "
5757 "different pages: found %#lx, expected %#lx\n",
5758 xpte - firstpte, *xpte, newpte);
5759 printf("page table dump\n");
5760 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5761 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5766 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5767 ("pmap_demote_pde: firstpte and newpte map different physical"
5774 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5775 pd_entry_t oldpde, struct rwlock **lockp)
5777 struct spglist free;
5781 sva = trunc_2mpage(va);
5782 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5783 if ((oldpde & pmap_global_bit(pmap)) == 0)
5784 pmap_invalidate_pde_page(pmap, sva, oldpde);
5785 vm_page_free_pages_toq(&free, true);
5786 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5791 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5792 struct rwlock **lockp)
5794 pd_entry_t newpde, oldpde;
5795 pt_entry_t *firstpte, newpte;
5796 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5802 PG_A = pmap_accessed_bit(pmap);
5803 PG_G = pmap_global_bit(pmap);
5804 PG_M = pmap_modified_bit(pmap);
5805 PG_RW = pmap_rw_bit(pmap);
5806 PG_V = pmap_valid_bit(pmap);
5807 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5808 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5810 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5811 in_kernel = va >= VM_MAXUSER_ADDRESS;
5813 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5814 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5817 * Invalidate the 2MB page mapping and return "failure" if the
5818 * mapping was never accessed.
5820 if ((oldpde & PG_A) == 0) {
5821 KASSERT((oldpde & PG_W) == 0,
5822 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5823 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5827 mpte = pmap_remove_pt_page(pmap, va);
5829 KASSERT((oldpde & PG_W) == 0,
5830 ("pmap_demote_pde: page table page for a wired mapping"
5834 * If the page table page is missing and the mapping
5835 * is for a kernel address, the mapping must belong to
5836 * the direct map. Page table pages are preallocated
5837 * for every other part of the kernel address space,
5838 * so the direct map region is the only part of the
5839 * kernel address space that must be handled here.
5841 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5842 va < DMAP_MAX_ADDRESS),
5843 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5846 * If the 2MB page mapping belongs to the direct map
5847 * region of the kernel's address space, then the page
5848 * allocation request specifies the highest possible
5849 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5850 * priority is normal.
5852 mpte = pmap_alloc_pt_page(pmap, pmap_pde_pindex(va),
5853 (in_kernel ? VM_ALLOC_INTERRUPT : 0) | VM_ALLOC_WIRED);
5856 * If the allocation of the new page table page fails,
5857 * invalidate the 2MB page mapping and return "failure".
5860 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5865 mpte->ref_count = NPTEPG;
5867 mptepa = VM_PAGE_TO_PHYS(mpte);
5868 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5869 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5870 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5871 ("pmap_demote_pde: oldpde is missing PG_M"));
5872 newpte = oldpde & ~PG_PS;
5873 newpte = pmap_swap_pat(pmap, newpte);
5876 * If the page table page is not leftover from an earlier promotion,
5879 if (mpte->valid == 0)
5880 pmap_fill_ptp(firstpte, newpte);
5882 pmap_demote_pde_check(firstpte, newpte);
5885 * If the mapping has changed attributes, update the page table
5888 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5889 pmap_fill_ptp(firstpte, newpte);
5892 * The spare PV entries must be reserved prior to demoting the
5893 * mapping, that is, prior to changing the PDE. Otherwise, the state
5894 * of the PDE and the PV lists will be inconsistent, which can result
5895 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5896 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5897 * PV entry for the 2MB page mapping that is being demoted.
5899 if ((oldpde & PG_MANAGED) != 0)
5900 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5903 * Demote the mapping. This pmap is locked. The old PDE has
5904 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5905 * set. Thus, there is no danger of a race with another
5906 * processor changing the setting of PG_A and/or PG_M between
5907 * the read above and the store below.
5909 if (workaround_erratum383)
5910 pmap_update_pde(pmap, va, pde, newpde);
5912 pde_store(pde, newpde);
5915 * Invalidate a stale recursive mapping of the page table page.
5918 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5921 * Demote the PV entry.
5923 if ((oldpde & PG_MANAGED) != 0)
5924 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5926 counter_u64_add(pmap_pde_demotions, 1);
5927 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5933 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5936 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5942 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5944 mpte = pmap_remove_pt_page(pmap, va);
5946 panic("pmap_remove_kernel_pde: Missing pt page.");
5948 mptepa = VM_PAGE_TO_PHYS(mpte);
5949 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5952 * If this page table page was unmapped by a promotion, then it
5953 * contains valid mappings. Zero it to invalidate those mappings.
5955 if (mpte->valid != 0)
5956 pagezero((void *)PHYS_TO_DMAP(mptepa));
5959 * Demote the mapping.
5961 if (workaround_erratum383)
5962 pmap_update_pde(pmap, va, pde, newpde);
5964 pde_store(pde, newpde);
5967 * Invalidate a stale recursive mapping of the page table page.
5969 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5973 * pmap_remove_pde: do the things to unmap a superpage in a process
5976 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5977 struct spglist *free, struct rwlock **lockp)
5979 struct md_page *pvh;
5981 vm_offset_t eva, va;
5983 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5985 PG_G = pmap_global_bit(pmap);
5986 PG_A = pmap_accessed_bit(pmap);
5987 PG_M = pmap_modified_bit(pmap);
5988 PG_RW = pmap_rw_bit(pmap);
5990 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5991 KASSERT((sva & PDRMASK) == 0,
5992 ("pmap_remove_pde: sva is not 2mpage aligned"));
5993 oldpde = pte_load_clear(pdq);
5995 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5996 if ((oldpde & PG_G) != 0)
5997 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5998 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
5999 if (oldpde & PG_MANAGED) {
6000 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
6001 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
6002 pmap_pvh_free(pvh, pmap, sva);
6004 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6005 va < eva; va += PAGE_SIZE, m++) {
6006 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
6009 vm_page_aflag_set(m, PGA_REFERENCED);
6010 if (TAILQ_EMPTY(&m->md.pv_list) &&
6011 TAILQ_EMPTY(&pvh->pv_list))
6012 vm_page_aflag_clear(m, PGA_WRITEABLE);
6013 pmap_delayed_invl_page(m);
6016 if (pmap == kernel_pmap) {
6017 pmap_remove_kernel_pde(pmap, pdq, sva);
6019 mpte = pmap_remove_pt_page(pmap, sva);
6021 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6022 ("pmap_remove_pde: pte page not promoted"));
6023 pmap_resident_count_adj(pmap, -1);
6024 KASSERT(mpte->ref_count == NPTEPG,
6025 ("pmap_remove_pde: pte page ref count error"));
6026 mpte->ref_count = 0;
6027 pmap_add_delayed_free_list(mpte, free, FALSE);
6030 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
6034 * pmap_remove_pte: do the things to unmap a page in a process
6037 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
6038 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
6040 struct md_page *pvh;
6041 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
6044 PG_A = pmap_accessed_bit(pmap);
6045 PG_M = pmap_modified_bit(pmap);
6046 PG_RW = pmap_rw_bit(pmap);
6048 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6049 oldpte = pte_load_clear(ptq);
6051 pmap->pm_stats.wired_count -= 1;
6052 pmap_resident_count_adj(pmap, -1);
6053 if (oldpte & PG_MANAGED) {
6054 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
6055 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6058 vm_page_aflag_set(m, PGA_REFERENCED);
6059 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
6060 pmap_pvh_free(&m->md, pmap, va);
6061 if (TAILQ_EMPTY(&m->md.pv_list) &&
6062 (m->flags & PG_FICTITIOUS) == 0) {
6063 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6064 if (TAILQ_EMPTY(&pvh->pv_list))
6065 vm_page_aflag_clear(m, PGA_WRITEABLE);
6067 pmap_delayed_invl_page(m);
6069 return (pmap_unuse_pt(pmap, va, ptepde, free));
6073 * Remove a single page from a process address space
6076 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
6077 struct spglist *free)
6079 struct rwlock *lock;
6080 pt_entry_t *pte, PG_V;
6082 PG_V = pmap_valid_bit(pmap);
6083 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6084 if ((*pde & PG_V) == 0)
6086 pte = pmap_pde_to_pte(pde, va);
6087 if ((*pte & PG_V) == 0)
6090 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
6093 pmap_invalidate_page(pmap, va);
6097 * Removes the specified range of addresses from the page table page.
6100 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
6101 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
6103 pt_entry_t PG_G, *pte;
6107 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6108 PG_G = pmap_global_bit(pmap);
6111 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
6115 pmap_invalidate_range(pmap, va, sva);
6120 if ((*pte & PG_G) == 0)
6124 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
6130 pmap_invalidate_range(pmap, va, sva);
6135 * Remove the given range of addresses from the specified map.
6137 * It is assumed that the start and end are properly
6138 * rounded to the page size.
6141 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6143 struct rwlock *lock;
6145 vm_offset_t va_next;
6146 pml5_entry_t *pml5e;
6147 pml4_entry_t *pml4e;
6149 pd_entry_t ptpaddr, *pde;
6150 pt_entry_t PG_G, PG_V;
6151 struct spglist free;
6154 PG_G = pmap_global_bit(pmap);
6155 PG_V = pmap_valid_bit(pmap);
6158 * If there are no resident pages besides the top level page
6159 * table page(s), there is nothing to do. Kernel pmap always
6160 * accounts whole preloaded area as resident, which makes its
6161 * resident count > 2.
6162 * Perform an unsynchronized read. This is, however, safe.
6164 if (pmap->pm_stats.resident_count <= 1 + (pmap->pm_pmltopu != NULL ?
6171 pmap_delayed_invl_start();
6173 pmap_pkru_on_remove(pmap, sva, eva);
6176 * special handling of removing one page. a very
6177 * common operation and easy to short circuit some
6180 if (sva + PAGE_SIZE == eva) {
6181 pde = pmap_pde(pmap, sva);
6182 if (pde && (*pde & PG_PS) == 0) {
6183 pmap_remove_page(pmap, sva, pde, &free);
6189 for (; sva < eva; sva = va_next) {
6190 if (pmap->pm_stats.resident_count == 0)
6193 if (pmap_is_la57(pmap)) {
6194 pml5e = pmap_pml5e(pmap, sva);
6195 if ((*pml5e & PG_V) == 0) {
6196 va_next = (sva + NBPML5) & ~PML5MASK;
6201 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
6203 pml4e = pmap_pml4e(pmap, sva);
6205 if ((*pml4e & PG_V) == 0) {
6206 va_next = (sva + NBPML4) & ~PML4MASK;
6212 va_next = (sva + NBPDP) & ~PDPMASK;
6215 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6216 if ((*pdpe & PG_V) == 0)
6218 if ((*pdpe & PG_PS) != 0) {
6219 KASSERT(va_next <= eva,
6220 ("partial update of non-transparent 1G mapping "
6221 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6222 *pdpe, sva, eva, va_next));
6223 MPASS(pmap != kernel_pmap); /* XXXKIB */
6224 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
6227 pmap_resident_count_adj(pmap, -NBPDP / PAGE_SIZE);
6228 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
6229 pmap_unwire_ptp(pmap, sva, mt, &free);
6234 * Calculate index for next page table.
6236 va_next = (sva + NBPDR) & ~PDRMASK;
6240 pde = pmap_pdpe_to_pde(pdpe, sva);
6244 * Weed out invalid mappings.
6250 * Check for large page.
6252 if ((ptpaddr & PG_PS) != 0) {
6254 * Are we removing the entire large page? If not,
6255 * demote the mapping and fall through.
6257 if (sva + NBPDR == va_next && eva >= va_next) {
6259 * The TLB entry for a PG_G mapping is
6260 * invalidated by pmap_remove_pde().
6262 if ((ptpaddr & PG_G) == 0)
6264 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6266 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6268 /* The large page mapping was destroyed. */
6275 * Limit our scan to either the end of the va represented
6276 * by the current page table page, or to the end of the
6277 * range being removed.
6282 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6289 pmap_invalidate_all(pmap);
6291 pmap_delayed_invl_finish();
6292 vm_page_free_pages_toq(&free, true);
6296 * Routine: pmap_remove_all
6298 * Removes this physical page from
6299 * all physical maps in which it resides.
6300 * Reflects back modify bits to the pager.
6303 * Original versions of this routine were very
6304 * inefficient because they iteratively called
6305 * pmap_remove (slow...)
6309 pmap_remove_all(vm_page_t m)
6311 struct md_page *pvh;
6314 struct rwlock *lock;
6315 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6318 struct spglist free;
6319 int pvh_gen, md_gen;
6321 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6322 ("pmap_remove_all: page %p is not managed", m));
6324 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6325 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6326 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6329 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6331 if (!PMAP_TRYLOCK(pmap)) {
6332 pvh_gen = pvh->pv_gen;
6336 if (pvh_gen != pvh->pv_gen) {
6342 pde = pmap_pde(pmap, va);
6343 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6346 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6348 if (!PMAP_TRYLOCK(pmap)) {
6349 pvh_gen = pvh->pv_gen;
6350 md_gen = m->md.pv_gen;
6354 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6359 PG_A = pmap_accessed_bit(pmap);
6360 PG_M = pmap_modified_bit(pmap);
6361 PG_RW = pmap_rw_bit(pmap);
6362 pmap_resident_count_adj(pmap, -1);
6363 pde = pmap_pde(pmap, pv->pv_va);
6364 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6365 " a 2mpage in page %p's pv list", m));
6366 pte = pmap_pde_to_pte(pde, pv->pv_va);
6367 tpte = pte_load_clear(pte);
6369 pmap->pm_stats.wired_count--;
6371 vm_page_aflag_set(m, PGA_REFERENCED);
6374 * Update the vm_page_t clean and reference bits.
6376 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6378 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6379 pmap_invalidate_page(pmap, pv->pv_va);
6380 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6382 free_pv_entry(pmap, pv);
6385 vm_page_aflag_clear(m, PGA_WRITEABLE);
6387 pmap_delayed_invl_wait(m);
6388 vm_page_free_pages_toq(&free, true);
6392 * pmap_protect_pde: do the things to protect a 2mpage in a process
6395 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6397 pd_entry_t newpde, oldpde;
6399 boolean_t anychanged;
6400 pt_entry_t PG_G, PG_M, PG_RW;
6402 PG_G = pmap_global_bit(pmap);
6403 PG_M = pmap_modified_bit(pmap);
6404 PG_RW = pmap_rw_bit(pmap);
6406 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6407 KASSERT((sva & PDRMASK) == 0,
6408 ("pmap_protect_pde: sva is not 2mpage aligned"));
6411 oldpde = newpde = *pde;
6412 if ((prot & VM_PROT_WRITE) == 0) {
6413 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6414 (PG_MANAGED | PG_M | PG_RW)) {
6415 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6416 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6419 newpde &= ~(PG_RW | PG_M);
6421 if ((prot & VM_PROT_EXECUTE) == 0)
6423 if (newpde != oldpde) {
6425 * As an optimization to future operations on this PDE, clear
6426 * PG_PROMOTED. The impending invalidation will remove any
6427 * lingering 4KB page mappings from the TLB.
6429 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6431 if ((oldpde & PG_G) != 0)
6432 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6436 return (anychanged);
6440 * Set the physical protection on the
6441 * specified range of this map as requested.
6444 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6447 vm_offset_t va_next;
6448 pml4_entry_t *pml4e;
6450 pd_entry_t ptpaddr, *pde;
6451 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6452 pt_entry_t obits, pbits;
6453 boolean_t anychanged;
6455 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6456 if (prot == VM_PROT_NONE) {
6457 pmap_remove(pmap, sva, eva);
6461 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6462 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6465 PG_G = pmap_global_bit(pmap);
6466 PG_M = pmap_modified_bit(pmap);
6467 PG_V = pmap_valid_bit(pmap);
6468 PG_RW = pmap_rw_bit(pmap);
6472 * Although this function delays and batches the invalidation
6473 * of stale TLB entries, it does not need to call
6474 * pmap_delayed_invl_start() and
6475 * pmap_delayed_invl_finish(), because it does not
6476 * ordinarily destroy mappings. Stale TLB entries from
6477 * protection-only changes need only be invalidated before the
6478 * pmap lock is released, because protection-only changes do
6479 * not destroy PV entries. Even operations that iterate over
6480 * a physical page's PV list of mappings, like
6481 * pmap_remove_write(), acquire the pmap lock for each
6482 * mapping. Consequently, for protection-only changes, the
6483 * pmap lock suffices to synchronize both page table and TLB
6486 * This function only destroys a mapping if pmap_demote_pde()
6487 * fails. In that case, stale TLB entries are immediately
6492 for (; sva < eva; sva = va_next) {
6493 pml4e = pmap_pml4e(pmap, sva);
6494 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6495 va_next = (sva + NBPML4) & ~PML4MASK;
6501 va_next = (sva + NBPDP) & ~PDPMASK;
6504 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6505 if ((*pdpe & PG_V) == 0)
6507 if ((*pdpe & PG_PS) != 0) {
6508 KASSERT(va_next <= eva,
6509 ("partial update of non-transparent 1G mapping "
6510 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6511 *pdpe, sva, eva, va_next));
6513 obits = pbits = *pdpe;
6514 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6515 MPASS(pmap != kernel_pmap); /* XXXKIB */
6516 if ((prot & VM_PROT_WRITE) == 0)
6517 pbits &= ~(PG_RW | PG_M);
6518 if ((prot & VM_PROT_EXECUTE) == 0)
6521 if (pbits != obits) {
6522 if (!atomic_cmpset_long(pdpe, obits, pbits))
6523 /* PG_PS cannot be cleared under us, */
6530 va_next = (sva + NBPDR) & ~PDRMASK;
6534 pde = pmap_pdpe_to_pde(pdpe, sva);
6538 * Weed out invalid mappings.
6544 * Check for large page.
6546 if ((ptpaddr & PG_PS) != 0) {
6548 * Are we protecting the entire large page? If not,
6549 * demote the mapping and fall through.
6551 if (sva + NBPDR == va_next && eva >= va_next) {
6553 * The TLB entry for a PG_G mapping is
6554 * invalidated by pmap_protect_pde().
6556 if (pmap_protect_pde(pmap, pde, sva, prot))
6559 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6561 * The large page mapping was destroyed.
6570 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6573 obits = pbits = *pte;
6574 if ((pbits & PG_V) == 0)
6577 if ((prot & VM_PROT_WRITE) == 0) {
6578 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6579 (PG_MANAGED | PG_M | PG_RW)) {
6580 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6583 pbits &= ~(PG_RW | PG_M);
6585 if ((prot & VM_PROT_EXECUTE) == 0)
6588 if (pbits != obits) {
6589 if (!atomic_cmpset_long(pte, obits, pbits))
6592 pmap_invalidate_page(pmap, sva);
6599 pmap_invalidate_all(pmap);
6603 #if VM_NRESERVLEVEL > 0
6605 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6608 if (pmap->pm_type != PT_EPT)
6610 return ((pde & EPT_PG_EXECUTE) != 0);
6614 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6615 * single page table page (PTP) to a single 2MB page mapping. For promotion
6616 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6617 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6618 * identical characteristics.
6621 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6622 struct rwlock **lockp)
6625 pt_entry_t *firstpte, oldpte, pa, *pte;
6626 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6630 PG_A = pmap_accessed_bit(pmap);
6631 PG_G = pmap_global_bit(pmap);
6632 PG_M = pmap_modified_bit(pmap);
6633 PG_V = pmap_valid_bit(pmap);
6634 PG_RW = pmap_rw_bit(pmap);
6635 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6636 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6638 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6641 * Examine the first PTE in the specified PTP. Abort if this PTE is
6642 * either invalid, unused, or does not map the first 4KB physical page
6643 * within a 2MB page.
6645 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6647 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6648 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6650 counter_u64_add(pmap_pde_p_failures, 1);
6651 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6652 " in pmap %p", va, pmap);
6656 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6658 * When PG_M is already clear, PG_RW can be cleared without
6659 * a TLB invalidation.
6661 if (!atomic_fcmpset_long(firstpte, &newpde, newpde & ~PG_RW))
6667 * Examine each of the other PTEs in the specified PTP. Abort if this
6668 * PTE maps an unexpected 4KB physical page or does not have identical
6669 * characteristics to the first PTE.
6671 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6672 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6674 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6675 counter_u64_add(pmap_pde_p_failures, 1);
6676 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6677 " in pmap %p", va, pmap);
6681 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6683 * When PG_M is already clear, PG_RW can be cleared
6684 * without a TLB invalidation.
6686 if (!atomic_fcmpset_long(pte, &oldpte, oldpte & ~PG_RW))
6689 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6690 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6691 (va & ~PDRMASK), pmap);
6693 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6694 counter_u64_add(pmap_pde_p_failures, 1);
6695 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6696 " in pmap %p", va, pmap);
6703 * Save the page table page in its current state until the PDE
6704 * mapping the superpage is demoted by pmap_demote_pde() or
6705 * destroyed by pmap_remove_pde().
6707 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6708 KASSERT(mpte >= vm_page_array &&
6709 mpte < &vm_page_array[vm_page_array_size],
6710 ("pmap_promote_pde: page table page is out of range"));
6711 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6712 ("pmap_promote_pde: page table page's pindex is wrong "
6713 "mpte %p pidx %#lx va %#lx va pde pidx %#lx",
6714 mpte, mpte->pindex, va, pmap_pde_pindex(va)));
6715 if (pmap_insert_pt_page(pmap, mpte, true)) {
6716 counter_u64_add(pmap_pde_p_failures, 1);
6718 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6724 * Promote the pv entries.
6726 if ((newpde & PG_MANAGED) != 0)
6727 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6730 * Propagate the PAT index to its proper position.
6732 newpde = pmap_swap_pat(pmap, newpde);
6735 * Map the superpage.
6737 if (workaround_erratum383)
6738 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6740 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6742 counter_u64_add(pmap_pde_promotions, 1);
6743 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6744 " in pmap %p", va, pmap);
6746 #endif /* VM_NRESERVLEVEL > 0 */
6749 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6753 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6755 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6756 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6757 ("psind %d unexpected", psind));
6758 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6759 ("unaligned phys address %#lx newpte %#lx psind %d",
6760 newpte & PG_FRAME, newpte, psind));
6761 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6762 ("unaligned va %#lx psind %d", va, psind));
6763 KASSERT(va < VM_MAXUSER_ADDRESS,
6764 ("kernel mode non-transparent superpage")); /* XXXKIB */
6765 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6766 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6768 PG_V = pmap_valid_bit(pmap);
6771 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6772 return (KERN_PROTECTION_FAILURE);
6774 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6775 pten |= pmap_pkru_get(pmap, va);
6777 if (psind == 2) { /* 1G */
6778 pml4e = pmap_pml4e(pmap, va);
6779 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6780 mp = pmap_allocpte_alloc(pmap, pmap_pml4e_pindex(va),
6784 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6785 pdpe = &pdpe[pmap_pdpe_index(va)];
6787 MPASS(origpte == 0);
6789 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6790 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6792 if ((origpte & PG_V) == 0) {
6793 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6798 } else /* (psind == 1) */ { /* 2M */
6799 pde = pmap_pde(pmap, va);
6801 mp = pmap_allocpte_alloc(pmap, pmap_pdpe_pindex(va),
6805 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6806 pde = &pde[pmap_pde_index(va)];
6808 MPASS(origpte == 0);
6811 if ((origpte & PG_V) == 0) {
6812 pdpe = pmap_pdpe(pmap, va);
6813 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6814 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6820 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6821 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6822 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6823 va, psind == 2 ? "1G" : "2M", origpte, pten));
6824 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6825 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6826 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6827 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6828 if ((origpte & PG_V) == 0)
6829 pmap_resident_count_adj(pmap, pagesizes[psind] / PAGE_SIZE);
6831 return (KERN_SUCCESS);
6834 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6835 return (KERN_RESOURCE_SHORTAGE);
6843 * Insert the given physical page (p) at
6844 * the specified virtual address (v) in the
6845 * target physical map with the protection requested.
6847 * If specified, the page will be wired down, meaning
6848 * that the related pte can not be reclaimed.
6850 * NB: This is the only routine which MAY NOT lazy-evaluate
6851 * or lose information. That is, this routine must actually
6852 * insert this page into the given map NOW.
6854 * When destroying both a page table and PV entry, this function
6855 * performs the TLB invalidation before releasing the PV list
6856 * lock, so we do not need pmap_delayed_invl_page() calls here.
6859 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6860 u_int flags, int8_t psind)
6862 struct rwlock *lock;
6864 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6865 pt_entry_t newpte, origpte;
6872 PG_A = pmap_accessed_bit(pmap);
6873 PG_G = pmap_global_bit(pmap);
6874 PG_M = pmap_modified_bit(pmap);
6875 PG_V = pmap_valid_bit(pmap);
6876 PG_RW = pmap_rw_bit(pmap);
6878 va = trunc_page(va);
6879 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6880 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6881 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6883 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6884 va >= kmi.clean_eva,
6885 ("pmap_enter: managed mapping within the clean submap"));
6886 if ((m->oflags & VPO_UNMANAGED) == 0)
6887 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6888 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6889 ("pmap_enter: flags %u has reserved bits set", flags));
6890 pa = VM_PAGE_TO_PHYS(m);
6891 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6892 if ((flags & VM_PROT_WRITE) != 0)
6894 if ((prot & VM_PROT_WRITE) != 0)
6896 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6897 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6898 if ((prot & VM_PROT_EXECUTE) == 0)
6900 if ((flags & PMAP_ENTER_WIRED) != 0)
6902 if (va < VM_MAXUSER_ADDRESS)
6904 if (pmap == kernel_pmap)
6906 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6909 * Set modified bit gratuitously for writeable mappings if
6910 * the page is unmanaged. We do not want to take a fault
6911 * to do the dirty bit accounting for these mappings.
6913 if ((m->oflags & VPO_UNMANAGED) != 0) {
6914 if ((newpte & PG_RW) != 0)
6917 newpte |= PG_MANAGED;
6921 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6922 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6923 ("managed largepage va %#lx flags %#x", va, flags));
6924 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6929 /* Assert the required virtual and physical alignment. */
6930 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6931 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6932 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6938 * In the case that a page table page is not
6939 * resident, we are creating it here.
6942 pde = pmap_pde(pmap, va);
6943 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6944 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6945 pte = pmap_pde_to_pte(pde, va);
6946 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6947 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6950 } else if (va < VM_MAXUSER_ADDRESS) {
6952 * Here if the pte page isn't mapped, or if it has been
6955 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6956 mpte = pmap_allocpte_alloc(pmap, pmap_pde_pindex(va),
6957 nosleep ? NULL : &lock, va);
6958 if (mpte == NULL && nosleep) {
6959 rv = KERN_RESOURCE_SHORTAGE;
6964 panic("pmap_enter: invalid page directory va=%#lx", va);
6968 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6969 newpte |= pmap_pkru_get(pmap, va);
6972 * Is the specified virtual address already mapped?
6974 if ((origpte & PG_V) != 0) {
6976 * Wiring change, just update stats. We don't worry about
6977 * wiring PT pages as they remain resident as long as there
6978 * are valid mappings in them. Hence, if a user page is wired,
6979 * the PT page will be also.
6981 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6982 pmap->pm_stats.wired_count++;
6983 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6984 pmap->pm_stats.wired_count--;
6987 * Remove the extra PT page reference.
6991 KASSERT(mpte->ref_count > 0,
6992 ("pmap_enter: missing reference to page table page,"
6997 * Has the physical page changed?
6999 opa = origpte & PG_FRAME;
7002 * No, might be a protection or wiring change.
7004 if ((origpte & PG_MANAGED) != 0 &&
7005 (newpte & PG_RW) != 0)
7006 vm_page_aflag_set(m, PGA_WRITEABLE);
7007 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
7013 * The physical page has changed. Temporarily invalidate
7014 * the mapping. This ensures that all threads sharing the
7015 * pmap keep a consistent view of the mapping, which is
7016 * necessary for the correct handling of COW faults. It
7017 * also permits reuse of the old mapping's PV entry,
7018 * avoiding an allocation.
7020 * For consistency, handle unmanaged mappings the same way.
7022 origpte = pte_load_clear(pte);
7023 KASSERT((origpte & PG_FRAME) == opa,
7024 ("pmap_enter: unexpected pa update for %#lx", va));
7025 if ((origpte & PG_MANAGED) != 0) {
7026 om = PHYS_TO_VM_PAGE(opa);
7029 * The pmap lock is sufficient to synchronize with
7030 * concurrent calls to pmap_page_test_mappings() and
7031 * pmap_ts_referenced().
7033 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7035 if ((origpte & PG_A) != 0) {
7036 pmap_invalidate_page(pmap, va);
7037 vm_page_aflag_set(om, PGA_REFERENCED);
7039 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
7040 pv = pmap_pvh_remove(&om->md, pmap, va);
7042 ("pmap_enter: no PV entry for %#lx", va));
7043 if ((newpte & PG_MANAGED) == 0)
7044 free_pv_entry(pmap, pv);
7045 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
7046 TAILQ_EMPTY(&om->md.pv_list) &&
7047 ((om->flags & PG_FICTITIOUS) != 0 ||
7048 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
7049 vm_page_aflag_clear(om, PGA_WRITEABLE);
7052 * Since this mapping is unmanaged, assume that PG_A
7055 pmap_invalidate_page(pmap, va);
7060 * Increment the counters.
7062 if ((newpte & PG_W) != 0)
7063 pmap->pm_stats.wired_count++;
7064 pmap_resident_count_adj(pmap, 1);
7068 * Enter on the PV list if part of our managed memory.
7070 if ((newpte & PG_MANAGED) != 0) {
7072 pv = get_pv_entry(pmap, &lock);
7075 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
7076 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7078 if ((newpte & PG_RW) != 0)
7079 vm_page_aflag_set(m, PGA_WRITEABLE);
7085 if ((origpte & PG_V) != 0) {
7087 origpte = pte_load_store(pte, newpte);
7088 KASSERT((origpte & PG_FRAME) == pa,
7089 ("pmap_enter: unexpected pa update for %#lx", va));
7090 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
7092 if ((origpte & PG_MANAGED) != 0)
7096 * Although the PTE may still have PG_RW set, TLB
7097 * invalidation may nonetheless be required because
7098 * the PTE no longer has PG_M set.
7100 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
7102 * This PTE change does not require TLB invalidation.
7106 if ((origpte & PG_A) != 0)
7107 pmap_invalidate_page(pmap, va);
7109 pte_store(pte, newpte);
7113 #if VM_NRESERVLEVEL > 0
7115 * If both the page table page and the reservation are fully
7116 * populated, then attempt promotion.
7118 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
7119 pmap_ps_enabled(pmap) &&
7120 (m->flags & PG_FICTITIOUS) == 0 &&
7121 vm_reserv_level_iffullpop(m) == 0)
7122 pmap_promote_pde(pmap, pde, va, &lock);
7134 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
7135 * if successful. Returns false if (1) a page table page cannot be allocated
7136 * without sleeping, (2) a mapping already exists at the specified virtual
7137 * address, or (3) a PV entry cannot be allocated without reclaiming another
7141 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
7142 struct rwlock **lockp)
7147 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7148 PG_V = pmap_valid_bit(pmap);
7149 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
7151 if ((m->oflags & VPO_UNMANAGED) == 0)
7152 newpde |= PG_MANAGED;
7153 if ((prot & VM_PROT_EXECUTE) == 0)
7155 if (va < VM_MAXUSER_ADDRESS)
7157 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
7158 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
7163 * Returns true if every page table entry in the specified page table page is
7167 pmap_every_pte_zero(vm_paddr_t pa)
7169 pt_entry_t *pt_end, *pte;
7171 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
7172 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
7173 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
7181 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
7182 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
7183 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
7184 * a mapping already exists at the specified virtual address. Returns
7185 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
7186 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
7187 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
7189 * The parameter "m" is only used when creating a managed, writeable mapping.
7192 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
7193 vm_page_t m, struct rwlock **lockp)
7195 struct spglist free;
7196 pd_entry_t oldpde, *pde;
7197 pt_entry_t PG_G, PG_RW, PG_V;
7200 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
7201 ("pmap_enter_pde: cannot create wired user mapping"));
7202 PG_G = pmap_global_bit(pmap);
7203 PG_RW = pmap_rw_bit(pmap);
7204 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
7205 ("pmap_enter_pde: newpde is missing PG_M"));
7206 PG_V = pmap_valid_bit(pmap);
7207 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7209 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
7211 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
7212 " in pmap %p", va, pmap);
7213 return (KERN_FAILURE);
7215 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
7216 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
7217 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7218 " in pmap %p", va, pmap);
7219 return (KERN_RESOURCE_SHORTAGE);
7223 * If pkru is not same for the whole pde range, return failure
7224 * and let vm_fault() cope. Check after pde allocation, since
7227 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
7228 pmap_abort_ptp(pmap, va, pdpg);
7229 return (KERN_PROTECTION_FAILURE);
7231 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
7232 newpde &= ~X86_PG_PKU_MASK;
7233 newpde |= pmap_pkru_get(pmap, va);
7237 * If there are existing mappings, either abort or remove them.
7240 if ((oldpde & PG_V) != 0) {
7241 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
7242 ("pmap_enter_pde: pdpg's reference count is too low"));
7243 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
7244 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
7245 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
7248 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7249 " in pmap %p", va, pmap);
7250 return (KERN_FAILURE);
7252 /* Break the existing mapping(s). */
7254 if ((oldpde & PG_PS) != 0) {
7256 * The reference to the PD page that was acquired by
7257 * pmap_alloc_pde() ensures that it won't be freed.
7258 * However, if the PDE resulted from a promotion, then
7259 * a reserved PT page could be freed.
7261 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
7262 if ((oldpde & PG_G) == 0)
7263 pmap_invalidate_pde_page(pmap, va, oldpde);
7265 pmap_delayed_invl_start();
7266 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7268 pmap_invalidate_all(pmap);
7269 pmap_delayed_invl_finish();
7271 if (va < VM_MAXUSER_ADDRESS) {
7272 vm_page_free_pages_toq(&free, true);
7273 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7276 KASSERT(SLIST_EMPTY(&free),
7277 ("pmap_enter_pde: freed kernel page table page"));
7280 * Both pmap_remove_pde() and pmap_remove_ptes() will
7281 * leave the kernel page table page zero filled.
7283 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7284 if (pmap_insert_pt_page(pmap, mt, false))
7285 panic("pmap_enter_pde: trie insert failed");
7289 if ((newpde & PG_MANAGED) != 0) {
7291 * Abort this mapping if its PV entry could not be created.
7293 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7295 pmap_abort_ptp(pmap, va, pdpg);
7296 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7297 " in pmap %p", va, pmap);
7298 return (KERN_RESOURCE_SHORTAGE);
7300 if ((newpde & PG_RW) != 0) {
7301 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7302 vm_page_aflag_set(mt, PGA_WRITEABLE);
7307 * Increment counters.
7309 if ((newpde & PG_W) != 0)
7310 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7311 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7314 * Map the superpage. (This is not a promoted mapping; there will not
7315 * be any lingering 4KB page mappings in the TLB.)
7317 pde_store(pde, newpde);
7319 counter_u64_add(pmap_pde_mappings, 1);
7320 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7322 return (KERN_SUCCESS);
7326 * Maps a sequence of resident pages belonging to the same object.
7327 * The sequence begins with the given page m_start. This page is
7328 * mapped at the given virtual address start. Each subsequent page is
7329 * mapped at a virtual address that is offset from start by the same
7330 * amount as the page is offset from m_start within the object. The
7331 * last page in the sequence is the page with the largest offset from
7332 * m_start that can be mapped at a virtual address less than the given
7333 * virtual address end. Not every virtual page between start and end
7334 * is mapped; only those for which a resident page exists with the
7335 * corresponding offset from m_start are mapped.
7338 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7339 vm_page_t m_start, vm_prot_t prot)
7341 struct rwlock *lock;
7344 vm_pindex_t diff, psize;
7346 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7348 psize = atop(end - start);
7353 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7354 va = start + ptoa(diff);
7355 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7356 m->psind == 1 && pmap_ps_enabled(pmap) &&
7357 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7358 m = &m[NBPDR / PAGE_SIZE - 1];
7360 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7362 m = TAILQ_NEXT(m, listq);
7370 * this code makes some *MAJOR* assumptions:
7371 * 1. Current pmap & pmap exists.
7374 * 4. No page table pages.
7375 * but is *MUCH* faster than pmap_enter...
7379 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7381 struct rwlock *lock;
7385 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7392 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7393 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7395 pt_entry_t newpte, *pte, PG_V;
7397 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7398 (m->oflags & VPO_UNMANAGED) != 0,
7399 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7400 PG_V = pmap_valid_bit(pmap);
7401 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7404 * In the case that a page table page is not
7405 * resident, we are creating it here.
7407 if (va < VM_MAXUSER_ADDRESS) {
7408 vm_pindex_t ptepindex;
7412 * Calculate pagetable page index
7414 ptepindex = pmap_pde_pindex(va);
7415 if (mpte && (mpte->pindex == ptepindex)) {
7419 * Get the page directory entry
7421 ptepa = pmap_pde(pmap, va);
7424 * If the page table page is mapped, we just increment
7425 * the hold count, and activate it. Otherwise, we
7426 * attempt to allocate a page table page. If this
7427 * attempt fails, we don't retry. Instead, we give up.
7429 if (ptepa && (*ptepa & PG_V) != 0) {
7432 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7436 * Pass NULL instead of the PV list lock
7437 * pointer, because we don't intend to sleep.
7439 mpte = pmap_allocpte_alloc(pmap, ptepindex,
7445 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7446 pte = &pte[pmap_pte_index(va)];
7458 * Enter on the PV list if part of our managed memory.
7460 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7461 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7463 pmap_abort_ptp(pmap, va, mpte);
7468 * Increment counters
7470 pmap_resident_count_adj(pmap, 1);
7472 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7473 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7474 if ((m->oflags & VPO_UNMANAGED) == 0)
7475 newpte |= PG_MANAGED;
7476 if ((prot & VM_PROT_EXECUTE) == 0)
7478 if (va < VM_MAXUSER_ADDRESS)
7479 newpte |= PG_U | pmap_pkru_get(pmap, va);
7480 pte_store(pte, newpte);
7485 * Make a temporary mapping for a physical address. This is only intended
7486 * to be used for panic dumps.
7489 pmap_kenter_temporary(vm_paddr_t pa, int i)
7493 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7494 pmap_kenter(va, pa);
7496 return ((void *)crashdumpmap);
7500 * This code maps large physical mmap regions into the
7501 * processor address space. Note that some shortcuts
7502 * are taken, but the code works.
7505 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7506 vm_pindex_t pindex, vm_size_t size)
7509 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7510 vm_paddr_t pa, ptepa;
7514 PG_A = pmap_accessed_bit(pmap);
7515 PG_M = pmap_modified_bit(pmap);
7516 PG_V = pmap_valid_bit(pmap);
7517 PG_RW = pmap_rw_bit(pmap);
7519 VM_OBJECT_ASSERT_WLOCKED(object);
7520 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7521 ("pmap_object_init_pt: non-device object"));
7522 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7523 if (!pmap_ps_enabled(pmap))
7525 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7527 p = vm_page_lookup(object, pindex);
7528 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7529 ("pmap_object_init_pt: invalid page %p", p));
7530 pat_mode = p->md.pat_mode;
7533 * Abort the mapping if the first page is not physically
7534 * aligned to a 2MB page boundary.
7536 ptepa = VM_PAGE_TO_PHYS(p);
7537 if (ptepa & (NBPDR - 1))
7541 * Skip the first page. Abort the mapping if the rest of
7542 * the pages are not physically contiguous or have differing
7543 * memory attributes.
7545 p = TAILQ_NEXT(p, listq);
7546 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7548 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7549 ("pmap_object_init_pt: invalid page %p", p));
7550 if (pa != VM_PAGE_TO_PHYS(p) ||
7551 pat_mode != p->md.pat_mode)
7553 p = TAILQ_NEXT(p, listq);
7557 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7558 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7559 * will not affect the termination of this loop.
7562 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7563 pa < ptepa + size; pa += NBPDR) {
7564 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7567 * The creation of mappings below is only an
7568 * optimization. If a page directory page
7569 * cannot be allocated without blocking,
7570 * continue on to the next mapping rather than
7576 if ((*pde & PG_V) == 0) {
7577 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7578 PG_U | PG_RW | PG_V);
7579 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7580 counter_u64_add(pmap_pde_mappings, 1);
7582 /* Continue on if the PDE is already valid. */
7584 KASSERT(pdpg->ref_count > 0,
7585 ("pmap_object_init_pt: missing reference "
7586 "to page directory page, va: 0x%lx", addr));
7595 * Clear the wired attribute from the mappings for the specified range of
7596 * addresses in the given pmap. Every valid mapping within that range
7597 * must have the wired attribute set. In contrast, invalid mappings
7598 * cannot have the wired attribute set, so they are ignored.
7600 * The wired attribute of the page table entry is not a hardware
7601 * feature, so there is no need to invalidate any TLB entries.
7602 * Since pmap_demote_pde() for the wired entry must never fail,
7603 * pmap_delayed_invl_start()/finish() calls around the
7604 * function are not needed.
7607 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7609 vm_offset_t va_next;
7610 pml4_entry_t *pml4e;
7613 pt_entry_t *pte, PG_V, PG_G;
7615 PG_V = pmap_valid_bit(pmap);
7616 PG_G = pmap_global_bit(pmap);
7618 for (; sva < eva; sva = va_next) {
7619 pml4e = pmap_pml4e(pmap, sva);
7620 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7621 va_next = (sva + NBPML4) & ~PML4MASK;
7627 va_next = (sva + NBPDP) & ~PDPMASK;
7630 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7631 if ((*pdpe & PG_V) == 0)
7633 if ((*pdpe & PG_PS) != 0) {
7634 KASSERT(va_next <= eva,
7635 ("partial update of non-transparent 1G mapping "
7636 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7637 *pdpe, sva, eva, va_next));
7638 MPASS(pmap != kernel_pmap); /* XXXKIB */
7639 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7640 atomic_clear_long(pdpe, PG_W);
7641 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7645 va_next = (sva + NBPDR) & ~PDRMASK;
7648 pde = pmap_pdpe_to_pde(pdpe, sva);
7649 if ((*pde & PG_V) == 0)
7651 if ((*pde & PG_PS) != 0) {
7652 if ((*pde & PG_W) == 0)
7653 panic("pmap_unwire: pde %#jx is missing PG_W",
7657 * Are we unwiring the entire large page? If not,
7658 * demote the mapping and fall through.
7660 if (sva + NBPDR == va_next && eva >= va_next) {
7661 atomic_clear_long(pde, PG_W);
7662 pmap->pm_stats.wired_count -= NBPDR /
7665 } else if (!pmap_demote_pde(pmap, pde, sva))
7666 panic("pmap_unwire: demotion failed");
7670 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7672 if ((*pte & PG_V) == 0)
7674 if ((*pte & PG_W) == 0)
7675 panic("pmap_unwire: pte %#jx is missing PG_W",
7679 * PG_W must be cleared atomically. Although the pmap
7680 * lock synchronizes access to PG_W, another processor
7681 * could be setting PG_M and/or PG_A concurrently.
7683 atomic_clear_long(pte, PG_W);
7684 pmap->pm_stats.wired_count--;
7691 * Copy the range specified by src_addr/len
7692 * from the source map to the range dst_addr/len
7693 * in the destination map.
7695 * This routine is only advisory and need not do anything.
7698 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7699 vm_offset_t src_addr)
7701 struct rwlock *lock;
7702 pml4_entry_t *pml4e;
7704 pd_entry_t *pde, srcptepaddr;
7705 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7706 vm_offset_t addr, end_addr, va_next;
7707 vm_page_t dst_pdpg, dstmpte, srcmpte;
7709 if (dst_addr != src_addr)
7712 if (dst_pmap->pm_type != src_pmap->pm_type)
7716 * EPT page table entries that require emulation of A/D bits are
7717 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7718 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7719 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7720 * implementations flag an EPT misconfiguration for exec-only
7721 * mappings we skip this function entirely for emulated pmaps.
7723 if (pmap_emulate_ad_bits(dst_pmap))
7726 end_addr = src_addr + len;
7728 if (dst_pmap < src_pmap) {
7729 PMAP_LOCK(dst_pmap);
7730 PMAP_LOCK(src_pmap);
7732 PMAP_LOCK(src_pmap);
7733 PMAP_LOCK(dst_pmap);
7736 PG_A = pmap_accessed_bit(dst_pmap);
7737 PG_M = pmap_modified_bit(dst_pmap);
7738 PG_V = pmap_valid_bit(dst_pmap);
7740 for (addr = src_addr; addr < end_addr; addr = va_next) {
7741 KASSERT(addr < UPT_MIN_ADDRESS,
7742 ("pmap_copy: invalid to pmap_copy page tables"));
7744 pml4e = pmap_pml4e(src_pmap, addr);
7745 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7746 va_next = (addr + NBPML4) & ~PML4MASK;
7752 va_next = (addr + NBPDP) & ~PDPMASK;
7755 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7756 if ((*pdpe & PG_V) == 0)
7758 if ((*pdpe & PG_PS) != 0) {
7759 KASSERT(va_next <= end_addr,
7760 ("partial update of non-transparent 1G mapping "
7761 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7762 *pdpe, addr, end_addr, va_next));
7763 MPASS((addr & PDPMASK) == 0);
7764 MPASS((*pdpe & PG_MANAGED) == 0);
7765 srcptepaddr = *pdpe;
7766 pdpe = pmap_pdpe(dst_pmap, addr);
7768 if (pmap_allocpte_alloc(dst_pmap,
7769 pmap_pml4e_pindex(addr), NULL, addr) ==
7772 pdpe = pmap_pdpe(dst_pmap, addr);
7774 pml4e = pmap_pml4e(dst_pmap, addr);
7775 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7776 dst_pdpg->ref_count++;
7779 ("1G mapping present in dst pmap "
7780 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7781 *pdpe, addr, end_addr, va_next));
7782 *pdpe = srcptepaddr & ~PG_W;
7783 pmap_resident_count_adj(dst_pmap, NBPDP / PAGE_SIZE);
7787 va_next = (addr + NBPDR) & ~PDRMASK;
7791 pde = pmap_pdpe_to_pde(pdpe, addr);
7793 if (srcptepaddr == 0)
7796 if (srcptepaddr & PG_PS) {
7798 * We can only virtual copy whole superpages.
7800 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7802 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7805 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7806 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7807 PMAP_ENTER_NORECLAIM, &lock))) {
7809 * We leave the dirty bit unchanged because
7810 * managed read/write superpage mappings are
7811 * required to be dirty. However, managed
7812 * superpage mappings are not required to
7813 * have their accessed bit set, so we clear
7814 * it because we don't know if this mapping
7817 srcptepaddr &= ~PG_W;
7818 if ((srcptepaddr & PG_MANAGED) != 0)
7819 srcptepaddr &= ~PG_A;
7821 pmap_resident_count_adj(dst_pmap, NBPDR /
7823 counter_u64_add(pmap_pde_mappings, 1);
7825 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7829 srcptepaddr &= PG_FRAME;
7830 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7831 KASSERT(srcmpte->ref_count > 0,
7832 ("pmap_copy: source page table page is unused"));
7834 if (va_next > end_addr)
7837 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7838 src_pte = &src_pte[pmap_pte_index(addr)];
7840 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7844 * We only virtual copy managed pages.
7846 if ((ptetemp & PG_MANAGED) == 0)
7849 if (dstmpte != NULL) {
7850 KASSERT(dstmpte->pindex ==
7851 pmap_pde_pindex(addr),
7852 ("dstmpte pindex/addr mismatch"));
7853 dstmpte->ref_count++;
7854 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7857 dst_pte = (pt_entry_t *)
7858 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7859 dst_pte = &dst_pte[pmap_pte_index(addr)];
7860 if (*dst_pte == 0 &&
7861 pmap_try_insert_pv_entry(dst_pmap, addr,
7862 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7864 * Clear the wired, modified, and accessed
7865 * (referenced) bits during the copy.
7867 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7868 pmap_resident_count_adj(dst_pmap, 1);
7870 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7873 /* Have we copied all of the valid mappings? */
7874 if (dstmpte->ref_count >= srcmpte->ref_count)
7881 PMAP_UNLOCK(src_pmap);
7882 PMAP_UNLOCK(dst_pmap);
7886 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7890 if (dst_pmap->pm_type != src_pmap->pm_type ||
7891 dst_pmap->pm_type != PT_X86 ||
7892 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7895 if (dst_pmap < src_pmap) {
7896 PMAP_LOCK(dst_pmap);
7897 PMAP_LOCK(src_pmap);
7899 PMAP_LOCK(src_pmap);
7900 PMAP_LOCK(dst_pmap);
7902 error = pmap_pkru_copy(dst_pmap, src_pmap);
7903 /* Clean up partial copy on failure due to no memory. */
7904 if (error == ENOMEM)
7905 pmap_pkru_deassign_all(dst_pmap);
7906 PMAP_UNLOCK(src_pmap);
7907 PMAP_UNLOCK(dst_pmap);
7908 if (error != ENOMEM)
7916 * Zero the specified hardware page.
7919 pmap_zero_page(vm_page_t m)
7921 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7923 pagezero((void *)va);
7927 * Zero an an area within a single hardware page. off and size must not
7928 * cover an area beyond a single hardware page.
7931 pmap_zero_page_area(vm_page_t m, int off, int size)
7933 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7935 if (off == 0 && size == PAGE_SIZE)
7936 pagezero((void *)va);
7938 bzero((char *)va + off, size);
7942 * Copy 1 specified hardware page to another.
7945 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7947 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7948 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7950 pagecopy((void *)src, (void *)dst);
7953 int unmapped_buf_allowed = 1;
7956 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7957 vm_offset_t b_offset, int xfersize)
7961 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7965 while (xfersize > 0) {
7966 a_pg_offset = a_offset & PAGE_MASK;
7967 pages[0] = ma[a_offset >> PAGE_SHIFT];
7968 b_pg_offset = b_offset & PAGE_MASK;
7969 pages[1] = mb[b_offset >> PAGE_SHIFT];
7970 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7971 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7972 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7973 a_cp = (char *)vaddr[0] + a_pg_offset;
7974 b_cp = (char *)vaddr[1] + b_pg_offset;
7975 bcopy(a_cp, b_cp, cnt);
7976 if (__predict_false(mapped))
7977 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7985 * Returns true if the pmap's pv is one of the first
7986 * 16 pvs linked to from this page. This count may
7987 * be changed upwards or downwards in the future; it
7988 * is only necessary that true be returned for a small
7989 * subset of pmaps for proper page aging.
7992 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7994 struct md_page *pvh;
7995 struct rwlock *lock;
8000 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8001 ("pmap_page_exists_quick: page %p is not managed", m));
8003 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8005 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8006 if (PV_PMAP(pv) == pmap) {
8014 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
8015 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8016 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8017 if (PV_PMAP(pv) == pmap) {
8031 * pmap_page_wired_mappings:
8033 * Return the number of managed mappings to the given physical page
8037 pmap_page_wired_mappings(vm_page_t m)
8039 struct rwlock *lock;
8040 struct md_page *pvh;
8044 int count, md_gen, pvh_gen;
8046 if ((m->oflags & VPO_UNMANAGED) != 0)
8048 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8052 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8054 if (!PMAP_TRYLOCK(pmap)) {
8055 md_gen = m->md.pv_gen;
8059 if (md_gen != m->md.pv_gen) {
8064 pte = pmap_pte(pmap, pv->pv_va);
8065 if ((*pte & PG_W) != 0)
8069 if ((m->flags & PG_FICTITIOUS) == 0) {
8070 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8071 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8073 if (!PMAP_TRYLOCK(pmap)) {
8074 md_gen = m->md.pv_gen;
8075 pvh_gen = pvh->pv_gen;
8079 if (md_gen != m->md.pv_gen ||
8080 pvh_gen != pvh->pv_gen) {
8085 pte = pmap_pde(pmap, pv->pv_va);
8086 if ((*pte & PG_W) != 0)
8096 * Returns TRUE if the given page is mapped individually or as part of
8097 * a 2mpage. Otherwise, returns FALSE.
8100 pmap_page_is_mapped(vm_page_t m)
8102 struct rwlock *lock;
8105 if ((m->oflags & VPO_UNMANAGED) != 0)
8107 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8109 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
8110 ((m->flags & PG_FICTITIOUS) == 0 &&
8111 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
8117 * Destroy all managed, non-wired mappings in the given user-space
8118 * pmap. This pmap cannot be active on any processor besides the
8121 * This function cannot be applied to the kernel pmap. Moreover, it
8122 * is not intended for general use. It is only to be used during
8123 * process termination. Consequently, it can be implemented in ways
8124 * that make it faster than pmap_remove(). First, it can more quickly
8125 * destroy mappings by iterating over the pmap's collection of PV
8126 * entries, rather than searching the page table. Second, it doesn't
8127 * have to test and clear the page table entries atomically, because
8128 * no processor is currently accessing the user address space. In
8129 * particular, a page table entry's dirty bit won't change state once
8130 * this function starts.
8132 * Although this function destroys all of the pmap's managed,
8133 * non-wired mappings, it can delay and batch the invalidation of TLB
8134 * entries without calling pmap_delayed_invl_start() and
8135 * pmap_delayed_invl_finish(). Because the pmap is not active on
8136 * any other processor, none of these TLB entries will ever be used
8137 * before their eventual invalidation. Consequently, there is no need
8138 * for either pmap_remove_all() or pmap_remove_write() to wait for
8139 * that eventual TLB invalidation.
8142 pmap_remove_pages(pmap_t pmap)
8145 pt_entry_t *pte, tpte;
8146 pt_entry_t PG_M, PG_RW, PG_V;
8147 struct spglist free;
8148 struct pv_chunklist free_chunks[PMAP_MEMDOM];
8149 vm_page_t m, mpte, mt;
8151 struct md_page *pvh;
8152 struct pv_chunk *pc, *npc;
8153 struct rwlock *lock;
8155 uint64_t inuse, bitmask;
8156 int allfree, field, freed, i, idx;
8157 boolean_t superpage;
8161 * Assert that the given pmap is only active on the current
8162 * CPU. Unfortunately, we cannot block another CPU from
8163 * activating the pmap while this function is executing.
8165 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
8168 cpuset_t other_cpus;
8170 other_cpus = all_cpus;
8172 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
8173 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
8175 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
8180 PG_M = pmap_modified_bit(pmap);
8181 PG_V = pmap_valid_bit(pmap);
8182 PG_RW = pmap_rw_bit(pmap);
8184 for (i = 0; i < PMAP_MEMDOM; i++)
8185 TAILQ_INIT(&free_chunks[i]);
8188 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
8191 for (field = 0; field < _NPCM; field++) {
8192 inuse = ~pc->pc_map[field] & pc_freemask[field];
8193 while (inuse != 0) {
8195 bitmask = 1UL << bit;
8196 idx = field * 64 + bit;
8197 pv = &pc->pc_pventry[idx];
8200 pte = pmap_pdpe(pmap, pv->pv_va);
8202 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
8204 if ((tpte & (PG_PS | PG_V)) == PG_V) {
8207 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
8209 pte = &pte[pmap_pte_index(pv->pv_va)];
8213 * Keep track whether 'tpte' is a
8214 * superpage explicitly instead of
8215 * relying on PG_PS being set.
8217 * This is because PG_PS is numerically
8218 * identical to PG_PTE_PAT and thus a
8219 * regular page could be mistaken for
8225 if ((tpte & PG_V) == 0) {
8226 panic("bad pte va %lx pte %lx",
8231 * We cannot remove wired pages from a process' mapping at this time
8239 pc->pc_map[field] |= bitmask;
8242 * Because this pmap is not active on other
8243 * processors, the dirty bit cannot have
8244 * changed state since we last loaded pte.
8249 pa = tpte & PG_PS_FRAME;
8251 pa = tpte & PG_FRAME;
8253 m = PHYS_TO_VM_PAGE(pa);
8254 KASSERT(m->phys_addr == pa,
8255 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
8256 m, (uintmax_t)m->phys_addr,
8259 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
8260 m < &vm_page_array[vm_page_array_size],
8261 ("pmap_remove_pages: bad tpte %#jx",
8265 * Update the vm_page_t clean/reference bits.
8267 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8269 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8275 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
8278 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
8279 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
8280 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8282 if (TAILQ_EMPTY(&pvh->pv_list)) {
8283 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8284 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8285 TAILQ_EMPTY(&mt->md.pv_list))
8286 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8288 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8290 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8291 ("pmap_remove_pages: pte page not promoted"));
8292 pmap_resident_count_adj(pmap, -1);
8293 KASSERT(mpte->ref_count == NPTEPG,
8294 ("pmap_remove_pages: pte page reference count error"));
8295 mpte->ref_count = 0;
8296 pmap_add_delayed_free_list(mpte, &free, FALSE);
8299 pmap_resident_count_adj(pmap, -1);
8300 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8302 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8303 TAILQ_EMPTY(&m->md.pv_list) &&
8304 (m->flags & PG_FICTITIOUS) == 0) {
8305 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8306 if (TAILQ_EMPTY(&pvh->pv_list))
8307 vm_page_aflag_clear(m, PGA_WRITEABLE);
8310 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8314 PV_STAT(counter_u64_add(pv_entry_frees, freed));
8315 PV_STAT(counter_u64_add(pv_entry_spare, freed));
8316 PV_STAT(counter_u64_add(pv_entry_count, -freed));
8318 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8319 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8324 pmap_invalidate_all(pmap);
8325 pmap_pkru_deassign_all(pmap);
8326 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8328 vm_page_free_pages_toq(&free, true);
8332 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8334 struct rwlock *lock;
8336 struct md_page *pvh;
8337 pt_entry_t *pte, mask;
8338 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8340 int md_gen, pvh_gen;
8344 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8347 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8349 if (!PMAP_TRYLOCK(pmap)) {
8350 md_gen = m->md.pv_gen;
8354 if (md_gen != m->md.pv_gen) {
8359 pte = pmap_pte(pmap, pv->pv_va);
8362 PG_M = pmap_modified_bit(pmap);
8363 PG_RW = pmap_rw_bit(pmap);
8364 mask |= PG_RW | PG_M;
8367 PG_A = pmap_accessed_bit(pmap);
8368 PG_V = pmap_valid_bit(pmap);
8369 mask |= PG_V | PG_A;
8371 rv = (*pte & mask) == mask;
8376 if ((m->flags & PG_FICTITIOUS) == 0) {
8377 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8378 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8380 if (!PMAP_TRYLOCK(pmap)) {
8381 md_gen = m->md.pv_gen;
8382 pvh_gen = pvh->pv_gen;
8386 if (md_gen != m->md.pv_gen ||
8387 pvh_gen != pvh->pv_gen) {
8392 pte = pmap_pde(pmap, pv->pv_va);
8395 PG_M = pmap_modified_bit(pmap);
8396 PG_RW = pmap_rw_bit(pmap);
8397 mask |= PG_RW | PG_M;
8400 PG_A = pmap_accessed_bit(pmap);
8401 PG_V = pmap_valid_bit(pmap);
8402 mask |= PG_V | PG_A;
8404 rv = (*pte & mask) == mask;
8418 * Return whether or not the specified physical page was modified
8419 * in any physical maps.
8422 pmap_is_modified(vm_page_t m)
8425 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8426 ("pmap_is_modified: page %p is not managed", m));
8429 * If the page is not busied then this check is racy.
8431 if (!pmap_page_is_write_mapped(m))
8433 return (pmap_page_test_mappings(m, FALSE, TRUE));
8437 * pmap_is_prefaultable:
8439 * Return whether or not the specified virtual address is eligible
8443 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8446 pt_entry_t *pte, PG_V;
8449 PG_V = pmap_valid_bit(pmap);
8452 pde = pmap_pde(pmap, addr);
8453 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8454 pte = pmap_pde_to_pte(pde, addr);
8455 rv = (*pte & PG_V) == 0;
8462 * pmap_is_referenced:
8464 * Return whether or not the specified physical page was referenced
8465 * in any physical maps.
8468 pmap_is_referenced(vm_page_t m)
8471 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8472 ("pmap_is_referenced: page %p is not managed", m));
8473 return (pmap_page_test_mappings(m, TRUE, FALSE));
8477 * Clear the write and modified bits in each of the given page's mappings.
8480 pmap_remove_write(vm_page_t m)
8482 struct md_page *pvh;
8484 struct rwlock *lock;
8485 pv_entry_t next_pv, pv;
8487 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8489 int pvh_gen, md_gen;
8491 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8492 ("pmap_remove_write: page %p is not managed", m));
8494 vm_page_assert_busied(m);
8495 if (!pmap_page_is_write_mapped(m))
8498 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8499 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8500 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8503 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8505 if (!PMAP_TRYLOCK(pmap)) {
8506 pvh_gen = pvh->pv_gen;
8510 if (pvh_gen != pvh->pv_gen) {
8515 PG_RW = pmap_rw_bit(pmap);
8517 pde = pmap_pde(pmap, va);
8518 if ((*pde & PG_RW) != 0)
8519 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8520 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8521 ("inconsistent pv lock %p %p for page %p",
8522 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8525 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8527 if (!PMAP_TRYLOCK(pmap)) {
8528 pvh_gen = pvh->pv_gen;
8529 md_gen = m->md.pv_gen;
8533 if (pvh_gen != pvh->pv_gen ||
8534 md_gen != m->md.pv_gen) {
8539 PG_M = pmap_modified_bit(pmap);
8540 PG_RW = pmap_rw_bit(pmap);
8541 pde = pmap_pde(pmap, pv->pv_va);
8542 KASSERT((*pde & PG_PS) == 0,
8543 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8545 pte = pmap_pde_to_pte(pde, pv->pv_va);
8547 if (oldpte & PG_RW) {
8548 while (!atomic_fcmpset_long(pte, &oldpte, oldpte &
8551 if ((oldpte & PG_M) != 0)
8553 pmap_invalidate_page(pmap, pv->pv_va);
8558 vm_page_aflag_clear(m, PGA_WRITEABLE);
8559 pmap_delayed_invl_wait(m);
8562 static __inline boolean_t
8563 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8566 if (!pmap_emulate_ad_bits(pmap))
8569 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8572 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8573 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8574 * if the EPT_PG_WRITE bit is set.
8576 if ((pte & EPT_PG_WRITE) != 0)
8580 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8582 if ((pte & EPT_PG_EXECUTE) == 0 ||
8583 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8590 * pmap_ts_referenced:
8592 * Return a count of reference bits for a page, clearing those bits.
8593 * It is not necessary for every reference bit to be cleared, but it
8594 * is necessary that 0 only be returned when there are truly no
8595 * reference bits set.
8597 * As an optimization, update the page's dirty field if a modified bit is
8598 * found while counting reference bits. This opportunistic update can be
8599 * performed at low cost and can eliminate the need for some future calls
8600 * to pmap_is_modified(). However, since this function stops after
8601 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8602 * dirty pages. Those dirty pages will only be detected by a future call
8603 * to pmap_is_modified().
8605 * A DI block is not needed within this function, because
8606 * invalidations are performed before the PV list lock is
8610 pmap_ts_referenced(vm_page_t m)
8612 struct md_page *pvh;
8615 struct rwlock *lock;
8616 pd_entry_t oldpde, *pde;
8617 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8620 int cleared, md_gen, not_cleared, pvh_gen;
8621 struct spglist free;
8624 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8625 ("pmap_ts_referenced: page %p is not managed", m));
8628 pa = VM_PAGE_TO_PHYS(m);
8629 lock = PHYS_TO_PV_LIST_LOCK(pa);
8630 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8634 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8635 goto small_mappings;
8641 if (!PMAP_TRYLOCK(pmap)) {
8642 pvh_gen = pvh->pv_gen;
8646 if (pvh_gen != pvh->pv_gen) {
8651 PG_A = pmap_accessed_bit(pmap);
8652 PG_M = pmap_modified_bit(pmap);
8653 PG_RW = pmap_rw_bit(pmap);
8655 pde = pmap_pde(pmap, pv->pv_va);
8657 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8659 * Although "oldpde" is mapping a 2MB page, because
8660 * this function is called at a 4KB page granularity,
8661 * we only update the 4KB page under test.
8665 if ((oldpde & PG_A) != 0) {
8667 * Since this reference bit is shared by 512 4KB
8668 * pages, it should not be cleared every time it is
8669 * tested. Apply a simple "hash" function on the
8670 * physical page number, the virtual superpage number,
8671 * and the pmap address to select one 4KB page out of
8672 * the 512 on which testing the reference bit will
8673 * result in clearing that reference bit. This
8674 * function is designed to avoid the selection of the
8675 * same 4KB page for every 2MB page mapping.
8677 * On demotion, a mapping that hasn't been referenced
8678 * is simply destroyed. To avoid the possibility of a
8679 * subsequent page fault on a demoted wired mapping,
8680 * always leave its reference bit set. Moreover,
8681 * since the superpage is wired, the current state of
8682 * its reference bit won't affect page replacement.
8684 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8685 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8686 (oldpde & PG_W) == 0) {
8687 if (safe_to_clear_referenced(pmap, oldpde)) {
8688 atomic_clear_long(pde, PG_A);
8689 pmap_invalidate_page(pmap, pv->pv_va);
8691 } else if (pmap_demote_pde_locked(pmap, pde,
8692 pv->pv_va, &lock)) {
8694 * Remove the mapping to a single page
8695 * so that a subsequent access may
8696 * repromote. Since the underlying
8697 * page table page is fully populated,
8698 * this removal never frees a page
8702 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8704 pte = pmap_pde_to_pte(pde, va);
8705 pmap_remove_pte(pmap, pte, va, *pde,
8707 pmap_invalidate_page(pmap, va);
8713 * The superpage mapping was removed
8714 * entirely and therefore 'pv' is no
8722 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8723 ("inconsistent pv lock %p %p for page %p",
8724 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8729 /* Rotate the PV list if it has more than one entry. */
8730 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8731 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8732 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8735 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8737 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8739 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8746 if (!PMAP_TRYLOCK(pmap)) {
8747 pvh_gen = pvh->pv_gen;
8748 md_gen = m->md.pv_gen;
8752 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8757 PG_A = pmap_accessed_bit(pmap);
8758 PG_M = pmap_modified_bit(pmap);
8759 PG_RW = pmap_rw_bit(pmap);
8760 pde = pmap_pde(pmap, pv->pv_va);
8761 KASSERT((*pde & PG_PS) == 0,
8762 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8764 pte = pmap_pde_to_pte(pde, pv->pv_va);
8765 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8767 if ((*pte & PG_A) != 0) {
8768 if (safe_to_clear_referenced(pmap, *pte)) {
8769 atomic_clear_long(pte, PG_A);
8770 pmap_invalidate_page(pmap, pv->pv_va);
8772 } else if ((*pte & PG_W) == 0) {
8774 * Wired pages cannot be paged out so
8775 * doing accessed bit emulation for
8776 * them is wasted effort. We do the
8777 * hard work for unwired pages only.
8779 pmap_remove_pte(pmap, pte, pv->pv_va,
8780 *pde, &free, &lock);
8781 pmap_invalidate_page(pmap, pv->pv_va);
8786 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8787 ("inconsistent pv lock %p %p for page %p",
8788 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8793 /* Rotate the PV list if it has more than one entry. */
8794 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8795 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8796 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8799 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8800 not_cleared < PMAP_TS_REFERENCED_MAX);
8803 vm_page_free_pages_toq(&free, true);
8804 return (cleared + not_cleared);
8808 * Apply the given advice to the specified range of addresses within the
8809 * given pmap. Depending on the advice, clear the referenced and/or
8810 * modified flags in each mapping and set the mapped page's dirty field.
8813 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8815 struct rwlock *lock;
8816 pml4_entry_t *pml4e;
8818 pd_entry_t oldpde, *pde;
8819 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8820 vm_offset_t va, va_next;
8824 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8828 * A/D bit emulation requires an alternate code path when clearing
8829 * the modified and accessed bits below. Since this function is
8830 * advisory in nature we skip it entirely for pmaps that require
8831 * A/D bit emulation.
8833 if (pmap_emulate_ad_bits(pmap))
8836 PG_A = pmap_accessed_bit(pmap);
8837 PG_G = pmap_global_bit(pmap);
8838 PG_M = pmap_modified_bit(pmap);
8839 PG_V = pmap_valid_bit(pmap);
8840 PG_RW = pmap_rw_bit(pmap);
8842 pmap_delayed_invl_start();
8844 for (; sva < eva; sva = va_next) {
8845 pml4e = pmap_pml4e(pmap, sva);
8846 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8847 va_next = (sva + NBPML4) & ~PML4MASK;
8853 va_next = (sva + NBPDP) & ~PDPMASK;
8856 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8857 if ((*pdpe & PG_V) == 0)
8859 if ((*pdpe & PG_PS) != 0) {
8860 KASSERT(va_next <= eva,
8861 ("partial update of non-transparent 1G mapping "
8862 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8863 *pdpe, sva, eva, va_next));
8867 va_next = (sva + NBPDR) & ~PDRMASK;
8870 pde = pmap_pdpe_to_pde(pdpe, sva);
8872 if ((oldpde & PG_V) == 0)
8874 else if ((oldpde & PG_PS) != 0) {
8875 if ((oldpde & PG_MANAGED) == 0)
8878 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8883 * The large page mapping was destroyed.
8889 * Unless the page mappings are wired, remove the
8890 * mapping to a single page so that a subsequent
8891 * access may repromote. Choosing the last page
8892 * within the address range [sva, min(va_next, eva))
8893 * generally results in more repromotions. Since the
8894 * underlying page table page is fully populated, this
8895 * removal never frees a page table page.
8897 if ((oldpde & PG_W) == 0) {
8903 ("pmap_advise: no address gap"));
8904 pte = pmap_pde_to_pte(pde, va);
8905 KASSERT((*pte & PG_V) != 0,
8906 ("pmap_advise: invalid PTE"));
8907 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8917 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8919 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8921 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8922 if (advice == MADV_DONTNEED) {
8924 * Future calls to pmap_is_modified()
8925 * can be avoided by making the page
8928 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8931 atomic_clear_long(pte, PG_M | PG_A);
8932 } else if ((*pte & PG_A) != 0)
8933 atomic_clear_long(pte, PG_A);
8937 if ((*pte & PG_G) != 0) {
8944 if (va != va_next) {
8945 pmap_invalidate_range(pmap, va, sva);
8950 pmap_invalidate_range(pmap, va, sva);
8953 pmap_invalidate_all(pmap);
8955 pmap_delayed_invl_finish();
8959 * Clear the modify bits on the specified physical page.
8962 pmap_clear_modify(vm_page_t m)
8964 struct md_page *pvh;
8966 pv_entry_t next_pv, pv;
8967 pd_entry_t oldpde, *pde;
8968 pt_entry_t *pte, PG_M, PG_RW;
8969 struct rwlock *lock;
8971 int md_gen, pvh_gen;
8973 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8974 ("pmap_clear_modify: page %p is not managed", m));
8975 vm_page_assert_busied(m);
8977 if (!pmap_page_is_write_mapped(m))
8979 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8980 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8981 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8984 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8986 if (!PMAP_TRYLOCK(pmap)) {
8987 pvh_gen = pvh->pv_gen;
8991 if (pvh_gen != pvh->pv_gen) {
8996 PG_M = pmap_modified_bit(pmap);
8997 PG_RW = pmap_rw_bit(pmap);
8999 pde = pmap_pde(pmap, va);
9001 /* If oldpde has PG_RW set, then it also has PG_M set. */
9002 if ((oldpde & PG_RW) != 0 &&
9003 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
9004 (oldpde & PG_W) == 0) {
9006 * Write protect the mapping to a single page so that
9007 * a subsequent write access may repromote.
9009 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
9010 pte = pmap_pde_to_pte(pde, va);
9011 atomic_clear_long(pte, PG_M | PG_RW);
9013 pmap_invalidate_page(pmap, va);
9017 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
9019 if (!PMAP_TRYLOCK(pmap)) {
9020 md_gen = m->md.pv_gen;
9021 pvh_gen = pvh->pv_gen;
9025 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
9030 PG_M = pmap_modified_bit(pmap);
9031 PG_RW = pmap_rw_bit(pmap);
9032 pde = pmap_pde(pmap, pv->pv_va);
9033 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
9034 " a 2mpage in page %p's pv list", m));
9035 pte = pmap_pde_to_pte(pde, pv->pv_va);
9036 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
9037 atomic_clear_long(pte, PG_M);
9038 pmap_invalidate_page(pmap, pv->pv_va);
9046 * Miscellaneous support routines follow
9049 /* Adjust the properties for a leaf page table entry. */
9050 static __inline void
9051 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
9055 opte = *(u_long *)pte;
9057 npte = opte & ~mask;
9059 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
9064 * Map a set of physical memory pages into the kernel virtual
9065 * address space. Return a pointer to where it is mapped. This
9066 * routine is intended to be used for mapping device memory,
9070 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
9072 struct pmap_preinit_mapping *ppim;
9073 vm_offset_t va, offset;
9077 offset = pa & PAGE_MASK;
9078 size = round_page(offset + size);
9079 pa = trunc_page(pa);
9081 if (!pmap_initialized) {
9083 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9084 ppim = pmap_preinit_mapping + i;
9085 if (ppim->va == 0) {
9089 ppim->va = virtual_avail;
9090 virtual_avail += size;
9096 panic("%s: too many preinit mappings", __func__);
9099 * If we have a preinit mapping, re-use it.
9101 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9102 ppim = pmap_preinit_mapping + i;
9103 if (ppim->pa == pa && ppim->sz == size &&
9104 (ppim->mode == mode ||
9105 (flags & MAPDEV_SETATTR) == 0))
9106 return ((void *)(ppim->va + offset));
9109 * If the specified range of physical addresses fits within
9110 * the direct map window, use the direct map.
9112 if (pa < dmaplimit && pa + size <= dmaplimit) {
9113 va = PHYS_TO_DMAP(pa);
9114 if ((flags & MAPDEV_SETATTR) != 0) {
9115 PMAP_LOCK(kernel_pmap);
9116 i = pmap_change_props_locked(va, size,
9117 PROT_NONE, mode, flags);
9118 PMAP_UNLOCK(kernel_pmap);
9122 return ((void *)(va + offset));
9124 va = kva_alloc(size);
9126 panic("%s: Couldn't allocate KVA", __func__);
9128 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
9129 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
9130 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
9131 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9132 pmap_invalidate_cache_range(va, va + tmpsize);
9133 return ((void *)(va + offset));
9137 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
9140 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
9145 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
9148 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
9152 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
9155 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
9160 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
9163 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
9164 MAPDEV_FLUSHCACHE));
9168 pmap_unmapdev(vm_offset_t va, vm_size_t size)
9170 struct pmap_preinit_mapping *ppim;
9174 /* If we gave a direct map region in pmap_mapdev, do nothing */
9175 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
9177 offset = va & PAGE_MASK;
9178 size = round_page(offset + size);
9179 va = trunc_page(va);
9180 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9181 ppim = pmap_preinit_mapping + i;
9182 if (ppim->va == va && ppim->sz == size) {
9183 if (pmap_initialized)
9189 if (va + size == virtual_avail)
9194 if (pmap_initialized) {
9195 pmap_qremove(va, atop(size));
9201 * Tries to demote a 1GB page mapping.
9204 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
9206 pdp_entry_t newpdpe, oldpdpe;
9207 pd_entry_t *firstpde, newpde, *pde;
9208 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
9212 PG_A = pmap_accessed_bit(pmap);
9213 PG_M = pmap_modified_bit(pmap);
9214 PG_V = pmap_valid_bit(pmap);
9215 PG_RW = pmap_rw_bit(pmap);
9217 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9219 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
9220 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
9221 pdpg = pmap_alloc_pt_page(pmap, va >> PDPSHIFT,
9222 VM_ALLOC_WIRED | VM_ALLOC_INTERRUPT);
9224 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
9225 " in pmap %p", va, pmap);
9228 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
9229 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
9230 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
9231 KASSERT((oldpdpe & PG_A) != 0,
9232 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
9233 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
9234 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
9238 * Initialize the page directory page.
9240 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
9246 * Demote the mapping.
9251 * Invalidate a stale recursive mapping of the page directory page.
9253 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
9255 counter_u64_add(pmap_pdpe_demotions, 1);
9256 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
9257 " in pmap %p", va, pmap);
9262 * Sets the memory attribute for the specified page.
9265 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
9268 m->md.pat_mode = ma;
9271 * If "m" is a normal page, update its direct mapping. This update
9272 * can be relied upon to perform any cache operations that are
9273 * required for data coherence.
9275 if ((m->flags & PG_FICTITIOUS) == 0 &&
9276 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
9278 panic("memory attribute change on the direct map failed");
9282 pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma)
9286 m->md.pat_mode = ma;
9288 if ((m->flags & PG_FICTITIOUS) != 0)
9290 PMAP_LOCK(kernel_pmap);
9291 error = pmap_change_props_locked(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)),
9292 PAGE_SIZE, PROT_NONE, m->md.pat_mode, 0);
9293 PMAP_UNLOCK(kernel_pmap);
9295 panic("memory attribute change on the direct map failed");
9299 * Changes the specified virtual address range's memory type to that given by
9300 * the parameter "mode". The specified virtual address range must be
9301 * completely contained within either the direct map or the kernel map. If
9302 * the virtual address range is contained within the kernel map, then the
9303 * memory type for each of the corresponding ranges of the direct map is also
9304 * changed. (The corresponding ranges of the direct map are those ranges that
9305 * map the same physical pages as the specified virtual address range.) These
9306 * changes to the direct map are necessary because Intel describes the
9307 * behavior of their processors as "undefined" if two or more mappings to the
9308 * same physical page have different memory types.
9310 * Returns zero if the change completed successfully, and either EINVAL or
9311 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9312 * of the virtual address range was not mapped, and ENOMEM is returned if
9313 * there was insufficient memory available to complete the change. In the
9314 * latter case, the memory type may have been changed on some part of the
9315 * virtual address range or the direct map.
9318 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9322 PMAP_LOCK(kernel_pmap);
9323 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9325 PMAP_UNLOCK(kernel_pmap);
9330 * Changes the specified virtual address range's protections to those
9331 * specified by "prot". Like pmap_change_attr(), protections for aliases
9332 * in the direct map are updated as well. Protections on aliasing mappings may
9333 * be a subset of the requested protections; for example, mappings in the direct
9334 * map are never executable.
9337 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9341 /* Only supported within the kernel map. */
9342 if (va < VM_MIN_KERNEL_ADDRESS)
9345 PMAP_LOCK(kernel_pmap);
9346 error = pmap_change_props_locked(va, size, prot, -1,
9347 MAPDEV_ASSERTVALID);
9348 PMAP_UNLOCK(kernel_pmap);
9353 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9354 int mode, int flags)
9356 vm_offset_t base, offset, tmpva;
9357 vm_paddr_t pa_start, pa_end, pa_end1;
9359 pd_entry_t *pde, pde_bits, pde_mask;
9360 pt_entry_t *pte, pte_bits, pte_mask;
9364 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9365 base = trunc_page(va);
9366 offset = va & PAGE_MASK;
9367 size = round_page(offset + size);
9370 * Only supported on kernel virtual addresses, including the direct
9371 * map but excluding the recursive map.
9373 if (base < DMAP_MIN_ADDRESS)
9377 * Construct our flag sets and masks. "bits" is the subset of
9378 * "mask" that will be set in each modified PTE.
9380 * Mappings in the direct map are never allowed to be executable.
9382 pde_bits = pte_bits = 0;
9383 pde_mask = pte_mask = 0;
9385 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9386 pde_mask |= X86_PG_PDE_CACHE;
9387 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9388 pte_mask |= X86_PG_PTE_CACHE;
9390 if (prot != VM_PROT_NONE) {
9391 if ((prot & VM_PROT_WRITE) != 0) {
9392 pde_bits |= X86_PG_RW;
9393 pte_bits |= X86_PG_RW;
9395 if ((prot & VM_PROT_EXECUTE) == 0 ||
9396 va < VM_MIN_KERNEL_ADDRESS) {
9400 pde_mask |= X86_PG_RW | pg_nx;
9401 pte_mask |= X86_PG_RW | pg_nx;
9405 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9406 * into 4KB pages if required.
9408 for (tmpva = base; tmpva < base + size; ) {
9409 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9410 if (pdpe == NULL || *pdpe == 0) {
9411 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9412 ("%s: addr %#lx is not mapped", __func__, tmpva));
9415 if (*pdpe & PG_PS) {
9417 * If the current 1GB page already has the required
9418 * properties, then we need not demote this page. Just
9419 * increment tmpva to the next 1GB page frame.
9421 if ((*pdpe & pde_mask) == pde_bits) {
9422 tmpva = trunc_1gpage(tmpva) + NBPDP;
9427 * If the current offset aligns with a 1GB page frame
9428 * and there is at least 1GB left within the range, then
9429 * we need not break down this page into 2MB pages.
9431 if ((tmpva & PDPMASK) == 0 &&
9432 tmpva + PDPMASK < base + size) {
9436 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9439 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9441 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9442 ("%s: addr %#lx is not mapped", __func__, tmpva));
9447 * If the current 2MB page already has the required
9448 * properties, then we need not demote this page. Just
9449 * increment tmpva to the next 2MB page frame.
9451 if ((*pde & pde_mask) == pde_bits) {
9452 tmpva = trunc_2mpage(tmpva) + NBPDR;
9457 * If the current offset aligns with a 2MB page frame
9458 * and there is at least 2MB left within the range, then
9459 * we need not break down this page into 4KB pages.
9461 if ((tmpva & PDRMASK) == 0 &&
9462 tmpva + PDRMASK < base + size) {
9466 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9469 pte = pmap_pde_to_pte(pde, tmpva);
9471 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9472 ("%s: addr %#lx is not mapped", __func__, tmpva));
9480 * Ok, all the pages exist, so run through them updating their
9481 * properties if required.
9484 pa_start = pa_end = 0;
9485 for (tmpva = base; tmpva < base + size; ) {
9486 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9487 if (*pdpe & PG_PS) {
9488 if ((*pdpe & pde_mask) != pde_bits) {
9489 pmap_pte_props(pdpe, pde_bits, pde_mask);
9492 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9493 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9494 if (pa_start == pa_end) {
9495 /* Start physical address run. */
9496 pa_start = *pdpe & PG_PS_FRAME;
9497 pa_end = pa_start + NBPDP;
9498 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9501 /* Run ended, update direct map. */
9502 error = pmap_change_props_locked(
9503 PHYS_TO_DMAP(pa_start),
9504 pa_end - pa_start, prot, mode,
9508 /* Start physical address run. */
9509 pa_start = *pdpe & PG_PS_FRAME;
9510 pa_end = pa_start + NBPDP;
9513 tmpva = trunc_1gpage(tmpva) + NBPDP;
9516 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9518 if ((*pde & pde_mask) != pde_bits) {
9519 pmap_pte_props(pde, pde_bits, pde_mask);
9522 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9523 (*pde & PG_PS_FRAME) < dmaplimit) {
9524 if (pa_start == pa_end) {
9525 /* Start physical address run. */
9526 pa_start = *pde & PG_PS_FRAME;
9527 pa_end = pa_start + NBPDR;
9528 } else if (pa_end == (*pde & PG_PS_FRAME))
9531 /* Run ended, update direct map. */
9532 error = pmap_change_props_locked(
9533 PHYS_TO_DMAP(pa_start),
9534 pa_end - pa_start, prot, mode,
9538 /* Start physical address run. */
9539 pa_start = *pde & PG_PS_FRAME;
9540 pa_end = pa_start + NBPDR;
9543 tmpva = trunc_2mpage(tmpva) + NBPDR;
9545 pte = pmap_pde_to_pte(pde, tmpva);
9546 if ((*pte & pte_mask) != pte_bits) {
9547 pmap_pte_props(pte, pte_bits, pte_mask);
9550 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9551 (*pte & PG_FRAME) < dmaplimit) {
9552 if (pa_start == pa_end) {
9553 /* Start physical address run. */
9554 pa_start = *pte & PG_FRAME;
9555 pa_end = pa_start + PAGE_SIZE;
9556 } else if (pa_end == (*pte & PG_FRAME))
9557 pa_end += PAGE_SIZE;
9559 /* Run ended, update direct map. */
9560 error = pmap_change_props_locked(
9561 PHYS_TO_DMAP(pa_start),
9562 pa_end - pa_start, prot, mode,
9566 /* Start physical address run. */
9567 pa_start = *pte & PG_FRAME;
9568 pa_end = pa_start + PAGE_SIZE;
9574 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9575 pa_end1 = MIN(pa_end, dmaplimit);
9576 if (pa_start != pa_end1)
9577 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9578 pa_end1 - pa_start, prot, mode, flags);
9582 * Flush CPU caches if required to make sure any data isn't cached that
9583 * shouldn't be, etc.
9586 pmap_invalidate_range(kernel_pmap, base, tmpva);
9587 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9588 pmap_invalidate_cache_range(base, tmpva);
9594 * Demotes any mapping within the direct map region that covers more than the
9595 * specified range of physical addresses. This range's size must be a power
9596 * of two and its starting address must be a multiple of its size. Since the
9597 * demotion does not change any attributes of the mapping, a TLB invalidation
9598 * is not mandatory. The caller may, however, request a TLB invalidation.
9601 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9610 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9611 KASSERT((base & (len - 1)) == 0,
9612 ("pmap_demote_DMAP: base is not a multiple of len"));
9613 if (len < NBPDP && base < dmaplimit) {
9614 va = PHYS_TO_DMAP(base);
9616 PMAP_LOCK(kernel_pmap);
9617 pdpe = pmap_pdpe(kernel_pmap, va);
9618 if ((*pdpe & X86_PG_V) == 0)
9619 panic("pmap_demote_DMAP: invalid PDPE");
9620 if ((*pdpe & PG_PS) != 0) {
9621 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9622 panic("pmap_demote_DMAP: PDPE failed");
9626 pde = pmap_pdpe_to_pde(pdpe, va);
9627 if ((*pde & X86_PG_V) == 0)
9628 panic("pmap_demote_DMAP: invalid PDE");
9629 if ((*pde & PG_PS) != 0) {
9630 if (!pmap_demote_pde(kernel_pmap, pde, va))
9631 panic("pmap_demote_DMAP: PDE failed");
9635 if (changed && invalidate)
9636 pmap_invalidate_page(kernel_pmap, va);
9637 PMAP_UNLOCK(kernel_pmap);
9642 * Perform the pmap work for mincore(2). If the page is not both referenced and
9643 * modified by this pmap, returns its physical address so that the caller can
9644 * find other mappings.
9647 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9651 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9655 PG_A = pmap_accessed_bit(pmap);
9656 PG_M = pmap_modified_bit(pmap);
9657 PG_V = pmap_valid_bit(pmap);
9658 PG_RW = pmap_rw_bit(pmap);
9664 pdpe = pmap_pdpe(pmap, addr);
9667 if ((*pdpe & PG_V) != 0) {
9668 if ((*pdpe & PG_PS) != 0) {
9670 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9672 val = MINCORE_PSIND(2);
9674 pdep = pmap_pde(pmap, addr);
9675 if (pdep != NULL && (*pdep & PG_V) != 0) {
9676 if ((*pdep & PG_PS) != 0) {
9678 /* Compute the physical address of the 4KB page. */
9679 pa = ((pte & PG_PS_FRAME) | (addr &
9680 PDRMASK)) & PG_FRAME;
9681 val = MINCORE_PSIND(1);
9683 pte = *pmap_pde_to_pte(pdep, addr);
9684 pa = pte & PG_FRAME;
9690 if ((pte & PG_V) != 0) {
9691 val |= MINCORE_INCORE;
9692 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9693 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9694 if ((pte & PG_A) != 0)
9695 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9697 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9698 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9699 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9708 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9710 uint32_t gen, new_gen, pcid_next;
9712 CRITICAL_ASSERT(curthread);
9713 gen = PCPU_GET(pcid_gen);
9714 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9715 return (pti ? 0 : CR3_PCID_SAVE);
9716 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9717 return (CR3_PCID_SAVE);
9718 pcid_next = PCPU_GET(pcid_next);
9719 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9720 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9721 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9722 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9723 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9727 PCPU_SET(pcid_gen, new_gen);
9728 pcid_next = PMAP_PCID_KERN + 1;
9732 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9733 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9734 PCPU_SET(pcid_next, pcid_next + 1);
9739 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9743 cached = pmap_pcid_alloc(pmap, cpuid);
9744 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9745 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9746 pmap->pm_pcids[cpuid].pm_pcid));
9747 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9748 pmap == kernel_pmap,
9749 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9750 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9755 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9758 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9759 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9763 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9766 uint64_t cached, cr3, kcr3, ucr3;
9768 KASSERT((read_rflags() & PSL_I) == 0,
9769 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9771 /* See the comment in pmap_invalidate_page_pcid(). */
9772 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9773 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9774 old_pmap = PCPU_GET(curpmap);
9775 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9776 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9779 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9781 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9782 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9783 PCPU_SET(curpmap, pmap);
9784 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9785 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9788 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9789 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9791 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9792 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9794 counter_u64_add(pcid_save_cnt, 1);
9796 pmap_activate_sw_pti_post(td, pmap);
9800 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9803 uint64_t cached, cr3;
9805 KASSERT((read_rflags() & PSL_I) == 0,
9806 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9808 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9810 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9811 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9813 PCPU_SET(curpmap, pmap);
9815 counter_u64_add(pcid_save_cnt, 1);
9819 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9820 u_int cpuid __unused)
9823 load_cr3(pmap->pm_cr3);
9824 PCPU_SET(curpmap, pmap);
9828 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9829 u_int cpuid __unused)
9832 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9833 PCPU_SET(kcr3, pmap->pm_cr3);
9834 PCPU_SET(ucr3, pmap->pm_ucr3);
9835 pmap_activate_sw_pti_post(td, pmap);
9838 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9842 if (pmap_pcid_enabled && pti)
9843 return (pmap_activate_sw_pcid_pti);
9844 else if (pmap_pcid_enabled && !pti)
9845 return (pmap_activate_sw_pcid_nopti);
9846 else if (!pmap_pcid_enabled && pti)
9847 return (pmap_activate_sw_nopcid_pti);
9848 else /* if (!pmap_pcid_enabled && !pti) */
9849 return (pmap_activate_sw_nopcid_nopti);
9853 pmap_activate_sw(struct thread *td)
9855 pmap_t oldpmap, pmap;
9858 oldpmap = PCPU_GET(curpmap);
9859 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9860 if (oldpmap == pmap) {
9861 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9865 cpuid = PCPU_GET(cpuid);
9867 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9869 CPU_SET(cpuid, &pmap->pm_active);
9871 pmap_activate_sw_mode(td, pmap, cpuid);
9873 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9875 CPU_CLR(cpuid, &oldpmap->pm_active);
9880 pmap_activate(struct thread *td)
9883 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9884 * invalidate_all IPI, which checks for curpmap ==
9885 * smp_tlb_pmap. The below sequence of operations has a
9886 * window where %CR3 is loaded with the new pmap's PML4
9887 * address, but the curpmap value has not yet been updated.
9888 * This causes the invltlb IPI handler, which is called
9889 * between the updates, to execute as a NOP, which leaves
9890 * stale TLB entries.
9892 * Note that the most common use of pmap_activate_sw(), from
9893 * a context switch, is immune to this race, because
9894 * interrupts are disabled (while the thread lock is owned),
9895 * so the IPI is delayed until after curpmap is updated. Protect
9896 * other callers in a similar way, by disabling interrupts
9897 * around the %cr3 register reload and curpmap assignment.
9900 pmap_activate_sw(td);
9905 pmap_activate_boot(pmap_t pmap)
9911 * kernel_pmap must be never deactivated, and we ensure that
9912 * by never activating it at all.
9914 MPASS(pmap != kernel_pmap);
9916 cpuid = PCPU_GET(cpuid);
9918 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9920 CPU_SET(cpuid, &pmap->pm_active);
9922 PCPU_SET(curpmap, pmap);
9924 kcr3 = pmap->pm_cr3;
9925 if (pmap_pcid_enabled)
9926 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9930 PCPU_SET(kcr3, kcr3);
9931 PCPU_SET(ucr3, PMAP_NO_CR3);
9935 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9940 * Increase the starting virtual address of the given mapping if a
9941 * different alignment might result in more superpage mappings.
9944 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9945 vm_offset_t *addr, vm_size_t size)
9947 vm_offset_t superpage_offset;
9951 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9952 offset += ptoa(object->pg_color);
9953 superpage_offset = offset & PDRMASK;
9954 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9955 (*addr & PDRMASK) == superpage_offset)
9957 if ((*addr & PDRMASK) < superpage_offset)
9958 *addr = (*addr & ~PDRMASK) + superpage_offset;
9960 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9964 static unsigned long num_dirty_emulations;
9965 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9966 &num_dirty_emulations, 0, NULL);
9968 static unsigned long num_accessed_emulations;
9969 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9970 &num_accessed_emulations, 0, NULL);
9972 static unsigned long num_superpage_accessed_emulations;
9973 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9974 &num_superpage_accessed_emulations, 0, NULL);
9976 static unsigned long ad_emulation_superpage_promotions;
9977 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9978 &ad_emulation_superpage_promotions, 0, NULL);
9979 #endif /* INVARIANTS */
9982 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9985 struct rwlock *lock;
9986 #if VM_NRESERVLEVEL > 0
9990 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9992 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9993 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9995 if (!pmap_emulate_ad_bits(pmap))
9998 PG_A = pmap_accessed_bit(pmap);
9999 PG_M = pmap_modified_bit(pmap);
10000 PG_V = pmap_valid_bit(pmap);
10001 PG_RW = pmap_rw_bit(pmap);
10007 pde = pmap_pde(pmap, va);
10008 if (pde == NULL || (*pde & PG_V) == 0)
10011 if ((*pde & PG_PS) != 0) {
10012 if (ftype == VM_PROT_READ) {
10014 atomic_add_long(&num_superpage_accessed_emulations, 1);
10022 pte = pmap_pde_to_pte(pde, va);
10023 if ((*pte & PG_V) == 0)
10026 if (ftype == VM_PROT_WRITE) {
10027 if ((*pte & PG_RW) == 0)
10030 * Set the modified and accessed bits simultaneously.
10032 * Intel EPT PTEs that do software emulation of A/D bits map
10033 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
10034 * An EPT misconfiguration is triggered if the PTE is writable
10035 * but not readable (WR=10). This is avoided by setting PG_A
10036 * and PG_M simultaneously.
10038 *pte |= PG_M | PG_A;
10043 #if VM_NRESERVLEVEL > 0
10044 /* try to promote the mapping */
10045 if (va < VM_MAXUSER_ADDRESS)
10046 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
10050 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
10052 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
10053 pmap_ps_enabled(pmap) &&
10054 (m->flags & PG_FICTITIOUS) == 0 &&
10055 vm_reserv_level_iffullpop(m) == 0) {
10056 pmap_promote_pde(pmap, pde, va, &lock);
10058 atomic_add_long(&ad_emulation_superpage_promotions, 1);
10064 if (ftype == VM_PROT_WRITE)
10065 atomic_add_long(&num_dirty_emulations, 1);
10067 atomic_add_long(&num_accessed_emulations, 1);
10069 rv = 0; /* success */
10078 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
10080 pml4_entry_t *pml4;
10083 pt_entry_t *pte, PG_V;
10087 PG_V = pmap_valid_bit(pmap);
10090 pml4 = pmap_pml4e(pmap, va);
10093 ptr[idx++] = *pml4;
10094 if ((*pml4 & PG_V) == 0)
10097 pdp = pmap_pml4e_to_pdpe(pml4, va);
10099 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
10102 pde = pmap_pdpe_to_pde(pdp, va);
10104 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
10107 pte = pmap_pde_to_pte(pde, va);
10116 * Get the kernel virtual address of a set of physical pages. If there are
10117 * physical addresses not covered by the DMAP perform a transient mapping
10118 * that will be removed when calling pmap_unmap_io_transient.
10120 * \param page The pages the caller wishes to obtain the virtual
10121 * address on the kernel memory map.
10122 * \param vaddr On return contains the kernel virtual memory address
10123 * of the pages passed in the page parameter.
10124 * \param count Number of pages passed in.
10125 * \param can_fault TRUE if the thread using the mapped pages can take
10126 * page faults, FALSE otherwise.
10128 * \returns TRUE if the caller must call pmap_unmap_io_transient when
10129 * finished or FALSE otherwise.
10133 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10134 boolean_t can_fault)
10137 boolean_t needs_mapping;
10139 int cache_bits, error __unused, i;
10142 * Allocate any KVA space that we need, this is done in a separate
10143 * loop to prevent calling vmem_alloc while pinned.
10145 needs_mapping = FALSE;
10146 for (i = 0; i < count; i++) {
10147 paddr = VM_PAGE_TO_PHYS(page[i]);
10148 if (__predict_false(paddr >= dmaplimit)) {
10149 error = vmem_alloc(kernel_arena, PAGE_SIZE,
10150 M_BESTFIT | M_WAITOK, &vaddr[i]);
10151 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
10152 needs_mapping = TRUE;
10154 vaddr[i] = PHYS_TO_DMAP(paddr);
10158 /* Exit early if everything is covered by the DMAP */
10159 if (!needs_mapping)
10163 * NB: The sequence of updating a page table followed by accesses
10164 * to the corresponding pages used in the !DMAP case is subject to
10165 * the situation described in the "AMD64 Architecture Programmer's
10166 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
10167 * Coherency Considerations". Therefore, issuing the INVLPG right
10168 * after modifying the PTE bits is crucial.
10172 for (i = 0; i < count; i++) {
10173 paddr = VM_PAGE_TO_PHYS(page[i]);
10174 if (paddr >= dmaplimit) {
10177 * Slow path, since we can get page faults
10178 * while mappings are active don't pin the
10179 * thread to the CPU and instead add a global
10180 * mapping visible to all CPUs.
10182 pmap_qenter(vaddr[i], &page[i], 1);
10184 pte = vtopte(vaddr[i]);
10185 cache_bits = pmap_cache_bits(kernel_pmap,
10186 page[i]->md.pat_mode, 0);
10187 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
10194 return (needs_mapping);
10198 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10199 boolean_t can_fault)
10206 for (i = 0; i < count; i++) {
10207 paddr = VM_PAGE_TO_PHYS(page[i]);
10208 if (paddr >= dmaplimit) {
10210 pmap_qremove(vaddr[i], 1);
10211 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
10217 pmap_quick_enter_page(vm_page_t m)
10221 paddr = VM_PAGE_TO_PHYS(m);
10222 if (paddr < dmaplimit)
10223 return (PHYS_TO_DMAP(paddr));
10224 mtx_lock_spin(&qframe_mtx);
10225 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
10226 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
10227 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
10232 pmap_quick_remove_page(vm_offset_t addr)
10235 if (addr != qframe)
10237 pte_store(vtopte(qframe), 0);
10239 mtx_unlock_spin(&qframe_mtx);
10243 * Pdp pages from the large map are managed differently from either
10244 * kernel or user page table pages. They are permanently allocated at
10245 * initialization time, and their reference count is permanently set to
10246 * zero. The pml4 entries pointing to those pages are copied into
10247 * each allocated pmap.
10249 * In contrast, pd and pt pages are managed like user page table
10250 * pages. They are dynamically allocated, and their reference count
10251 * represents the number of valid entries within the page.
10254 pmap_large_map_getptp_unlocked(void)
10256 return (pmap_alloc_pt_page(kernel_pmap, 0, VM_ALLOC_ZERO));
10260 pmap_large_map_getptp(void)
10264 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
10265 m = pmap_large_map_getptp_unlocked();
10267 PMAP_UNLOCK(kernel_pmap);
10269 PMAP_LOCK(kernel_pmap);
10270 /* Callers retry. */
10275 static pdp_entry_t *
10276 pmap_large_map_pdpe(vm_offset_t va)
10278 vm_pindex_t pml4_idx;
10281 pml4_idx = pmap_pml4e_index(va);
10282 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
10283 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
10285 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10286 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
10287 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
10288 "LMSPML4I %#jx lm_ents %d",
10289 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10290 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
10291 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
10294 static pd_entry_t *
10295 pmap_large_map_pde(vm_offset_t va)
10302 pdpe = pmap_large_map_pdpe(va);
10304 m = pmap_large_map_getptp();
10307 mphys = VM_PAGE_TO_PHYS(m);
10308 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10310 MPASS((*pdpe & X86_PG_PS) == 0);
10311 mphys = *pdpe & PG_FRAME;
10313 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10316 static pt_entry_t *
10317 pmap_large_map_pte(vm_offset_t va)
10324 pde = pmap_large_map_pde(va);
10326 m = pmap_large_map_getptp();
10329 mphys = VM_PAGE_TO_PHYS(m);
10330 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10331 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10333 MPASS((*pde & X86_PG_PS) == 0);
10334 mphys = *pde & PG_FRAME;
10336 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10340 pmap_large_map_kextract(vm_offset_t va)
10342 pdp_entry_t *pdpe, pdp;
10343 pd_entry_t *pde, pd;
10344 pt_entry_t *pte, pt;
10346 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10347 ("not largemap range %#lx", (u_long)va));
10348 pdpe = pmap_large_map_pdpe(va);
10350 KASSERT((pdp & X86_PG_V) != 0,
10351 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10352 (u_long)pdpe, pdp));
10353 if ((pdp & X86_PG_PS) != 0) {
10354 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10355 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10356 (u_long)pdpe, pdp));
10357 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10359 pde = pmap_pdpe_to_pde(pdpe, va);
10361 KASSERT((pd & X86_PG_V) != 0,
10362 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10363 if ((pd & X86_PG_PS) != 0)
10364 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10365 pte = pmap_pde_to_pte(pde, va);
10367 KASSERT((pt & X86_PG_V) != 0,
10368 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10369 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10373 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10374 vmem_addr_t *vmem_res)
10378 * Large mappings are all but static. Consequently, there
10379 * is no point in waiting for an earlier allocation to be
10382 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10383 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10387 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10388 vm_memattr_t mattr)
10393 vm_offset_t va, inc;
10394 vmem_addr_t vmem_res;
10398 if (len == 0 || spa + len < spa)
10401 /* See if DMAP can serve. */
10402 if (spa + len <= dmaplimit) {
10403 va = PHYS_TO_DMAP(spa);
10404 *addr = (void *)va;
10405 return (pmap_change_attr(va, len, mattr));
10409 * No, allocate KVA. Fit the address with best possible
10410 * alignment for superpages. Fall back to worse align if
10414 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10415 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10416 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10418 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10420 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10423 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10428 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10429 * in the pagetable to minimize flushing. No need to
10430 * invalidate TLB, since we only update invalid entries.
10432 PMAP_LOCK(kernel_pmap);
10433 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10435 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10436 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10437 pdpe = pmap_large_map_pdpe(va);
10439 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10440 X86_PG_V | X86_PG_A | pg_nx |
10441 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10443 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10444 (va & PDRMASK) == 0) {
10445 pde = pmap_large_map_pde(va);
10447 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10448 X86_PG_V | X86_PG_A | pg_nx |
10449 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10450 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10454 pte = pmap_large_map_pte(va);
10456 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10457 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10459 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10464 PMAP_UNLOCK(kernel_pmap);
10467 *addr = (void *)vmem_res;
10472 pmap_large_unmap(void *svaa, vm_size_t len)
10474 vm_offset_t sva, va;
10476 pdp_entry_t *pdpe, pdp;
10477 pd_entry_t *pde, pd;
10480 struct spglist spgf;
10482 sva = (vm_offset_t)svaa;
10483 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10484 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10488 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10489 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10490 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10491 PMAP_LOCK(kernel_pmap);
10492 for (va = sva; va < sva + len; va += inc) {
10493 pdpe = pmap_large_map_pdpe(va);
10495 KASSERT((pdp & X86_PG_V) != 0,
10496 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10497 (u_long)pdpe, pdp));
10498 if ((pdp & X86_PG_PS) != 0) {
10499 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10500 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10501 (u_long)pdpe, pdp));
10502 KASSERT((va & PDPMASK) == 0,
10503 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10504 (u_long)pdpe, pdp));
10505 KASSERT(va + NBPDP <= sva + len,
10506 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10507 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10508 (u_long)pdpe, pdp, len));
10513 pde = pmap_pdpe_to_pde(pdpe, va);
10515 KASSERT((pd & X86_PG_V) != 0,
10516 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10518 if ((pd & X86_PG_PS) != 0) {
10519 KASSERT((va & PDRMASK) == 0,
10520 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10522 KASSERT(va + NBPDR <= sva + len,
10523 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10524 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10528 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10530 if (m->ref_count == 0) {
10532 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10536 pte = pmap_pde_to_pte(pde, va);
10537 KASSERT((*pte & X86_PG_V) != 0,
10538 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10539 (u_long)pte, *pte));
10542 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10544 if (m->ref_count == 0) {
10546 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10547 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10549 if (m->ref_count == 0) {
10551 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10555 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10556 PMAP_UNLOCK(kernel_pmap);
10557 vm_page_free_pages_toq(&spgf, false);
10558 vmem_free(large_vmem, sva, len);
10562 pmap_large_map_wb_fence_mfence(void)
10569 pmap_large_map_wb_fence_atomic(void)
10572 atomic_thread_fence_seq_cst();
10576 pmap_large_map_wb_fence_nop(void)
10580 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10583 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10584 return (pmap_large_map_wb_fence_mfence);
10585 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10586 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10587 return (pmap_large_map_wb_fence_atomic);
10589 /* clflush is strongly enough ordered */
10590 return (pmap_large_map_wb_fence_nop);
10594 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10597 for (; len > 0; len -= cpu_clflush_line_size,
10598 va += cpu_clflush_line_size)
10603 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10606 for (; len > 0; len -= cpu_clflush_line_size,
10607 va += cpu_clflush_line_size)
10612 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10615 for (; len > 0; len -= cpu_clflush_line_size,
10616 va += cpu_clflush_line_size)
10621 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10625 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10628 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10629 return (pmap_large_map_flush_range_clwb);
10630 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10631 return (pmap_large_map_flush_range_clflushopt);
10632 else if ((cpu_feature & CPUID_CLFSH) != 0)
10633 return (pmap_large_map_flush_range_clflush);
10635 return (pmap_large_map_flush_range_nop);
10639 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10641 volatile u_long *pe;
10647 for (va = sva; va < eva; va += inc) {
10649 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10650 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10652 if ((p & X86_PG_PS) != 0)
10656 pe = (volatile u_long *)pmap_large_map_pde(va);
10658 if ((p & X86_PG_PS) != 0)
10662 pe = (volatile u_long *)pmap_large_map_pte(va);
10666 seen_other = false;
10668 if ((p & X86_PG_AVAIL1) != 0) {
10670 * Spin-wait for the end of a parallel
10677 * If we saw other write-back
10678 * occuring, we cannot rely on PG_M to
10679 * indicate state of the cache. The
10680 * PG_M bit is cleared before the
10681 * flush to avoid ignoring new writes,
10682 * and writes which are relevant for
10683 * us might happen after.
10689 if ((p & X86_PG_M) != 0 || seen_other) {
10690 if (!atomic_fcmpset_long(pe, &p,
10691 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10693 * If we saw PG_M without
10694 * PG_AVAIL1, and then on the
10695 * next attempt we do not
10696 * observe either PG_M or
10697 * PG_AVAIL1, the other
10698 * write-back started after us
10699 * and finished before us. We
10700 * can rely on it doing our
10704 pmap_large_map_flush_range(va, inc);
10705 atomic_clear_long(pe, X86_PG_AVAIL1);
10714 * Write-back cache lines for the given address range.
10716 * Must be called only on the range or sub-range returned from
10717 * pmap_large_map(). Must not be called on the coalesced ranges.
10719 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10720 * instructions support.
10723 pmap_large_map_wb(void *svap, vm_size_t len)
10725 vm_offset_t eva, sva;
10727 sva = (vm_offset_t)svap;
10729 pmap_large_map_wb_fence();
10730 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10731 pmap_large_map_flush_range(sva, len);
10733 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10734 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10735 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10736 pmap_large_map_wb_large(sva, eva);
10738 pmap_large_map_wb_fence();
10742 pmap_pti_alloc_page(void)
10746 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10747 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10748 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10753 pmap_pti_free_page(vm_page_t m)
10756 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10757 if (!vm_page_unwire_noq(m))
10759 vm_page_free_zero(m);
10764 pmap_pti_init(void)
10773 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10774 VM_OBJECT_WLOCK(pti_obj);
10775 pml4_pg = pmap_pti_alloc_page();
10776 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10777 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10778 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10779 pdpe = pmap_pti_pdpe(va);
10780 pmap_pti_wire_pte(pdpe);
10782 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10783 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10784 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10785 sizeof(struct gate_descriptor) * NIDT, false);
10787 /* Doublefault stack IST 1 */
10788 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10789 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10790 /* NMI stack IST 2 */
10791 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10792 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10793 /* MC# stack IST 3 */
10794 va = __pcpu[i].pc_common_tss.tss_ist3 +
10795 sizeof(struct nmi_pcpu);
10796 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10797 /* DB# stack IST 4 */
10798 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10799 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10801 pmap_pti_add_kva_locked((vm_offset_t)KERNSTART, (vm_offset_t)etext,
10803 pti_finalized = true;
10804 VM_OBJECT_WUNLOCK(pti_obj);
10808 pmap_cpu_init(void *arg __unused)
10810 CPU_COPY(&all_cpus, &kernel_pmap->pm_active);
10813 SYSINIT(pmap_cpu, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_cpu_init, NULL);
10815 static pdp_entry_t *
10816 pmap_pti_pdpe(vm_offset_t va)
10818 pml4_entry_t *pml4e;
10821 vm_pindex_t pml4_idx;
10824 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10826 pml4_idx = pmap_pml4e_index(va);
10827 pml4e = &pti_pml4[pml4_idx];
10831 panic("pml4 alloc after finalization\n");
10832 m = pmap_pti_alloc_page();
10834 pmap_pti_free_page(m);
10835 mphys = *pml4e & ~PAGE_MASK;
10837 mphys = VM_PAGE_TO_PHYS(m);
10838 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10841 mphys = *pml4e & ~PAGE_MASK;
10843 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10848 pmap_pti_wire_pte(void *pte)
10852 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10853 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10858 pmap_pti_unwire_pde(void *pde, bool only_ref)
10862 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10863 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10864 MPASS(m->ref_count > 0);
10865 MPASS(only_ref || m->ref_count > 1);
10866 pmap_pti_free_page(m);
10870 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10875 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10876 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10877 MPASS(m->ref_count > 0);
10878 if (pmap_pti_free_page(m)) {
10879 pde = pmap_pti_pde(va);
10880 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10882 pmap_pti_unwire_pde(pde, false);
10886 static pd_entry_t *
10887 pmap_pti_pde(vm_offset_t va)
10892 vm_pindex_t pd_idx;
10895 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10897 pdpe = pmap_pti_pdpe(va);
10899 m = pmap_pti_alloc_page();
10901 pmap_pti_free_page(m);
10902 MPASS((*pdpe & X86_PG_PS) == 0);
10903 mphys = *pdpe & ~PAGE_MASK;
10905 mphys = VM_PAGE_TO_PHYS(m);
10906 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10909 MPASS((*pdpe & X86_PG_PS) == 0);
10910 mphys = *pdpe & ~PAGE_MASK;
10913 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10914 pd_idx = pmap_pde_index(va);
10919 static pt_entry_t *
10920 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10927 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10929 pde = pmap_pti_pde(va);
10930 if (unwire_pde != NULL) {
10931 *unwire_pde = true;
10932 pmap_pti_wire_pte(pde);
10935 m = pmap_pti_alloc_page();
10937 pmap_pti_free_page(m);
10938 MPASS((*pde & X86_PG_PS) == 0);
10939 mphys = *pde & ~(PAGE_MASK | pg_nx);
10941 mphys = VM_PAGE_TO_PHYS(m);
10942 *pde = mphys | X86_PG_RW | X86_PG_V;
10943 if (unwire_pde != NULL)
10944 *unwire_pde = false;
10947 MPASS((*pde & X86_PG_PS) == 0);
10948 mphys = *pde & ~(PAGE_MASK | pg_nx);
10951 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10952 pte += pmap_pte_index(va);
10958 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10962 pt_entry_t *pte, ptev;
10965 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10967 sva = trunc_page(sva);
10968 MPASS(sva > VM_MAXUSER_ADDRESS);
10969 eva = round_page(eva);
10971 for (; sva < eva; sva += PAGE_SIZE) {
10972 pte = pmap_pti_pte(sva, &unwire_pde);
10973 pa = pmap_kextract(sva);
10974 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10975 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10976 VM_MEMATTR_DEFAULT, FALSE);
10978 pte_store(pte, ptev);
10979 pmap_pti_wire_pte(pte);
10981 KASSERT(!pti_finalized,
10982 ("pti overlap after fin %#lx %#lx %#lx",
10984 KASSERT(*pte == ptev,
10985 ("pti non-identical pte after fin %#lx %#lx %#lx",
10989 pde = pmap_pti_pde(sva);
10990 pmap_pti_unwire_pde(pde, true);
10996 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
11001 VM_OBJECT_WLOCK(pti_obj);
11002 pmap_pti_add_kva_locked(sva, eva, exec);
11003 VM_OBJECT_WUNLOCK(pti_obj);
11007 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
11014 sva = rounddown2(sva, PAGE_SIZE);
11015 MPASS(sva > VM_MAXUSER_ADDRESS);
11016 eva = roundup2(eva, PAGE_SIZE);
11018 VM_OBJECT_WLOCK(pti_obj);
11019 for (va = sva; va < eva; va += PAGE_SIZE) {
11020 pte = pmap_pti_pte(va, NULL);
11021 KASSERT((*pte & X86_PG_V) != 0,
11022 ("invalid pte va %#lx pte %#lx pt %#lx", va,
11023 (u_long)pte, *pte));
11025 pmap_pti_unwire_pte(pte, va);
11027 pmap_invalidate_range(kernel_pmap, sva, eva);
11028 VM_OBJECT_WUNLOCK(pti_obj);
11032 pkru_dup_range(void *ctx __unused, void *data)
11034 struct pmap_pkru_range *node, *new_node;
11036 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11037 if (new_node == NULL)
11040 memcpy(new_node, node, sizeof(*node));
11045 pkru_free_range(void *ctx __unused, void *node)
11048 uma_zfree(pmap_pkru_ranges_zone, node);
11052 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11055 struct pmap_pkru_range *ppr;
11058 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11059 MPASS(pmap->pm_type == PT_X86);
11060 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11061 if ((flags & AMD64_PKRU_EXCL) != 0 &&
11062 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
11064 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11067 ppr->pkru_keyidx = keyidx;
11068 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
11069 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
11071 uma_zfree(pmap_pkru_ranges_zone, ppr);
11076 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11079 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11080 MPASS(pmap->pm_type == PT_X86);
11081 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11082 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
11086 pmap_pkru_deassign_all(pmap_t pmap)
11089 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11090 if (pmap->pm_type == PT_X86 &&
11091 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
11092 rangeset_remove_all(&pmap->pm_pkru);
11096 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11098 struct pmap_pkru_range *ppr, *prev_ppr;
11101 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11102 if (pmap->pm_type != PT_X86 ||
11103 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11104 sva >= VM_MAXUSER_ADDRESS)
11106 MPASS(eva <= VM_MAXUSER_ADDRESS);
11107 for (va = sva; va < eva; prev_ppr = ppr) {
11108 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11111 else if ((ppr == NULL) ^ (prev_ppr == NULL))
11117 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
11119 va = ppr->pkru_rs_el.re_end;
11125 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
11127 struct pmap_pkru_range *ppr;
11129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11130 if (pmap->pm_type != PT_X86 ||
11131 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11132 va >= VM_MAXUSER_ADDRESS)
11134 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11136 return (X86_PG_PKU(ppr->pkru_keyidx));
11141 pred_pkru_on_remove(void *ctx __unused, void *r)
11143 struct pmap_pkru_range *ppr;
11146 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
11150 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11153 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11154 if (pmap->pm_type == PT_X86 &&
11155 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
11156 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
11157 pred_pkru_on_remove);
11162 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
11165 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
11166 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
11167 MPASS(dst_pmap->pm_type == PT_X86);
11168 MPASS(src_pmap->pm_type == PT_X86);
11169 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11170 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
11172 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
11176 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11179 pml4_entry_t *pml4e;
11181 pd_entry_t newpde, ptpaddr, *pde;
11182 pt_entry_t newpte, *ptep, pte;
11183 vm_offset_t va, va_next;
11186 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11187 MPASS(pmap->pm_type == PT_X86);
11188 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
11190 for (changed = false, va = sva; va < eva; va = va_next) {
11191 pml4e = pmap_pml4e(pmap, va);
11192 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
11193 va_next = (va + NBPML4) & ~PML4MASK;
11199 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
11200 if ((*pdpe & X86_PG_V) == 0) {
11201 va_next = (va + NBPDP) & ~PDPMASK;
11207 va_next = (va + NBPDR) & ~PDRMASK;
11211 pde = pmap_pdpe_to_pde(pdpe, va);
11216 MPASS((ptpaddr & X86_PG_V) != 0);
11217 if ((ptpaddr & PG_PS) != 0) {
11218 if (va + NBPDR == va_next && eva >= va_next) {
11219 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
11220 X86_PG_PKU(keyidx);
11221 if (newpde != ptpaddr) {
11226 } else if (!pmap_demote_pde(pmap, pde, va)) {
11234 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
11235 ptep++, va += PAGE_SIZE) {
11237 if ((pte & X86_PG_V) == 0)
11239 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
11240 if (newpte != pte) {
11247 pmap_invalidate_range(pmap, sva, eva);
11251 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11252 u_int keyidx, int flags)
11255 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
11256 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
11258 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
11260 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
11266 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11271 sva = trunc_page(sva);
11272 eva = round_page(eva);
11273 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
11278 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
11280 pmap_pkru_update_range(pmap, sva, eva, keyidx);
11282 if (error != ENOMEM)
11290 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11294 sva = trunc_page(sva);
11295 eva = round_page(eva);
11296 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
11301 error = pmap_pkru_deassign(pmap, sva, eva);
11303 pmap_pkru_update_range(pmap, sva, eva, 0);
11305 if (error != ENOMEM)
11314 pmap_kasan_enter_alloc_4k(void)
11318 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
11321 panic("%s: no memory to grow shadow map", __func__);
11326 pmap_kasan_enter_alloc_2m(void)
11328 return (vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO,
11329 NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT));
11333 * Grow the shadow map by at least one 4KB page at the specified address. Use
11334 * 2MB pages when possible.
11337 pmap_kasan_enter(vm_offset_t va)
11344 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11346 pdpe = pmap_pdpe(kernel_pmap, va);
11347 if ((*pdpe & X86_PG_V) == 0) {
11348 m = pmap_kasan_enter_alloc_4k();
11349 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11352 pde = pmap_pdpe_to_pde(pdpe, va);
11353 if ((*pde & X86_PG_V) == 0) {
11354 m = pmap_kasan_enter_alloc_2m();
11356 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11357 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx);
11359 m = pmap_kasan_enter_alloc_4k();
11360 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11364 if ((*pde & X86_PG_PS) != 0)
11366 pte = pmap_pde_to_pte(pde, va);
11367 if ((*pte & X86_PG_V) != 0)
11369 m = pmap_kasan_enter_alloc_4k();
11370 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11371 X86_PG_M | X86_PG_A | pg_nx);
11377 pmap_kmsan_enter_alloc_4k(void)
11381 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
11384 panic("%s: no memory to grow shadow map", __func__);
11389 pmap_kmsan_enter_alloc_2m(void)
11391 return (vm_page_alloc_noobj_contig(VM_ALLOC_ZERO | VM_ALLOC_WIRED,
11392 NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT));
11396 * Grow the shadow or origin maps by at least one 4KB page at the specified
11397 * address. Use 2MB pages when possible.
11400 pmap_kmsan_enter(vm_offset_t va)
11407 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11409 pdpe = pmap_pdpe(kernel_pmap, va);
11410 if ((*pdpe & X86_PG_V) == 0) {
11411 m = pmap_kmsan_enter_alloc_4k();
11412 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11415 pde = pmap_pdpe_to_pde(pdpe, va);
11416 if ((*pde & X86_PG_V) == 0) {
11417 m = pmap_kmsan_enter_alloc_2m();
11419 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11420 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx);
11422 m = pmap_kmsan_enter_alloc_4k();
11423 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11427 if ((*pde & X86_PG_PS) != 0)
11429 pte = pmap_pde_to_pte(pde, va);
11430 if ((*pte & X86_PG_V) != 0)
11432 m = pmap_kmsan_enter_alloc_4k();
11433 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11434 X86_PG_M | X86_PG_A | pg_nx);
11439 * Track a range of the kernel's virtual address space that is contiguous
11440 * in various mapping attributes.
11442 struct pmap_kernel_map_range {
11451 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11457 if (eva <= range->sva)
11460 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11461 for (i = 0; i < PAT_INDEX_SIZE; i++)
11462 if (pat_index[i] == pat_idx)
11466 case PAT_WRITE_BACK:
11469 case PAT_WRITE_THROUGH:
11472 case PAT_UNCACHEABLE:
11478 case PAT_WRITE_PROTECTED:
11481 case PAT_WRITE_COMBINING:
11485 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11486 __func__, pat_idx, range->sva, eva);
11491 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11493 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11494 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11495 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11496 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11497 mode, range->pdpes, range->pdes, range->ptes);
11499 /* Reset to sentinel value. */
11500 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11501 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11502 NPDEPG - 1, NPTEPG - 1);
11506 * Determine whether the attributes specified by a page table entry match those
11507 * being tracked by the current range. This is not quite as simple as a direct
11508 * flag comparison since some PAT modes have multiple representations.
11511 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11513 pt_entry_t diff, mask;
11515 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11516 diff = (range->attrs ^ attrs) & mask;
11519 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11520 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11521 pmap_pat_index(kernel_pmap, attrs, true))
11527 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11531 memset(range, 0, sizeof(*range));
11533 range->attrs = attrs;
11537 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11538 * those of the current run, dump the address range and its attributes, and
11542 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11543 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11548 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11550 attrs |= pdpe & pg_nx;
11551 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11552 if ((pdpe & PG_PS) != 0) {
11553 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11554 } else if (pde != 0) {
11555 attrs |= pde & pg_nx;
11556 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11558 if ((pde & PG_PS) != 0) {
11559 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11560 } else if (pte != 0) {
11561 attrs |= pte & pg_nx;
11562 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11563 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11565 /* Canonicalize by always using the PDE PAT bit. */
11566 if ((attrs & X86_PG_PTE_PAT) != 0)
11567 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11570 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11571 sysctl_kmaps_dump(sb, range, va);
11572 sysctl_kmaps_reinit(range, va, attrs);
11577 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11579 struct pmap_kernel_map_range range;
11580 struct sbuf sbuf, *sb;
11581 pml4_entry_t pml4e;
11582 pdp_entry_t *pdp, pdpe;
11583 pd_entry_t *pd, pde;
11584 pt_entry_t *pt, pte;
11587 int error, i, j, k, l;
11589 error = sysctl_wire_old_buffer(req, 0);
11593 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11595 /* Sentinel value. */
11596 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11597 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11598 NPDEPG - 1, NPTEPG - 1);
11601 * Iterate over the kernel page tables without holding the kernel pmap
11602 * lock. Outside of the large map, kernel page table pages are never
11603 * freed, so at worst we will observe inconsistencies in the output.
11604 * Within the large map, ensure that PDP and PD page addresses are
11605 * valid before descending.
11607 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11610 sbuf_printf(sb, "\nRecursive map:\n");
11613 sbuf_printf(sb, "\nDirect map:\n");
11617 sbuf_printf(sb, "\nKASAN shadow map:\n");
11621 case KMSANSHADPML4I:
11622 sbuf_printf(sb, "\nKMSAN shadow map:\n");
11624 case KMSANORIGPML4I:
11625 sbuf_printf(sb, "\nKMSAN origin map:\n");
11629 sbuf_printf(sb, "\nKernel map:\n");
11632 sbuf_printf(sb, "\nLarge map:\n");
11636 /* Convert to canonical form. */
11637 if (sva == 1ul << 47)
11641 pml4e = kernel_pml4[i];
11642 if ((pml4e & X86_PG_V) == 0) {
11643 sva = rounddown2(sva, NBPML4);
11644 sysctl_kmaps_dump(sb, &range, sva);
11648 pa = pml4e & PG_FRAME;
11649 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11651 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11653 if ((pdpe & X86_PG_V) == 0) {
11654 sva = rounddown2(sva, NBPDP);
11655 sysctl_kmaps_dump(sb, &range, sva);
11659 pa = pdpe & PG_FRAME;
11660 if ((pdpe & PG_PS) != 0) {
11661 sva = rounddown2(sva, NBPDP);
11662 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11668 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11669 vm_phys_paddr_to_vm_page(pa) == NULL) {
11671 * Page table pages for the large map may be
11672 * freed. Validate the next-level address
11673 * before descending.
11677 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11679 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11681 if ((pde & X86_PG_V) == 0) {
11682 sva = rounddown2(sva, NBPDR);
11683 sysctl_kmaps_dump(sb, &range, sva);
11687 pa = pde & PG_FRAME;
11688 if ((pde & PG_PS) != 0) {
11689 sva = rounddown2(sva, NBPDR);
11690 sysctl_kmaps_check(sb, &range, sva,
11691 pml4e, pdpe, pde, 0);
11696 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11697 vm_phys_paddr_to_vm_page(pa) == NULL) {
11699 * Page table pages for the large map
11700 * may be freed. Validate the
11701 * next-level address before descending.
11705 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11707 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11708 sva += PAGE_SIZE) {
11710 if ((pte & X86_PG_V) == 0) {
11711 sysctl_kmaps_dump(sb, &range,
11715 sysctl_kmaps_check(sb, &range, sva,
11716 pml4e, pdpe, pde, pte);
11723 error = sbuf_finish(sb);
11727 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11728 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
11729 NULL, 0, sysctl_kmaps, "A",
11730 "Dump kernel address layout");
11733 DB_SHOW_COMMAND(pte, pmap_print_pte)
11736 pml5_entry_t *pml5;
11737 pml4_entry_t *pml4;
11740 pt_entry_t *pte, PG_V;
11744 db_printf("show pte addr\n");
11747 va = (vm_offset_t)addr;
11749 if (kdb_thread != NULL)
11750 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11752 pmap = PCPU_GET(curpmap);
11754 PG_V = pmap_valid_bit(pmap);
11755 db_printf("VA 0x%016lx", va);
11757 if (pmap_is_la57(pmap)) {
11758 pml5 = pmap_pml5e(pmap, va);
11759 db_printf(" pml5e 0x%016lx", *pml5);
11760 if ((*pml5 & PG_V) == 0) {
11764 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11766 pml4 = pmap_pml4e(pmap, va);
11768 db_printf(" pml4e 0x%016lx", *pml4);
11769 if ((*pml4 & PG_V) == 0) {
11773 pdp = pmap_pml4e_to_pdpe(pml4, va);
11774 db_printf(" pdpe 0x%016lx", *pdp);
11775 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11779 pde = pmap_pdpe_to_pde(pdp, va);
11780 db_printf(" pde 0x%016lx", *pde);
11781 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11785 pte = pmap_pde_to_pte(pde, va);
11786 db_printf(" pte 0x%016lx\n", *pte);
11789 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11794 a = (vm_paddr_t)addr;
11795 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11797 db_printf("show phys2dmap addr\n");
11802 ptpages_show_page(int level, int idx, vm_page_t pg)
11804 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11805 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11809 ptpages_show_complain(int level, int idx, uint64_t pte)
11811 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11815 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11817 vm_page_t pg3, pg2, pg1;
11818 pml4_entry_t *pml4;
11823 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11824 for (i4 = 0; i4 < num_entries; i4++) {
11825 if ((pml4[i4] & PG_V) == 0)
11827 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11829 ptpages_show_complain(3, i4, pml4[i4]);
11832 ptpages_show_page(3, i4, pg3);
11833 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11834 for (i3 = 0; i3 < NPDPEPG; i3++) {
11835 if ((pdp[i3] & PG_V) == 0)
11837 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11839 ptpages_show_complain(2, i3, pdp[i3]);
11842 ptpages_show_page(2, i3, pg2);
11843 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11844 for (i2 = 0; i2 < NPDEPG; i2++) {
11845 if ((pd[i2] & PG_V) == 0)
11847 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11849 ptpages_show_complain(1, i2, pd[i2]);
11852 ptpages_show_page(1, i2, pg1);
11858 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11862 pml5_entry_t *pml5;
11867 pmap = (pmap_t)addr;
11869 pmap = PCPU_GET(curpmap);
11871 PG_V = pmap_valid_bit(pmap);
11873 if (pmap_is_la57(pmap)) {
11874 pml5 = pmap->pm_pmltop;
11875 for (i5 = 0; i5 < NUPML5E; i5++) {
11876 if ((pml5[i5] & PG_V) == 0)
11878 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11880 ptpages_show_complain(4, i5, pml5[i5]);
11883 ptpages_show_page(4, i5, pg);
11884 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11887 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11888 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);