2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/asan.h>
116 #include <sys/bitstring.h>
118 #include <sys/systm.h>
119 #include <sys/counter.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/malloc.h>
124 #include <sys/mman.h>
125 #include <sys/msan.h>
126 #include <sys/mutex.h>
127 #include <sys/proc.h>
128 #include <sys/rangeset.h>
129 #include <sys/rwlock.h>
130 #include <sys/sbuf.h>
133 #include <sys/turnstile.h>
134 #include <sys/vmem.h>
135 #include <sys/vmmeter.h>
136 #include <sys/sched.h>
137 #include <sys/sysctl.h>
145 #include <vm/vm_param.h>
146 #include <vm/vm_kern.h>
147 #include <vm/vm_page.h>
148 #include <vm/vm_map.h>
149 #include <vm/vm_object.h>
150 #include <vm/vm_extern.h>
151 #include <vm/vm_pageout.h>
152 #include <vm/vm_pager.h>
153 #include <vm/vm_phys.h>
154 #include <vm/vm_radix.h>
155 #include <vm/vm_reserv.h>
156 #include <vm/vm_dumpset.h>
159 #include <machine/asan.h>
160 #include <machine/intr_machdep.h>
161 #include <x86/apicvar.h>
162 #include <x86/ifunc.h>
163 #include <machine/cpu.h>
164 #include <machine/cputypes.h>
165 #include <machine/md_var.h>
166 #include <machine/msan.h>
167 #include <machine/pcb.h>
168 #include <machine/specialreg.h>
170 #include <machine/smp.h>
172 #include <machine/sysarch.h>
173 #include <machine/tss.h>
176 #define PMAP_MEMDOM MAXMEMDOM
178 #define PMAP_MEMDOM 1
181 static __inline boolean_t
182 pmap_type_guest(pmap_t pmap)
185 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
188 static __inline boolean_t
189 pmap_emulate_ad_bits(pmap_t pmap)
192 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
195 static __inline pt_entry_t
196 pmap_valid_bit(pmap_t pmap)
200 switch (pmap->pm_type) {
206 if (pmap_emulate_ad_bits(pmap))
207 mask = EPT_PG_EMUL_V;
212 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
218 static __inline pt_entry_t
219 pmap_rw_bit(pmap_t pmap)
223 switch (pmap->pm_type) {
229 if (pmap_emulate_ad_bits(pmap))
230 mask = EPT_PG_EMUL_RW;
235 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
241 static pt_entry_t pg_g;
243 static __inline pt_entry_t
244 pmap_global_bit(pmap_t pmap)
248 switch (pmap->pm_type) {
257 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
263 static __inline pt_entry_t
264 pmap_accessed_bit(pmap_t pmap)
268 switch (pmap->pm_type) {
274 if (pmap_emulate_ad_bits(pmap))
280 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
286 static __inline pt_entry_t
287 pmap_modified_bit(pmap_t pmap)
291 switch (pmap->pm_type) {
297 if (pmap_emulate_ad_bits(pmap))
303 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
309 static __inline pt_entry_t
310 pmap_pku_mask_bit(pmap_t pmap)
313 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
316 #if !defined(DIAGNOSTIC)
317 #ifdef __GNUC_GNU_INLINE__
318 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
320 #define PMAP_INLINE extern inline
327 #define PV_STAT(x) do { x ; } while (0)
329 #define PV_STAT(x) do { } while (0)
334 #define pa_index(pa) ({ \
335 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
336 ("address %lx beyond the last segment", (pa))); \
339 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
340 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
341 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
342 struct rwlock *_lock; \
343 if (__predict_false((pa) > pmap_last_pa)) \
344 _lock = &pv_dummy_large.pv_lock; \
346 _lock = &(pa_to_pmdp(pa)->pv_lock); \
350 #define pa_index(pa) ((pa) >> PDRSHIFT)
351 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
353 #define NPV_LIST_LOCKS MAXCPU
355 #define PHYS_TO_PV_LIST_LOCK(pa) \
356 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
359 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
360 struct rwlock **_lockp = (lockp); \
361 struct rwlock *_new_lock; \
363 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
364 if (_new_lock != *_lockp) { \
365 if (*_lockp != NULL) \
366 rw_wunlock(*_lockp); \
367 *_lockp = _new_lock; \
372 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
373 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
375 #define RELEASE_PV_LIST_LOCK(lockp) do { \
376 struct rwlock **_lockp = (lockp); \
378 if (*_lockp != NULL) { \
379 rw_wunlock(*_lockp); \
384 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
385 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
387 struct pmap kernel_pmap_store;
389 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
390 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
393 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
394 "Number of kernel page table pages allocated on bootup");
397 vm_paddr_t dmaplimit;
398 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
401 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
402 "VM/pmap parameters");
404 static int pg_ps_enabled = 1;
405 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
406 &pg_ps_enabled, 0, "Are large page mappings enabled?");
408 int __read_frequently la57 = 0;
409 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
411 "5-level paging for host is enabled");
414 pmap_is_la57(pmap_t pmap)
416 if (pmap->pm_type == PT_X86)
418 return (false); /* XXXKIB handle EPT */
421 #define PAT_INDEX_SIZE 8
422 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
424 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
425 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
426 static u_int64_t KPDPphys; /* phys addr of kernel level 3 */
427 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
428 u_int64_t KPML5phys; /* phys addr of kernel level 5,
432 static uint64_t KASANPDPphys;
435 static uint64_t KMSANSHADPDPphys;
436 static uint64_t KMSANORIGPDPphys;
439 * To support systems with large amounts of memory, it is necessary to extend
440 * the maximum size of the direct map. This could eat into the space reserved
441 * for the shadow map.
443 _Static_assert(DMPML4I + NDMPML4E <= KMSANSHADPML4I, "direct map overflow");
446 static pml4_entry_t *kernel_pml4;
447 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
448 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
449 static int ndmpdpphys; /* number of DMPDPphys pages */
451 vm_paddr_t kernphys; /* phys addr of start of bootstrap data */
452 vm_paddr_t KERNend; /* and the end */
455 * pmap_mapdev support pre initialization (i.e. console)
457 #define PMAP_PREINIT_MAPPING_COUNT 8
458 static struct pmap_preinit_mapping {
463 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
464 static int pmap_initialized;
467 * Data for the pv entry allocation mechanism.
468 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
472 pc_to_domain(struct pv_chunk *pc)
475 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
479 pc_to_domain(struct pv_chunk *pc __unused)
486 struct pv_chunks_list {
488 TAILQ_HEAD(pch, pv_chunk) pvc_list;
490 } __aligned(CACHE_LINE_SIZE);
492 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
495 struct pmap_large_md_page {
496 struct rwlock pv_lock;
497 struct md_page pv_page;
500 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
501 #define pv_dummy pv_dummy_large.pv_page
502 __read_mostly static struct pmap_large_md_page *pv_table;
503 __read_mostly vm_paddr_t pmap_last_pa;
505 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
506 static u_long pv_invl_gen[NPV_LIST_LOCKS];
507 static struct md_page *pv_table;
508 static struct md_page pv_dummy;
512 * All those kernel PT submaps that BSD is so fond of
514 pt_entry_t *CMAP1 = NULL;
516 static vm_offset_t qframe = 0;
517 static struct mtx qframe_mtx;
519 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
521 static vmem_t *large_vmem;
522 static u_int lm_ents;
523 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
524 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
526 int pmap_pcid_enabled = 1;
527 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
528 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
529 int invpcid_works = 0;
530 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
531 "Is the invpcid instruction available ?");
533 int __read_frequently pti = 0;
534 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
536 "Page Table Isolation enabled");
537 static vm_object_t pti_obj;
538 static pml4_entry_t *pti_pml4;
539 static vm_pindex_t pti_pg_idx;
540 static bool pti_finalized;
542 struct pmap_pkru_range {
543 struct rs_el pkru_rs_el;
548 static uma_zone_t pmap_pkru_ranges_zone;
549 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
550 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
551 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
552 static void *pkru_dup_range(void *ctx, void *data);
553 static void pkru_free_range(void *ctx, void *node);
554 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
555 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
556 static void pmap_pkru_deassign_all(pmap_t pmap);
558 static COUNTER_U64_DEFINE_EARLY(pcid_save_cnt);
559 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLFLAG_RD,
560 &pcid_save_cnt, "Count of saved TLB context on switch");
562 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
563 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
564 static struct mtx invl_gen_mtx;
565 /* Fake lock object to satisfy turnstiles interface. */
566 static struct lock_object invl_gen_ts = {
569 static struct pmap_invl_gen pmap_invl_gen_head = {
573 static u_long pmap_invl_gen = 1;
574 static int pmap_invl_waiters;
575 static struct callout pmap_invl_callout;
576 static bool pmap_invl_callout_inited;
578 #define PMAP_ASSERT_NOT_IN_DI() \
579 KASSERT(pmap_not_in_di(), ("DI already started"))
586 if ((cpu_feature2 & CPUID2_CX16) == 0)
589 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
594 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
598 locked = pmap_di_locked();
599 return (sysctl_handle_int(oidp, &locked, 0, req));
601 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
602 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
603 "Locked delayed invalidation");
605 static bool pmap_not_in_di_l(void);
606 static bool pmap_not_in_di_u(void);
607 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
610 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
614 pmap_not_in_di_l(void)
616 struct pmap_invl_gen *invl_gen;
618 invl_gen = &curthread->td_md.md_invl_gen;
619 return (invl_gen->gen == 0);
623 pmap_thread_init_invl_gen_l(struct thread *td)
625 struct pmap_invl_gen *invl_gen;
627 invl_gen = &td->td_md.md_invl_gen;
632 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
634 struct turnstile *ts;
636 ts = turnstile_trywait(&invl_gen_ts);
637 if (*m_gen > atomic_load_long(invl_gen))
638 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
640 turnstile_cancel(ts);
644 pmap_delayed_invl_finish_unblock(u_long new_gen)
646 struct turnstile *ts;
648 turnstile_chain_lock(&invl_gen_ts);
649 ts = turnstile_lookup(&invl_gen_ts);
651 pmap_invl_gen = new_gen;
653 turnstile_broadcast(ts, TS_SHARED_QUEUE);
654 turnstile_unpend(ts);
656 turnstile_chain_unlock(&invl_gen_ts);
660 * Start a new Delayed Invalidation (DI) block of code, executed by
661 * the current thread. Within a DI block, the current thread may
662 * destroy both the page table and PV list entries for a mapping and
663 * then release the corresponding PV list lock before ensuring that
664 * the mapping is flushed from the TLBs of any processors with the
668 pmap_delayed_invl_start_l(void)
670 struct pmap_invl_gen *invl_gen;
673 invl_gen = &curthread->td_md.md_invl_gen;
674 PMAP_ASSERT_NOT_IN_DI();
675 mtx_lock(&invl_gen_mtx);
676 if (LIST_EMPTY(&pmap_invl_gen_tracker))
677 currgen = pmap_invl_gen;
679 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
680 invl_gen->gen = currgen + 1;
681 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
682 mtx_unlock(&invl_gen_mtx);
686 * Finish the DI block, previously started by the current thread. All
687 * required TLB flushes for the pages marked by
688 * pmap_delayed_invl_page() must be finished before this function is
691 * This function works by bumping the global DI generation number to
692 * the generation number of the current thread's DI, unless there is a
693 * pending DI that started earlier. In the latter case, bumping the
694 * global DI generation number would incorrectly signal that the
695 * earlier DI had finished. Instead, this function bumps the earlier
696 * DI's generation number to match the generation number of the
697 * current thread's DI.
700 pmap_delayed_invl_finish_l(void)
702 struct pmap_invl_gen *invl_gen, *next;
704 invl_gen = &curthread->td_md.md_invl_gen;
705 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
706 mtx_lock(&invl_gen_mtx);
707 next = LIST_NEXT(invl_gen, link);
709 pmap_delayed_invl_finish_unblock(invl_gen->gen);
711 next->gen = invl_gen->gen;
712 LIST_REMOVE(invl_gen, link);
713 mtx_unlock(&invl_gen_mtx);
718 pmap_not_in_di_u(void)
720 struct pmap_invl_gen *invl_gen;
722 invl_gen = &curthread->td_md.md_invl_gen;
723 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
727 pmap_thread_init_invl_gen_u(struct thread *td)
729 struct pmap_invl_gen *invl_gen;
731 invl_gen = &td->td_md.md_invl_gen;
733 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
737 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
739 uint64_t new_high, new_low, old_high, old_low;
742 old_low = new_low = 0;
743 old_high = new_high = (uintptr_t)0;
745 __asm volatile("lock;cmpxchg16b\t%1"
746 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
747 : "b"(new_low), "c" (new_high)
750 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
753 out->next = (void *)old_high;
756 out->next = (void *)new_high;
762 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
763 struct pmap_invl_gen *new_val)
765 uint64_t new_high, new_low, old_high, old_low;
768 new_low = new_val->gen;
769 new_high = (uintptr_t)new_val->next;
770 old_low = old_val->gen;
771 old_high = (uintptr_t)old_val->next;
773 __asm volatile("lock;cmpxchg16b\t%1"
774 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
775 : "b"(new_low), "c" (new_high)
780 static COUNTER_U64_DEFINE_EARLY(pv_page_count);
781 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_page_count, CTLFLAG_RD,
782 &pv_page_count, "Current number of allocated pv pages");
784 static COUNTER_U64_DEFINE_EARLY(user_pt_page_count);
785 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, user_pt_page_count, CTLFLAG_RD,
787 "Current number of allocated page table pages for userspace");
789 static COUNTER_U64_DEFINE_EARLY(kernel_pt_page_count);
790 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, kernel_pt_page_count, CTLFLAG_RD,
791 &kernel_pt_page_count,
792 "Current number of allocated page table pages for the kernel");
796 static COUNTER_U64_DEFINE_EARLY(invl_start_restart);
797 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_start_restart,
798 CTLFLAG_RD, &invl_start_restart,
799 "Number of delayed TLB invalidation request restarts");
801 static COUNTER_U64_DEFINE_EARLY(invl_finish_restart);
802 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
803 &invl_finish_restart,
804 "Number of delayed TLB invalidation completion restarts");
806 static int invl_max_qlen;
807 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
809 "Maximum delayed TLB invalidation request queue length");
812 #define di_delay locks_delay
815 pmap_delayed_invl_start_u(void)
817 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
819 struct lock_delay_arg lda;
827 invl_gen = &td->td_md.md_invl_gen;
828 PMAP_ASSERT_NOT_IN_DI();
829 lock_delay_arg_init(&lda, &di_delay);
830 invl_gen->saved_pri = 0;
831 pri = td->td_base_pri;
834 pri = td->td_base_pri;
836 invl_gen->saved_pri = pri;
843 for (p = &pmap_invl_gen_head;; p = prev.next) {
845 prevl = (uintptr_t)atomic_load_ptr(&p->next);
846 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
847 PV_STAT(counter_u64_add(invl_start_restart, 1));
853 prev.next = (void *)prevl;
856 if ((ii = invl_max_qlen) < i)
857 atomic_cmpset_int(&invl_max_qlen, ii, i);
860 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
861 PV_STAT(counter_u64_add(invl_start_restart, 1));
866 new_prev.gen = prev.gen;
867 new_prev.next = invl_gen;
868 invl_gen->gen = prev.gen + 1;
870 /* Formal fence between store to invl->gen and updating *p. */
871 atomic_thread_fence_rel();
874 * After inserting an invl_gen element with invalid bit set,
875 * this thread blocks any other thread trying to enter the
876 * delayed invalidation block. Do not allow to remove us from
877 * the CPU, because it causes starvation for other threads.
882 * ABA for *p is not possible there, since p->gen can only
883 * increase. So if the *p thread finished its di, then
884 * started a new one and got inserted into the list at the
885 * same place, its gen will appear greater than the previously
888 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
890 PV_STAT(counter_u64_add(invl_start_restart, 1));
896 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
897 * invl_gen->next, allowing other threads to iterate past us.
898 * pmap_di_store_invl() provides fence between the generation
899 * write and the update of next.
901 invl_gen->next = NULL;
906 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
907 struct pmap_invl_gen *p)
909 struct pmap_invl_gen prev, new_prev;
913 * Load invl_gen->gen after setting invl_gen->next
914 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
915 * generations to propagate to our invl_gen->gen. Lock prefix
916 * in atomic_set_ptr() worked as seq_cst fence.
918 mygen = atomic_load_long(&invl_gen->gen);
920 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
923 KASSERT(prev.gen < mygen,
924 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
925 new_prev.gen = mygen;
926 new_prev.next = (void *)((uintptr_t)invl_gen->next &
927 ~PMAP_INVL_GEN_NEXT_INVALID);
929 /* Formal fence between load of prev and storing update to it. */
930 atomic_thread_fence_rel();
932 return (pmap_di_store_invl(p, &prev, &new_prev));
936 pmap_delayed_invl_finish_u(void)
938 struct pmap_invl_gen *invl_gen, *p;
940 struct lock_delay_arg lda;
944 invl_gen = &td->td_md.md_invl_gen;
945 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
946 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
947 ("missed invl_start: INVALID"));
948 lock_delay_arg_init(&lda, &di_delay);
951 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
952 prevl = (uintptr_t)atomic_load_ptr(&p->next);
953 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
954 PV_STAT(counter_u64_add(invl_finish_restart, 1));
958 if ((void *)prevl == invl_gen)
963 * It is legitimate to not find ourself on the list if a
964 * thread before us finished its DI and started it again.
966 if (__predict_false(p == NULL)) {
967 PV_STAT(counter_u64_add(invl_finish_restart, 1));
973 atomic_set_ptr((uintptr_t *)&invl_gen->next,
974 PMAP_INVL_GEN_NEXT_INVALID);
975 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
976 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
977 PMAP_INVL_GEN_NEXT_INVALID);
979 PV_STAT(counter_u64_add(invl_finish_restart, 1));
984 if (atomic_load_int(&pmap_invl_waiters) > 0)
985 pmap_delayed_invl_finish_unblock(0);
986 if (invl_gen->saved_pri != 0) {
988 sched_prio(td, invl_gen->saved_pri);
994 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
996 struct pmap_invl_gen *p, *pn;
1001 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
1003 nextl = (uintptr_t)atomic_load_ptr(&p->next);
1004 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
1005 td = first ? NULL : __containerof(p, struct thread,
1007 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
1008 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
1009 td != NULL ? td->td_tid : -1);
1015 static COUNTER_U64_DEFINE_EARLY(invl_wait);
1016 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait,
1017 CTLFLAG_RD, &invl_wait,
1018 "Number of times DI invalidation blocked pmap_remove_all/write");
1020 static COUNTER_U64_DEFINE_EARLY(invl_wait_slow);
1021 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD,
1022 &invl_wait_slow, "Number of slow invalidation waits for lockless DI");
1028 pmap_delayed_invl_genp(vm_page_t m)
1033 pa = VM_PAGE_TO_PHYS(m);
1034 if (__predict_false((pa) > pmap_last_pa))
1035 gen = &pv_dummy_large.pv_invl_gen;
1037 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1043 pmap_delayed_invl_genp(vm_page_t m)
1046 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1051 pmap_delayed_invl_callout_func(void *arg __unused)
1054 if (atomic_load_int(&pmap_invl_waiters) == 0)
1056 pmap_delayed_invl_finish_unblock(0);
1060 pmap_delayed_invl_callout_init(void *arg __unused)
1063 if (pmap_di_locked())
1065 callout_init(&pmap_invl_callout, 1);
1066 pmap_invl_callout_inited = true;
1068 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1069 pmap_delayed_invl_callout_init, NULL);
1072 * Ensure that all currently executing DI blocks, that need to flush
1073 * TLB for the given page m, actually flushed the TLB at the time the
1074 * function returned. If the page m has an empty PV list and we call
1075 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1076 * valid mapping for the page m in either its page table or TLB.
1078 * This function works by blocking until the global DI generation
1079 * number catches up with the generation number associated with the
1080 * given page m and its PV list. Since this function's callers
1081 * typically own an object lock and sometimes own a page lock, it
1082 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1086 pmap_delayed_invl_wait_l(vm_page_t m)
1090 bool accounted = false;
1093 m_gen = pmap_delayed_invl_genp(m);
1094 while (*m_gen > pmap_invl_gen) {
1097 counter_u64_add(invl_wait, 1);
1101 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1106 pmap_delayed_invl_wait_u(vm_page_t m)
1109 struct lock_delay_arg lda;
1113 m_gen = pmap_delayed_invl_genp(m);
1114 lock_delay_arg_init(&lda, &di_delay);
1115 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1116 if (fast || !pmap_invl_callout_inited) {
1117 PV_STAT(counter_u64_add(invl_wait, 1));
1122 * The page's invalidation generation number
1123 * is still below the current thread's number.
1124 * Prepare to block so that we do not waste
1125 * CPU cycles or worse, suffer livelock.
1127 * Since it is impossible to block without
1128 * racing with pmap_delayed_invl_finish_u(),
1129 * prepare for the race by incrementing
1130 * pmap_invl_waiters and arming a 1-tick
1131 * callout which will unblock us if we lose
1134 atomic_add_int(&pmap_invl_waiters, 1);
1137 * Re-check the current thread's invalidation
1138 * generation after incrementing
1139 * pmap_invl_waiters, so that there is no race
1140 * with pmap_delayed_invl_finish_u() setting
1141 * the page generation and checking
1142 * pmap_invl_waiters. The only race allowed
1143 * is for a missed unblock, which is handled
1147 atomic_load_long(&pmap_invl_gen_head.gen)) {
1148 callout_reset(&pmap_invl_callout, 1,
1149 pmap_delayed_invl_callout_func, NULL);
1150 PV_STAT(counter_u64_add(invl_wait_slow, 1));
1151 pmap_delayed_invl_wait_block(m_gen,
1152 &pmap_invl_gen_head.gen);
1154 atomic_add_int(&pmap_invl_waiters, -1);
1159 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1162 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1163 pmap_thread_init_invl_gen_u);
1166 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1169 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1170 pmap_delayed_invl_start_u);
1173 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1176 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1177 pmap_delayed_invl_finish_u);
1180 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1183 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1184 pmap_delayed_invl_wait_u);
1188 * Mark the page m's PV list as participating in the current thread's
1189 * DI block. Any threads concurrently using m's PV list to remove or
1190 * restrict all mappings to m will wait for the current thread's DI
1191 * block to complete before proceeding.
1193 * The function works by setting the DI generation number for m's PV
1194 * list to at least the DI generation number of the current thread.
1195 * This forces a caller of pmap_delayed_invl_wait() to block until
1196 * current thread calls pmap_delayed_invl_finish().
1199 pmap_delayed_invl_page(vm_page_t m)
1203 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1204 gen = curthread->td_md.md_invl_gen.gen;
1207 m_gen = pmap_delayed_invl_genp(m);
1215 static caddr_t crashdumpmap;
1218 * Internal flags for pmap_enter()'s helper functions.
1220 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1221 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1224 * Internal flags for pmap_mapdev_internal() and
1225 * pmap_change_props_locked().
1227 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1228 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1229 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1231 TAILQ_HEAD(pv_chunklist, pv_chunk);
1233 static void free_pv_chunk(struct pv_chunk *pc);
1234 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1235 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1236 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1237 static int popcnt_pc_map_pq(uint64_t *map);
1238 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1239 static void reserve_pv_entries(pmap_t pmap, int needed,
1240 struct rwlock **lockp);
1241 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1242 struct rwlock **lockp);
1243 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1244 u_int flags, struct rwlock **lockp);
1245 #if VM_NRESERVLEVEL > 0
1246 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1247 struct rwlock **lockp);
1249 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1250 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1253 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1254 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1255 vm_prot_t prot, int mode, int flags);
1256 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1257 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1258 vm_offset_t va, struct rwlock **lockp);
1259 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1261 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1262 vm_prot_t prot, struct rwlock **lockp);
1263 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1264 u_int flags, vm_page_t m, struct rwlock **lockp);
1265 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1266 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1267 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1268 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1269 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1271 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1273 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1275 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1276 static vm_page_t pmap_large_map_getptp_unlocked(void);
1277 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1278 #if VM_NRESERVLEVEL > 0
1279 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1280 struct rwlock **lockp);
1282 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1284 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1285 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1287 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1288 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1289 static void pmap_pti_wire_pte(void *pte);
1290 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1291 struct spglist *free, struct rwlock **lockp);
1292 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1293 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1294 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1295 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1296 struct spglist *free);
1297 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1298 pd_entry_t *pde, struct spglist *free,
1299 struct rwlock **lockp);
1300 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1301 vm_page_t m, struct rwlock **lockp);
1302 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1304 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1306 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1307 struct rwlock **lockp);
1308 static vm_page_t pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex,
1309 struct rwlock **lockp, vm_offset_t va);
1310 static vm_page_t pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex,
1311 struct rwlock **lockp, vm_offset_t va);
1312 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1313 struct rwlock **lockp);
1315 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1316 struct spglist *free);
1317 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1319 static vm_page_t pmap_alloc_pt_page(pmap_t, vm_pindex_t, int);
1320 static void pmap_free_pt_page(pmap_t, vm_page_t, bool);
1322 /********************/
1323 /* Inline functions */
1324 /********************/
1327 * Return a non-clipped indexes for a given VA, which are page table
1328 * pages indexes at the corresponding level.
1330 static __inline vm_pindex_t
1331 pmap_pde_pindex(vm_offset_t va)
1333 return (va >> PDRSHIFT);
1336 static __inline vm_pindex_t
1337 pmap_pdpe_pindex(vm_offset_t va)
1339 return (NUPDE + (va >> PDPSHIFT));
1342 static __inline vm_pindex_t
1343 pmap_pml4e_pindex(vm_offset_t va)
1345 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1348 static __inline vm_pindex_t
1349 pmap_pml5e_pindex(vm_offset_t va)
1351 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1354 static __inline pml4_entry_t *
1355 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1358 MPASS(pmap_is_la57(pmap));
1359 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1362 static __inline pml4_entry_t *
1363 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1366 MPASS(pmap_is_la57(pmap));
1367 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1370 static __inline pml4_entry_t *
1371 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1373 pml4_entry_t *pml4e;
1375 /* XXX MPASS(pmap_is_la57(pmap); */
1376 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1377 return (&pml4e[pmap_pml4e_index(va)]);
1380 /* Return a pointer to the PML4 slot that corresponds to a VA */
1381 static __inline pml4_entry_t *
1382 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1384 pml5_entry_t *pml5e;
1385 pml4_entry_t *pml4e;
1388 if (pmap_is_la57(pmap)) {
1389 pml5e = pmap_pml5e(pmap, va);
1390 PG_V = pmap_valid_bit(pmap);
1391 if ((*pml5e & PG_V) == 0)
1393 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1395 pml4e = pmap->pm_pmltop;
1397 return (&pml4e[pmap_pml4e_index(va)]);
1400 static __inline pml4_entry_t *
1401 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1403 MPASS(!pmap_is_la57(pmap));
1404 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1407 /* Return a pointer to the PDP slot that corresponds to a VA */
1408 static __inline pdp_entry_t *
1409 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1413 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1414 return (&pdpe[pmap_pdpe_index(va)]);
1417 /* Return a pointer to the PDP slot that corresponds to a VA */
1418 static __inline pdp_entry_t *
1419 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1421 pml4_entry_t *pml4e;
1424 PG_V = pmap_valid_bit(pmap);
1425 pml4e = pmap_pml4e(pmap, va);
1426 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1428 return (pmap_pml4e_to_pdpe(pml4e, va));
1431 /* Return a pointer to the PD slot that corresponds to a VA */
1432 static __inline pd_entry_t *
1433 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1437 KASSERT((*pdpe & PG_PS) == 0,
1438 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1439 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1440 return (&pde[pmap_pde_index(va)]);
1443 /* Return a pointer to the PD slot that corresponds to a VA */
1444 static __inline pd_entry_t *
1445 pmap_pde(pmap_t pmap, vm_offset_t va)
1450 PG_V = pmap_valid_bit(pmap);
1451 pdpe = pmap_pdpe(pmap, va);
1452 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1454 KASSERT((*pdpe & PG_PS) == 0,
1455 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1456 return (pmap_pdpe_to_pde(pdpe, va));
1459 /* Return a pointer to the PT slot that corresponds to a VA */
1460 static __inline pt_entry_t *
1461 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1465 KASSERT((*pde & PG_PS) == 0,
1466 ("%s: pde %#lx is a leaf", __func__, *pde));
1467 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1468 return (&pte[pmap_pte_index(va)]);
1471 /* Return a pointer to the PT slot that corresponds to a VA */
1472 static __inline pt_entry_t *
1473 pmap_pte(pmap_t pmap, vm_offset_t va)
1478 PG_V = pmap_valid_bit(pmap);
1479 pde = pmap_pde(pmap, va);
1480 if (pde == NULL || (*pde & PG_V) == 0)
1482 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1483 return ((pt_entry_t *)pde);
1484 return (pmap_pde_to_pte(pde, va));
1487 static __inline void
1488 pmap_resident_count_adj(pmap_t pmap, int count)
1491 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1492 KASSERT(pmap->pm_stats.resident_count + count >= 0,
1493 ("pmap %p resident count underflow %ld %d", pmap,
1494 pmap->pm_stats.resident_count, count));
1495 pmap->pm_stats.resident_count += count;
1498 static __inline void
1499 pmap_pt_page_count_adj(pmap_t pmap, int count)
1501 if (pmap == kernel_pmap)
1502 counter_u64_add(kernel_pt_page_count, count);
1505 pmap_resident_count_adj(pmap, count);
1506 counter_u64_add(user_pt_page_count, count);
1510 PMAP_INLINE pt_entry_t *
1511 vtopte(vm_offset_t va)
1515 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1518 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1519 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1520 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1522 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1523 NPML4EPGSHIFT)) - 1);
1524 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1528 static __inline pd_entry_t *
1529 vtopde(vm_offset_t va)
1533 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1536 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1537 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1538 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1540 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1541 NPML4EPGSHIFT)) - 1);
1542 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1547 allocpages(vm_paddr_t *firstaddr, int n)
1552 bzero((void *)ret, n * PAGE_SIZE);
1553 *firstaddr += n * PAGE_SIZE;
1557 CTASSERT(powerof2(NDMPML4E));
1559 /* number of kernel PDP slots */
1560 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1563 nkpt_init(vm_paddr_t addr)
1570 pt_pages = howmany(addr - kernphys, NBPDR) + 1; /* +1 for 2M hole @0 */
1571 pt_pages += NKPDPE(pt_pages);
1574 * Add some slop beyond the bare minimum required for bootstrapping
1577 * This is quite important when allocating KVA for kernel modules.
1578 * The modules are required to be linked in the negative 2GB of
1579 * the address space. If we run out of KVA in this region then
1580 * pmap_growkernel() will need to allocate page table pages to map
1581 * the entire 512GB of KVA space which is an unnecessary tax on
1584 * Secondly, device memory mapped as part of setting up the low-
1585 * level console(s) is taken from KVA, starting at virtual_avail.
1586 * This is because cninit() is called after pmap_bootstrap() but
1587 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1590 pt_pages += 32; /* 64MB additional slop. */
1596 * Returns the proper write/execute permission for a physical page that is
1597 * part of the initial boot allocations.
1599 * If the page has kernel text, it is marked as read-only. If the page has
1600 * kernel read-only data, it is marked as read-only/not-executable. If the
1601 * page has only read-write data, it is marked as read-write/not-executable.
1602 * If the page is below/above the kernel range, it is marked as read-write.
1604 * This function operates on 2M pages, since we map the kernel space that
1607 static inline pt_entry_t
1608 bootaddr_rwx(vm_paddr_t pa)
1611 * The kernel is loaded at a 2MB-aligned address, and memory below that
1612 * need not be executable. The .bss section is padded to a 2MB
1613 * boundary, so memory following the kernel need not be executable
1614 * either. Preloaded kernel modules have their mapping permissions
1615 * fixed up by the linker.
1617 if (pa < trunc_2mpage(kernphys + btext - KERNSTART) ||
1618 pa >= trunc_2mpage(kernphys + _end - KERNSTART))
1619 return (X86_PG_RW | pg_nx);
1622 * The linker should ensure that the read-only and read-write
1623 * portions don't share the same 2M page, so this shouldn't
1624 * impact read-only data. However, in any case, any page with
1625 * read-write data needs to be read-write.
1627 if (pa >= trunc_2mpage(kernphys + brwsection - KERNSTART))
1628 return (X86_PG_RW | pg_nx);
1631 * Mark any 2M page containing kernel text as read-only. Mark
1632 * other pages with read-only data as read-only and not executable.
1633 * (It is likely a small portion of the read-only data section will
1634 * be marked as read-only, but executable. This should be acceptable
1635 * since the read-only protection will keep the data from changing.)
1636 * Note that fixups to the .text section will still work until we
1639 if (pa < round_2mpage(kernphys + etext - KERNSTART))
1645 create_pagetables(vm_paddr_t *firstaddr)
1650 uint64_t DMPDkernphys;
1654 uint64_t KASANPDphys, KASANPTphys, KASANphys;
1655 vm_offset_t kasankernbase;
1656 int kasankpdpi, kasankpdi, nkasanpte;
1658 int i, j, ndm1g, nkpdpe, nkdmpde;
1660 /* Allocate page table pages for the direct map */
1661 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1662 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1664 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1665 if (ndmpdpphys > NDMPML4E) {
1667 * Each NDMPML4E allows 512 GB, so limit to that,
1668 * and then readjust ndmpdp and ndmpdpphys.
1670 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1671 Maxmem = atop(NDMPML4E * NBPML4);
1672 ndmpdpphys = NDMPML4E;
1673 ndmpdp = NDMPML4E * NPDEPG;
1675 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1677 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1679 * Calculate the number of 1G pages that will fully fit in
1682 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1685 * Allocate 2M pages for the kernel. These will be used in
1686 * place of the one or more 1G pages from ndm1g that maps
1687 * kernel memory into DMAP.
1689 nkdmpde = howmany((vm_offset_t)brwsection - KERNSTART +
1690 kernphys - rounddown2(kernphys, NBPDP), NBPDP);
1691 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1694 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1695 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1697 /* Allocate pages. */
1698 KPML4phys = allocpages(firstaddr, 1);
1699 KPDPphys = allocpages(firstaddr, NKPML4E);
1701 KASANPDPphys = allocpages(firstaddr, NKASANPML4E);
1702 KASANPDphys = allocpages(firstaddr, 1);
1706 * The KMSAN shadow maps are initially left unpopulated, since there is
1707 * no need to shadow memory above KERNBASE.
1709 KMSANSHADPDPphys = allocpages(firstaddr, NKMSANSHADPML4E);
1710 KMSANORIGPDPphys = allocpages(firstaddr, NKMSANORIGPML4E);
1714 * Allocate the initial number of kernel page table pages required to
1715 * bootstrap. We defer this until after all memory-size dependent
1716 * allocations are done (e.g. direct map), so that we don't have to
1717 * build in too much slop in our estimate.
1719 * Note that when NKPML4E > 1, we have an empty page underneath
1720 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1721 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1723 nkpt_init(*firstaddr);
1724 nkpdpe = NKPDPE(nkpt);
1726 KPTphys = allocpages(firstaddr, nkpt);
1727 KPDphys = allocpages(firstaddr, nkpdpe);
1730 nkasanpte = howmany(nkpt, KASAN_SHADOW_SCALE);
1731 KASANPTphys = allocpages(firstaddr, nkasanpte);
1732 KASANphys = allocpages(firstaddr, nkasanpte * NPTEPG);
1736 * Connect the zero-filled PT pages to their PD entries. This
1737 * implicitly maps the PT pages at their correct locations within
1740 pd_p = (pd_entry_t *)KPDphys;
1741 for (i = 0; i < nkpt; i++)
1742 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1745 * Map from start of the kernel in physical memory (staging
1746 * area) to the end of loader preallocated memory using 2MB
1747 * pages. This replaces some of the PD entries created above.
1748 * For compatibility, identity map 2M at the start.
1750 pd_p[0] = X86_PG_V | PG_PS | pg_g | X86_PG_M | X86_PG_A |
1752 for (i = 1, pax = kernphys; pax < KERNend; i++, pax += NBPDR) {
1753 /* Preset PG_M and PG_A because demotion expects it. */
1754 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M |
1755 X86_PG_A | bootaddr_rwx(pax);
1759 * Because we map the physical blocks in 2M pages, adjust firstaddr
1760 * to record the physical blocks we've actually mapped into kernel
1761 * virtual address space.
1763 if (*firstaddr < round_2mpage(KERNend))
1764 *firstaddr = round_2mpage(KERNend);
1766 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1767 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1768 for (i = 0; i < nkpdpe; i++)
1769 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1772 kasankernbase = kasan_md_addr_to_shad(KERNBASE);
1773 kasankpdpi = pmap_pdpe_index(kasankernbase);
1774 kasankpdi = pmap_pde_index(kasankernbase);
1776 pdp_p = (pdp_entry_t *)KASANPDPphys;
1777 pdp_p[kasankpdpi] = (KASANPDphys | X86_PG_RW | X86_PG_V | pg_nx);
1779 pd_p = (pd_entry_t *)KASANPDphys;
1780 for (i = 0; i < nkasanpte; i++)
1781 pd_p[i + kasankpdi] = (KASANPTphys + ptoa(i)) | X86_PG_RW |
1784 pt_p = (pt_entry_t *)KASANPTphys;
1785 for (i = 0; i < nkasanpte * NPTEPG; i++)
1786 pt_p[i] = (KASANphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
1787 X86_PG_M | X86_PG_A | pg_nx;
1791 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1792 * the end of physical memory is not aligned to a 1GB page boundary,
1793 * then the residual physical memory is mapped with 2MB pages. Later,
1794 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1795 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1796 * that are partially used.
1798 pd_p = (pd_entry_t *)DMPDphys;
1799 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1800 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1801 /* Preset PG_M and PG_A because demotion expects it. */
1802 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1803 X86_PG_M | X86_PG_A | pg_nx;
1805 pdp_p = (pdp_entry_t *)DMPDPphys;
1806 for (i = 0; i < ndm1g; i++) {
1807 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1808 /* Preset PG_M and PG_A because demotion expects it. */
1809 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1810 X86_PG_M | X86_PG_A | pg_nx;
1812 for (j = 0; i < ndmpdp; i++, j++) {
1813 pdp_p[i] = DMPDphys + ptoa(j);
1814 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1818 * Instead of using a 1G page for the memory containing the kernel,
1819 * use 2M pages with read-only and no-execute permissions. (If using 1G
1820 * pages, this will partially overwrite the PDPEs above.)
1823 pd_p = (pd_entry_t *)DMPDkernphys;
1824 for (i = 0, pax = rounddown2(kernphys, NBPDP);
1825 i < NPDEPG * nkdmpde; i++, pax += NBPDR) {
1826 pd_p[i] = pax | X86_PG_V | PG_PS | pg_g | X86_PG_M |
1827 X86_PG_A | pg_nx | bootaddr_rwx(pax);
1829 j = rounddown2(kernphys, NBPDP) >> PDPSHIFT;
1830 for (i = 0; i < nkdmpde; i++) {
1831 pdp_p[i + j] = (DMPDkernphys + ptoa(i)) |
1832 X86_PG_RW | X86_PG_V | pg_nx;
1836 /* And recursively map PML4 to itself in order to get PTmap */
1837 p4_p = (pml4_entry_t *)KPML4phys;
1838 p4_p[PML4PML4I] = KPML4phys;
1839 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1842 /* Connect the KASAN shadow map slots up to the PML4. */
1843 for (i = 0; i < NKASANPML4E; i++) {
1844 p4_p[KASANPML4I + i] = KASANPDPphys + ptoa(i);
1845 p4_p[KASANPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1850 /* Connect the KMSAN shadow map slots up to the PML4. */
1851 for (i = 0; i < NKMSANSHADPML4E; i++) {
1852 p4_p[KMSANSHADPML4I + i] = KMSANSHADPDPphys + ptoa(i);
1853 p4_p[KMSANSHADPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1856 /* Connect the KMSAN origin map slots up to the PML4. */
1857 for (i = 0; i < NKMSANORIGPML4E; i++) {
1858 p4_p[KMSANORIGPML4I + i] = KMSANORIGPDPphys + ptoa(i);
1859 p4_p[KMSANORIGPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1863 /* Connect the Direct Map slots up to the PML4. */
1864 for (i = 0; i < ndmpdpphys; i++) {
1865 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1866 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1869 /* Connect the KVA slots up to the PML4 */
1870 for (i = 0; i < NKPML4E; i++) {
1871 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1872 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1875 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1879 * Bootstrap the system enough to run with virtual memory.
1881 * On amd64 this is called after mapping has already been enabled
1882 * and just syncs the pmap module with what has already been done.
1883 * [We can't call it easily with mapping off since the kernel is not
1884 * mapped with PA == VA, hence we would have to relocate every address
1885 * from the linked base (virtual) address "KERNBASE" to the actual
1886 * (physical) address starting relative to 0]
1889 pmap_bootstrap(vm_paddr_t *firstaddr)
1892 pt_entry_t *pte, *pcpu_pte;
1893 struct region_descriptor r_gdt;
1894 uint64_t cr4, pcpu_phys;
1898 KERNend = *firstaddr;
1899 res = atop(KERNend - (vm_paddr_t)kernphys);
1905 * Create an initial set of page tables to run the kernel in.
1907 create_pagetables(firstaddr);
1909 pcpu_phys = allocpages(firstaddr, MAXCPU);
1912 * Add a physical memory segment (vm_phys_seg) corresponding to the
1913 * preallocated kernel page table pages so that vm_page structures
1914 * representing these pages will be created. The vm_page structures
1915 * are required for promotion of the corresponding kernel virtual
1916 * addresses to superpage mappings.
1918 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1921 * Account for the virtual addresses mapped by create_pagetables().
1923 virtual_avail = (vm_offset_t)KERNSTART + round_2mpage(KERNend -
1924 (vm_paddr_t)kernphys);
1925 virtual_end = VM_MAX_KERNEL_ADDRESS;
1928 * Enable PG_G global pages, then switch to the kernel page
1929 * table from the bootstrap page table. After the switch, it
1930 * is possible to enable SMEP and SMAP since PG_U bits are
1936 load_cr3(KPML4phys);
1937 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1939 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1944 * Initialize the kernel pmap (which is statically allocated).
1945 * Count bootstrap data as being resident in case any of this data is
1946 * later unmapped (using pmap_remove()) and freed.
1948 PMAP_LOCK_INIT(kernel_pmap);
1949 kernel_pmap->pm_pmltop = kernel_pml4;
1950 kernel_pmap->pm_cr3 = KPML4phys;
1951 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1952 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1953 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1954 kernel_pmap->pm_stats.resident_count = res;
1955 kernel_pmap->pm_flags = pmap_flags;
1958 * Initialize the TLB invalidations generation number lock.
1960 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1963 * Reserve some special page table entries/VA space for temporary
1966 #define SYSMAP(c, p, v, n) \
1967 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1973 * Crashdump maps. The first page is reused as CMAP1 for the
1976 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1977 CADDR1 = crashdumpmap;
1979 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1982 for (i = 0; i < MAXCPU; i++) {
1983 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1984 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1988 * Re-initialize PCPU area for BSP after switching.
1989 * Make hardware use gdt and common_tss from the new PCPU.
1991 STAILQ_INIT(&cpuhead);
1992 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1993 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1994 amd64_bsp_pcpu_init1(&__pcpu[0]);
1995 amd64_bsp_ist_init(&__pcpu[0]);
1996 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1998 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1999 sizeof(struct user_segment_descriptor));
2000 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
2001 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2002 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2003 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2004 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2006 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2007 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2008 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
2009 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
2012 * Initialize the PAT MSR.
2013 * pmap_init_pat() clears and sets CR4_PGE, which, as a
2014 * side-effect, invalidates stale PG_G TLB entries that might
2015 * have been created in our pre-boot environment.
2019 /* Initialize TLB Context Id. */
2020 if (pmap_pcid_enabled) {
2021 for (i = 0; i < MAXCPU; i++) {
2022 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
2023 kernel_pmap->pm_pcids[i].pm_gen = 1;
2027 * PMAP_PCID_KERN + 1 is used for initialization of
2028 * proc0 pmap. The pmap' pcid state might be used by
2029 * EFIRT entry before first context switch, so it
2030 * needs to be valid.
2032 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
2033 PCPU_SET(pcid_gen, 1);
2036 * pcpu area for APs is zeroed during AP startup.
2037 * pc_pcid_next and pc_pcid_gen are initialized by AP
2038 * during pcpu setup.
2040 load_cr4(rcr4() | CR4_PCIDE);
2045 * Setup the PAT MSR.
2054 /* Bail if this CPU doesn't implement PAT. */
2055 if ((cpu_feature & CPUID_PAT) == 0)
2058 /* Set default PAT index table. */
2059 for (i = 0; i < PAT_INDEX_SIZE; i++)
2061 pat_index[PAT_WRITE_BACK] = 0;
2062 pat_index[PAT_WRITE_THROUGH] = 1;
2063 pat_index[PAT_UNCACHEABLE] = 3;
2064 pat_index[PAT_WRITE_COMBINING] = 6;
2065 pat_index[PAT_WRITE_PROTECTED] = 5;
2066 pat_index[PAT_UNCACHED] = 2;
2069 * Initialize default PAT entries.
2070 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
2071 * Program 5 and 6 as WP and WC.
2073 * Leave 4 and 7 as WB and UC. Note that a recursive page table
2074 * mapping for a 2M page uses a PAT value with the bit 3 set due
2075 * to its overload with PG_PS.
2077 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
2078 PAT_VALUE(1, PAT_WRITE_THROUGH) |
2079 PAT_VALUE(2, PAT_UNCACHED) |
2080 PAT_VALUE(3, PAT_UNCACHEABLE) |
2081 PAT_VALUE(4, PAT_WRITE_BACK) |
2082 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
2083 PAT_VALUE(6, PAT_WRITE_COMBINING) |
2084 PAT_VALUE(7, PAT_UNCACHEABLE);
2088 load_cr4(cr4 & ~CR4_PGE);
2090 /* Disable caches (CD = 1, NW = 0). */
2092 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
2094 /* Flushes caches and TLBs. */
2098 /* Update PAT and index table. */
2099 wrmsr(MSR_PAT, pat_msr);
2101 /* Flush caches and TLBs again. */
2105 /* Restore caches and PGE. */
2111 pmap_page_alloc_below_4g(bool zeroed)
2115 m = vm_page_alloc_contig(NULL, 0, (zeroed ? VM_ALLOC_ZERO : 0) |
2116 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_NOOBJ,
2117 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2118 if (m != NULL && zeroed && (m->flags & PG_ZERO) == 0)
2123 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
2124 la57_trampoline_gdt[], la57_trampoline_end[];
2127 pmap_bootstrap_la57(void *arg __unused)
2130 pml5_entry_t *v_pml5;
2131 pml4_entry_t *v_pml4;
2135 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2136 void (*la57_tramp)(uint64_t pml5);
2137 struct region_descriptor r_gdt;
2139 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2141 TUNABLE_INT_FETCH("vm.pmap.la57", &la57);
2145 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2146 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2148 m_code = pmap_page_alloc_below_4g(true);
2149 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2150 m_pml5 = pmap_page_alloc_below_4g(true);
2151 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2152 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2153 m_pml4 = pmap_page_alloc_below_4g(true);
2154 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2155 m_pdp = pmap_page_alloc_below_4g(true);
2156 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2157 m_pd = pmap_page_alloc_below_4g(true);
2158 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2159 m_pt = pmap_page_alloc_below_4g(true);
2160 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2163 * Map m_code 1:1, it appears below 4G in KVA due to physical
2164 * address being below 4G. Since kernel KVA is in upper half,
2165 * the pml4e should be zero and free for temporary use.
2167 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2168 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2170 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2171 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2173 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2174 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2176 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2177 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2181 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2182 * entering all existing kernel mappings into level 5 table.
2184 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2185 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2188 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2190 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2191 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2193 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2194 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2198 * Copy and call the 48->57 trampoline, hope we return there, alive.
2200 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2201 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2202 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2203 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2204 invlpg((vm_offset_t)la57_tramp);
2205 la57_tramp(KPML5phys);
2208 * gdt was necessary reset, switch back to our gdt.
2211 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2215 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2216 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2217 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2220 * Now unmap the trampoline, and free the pages.
2221 * Clear pml5 entry used for 1:1 trampoline mapping.
2223 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2224 invlpg((vm_offset_t)v_code);
2225 vm_page_free(m_code);
2226 vm_page_free(m_pdp);
2231 * Recursively map PML5 to itself in order to get PTmap and
2234 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2236 kernel_pmap->pm_cr3 = KPML5phys;
2237 kernel_pmap->pm_pmltop = v_pml5;
2238 pmap_pt_page_count_adj(kernel_pmap, 1);
2240 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2243 * Initialize a vm_page's machine-dependent fields.
2246 pmap_page_init(vm_page_t m)
2249 TAILQ_INIT(&m->md.pv_list);
2250 m->md.pat_mode = PAT_WRITE_BACK;
2253 static int pmap_allow_2m_x_ept;
2254 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2255 &pmap_allow_2m_x_ept, 0,
2256 "Allow executable superpage mappings in EPT");
2259 pmap_allow_2m_x_ept_recalculate(void)
2262 * SKL002, SKL012S. Since the EPT format is only used by
2263 * Intel CPUs, the vendor check is merely a formality.
2265 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2266 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2267 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2268 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2269 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2270 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2271 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2272 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2273 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2274 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2275 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2276 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2277 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2278 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2279 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2280 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2281 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2282 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2283 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2284 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2285 CPUID_TO_MODEL(cpu_id) == 0x85))))
2286 pmap_allow_2m_x_ept = 1;
2287 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2291 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2294 return (pmap->pm_type != PT_EPT || !executable ||
2295 !pmap_allow_2m_x_ept);
2300 pmap_init_pv_table(void)
2302 struct pmap_large_md_page *pvd;
2304 long start, end, highest, pv_npg;
2305 int domain, i, j, pages;
2308 * We strongly depend on the size being a power of two, so the assert
2309 * is overzealous. However, should the struct be resized to a
2310 * different power of two, the code below needs to be revisited.
2312 CTASSERT((sizeof(*pvd) == 64));
2315 * Calculate the size of the array.
2317 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2318 pv_npg = howmany(pmap_last_pa, NBPDR);
2319 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2321 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2322 if (pv_table == NULL)
2323 panic("%s: kva_alloc failed\n", __func__);
2326 * Iterate physical segments to allocate space for respective pages.
2330 for (i = 0; i < vm_phys_nsegs; i++) {
2331 end = vm_phys_segs[i].end / NBPDR;
2332 domain = vm_phys_segs[i].domain;
2337 start = highest + 1;
2338 pvd = &pv_table[start];
2340 pages = end - start + 1;
2341 s = round_page(pages * sizeof(*pvd));
2342 highest = start + (s / sizeof(*pvd)) - 1;
2344 for (j = 0; j < s; j += PAGE_SIZE) {
2345 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2346 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2348 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2349 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2352 for (j = 0; j < s / sizeof(*pvd); j++) {
2353 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2354 TAILQ_INIT(&pvd->pv_page.pv_list);
2355 pvd->pv_page.pv_gen = 0;
2356 pvd->pv_page.pat_mode = 0;
2357 pvd->pv_invl_gen = 0;
2361 pvd = &pv_dummy_large;
2362 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2363 TAILQ_INIT(&pvd->pv_page.pv_list);
2364 pvd->pv_page.pv_gen = 0;
2365 pvd->pv_page.pat_mode = 0;
2366 pvd->pv_invl_gen = 0;
2370 pmap_init_pv_table(void)
2376 * Initialize the pool of pv list locks.
2378 for (i = 0; i < NPV_LIST_LOCKS; i++)
2379 rw_init(&pv_list_locks[i], "pmap pv list");
2382 * Calculate the size of the pv head table for superpages.
2384 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2387 * Allocate memory for the pv head table for superpages.
2389 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2391 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2392 for (i = 0; i < pv_npg; i++)
2393 TAILQ_INIT(&pv_table[i].pv_list);
2394 TAILQ_INIT(&pv_dummy.pv_list);
2399 * Initialize the pmap module.
2400 * Called by vm_init, to initialize any structures that the pmap
2401 * system needs to map virtual memory.
2406 struct pmap_preinit_mapping *ppim;
2408 int error, i, ret, skz63;
2410 /* L1TF, reserve page @0 unconditionally */
2411 vm_page_blacklist_add(0, bootverbose);
2413 /* Detect bare-metal Skylake Server and Skylake-X. */
2414 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2415 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2417 * Skylake-X errata SKZ63. Processor May Hang When
2418 * Executing Code In an HLE Transaction Region between
2419 * 40000000H and 403FFFFFH.
2421 * Mark the pages in the range as preallocated. It
2422 * seems to be impossible to distinguish between
2423 * Skylake Server and Skylake X.
2426 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2429 printf("SKZ63: skipping 4M RAM starting "
2430 "at physical 1G\n");
2431 for (i = 0; i < atop(0x400000); i++) {
2432 ret = vm_page_blacklist_add(0x40000000 +
2434 if (!ret && bootverbose)
2435 printf("page at %#lx already used\n",
2436 0x40000000 + ptoa(i));
2442 pmap_allow_2m_x_ept_recalculate();
2445 * Initialize the vm page array entries for the kernel pmap's
2448 PMAP_LOCK(kernel_pmap);
2449 for (i = 0; i < nkpt; i++) {
2450 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2451 KASSERT(mpte >= vm_page_array &&
2452 mpte < &vm_page_array[vm_page_array_size],
2453 ("pmap_init: page table page is out of range"));
2454 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2455 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2456 mpte->ref_count = 1;
2459 * Collect the page table pages that were replaced by a 2MB
2460 * page in create_pagetables(). They are zero filled.
2463 kernphys + ((vm_paddr_t)(i - 1) << PDRSHIFT) < KERNend) &&
2464 pmap_insert_pt_page(kernel_pmap, mpte, false))
2465 panic("pmap_init: pmap_insert_pt_page failed");
2467 PMAP_UNLOCK(kernel_pmap);
2471 * If the kernel is running on a virtual machine, then it must assume
2472 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2473 * be prepared for the hypervisor changing the vendor and family that
2474 * are reported by CPUID. Consequently, the workaround for AMD Family
2475 * 10h Erratum 383 is enabled if the processor's feature set does not
2476 * include at least one feature that is only supported by older Intel
2477 * or newer AMD processors.
2479 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2480 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2481 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2483 workaround_erratum383 = 1;
2486 * Are large page mappings enabled?
2488 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2489 if (pg_ps_enabled) {
2490 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2491 ("pmap_init: can't assign to pagesizes[1]"));
2492 pagesizes[1] = NBPDR;
2493 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2494 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2495 ("pmap_init: can't assign to pagesizes[2]"));
2496 pagesizes[2] = NBPDP;
2501 * Initialize pv chunk lists.
2503 for (i = 0; i < PMAP_MEMDOM; i++) {
2504 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2505 TAILQ_INIT(&pv_chunks[i].pvc_list);
2507 pmap_init_pv_table();
2509 pmap_initialized = 1;
2510 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2511 ppim = pmap_preinit_mapping + i;
2514 /* Make the direct map consistent */
2515 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2516 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2517 ppim->sz, ppim->mode);
2521 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2522 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2525 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2526 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2527 (vmem_addr_t *)&qframe);
2529 panic("qframe allocation failed");
2532 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2533 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2534 lm_ents = LMEPML4I - LMSPML4I + 1;
2536 if (lm_ents > KMSANORIGPML4I - LMSPML4I) {
2538 "pmap: shrinking large map for KMSAN (%d slots to %ld slots)\n",
2539 lm_ents, KMSANORIGPML4I - LMSPML4I);
2540 lm_ents = KMSANORIGPML4I - LMSPML4I;
2544 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2545 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2547 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2548 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2549 if (large_vmem == NULL) {
2550 printf("pmap: cannot create large map\n");
2553 for (i = 0; i < lm_ents; i++) {
2554 m = pmap_large_map_getptp_unlocked();
2556 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2557 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2563 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2564 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2565 "Maximum number of PML4 entries for use by large map (tunable). "
2566 "Each entry corresponds to 512GB of address space.");
2568 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2569 "2MB page mapping counters");
2571 static COUNTER_U64_DEFINE_EARLY(pmap_pde_demotions);
2572 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, demotions,
2573 CTLFLAG_RD, &pmap_pde_demotions, "2MB page demotions");
2575 static COUNTER_U64_DEFINE_EARLY(pmap_pde_mappings);
2576 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2577 &pmap_pde_mappings, "2MB page mappings");
2579 static COUNTER_U64_DEFINE_EARLY(pmap_pde_p_failures);
2580 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2581 &pmap_pde_p_failures, "2MB page promotion failures");
2583 static COUNTER_U64_DEFINE_EARLY(pmap_pde_promotions);
2584 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2585 &pmap_pde_promotions, "2MB page promotions");
2587 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2588 "1GB page mapping counters");
2590 static COUNTER_U64_DEFINE_EARLY(pmap_pdpe_demotions);
2591 SYSCTL_COUNTER_U64(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2592 &pmap_pdpe_demotions, "1GB page demotions");
2594 /***************************************************
2595 * Low level helper routines.....
2596 ***************************************************/
2599 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2601 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2603 switch (pmap->pm_type) {
2606 /* Verify that both PAT bits are not set at the same time */
2607 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2608 ("Invalid PAT bits in entry %#lx", entry));
2610 /* Swap the PAT bits if one of them is set */
2611 if ((entry & x86_pat_bits) != 0)
2612 entry ^= x86_pat_bits;
2616 * Nothing to do - the memory attributes are represented
2617 * the same way for regular pages and superpages.
2621 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2628 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2631 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2632 pat_index[(int)mode] >= 0);
2636 * Determine the appropriate bits to set in a PTE or PDE for a specified
2640 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2642 int cache_bits, pat_flag, pat_idx;
2644 if (!pmap_is_valid_memattr(pmap, mode))
2645 panic("Unknown caching mode %d\n", mode);
2647 switch (pmap->pm_type) {
2650 /* The PAT bit is different for PTE's and PDE's. */
2651 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2653 /* Map the caching mode to a PAT index. */
2654 pat_idx = pat_index[mode];
2656 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2659 cache_bits |= pat_flag;
2661 cache_bits |= PG_NC_PCD;
2663 cache_bits |= PG_NC_PWT;
2667 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2671 panic("unsupported pmap type %d", pmap->pm_type);
2674 return (cache_bits);
2678 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2682 switch (pmap->pm_type) {
2685 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2688 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2691 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2698 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2700 int pat_flag, pat_idx;
2703 switch (pmap->pm_type) {
2706 /* The PAT bit is different for PTE's and PDE's. */
2707 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2709 if ((pte & pat_flag) != 0)
2711 if ((pte & PG_NC_PCD) != 0)
2713 if ((pte & PG_NC_PWT) != 0)
2717 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2718 panic("EPT PTE %#lx has no PAT memory type", pte);
2719 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2723 /* See pmap_init_pat(). */
2733 pmap_ps_enabled(pmap_t pmap)
2736 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2740 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2743 switch (pmap->pm_type) {
2750 * This is a little bogus since the generation number is
2751 * supposed to be bumped up when a region of the address
2752 * space is invalidated in the page tables.
2754 * In this case the old PDE entry is valid but yet we want
2755 * to make sure that any mappings using the old entry are
2756 * invalidated in the TLB.
2758 * The reason this works as expected is because we rendezvous
2759 * "all" host cpus and force any vcpu context to exit as a
2762 atomic_add_long(&pmap->pm_eptgen, 1);
2765 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2767 pde_store(pde, newpde);
2771 * After changing the page size for the specified virtual address in the page
2772 * table, flush the corresponding entries from the processor's TLB. Only the
2773 * calling processor's TLB is affected.
2775 * The calling thread must be pinned to a processor.
2778 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2782 if (pmap_type_guest(pmap))
2785 KASSERT(pmap->pm_type == PT_X86,
2786 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2788 PG_G = pmap_global_bit(pmap);
2790 if ((newpde & PG_PS) == 0)
2791 /* Demotion: flush a specific 2MB page mapping. */
2793 else if ((newpde & PG_G) == 0)
2795 * Promotion: flush every 4KB page mapping from the TLB
2796 * because there are too many to flush individually.
2801 * Promotion: flush every 4KB page mapping from the TLB,
2802 * including any global (PG_G) mappings.
2809 * The amd64 pmap uses different approaches to TLB invalidation
2810 * depending on the kernel configuration, available hardware features,
2811 * and known hardware errata. The kernel configuration option that
2812 * has the greatest operational impact on TLB invalidation is PTI,
2813 * which is enabled automatically on affected Intel CPUs. The most
2814 * impactful hardware features are first PCID, and then INVPCID
2815 * instruction presence. PCID usage is quite different for PTI
2818 * * Kernel Page Table Isolation (PTI or KPTI) is used to mitigate
2819 * the Meltdown bug in some Intel CPUs. Under PTI, each user address
2820 * space is served by two page tables, user and kernel. The user
2821 * page table only maps user space and a kernel trampoline. The
2822 * kernel trampoline includes the entirety of the kernel text but
2823 * only the kernel data that is needed to switch from user to kernel
2824 * mode. The kernel page table maps the user and kernel address
2825 * spaces in their entirety. It is identical to the per-process
2826 * page table used in non-PTI mode.
2828 * User page tables are only used when the CPU is in user mode.
2829 * Consequently, some TLB invalidations can be postponed until the
2830 * switch from kernel to user mode. In contrast, the user
2831 * space part of the kernel page table is used for copyout(9), so
2832 * TLB invalidations on this page table cannot be similarly postponed.
2834 * The existence of a user mode page table for the given pmap is
2835 * indicated by a pm_ucr3 value that differs from PMAP_NO_CR3, in
2836 * which case pm_ucr3 contains the %cr3 register value for the user
2837 * mode page table's root.
2839 * * The pm_active bitmask indicates which CPUs currently have the
2840 * pmap active. A CPU's bit is set on context switch to the pmap, and
2841 * cleared on switching off this CPU. For the kernel page table,
2842 * the pm_active field is immutable and contains all CPUs. The
2843 * kernel page table is always logically active on every processor,
2844 * but not necessarily in use by the hardware, e.g., in PTI mode.
2846 * When requesting invalidation of virtual addresses with
2847 * pmap_invalidate_XXX() functions, the pmap sends shootdown IPIs to
2848 * all CPUs recorded as active in pm_active. Updates to and reads
2849 * from pm_active are not synchronized, and so they may race with
2850 * each other. Shootdown handlers are prepared to handle the race.
2852 * * PCID is an optional feature of the long mode x86 MMU where TLB
2853 * entries are tagged with the 'Process ID' of the address space
2854 * they belong to. This feature provides a limited namespace for
2855 * process identifiers, 12 bits, supporting 4095 simultaneous IDs
2858 * Allocation of a PCID to a pmap is done by an algorithm described
2859 * in section 15.12, "Other TLB Consistency Algorithms", of
2860 * Vahalia's book "Unix Internals". A PCID cannot be allocated for
2861 * the whole lifetime of a pmap in pmap_pinit() due to the limited
2862 * namespace. Instead, a per-CPU, per-pmap PCID is assigned when
2863 * the CPU is about to start caching TLB entries from a pmap,
2864 * i.e., on the context switch that activates the pmap on the CPU.
2866 * The PCID allocator maintains a per-CPU, per-pmap generation
2867 * count, pm_gen, which is incremented each time a new PCID is
2868 * allocated. On TLB invalidation, the generation counters for the
2869 * pmap are zeroed, which signals the context switch code that the
2870 * previously allocated PCID is no longer valid. Effectively,
2871 * zeroing any of these counters triggers a TLB shootdown for the
2872 * given CPU/address space, due to the allocation of a new PCID.
2874 * Zeroing can be performed remotely. Consequently, if a pmap is
2875 * inactive on a CPU, then a TLB shootdown for that pmap and CPU can
2876 * be initiated by an ordinary memory access to reset the target
2877 * CPU's generation count within the pmap. The CPU initiating the
2878 * TLB shootdown does not need to send an IPI to the target CPU.
2880 * * PTI + PCID. The available PCIDs are divided into two sets: PCIDs
2881 * for complete (kernel) page tables, and PCIDs for user mode page
2882 * tables. A user PCID value is obtained from the kernel PCID value
2883 * by setting the highest bit, 11, to 1 (0x800 == PMAP_PCID_USER_PT).
2885 * User space page tables are activated on return to user mode, by
2886 * loading pm_ucr3 into %cr3. If the PCPU(ucr3_load_mask) requests
2887 * clearing bit 63 of the loaded ucr3, this effectively causes
2888 * complete invalidation of the user mode TLB entries for the
2889 * current pmap. In which case, local invalidations of individual
2890 * pages in the user page table are skipped.
2892 * * Local invalidation, all modes. If the requested invalidation is
2893 * for a specific address or the total invalidation of a currently
2894 * active pmap, then the TLB is flushed using INVLPG for a kernel
2895 * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a
2896 * user space page table(s).
2898 * If the INVPCID instruction is available, it is used to flush entries
2899 * from the kernel page table.
2901 * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its
2902 * address space, all other 4095 PCIDs are used for user mode spaces
2903 * as described above. A context switch allocates a new PCID if
2904 * the recorded PCID is zero or the recorded generation does not match
2905 * the CPU's generation, effectively flushing the TLB for this address space.
2906 * Total remote invalidation is performed by zeroing pm_gen for all CPUs.
2907 * local user page: INVLPG
2908 * local kernel page: INVLPG
2909 * local user total: INVPCID(CTX)
2910 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2911 * remote user page, inactive pmap: zero pm_gen
2912 * remote user page, active pmap: zero pm_gen + IPI:INVLPG
2913 * (Both actions are required to handle the aforementioned pm_active races.)
2914 * remote kernel page: IPI:INVLPG
2915 * remote user total, inactive pmap: zero pm_gen
2916 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) or
2918 * (See note above about pm_active races.)
2919 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2921 * PTI enabled, PCID present.
2922 * local user page: INVLPG for kpt, INVPCID(ADDR) or (INVLPG for ucr3)
2924 * local kernel page: INVLPG
2925 * local user total: INVPCID(CTX) or reload %cr3 for kpt, clear PCID_SAVE
2926 * on loading UCR3 into %cr3 for upt
2927 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2928 * remote user page, inactive pmap: zero pm_gen
2929 * remote user page, active pmap: zero pm_gen + IPI:(INVLPG for kpt,
2930 * INVPCID(ADDR) for upt)
2931 * remote kernel page: IPI:INVLPG
2932 * remote user total, inactive pmap: zero pm_gen
2933 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) for kpt,
2934 * clear PCID_SAVE on loading UCR3 into $cr3 for upt)
2935 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2938 * local user page: INVLPG
2939 * local kernel page: INVLPG
2940 * local user total: reload %cr3
2941 * local kernel total: invltlb_glob()
2942 * remote user page, inactive pmap: -
2943 * remote user page, active pmap: IPI:INVLPG
2944 * remote kernel page: IPI:INVLPG
2945 * remote user total, inactive pmap: -
2946 * remote user total, active pmap: IPI:(reload %cr3)
2947 * remote kernel total: IPI:invltlb_glob()
2948 * Since on return to user mode, the reload of %cr3 with ucr3 causes
2949 * TLB invalidation, no specific action is required for user page table.
2951 * EPT. EPT pmaps do not map KVA, all mappings are userspace.
2957 * Interrupt the cpus that are executing in the guest context.
2958 * This will force the vcpu to exit and the cached EPT mappings
2959 * will be invalidated by the host before the next vmresume.
2961 static __inline void
2962 pmap_invalidate_ept(pmap_t pmap)
2968 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2969 ("pmap_invalidate_ept: absurd pm_active"));
2972 * The TLB mappings associated with a vcpu context are not
2973 * flushed each time a different vcpu is chosen to execute.
2975 * This is in contrast with a process's vtop mappings that
2976 * are flushed from the TLB on each context switch.
2978 * Therefore we need to do more than just a TLB shootdown on
2979 * the active cpus in 'pmap->pm_active'. To do this we keep
2980 * track of the number of invalidations performed on this pmap.
2982 * Each vcpu keeps a cache of this counter and compares it
2983 * just before a vmresume. If the counter is out-of-date an
2984 * invept will be done to flush stale mappings from the TLB.
2986 * To ensure that all vCPU threads have observed the new counter
2987 * value before returning, we use SMR. Ordering is important here:
2988 * the VMM enters an SMR read section before loading the counter
2989 * and after updating the pm_active bit set. Thus, pm_active is
2990 * a superset of active readers, and any reader that has observed
2991 * the goal has observed the new counter value.
2993 atomic_add_long(&pmap->pm_eptgen, 1);
2995 goal = smr_advance(pmap->pm_eptsmr);
2998 * Force the vcpu to exit and trap back into the hypervisor.
3000 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
3001 ipi_selected(pmap->pm_active, ipinum);
3005 * Ensure that all active vCPUs will observe the new generation counter
3006 * value before executing any more guest instructions.
3008 smr_wait(pmap->pm_eptsmr, goal);
3012 pmap_invalidate_cpu_mask(pmap_t pmap)
3014 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
3018 pmap_invalidate_preipi_pcid(pmap_t pmap)
3024 cpuid = PCPU_GET(cpuid);
3025 if (pmap != PCPU_GET(curpmap))
3026 cpuid = 0xffffffff; /* An impossible value */
3030 pmap->pm_pcids[i].pm_gen = 0;
3034 * The fence is between stores to pm_gen and the read of the
3035 * pm_active mask. We need to ensure that it is impossible
3036 * for us to miss the bit update in pm_active and
3037 * simultaneously observe a non-zero pm_gen in
3038 * pmap_activate_sw(), otherwise TLB update is missed.
3039 * Without the fence, IA32 allows such an outcome. Note that
3040 * pm_active is updated by a locked operation, which provides
3041 * the reciprocal fence.
3043 atomic_thread_fence_seq_cst();
3047 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
3052 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t))
3054 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
3055 pmap_invalidate_preipi_nopcid);
3059 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
3060 const bool invpcid_works1)
3062 struct invpcid_descr d;
3063 uint64_t kcr3, ucr3;
3068 * Because pm_pcid is recalculated on a context switch, we
3069 * must ensure there is no preemption, not just pinning.
3070 * Otherwise, we might use a stale value below.
3072 CRITICAL_ASSERT(curthread);
3075 * No need to do anything with user page tables invalidation
3076 * if there is no user page table, or invalidation is deferred
3077 * until the return to userspace. ucr3_load_mask is stable
3078 * because we have preemption disabled.
3080 if (pmap->pm_ucr3 == PMAP_NO_CR3 ||
3081 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3084 cpuid = PCPU_GET(cpuid);
3086 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3087 if (invpcid_works1) {
3088 d.pcid = pcid | PMAP_PCID_USER_PT;
3091 invpcid(&d, INVPCID_ADDR);
3093 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3094 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3095 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3100 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
3102 pmap_invalidate_page_pcid_cb(pmap, va, true);
3106 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
3108 pmap_invalidate_page_pcid_cb(pmap, va, false);
3112 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
3116 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t))
3118 if (pmap_pcid_enabled)
3119 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
3120 pmap_invalidate_page_pcid_noinvpcid_cb);
3121 return (pmap_invalidate_page_nopcid_cb);
3125 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
3126 vm_offset_t addr2 __unused)
3128 if (pmap == kernel_pmap) {
3130 } else if (pmap == PCPU_GET(curpmap)) {
3132 pmap_invalidate_page_cb(pmap, va);
3137 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3139 if (pmap_type_guest(pmap)) {
3140 pmap_invalidate_ept(pmap);
3144 KASSERT(pmap->pm_type == PT_X86,
3145 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
3147 pmap_invalidate_preipi(pmap);
3148 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
3149 pmap_invalidate_page_curcpu_cb);
3152 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
3153 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
3156 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3157 const bool invpcid_works1)
3159 struct invpcid_descr d;
3160 uint64_t kcr3, ucr3;
3164 CRITICAL_ASSERT(curthread);
3166 if (pmap != PCPU_GET(curpmap) ||
3167 pmap->pm_ucr3 == PMAP_NO_CR3 ||
3168 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3171 cpuid = PCPU_GET(cpuid);
3173 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3174 if (invpcid_works1) {
3175 d.pcid = pcid | PMAP_PCID_USER_PT;
3177 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
3178 invpcid(&d, INVPCID_ADDR);
3180 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3181 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3182 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3187 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
3190 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
3194 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
3197 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
3201 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
3202 vm_offset_t eva __unused)
3206 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
3209 if (pmap_pcid_enabled)
3210 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
3211 pmap_invalidate_range_pcid_noinvpcid_cb);
3212 return (pmap_invalidate_range_nopcid_cb);
3216 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3220 if (pmap == kernel_pmap) {
3221 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3223 } else if (pmap == PCPU_GET(curpmap)) {
3224 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3226 pmap_invalidate_range_cb(pmap, sva, eva);
3231 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3233 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
3234 pmap_invalidate_all(pmap);
3238 if (pmap_type_guest(pmap)) {
3239 pmap_invalidate_ept(pmap);
3243 KASSERT(pmap->pm_type == PT_X86,
3244 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3246 pmap_invalidate_preipi(pmap);
3247 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
3248 pmap_invalidate_range_curcpu_cb);
3252 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
3254 struct invpcid_descr d;
3259 if (pmap == kernel_pmap) {
3260 if (invpcid_works1) {
3261 bzero(&d, sizeof(d));
3262 invpcid(&d, INVPCID_CTXGLOB);
3266 } else if (pmap == PCPU_GET(curpmap)) {
3267 CRITICAL_ASSERT(curthread);
3268 cpuid = PCPU_GET(cpuid);
3270 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3271 if (invpcid_works1) {
3275 invpcid(&d, INVPCID_CTX);
3277 kcr3 = pmap->pm_cr3 | pcid;
3280 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3281 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3286 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
3288 pmap_invalidate_all_pcid_cb(pmap, true);
3292 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
3294 pmap_invalidate_all_pcid_cb(pmap, false);
3298 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
3300 if (pmap == kernel_pmap)
3302 else if (pmap == PCPU_GET(curpmap))
3306 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t))
3308 if (pmap_pcid_enabled)
3309 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
3310 pmap_invalidate_all_pcid_noinvpcid_cb);
3311 return (pmap_invalidate_all_nopcid_cb);
3315 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3316 vm_offset_t addr2 __unused)
3318 pmap_invalidate_all_cb(pmap);
3322 pmap_invalidate_all(pmap_t pmap)
3324 if (pmap_type_guest(pmap)) {
3325 pmap_invalidate_ept(pmap);
3329 KASSERT(pmap->pm_type == PT_X86,
3330 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3332 pmap_invalidate_preipi(pmap);
3333 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3334 pmap_invalidate_all_curcpu_cb);
3338 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3339 vm_offset_t addr2 __unused)
3345 pmap_invalidate_cache(void)
3348 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3352 cpuset_t invalidate; /* processors that invalidate their TLB */
3357 u_int store; /* processor that updates the PDE */
3361 pmap_update_pde_action(void *arg)
3363 struct pde_action *act = arg;
3365 if (act->store == PCPU_GET(cpuid))
3366 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3370 pmap_update_pde_teardown(void *arg)
3372 struct pde_action *act = arg;
3374 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3375 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3379 * Change the page size for the specified virtual address in a way that
3380 * prevents any possibility of the TLB ever having two entries that map the
3381 * same virtual address using different page sizes. This is the recommended
3382 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3383 * machine check exception for a TLB state that is improperly diagnosed as a
3387 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3389 struct pde_action act;
3390 cpuset_t active, other_cpus;
3394 cpuid = PCPU_GET(cpuid);
3395 other_cpus = all_cpus;
3396 CPU_CLR(cpuid, &other_cpus);
3397 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3400 active = pmap->pm_active;
3402 if (CPU_OVERLAP(&active, &other_cpus)) {
3404 act.invalidate = active;
3408 act.newpde = newpde;
3409 CPU_SET(cpuid, &active);
3410 smp_rendezvous_cpus(active,
3411 smp_no_rendezvous_barrier, pmap_update_pde_action,
3412 pmap_update_pde_teardown, &act);
3414 pmap_update_pde_store(pmap, pde, newpde);
3415 if (CPU_ISSET(cpuid, &active))
3416 pmap_update_pde_invalidate(pmap, va, newpde);
3422 * Normal, non-SMP, invalidation functions.
3425 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3427 struct invpcid_descr d;
3428 uint64_t kcr3, ucr3;
3431 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3435 KASSERT(pmap->pm_type == PT_X86,
3436 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3438 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3440 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3441 pmap->pm_ucr3 != PMAP_NO_CR3) {
3443 pcid = pmap->pm_pcids[0].pm_pcid;
3444 if (invpcid_works) {
3445 d.pcid = pcid | PMAP_PCID_USER_PT;
3448 invpcid(&d, INVPCID_ADDR);
3450 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3451 ucr3 = pmap->pm_ucr3 | pcid |
3452 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3453 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3457 } else if (pmap_pcid_enabled)
3458 pmap->pm_pcids[0].pm_gen = 0;
3462 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3464 struct invpcid_descr d;
3466 uint64_t kcr3, ucr3;
3468 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3472 KASSERT(pmap->pm_type == PT_X86,
3473 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3475 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3476 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3478 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3479 pmap->pm_ucr3 != PMAP_NO_CR3) {
3481 if (invpcid_works) {
3482 d.pcid = pmap->pm_pcids[0].pm_pcid |
3486 for (; d.addr < eva; d.addr += PAGE_SIZE)
3487 invpcid(&d, INVPCID_ADDR);
3489 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3490 pm_pcid | CR3_PCID_SAVE;
3491 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3492 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3493 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3497 } else if (pmap_pcid_enabled) {
3498 pmap->pm_pcids[0].pm_gen = 0;
3503 pmap_invalidate_all(pmap_t pmap)
3505 struct invpcid_descr d;
3506 uint64_t kcr3, ucr3;
3508 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3512 KASSERT(pmap->pm_type == PT_X86,
3513 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3515 if (pmap == kernel_pmap) {
3516 if (pmap_pcid_enabled && invpcid_works) {
3517 bzero(&d, sizeof(d));
3518 invpcid(&d, INVPCID_CTXGLOB);
3522 } else if (pmap == PCPU_GET(curpmap)) {
3523 if (pmap_pcid_enabled) {
3525 if (invpcid_works) {
3526 d.pcid = pmap->pm_pcids[0].pm_pcid;
3529 invpcid(&d, INVPCID_CTX);
3530 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3531 d.pcid |= PMAP_PCID_USER_PT;
3532 invpcid(&d, INVPCID_CTX);
3535 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3536 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3537 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3538 0].pm_pcid | PMAP_PCID_USER_PT;
3539 pmap_pti_pcid_invalidate(ucr3, kcr3);
3547 } else if (pmap_pcid_enabled) {
3548 pmap->pm_pcids[0].pm_gen = 0;
3553 pmap_invalidate_cache(void)
3560 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3563 pmap_update_pde_store(pmap, pde, newpde);
3564 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3565 pmap_update_pde_invalidate(pmap, va, newpde);
3567 pmap->pm_pcids[0].pm_gen = 0;
3572 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3576 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3577 * by a promotion that did not invalidate the 512 4KB page mappings
3578 * that might exist in the TLB. Consequently, at this point, the TLB
3579 * may hold both 4KB and 2MB page mappings for the address range [va,
3580 * va + NBPDR). Therefore, the entire range must be invalidated here.
3581 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3582 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3583 * single INVLPG suffices to invalidate the 2MB page mapping from the
3586 if ((pde & PG_PROMOTED) != 0)
3587 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3589 pmap_invalidate_page(pmap, va);
3592 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3593 (vm_offset_t sva, vm_offset_t eva))
3596 if ((cpu_feature & CPUID_SS) != 0)
3597 return (pmap_invalidate_cache_range_selfsnoop);
3598 if ((cpu_feature & CPUID_CLFSH) != 0)
3599 return (pmap_force_invalidate_cache_range);
3600 return (pmap_invalidate_cache_range_all);
3603 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3606 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3609 KASSERT((sva & PAGE_MASK) == 0,
3610 ("pmap_invalidate_cache_range: sva not page-aligned"));
3611 KASSERT((eva & PAGE_MASK) == 0,
3612 ("pmap_invalidate_cache_range: eva not page-aligned"));
3616 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3619 pmap_invalidate_cache_range_check_align(sva, eva);
3623 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3626 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3629 * XXX: Some CPUs fault, hang, or trash the local APIC
3630 * registers if we use CLFLUSH on the local APIC range. The
3631 * local APIC is always uncached, so we don't need to flush
3632 * for that range anyway.
3634 if (pmap_kextract(sva) == lapic_paddr)
3637 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3639 * Do per-cache line flush. Use a locked
3640 * instruction to insure that previous stores are
3641 * included in the write-back. The processor
3642 * propagates flush to other processors in the cache
3645 atomic_thread_fence_seq_cst();
3646 for (; sva < eva; sva += cpu_clflush_line_size)
3648 atomic_thread_fence_seq_cst();
3651 * Writes are ordered by CLFLUSH on Intel CPUs.
3653 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3655 for (; sva < eva; sva += cpu_clflush_line_size)
3657 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3663 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3666 pmap_invalidate_cache_range_check_align(sva, eva);
3667 pmap_invalidate_cache();
3671 * Remove the specified set of pages from the data and instruction caches.
3673 * In contrast to pmap_invalidate_cache_range(), this function does not
3674 * rely on the CPU's self-snoop feature, because it is intended for use
3675 * when moving pages into a different cache domain.
3678 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3680 vm_offset_t daddr, eva;
3684 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3685 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3686 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3687 pmap_invalidate_cache();
3690 atomic_thread_fence_seq_cst();
3691 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3693 for (i = 0; i < count; i++) {
3694 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3695 eva = daddr + PAGE_SIZE;
3696 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3704 atomic_thread_fence_seq_cst();
3705 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3711 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3714 pmap_invalidate_cache_range_check_align(sva, eva);
3716 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3717 pmap_force_invalidate_cache_range(sva, eva);
3721 /* See comment in pmap_force_invalidate_cache_range(). */
3722 if (pmap_kextract(sva) == lapic_paddr)
3725 atomic_thread_fence_seq_cst();
3726 for (; sva < eva; sva += cpu_clflush_line_size)
3728 atomic_thread_fence_seq_cst();
3732 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3736 int error, pte_bits;
3738 KASSERT((spa & PAGE_MASK) == 0,
3739 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3740 KASSERT((epa & PAGE_MASK) == 0,
3741 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3743 if (spa < dmaplimit) {
3744 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3746 if (dmaplimit >= epa)
3751 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3753 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3755 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3756 pte = vtopte(vaddr);
3757 for (; spa < epa; spa += PAGE_SIZE) {
3759 pte_store(pte, spa | pte_bits);
3761 /* XXXKIB atomic inside flush_cache_range are excessive */
3762 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3765 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3769 * Routine: pmap_extract
3771 * Extract the physical page address associated
3772 * with the given map/virtual_address pair.
3775 pmap_extract(pmap_t pmap, vm_offset_t va)
3779 pt_entry_t *pte, PG_V;
3783 PG_V = pmap_valid_bit(pmap);
3785 pdpe = pmap_pdpe(pmap, va);
3786 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3787 if ((*pdpe & PG_PS) != 0)
3788 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3790 pde = pmap_pdpe_to_pde(pdpe, va);
3791 if ((*pde & PG_V) != 0) {
3792 if ((*pde & PG_PS) != 0) {
3793 pa = (*pde & PG_PS_FRAME) |
3796 pte = pmap_pde_to_pte(pde, va);
3797 pa = (*pte & PG_FRAME) |
3808 * Routine: pmap_extract_and_hold
3810 * Atomically extract and hold the physical page
3811 * with the given pmap and virtual address pair
3812 * if that mapping permits the given protection.
3815 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3817 pdp_entry_t pdpe, *pdpep;
3818 pd_entry_t pde, *pdep;
3819 pt_entry_t pte, PG_RW, PG_V;
3823 PG_RW = pmap_rw_bit(pmap);
3824 PG_V = pmap_valid_bit(pmap);
3827 pdpep = pmap_pdpe(pmap, va);
3828 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3830 if ((pdpe & PG_PS) != 0) {
3831 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3833 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3837 pdep = pmap_pdpe_to_pde(pdpep, va);
3838 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3840 if ((pde & PG_PS) != 0) {
3841 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3843 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3847 pte = *pmap_pde_to_pte(pdep, va);
3848 if ((pte & PG_V) == 0 ||
3849 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3851 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3854 if (m != NULL && !vm_page_wire_mapped(m))
3862 pmap_kextract(vm_offset_t va)
3867 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3868 pa = DMAP_TO_PHYS(va);
3869 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3870 pa = pmap_large_map_kextract(va);
3874 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3877 * Beware of a concurrent promotion that changes the
3878 * PDE at this point! For example, vtopte() must not
3879 * be used to access the PTE because it would use the
3880 * new PDE. It is, however, safe to use the old PDE
3881 * because the page table page is preserved by the
3884 pa = *pmap_pde_to_pte(&pde, va);
3885 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3891 /***************************************************
3892 * Low level mapping routines.....
3893 ***************************************************/
3896 * Add a wired page to the kva.
3897 * Note: not SMP coherent.
3900 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3905 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3908 static __inline void
3909 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3915 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3916 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3920 * Remove a page from the kernel pagetables.
3921 * Note: not SMP coherent.
3924 pmap_kremove(vm_offset_t va)
3933 * Used to map a range of physical addresses into kernel
3934 * virtual address space.
3936 * The value passed in '*virt' is a suggested virtual address for
3937 * the mapping. Architectures which can support a direct-mapped
3938 * physical to virtual region can return the appropriate address
3939 * within that region, leaving '*virt' unchanged. Other
3940 * architectures should map the pages starting at '*virt' and
3941 * update '*virt' with the first usable address after the mapped
3945 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3947 return PHYS_TO_DMAP(start);
3951 * Add a list of wired pages to the kva
3952 * this routine is only used for temporary
3953 * kernel mappings that do not need to have
3954 * page modification or references recorded.
3955 * Note that old mappings are simply written
3956 * over. The page *must* be wired.
3957 * Note: SMP coherent. Uses a ranged shootdown IPI.
3960 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3962 pt_entry_t *endpte, oldpte, pa, *pte;
3968 endpte = pte + count;
3969 while (pte < endpte) {
3971 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3972 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3973 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3975 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3979 if (__predict_false((oldpte & X86_PG_V) != 0))
3980 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3985 * This routine tears out page mappings from the
3986 * kernel -- it is meant only for temporary mappings.
3987 * Note: SMP coherent. Uses a ranged shootdown IPI.
3990 pmap_qremove(vm_offset_t sva, int count)
3995 while (count-- > 0) {
3996 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
4000 pmap_invalidate_range(kernel_pmap, sva, va);
4003 /***************************************************
4004 * Page table page management routines.....
4005 ***************************************************/
4007 * Schedule the specified unused page table page to be freed. Specifically,
4008 * add the page to the specified list of pages that will be released to the
4009 * physical memory manager after the TLB has been updated.
4011 static __inline void
4012 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
4013 boolean_t set_PG_ZERO)
4017 m->flags |= PG_ZERO;
4019 m->flags &= ~PG_ZERO;
4020 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
4024 * Inserts the specified page table page into the specified pmap's collection
4025 * of idle page table pages. Each of a pmap's page table pages is responsible
4026 * for mapping a distinct range of virtual addresses. The pmap's collection is
4027 * ordered by this virtual address range.
4029 * If "promoted" is false, then the page table page "mpte" must be zero filled.
4032 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
4035 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4036 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
4037 return (vm_radix_insert(&pmap->pm_root, mpte));
4041 * Removes the page table page mapping the specified virtual address from the
4042 * specified pmap's collection of idle page table pages, and returns it.
4043 * Otherwise, returns NULL if there is no page table page corresponding to the
4044 * specified virtual address.
4046 static __inline vm_page_t
4047 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
4050 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4051 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
4055 * Decrements a page table page's reference count, which is used to record the
4056 * number of valid page table entries within the page. If the reference count
4057 * drops to zero, then the page table page is unmapped. Returns TRUE if the
4058 * page table page was unmapped and FALSE otherwise.
4060 static inline boolean_t
4061 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4065 if (m->ref_count == 0) {
4066 _pmap_unwire_ptp(pmap, va, m, free);
4073 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4079 vm_page_t pdpg, pdppg, pml4pg;
4081 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4084 * unmap the page table page
4086 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
4088 MPASS(pmap_is_la57(pmap));
4089 pml5 = pmap_pml5e(pmap, va);
4091 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
4092 pml5 = pmap_pml5e_u(pmap, va);
4095 } else if (m->pindex >= NUPDE + NUPDPE) {
4097 pml4 = pmap_pml4e(pmap, va);
4099 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4100 va <= VM_MAXUSER_ADDRESS) {
4101 pml4 = pmap_pml4e_u(pmap, va);
4104 } else if (m->pindex >= NUPDE) {
4106 pdp = pmap_pdpe(pmap, va);
4110 pd = pmap_pde(pmap, va);
4113 if (m->pindex < NUPDE) {
4114 /* We just released a PT, unhold the matching PD */
4115 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
4116 pmap_unwire_ptp(pmap, va, pdpg, free);
4117 } else if (m->pindex < NUPDE + NUPDPE) {
4118 /* We just released a PD, unhold the matching PDP */
4119 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
4120 pmap_unwire_ptp(pmap, va, pdppg, free);
4121 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
4122 /* We just released a PDP, unhold the matching PML4 */
4123 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
4124 pmap_unwire_ptp(pmap, va, pml4pg, free);
4127 pmap_pt_page_count_adj(pmap, -1);
4130 * Put page on a list so that it is released after
4131 * *ALL* TLB shootdown is done
4133 pmap_add_delayed_free_list(m, free, TRUE);
4137 * After removing a page table entry, this routine is used to
4138 * conditionally free the page, and manage the reference count.
4141 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
4142 struct spglist *free)
4146 if (va >= VM_MAXUSER_ADDRESS)
4148 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
4149 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
4150 return (pmap_unwire_ptp(pmap, va, mpte, free));
4154 * Release a page table page reference after a failed attempt to create a
4158 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
4160 struct spglist free;
4163 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4165 * Although "va" was never mapped, paging-structure caches
4166 * could nonetheless have entries that refer to the freed
4167 * page table pages. Invalidate those entries.
4169 pmap_invalidate_page(pmap, va);
4170 vm_page_free_pages_toq(&free, true);
4175 pmap_pinit0(pmap_t pmap)
4181 PMAP_LOCK_INIT(pmap);
4182 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
4183 pmap->pm_pmltopu = NULL;
4184 pmap->pm_cr3 = kernel_pmap->pm_cr3;
4185 /* hack to keep pmap_pti_pcid_invalidate() alive */
4186 pmap->pm_ucr3 = PMAP_NO_CR3;
4187 pmap->pm_root.rt_root = 0;
4188 CPU_ZERO(&pmap->pm_active);
4189 TAILQ_INIT(&pmap->pm_pvchunk);
4190 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4191 pmap->pm_flags = pmap_flags;
4193 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
4194 pmap->pm_pcids[i].pm_gen = 1;
4196 pmap_activate_boot(pmap);
4201 p->p_md.md_flags |= P_MD_KPTI;
4204 pmap_thread_init_invl_gen(td);
4206 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4207 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
4208 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
4214 pmap_pinit_pml4(vm_page_t pml4pg)
4216 pml4_entry_t *pm_pml4;
4219 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
4221 /* Wire in kernel global address entries. */
4222 for (i = 0; i < NKPML4E; i++) {
4223 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
4227 for (i = 0; i < NKASANPML4E; i++) {
4228 pm_pml4[KASANPML4I + i] = (KASANPDPphys + ptoa(i)) | X86_PG_RW |
4233 for (i = 0; i < NKMSANSHADPML4E; i++) {
4234 pm_pml4[KMSANSHADPML4I + i] = (KMSANSHADPDPphys + ptoa(i)) |
4235 X86_PG_RW | X86_PG_V | pg_nx;
4237 for (i = 0; i < NKMSANORIGPML4E; i++) {
4238 pm_pml4[KMSANORIGPML4I + i] = (KMSANORIGPDPphys + ptoa(i)) |
4239 X86_PG_RW | X86_PG_V | pg_nx;
4242 for (i = 0; i < ndmpdpphys; i++) {
4243 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
4247 /* install self-referential address mapping entry(s) */
4248 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
4249 X86_PG_A | X86_PG_M;
4251 /* install large map entries if configured */
4252 for (i = 0; i < lm_ents; i++)
4253 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4257 pmap_pinit_pml5(vm_page_t pml5pg)
4259 pml5_entry_t *pm_pml5;
4261 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4264 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4265 * entering all existing kernel mappings into level 5 table.
4267 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4268 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4269 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4272 * Install self-referential address mapping entry.
4274 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4275 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4276 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4280 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4282 pml4_entry_t *pm_pml4u;
4285 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4286 for (i = 0; i < NPML4EPG; i++)
4287 pm_pml4u[i] = pti_pml4[i];
4291 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4293 pml5_entry_t *pm_pml5u;
4295 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4298 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4299 * table, entering all kernel mappings needed for usermode
4300 * into level 5 table.
4302 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4303 pmap_kextract((vm_offset_t)pti_pml4) |
4304 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4305 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4308 /* Allocate a page table page and do related bookkeeping */
4310 pmap_alloc_pt_page(pmap_t pmap, vm_pindex_t pindex, int flags)
4314 m = vm_page_alloc(NULL, pindex, flags | VM_ALLOC_NOOBJ);
4315 if (__predict_false(m == NULL))
4318 pmap_pt_page_count_adj(pmap, 1);
4320 if ((flags & VM_ALLOC_ZERO) != 0 && (m->flags & PG_ZERO) == 0)
4327 pmap_free_pt_page(pmap_t pmap, vm_page_t m, bool zerofilled)
4330 * This function assumes the page will need to be unwired,
4331 * even though the counterpart allocation in pmap_alloc_pt_page()
4332 * doesn't enforce VM_ALLOC_WIRED. However, all current uses
4333 * of pmap_free_pt_page() require unwiring. The case in which
4334 * a PT page doesn't require unwiring because its ref_count has
4335 * naturally reached 0 is handled through _pmap_unwire_ptp().
4337 vm_page_unwire_noq(m);
4339 vm_page_free_zero(m);
4343 pmap_pt_page_count_adj(pmap, -1);
4347 * Initialize a preallocated and zeroed pmap structure,
4348 * such as one in a vmspace structure.
4351 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4353 vm_page_t pmltop_pg, pmltop_pgu;
4354 vm_paddr_t pmltop_phys;
4358 * allocate the page directory page
4360 pmltop_pg = pmap_alloc_pt_page(NULL, 0, VM_ALLOC_NORMAL |
4361 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4363 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4364 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4367 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4368 pmap->pm_pcids[i].pm_gen = 0;
4370 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4371 pmap->pm_ucr3 = PMAP_NO_CR3;
4372 pmap->pm_pmltopu = NULL;
4374 pmap->pm_type = pm_type;
4377 * Do not install the host kernel mappings in the nested page
4378 * tables. These mappings are meaningless in the guest physical
4380 * Install minimal kernel mappings in PTI case.
4384 pmap->pm_cr3 = pmltop_phys;
4385 if (pmap_is_la57(pmap))
4386 pmap_pinit_pml5(pmltop_pg);
4388 pmap_pinit_pml4(pmltop_pg);
4389 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4390 pmltop_pgu = pmap_alloc_pt_page(NULL, 0,
4391 VM_ALLOC_WIRED | VM_ALLOC_NORMAL |
4393 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4394 VM_PAGE_TO_PHYS(pmltop_pgu));
4395 if (pmap_is_la57(pmap))
4396 pmap_pinit_pml5_pti(pmltop_pgu);
4398 pmap_pinit_pml4_pti(pmltop_pgu);
4399 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4401 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4402 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4403 pkru_free_range, pmap, M_NOWAIT);
4408 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4412 pmap->pm_root.rt_root = 0;
4413 CPU_ZERO(&pmap->pm_active);
4414 TAILQ_INIT(&pmap->pm_pvchunk);
4415 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4416 pmap->pm_flags = flags;
4417 pmap->pm_eptgen = 0;
4423 pmap_pinit(pmap_t pmap)
4426 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4430 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4433 struct spglist free;
4435 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4436 if (mpg->ref_count != 0)
4439 _pmap_unwire_ptp(pmap, va, mpg, &free);
4440 pmap_invalidate_page(pmap, va);
4441 vm_page_free_pages_toq(&free, true);
4444 static pml4_entry_t *
4445 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4448 vm_pindex_t pml5index;
4455 if (!pmap_is_la57(pmap))
4456 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4458 PG_V = pmap_valid_bit(pmap);
4459 pml5index = pmap_pml5e_index(va);
4460 pml5 = &pmap->pm_pmltop[pml5index];
4461 if ((*pml5 & PG_V) == 0) {
4462 if (pmap_allocpte_nosleep(pmap, pmap_pml5e_pindex(va), lockp,
4469 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4470 pml4 = &pml4[pmap_pml4e_index(va)];
4471 if ((*pml4 & PG_V) == 0) {
4472 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4473 if (allocated && !addref)
4474 pml4pg->ref_count--;
4475 else if (!allocated && addref)
4476 pml4pg->ref_count++;
4481 static pdp_entry_t *
4482 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4491 PG_V = pmap_valid_bit(pmap);
4493 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4497 if ((*pml4 & PG_V) == 0) {
4498 /* Have to allocate a new pdp, recurse */
4499 if (pmap_allocpte_nosleep(pmap, pmap_pml4e_pindex(va), lockp,
4501 if (pmap_is_la57(pmap))
4502 pmap_allocpte_free_unref(pmap, va,
4503 pmap_pml5e(pmap, va));
4510 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4511 pdp = &pdp[pmap_pdpe_index(va)];
4512 if ((*pdp & PG_V) == 0) {
4513 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4514 if (allocated && !addref)
4516 else if (!allocated && addref)
4523 * The ptepindexes, i.e. page indices, of the page table pages encountered
4524 * while translating virtual address va are defined as follows:
4525 * - for the page table page (last level),
4526 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4527 * in other words, it is just the index of the PDE that maps the page
4529 * - for the page directory page,
4530 * ptepindex = NUPDE (number of userland PD entries) +
4531 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4532 * i.e. index of PDPE is put after the last index of PDE,
4533 * - for the page directory pointer page,
4534 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4536 * i.e. index of pml4e is put after the last index of PDPE,
4537 * - for the PML4 page (if LA57 mode is enabled),
4538 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4539 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4540 * i.e. index of pml5e is put after the last index of PML4E.
4542 * Define an order on the paging entries, where all entries of the
4543 * same height are put together, then heights are put from deepest to
4544 * root. Then ptexpindex is the sequential number of the
4545 * corresponding paging entry in this order.
4547 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4548 * LA57 paging structures even in LA48 paging mode. Moreover, the
4549 * ptepindexes are calculated as if the paging structures were 5-level
4550 * regardless of the actual mode of operation.
4552 * The root page at PML4/PML5 does not participate in this indexing scheme,
4553 * since it is statically allocated by pmap_pinit() and not by pmap_allocpte().
4556 pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4559 vm_pindex_t pml5index, pml4index;
4560 pml5_entry_t *pml5, *pml5u;
4561 pml4_entry_t *pml4, *pml4u;
4565 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4567 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4569 PG_A = pmap_accessed_bit(pmap);
4570 PG_M = pmap_modified_bit(pmap);
4571 PG_V = pmap_valid_bit(pmap);
4572 PG_RW = pmap_rw_bit(pmap);
4575 * Allocate a page table page.
4577 m = pmap_alloc_pt_page(pmap, ptepindex,
4578 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4583 * Map the pagetable page into the process address space, if
4584 * it isn't already there.
4586 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4587 MPASS(pmap_is_la57(pmap));
4589 pml5index = pmap_pml5e_index(va);
4590 pml5 = &pmap->pm_pmltop[pml5index];
4591 KASSERT((*pml5 & PG_V) == 0,
4592 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4593 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4595 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4596 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4599 pml5u = &pmap->pm_pmltopu[pml5index];
4600 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4603 } else if (ptepindex >= NUPDE + NUPDPE) {
4604 pml4index = pmap_pml4e_index(va);
4605 /* Wire up a new PDPE page */
4606 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4608 pmap_free_pt_page(pmap, m, true);
4611 KASSERT((*pml4 & PG_V) == 0,
4612 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4613 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4615 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4616 pml4index < NUPML4E) {
4618 * PTI: Make all user-space mappings in the
4619 * kernel-mode page table no-execute so that
4620 * we detect any programming errors that leave
4621 * the kernel-mode page table active on return
4624 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4627 pml4u = &pmap->pm_pmltopu[pml4index];
4628 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4631 } else if (ptepindex >= NUPDE) {
4632 /* Wire up a new PDE page */
4633 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4635 pmap_free_pt_page(pmap, m, true);
4638 KASSERT((*pdp & PG_V) == 0,
4639 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4640 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4642 /* Wire up a new PTE page */
4643 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4645 pmap_free_pt_page(pmap, m, true);
4648 if ((*pdp & PG_V) == 0) {
4649 /* Have to allocate a new pd, recurse */
4650 if (pmap_allocpte_nosleep(pmap, pmap_pdpe_pindex(va),
4651 lockp, va) == NULL) {
4652 pmap_allocpte_free_unref(pmap, va,
4653 pmap_pml4e(pmap, va));
4654 pmap_free_pt_page(pmap, m, true);
4658 /* Add reference to the pd page */
4659 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4662 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4664 /* Now we know where the page directory page is */
4665 pd = &pd[pmap_pde_index(va)];
4666 KASSERT((*pd & PG_V) == 0,
4667 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4668 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4675 * This routine is called if the desired page table page does not exist.
4677 * If page table page allocation fails, this routine may sleep before
4678 * returning NULL. It sleeps only if a lock pointer was given. Sleep
4679 * occurs right before returning to the caller. This way, we never
4680 * drop pmap lock to sleep while a page table page has ref_count == 0,
4681 * which prevents the page from being freed under us.
4684 pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4689 m = pmap_allocpte_nosleep(pmap, ptepindex, lockp, va);
4690 if (m == NULL && lockp != NULL) {
4691 RELEASE_PV_LIST_LOCK(lockp);
4693 PMAP_ASSERT_NOT_IN_DI();
4701 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4702 struct rwlock **lockp)
4704 pdp_entry_t *pdpe, PG_V;
4707 vm_pindex_t pdpindex;
4709 PG_V = pmap_valid_bit(pmap);
4712 pdpe = pmap_pdpe(pmap, va);
4713 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4714 pde = pmap_pdpe_to_pde(pdpe, va);
4715 if (va < VM_MAXUSER_ADDRESS) {
4716 /* Add a reference to the pd page. */
4717 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4721 } else if (va < VM_MAXUSER_ADDRESS) {
4722 /* Allocate a pd page. */
4723 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4724 pdpg = pmap_allocpte_alloc(pmap, NUPDE + pdpindex, lockp, va);
4731 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4732 pde = &pde[pmap_pde_index(va)];
4734 panic("pmap_alloc_pde: missing page table page for va %#lx",
4741 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4743 vm_pindex_t ptepindex;
4744 pd_entry_t *pd, PG_V;
4747 PG_V = pmap_valid_bit(pmap);
4750 * Calculate pagetable page index
4752 ptepindex = pmap_pde_pindex(va);
4755 * Get the page directory entry
4757 pd = pmap_pde(pmap, va);
4760 * This supports switching from a 2MB page to a
4763 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4764 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4766 * Invalidation of the 2MB page mapping may have caused
4767 * the deallocation of the underlying PD page.
4774 * If the page table page is mapped, we just increment the
4775 * hold count, and activate it.
4777 if (pd != NULL && (*pd & PG_V) != 0) {
4778 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4782 * Here if the pte page isn't mapped, or if it has been
4785 m = pmap_allocpte_alloc(pmap, ptepindex, lockp, va);
4786 if (m == NULL && lockp != NULL)
4792 /***************************************************
4793 * Pmap allocation/deallocation routines.
4794 ***************************************************/
4797 * Release any resources held by the given physical map.
4798 * Called when a pmap initialized by pmap_pinit is being released.
4799 * Should only be called if the map contains no valid mappings.
4802 pmap_release(pmap_t pmap)
4807 KASSERT(pmap->pm_stats.resident_count == 0,
4808 ("pmap_release: pmap %p resident count %ld != 0",
4809 pmap, pmap->pm_stats.resident_count));
4810 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4811 ("pmap_release: pmap %p has reserved page table page(s)",
4813 KASSERT(CPU_EMPTY(&pmap->pm_active),
4814 ("releasing active pmap %p", pmap));
4816 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4818 if (pmap_is_la57(pmap)) {
4819 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4820 pmap->pm_pmltop[PML5PML5I] = 0;
4822 for (i = 0; i < NKPML4E; i++) /* KVA */
4823 pmap->pm_pmltop[KPML4BASE + i] = 0;
4825 for (i = 0; i < NKASANPML4E; i++) /* KASAN shadow map */
4826 pmap->pm_pmltop[KASANPML4I + i] = 0;
4829 for (i = 0; i < NKMSANSHADPML4E; i++) /* KMSAN shadow map */
4830 pmap->pm_pmltop[KMSANSHADPML4I + i] = 0;
4831 for (i = 0; i < NKMSANORIGPML4E; i++) /* KMSAN shadow map */
4832 pmap->pm_pmltop[KMSANORIGPML4I + i] = 0;
4834 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4835 pmap->pm_pmltop[DMPML4I + i] = 0;
4836 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4837 for (i = 0; i < lm_ents; i++) /* Large Map */
4838 pmap->pm_pmltop[LMSPML4I + i] = 0;
4841 pmap_free_pt_page(NULL, m, true);
4843 if (pmap->pm_pmltopu != NULL) {
4844 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4846 pmap_free_pt_page(NULL, m, false);
4848 if (pmap->pm_type == PT_X86 &&
4849 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4850 rangeset_fini(&pmap->pm_pkru);
4854 kvm_size(SYSCTL_HANDLER_ARGS)
4856 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4858 return sysctl_handle_long(oidp, &ksize, 0, req);
4860 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4861 0, 0, kvm_size, "LU",
4865 kvm_free(SYSCTL_HANDLER_ARGS)
4867 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4869 return sysctl_handle_long(oidp, &kfree, 0, req);
4871 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4872 0, 0, kvm_free, "LU",
4873 "Amount of KVM free");
4877 pmap_kmsan_shadow_map_page_array(vm_paddr_t pdppa, vm_size_t size)
4882 vm_paddr_t dummypa, dummypd, dummypt;
4885 npdpg = howmany(size, NBPDP);
4886 npde = size / NBPDR;
4888 dummypa = vm_phys_early_alloc(-1, PAGE_SIZE);
4889 pagezero((void *)PHYS_TO_DMAP(dummypa));
4891 dummypt = vm_phys_early_alloc(-1, PAGE_SIZE);
4892 pagezero((void *)PHYS_TO_DMAP(dummypt));
4893 dummypd = vm_phys_early_alloc(-1, PAGE_SIZE * npdpg);
4894 for (i = 0; i < npdpg; i++)
4895 pagezero((void *)PHYS_TO_DMAP(dummypd + ptoa(i)));
4897 pte = (pt_entry_t *)PHYS_TO_DMAP(dummypt);
4898 for (i = 0; i < NPTEPG; i++)
4899 pte[i] = (pt_entry_t)(dummypa | X86_PG_V | X86_PG_RW |
4900 X86_PG_A | X86_PG_M | pg_nx);
4902 pde = (pd_entry_t *)PHYS_TO_DMAP(dummypd);
4903 for (i = 0; i < npde; i++)
4904 pde[i] = (pd_entry_t)(dummypt | X86_PG_V | X86_PG_RW | pg_nx);
4906 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(pdppa);
4907 for (i = 0; i < npdpg; i++)
4908 pdpe[i] = (pdp_entry_t)(dummypd + ptoa(i) | X86_PG_V |
4913 pmap_kmsan_page_array_startup(vm_offset_t start, vm_offset_t end)
4917 KASSERT(start % NBPDP == 0, ("unaligned page array start address"));
4920 * The end of the page array's KVA region is 2MB aligned, see
4923 size = round_2mpage(end) - start;
4924 pmap_kmsan_shadow_map_page_array(KMSANSHADPDPphys, size);
4925 pmap_kmsan_shadow_map_page_array(KMSANORIGPDPphys, size);
4930 * Allocate physical memory for the vm_page array and map it into KVA,
4931 * attempting to back the vm_pages with domain-local memory.
4934 pmap_page_array_startup(long pages)
4937 pd_entry_t *pde, newpdir;
4938 vm_offset_t va, start, end;
4943 vm_page_array_size = pages;
4945 start = VM_MIN_KERNEL_ADDRESS;
4946 end = start + pages * sizeof(struct vm_page);
4947 for (va = start; va < end; va += NBPDR) {
4948 pfn = first_page + (va - start) / sizeof(struct vm_page);
4949 domain = vm_phys_domain(ptoa(pfn));
4950 pdpe = pmap_pdpe(kernel_pmap, va);
4951 if ((*pdpe & X86_PG_V) == 0) {
4952 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4954 pagezero((void *)PHYS_TO_DMAP(pa));
4955 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4956 X86_PG_A | X86_PG_M);
4958 pde = pmap_pdpe_to_pde(pdpe, va);
4959 if ((*pde & X86_PG_V) != 0)
4960 panic("Unexpected pde");
4961 pa = vm_phys_early_alloc(domain, NBPDR);
4962 for (i = 0; i < NPDEPG; i++)
4963 dump_add_page(pa + i * PAGE_SIZE);
4964 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4965 X86_PG_M | PG_PS | pg_g | pg_nx);
4966 pde_store(pde, newpdir);
4968 vm_page_array = (vm_page_t)start;
4971 pmap_kmsan_page_array_startup(start, end);
4976 * grow the number of kernel page table entries, if needed
4979 pmap_growkernel(vm_offset_t addr)
4983 pd_entry_t *pde, newpdir;
4986 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4989 * Return if "addr" is within the range of kernel page table pages
4990 * that were preallocated during pmap bootstrap. Moreover, leave
4991 * "kernel_vm_end" and the kernel page table as they were.
4993 * The correctness of this action is based on the following
4994 * argument: vm_map_insert() allocates contiguous ranges of the
4995 * kernel virtual address space. It calls this function if a range
4996 * ends after "kernel_vm_end". If the kernel is mapped between
4997 * "kernel_vm_end" and "addr", then the range cannot begin at
4998 * "kernel_vm_end". In fact, its beginning address cannot be less
4999 * than the kernel. Thus, there is no immediate need to allocate
5000 * any new kernel page table pages between "kernel_vm_end" and
5003 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
5006 addr = roundup2(addr, NBPDR);
5007 if (addr - 1 >= vm_map_max(kernel_map))
5008 addr = vm_map_max(kernel_map);
5009 if (kernel_vm_end < addr)
5010 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
5011 if (kernel_vm_end < addr)
5012 kmsan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
5013 while (kernel_vm_end < addr) {
5014 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
5015 if ((*pdpe & X86_PG_V) == 0) {
5016 /* We need a new PDP entry */
5017 nkpg = pmap_alloc_pt_page(kernel_pmap,
5018 kernel_vm_end >> PDPSHIFT, VM_ALLOC_WIRED |
5019 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
5021 panic("pmap_growkernel: no memory to grow kernel");
5022 paddr = VM_PAGE_TO_PHYS(nkpg);
5023 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
5024 X86_PG_A | X86_PG_M);
5025 continue; /* try again */
5027 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
5028 if ((*pde & X86_PG_V) != 0) {
5029 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
5030 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
5031 kernel_vm_end = vm_map_max(kernel_map);
5037 nkpg = pmap_alloc_pt_page(kernel_pmap,
5038 pmap_pde_pindex(kernel_vm_end), VM_ALLOC_WIRED |
5039 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
5041 panic("pmap_growkernel: no memory to grow kernel");
5042 paddr = VM_PAGE_TO_PHYS(nkpg);
5043 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
5044 pde_store(pde, newpdir);
5046 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
5047 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
5048 kernel_vm_end = vm_map_max(kernel_map);
5054 /***************************************************
5055 * page management routines.
5056 ***************************************************/
5058 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
5059 CTASSERT(_NPCM == 3);
5060 CTASSERT(_NPCPV == 168);
5062 static __inline struct pv_chunk *
5063 pv_to_chunk(pv_entry_t pv)
5066 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
5069 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
5071 #define PC_FREE0 0xfffffffffffffffful
5072 #define PC_FREE1 0xfffffffffffffffful
5073 #define PC_FREE2 0x000000fffffffffful
5075 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
5079 static COUNTER_U64_DEFINE_EARLY(pc_chunk_count);
5080 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD,
5081 &pc_chunk_count, "Current number of pv entry cnunks");
5083 static COUNTER_U64_DEFINE_EARLY(pc_chunk_allocs);
5084 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD,
5085 &pc_chunk_allocs, "Total number of pv entry chunks allocated");
5087 static COUNTER_U64_DEFINE_EARLY(pc_chunk_frees);
5088 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD,
5089 &pc_chunk_frees, "Total number of pv entry chunks freed");
5091 static COUNTER_U64_DEFINE_EARLY(pc_chunk_tryfail);
5092 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD,
5094 "Number of failed attempts to get a pv entry chunk page");
5096 static COUNTER_U64_DEFINE_EARLY(pv_entry_frees);
5097 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD,
5098 &pv_entry_frees, "Total number of pv entries freed");
5100 static COUNTER_U64_DEFINE_EARLY(pv_entry_allocs);
5101 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD,
5102 &pv_entry_allocs, "Total number of pv entries allocated");
5104 static COUNTER_U64_DEFINE_EARLY(pv_entry_count);
5105 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD,
5106 &pv_entry_count, "Current number of pv entries");
5108 static COUNTER_U64_DEFINE_EARLY(pv_entry_spare);
5109 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD,
5110 &pv_entry_spare, "Current number of spare pv entries");
5114 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
5119 pmap_invalidate_all(pmap);
5120 if (pmap != locked_pmap)
5123 pmap_delayed_invl_finish();
5127 * We are in a serious low memory condition. Resort to
5128 * drastic measures to free some pages so we can allocate
5129 * another pv entry chunk.
5131 * Returns NULL if PV entries were reclaimed from the specified pmap.
5133 * We do not, however, unmap 2mpages because subsequent accesses will
5134 * allocate per-page pv entries until repromotion occurs, thereby
5135 * exacerbating the shortage of free pv entries.
5138 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
5140 struct pv_chunks_list *pvc;
5141 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
5142 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
5143 struct md_page *pvh;
5145 pmap_t next_pmap, pmap;
5146 pt_entry_t *pte, tpte;
5147 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5151 struct spglist free;
5153 int bit, field, freed;
5154 bool start_di, restart;
5156 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
5157 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
5160 PG_G = PG_A = PG_M = PG_RW = 0;
5162 bzero(&pc_marker_b, sizeof(pc_marker_b));
5163 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
5164 pc_marker = (struct pv_chunk *)&pc_marker_b;
5165 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
5168 * A delayed invalidation block should already be active if
5169 * pmap_advise() or pmap_remove() called this function by way
5170 * of pmap_demote_pde_locked().
5172 start_di = pmap_not_in_di();
5174 pvc = &pv_chunks[domain];
5175 mtx_lock(&pvc->pvc_lock);
5176 pvc->active_reclaims++;
5177 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
5178 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
5179 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
5180 SLIST_EMPTY(&free)) {
5181 next_pmap = pc->pc_pmap;
5182 if (next_pmap == NULL) {
5184 * The next chunk is a marker. However, it is
5185 * not our marker, so active_reclaims must be
5186 * > 1. Consequently, the next_chunk code
5187 * will not rotate the pv_chunks list.
5191 mtx_unlock(&pvc->pvc_lock);
5194 * A pv_chunk can only be removed from the pc_lru list
5195 * when both pc_chunks_mutex is owned and the
5196 * corresponding pmap is locked.
5198 if (pmap != next_pmap) {
5200 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
5203 /* Avoid deadlock and lock recursion. */
5204 if (pmap > locked_pmap) {
5205 RELEASE_PV_LIST_LOCK(lockp);
5208 pmap_delayed_invl_start();
5209 mtx_lock(&pvc->pvc_lock);
5211 } else if (pmap != locked_pmap) {
5212 if (PMAP_TRYLOCK(pmap)) {
5214 pmap_delayed_invl_start();
5215 mtx_lock(&pvc->pvc_lock);
5218 pmap = NULL; /* pmap is not locked */
5219 mtx_lock(&pvc->pvc_lock);
5220 pc = TAILQ_NEXT(pc_marker, pc_lru);
5222 pc->pc_pmap != next_pmap)
5226 } else if (start_di)
5227 pmap_delayed_invl_start();
5228 PG_G = pmap_global_bit(pmap);
5229 PG_A = pmap_accessed_bit(pmap);
5230 PG_M = pmap_modified_bit(pmap);
5231 PG_RW = pmap_rw_bit(pmap);
5237 * Destroy every non-wired, 4 KB page mapping in the chunk.
5240 for (field = 0; field < _NPCM; field++) {
5241 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
5242 inuse != 0; inuse &= ~(1UL << bit)) {
5244 pv = &pc->pc_pventry[field * 64 + bit];
5246 pde = pmap_pde(pmap, va);
5247 if ((*pde & PG_PS) != 0)
5249 pte = pmap_pde_to_pte(pde, va);
5250 if ((*pte & PG_W) != 0)
5252 tpte = pte_load_clear(pte);
5253 if ((tpte & PG_G) != 0)
5254 pmap_invalidate_page(pmap, va);
5255 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
5256 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5258 if ((tpte & PG_A) != 0)
5259 vm_page_aflag_set(m, PGA_REFERENCED);
5260 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5261 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5263 if (TAILQ_EMPTY(&m->md.pv_list) &&
5264 (m->flags & PG_FICTITIOUS) == 0) {
5265 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5266 if (TAILQ_EMPTY(&pvh->pv_list)) {
5267 vm_page_aflag_clear(m,
5271 pmap_delayed_invl_page(m);
5272 pc->pc_map[field] |= 1UL << bit;
5273 pmap_unuse_pt(pmap, va, *pde, &free);
5278 mtx_lock(&pvc->pvc_lock);
5281 /* Every freed mapping is for a 4 KB page. */
5282 pmap_resident_count_adj(pmap, -freed);
5283 PV_STAT(counter_u64_add(pv_entry_frees, freed));
5284 PV_STAT(counter_u64_add(pv_entry_spare, freed));
5285 PV_STAT(counter_u64_add(pv_entry_count, -freed));
5286 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5287 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
5288 pc->pc_map[2] == PC_FREE2) {
5289 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5290 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5291 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5292 /* Entire chunk is free; return it. */
5293 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5294 dump_drop_page(m_pc->phys_addr);
5295 mtx_lock(&pvc->pvc_lock);
5296 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5299 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5300 mtx_lock(&pvc->pvc_lock);
5301 /* One freed pv entry in locked_pmap is sufficient. */
5302 if (pmap == locked_pmap)
5305 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5306 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
5307 if (pvc->active_reclaims == 1 && pmap != NULL) {
5309 * Rotate the pv chunks list so that we do not
5310 * scan the same pv chunks that could not be
5311 * freed (because they contained a wired
5312 * and/or superpage mapping) on every
5313 * invocation of reclaim_pv_chunk().
5315 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
5316 MPASS(pc->pc_pmap != NULL);
5317 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5318 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5322 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5323 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
5324 pvc->active_reclaims--;
5325 mtx_unlock(&pvc->pvc_lock);
5326 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
5327 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
5328 m_pc = SLIST_FIRST(&free);
5329 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
5330 /* Recycle a freed page table page. */
5331 m_pc->ref_count = 1;
5333 vm_page_free_pages_toq(&free, true);
5338 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
5343 domain = PCPU_GET(domain);
5344 for (i = 0; i < vm_ndomains; i++) {
5345 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
5348 domain = (domain + 1) % vm_ndomains;
5355 * free the pv_entry back to the free list
5358 free_pv_entry(pmap_t pmap, pv_entry_t pv)
5360 struct pv_chunk *pc;
5361 int idx, field, bit;
5363 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5364 PV_STAT(counter_u64_add(pv_entry_frees, 1));
5365 PV_STAT(counter_u64_add(pv_entry_spare, 1));
5366 PV_STAT(counter_u64_add(pv_entry_count, -1));
5367 pc = pv_to_chunk(pv);
5368 idx = pv - &pc->pc_pventry[0];
5371 pc->pc_map[field] |= 1ul << bit;
5372 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5373 pc->pc_map[2] != PC_FREE2) {
5374 /* 98% of the time, pc is already at the head of the list. */
5375 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5376 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5377 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5381 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5386 free_pv_chunk_dequeued(struct pv_chunk *pc)
5390 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5391 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5392 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5393 counter_u64_add(pv_page_count, -1);
5394 /* entire chunk is free, return it */
5395 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5396 dump_drop_page(m->phys_addr);
5397 vm_page_unwire_noq(m);
5402 free_pv_chunk(struct pv_chunk *pc)
5404 struct pv_chunks_list *pvc;
5406 pvc = &pv_chunks[pc_to_domain(pc)];
5407 mtx_lock(&pvc->pvc_lock);
5408 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5409 mtx_unlock(&pvc->pvc_lock);
5410 free_pv_chunk_dequeued(pc);
5414 free_pv_chunk_batch(struct pv_chunklist *batch)
5416 struct pv_chunks_list *pvc;
5417 struct pv_chunk *pc, *npc;
5420 for (i = 0; i < vm_ndomains; i++) {
5421 if (TAILQ_EMPTY(&batch[i]))
5423 pvc = &pv_chunks[i];
5424 mtx_lock(&pvc->pvc_lock);
5425 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5426 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5428 mtx_unlock(&pvc->pvc_lock);
5431 for (i = 0; i < vm_ndomains; i++) {
5432 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5433 free_pv_chunk_dequeued(pc);
5439 * Returns a new PV entry, allocating a new PV chunk from the system when
5440 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5441 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5444 * The given PV list lock may be released.
5447 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5449 struct pv_chunks_list *pvc;
5452 struct pv_chunk *pc;
5455 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5456 PV_STAT(counter_u64_add(pv_entry_allocs, 1));
5458 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5460 for (field = 0; field < _NPCM; field++) {
5461 if (pc->pc_map[field]) {
5462 bit = bsfq(pc->pc_map[field]);
5466 if (field < _NPCM) {
5467 pv = &pc->pc_pventry[field * 64 + bit];
5468 pc->pc_map[field] &= ~(1ul << bit);
5469 /* If this was the last item, move it to tail */
5470 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5471 pc->pc_map[2] == 0) {
5472 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5473 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5476 PV_STAT(counter_u64_add(pv_entry_count, 1));
5477 PV_STAT(counter_u64_add(pv_entry_spare, -1));
5481 /* No free items, allocate another chunk */
5482 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5485 if (lockp == NULL) {
5486 PV_STAT(counter_u64_add(pc_chunk_tryfail, 1));
5489 m = reclaim_pv_chunk(pmap, lockp);
5493 counter_u64_add(pv_page_count, 1);
5494 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5495 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5496 dump_add_page(m->phys_addr);
5497 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5499 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5500 pc->pc_map[1] = PC_FREE1;
5501 pc->pc_map[2] = PC_FREE2;
5502 pvc = &pv_chunks[vm_page_domain(m)];
5503 mtx_lock(&pvc->pvc_lock);
5504 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5505 mtx_unlock(&pvc->pvc_lock);
5506 pv = &pc->pc_pventry[0];
5507 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5508 PV_STAT(counter_u64_add(pv_entry_count, 1));
5509 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV - 1));
5514 * Returns the number of one bits within the given PV chunk map.
5516 * The erratas for Intel processors state that "POPCNT Instruction May
5517 * Take Longer to Execute Than Expected". It is believed that the
5518 * issue is the spurious dependency on the destination register.
5519 * Provide a hint to the register rename logic that the destination
5520 * value is overwritten, by clearing it, as suggested in the
5521 * optimization manual. It should be cheap for unaffected processors
5524 * Reference numbers for erratas are
5525 * 4th Gen Core: HSD146
5526 * 5th Gen Core: BDM85
5527 * 6th Gen Core: SKL029
5530 popcnt_pc_map_pq(uint64_t *map)
5534 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5535 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5536 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5537 : "=&r" (result), "=&r" (tmp)
5538 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5543 * Ensure that the number of spare PV entries in the specified pmap meets or
5544 * exceeds the given count, "needed".
5546 * The given PV list lock may be released.
5549 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5551 struct pv_chunks_list *pvc;
5552 struct pch new_tail[PMAP_MEMDOM];
5553 struct pv_chunk *pc;
5558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5559 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5562 * Newly allocated PV chunks must be stored in a private list until
5563 * the required number of PV chunks have been allocated. Otherwise,
5564 * reclaim_pv_chunk() could recycle one of these chunks. In
5565 * contrast, these chunks must be added to the pmap upon allocation.
5567 for (i = 0; i < PMAP_MEMDOM; i++)
5568 TAILQ_INIT(&new_tail[i]);
5571 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5573 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5574 bit_count((bitstr_t *)pc->pc_map, 0,
5575 sizeof(pc->pc_map) * NBBY, &free);
5578 free = popcnt_pc_map_pq(pc->pc_map);
5582 if (avail >= needed)
5585 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5586 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5589 m = reclaim_pv_chunk(pmap, lockp);
5594 counter_u64_add(pv_page_count, 1);
5595 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5596 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5597 dump_add_page(m->phys_addr);
5598 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5600 pc->pc_map[0] = PC_FREE0;
5601 pc->pc_map[1] = PC_FREE1;
5602 pc->pc_map[2] = PC_FREE2;
5603 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5604 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
5605 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV));
5608 * The reclaim might have freed a chunk from the current pmap.
5609 * If that chunk contained available entries, we need to
5610 * re-count the number of available entries.
5615 for (i = 0; i < vm_ndomains; i++) {
5616 if (TAILQ_EMPTY(&new_tail[i]))
5618 pvc = &pv_chunks[i];
5619 mtx_lock(&pvc->pvc_lock);
5620 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5621 mtx_unlock(&pvc->pvc_lock);
5626 * First find and then remove the pv entry for the specified pmap and virtual
5627 * address from the specified pv list. Returns the pv entry if found and NULL
5628 * otherwise. This operation can be performed on pv lists for either 4KB or
5629 * 2MB page mappings.
5631 static __inline pv_entry_t
5632 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5636 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5637 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5638 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5647 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5648 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5649 * entries for each of the 4KB page mappings.
5652 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5653 struct rwlock **lockp)
5655 struct md_page *pvh;
5656 struct pv_chunk *pc;
5658 vm_offset_t va_last;
5662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5663 KASSERT((pa & PDRMASK) == 0,
5664 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5665 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5668 * Transfer the 2mpage's pv entry for this mapping to the first
5669 * page's pv list. Once this transfer begins, the pv list lock
5670 * must not be released until the last pv entry is reinstantiated.
5672 pvh = pa_to_pvh(pa);
5673 va = trunc_2mpage(va);
5674 pv = pmap_pvh_remove(pvh, pmap, va);
5675 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5676 m = PHYS_TO_VM_PAGE(pa);
5677 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5679 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5680 PV_STAT(counter_u64_add(pv_entry_allocs, NPTEPG - 1));
5681 va_last = va + NBPDR - PAGE_SIZE;
5683 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5684 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5685 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5686 for (field = 0; field < _NPCM; field++) {
5687 while (pc->pc_map[field]) {
5688 bit = bsfq(pc->pc_map[field]);
5689 pc->pc_map[field] &= ~(1ul << bit);
5690 pv = &pc->pc_pventry[field * 64 + bit];
5694 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5695 ("pmap_pv_demote_pde: page %p is not managed", m));
5696 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5702 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5703 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5706 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5707 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5708 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5710 PV_STAT(counter_u64_add(pv_entry_count, NPTEPG - 1));
5711 PV_STAT(counter_u64_add(pv_entry_spare, -(NPTEPG - 1)));
5714 #if VM_NRESERVLEVEL > 0
5716 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5717 * replace the many pv entries for the 4KB page mappings by a single pv entry
5718 * for the 2MB page mapping.
5721 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5722 struct rwlock **lockp)
5724 struct md_page *pvh;
5726 vm_offset_t va_last;
5729 KASSERT((pa & PDRMASK) == 0,
5730 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5731 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5734 * Transfer the first page's pv entry for this mapping to the 2mpage's
5735 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5736 * a transfer avoids the possibility that get_pv_entry() calls
5737 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5738 * mappings that is being promoted.
5740 m = PHYS_TO_VM_PAGE(pa);
5741 va = trunc_2mpage(va);
5742 pv = pmap_pvh_remove(&m->md, pmap, va);
5743 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5744 pvh = pa_to_pvh(pa);
5745 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5747 /* Free the remaining NPTEPG - 1 pv entries. */
5748 va_last = va + NBPDR - PAGE_SIZE;
5752 pmap_pvh_free(&m->md, pmap, va);
5753 } while (va < va_last);
5755 #endif /* VM_NRESERVLEVEL > 0 */
5758 * First find and then destroy the pv entry for the specified pmap and virtual
5759 * address. This operation can be performed on pv lists for either 4KB or 2MB
5763 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5767 pv = pmap_pvh_remove(pvh, pmap, va);
5768 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5769 free_pv_entry(pmap, pv);
5773 * Conditionally create the PV entry for a 4KB page mapping if the required
5774 * memory can be allocated without resorting to reclamation.
5777 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5778 struct rwlock **lockp)
5782 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5783 /* Pass NULL instead of the lock pointer to disable reclamation. */
5784 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5786 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5787 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5795 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5796 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5797 * false if the PV entry cannot be allocated without resorting to reclamation.
5800 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5801 struct rwlock **lockp)
5803 struct md_page *pvh;
5807 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5808 /* Pass NULL instead of the lock pointer to disable reclamation. */
5809 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5810 NULL : lockp)) == NULL)
5813 pa = pde & PG_PS_FRAME;
5814 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5815 pvh = pa_to_pvh(pa);
5816 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5822 * Fills a page table page with mappings to consecutive physical pages.
5825 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5829 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5831 newpte += PAGE_SIZE;
5836 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5837 * mapping is invalidated.
5840 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5842 struct rwlock *lock;
5846 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5853 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5857 pt_entry_t *xpte, *ypte;
5859 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5860 xpte++, newpte += PAGE_SIZE) {
5861 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5862 printf("pmap_demote_pde: xpte %zd and newpte map "
5863 "different pages: found %#lx, expected %#lx\n",
5864 xpte - firstpte, *xpte, newpte);
5865 printf("page table dump\n");
5866 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5867 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5872 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5873 ("pmap_demote_pde: firstpte and newpte map different physical"
5880 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5881 pd_entry_t oldpde, struct rwlock **lockp)
5883 struct spglist free;
5887 sva = trunc_2mpage(va);
5888 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5889 if ((oldpde & pmap_global_bit(pmap)) == 0)
5890 pmap_invalidate_pde_page(pmap, sva, oldpde);
5891 vm_page_free_pages_toq(&free, true);
5892 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5897 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5898 struct rwlock **lockp)
5900 pd_entry_t newpde, oldpde;
5901 pt_entry_t *firstpte, newpte;
5902 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5908 PG_A = pmap_accessed_bit(pmap);
5909 PG_G = pmap_global_bit(pmap);
5910 PG_M = pmap_modified_bit(pmap);
5911 PG_RW = pmap_rw_bit(pmap);
5912 PG_V = pmap_valid_bit(pmap);
5913 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5914 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5917 in_kernel = va >= VM_MAXUSER_ADDRESS;
5919 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5920 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5923 * Invalidate the 2MB page mapping and return "failure" if the
5924 * mapping was never accessed.
5926 if ((oldpde & PG_A) == 0) {
5927 KASSERT((oldpde & PG_W) == 0,
5928 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5929 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5933 mpte = pmap_remove_pt_page(pmap, va);
5935 KASSERT((oldpde & PG_W) == 0,
5936 ("pmap_demote_pde: page table page for a wired mapping"
5940 * If the page table page is missing and the mapping
5941 * is for a kernel address, the mapping must belong to
5942 * the direct map. Page table pages are preallocated
5943 * for every other part of the kernel address space,
5944 * so the direct map region is the only part of the
5945 * kernel address space that must be handled here.
5947 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5948 va < DMAP_MAX_ADDRESS),
5949 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5952 * If the 2MB page mapping belongs to the direct map
5953 * region of the kernel's address space, then the page
5954 * allocation request specifies the highest possible
5955 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5956 * priority is normal.
5958 mpte = pmap_alloc_pt_page(pmap, pmap_pde_pindex(va),
5959 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5963 * If the allocation of the new page table page fails,
5964 * invalidate the 2MB page mapping and return "failure".
5967 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5972 mpte->ref_count = NPTEPG;
5974 mptepa = VM_PAGE_TO_PHYS(mpte);
5975 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5976 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5977 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5978 ("pmap_demote_pde: oldpde is missing PG_M"));
5979 newpte = oldpde & ~PG_PS;
5980 newpte = pmap_swap_pat(pmap, newpte);
5983 * If the page table page is not leftover from an earlier promotion,
5986 if (mpte->valid == 0)
5987 pmap_fill_ptp(firstpte, newpte);
5989 pmap_demote_pde_check(firstpte, newpte);
5992 * If the mapping has changed attributes, update the page table
5995 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5996 pmap_fill_ptp(firstpte, newpte);
5999 * The spare PV entries must be reserved prior to demoting the
6000 * mapping, that is, prior to changing the PDE. Otherwise, the state
6001 * of the PDE and the PV lists will be inconsistent, which can result
6002 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6003 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
6004 * PV entry for the 2MB page mapping that is being demoted.
6006 if ((oldpde & PG_MANAGED) != 0)
6007 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
6010 * Demote the mapping. This pmap is locked. The old PDE has
6011 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
6012 * set. Thus, there is no danger of a race with another
6013 * processor changing the setting of PG_A and/or PG_M between
6014 * the read above and the store below.
6016 if (workaround_erratum383)
6017 pmap_update_pde(pmap, va, pde, newpde);
6019 pde_store(pde, newpde);
6022 * Invalidate a stale recursive mapping of the page table page.
6025 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
6028 * Demote the PV entry.
6030 if ((oldpde & PG_MANAGED) != 0)
6031 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
6033 counter_u64_add(pmap_pde_demotions, 1);
6034 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
6040 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
6043 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
6049 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
6050 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6051 mpte = pmap_remove_pt_page(pmap, va);
6053 panic("pmap_remove_kernel_pde: Missing pt page.");
6055 mptepa = VM_PAGE_TO_PHYS(mpte);
6056 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
6059 * If this page table page was unmapped by a promotion, then it
6060 * contains valid mappings. Zero it to invalidate those mappings.
6062 if (mpte->valid != 0)
6063 pagezero((void *)PHYS_TO_DMAP(mptepa));
6066 * Demote the mapping.
6068 if (workaround_erratum383)
6069 pmap_update_pde(pmap, va, pde, newpde);
6071 pde_store(pde, newpde);
6074 * Invalidate a stale recursive mapping of the page table page.
6076 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
6080 * pmap_remove_pde: do the things to unmap a superpage in a process
6083 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
6084 struct spglist *free, struct rwlock **lockp)
6086 struct md_page *pvh;
6088 vm_offset_t eva, va;
6090 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
6092 PG_G = pmap_global_bit(pmap);
6093 PG_A = pmap_accessed_bit(pmap);
6094 PG_M = pmap_modified_bit(pmap);
6095 PG_RW = pmap_rw_bit(pmap);
6097 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6098 KASSERT((sva & PDRMASK) == 0,
6099 ("pmap_remove_pde: sva is not 2mpage aligned"));
6100 oldpde = pte_load_clear(pdq);
6102 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
6103 if ((oldpde & PG_G) != 0)
6104 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6105 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
6106 if (oldpde & PG_MANAGED) {
6107 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
6108 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
6109 pmap_pvh_free(pvh, pmap, sva);
6111 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6112 va < eva; va += PAGE_SIZE, m++) {
6113 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
6116 vm_page_aflag_set(m, PGA_REFERENCED);
6117 if (TAILQ_EMPTY(&m->md.pv_list) &&
6118 TAILQ_EMPTY(&pvh->pv_list))
6119 vm_page_aflag_clear(m, PGA_WRITEABLE);
6120 pmap_delayed_invl_page(m);
6123 if (pmap == kernel_pmap) {
6124 pmap_remove_kernel_pde(pmap, pdq, sva);
6126 mpte = pmap_remove_pt_page(pmap, sva);
6128 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6129 ("pmap_remove_pde: pte page not promoted"));
6130 pmap_resident_count_adj(pmap, -1);
6131 KASSERT(mpte->ref_count == NPTEPG,
6132 ("pmap_remove_pde: pte page ref count error"));
6133 mpte->ref_count = 0;
6134 pmap_add_delayed_free_list(mpte, free, FALSE);
6137 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
6141 * pmap_remove_pte: do the things to unmap a page in a process
6144 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
6145 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
6147 struct md_page *pvh;
6148 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
6151 PG_A = pmap_accessed_bit(pmap);
6152 PG_M = pmap_modified_bit(pmap);
6153 PG_RW = pmap_rw_bit(pmap);
6155 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6156 oldpte = pte_load_clear(ptq);
6158 pmap->pm_stats.wired_count -= 1;
6159 pmap_resident_count_adj(pmap, -1);
6160 if (oldpte & PG_MANAGED) {
6161 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
6162 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6165 vm_page_aflag_set(m, PGA_REFERENCED);
6166 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
6167 pmap_pvh_free(&m->md, pmap, va);
6168 if (TAILQ_EMPTY(&m->md.pv_list) &&
6169 (m->flags & PG_FICTITIOUS) == 0) {
6170 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6171 if (TAILQ_EMPTY(&pvh->pv_list))
6172 vm_page_aflag_clear(m, PGA_WRITEABLE);
6174 pmap_delayed_invl_page(m);
6176 return (pmap_unuse_pt(pmap, va, ptepde, free));
6180 * Remove a single page from a process address space
6183 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
6184 struct spglist *free)
6186 struct rwlock *lock;
6187 pt_entry_t *pte, PG_V;
6189 PG_V = pmap_valid_bit(pmap);
6190 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6191 if ((*pde & PG_V) == 0)
6193 pte = pmap_pde_to_pte(pde, va);
6194 if ((*pte & PG_V) == 0)
6197 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
6200 pmap_invalidate_page(pmap, va);
6204 * Removes the specified range of addresses from the page table page.
6207 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
6208 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
6210 pt_entry_t PG_G, *pte;
6214 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6215 PG_G = pmap_global_bit(pmap);
6218 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
6222 pmap_invalidate_range(pmap, va, sva);
6227 if ((*pte & PG_G) == 0)
6231 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
6237 pmap_invalidate_range(pmap, va, sva);
6242 * Remove the given range of addresses from the specified map.
6244 * It is assumed that the start and end are properly
6245 * rounded to the page size.
6248 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6250 struct rwlock *lock;
6252 vm_offset_t va_next;
6253 pml5_entry_t *pml5e;
6254 pml4_entry_t *pml4e;
6256 pd_entry_t ptpaddr, *pde;
6257 pt_entry_t PG_G, PG_V;
6258 struct spglist free;
6261 PG_G = pmap_global_bit(pmap);
6262 PG_V = pmap_valid_bit(pmap);
6265 * Perform an unsynchronized read. This is, however, safe.
6267 if (pmap->pm_stats.resident_count == 0)
6273 pmap_delayed_invl_start();
6275 pmap_pkru_on_remove(pmap, sva, eva);
6278 * special handling of removing one page. a very
6279 * common operation and easy to short circuit some
6282 if (sva + PAGE_SIZE == eva) {
6283 pde = pmap_pde(pmap, sva);
6284 if (pde && (*pde & PG_PS) == 0) {
6285 pmap_remove_page(pmap, sva, pde, &free);
6291 for (; sva < eva; sva = va_next) {
6292 if (pmap->pm_stats.resident_count == 0)
6295 if (pmap_is_la57(pmap)) {
6296 pml5e = pmap_pml5e(pmap, sva);
6297 if ((*pml5e & PG_V) == 0) {
6298 va_next = (sva + NBPML5) & ~PML5MASK;
6303 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
6305 pml4e = pmap_pml4e(pmap, sva);
6307 if ((*pml4e & PG_V) == 0) {
6308 va_next = (sva + NBPML4) & ~PML4MASK;
6314 va_next = (sva + NBPDP) & ~PDPMASK;
6317 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6318 if ((*pdpe & PG_V) == 0)
6320 if ((*pdpe & PG_PS) != 0) {
6321 KASSERT(va_next <= eva,
6322 ("partial update of non-transparent 1G mapping "
6323 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6324 *pdpe, sva, eva, va_next));
6325 MPASS(pmap != kernel_pmap); /* XXXKIB */
6326 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
6329 pmap_resident_count_adj(pmap, -NBPDP / PAGE_SIZE);
6330 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
6331 pmap_unwire_ptp(pmap, sva, mt, &free);
6336 * Calculate index for next page table.
6338 va_next = (sva + NBPDR) & ~PDRMASK;
6342 pde = pmap_pdpe_to_pde(pdpe, sva);
6346 * Weed out invalid mappings.
6352 * Check for large page.
6354 if ((ptpaddr & PG_PS) != 0) {
6356 * Are we removing the entire large page? If not,
6357 * demote the mapping and fall through.
6359 if (sva + NBPDR == va_next && eva >= va_next) {
6361 * The TLB entry for a PG_G mapping is
6362 * invalidated by pmap_remove_pde().
6364 if ((ptpaddr & PG_G) == 0)
6366 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6368 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6370 /* The large page mapping was destroyed. */
6377 * Limit our scan to either the end of the va represented
6378 * by the current page table page, or to the end of the
6379 * range being removed.
6384 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6391 pmap_invalidate_all(pmap);
6393 pmap_delayed_invl_finish();
6394 vm_page_free_pages_toq(&free, true);
6398 * Routine: pmap_remove_all
6400 * Removes this physical page from
6401 * all physical maps in which it resides.
6402 * Reflects back modify bits to the pager.
6405 * Original versions of this routine were very
6406 * inefficient because they iteratively called
6407 * pmap_remove (slow...)
6411 pmap_remove_all(vm_page_t m)
6413 struct md_page *pvh;
6416 struct rwlock *lock;
6417 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6420 struct spglist free;
6421 int pvh_gen, md_gen;
6423 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6424 ("pmap_remove_all: page %p is not managed", m));
6426 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6427 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6428 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6431 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6433 if (!PMAP_TRYLOCK(pmap)) {
6434 pvh_gen = pvh->pv_gen;
6438 if (pvh_gen != pvh->pv_gen) {
6444 pde = pmap_pde(pmap, va);
6445 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6448 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6450 if (!PMAP_TRYLOCK(pmap)) {
6451 pvh_gen = pvh->pv_gen;
6452 md_gen = m->md.pv_gen;
6456 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6461 PG_A = pmap_accessed_bit(pmap);
6462 PG_M = pmap_modified_bit(pmap);
6463 PG_RW = pmap_rw_bit(pmap);
6464 pmap_resident_count_adj(pmap, -1);
6465 pde = pmap_pde(pmap, pv->pv_va);
6466 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6467 " a 2mpage in page %p's pv list", m));
6468 pte = pmap_pde_to_pte(pde, pv->pv_va);
6469 tpte = pte_load_clear(pte);
6471 pmap->pm_stats.wired_count--;
6473 vm_page_aflag_set(m, PGA_REFERENCED);
6476 * Update the vm_page_t clean and reference bits.
6478 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6480 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6481 pmap_invalidate_page(pmap, pv->pv_va);
6482 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6484 free_pv_entry(pmap, pv);
6487 vm_page_aflag_clear(m, PGA_WRITEABLE);
6489 pmap_delayed_invl_wait(m);
6490 vm_page_free_pages_toq(&free, true);
6494 * pmap_protect_pde: do the things to protect a 2mpage in a process
6497 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6499 pd_entry_t newpde, oldpde;
6501 boolean_t anychanged;
6502 pt_entry_t PG_G, PG_M, PG_RW;
6504 PG_G = pmap_global_bit(pmap);
6505 PG_M = pmap_modified_bit(pmap);
6506 PG_RW = pmap_rw_bit(pmap);
6508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6509 KASSERT((sva & PDRMASK) == 0,
6510 ("pmap_protect_pde: sva is not 2mpage aligned"));
6513 oldpde = newpde = *pde;
6514 if ((prot & VM_PROT_WRITE) == 0) {
6515 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6516 (PG_MANAGED | PG_M | PG_RW)) {
6517 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6518 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6521 newpde &= ~(PG_RW | PG_M);
6523 if ((prot & VM_PROT_EXECUTE) == 0)
6525 if (newpde != oldpde) {
6527 * As an optimization to future operations on this PDE, clear
6528 * PG_PROMOTED. The impending invalidation will remove any
6529 * lingering 4KB page mappings from the TLB.
6531 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6533 if ((oldpde & PG_G) != 0)
6534 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6538 return (anychanged);
6542 * Set the physical protection on the
6543 * specified range of this map as requested.
6546 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6549 vm_offset_t va_next;
6550 pml4_entry_t *pml4e;
6552 pd_entry_t ptpaddr, *pde;
6553 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6554 pt_entry_t obits, pbits;
6555 boolean_t anychanged;
6557 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6558 if (prot == VM_PROT_NONE) {
6559 pmap_remove(pmap, sva, eva);
6563 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6564 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6567 PG_G = pmap_global_bit(pmap);
6568 PG_M = pmap_modified_bit(pmap);
6569 PG_V = pmap_valid_bit(pmap);
6570 PG_RW = pmap_rw_bit(pmap);
6574 * Although this function delays and batches the invalidation
6575 * of stale TLB entries, it does not need to call
6576 * pmap_delayed_invl_start() and
6577 * pmap_delayed_invl_finish(), because it does not
6578 * ordinarily destroy mappings. Stale TLB entries from
6579 * protection-only changes need only be invalidated before the
6580 * pmap lock is released, because protection-only changes do
6581 * not destroy PV entries. Even operations that iterate over
6582 * a physical page's PV list of mappings, like
6583 * pmap_remove_write(), acquire the pmap lock for each
6584 * mapping. Consequently, for protection-only changes, the
6585 * pmap lock suffices to synchronize both page table and TLB
6588 * This function only destroys a mapping if pmap_demote_pde()
6589 * fails. In that case, stale TLB entries are immediately
6594 for (; sva < eva; sva = va_next) {
6595 pml4e = pmap_pml4e(pmap, sva);
6596 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6597 va_next = (sva + NBPML4) & ~PML4MASK;
6603 va_next = (sva + NBPDP) & ~PDPMASK;
6606 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6607 if ((*pdpe & PG_V) == 0)
6609 if ((*pdpe & PG_PS) != 0) {
6610 KASSERT(va_next <= eva,
6611 ("partial update of non-transparent 1G mapping "
6612 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6613 *pdpe, sva, eva, va_next));
6615 obits = pbits = *pdpe;
6616 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6617 MPASS(pmap != kernel_pmap); /* XXXKIB */
6618 if ((prot & VM_PROT_WRITE) == 0)
6619 pbits &= ~(PG_RW | PG_M);
6620 if ((prot & VM_PROT_EXECUTE) == 0)
6623 if (pbits != obits) {
6624 if (!atomic_cmpset_long(pdpe, obits, pbits))
6625 /* PG_PS cannot be cleared under us, */
6632 va_next = (sva + NBPDR) & ~PDRMASK;
6636 pde = pmap_pdpe_to_pde(pdpe, sva);
6640 * Weed out invalid mappings.
6646 * Check for large page.
6648 if ((ptpaddr & PG_PS) != 0) {
6650 * Are we protecting the entire large page? If not,
6651 * demote the mapping and fall through.
6653 if (sva + NBPDR == va_next && eva >= va_next) {
6655 * The TLB entry for a PG_G mapping is
6656 * invalidated by pmap_protect_pde().
6658 if (pmap_protect_pde(pmap, pde, sva, prot))
6661 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6663 * The large page mapping was destroyed.
6672 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6675 obits = pbits = *pte;
6676 if ((pbits & PG_V) == 0)
6679 if ((prot & VM_PROT_WRITE) == 0) {
6680 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6681 (PG_MANAGED | PG_M | PG_RW)) {
6682 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6685 pbits &= ~(PG_RW | PG_M);
6687 if ((prot & VM_PROT_EXECUTE) == 0)
6690 if (pbits != obits) {
6691 if (!atomic_cmpset_long(pte, obits, pbits))
6694 pmap_invalidate_page(pmap, sva);
6701 pmap_invalidate_all(pmap);
6705 #if VM_NRESERVLEVEL > 0
6707 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6710 if (pmap->pm_type != PT_EPT)
6712 return ((pde & EPT_PG_EXECUTE) != 0);
6716 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6717 * single page table page (PTP) to a single 2MB page mapping. For promotion
6718 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6719 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6720 * identical characteristics.
6723 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6724 struct rwlock **lockp)
6727 pt_entry_t *firstpte, oldpte, pa, *pte;
6728 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6732 PG_A = pmap_accessed_bit(pmap);
6733 PG_G = pmap_global_bit(pmap);
6734 PG_M = pmap_modified_bit(pmap);
6735 PG_V = pmap_valid_bit(pmap);
6736 PG_RW = pmap_rw_bit(pmap);
6737 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6738 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6740 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6743 * Examine the first PTE in the specified PTP. Abort if this PTE is
6744 * either invalid, unused, or does not map the first 4KB physical page
6745 * within a 2MB page.
6747 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6749 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6750 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6752 counter_u64_add(pmap_pde_p_failures, 1);
6753 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6754 " in pmap %p", va, pmap);
6758 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6760 * When PG_M is already clear, PG_RW can be cleared without
6761 * a TLB invalidation.
6763 if (!atomic_fcmpset_long(firstpte, &newpde, newpde & ~PG_RW))
6769 * Examine each of the other PTEs in the specified PTP. Abort if this
6770 * PTE maps an unexpected 4KB physical page or does not have identical
6771 * characteristics to the first PTE.
6773 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6774 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6776 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6777 counter_u64_add(pmap_pde_p_failures, 1);
6778 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6779 " in pmap %p", va, pmap);
6783 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6785 * When PG_M is already clear, PG_RW can be cleared
6786 * without a TLB invalidation.
6788 if (!atomic_fcmpset_long(pte, &oldpte, oldpte & ~PG_RW))
6791 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6792 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6793 (va & ~PDRMASK), pmap);
6795 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6796 counter_u64_add(pmap_pde_p_failures, 1);
6797 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6798 " in pmap %p", va, pmap);
6805 * Save the page table page in its current state until the PDE
6806 * mapping the superpage is demoted by pmap_demote_pde() or
6807 * destroyed by pmap_remove_pde().
6809 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6810 KASSERT(mpte >= vm_page_array &&
6811 mpte < &vm_page_array[vm_page_array_size],
6812 ("pmap_promote_pde: page table page is out of range"));
6813 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6814 ("pmap_promote_pde: page table page's pindex is wrong "
6815 "mpte %p pidx %#lx va %#lx va pde pidx %#lx",
6816 mpte, mpte->pindex, va, pmap_pde_pindex(va)));
6817 if (pmap_insert_pt_page(pmap, mpte, true)) {
6818 counter_u64_add(pmap_pde_p_failures, 1);
6820 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6826 * Promote the pv entries.
6828 if ((newpde & PG_MANAGED) != 0)
6829 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6832 * Propagate the PAT index to its proper position.
6834 newpde = pmap_swap_pat(pmap, newpde);
6837 * Map the superpage.
6839 if (workaround_erratum383)
6840 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6842 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6844 counter_u64_add(pmap_pde_promotions, 1);
6845 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6846 " in pmap %p", va, pmap);
6848 #endif /* VM_NRESERVLEVEL > 0 */
6851 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6855 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6857 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6858 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6859 ("psind %d unexpected", psind));
6860 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6861 ("unaligned phys address %#lx newpte %#lx psind %d",
6862 newpte & PG_FRAME, newpte, psind));
6863 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6864 ("unaligned va %#lx psind %d", va, psind));
6865 KASSERT(va < VM_MAXUSER_ADDRESS,
6866 ("kernel mode non-transparent superpage")); /* XXXKIB */
6867 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6868 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6870 PG_V = pmap_valid_bit(pmap);
6873 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6874 return (KERN_PROTECTION_FAILURE);
6876 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6877 pten |= pmap_pkru_get(pmap, va);
6879 if (psind == 2) { /* 1G */
6880 pml4e = pmap_pml4e(pmap, va);
6881 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6882 mp = pmap_allocpte_alloc(pmap, pmap_pml4e_pindex(va),
6886 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6887 pdpe = &pdpe[pmap_pdpe_index(va)];
6889 MPASS(origpte == 0);
6891 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6892 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6894 if ((origpte & PG_V) == 0) {
6895 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6900 } else /* (psind == 1) */ { /* 2M */
6901 pde = pmap_pde(pmap, va);
6903 mp = pmap_allocpte_alloc(pmap, pmap_pdpe_pindex(va),
6907 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6908 pde = &pde[pmap_pde_index(va)];
6910 MPASS(origpte == 0);
6913 if ((origpte & PG_V) == 0) {
6914 pdpe = pmap_pdpe(pmap, va);
6915 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6916 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6922 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6923 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6924 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6925 va, psind == 2 ? "1G" : "2M", origpte, pten));
6926 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6927 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6928 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6929 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6930 if ((origpte & PG_V) == 0)
6931 pmap_resident_count_adj(pmap, pagesizes[psind] / PAGE_SIZE);
6933 return (KERN_SUCCESS);
6936 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6937 return (KERN_RESOURCE_SHORTAGE);
6945 * Insert the given physical page (p) at
6946 * the specified virtual address (v) in the
6947 * target physical map with the protection requested.
6949 * If specified, the page will be wired down, meaning
6950 * that the related pte can not be reclaimed.
6952 * NB: This is the only routine which MAY NOT lazy-evaluate
6953 * or lose information. That is, this routine must actually
6954 * insert this page into the given map NOW.
6956 * When destroying both a page table and PV entry, this function
6957 * performs the TLB invalidation before releasing the PV list
6958 * lock, so we do not need pmap_delayed_invl_page() calls here.
6961 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6962 u_int flags, int8_t psind)
6964 struct rwlock *lock;
6966 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6967 pt_entry_t newpte, origpte;
6974 PG_A = pmap_accessed_bit(pmap);
6975 PG_G = pmap_global_bit(pmap);
6976 PG_M = pmap_modified_bit(pmap);
6977 PG_V = pmap_valid_bit(pmap);
6978 PG_RW = pmap_rw_bit(pmap);
6980 va = trunc_page(va);
6981 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6982 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6983 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6985 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va),
6986 ("pmap_enter: managed mapping within the clean submap"));
6987 if ((m->oflags & VPO_UNMANAGED) == 0)
6988 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6989 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6990 ("pmap_enter: flags %u has reserved bits set", flags));
6991 pa = VM_PAGE_TO_PHYS(m);
6992 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6993 if ((flags & VM_PROT_WRITE) != 0)
6995 if ((prot & VM_PROT_WRITE) != 0)
6997 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6998 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6999 if ((prot & VM_PROT_EXECUTE) == 0)
7001 if ((flags & PMAP_ENTER_WIRED) != 0)
7003 if (va < VM_MAXUSER_ADDRESS)
7005 if (pmap == kernel_pmap)
7007 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
7010 * Set modified bit gratuitously for writeable mappings if
7011 * the page is unmanaged. We do not want to take a fault
7012 * to do the dirty bit accounting for these mappings.
7014 if ((m->oflags & VPO_UNMANAGED) != 0) {
7015 if ((newpte & PG_RW) != 0)
7018 newpte |= PG_MANAGED;
7022 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
7023 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
7024 ("managed largepage va %#lx flags %#x", va, flags));
7025 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
7030 /* Assert the required virtual and physical alignment. */
7031 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
7032 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
7033 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
7039 * In the case that a page table page is not
7040 * resident, we are creating it here.
7043 pde = pmap_pde(pmap, va);
7044 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
7045 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
7046 pte = pmap_pde_to_pte(pde, va);
7047 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
7048 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7051 } else if (va < VM_MAXUSER_ADDRESS) {
7053 * Here if the pte page isn't mapped, or if it has been
7056 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
7057 mpte = pmap_allocpte_alloc(pmap, pmap_pde_pindex(va),
7058 nosleep ? NULL : &lock, va);
7059 if (mpte == NULL && nosleep) {
7060 rv = KERN_RESOURCE_SHORTAGE;
7065 panic("pmap_enter: invalid page directory va=%#lx", va);
7069 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
7070 newpte |= pmap_pkru_get(pmap, va);
7073 * Is the specified virtual address already mapped?
7075 if ((origpte & PG_V) != 0) {
7077 * Wiring change, just update stats. We don't worry about
7078 * wiring PT pages as they remain resident as long as there
7079 * are valid mappings in them. Hence, if a user page is wired,
7080 * the PT page will be also.
7082 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
7083 pmap->pm_stats.wired_count++;
7084 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
7085 pmap->pm_stats.wired_count--;
7088 * Remove the extra PT page reference.
7092 KASSERT(mpte->ref_count > 0,
7093 ("pmap_enter: missing reference to page table page,"
7098 * Has the physical page changed?
7100 opa = origpte & PG_FRAME;
7103 * No, might be a protection or wiring change.
7105 if ((origpte & PG_MANAGED) != 0 &&
7106 (newpte & PG_RW) != 0)
7107 vm_page_aflag_set(m, PGA_WRITEABLE);
7108 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
7114 * The physical page has changed. Temporarily invalidate
7115 * the mapping. This ensures that all threads sharing the
7116 * pmap keep a consistent view of the mapping, which is
7117 * necessary for the correct handling of COW faults. It
7118 * also permits reuse of the old mapping's PV entry,
7119 * avoiding an allocation.
7121 * For consistency, handle unmanaged mappings the same way.
7123 origpte = pte_load_clear(pte);
7124 KASSERT((origpte & PG_FRAME) == opa,
7125 ("pmap_enter: unexpected pa update for %#lx", va));
7126 if ((origpte & PG_MANAGED) != 0) {
7127 om = PHYS_TO_VM_PAGE(opa);
7130 * The pmap lock is sufficient to synchronize with
7131 * concurrent calls to pmap_page_test_mappings() and
7132 * pmap_ts_referenced().
7134 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7136 if ((origpte & PG_A) != 0) {
7137 pmap_invalidate_page(pmap, va);
7138 vm_page_aflag_set(om, PGA_REFERENCED);
7140 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
7141 pv = pmap_pvh_remove(&om->md, pmap, va);
7143 ("pmap_enter: no PV entry for %#lx", va));
7144 if ((newpte & PG_MANAGED) == 0)
7145 free_pv_entry(pmap, pv);
7146 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
7147 TAILQ_EMPTY(&om->md.pv_list) &&
7148 ((om->flags & PG_FICTITIOUS) != 0 ||
7149 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
7150 vm_page_aflag_clear(om, PGA_WRITEABLE);
7153 * Since this mapping is unmanaged, assume that PG_A
7156 pmap_invalidate_page(pmap, va);
7161 * Increment the counters.
7163 if ((newpte & PG_W) != 0)
7164 pmap->pm_stats.wired_count++;
7165 pmap_resident_count_adj(pmap, 1);
7169 * Enter on the PV list if part of our managed memory.
7171 if ((newpte & PG_MANAGED) != 0) {
7173 pv = get_pv_entry(pmap, &lock);
7176 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
7177 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7179 if ((newpte & PG_RW) != 0)
7180 vm_page_aflag_set(m, PGA_WRITEABLE);
7186 if ((origpte & PG_V) != 0) {
7188 origpte = pte_load_store(pte, newpte);
7189 KASSERT((origpte & PG_FRAME) == pa,
7190 ("pmap_enter: unexpected pa update for %#lx", va));
7191 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
7193 if ((origpte & PG_MANAGED) != 0)
7197 * Although the PTE may still have PG_RW set, TLB
7198 * invalidation may nonetheless be required because
7199 * the PTE no longer has PG_M set.
7201 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
7203 * This PTE change does not require TLB invalidation.
7207 if ((origpte & PG_A) != 0)
7208 pmap_invalidate_page(pmap, va);
7210 pte_store(pte, newpte);
7214 #if VM_NRESERVLEVEL > 0
7216 * If both the page table page and the reservation are fully
7217 * populated, then attempt promotion.
7219 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
7220 pmap_ps_enabled(pmap) &&
7221 (m->flags & PG_FICTITIOUS) == 0 &&
7222 vm_reserv_level_iffullpop(m) == 0)
7223 pmap_promote_pde(pmap, pde, va, &lock);
7235 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
7236 * if successful. Returns false if (1) a page table page cannot be allocated
7237 * without sleeping, (2) a mapping already exists at the specified virtual
7238 * address, or (3) a PV entry cannot be allocated without reclaiming another
7242 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
7243 struct rwlock **lockp)
7248 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7249 PG_V = pmap_valid_bit(pmap);
7250 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
7252 if ((m->oflags & VPO_UNMANAGED) == 0)
7253 newpde |= PG_MANAGED;
7254 if ((prot & VM_PROT_EXECUTE) == 0)
7256 if (va < VM_MAXUSER_ADDRESS)
7258 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
7259 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
7264 * Returns true if every page table entry in the specified page table page is
7268 pmap_every_pte_zero(vm_paddr_t pa)
7270 pt_entry_t *pt_end, *pte;
7272 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
7273 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
7274 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
7282 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
7283 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
7284 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
7285 * a mapping already exists at the specified virtual address. Returns
7286 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
7287 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
7288 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
7290 * The parameter "m" is only used when creating a managed, writeable mapping.
7293 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
7294 vm_page_t m, struct rwlock **lockp)
7296 struct spglist free;
7297 pd_entry_t oldpde, *pde;
7298 pt_entry_t PG_G, PG_RW, PG_V;
7301 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
7302 ("pmap_enter_pde: cannot create wired user mapping"));
7303 PG_G = pmap_global_bit(pmap);
7304 PG_RW = pmap_rw_bit(pmap);
7305 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
7306 ("pmap_enter_pde: newpde is missing PG_M"));
7307 PG_V = pmap_valid_bit(pmap);
7308 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7310 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
7312 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
7313 " in pmap %p", va, pmap);
7314 return (KERN_FAILURE);
7316 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
7317 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
7318 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7319 " in pmap %p", va, pmap);
7320 return (KERN_RESOURCE_SHORTAGE);
7324 * If pkru is not same for the whole pde range, return failure
7325 * and let vm_fault() cope. Check after pde allocation, since
7328 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
7329 pmap_abort_ptp(pmap, va, pdpg);
7330 return (KERN_PROTECTION_FAILURE);
7332 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
7333 newpde &= ~X86_PG_PKU_MASK;
7334 newpde |= pmap_pkru_get(pmap, va);
7338 * If there are existing mappings, either abort or remove them.
7341 if ((oldpde & PG_V) != 0) {
7342 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
7343 ("pmap_enter_pde: pdpg's reference count is too low"));
7344 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
7345 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
7346 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
7349 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7350 " in pmap %p", va, pmap);
7351 return (KERN_FAILURE);
7353 /* Break the existing mapping(s). */
7355 if ((oldpde & PG_PS) != 0) {
7357 * The reference to the PD page that was acquired by
7358 * pmap_alloc_pde() ensures that it won't be freed.
7359 * However, if the PDE resulted from a promotion, then
7360 * a reserved PT page could be freed.
7362 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
7363 if ((oldpde & PG_G) == 0)
7364 pmap_invalidate_pde_page(pmap, va, oldpde);
7366 pmap_delayed_invl_start();
7367 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7369 pmap_invalidate_all(pmap);
7370 pmap_delayed_invl_finish();
7372 if (va < VM_MAXUSER_ADDRESS) {
7373 vm_page_free_pages_toq(&free, true);
7374 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7377 KASSERT(SLIST_EMPTY(&free),
7378 ("pmap_enter_pde: freed kernel page table page"));
7381 * Both pmap_remove_pde() and pmap_remove_ptes() will
7382 * leave the kernel page table page zero filled.
7384 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7385 if (pmap_insert_pt_page(pmap, mt, false))
7386 panic("pmap_enter_pde: trie insert failed");
7390 if ((newpde & PG_MANAGED) != 0) {
7392 * Abort this mapping if its PV entry could not be created.
7394 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7396 pmap_abort_ptp(pmap, va, pdpg);
7397 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7398 " in pmap %p", va, pmap);
7399 return (KERN_RESOURCE_SHORTAGE);
7401 if ((newpde & PG_RW) != 0) {
7402 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7403 vm_page_aflag_set(mt, PGA_WRITEABLE);
7408 * Increment counters.
7410 if ((newpde & PG_W) != 0)
7411 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7412 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7415 * Map the superpage. (This is not a promoted mapping; there will not
7416 * be any lingering 4KB page mappings in the TLB.)
7418 pde_store(pde, newpde);
7420 counter_u64_add(pmap_pde_mappings, 1);
7421 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7423 return (KERN_SUCCESS);
7427 * Maps a sequence of resident pages belonging to the same object.
7428 * The sequence begins with the given page m_start. This page is
7429 * mapped at the given virtual address start. Each subsequent page is
7430 * mapped at a virtual address that is offset from start by the same
7431 * amount as the page is offset from m_start within the object. The
7432 * last page in the sequence is the page with the largest offset from
7433 * m_start that can be mapped at a virtual address less than the given
7434 * virtual address end. Not every virtual page between start and end
7435 * is mapped; only those for which a resident page exists with the
7436 * corresponding offset from m_start are mapped.
7439 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7440 vm_page_t m_start, vm_prot_t prot)
7442 struct rwlock *lock;
7445 vm_pindex_t diff, psize;
7447 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7449 psize = atop(end - start);
7454 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7455 va = start + ptoa(diff);
7456 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7457 m->psind == 1 && pmap_ps_enabled(pmap) &&
7458 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7459 m = &m[NBPDR / PAGE_SIZE - 1];
7461 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7463 m = TAILQ_NEXT(m, listq);
7471 * this code makes some *MAJOR* assumptions:
7472 * 1. Current pmap & pmap exists.
7475 * 4. No page table pages.
7476 * but is *MUCH* faster than pmap_enter...
7480 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7482 struct rwlock *lock;
7486 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7493 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7494 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7496 pt_entry_t newpte, *pte, PG_V;
7498 KASSERT(!VA_IS_CLEANMAP(va) ||
7499 (m->oflags & VPO_UNMANAGED) != 0,
7500 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7501 PG_V = pmap_valid_bit(pmap);
7502 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7505 * In the case that a page table page is not
7506 * resident, we are creating it here.
7508 if (va < VM_MAXUSER_ADDRESS) {
7509 vm_pindex_t ptepindex;
7513 * Calculate pagetable page index
7515 ptepindex = pmap_pde_pindex(va);
7516 if (mpte && (mpte->pindex == ptepindex)) {
7520 * Get the page directory entry
7522 ptepa = pmap_pde(pmap, va);
7525 * If the page table page is mapped, we just increment
7526 * the hold count, and activate it. Otherwise, we
7527 * attempt to allocate a page table page. If this
7528 * attempt fails, we don't retry. Instead, we give up.
7530 if (ptepa && (*ptepa & PG_V) != 0) {
7533 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7537 * Pass NULL instead of the PV list lock
7538 * pointer, because we don't intend to sleep.
7540 mpte = pmap_allocpte_alloc(pmap, ptepindex,
7546 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7547 pte = &pte[pmap_pte_index(va)];
7559 * Enter on the PV list if part of our managed memory.
7561 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7562 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7564 pmap_abort_ptp(pmap, va, mpte);
7569 * Increment counters
7571 pmap_resident_count_adj(pmap, 1);
7573 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7574 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7575 if ((m->oflags & VPO_UNMANAGED) == 0)
7576 newpte |= PG_MANAGED;
7577 if ((prot & VM_PROT_EXECUTE) == 0)
7579 if (va < VM_MAXUSER_ADDRESS)
7580 newpte |= PG_U | pmap_pkru_get(pmap, va);
7581 pte_store(pte, newpte);
7586 * Make a temporary mapping for a physical address. This is only intended
7587 * to be used for panic dumps.
7590 pmap_kenter_temporary(vm_paddr_t pa, int i)
7594 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7595 pmap_kenter(va, pa);
7597 return ((void *)crashdumpmap);
7601 * This code maps large physical mmap regions into the
7602 * processor address space. Note that some shortcuts
7603 * are taken, but the code works.
7606 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7607 vm_pindex_t pindex, vm_size_t size)
7610 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7611 vm_paddr_t pa, ptepa;
7615 PG_A = pmap_accessed_bit(pmap);
7616 PG_M = pmap_modified_bit(pmap);
7617 PG_V = pmap_valid_bit(pmap);
7618 PG_RW = pmap_rw_bit(pmap);
7620 VM_OBJECT_ASSERT_WLOCKED(object);
7621 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7622 ("pmap_object_init_pt: non-device object"));
7623 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7624 if (!pmap_ps_enabled(pmap))
7626 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7628 p = vm_page_lookup(object, pindex);
7629 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7630 ("pmap_object_init_pt: invalid page %p", p));
7631 pat_mode = p->md.pat_mode;
7634 * Abort the mapping if the first page is not physically
7635 * aligned to a 2MB page boundary.
7637 ptepa = VM_PAGE_TO_PHYS(p);
7638 if (ptepa & (NBPDR - 1))
7642 * Skip the first page. Abort the mapping if the rest of
7643 * the pages are not physically contiguous or have differing
7644 * memory attributes.
7646 p = TAILQ_NEXT(p, listq);
7647 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7649 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7650 ("pmap_object_init_pt: invalid page %p", p));
7651 if (pa != VM_PAGE_TO_PHYS(p) ||
7652 pat_mode != p->md.pat_mode)
7654 p = TAILQ_NEXT(p, listq);
7658 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7659 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7660 * will not affect the termination of this loop.
7663 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7664 pa < ptepa + size; pa += NBPDR) {
7665 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7668 * The creation of mappings below is only an
7669 * optimization. If a page directory page
7670 * cannot be allocated without blocking,
7671 * continue on to the next mapping rather than
7677 if ((*pde & PG_V) == 0) {
7678 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7679 PG_U | PG_RW | PG_V);
7680 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7681 counter_u64_add(pmap_pde_mappings, 1);
7683 /* Continue on if the PDE is already valid. */
7685 KASSERT(pdpg->ref_count > 0,
7686 ("pmap_object_init_pt: missing reference "
7687 "to page directory page, va: 0x%lx", addr));
7696 * Clear the wired attribute from the mappings for the specified range of
7697 * addresses in the given pmap. Every valid mapping within that range
7698 * must have the wired attribute set. In contrast, invalid mappings
7699 * cannot have the wired attribute set, so they are ignored.
7701 * The wired attribute of the page table entry is not a hardware
7702 * feature, so there is no need to invalidate any TLB entries.
7703 * Since pmap_demote_pde() for the wired entry must never fail,
7704 * pmap_delayed_invl_start()/finish() calls around the
7705 * function are not needed.
7708 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7710 vm_offset_t va_next;
7711 pml4_entry_t *pml4e;
7714 pt_entry_t *pte, PG_V, PG_G;
7716 PG_V = pmap_valid_bit(pmap);
7717 PG_G = pmap_global_bit(pmap);
7719 for (; sva < eva; sva = va_next) {
7720 pml4e = pmap_pml4e(pmap, sva);
7721 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7722 va_next = (sva + NBPML4) & ~PML4MASK;
7728 va_next = (sva + NBPDP) & ~PDPMASK;
7731 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7732 if ((*pdpe & PG_V) == 0)
7734 if ((*pdpe & PG_PS) != 0) {
7735 KASSERT(va_next <= eva,
7736 ("partial update of non-transparent 1G mapping "
7737 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7738 *pdpe, sva, eva, va_next));
7739 MPASS(pmap != kernel_pmap); /* XXXKIB */
7740 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7741 atomic_clear_long(pdpe, PG_W);
7742 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7746 va_next = (sva + NBPDR) & ~PDRMASK;
7749 pde = pmap_pdpe_to_pde(pdpe, sva);
7750 if ((*pde & PG_V) == 0)
7752 if ((*pde & PG_PS) != 0) {
7753 if ((*pde & PG_W) == 0)
7754 panic("pmap_unwire: pde %#jx is missing PG_W",
7758 * Are we unwiring the entire large page? If not,
7759 * demote the mapping and fall through.
7761 if (sva + NBPDR == va_next && eva >= va_next) {
7762 atomic_clear_long(pde, PG_W);
7763 pmap->pm_stats.wired_count -= NBPDR /
7766 } else if (!pmap_demote_pde(pmap, pde, sva))
7767 panic("pmap_unwire: demotion failed");
7771 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7773 if ((*pte & PG_V) == 0)
7775 if ((*pte & PG_W) == 0)
7776 panic("pmap_unwire: pte %#jx is missing PG_W",
7780 * PG_W must be cleared atomically. Although the pmap
7781 * lock synchronizes access to PG_W, another processor
7782 * could be setting PG_M and/or PG_A concurrently.
7784 atomic_clear_long(pte, PG_W);
7785 pmap->pm_stats.wired_count--;
7792 * Copy the range specified by src_addr/len
7793 * from the source map to the range dst_addr/len
7794 * in the destination map.
7796 * This routine is only advisory and need not do anything.
7799 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7800 vm_offset_t src_addr)
7802 struct rwlock *lock;
7803 pml4_entry_t *pml4e;
7805 pd_entry_t *pde, srcptepaddr;
7806 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7807 vm_offset_t addr, end_addr, va_next;
7808 vm_page_t dst_pdpg, dstmpte, srcmpte;
7810 if (dst_addr != src_addr)
7813 if (dst_pmap->pm_type != src_pmap->pm_type)
7817 * EPT page table entries that require emulation of A/D bits are
7818 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7819 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7820 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7821 * implementations flag an EPT misconfiguration for exec-only
7822 * mappings we skip this function entirely for emulated pmaps.
7824 if (pmap_emulate_ad_bits(dst_pmap))
7827 end_addr = src_addr + len;
7829 if (dst_pmap < src_pmap) {
7830 PMAP_LOCK(dst_pmap);
7831 PMAP_LOCK(src_pmap);
7833 PMAP_LOCK(src_pmap);
7834 PMAP_LOCK(dst_pmap);
7837 PG_A = pmap_accessed_bit(dst_pmap);
7838 PG_M = pmap_modified_bit(dst_pmap);
7839 PG_V = pmap_valid_bit(dst_pmap);
7841 for (addr = src_addr; addr < end_addr; addr = va_next) {
7842 KASSERT(addr < UPT_MIN_ADDRESS,
7843 ("pmap_copy: invalid to pmap_copy page tables"));
7845 pml4e = pmap_pml4e(src_pmap, addr);
7846 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7847 va_next = (addr + NBPML4) & ~PML4MASK;
7853 va_next = (addr + NBPDP) & ~PDPMASK;
7856 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7857 if ((*pdpe & PG_V) == 0)
7859 if ((*pdpe & PG_PS) != 0) {
7860 KASSERT(va_next <= end_addr,
7861 ("partial update of non-transparent 1G mapping "
7862 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7863 *pdpe, addr, end_addr, va_next));
7864 MPASS((addr & PDPMASK) == 0);
7865 MPASS((*pdpe & PG_MANAGED) == 0);
7866 srcptepaddr = *pdpe;
7867 pdpe = pmap_pdpe(dst_pmap, addr);
7869 if (pmap_allocpte_alloc(dst_pmap,
7870 pmap_pml4e_pindex(addr), NULL, addr) ==
7873 pdpe = pmap_pdpe(dst_pmap, addr);
7875 pml4e = pmap_pml4e(dst_pmap, addr);
7876 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7877 dst_pdpg->ref_count++;
7880 ("1G mapping present in dst pmap "
7881 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7882 *pdpe, addr, end_addr, va_next));
7883 *pdpe = srcptepaddr & ~PG_W;
7884 pmap_resident_count_adj(dst_pmap, NBPDP / PAGE_SIZE);
7888 va_next = (addr + NBPDR) & ~PDRMASK;
7892 pde = pmap_pdpe_to_pde(pdpe, addr);
7894 if (srcptepaddr == 0)
7897 if (srcptepaddr & PG_PS) {
7899 * We can only virtual copy whole superpages.
7901 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7903 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7906 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7907 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7908 PMAP_ENTER_NORECLAIM, &lock))) {
7910 * We leave the dirty bit unchanged because
7911 * managed read/write superpage mappings are
7912 * required to be dirty. However, managed
7913 * superpage mappings are not required to
7914 * have their accessed bit set, so we clear
7915 * it because we don't know if this mapping
7918 srcptepaddr &= ~PG_W;
7919 if ((srcptepaddr & PG_MANAGED) != 0)
7920 srcptepaddr &= ~PG_A;
7922 pmap_resident_count_adj(dst_pmap, NBPDR /
7924 counter_u64_add(pmap_pde_mappings, 1);
7926 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7930 srcptepaddr &= PG_FRAME;
7931 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7932 KASSERT(srcmpte->ref_count > 0,
7933 ("pmap_copy: source page table page is unused"));
7935 if (va_next > end_addr)
7938 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7939 src_pte = &src_pte[pmap_pte_index(addr)];
7941 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7945 * We only virtual copy managed pages.
7947 if ((ptetemp & PG_MANAGED) == 0)
7950 if (dstmpte != NULL) {
7951 KASSERT(dstmpte->pindex ==
7952 pmap_pde_pindex(addr),
7953 ("dstmpte pindex/addr mismatch"));
7954 dstmpte->ref_count++;
7955 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7958 dst_pte = (pt_entry_t *)
7959 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7960 dst_pte = &dst_pte[pmap_pte_index(addr)];
7961 if (*dst_pte == 0 &&
7962 pmap_try_insert_pv_entry(dst_pmap, addr,
7963 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7965 * Clear the wired, modified, and accessed
7966 * (referenced) bits during the copy.
7968 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7969 pmap_resident_count_adj(dst_pmap, 1);
7971 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7974 /* Have we copied all of the valid mappings? */
7975 if (dstmpte->ref_count >= srcmpte->ref_count)
7982 PMAP_UNLOCK(src_pmap);
7983 PMAP_UNLOCK(dst_pmap);
7987 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7991 if (dst_pmap->pm_type != src_pmap->pm_type ||
7992 dst_pmap->pm_type != PT_X86 ||
7993 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7996 if (dst_pmap < src_pmap) {
7997 PMAP_LOCK(dst_pmap);
7998 PMAP_LOCK(src_pmap);
8000 PMAP_LOCK(src_pmap);
8001 PMAP_LOCK(dst_pmap);
8003 error = pmap_pkru_copy(dst_pmap, src_pmap);
8004 /* Clean up partial copy on failure due to no memory. */
8005 if (error == ENOMEM)
8006 pmap_pkru_deassign_all(dst_pmap);
8007 PMAP_UNLOCK(src_pmap);
8008 PMAP_UNLOCK(dst_pmap);
8009 if (error != ENOMEM)
8017 * Zero the specified hardware page.
8020 pmap_zero_page(vm_page_t m)
8022 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
8024 pagezero((void *)va);
8028 * Zero an an area within a single hardware page. off and size must not
8029 * cover an area beyond a single hardware page.
8032 pmap_zero_page_area(vm_page_t m, int off, int size)
8034 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
8036 if (off == 0 && size == PAGE_SIZE)
8037 pagezero((void *)va);
8039 bzero((char *)va + off, size);
8043 * Copy 1 specified hardware page to another.
8046 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
8048 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
8049 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
8051 pagecopy((void *)src, (void *)dst);
8054 int unmapped_buf_allowed = 1;
8057 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
8058 vm_offset_t b_offset, int xfersize)
8062 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
8066 while (xfersize > 0) {
8067 a_pg_offset = a_offset & PAGE_MASK;
8068 pages[0] = ma[a_offset >> PAGE_SHIFT];
8069 b_pg_offset = b_offset & PAGE_MASK;
8070 pages[1] = mb[b_offset >> PAGE_SHIFT];
8071 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
8072 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
8073 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
8074 a_cp = (char *)vaddr[0] + a_pg_offset;
8075 b_cp = (char *)vaddr[1] + b_pg_offset;
8076 bcopy(a_cp, b_cp, cnt);
8077 if (__predict_false(mapped))
8078 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
8086 * Returns true if the pmap's pv is one of the first
8087 * 16 pvs linked to from this page. This count may
8088 * be changed upwards or downwards in the future; it
8089 * is only necessary that true be returned for a small
8090 * subset of pmaps for proper page aging.
8093 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
8095 struct md_page *pvh;
8096 struct rwlock *lock;
8101 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8102 ("pmap_page_exists_quick: page %p is not managed", m));
8104 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8106 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8107 if (PV_PMAP(pv) == pmap) {
8115 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
8116 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8117 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8118 if (PV_PMAP(pv) == pmap) {
8132 * pmap_page_wired_mappings:
8134 * Return the number of managed mappings to the given physical page
8138 pmap_page_wired_mappings(vm_page_t m)
8140 struct rwlock *lock;
8141 struct md_page *pvh;
8145 int count, md_gen, pvh_gen;
8147 if ((m->oflags & VPO_UNMANAGED) != 0)
8149 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8153 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8155 if (!PMAP_TRYLOCK(pmap)) {
8156 md_gen = m->md.pv_gen;
8160 if (md_gen != m->md.pv_gen) {
8165 pte = pmap_pte(pmap, pv->pv_va);
8166 if ((*pte & PG_W) != 0)
8170 if ((m->flags & PG_FICTITIOUS) == 0) {
8171 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8172 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8174 if (!PMAP_TRYLOCK(pmap)) {
8175 md_gen = m->md.pv_gen;
8176 pvh_gen = pvh->pv_gen;
8180 if (md_gen != m->md.pv_gen ||
8181 pvh_gen != pvh->pv_gen) {
8186 pte = pmap_pde(pmap, pv->pv_va);
8187 if ((*pte & PG_W) != 0)
8197 * Returns TRUE if the given page is mapped individually or as part of
8198 * a 2mpage. Otherwise, returns FALSE.
8201 pmap_page_is_mapped(vm_page_t m)
8203 struct rwlock *lock;
8206 if ((m->oflags & VPO_UNMANAGED) != 0)
8208 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8210 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
8211 ((m->flags & PG_FICTITIOUS) == 0 &&
8212 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
8218 * Destroy all managed, non-wired mappings in the given user-space
8219 * pmap. This pmap cannot be active on any processor besides the
8222 * This function cannot be applied to the kernel pmap. Moreover, it
8223 * is not intended for general use. It is only to be used during
8224 * process termination. Consequently, it can be implemented in ways
8225 * that make it faster than pmap_remove(). First, it can more quickly
8226 * destroy mappings by iterating over the pmap's collection of PV
8227 * entries, rather than searching the page table. Second, it doesn't
8228 * have to test and clear the page table entries atomically, because
8229 * no processor is currently accessing the user address space. In
8230 * particular, a page table entry's dirty bit won't change state once
8231 * this function starts.
8233 * Although this function destroys all of the pmap's managed,
8234 * non-wired mappings, it can delay and batch the invalidation of TLB
8235 * entries without calling pmap_delayed_invl_start() and
8236 * pmap_delayed_invl_finish(). Because the pmap is not active on
8237 * any other processor, none of these TLB entries will ever be used
8238 * before their eventual invalidation. Consequently, there is no need
8239 * for either pmap_remove_all() or pmap_remove_write() to wait for
8240 * that eventual TLB invalidation.
8243 pmap_remove_pages(pmap_t pmap)
8246 pt_entry_t *pte, tpte;
8247 pt_entry_t PG_M, PG_RW, PG_V;
8248 struct spglist free;
8249 struct pv_chunklist free_chunks[PMAP_MEMDOM];
8250 vm_page_t m, mpte, mt;
8252 struct md_page *pvh;
8253 struct pv_chunk *pc, *npc;
8254 struct rwlock *lock;
8256 uint64_t inuse, bitmask;
8257 int allfree, field, freed, i, idx;
8258 boolean_t superpage;
8262 * Assert that the given pmap is only active on the current
8263 * CPU. Unfortunately, we cannot block another CPU from
8264 * activating the pmap while this function is executing.
8266 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
8269 cpuset_t other_cpus;
8271 other_cpus = all_cpus;
8273 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
8274 CPU_AND(&other_cpus, &pmap->pm_active);
8276 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
8281 PG_M = pmap_modified_bit(pmap);
8282 PG_V = pmap_valid_bit(pmap);
8283 PG_RW = pmap_rw_bit(pmap);
8285 for (i = 0; i < PMAP_MEMDOM; i++)
8286 TAILQ_INIT(&free_chunks[i]);
8289 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
8292 for (field = 0; field < _NPCM; field++) {
8293 inuse = ~pc->pc_map[field] & pc_freemask[field];
8294 while (inuse != 0) {
8296 bitmask = 1UL << bit;
8297 idx = field * 64 + bit;
8298 pv = &pc->pc_pventry[idx];
8301 pte = pmap_pdpe(pmap, pv->pv_va);
8303 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
8305 if ((tpte & (PG_PS | PG_V)) == PG_V) {
8308 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
8310 pte = &pte[pmap_pte_index(pv->pv_va)];
8314 * Keep track whether 'tpte' is a
8315 * superpage explicitly instead of
8316 * relying on PG_PS being set.
8318 * This is because PG_PS is numerically
8319 * identical to PG_PTE_PAT and thus a
8320 * regular page could be mistaken for
8326 if ((tpte & PG_V) == 0) {
8327 panic("bad pte va %lx pte %lx",
8332 * We cannot remove wired pages from a process' mapping at this time
8340 pc->pc_map[field] |= bitmask;
8343 * Because this pmap is not active on other
8344 * processors, the dirty bit cannot have
8345 * changed state since we last loaded pte.
8350 pa = tpte & PG_PS_FRAME;
8352 pa = tpte & PG_FRAME;
8354 m = PHYS_TO_VM_PAGE(pa);
8355 KASSERT(m->phys_addr == pa,
8356 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
8357 m, (uintmax_t)m->phys_addr,
8360 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
8361 m < &vm_page_array[vm_page_array_size],
8362 ("pmap_remove_pages: bad tpte %#jx",
8366 * Update the vm_page_t clean/reference bits.
8368 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8370 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8376 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
8379 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
8380 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
8381 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8383 if (TAILQ_EMPTY(&pvh->pv_list)) {
8384 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8385 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8386 TAILQ_EMPTY(&mt->md.pv_list))
8387 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8389 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8391 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8392 ("pmap_remove_pages: pte page not promoted"));
8393 pmap_resident_count_adj(pmap, -1);
8394 KASSERT(mpte->ref_count == NPTEPG,
8395 ("pmap_remove_pages: pte page reference count error"));
8396 mpte->ref_count = 0;
8397 pmap_add_delayed_free_list(mpte, &free, FALSE);
8400 pmap_resident_count_adj(pmap, -1);
8401 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8403 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8404 TAILQ_EMPTY(&m->md.pv_list) &&
8405 (m->flags & PG_FICTITIOUS) == 0) {
8406 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8407 if (TAILQ_EMPTY(&pvh->pv_list))
8408 vm_page_aflag_clear(m, PGA_WRITEABLE);
8411 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8415 PV_STAT(counter_u64_add(pv_entry_frees, freed));
8416 PV_STAT(counter_u64_add(pv_entry_spare, freed));
8417 PV_STAT(counter_u64_add(pv_entry_count, -freed));
8419 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8420 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8425 pmap_invalidate_all(pmap);
8426 pmap_pkru_deassign_all(pmap);
8427 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8429 vm_page_free_pages_toq(&free, true);
8433 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8435 struct rwlock *lock;
8437 struct md_page *pvh;
8438 pt_entry_t *pte, mask;
8439 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8441 int md_gen, pvh_gen;
8445 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8448 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8450 if (!PMAP_TRYLOCK(pmap)) {
8451 md_gen = m->md.pv_gen;
8455 if (md_gen != m->md.pv_gen) {
8460 pte = pmap_pte(pmap, pv->pv_va);
8463 PG_M = pmap_modified_bit(pmap);
8464 PG_RW = pmap_rw_bit(pmap);
8465 mask |= PG_RW | PG_M;
8468 PG_A = pmap_accessed_bit(pmap);
8469 PG_V = pmap_valid_bit(pmap);
8470 mask |= PG_V | PG_A;
8472 rv = (*pte & mask) == mask;
8477 if ((m->flags & PG_FICTITIOUS) == 0) {
8478 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8479 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8481 if (!PMAP_TRYLOCK(pmap)) {
8482 md_gen = m->md.pv_gen;
8483 pvh_gen = pvh->pv_gen;
8487 if (md_gen != m->md.pv_gen ||
8488 pvh_gen != pvh->pv_gen) {
8493 pte = pmap_pde(pmap, pv->pv_va);
8496 PG_M = pmap_modified_bit(pmap);
8497 PG_RW = pmap_rw_bit(pmap);
8498 mask |= PG_RW | PG_M;
8501 PG_A = pmap_accessed_bit(pmap);
8502 PG_V = pmap_valid_bit(pmap);
8503 mask |= PG_V | PG_A;
8505 rv = (*pte & mask) == mask;
8519 * Return whether or not the specified physical page was modified
8520 * in any physical maps.
8523 pmap_is_modified(vm_page_t m)
8526 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8527 ("pmap_is_modified: page %p is not managed", m));
8530 * If the page is not busied then this check is racy.
8532 if (!pmap_page_is_write_mapped(m))
8534 return (pmap_page_test_mappings(m, FALSE, TRUE));
8538 * pmap_is_prefaultable:
8540 * Return whether or not the specified virtual address is eligible
8544 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8547 pt_entry_t *pte, PG_V;
8550 PG_V = pmap_valid_bit(pmap);
8553 pde = pmap_pde(pmap, addr);
8554 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8555 pte = pmap_pde_to_pte(pde, addr);
8556 rv = (*pte & PG_V) == 0;
8563 * pmap_is_referenced:
8565 * Return whether or not the specified physical page was referenced
8566 * in any physical maps.
8569 pmap_is_referenced(vm_page_t m)
8572 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8573 ("pmap_is_referenced: page %p is not managed", m));
8574 return (pmap_page_test_mappings(m, TRUE, FALSE));
8578 * Clear the write and modified bits in each of the given page's mappings.
8581 pmap_remove_write(vm_page_t m)
8583 struct md_page *pvh;
8585 struct rwlock *lock;
8586 pv_entry_t next_pv, pv;
8588 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8590 int pvh_gen, md_gen;
8592 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8593 ("pmap_remove_write: page %p is not managed", m));
8595 vm_page_assert_busied(m);
8596 if (!pmap_page_is_write_mapped(m))
8599 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8600 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8601 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8604 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8606 if (!PMAP_TRYLOCK(pmap)) {
8607 pvh_gen = pvh->pv_gen;
8611 if (pvh_gen != pvh->pv_gen) {
8616 PG_RW = pmap_rw_bit(pmap);
8618 pde = pmap_pde(pmap, va);
8619 if ((*pde & PG_RW) != 0)
8620 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8621 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8622 ("inconsistent pv lock %p %p for page %p",
8623 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8626 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8628 if (!PMAP_TRYLOCK(pmap)) {
8629 pvh_gen = pvh->pv_gen;
8630 md_gen = m->md.pv_gen;
8634 if (pvh_gen != pvh->pv_gen ||
8635 md_gen != m->md.pv_gen) {
8640 PG_M = pmap_modified_bit(pmap);
8641 PG_RW = pmap_rw_bit(pmap);
8642 pde = pmap_pde(pmap, pv->pv_va);
8643 KASSERT((*pde & PG_PS) == 0,
8644 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8646 pte = pmap_pde_to_pte(pde, pv->pv_va);
8648 if (oldpte & PG_RW) {
8649 while (!atomic_fcmpset_long(pte, &oldpte, oldpte &
8652 if ((oldpte & PG_M) != 0)
8654 pmap_invalidate_page(pmap, pv->pv_va);
8659 vm_page_aflag_clear(m, PGA_WRITEABLE);
8660 pmap_delayed_invl_wait(m);
8663 static __inline boolean_t
8664 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8667 if (!pmap_emulate_ad_bits(pmap))
8670 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8673 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8674 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8675 * if the EPT_PG_WRITE bit is set.
8677 if ((pte & EPT_PG_WRITE) != 0)
8681 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8683 if ((pte & EPT_PG_EXECUTE) == 0 ||
8684 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8691 * pmap_ts_referenced:
8693 * Return a count of reference bits for a page, clearing those bits.
8694 * It is not necessary for every reference bit to be cleared, but it
8695 * is necessary that 0 only be returned when there are truly no
8696 * reference bits set.
8698 * As an optimization, update the page's dirty field if a modified bit is
8699 * found while counting reference bits. This opportunistic update can be
8700 * performed at low cost and can eliminate the need for some future calls
8701 * to pmap_is_modified(). However, since this function stops after
8702 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8703 * dirty pages. Those dirty pages will only be detected by a future call
8704 * to pmap_is_modified().
8706 * A DI block is not needed within this function, because
8707 * invalidations are performed before the PV list lock is
8711 pmap_ts_referenced(vm_page_t m)
8713 struct md_page *pvh;
8716 struct rwlock *lock;
8717 pd_entry_t oldpde, *pde;
8718 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8721 int cleared, md_gen, not_cleared, pvh_gen;
8722 struct spglist free;
8725 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8726 ("pmap_ts_referenced: page %p is not managed", m));
8729 pa = VM_PAGE_TO_PHYS(m);
8730 lock = PHYS_TO_PV_LIST_LOCK(pa);
8731 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8735 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8736 goto small_mappings;
8742 if (!PMAP_TRYLOCK(pmap)) {
8743 pvh_gen = pvh->pv_gen;
8747 if (pvh_gen != pvh->pv_gen) {
8752 PG_A = pmap_accessed_bit(pmap);
8753 PG_M = pmap_modified_bit(pmap);
8754 PG_RW = pmap_rw_bit(pmap);
8756 pde = pmap_pde(pmap, pv->pv_va);
8758 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8760 * Although "oldpde" is mapping a 2MB page, because
8761 * this function is called at a 4KB page granularity,
8762 * we only update the 4KB page under test.
8766 if ((oldpde & PG_A) != 0) {
8768 * Since this reference bit is shared by 512 4KB
8769 * pages, it should not be cleared every time it is
8770 * tested. Apply a simple "hash" function on the
8771 * physical page number, the virtual superpage number,
8772 * and the pmap address to select one 4KB page out of
8773 * the 512 on which testing the reference bit will
8774 * result in clearing that reference bit. This
8775 * function is designed to avoid the selection of the
8776 * same 4KB page for every 2MB page mapping.
8778 * On demotion, a mapping that hasn't been referenced
8779 * is simply destroyed. To avoid the possibility of a
8780 * subsequent page fault on a demoted wired mapping,
8781 * always leave its reference bit set. Moreover,
8782 * since the superpage is wired, the current state of
8783 * its reference bit won't affect page replacement.
8785 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8786 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8787 (oldpde & PG_W) == 0) {
8788 if (safe_to_clear_referenced(pmap, oldpde)) {
8789 atomic_clear_long(pde, PG_A);
8790 pmap_invalidate_page(pmap, pv->pv_va);
8792 } else if (pmap_demote_pde_locked(pmap, pde,
8793 pv->pv_va, &lock)) {
8795 * Remove the mapping to a single page
8796 * so that a subsequent access may
8797 * repromote. Since the underlying
8798 * page table page is fully populated,
8799 * this removal never frees a page
8803 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8805 pte = pmap_pde_to_pte(pde, va);
8806 pmap_remove_pte(pmap, pte, va, *pde,
8808 pmap_invalidate_page(pmap, va);
8814 * The superpage mapping was removed
8815 * entirely and therefore 'pv' is no
8823 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8824 ("inconsistent pv lock %p %p for page %p",
8825 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8830 /* Rotate the PV list if it has more than one entry. */
8831 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8832 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8833 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8836 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8838 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8840 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8847 if (!PMAP_TRYLOCK(pmap)) {
8848 pvh_gen = pvh->pv_gen;
8849 md_gen = m->md.pv_gen;
8853 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8858 PG_A = pmap_accessed_bit(pmap);
8859 PG_M = pmap_modified_bit(pmap);
8860 PG_RW = pmap_rw_bit(pmap);
8861 pde = pmap_pde(pmap, pv->pv_va);
8862 KASSERT((*pde & PG_PS) == 0,
8863 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8865 pte = pmap_pde_to_pte(pde, pv->pv_va);
8866 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8868 if ((*pte & PG_A) != 0) {
8869 if (safe_to_clear_referenced(pmap, *pte)) {
8870 atomic_clear_long(pte, PG_A);
8871 pmap_invalidate_page(pmap, pv->pv_va);
8873 } else if ((*pte & PG_W) == 0) {
8875 * Wired pages cannot be paged out so
8876 * doing accessed bit emulation for
8877 * them is wasted effort. We do the
8878 * hard work for unwired pages only.
8880 pmap_remove_pte(pmap, pte, pv->pv_va,
8881 *pde, &free, &lock);
8882 pmap_invalidate_page(pmap, pv->pv_va);
8887 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8888 ("inconsistent pv lock %p %p for page %p",
8889 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8894 /* Rotate the PV list if it has more than one entry. */
8895 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8896 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8897 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8900 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8901 not_cleared < PMAP_TS_REFERENCED_MAX);
8904 vm_page_free_pages_toq(&free, true);
8905 return (cleared + not_cleared);
8909 * Apply the given advice to the specified range of addresses within the
8910 * given pmap. Depending on the advice, clear the referenced and/or
8911 * modified flags in each mapping and set the mapped page's dirty field.
8914 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8916 struct rwlock *lock;
8917 pml4_entry_t *pml4e;
8919 pd_entry_t oldpde, *pde;
8920 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8921 vm_offset_t va, va_next;
8925 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8929 * A/D bit emulation requires an alternate code path when clearing
8930 * the modified and accessed bits below. Since this function is
8931 * advisory in nature we skip it entirely for pmaps that require
8932 * A/D bit emulation.
8934 if (pmap_emulate_ad_bits(pmap))
8937 PG_A = pmap_accessed_bit(pmap);
8938 PG_G = pmap_global_bit(pmap);
8939 PG_M = pmap_modified_bit(pmap);
8940 PG_V = pmap_valid_bit(pmap);
8941 PG_RW = pmap_rw_bit(pmap);
8943 pmap_delayed_invl_start();
8945 for (; sva < eva; sva = va_next) {
8946 pml4e = pmap_pml4e(pmap, sva);
8947 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8948 va_next = (sva + NBPML4) & ~PML4MASK;
8954 va_next = (sva + NBPDP) & ~PDPMASK;
8957 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8958 if ((*pdpe & PG_V) == 0)
8960 if ((*pdpe & PG_PS) != 0) {
8961 KASSERT(va_next <= eva,
8962 ("partial update of non-transparent 1G mapping "
8963 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8964 *pdpe, sva, eva, va_next));
8968 va_next = (sva + NBPDR) & ~PDRMASK;
8971 pde = pmap_pdpe_to_pde(pdpe, sva);
8973 if ((oldpde & PG_V) == 0)
8975 else if ((oldpde & PG_PS) != 0) {
8976 if ((oldpde & PG_MANAGED) == 0)
8979 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8984 * The large page mapping was destroyed.
8990 * Unless the page mappings are wired, remove the
8991 * mapping to a single page so that a subsequent
8992 * access may repromote. Choosing the last page
8993 * within the address range [sva, min(va_next, eva))
8994 * generally results in more repromotions. Since the
8995 * underlying page table page is fully populated, this
8996 * removal never frees a page table page.
8998 if ((oldpde & PG_W) == 0) {
9004 ("pmap_advise: no address gap"));
9005 pte = pmap_pde_to_pte(pde, va);
9006 KASSERT((*pte & PG_V) != 0,
9007 ("pmap_advise: invalid PTE"));
9008 pmap_remove_pte(pmap, pte, va, *pde, NULL,
9018 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
9020 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
9022 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
9023 if (advice == MADV_DONTNEED) {
9025 * Future calls to pmap_is_modified()
9026 * can be avoided by making the page
9029 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9032 atomic_clear_long(pte, PG_M | PG_A);
9033 } else if ((*pte & PG_A) != 0)
9034 atomic_clear_long(pte, PG_A);
9038 if ((*pte & PG_G) != 0) {
9045 if (va != va_next) {
9046 pmap_invalidate_range(pmap, va, sva);
9051 pmap_invalidate_range(pmap, va, sva);
9054 pmap_invalidate_all(pmap);
9056 pmap_delayed_invl_finish();
9060 * Clear the modify bits on the specified physical page.
9063 pmap_clear_modify(vm_page_t m)
9065 struct md_page *pvh;
9067 pv_entry_t next_pv, pv;
9068 pd_entry_t oldpde, *pde;
9069 pt_entry_t *pte, PG_M, PG_RW;
9070 struct rwlock *lock;
9072 int md_gen, pvh_gen;
9074 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
9075 ("pmap_clear_modify: page %p is not managed", m));
9076 vm_page_assert_busied(m);
9078 if (!pmap_page_is_write_mapped(m))
9080 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
9081 pa_to_pvh(VM_PAGE_TO_PHYS(m));
9082 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
9085 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
9087 if (!PMAP_TRYLOCK(pmap)) {
9088 pvh_gen = pvh->pv_gen;
9092 if (pvh_gen != pvh->pv_gen) {
9097 PG_M = pmap_modified_bit(pmap);
9098 PG_RW = pmap_rw_bit(pmap);
9100 pde = pmap_pde(pmap, va);
9102 /* If oldpde has PG_RW set, then it also has PG_M set. */
9103 if ((oldpde & PG_RW) != 0 &&
9104 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
9105 (oldpde & PG_W) == 0) {
9107 * Write protect the mapping to a single page so that
9108 * a subsequent write access may repromote.
9110 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
9111 pte = pmap_pde_to_pte(pde, va);
9112 atomic_clear_long(pte, PG_M | PG_RW);
9114 pmap_invalidate_page(pmap, va);
9118 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
9120 if (!PMAP_TRYLOCK(pmap)) {
9121 md_gen = m->md.pv_gen;
9122 pvh_gen = pvh->pv_gen;
9126 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
9131 PG_M = pmap_modified_bit(pmap);
9132 PG_RW = pmap_rw_bit(pmap);
9133 pde = pmap_pde(pmap, pv->pv_va);
9134 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
9135 " a 2mpage in page %p's pv list", m));
9136 pte = pmap_pde_to_pte(pde, pv->pv_va);
9137 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
9138 atomic_clear_long(pte, PG_M);
9139 pmap_invalidate_page(pmap, pv->pv_va);
9147 * Miscellaneous support routines follow
9150 /* Adjust the properties for a leaf page table entry. */
9151 static __inline void
9152 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
9156 opte = *(u_long *)pte;
9158 npte = opte & ~mask;
9160 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
9165 * Map a set of physical memory pages into the kernel virtual
9166 * address space. Return a pointer to where it is mapped. This
9167 * routine is intended to be used for mapping device memory,
9171 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
9173 struct pmap_preinit_mapping *ppim;
9174 vm_offset_t va, offset;
9178 offset = pa & PAGE_MASK;
9179 size = round_page(offset + size);
9180 pa = trunc_page(pa);
9182 if (!pmap_initialized) {
9184 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9185 ppim = pmap_preinit_mapping + i;
9186 if (ppim->va == 0) {
9190 ppim->va = virtual_avail;
9191 virtual_avail += size;
9197 panic("%s: too many preinit mappings", __func__);
9200 * If we have a preinit mapping, re-use it.
9202 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9203 ppim = pmap_preinit_mapping + i;
9204 if (ppim->pa == pa && ppim->sz == size &&
9205 (ppim->mode == mode ||
9206 (flags & MAPDEV_SETATTR) == 0))
9207 return ((void *)(ppim->va + offset));
9210 * If the specified range of physical addresses fits within
9211 * the direct map window, use the direct map.
9213 if (pa < dmaplimit && pa + size <= dmaplimit) {
9214 va = PHYS_TO_DMAP(pa);
9215 if ((flags & MAPDEV_SETATTR) != 0) {
9216 PMAP_LOCK(kernel_pmap);
9217 i = pmap_change_props_locked(va, size,
9218 PROT_NONE, mode, flags);
9219 PMAP_UNLOCK(kernel_pmap);
9223 return ((void *)(va + offset));
9225 va = kva_alloc(size);
9227 panic("%s: Couldn't allocate KVA", __func__);
9229 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
9230 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
9231 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
9232 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9233 pmap_invalidate_cache_range(va, va + tmpsize);
9234 return ((void *)(va + offset));
9238 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
9241 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
9246 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
9249 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
9253 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
9256 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
9261 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
9264 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
9265 MAPDEV_FLUSHCACHE));
9269 pmap_unmapdev(vm_offset_t va, vm_size_t size)
9271 struct pmap_preinit_mapping *ppim;
9275 /* If we gave a direct map region in pmap_mapdev, do nothing */
9276 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
9278 offset = va & PAGE_MASK;
9279 size = round_page(offset + size);
9280 va = trunc_page(va);
9281 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9282 ppim = pmap_preinit_mapping + i;
9283 if (ppim->va == va && ppim->sz == size) {
9284 if (pmap_initialized)
9290 if (va + size == virtual_avail)
9295 if (pmap_initialized) {
9296 pmap_qremove(va, atop(size));
9302 * Tries to demote a 1GB page mapping.
9305 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
9307 pdp_entry_t newpdpe, oldpdpe;
9308 pd_entry_t *firstpde, newpde, *pde;
9309 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
9313 PG_A = pmap_accessed_bit(pmap);
9314 PG_M = pmap_modified_bit(pmap);
9315 PG_V = pmap_valid_bit(pmap);
9316 PG_RW = pmap_rw_bit(pmap);
9318 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9320 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
9321 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
9322 pdpg = pmap_alloc_pt_page(pmap, va >> PDPSHIFT,
9323 VM_ALLOC_WIRED | VM_ALLOC_INTERRUPT);
9325 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
9326 " in pmap %p", va, pmap);
9329 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
9330 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
9331 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
9332 KASSERT((oldpdpe & PG_A) != 0,
9333 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
9334 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
9335 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
9339 * Initialize the page directory page.
9341 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
9347 * Demote the mapping.
9352 * Invalidate a stale recursive mapping of the page directory page.
9354 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
9356 counter_u64_add(pmap_pdpe_demotions, 1);
9357 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
9358 " in pmap %p", va, pmap);
9363 * Sets the memory attribute for the specified page.
9366 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
9369 m->md.pat_mode = ma;
9372 * If "m" is a normal page, update its direct mapping. This update
9373 * can be relied upon to perform any cache operations that are
9374 * required for data coherence.
9376 if ((m->flags & PG_FICTITIOUS) == 0 &&
9377 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
9379 panic("memory attribute change on the direct map failed");
9383 * Changes the specified virtual address range's memory type to that given by
9384 * the parameter "mode". The specified virtual address range must be
9385 * completely contained within either the direct map or the kernel map. If
9386 * the virtual address range is contained within the kernel map, then the
9387 * memory type for each of the corresponding ranges of the direct map is also
9388 * changed. (The corresponding ranges of the direct map are those ranges that
9389 * map the same physical pages as the specified virtual address range.) These
9390 * changes to the direct map are necessary because Intel describes the
9391 * behavior of their processors as "undefined" if two or more mappings to the
9392 * same physical page have different memory types.
9394 * Returns zero if the change completed successfully, and either EINVAL or
9395 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9396 * of the virtual address range was not mapped, and ENOMEM is returned if
9397 * there was insufficient memory available to complete the change. In the
9398 * latter case, the memory type may have been changed on some part of the
9399 * virtual address range or the direct map.
9402 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9406 PMAP_LOCK(kernel_pmap);
9407 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9409 PMAP_UNLOCK(kernel_pmap);
9414 * Changes the specified virtual address range's protections to those
9415 * specified by "prot". Like pmap_change_attr(), protections for aliases
9416 * in the direct map are updated as well. Protections on aliasing mappings may
9417 * be a subset of the requested protections; for example, mappings in the direct
9418 * map are never executable.
9421 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9425 /* Only supported within the kernel map. */
9426 if (va < VM_MIN_KERNEL_ADDRESS)
9429 PMAP_LOCK(kernel_pmap);
9430 error = pmap_change_props_locked(va, size, prot, -1,
9431 MAPDEV_ASSERTVALID);
9432 PMAP_UNLOCK(kernel_pmap);
9437 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9438 int mode, int flags)
9440 vm_offset_t base, offset, tmpva;
9441 vm_paddr_t pa_start, pa_end, pa_end1;
9443 pd_entry_t *pde, pde_bits, pde_mask;
9444 pt_entry_t *pte, pte_bits, pte_mask;
9448 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9449 base = trunc_page(va);
9450 offset = va & PAGE_MASK;
9451 size = round_page(offset + size);
9454 * Only supported on kernel virtual addresses, including the direct
9455 * map but excluding the recursive map.
9457 if (base < DMAP_MIN_ADDRESS)
9461 * Construct our flag sets and masks. "bits" is the subset of
9462 * "mask" that will be set in each modified PTE.
9464 * Mappings in the direct map are never allowed to be executable.
9466 pde_bits = pte_bits = 0;
9467 pde_mask = pte_mask = 0;
9469 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9470 pde_mask |= X86_PG_PDE_CACHE;
9471 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9472 pte_mask |= X86_PG_PTE_CACHE;
9474 if (prot != VM_PROT_NONE) {
9475 if ((prot & VM_PROT_WRITE) != 0) {
9476 pde_bits |= X86_PG_RW;
9477 pte_bits |= X86_PG_RW;
9479 if ((prot & VM_PROT_EXECUTE) == 0 ||
9480 va < VM_MIN_KERNEL_ADDRESS) {
9484 pde_mask |= X86_PG_RW | pg_nx;
9485 pte_mask |= X86_PG_RW | pg_nx;
9489 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9490 * into 4KB pages if required.
9492 for (tmpva = base; tmpva < base + size; ) {
9493 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9494 if (pdpe == NULL || *pdpe == 0) {
9495 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9496 ("%s: addr %#lx is not mapped", __func__, tmpva));
9499 if (*pdpe & PG_PS) {
9501 * If the current 1GB page already has the required
9502 * properties, then we need not demote this page. Just
9503 * increment tmpva to the next 1GB page frame.
9505 if ((*pdpe & pde_mask) == pde_bits) {
9506 tmpva = trunc_1gpage(tmpva) + NBPDP;
9511 * If the current offset aligns with a 1GB page frame
9512 * and there is at least 1GB left within the range, then
9513 * we need not break down this page into 2MB pages.
9515 if ((tmpva & PDPMASK) == 0 &&
9516 tmpva + PDPMASK < base + size) {
9520 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9523 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9525 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9526 ("%s: addr %#lx is not mapped", __func__, tmpva));
9531 * If the current 2MB page already has the required
9532 * properties, then we need not demote this page. Just
9533 * increment tmpva to the next 2MB page frame.
9535 if ((*pde & pde_mask) == pde_bits) {
9536 tmpva = trunc_2mpage(tmpva) + NBPDR;
9541 * If the current offset aligns with a 2MB page frame
9542 * and there is at least 2MB left within the range, then
9543 * we need not break down this page into 4KB pages.
9545 if ((tmpva & PDRMASK) == 0 &&
9546 tmpva + PDRMASK < base + size) {
9550 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9553 pte = pmap_pde_to_pte(pde, tmpva);
9555 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9556 ("%s: addr %#lx is not mapped", __func__, tmpva));
9564 * Ok, all the pages exist, so run through them updating their
9565 * properties if required.
9568 pa_start = pa_end = 0;
9569 for (tmpva = base; tmpva < base + size; ) {
9570 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9571 if (*pdpe & PG_PS) {
9572 if ((*pdpe & pde_mask) != pde_bits) {
9573 pmap_pte_props(pdpe, pde_bits, pde_mask);
9576 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9577 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9578 if (pa_start == pa_end) {
9579 /* Start physical address run. */
9580 pa_start = *pdpe & PG_PS_FRAME;
9581 pa_end = pa_start + NBPDP;
9582 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9585 /* Run ended, update direct map. */
9586 error = pmap_change_props_locked(
9587 PHYS_TO_DMAP(pa_start),
9588 pa_end - pa_start, prot, mode,
9592 /* Start physical address run. */
9593 pa_start = *pdpe & PG_PS_FRAME;
9594 pa_end = pa_start + NBPDP;
9597 tmpva = trunc_1gpage(tmpva) + NBPDP;
9600 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9602 if ((*pde & pde_mask) != pde_bits) {
9603 pmap_pte_props(pde, pde_bits, pde_mask);
9606 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9607 (*pde & PG_PS_FRAME) < dmaplimit) {
9608 if (pa_start == pa_end) {
9609 /* Start physical address run. */
9610 pa_start = *pde & PG_PS_FRAME;
9611 pa_end = pa_start + NBPDR;
9612 } else if (pa_end == (*pde & PG_PS_FRAME))
9615 /* Run ended, update direct map. */
9616 error = pmap_change_props_locked(
9617 PHYS_TO_DMAP(pa_start),
9618 pa_end - pa_start, prot, mode,
9622 /* Start physical address run. */
9623 pa_start = *pde & PG_PS_FRAME;
9624 pa_end = pa_start + NBPDR;
9627 tmpva = trunc_2mpage(tmpva) + NBPDR;
9629 pte = pmap_pde_to_pte(pde, tmpva);
9630 if ((*pte & pte_mask) != pte_bits) {
9631 pmap_pte_props(pte, pte_bits, pte_mask);
9634 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9635 (*pte & PG_FRAME) < dmaplimit) {
9636 if (pa_start == pa_end) {
9637 /* Start physical address run. */
9638 pa_start = *pte & PG_FRAME;
9639 pa_end = pa_start + PAGE_SIZE;
9640 } else if (pa_end == (*pte & PG_FRAME))
9641 pa_end += PAGE_SIZE;
9643 /* Run ended, update direct map. */
9644 error = pmap_change_props_locked(
9645 PHYS_TO_DMAP(pa_start),
9646 pa_end - pa_start, prot, mode,
9650 /* Start physical address run. */
9651 pa_start = *pte & PG_FRAME;
9652 pa_end = pa_start + PAGE_SIZE;
9658 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9659 pa_end1 = MIN(pa_end, dmaplimit);
9660 if (pa_start != pa_end1)
9661 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9662 pa_end1 - pa_start, prot, mode, flags);
9666 * Flush CPU caches if required to make sure any data isn't cached that
9667 * shouldn't be, etc.
9670 pmap_invalidate_range(kernel_pmap, base, tmpva);
9671 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9672 pmap_invalidate_cache_range(base, tmpva);
9678 * Demotes any mapping within the direct map region that covers more than the
9679 * specified range of physical addresses. This range's size must be a power
9680 * of two and its starting address must be a multiple of its size. Since the
9681 * demotion does not change any attributes of the mapping, a TLB invalidation
9682 * is not mandatory. The caller may, however, request a TLB invalidation.
9685 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9694 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9695 KASSERT((base & (len - 1)) == 0,
9696 ("pmap_demote_DMAP: base is not a multiple of len"));
9697 if (len < NBPDP && base < dmaplimit) {
9698 va = PHYS_TO_DMAP(base);
9700 PMAP_LOCK(kernel_pmap);
9701 pdpe = pmap_pdpe(kernel_pmap, va);
9702 if ((*pdpe & X86_PG_V) == 0)
9703 panic("pmap_demote_DMAP: invalid PDPE");
9704 if ((*pdpe & PG_PS) != 0) {
9705 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9706 panic("pmap_demote_DMAP: PDPE failed");
9710 pde = pmap_pdpe_to_pde(pdpe, va);
9711 if ((*pde & X86_PG_V) == 0)
9712 panic("pmap_demote_DMAP: invalid PDE");
9713 if ((*pde & PG_PS) != 0) {
9714 if (!pmap_demote_pde(kernel_pmap, pde, va))
9715 panic("pmap_demote_DMAP: PDE failed");
9719 if (changed && invalidate)
9720 pmap_invalidate_page(kernel_pmap, va);
9721 PMAP_UNLOCK(kernel_pmap);
9726 * Perform the pmap work for mincore(2). If the page is not both referenced and
9727 * modified by this pmap, returns its physical address so that the caller can
9728 * find other mappings.
9731 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9735 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9739 PG_A = pmap_accessed_bit(pmap);
9740 PG_M = pmap_modified_bit(pmap);
9741 PG_V = pmap_valid_bit(pmap);
9742 PG_RW = pmap_rw_bit(pmap);
9748 pdpe = pmap_pdpe(pmap, addr);
9751 if ((*pdpe & PG_V) != 0) {
9752 if ((*pdpe & PG_PS) != 0) {
9754 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9756 val = MINCORE_PSIND(2);
9758 pdep = pmap_pde(pmap, addr);
9759 if (pdep != NULL && (*pdep & PG_V) != 0) {
9760 if ((*pdep & PG_PS) != 0) {
9762 /* Compute the physical address of the 4KB page. */
9763 pa = ((pte & PG_PS_FRAME) | (addr &
9764 PDRMASK)) & PG_FRAME;
9765 val = MINCORE_PSIND(1);
9767 pte = *pmap_pde_to_pte(pdep, addr);
9768 pa = pte & PG_FRAME;
9774 if ((pte & PG_V) != 0) {
9775 val |= MINCORE_INCORE;
9776 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9777 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9778 if ((pte & PG_A) != 0)
9779 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9781 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9782 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9783 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9792 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9794 uint32_t gen, new_gen, pcid_next;
9796 CRITICAL_ASSERT(curthread);
9797 gen = PCPU_GET(pcid_gen);
9798 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9799 return (pti ? 0 : CR3_PCID_SAVE);
9800 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9801 return (CR3_PCID_SAVE);
9802 pcid_next = PCPU_GET(pcid_next);
9803 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9804 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9805 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9806 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9807 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9811 PCPU_SET(pcid_gen, new_gen);
9812 pcid_next = PMAP_PCID_KERN + 1;
9816 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9817 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9818 PCPU_SET(pcid_next, pcid_next + 1);
9823 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9827 cached = pmap_pcid_alloc(pmap, cpuid);
9828 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9829 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9830 pmap->pm_pcids[cpuid].pm_pcid));
9831 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9832 pmap == kernel_pmap,
9833 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9834 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9839 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9842 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9843 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9847 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9850 uint64_t cached, cr3, kcr3, ucr3;
9852 KASSERT((read_rflags() & PSL_I) == 0,
9853 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9855 /* See the comment in pmap_invalidate_page_pcid(). */
9856 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9857 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9858 old_pmap = PCPU_GET(curpmap);
9859 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9860 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9863 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9865 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9866 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9867 PCPU_SET(curpmap, pmap);
9868 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9869 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9872 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9873 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9875 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9876 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9878 counter_u64_add(pcid_save_cnt, 1);
9880 pmap_activate_sw_pti_post(td, pmap);
9884 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9887 uint64_t cached, cr3;
9889 KASSERT((read_rflags() & PSL_I) == 0,
9890 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9892 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9894 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9895 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9897 PCPU_SET(curpmap, pmap);
9899 counter_u64_add(pcid_save_cnt, 1);
9903 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9904 u_int cpuid __unused)
9907 load_cr3(pmap->pm_cr3);
9908 PCPU_SET(curpmap, pmap);
9912 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9913 u_int cpuid __unused)
9916 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9917 PCPU_SET(kcr3, pmap->pm_cr3);
9918 PCPU_SET(ucr3, pmap->pm_ucr3);
9919 pmap_activate_sw_pti_post(td, pmap);
9922 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9926 if (pmap_pcid_enabled && pti)
9927 return (pmap_activate_sw_pcid_pti);
9928 else if (pmap_pcid_enabled && !pti)
9929 return (pmap_activate_sw_pcid_nopti);
9930 else if (!pmap_pcid_enabled && pti)
9931 return (pmap_activate_sw_nopcid_pti);
9932 else /* if (!pmap_pcid_enabled && !pti) */
9933 return (pmap_activate_sw_nopcid_nopti);
9937 pmap_activate_sw(struct thread *td)
9939 pmap_t oldpmap, pmap;
9942 oldpmap = PCPU_GET(curpmap);
9943 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9944 if (oldpmap == pmap) {
9945 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9949 cpuid = PCPU_GET(cpuid);
9951 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9953 CPU_SET(cpuid, &pmap->pm_active);
9955 pmap_activate_sw_mode(td, pmap, cpuid);
9957 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9959 CPU_CLR(cpuid, &oldpmap->pm_active);
9964 pmap_activate(struct thread *td)
9967 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9968 * invalidate_all IPI, which checks for curpmap ==
9969 * smp_tlb_pmap. The below sequence of operations has a
9970 * window where %CR3 is loaded with the new pmap's PML4
9971 * address, but the curpmap value has not yet been updated.
9972 * This causes the invltlb IPI handler, which is called
9973 * between the updates, to execute as a NOP, which leaves
9974 * stale TLB entries.
9976 * Note that the most common use of pmap_activate_sw(), from
9977 * a context switch, is immune to this race, because
9978 * interrupts are disabled (while the thread lock is owned),
9979 * so the IPI is delayed until after curpmap is updated. Protect
9980 * other callers in a similar way, by disabling interrupts
9981 * around the %cr3 register reload and curpmap assignment.
9984 pmap_activate_sw(td);
9989 pmap_activate_boot(pmap_t pmap)
9995 * kernel_pmap must be never deactivated, and we ensure that
9996 * by never activating it at all.
9998 MPASS(pmap != kernel_pmap);
10000 cpuid = PCPU_GET(cpuid);
10002 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
10004 CPU_SET(cpuid, &pmap->pm_active);
10006 PCPU_SET(curpmap, pmap);
10008 kcr3 = pmap->pm_cr3;
10009 if (pmap_pcid_enabled)
10010 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
10012 kcr3 = PMAP_NO_CR3;
10014 PCPU_SET(kcr3, kcr3);
10015 PCPU_SET(ucr3, PMAP_NO_CR3);
10019 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
10024 * Increase the starting virtual address of the given mapping if a
10025 * different alignment might result in more superpage mappings.
10028 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
10029 vm_offset_t *addr, vm_size_t size)
10031 vm_offset_t superpage_offset;
10035 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
10036 offset += ptoa(object->pg_color);
10037 superpage_offset = offset & PDRMASK;
10038 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
10039 (*addr & PDRMASK) == superpage_offset)
10041 if ((*addr & PDRMASK) < superpage_offset)
10042 *addr = (*addr & ~PDRMASK) + superpage_offset;
10044 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
10048 static unsigned long num_dirty_emulations;
10049 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
10050 &num_dirty_emulations, 0, NULL);
10052 static unsigned long num_accessed_emulations;
10053 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
10054 &num_accessed_emulations, 0, NULL);
10056 static unsigned long num_superpage_accessed_emulations;
10057 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
10058 &num_superpage_accessed_emulations, 0, NULL);
10060 static unsigned long ad_emulation_superpage_promotions;
10061 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
10062 &ad_emulation_superpage_promotions, 0, NULL);
10063 #endif /* INVARIANTS */
10066 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
10069 struct rwlock *lock;
10070 #if VM_NRESERVLEVEL > 0
10074 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
10076 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
10077 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
10079 if (!pmap_emulate_ad_bits(pmap))
10082 PG_A = pmap_accessed_bit(pmap);
10083 PG_M = pmap_modified_bit(pmap);
10084 PG_V = pmap_valid_bit(pmap);
10085 PG_RW = pmap_rw_bit(pmap);
10091 pde = pmap_pde(pmap, va);
10092 if (pde == NULL || (*pde & PG_V) == 0)
10095 if ((*pde & PG_PS) != 0) {
10096 if (ftype == VM_PROT_READ) {
10098 atomic_add_long(&num_superpage_accessed_emulations, 1);
10106 pte = pmap_pde_to_pte(pde, va);
10107 if ((*pte & PG_V) == 0)
10110 if (ftype == VM_PROT_WRITE) {
10111 if ((*pte & PG_RW) == 0)
10114 * Set the modified and accessed bits simultaneously.
10116 * Intel EPT PTEs that do software emulation of A/D bits map
10117 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
10118 * An EPT misconfiguration is triggered if the PTE is writable
10119 * but not readable (WR=10). This is avoided by setting PG_A
10120 * and PG_M simultaneously.
10122 *pte |= PG_M | PG_A;
10127 #if VM_NRESERVLEVEL > 0
10128 /* try to promote the mapping */
10129 if (va < VM_MAXUSER_ADDRESS)
10130 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
10134 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
10136 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
10137 pmap_ps_enabled(pmap) &&
10138 (m->flags & PG_FICTITIOUS) == 0 &&
10139 vm_reserv_level_iffullpop(m) == 0) {
10140 pmap_promote_pde(pmap, pde, va, &lock);
10142 atomic_add_long(&ad_emulation_superpage_promotions, 1);
10148 if (ftype == VM_PROT_WRITE)
10149 atomic_add_long(&num_dirty_emulations, 1);
10151 atomic_add_long(&num_accessed_emulations, 1);
10153 rv = 0; /* success */
10162 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
10164 pml4_entry_t *pml4;
10167 pt_entry_t *pte, PG_V;
10171 PG_V = pmap_valid_bit(pmap);
10174 pml4 = pmap_pml4e(pmap, va);
10177 ptr[idx++] = *pml4;
10178 if ((*pml4 & PG_V) == 0)
10181 pdp = pmap_pml4e_to_pdpe(pml4, va);
10183 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
10186 pde = pmap_pdpe_to_pde(pdp, va);
10188 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
10191 pte = pmap_pde_to_pte(pde, va);
10200 * Get the kernel virtual address of a set of physical pages. If there are
10201 * physical addresses not covered by the DMAP perform a transient mapping
10202 * that will be removed when calling pmap_unmap_io_transient.
10204 * \param page The pages the caller wishes to obtain the virtual
10205 * address on the kernel memory map.
10206 * \param vaddr On return contains the kernel virtual memory address
10207 * of the pages passed in the page parameter.
10208 * \param count Number of pages passed in.
10209 * \param can_fault TRUE if the thread using the mapped pages can take
10210 * page faults, FALSE otherwise.
10212 * \returns TRUE if the caller must call pmap_unmap_io_transient when
10213 * finished or FALSE otherwise.
10217 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10218 boolean_t can_fault)
10221 boolean_t needs_mapping;
10223 int cache_bits, error __unused, i;
10226 * Allocate any KVA space that we need, this is done in a separate
10227 * loop to prevent calling vmem_alloc while pinned.
10229 needs_mapping = FALSE;
10230 for (i = 0; i < count; i++) {
10231 paddr = VM_PAGE_TO_PHYS(page[i]);
10232 if (__predict_false(paddr >= dmaplimit)) {
10233 error = vmem_alloc(kernel_arena, PAGE_SIZE,
10234 M_BESTFIT | M_WAITOK, &vaddr[i]);
10235 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
10236 needs_mapping = TRUE;
10238 vaddr[i] = PHYS_TO_DMAP(paddr);
10242 /* Exit early if everything is covered by the DMAP */
10243 if (!needs_mapping)
10247 * NB: The sequence of updating a page table followed by accesses
10248 * to the corresponding pages used in the !DMAP case is subject to
10249 * the situation described in the "AMD64 Architecture Programmer's
10250 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
10251 * Coherency Considerations". Therefore, issuing the INVLPG right
10252 * after modifying the PTE bits is crucial.
10256 for (i = 0; i < count; i++) {
10257 paddr = VM_PAGE_TO_PHYS(page[i]);
10258 if (paddr >= dmaplimit) {
10261 * Slow path, since we can get page faults
10262 * while mappings are active don't pin the
10263 * thread to the CPU and instead add a global
10264 * mapping visible to all CPUs.
10266 pmap_qenter(vaddr[i], &page[i], 1);
10268 pte = vtopte(vaddr[i]);
10269 cache_bits = pmap_cache_bits(kernel_pmap,
10270 page[i]->md.pat_mode, 0);
10271 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
10278 return (needs_mapping);
10282 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10283 boolean_t can_fault)
10290 for (i = 0; i < count; i++) {
10291 paddr = VM_PAGE_TO_PHYS(page[i]);
10292 if (paddr >= dmaplimit) {
10294 pmap_qremove(vaddr[i], 1);
10295 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
10301 pmap_quick_enter_page(vm_page_t m)
10305 paddr = VM_PAGE_TO_PHYS(m);
10306 if (paddr < dmaplimit)
10307 return (PHYS_TO_DMAP(paddr));
10308 mtx_lock_spin(&qframe_mtx);
10309 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
10310 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
10311 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
10316 pmap_quick_remove_page(vm_offset_t addr)
10319 if (addr != qframe)
10321 pte_store(vtopte(qframe), 0);
10323 mtx_unlock_spin(&qframe_mtx);
10327 * Pdp pages from the large map are managed differently from either
10328 * kernel or user page table pages. They are permanently allocated at
10329 * initialization time, and their reference count is permanently set to
10330 * zero. The pml4 entries pointing to those pages are copied into
10331 * each allocated pmap.
10333 * In contrast, pd and pt pages are managed like user page table
10334 * pages. They are dynamically allocated, and their reference count
10335 * represents the number of valid entries within the page.
10338 pmap_large_map_getptp_unlocked(void)
10340 return (pmap_alloc_pt_page(kernel_pmap, 0,
10341 VM_ALLOC_NORMAL | VM_ALLOC_ZERO));
10345 pmap_large_map_getptp(void)
10349 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
10350 m = pmap_large_map_getptp_unlocked();
10352 PMAP_UNLOCK(kernel_pmap);
10354 PMAP_LOCK(kernel_pmap);
10355 /* Callers retry. */
10360 static pdp_entry_t *
10361 pmap_large_map_pdpe(vm_offset_t va)
10363 vm_pindex_t pml4_idx;
10366 pml4_idx = pmap_pml4e_index(va);
10367 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
10368 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
10370 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10371 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
10372 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
10373 "LMSPML4I %#jx lm_ents %d",
10374 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10375 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
10376 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
10379 static pd_entry_t *
10380 pmap_large_map_pde(vm_offset_t va)
10387 pdpe = pmap_large_map_pdpe(va);
10389 m = pmap_large_map_getptp();
10392 mphys = VM_PAGE_TO_PHYS(m);
10393 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10395 MPASS((*pdpe & X86_PG_PS) == 0);
10396 mphys = *pdpe & PG_FRAME;
10398 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10401 static pt_entry_t *
10402 pmap_large_map_pte(vm_offset_t va)
10409 pde = pmap_large_map_pde(va);
10411 m = pmap_large_map_getptp();
10414 mphys = VM_PAGE_TO_PHYS(m);
10415 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10416 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10418 MPASS((*pde & X86_PG_PS) == 0);
10419 mphys = *pde & PG_FRAME;
10421 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10425 pmap_large_map_kextract(vm_offset_t va)
10427 pdp_entry_t *pdpe, pdp;
10428 pd_entry_t *pde, pd;
10429 pt_entry_t *pte, pt;
10431 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10432 ("not largemap range %#lx", (u_long)va));
10433 pdpe = pmap_large_map_pdpe(va);
10435 KASSERT((pdp & X86_PG_V) != 0,
10436 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10437 (u_long)pdpe, pdp));
10438 if ((pdp & X86_PG_PS) != 0) {
10439 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10440 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10441 (u_long)pdpe, pdp));
10442 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10444 pde = pmap_pdpe_to_pde(pdpe, va);
10446 KASSERT((pd & X86_PG_V) != 0,
10447 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10448 if ((pd & X86_PG_PS) != 0)
10449 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10450 pte = pmap_pde_to_pte(pde, va);
10452 KASSERT((pt & X86_PG_V) != 0,
10453 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10454 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10458 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10459 vmem_addr_t *vmem_res)
10463 * Large mappings are all but static. Consequently, there
10464 * is no point in waiting for an earlier allocation to be
10467 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10468 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10472 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10473 vm_memattr_t mattr)
10478 vm_offset_t va, inc;
10479 vmem_addr_t vmem_res;
10483 if (len == 0 || spa + len < spa)
10486 /* See if DMAP can serve. */
10487 if (spa + len <= dmaplimit) {
10488 va = PHYS_TO_DMAP(spa);
10489 *addr = (void *)va;
10490 return (pmap_change_attr(va, len, mattr));
10494 * No, allocate KVA. Fit the address with best possible
10495 * alignment for superpages. Fall back to worse align if
10499 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10500 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10501 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10503 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10505 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10508 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10513 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10514 * in the pagetable to minimize flushing. No need to
10515 * invalidate TLB, since we only update invalid entries.
10517 PMAP_LOCK(kernel_pmap);
10518 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10520 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10521 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10522 pdpe = pmap_large_map_pdpe(va);
10524 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10525 X86_PG_V | X86_PG_A | pg_nx |
10526 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10528 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10529 (va & PDRMASK) == 0) {
10530 pde = pmap_large_map_pde(va);
10532 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10533 X86_PG_V | X86_PG_A | pg_nx |
10534 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10535 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10539 pte = pmap_large_map_pte(va);
10541 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10542 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10544 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10549 PMAP_UNLOCK(kernel_pmap);
10552 *addr = (void *)vmem_res;
10557 pmap_large_unmap(void *svaa, vm_size_t len)
10559 vm_offset_t sva, va;
10561 pdp_entry_t *pdpe, pdp;
10562 pd_entry_t *pde, pd;
10565 struct spglist spgf;
10567 sva = (vm_offset_t)svaa;
10568 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10569 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10573 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10574 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10575 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10576 PMAP_LOCK(kernel_pmap);
10577 for (va = sva; va < sva + len; va += inc) {
10578 pdpe = pmap_large_map_pdpe(va);
10580 KASSERT((pdp & X86_PG_V) != 0,
10581 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10582 (u_long)pdpe, pdp));
10583 if ((pdp & X86_PG_PS) != 0) {
10584 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10585 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10586 (u_long)pdpe, pdp));
10587 KASSERT((va & PDPMASK) == 0,
10588 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10589 (u_long)pdpe, pdp));
10590 KASSERT(va + NBPDP <= sva + len,
10591 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10592 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10593 (u_long)pdpe, pdp, len));
10598 pde = pmap_pdpe_to_pde(pdpe, va);
10600 KASSERT((pd & X86_PG_V) != 0,
10601 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10603 if ((pd & X86_PG_PS) != 0) {
10604 KASSERT((va & PDRMASK) == 0,
10605 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10607 KASSERT(va + NBPDR <= sva + len,
10608 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10609 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10613 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10615 if (m->ref_count == 0) {
10617 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10621 pte = pmap_pde_to_pte(pde, va);
10622 KASSERT((*pte & X86_PG_V) != 0,
10623 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10624 (u_long)pte, *pte));
10627 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10629 if (m->ref_count == 0) {
10631 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10632 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10634 if (m->ref_count == 0) {
10636 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10640 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10641 PMAP_UNLOCK(kernel_pmap);
10642 vm_page_free_pages_toq(&spgf, false);
10643 vmem_free(large_vmem, sva, len);
10647 pmap_large_map_wb_fence_mfence(void)
10654 pmap_large_map_wb_fence_atomic(void)
10657 atomic_thread_fence_seq_cst();
10661 pmap_large_map_wb_fence_nop(void)
10665 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10668 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10669 return (pmap_large_map_wb_fence_mfence);
10670 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10671 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10672 return (pmap_large_map_wb_fence_atomic);
10674 /* clflush is strongly enough ordered */
10675 return (pmap_large_map_wb_fence_nop);
10679 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10682 for (; len > 0; len -= cpu_clflush_line_size,
10683 va += cpu_clflush_line_size)
10688 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10691 for (; len > 0; len -= cpu_clflush_line_size,
10692 va += cpu_clflush_line_size)
10697 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10700 for (; len > 0; len -= cpu_clflush_line_size,
10701 va += cpu_clflush_line_size)
10706 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10710 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10713 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10714 return (pmap_large_map_flush_range_clwb);
10715 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10716 return (pmap_large_map_flush_range_clflushopt);
10717 else if ((cpu_feature & CPUID_CLFSH) != 0)
10718 return (pmap_large_map_flush_range_clflush);
10720 return (pmap_large_map_flush_range_nop);
10724 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10726 volatile u_long *pe;
10732 for (va = sva; va < eva; va += inc) {
10734 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10735 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10737 if ((p & X86_PG_PS) != 0)
10741 pe = (volatile u_long *)pmap_large_map_pde(va);
10743 if ((p & X86_PG_PS) != 0)
10747 pe = (volatile u_long *)pmap_large_map_pte(va);
10751 seen_other = false;
10753 if ((p & X86_PG_AVAIL1) != 0) {
10755 * Spin-wait for the end of a parallel
10762 * If we saw other write-back
10763 * occuring, we cannot rely on PG_M to
10764 * indicate state of the cache. The
10765 * PG_M bit is cleared before the
10766 * flush to avoid ignoring new writes,
10767 * and writes which are relevant for
10768 * us might happen after.
10774 if ((p & X86_PG_M) != 0 || seen_other) {
10775 if (!atomic_fcmpset_long(pe, &p,
10776 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10778 * If we saw PG_M without
10779 * PG_AVAIL1, and then on the
10780 * next attempt we do not
10781 * observe either PG_M or
10782 * PG_AVAIL1, the other
10783 * write-back started after us
10784 * and finished before us. We
10785 * can rely on it doing our
10789 pmap_large_map_flush_range(va, inc);
10790 atomic_clear_long(pe, X86_PG_AVAIL1);
10799 * Write-back cache lines for the given address range.
10801 * Must be called only on the range or sub-range returned from
10802 * pmap_large_map(). Must not be called on the coalesced ranges.
10804 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10805 * instructions support.
10808 pmap_large_map_wb(void *svap, vm_size_t len)
10810 vm_offset_t eva, sva;
10812 sva = (vm_offset_t)svap;
10814 pmap_large_map_wb_fence();
10815 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10816 pmap_large_map_flush_range(sva, len);
10818 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10819 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10820 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10821 pmap_large_map_wb_large(sva, eva);
10823 pmap_large_map_wb_fence();
10827 pmap_pti_alloc_page(void)
10831 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10832 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10833 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10838 pmap_pti_free_page(vm_page_t m)
10841 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10842 if (!vm_page_unwire_noq(m))
10844 vm_page_free_zero(m);
10849 pmap_pti_init(void)
10858 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10859 VM_OBJECT_WLOCK(pti_obj);
10860 pml4_pg = pmap_pti_alloc_page();
10861 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10862 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10863 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10864 pdpe = pmap_pti_pdpe(va);
10865 pmap_pti_wire_pte(pdpe);
10867 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10868 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10869 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10870 sizeof(struct gate_descriptor) * NIDT, false);
10872 /* Doublefault stack IST 1 */
10873 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10874 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10875 /* NMI stack IST 2 */
10876 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10877 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10878 /* MC# stack IST 3 */
10879 va = __pcpu[i].pc_common_tss.tss_ist3 +
10880 sizeof(struct nmi_pcpu);
10881 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10882 /* DB# stack IST 4 */
10883 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10884 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10886 pmap_pti_add_kva_locked((vm_offset_t)KERNSTART, (vm_offset_t)etext,
10888 pti_finalized = true;
10889 VM_OBJECT_WUNLOCK(pti_obj);
10891 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10893 static pdp_entry_t *
10894 pmap_pti_pdpe(vm_offset_t va)
10896 pml4_entry_t *pml4e;
10899 vm_pindex_t pml4_idx;
10902 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10904 pml4_idx = pmap_pml4e_index(va);
10905 pml4e = &pti_pml4[pml4_idx];
10909 panic("pml4 alloc after finalization\n");
10910 m = pmap_pti_alloc_page();
10912 pmap_pti_free_page(m);
10913 mphys = *pml4e & ~PAGE_MASK;
10915 mphys = VM_PAGE_TO_PHYS(m);
10916 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10919 mphys = *pml4e & ~PAGE_MASK;
10921 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10926 pmap_pti_wire_pte(void *pte)
10930 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10931 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10936 pmap_pti_unwire_pde(void *pde, bool only_ref)
10940 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10941 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10942 MPASS(m->ref_count > 0);
10943 MPASS(only_ref || m->ref_count > 1);
10944 pmap_pti_free_page(m);
10948 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10953 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10954 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10955 MPASS(m->ref_count > 0);
10956 if (pmap_pti_free_page(m)) {
10957 pde = pmap_pti_pde(va);
10958 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10960 pmap_pti_unwire_pde(pde, false);
10964 static pd_entry_t *
10965 pmap_pti_pde(vm_offset_t va)
10970 vm_pindex_t pd_idx;
10973 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10975 pdpe = pmap_pti_pdpe(va);
10977 m = pmap_pti_alloc_page();
10979 pmap_pti_free_page(m);
10980 MPASS((*pdpe & X86_PG_PS) == 0);
10981 mphys = *pdpe & ~PAGE_MASK;
10983 mphys = VM_PAGE_TO_PHYS(m);
10984 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10987 MPASS((*pdpe & X86_PG_PS) == 0);
10988 mphys = *pdpe & ~PAGE_MASK;
10991 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10992 pd_idx = pmap_pde_index(va);
10997 static pt_entry_t *
10998 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
11005 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
11007 pde = pmap_pti_pde(va);
11008 if (unwire_pde != NULL) {
11009 *unwire_pde = true;
11010 pmap_pti_wire_pte(pde);
11013 m = pmap_pti_alloc_page();
11015 pmap_pti_free_page(m);
11016 MPASS((*pde & X86_PG_PS) == 0);
11017 mphys = *pde & ~(PAGE_MASK | pg_nx);
11019 mphys = VM_PAGE_TO_PHYS(m);
11020 *pde = mphys | X86_PG_RW | X86_PG_V;
11021 if (unwire_pde != NULL)
11022 *unwire_pde = false;
11025 MPASS((*pde & X86_PG_PS) == 0);
11026 mphys = *pde & ~(PAGE_MASK | pg_nx);
11029 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
11030 pte += pmap_pte_index(va);
11036 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
11040 pt_entry_t *pte, ptev;
11043 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
11045 sva = trunc_page(sva);
11046 MPASS(sva > VM_MAXUSER_ADDRESS);
11047 eva = round_page(eva);
11049 for (; sva < eva; sva += PAGE_SIZE) {
11050 pte = pmap_pti_pte(sva, &unwire_pde);
11051 pa = pmap_kextract(sva);
11052 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
11053 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
11054 VM_MEMATTR_DEFAULT, FALSE);
11056 pte_store(pte, ptev);
11057 pmap_pti_wire_pte(pte);
11059 KASSERT(!pti_finalized,
11060 ("pti overlap after fin %#lx %#lx %#lx",
11062 KASSERT(*pte == ptev,
11063 ("pti non-identical pte after fin %#lx %#lx %#lx",
11067 pde = pmap_pti_pde(sva);
11068 pmap_pti_unwire_pde(pde, true);
11074 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
11079 VM_OBJECT_WLOCK(pti_obj);
11080 pmap_pti_add_kva_locked(sva, eva, exec);
11081 VM_OBJECT_WUNLOCK(pti_obj);
11085 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
11092 sva = rounddown2(sva, PAGE_SIZE);
11093 MPASS(sva > VM_MAXUSER_ADDRESS);
11094 eva = roundup2(eva, PAGE_SIZE);
11096 VM_OBJECT_WLOCK(pti_obj);
11097 for (va = sva; va < eva; va += PAGE_SIZE) {
11098 pte = pmap_pti_pte(va, NULL);
11099 KASSERT((*pte & X86_PG_V) != 0,
11100 ("invalid pte va %#lx pte %#lx pt %#lx", va,
11101 (u_long)pte, *pte));
11103 pmap_pti_unwire_pte(pte, va);
11105 pmap_invalidate_range(kernel_pmap, sva, eva);
11106 VM_OBJECT_WUNLOCK(pti_obj);
11110 pkru_dup_range(void *ctx __unused, void *data)
11112 struct pmap_pkru_range *node, *new_node;
11114 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11115 if (new_node == NULL)
11118 memcpy(new_node, node, sizeof(*node));
11123 pkru_free_range(void *ctx __unused, void *node)
11126 uma_zfree(pmap_pkru_ranges_zone, node);
11130 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11133 struct pmap_pkru_range *ppr;
11136 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11137 MPASS(pmap->pm_type == PT_X86);
11138 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11139 if ((flags & AMD64_PKRU_EXCL) != 0 &&
11140 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
11142 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11145 ppr->pkru_keyidx = keyidx;
11146 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
11147 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
11149 uma_zfree(pmap_pkru_ranges_zone, ppr);
11154 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11157 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11158 MPASS(pmap->pm_type == PT_X86);
11159 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11160 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
11164 pmap_pkru_deassign_all(pmap_t pmap)
11167 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11168 if (pmap->pm_type == PT_X86 &&
11169 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
11170 rangeset_remove_all(&pmap->pm_pkru);
11174 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11176 struct pmap_pkru_range *ppr, *prev_ppr;
11179 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11180 if (pmap->pm_type != PT_X86 ||
11181 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11182 sva >= VM_MAXUSER_ADDRESS)
11184 MPASS(eva <= VM_MAXUSER_ADDRESS);
11185 for (va = sva; va < eva; prev_ppr = ppr) {
11186 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11189 else if ((ppr == NULL) ^ (prev_ppr == NULL))
11195 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
11197 va = ppr->pkru_rs_el.re_end;
11203 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
11205 struct pmap_pkru_range *ppr;
11207 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11208 if (pmap->pm_type != PT_X86 ||
11209 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11210 va >= VM_MAXUSER_ADDRESS)
11212 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11214 return (X86_PG_PKU(ppr->pkru_keyidx));
11219 pred_pkru_on_remove(void *ctx __unused, void *r)
11221 struct pmap_pkru_range *ppr;
11224 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
11228 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11231 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11232 if (pmap->pm_type == PT_X86 &&
11233 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
11234 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
11235 pred_pkru_on_remove);
11240 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
11243 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
11244 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
11245 MPASS(dst_pmap->pm_type == PT_X86);
11246 MPASS(src_pmap->pm_type == PT_X86);
11247 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11248 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
11250 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
11254 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11257 pml4_entry_t *pml4e;
11259 pd_entry_t newpde, ptpaddr, *pde;
11260 pt_entry_t newpte, *ptep, pte;
11261 vm_offset_t va, va_next;
11264 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11265 MPASS(pmap->pm_type == PT_X86);
11266 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
11268 for (changed = false, va = sva; va < eva; va = va_next) {
11269 pml4e = pmap_pml4e(pmap, va);
11270 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
11271 va_next = (va + NBPML4) & ~PML4MASK;
11277 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
11278 if ((*pdpe & X86_PG_V) == 0) {
11279 va_next = (va + NBPDP) & ~PDPMASK;
11285 va_next = (va + NBPDR) & ~PDRMASK;
11289 pde = pmap_pdpe_to_pde(pdpe, va);
11294 MPASS((ptpaddr & X86_PG_V) != 0);
11295 if ((ptpaddr & PG_PS) != 0) {
11296 if (va + NBPDR == va_next && eva >= va_next) {
11297 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
11298 X86_PG_PKU(keyidx);
11299 if (newpde != ptpaddr) {
11304 } else if (!pmap_demote_pde(pmap, pde, va)) {
11312 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
11313 ptep++, va += PAGE_SIZE) {
11315 if ((pte & X86_PG_V) == 0)
11317 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
11318 if (newpte != pte) {
11325 pmap_invalidate_range(pmap, sva, eva);
11329 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11330 u_int keyidx, int flags)
11333 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
11334 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
11336 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
11338 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
11344 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11349 sva = trunc_page(sva);
11350 eva = round_page(eva);
11351 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
11356 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
11358 pmap_pkru_update_range(pmap, sva, eva, keyidx);
11360 if (error != ENOMEM)
11368 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11372 sva = trunc_page(sva);
11373 eva = round_page(eva);
11374 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
11379 error = pmap_pkru_deassign(pmap, sva, eva);
11381 pmap_pkru_update_range(pmap, sva, eva, 0);
11383 if (error != ENOMEM)
11392 pmap_kasan_enter_alloc_4k(void)
11396 m = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
11397 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
11399 panic("%s: no memory to grow shadow map", __func__);
11400 if ((m->flags & PG_ZERO) == 0)
11406 pmap_kasan_enter_alloc_2m(void)
11410 m = vm_page_alloc_contig(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
11411 VM_ALLOC_WIRED, NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT);
11413 memset((void *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), 0, NBPDR);
11418 * Grow the shadow map by at least one 4KB page at the specified address. Use
11419 * 2MB pages when possible.
11422 pmap_kasan_enter(vm_offset_t va)
11429 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11431 pdpe = pmap_pdpe(kernel_pmap, va);
11432 if ((*pdpe & X86_PG_V) == 0) {
11433 m = pmap_kasan_enter_alloc_4k();
11434 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11437 pde = pmap_pdpe_to_pde(pdpe, va);
11438 if ((*pde & X86_PG_V) == 0) {
11439 m = pmap_kasan_enter_alloc_2m();
11441 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11442 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx);
11444 m = pmap_kasan_enter_alloc_4k();
11445 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11449 if ((*pde & X86_PG_PS) != 0)
11451 pte = pmap_pde_to_pte(pde, va);
11452 if ((*pte & X86_PG_V) != 0)
11454 m = pmap_kasan_enter_alloc_4k();
11455 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11456 X86_PG_M | X86_PG_A | pg_nx);
11462 pmap_kmsan_enter_alloc_4k(void)
11466 m = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
11467 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
11469 panic("%s: no memory to grow shadow map", __func__);
11470 if ((m->flags & PG_ZERO) == 0)
11476 pmap_kmsan_enter_alloc_2m(void)
11480 m = vm_page_alloc_contig(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
11481 VM_ALLOC_WIRED, NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT);
11483 memset((void *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), 0, NBPDR);
11488 * Grow the shadow or origin maps by at least one 4KB page at the specified
11489 * address. Use 2MB pages when possible.
11492 pmap_kmsan_enter(vm_offset_t va)
11499 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11501 pdpe = pmap_pdpe(kernel_pmap, va);
11502 if ((*pdpe & X86_PG_V) == 0) {
11503 m = pmap_kmsan_enter_alloc_4k();
11504 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11507 pde = pmap_pdpe_to_pde(pdpe, va);
11508 if ((*pde & X86_PG_V) == 0) {
11509 m = pmap_kmsan_enter_alloc_2m();
11511 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11512 X86_PG_PS | X86_PG_V | X86_PG_A | X86_PG_M | pg_nx);
11514 m = pmap_kmsan_enter_alloc_4k();
11515 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11519 if ((*pde & X86_PG_PS) != 0)
11521 pte = pmap_pde_to_pte(pde, va);
11522 if ((*pte & X86_PG_V) != 0)
11524 m = pmap_kmsan_enter_alloc_4k();
11525 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11526 X86_PG_M | X86_PG_A | pg_nx);
11531 * Track a range of the kernel's virtual address space that is contiguous
11532 * in various mapping attributes.
11534 struct pmap_kernel_map_range {
11543 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11549 if (eva <= range->sva)
11552 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11553 for (i = 0; i < PAT_INDEX_SIZE; i++)
11554 if (pat_index[i] == pat_idx)
11558 case PAT_WRITE_BACK:
11561 case PAT_WRITE_THROUGH:
11564 case PAT_UNCACHEABLE:
11570 case PAT_WRITE_PROTECTED:
11573 case PAT_WRITE_COMBINING:
11577 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11578 __func__, pat_idx, range->sva, eva);
11583 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11585 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11586 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11587 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11588 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11589 mode, range->pdpes, range->pdes, range->ptes);
11591 /* Reset to sentinel value. */
11592 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11593 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11594 NPDEPG - 1, NPTEPG - 1);
11598 * Determine whether the attributes specified by a page table entry match those
11599 * being tracked by the current range. This is not quite as simple as a direct
11600 * flag comparison since some PAT modes have multiple representations.
11603 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11605 pt_entry_t diff, mask;
11607 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11608 diff = (range->attrs ^ attrs) & mask;
11611 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11612 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11613 pmap_pat_index(kernel_pmap, attrs, true))
11619 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11623 memset(range, 0, sizeof(*range));
11625 range->attrs = attrs;
11629 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11630 * those of the current run, dump the address range and its attributes, and
11634 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11635 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11640 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11642 attrs |= pdpe & pg_nx;
11643 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11644 if ((pdpe & PG_PS) != 0) {
11645 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11646 } else if (pde != 0) {
11647 attrs |= pde & pg_nx;
11648 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11650 if ((pde & PG_PS) != 0) {
11651 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11652 } else if (pte != 0) {
11653 attrs |= pte & pg_nx;
11654 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11655 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11657 /* Canonicalize by always using the PDE PAT bit. */
11658 if ((attrs & X86_PG_PTE_PAT) != 0)
11659 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11662 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11663 sysctl_kmaps_dump(sb, range, va);
11664 sysctl_kmaps_reinit(range, va, attrs);
11669 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11671 struct pmap_kernel_map_range range;
11672 struct sbuf sbuf, *sb;
11673 pml4_entry_t pml4e;
11674 pdp_entry_t *pdp, pdpe;
11675 pd_entry_t *pd, pde;
11676 pt_entry_t *pt, pte;
11679 int error, i, j, k, l;
11681 error = sysctl_wire_old_buffer(req, 0);
11685 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11687 /* Sentinel value. */
11688 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11689 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11690 NPDEPG - 1, NPTEPG - 1);
11693 * Iterate over the kernel page tables without holding the kernel pmap
11694 * lock. Outside of the large map, kernel page table pages are never
11695 * freed, so at worst we will observe inconsistencies in the output.
11696 * Within the large map, ensure that PDP and PD page addresses are
11697 * valid before descending.
11699 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11702 sbuf_printf(sb, "\nRecursive map:\n");
11705 sbuf_printf(sb, "\nDirect map:\n");
11709 sbuf_printf(sb, "\nKASAN shadow map:\n");
11713 case KMSANSHADPML4I:
11714 sbuf_printf(sb, "\nKMSAN shadow map:\n");
11716 case KMSANORIGPML4I:
11717 sbuf_printf(sb, "\nKMSAN origin map:\n");
11721 sbuf_printf(sb, "\nKernel map:\n");
11724 sbuf_printf(sb, "\nLarge map:\n");
11728 /* Convert to canonical form. */
11729 if (sva == 1ul << 47)
11733 pml4e = kernel_pml4[i];
11734 if ((pml4e & X86_PG_V) == 0) {
11735 sva = rounddown2(sva, NBPML4);
11736 sysctl_kmaps_dump(sb, &range, sva);
11740 pa = pml4e & PG_FRAME;
11741 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11743 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11745 if ((pdpe & X86_PG_V) == 0) {
11746 sva = rounddown2(sva, NBPDP);
11747 sysctl_kmaps_dump(sb, &range, sva);
11751 pa = pdpe & PG_FRAME;
11752 if ((pdpe & PG_PS) != 0) {
11753 sva = rounddown2(sva, NBPDP);
11754 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11760 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11761 vm_phys_paddr_to_vm_page(pa) == NULL) {
11763 * Page table pages for the large map may be
11764 * freed. Validate the next-level address
11765 * before descending.
11769 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11771 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11773 if ((pde & X86_PG_V) == 0) {
11774 sva = rounddown2(sva, NBPDR);
11775 sysctl_kmaps_dump(sb, &range, sva);
11779 pa = pde & PG_FRAME;
11780 if ((pde & PG_PS) != 0) {
11781 sva = rounddown2(sva, NBPDR);
11782 sysctl_kmaps_check(sb, &range, sva,
11783 pml4e, pdpe, pde, 0);
11788 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11789 vm_phys_paddr_to_vm_page(pa) == NULL) {
11791 * Page table pages for the large map
11792 * may be freed. Validate the
11793 * next-level address before descending.
11797 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11799 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11800 sva += PAGE_SIZE) {
11802 if ((pte & X86_PG_V) == 0) {
11803 sysctl_kmaps_dump(sb, &range,
11807 sysctl_kmaps_check(sb, &range, sva,
11808 pml4e, pdpe, pde, pte);
11815 error = sbuf_finish(sb);
11819 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11820 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
11821 NULL, 0, sysctl_kmaps, "A",
11822 "Dump kernel address layout");
11825 DB_SHOW_COMMAND(pte, pmap_print_pte)
11828 pml5_entry_t *pml5;
11829 pml4_entry_t *pml4;
11832 pt_entry_t *pte, PG_V;
11836 db_printf("show pte addr\n");
11839 va = (vm_offset_t)addr;
11841 if (kdb_thread != NULL)
11842 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11844 pmap = PCPU_GET(curpmap);
11846 PG_V = pmap_valid_bit(pmap);
11847 db_printf("VA 0x%016lx", va);
11849 if (pmap_is_la57(pmap)) {
11850 pml5 = pmap_pml5e(pmap, va);
11851 db_printf(" pml5e 0x%016lx", *pml5);
11852 if ((*pml5 & PG_V) == 0) {
11856 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11858 pml4 = pmap_pml4e(pmap, va);
11860 db_printf(" pml4e 0x%016lx", *pml4);
11861 if ((*pml4 & PG_V) == 0) {
11865 pdp = pmap_pml4e_to_pdpe(pml4, va);
11866 db_printf(" pdpe 0x%016lx", *pdp);
11867 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11871 pde = pmap_pdpe_to_pde(pdp, va);
11872 db_printf(" pde 0x%016lx", *pde);
11873 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11877 pte = pmap_pde_to_pte(pde, va);
11878 db_printf(" pte 0x%016lx\n", *pte);
11881 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11886 a = (vm_paddr_t)addr;
11887 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11889 db_printf("show phys2dmap addr\n");
11894 ptpages_show_page(int level, int idx, vm_page_t pg)
11896 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11897 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11901 ptpages_show_complain(int level, int idx, uint64_t pte)
11903 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11907 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11909 vm_page_t pg3, pg2, pg1;
11910 pml4_entry_t *pml4;
11915 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11916 for (i4 = 0; i4 < num_entries; i4++) {
11917 if ((pml4[i4] & PG_V) == 0)
11919 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11921 ptpages_show_complain(3, i4, pml4[i4]);
11924 ptpages_show_page(3, i4, pg3);
11925 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11926 for (i3 = 0; i3 < NPDPEPG; i3++) {
11927 if ((pdp[i3] & PG_V) == 0)
11929 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11931 ptpages_show_complain(2, i3, pdp[i3]);
11934 ptpages_show_page(2, i3, pg2);
11935 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11936 for (i2 = 0; i2 < NPDEPG; i2++) {
11937 if ((pd[i2] & PG_V) == 0)
11939 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11941 ptpages_show_complain(1, i2, pd[i2]);
11944 ptpages_show_page(1, i2, pg1);
11950 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11954 pml5_entry_t *pml5;
11959 pmap = (pmap_t)addr;
11961 pmap = PCPU_GET(curpmap);
11963 PG_V = pmap_valid_bit(pmap);
11965 if (pmap_is_la57(pmap)) {
11966 pml5 = pmap->pm_pmltop;
11967 for (i5 = 0; i5 < NUPML5E; i5++) {
11968 if ((pml5[i5] & PG_V) == 0)
11970 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11972 ptpages_show_complain(4, i5, pml5[i5]);
11975 ptpages_show_page(4, i5, pg);
11976 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11979 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11980 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);