2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
130 #include <sys/turnstile.h>
131 #include <sys/vmem.h>
132 #include <sys/vmmeter.h>
133 #include <sys/sched.h>
134 #include <sys/sysctl.h>
142 #include <vm/vm_param.h>
143 #include <vm/vm_kern.h>
144 #include <vm/vm_page.h>
145 #include <vm/vm_map.h>
146 #include <vm/vm_object.h>
147 #include <vm/vm_extern.h>
148 #include <vm/vm_pageout.h>
149 #include <vm/vm_pager.h>
150 #include <vm/vm_phys.h>
151 #include <vm/vm_radix.h>
152 #include <vm/vm_reserv.h>
153 #include <vm/vm_dumpset.h>
156 #include <machine/intr_machdep.h>
157 #include <x86/apicvar.h>
158 #include <x86/ifunc.h>
159 #include <machine/cpu.h>
160 #include <machine/cputypes.h>
161 #include <machine/intr_machdep.h>
162 #include <machine/md_var.h>
163 #include <machine/pcb.h>
164 #include <machine/specialreg.h>
166 #include <machine/smp.h>
168 #include <machine/sysarch.h>
169 #include <machine/tss.h>
172 #define PMAP_MEMDOM MAXMEMDOM
174 #define PMAP_MEMDOM 1
177 static __inline boolean_t
178 pmap_type_guest(pmap_t pmap)
181 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
184 static __inline boolean_t
185 pmap_emulate_ad_bits(pmap_t pmap)
188 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
191 static __inline pt_entry_t
192 pmap_valid_bit(pmap_t pmap)
196 switch (pmap->pm_type) {
202 if (pmap_emulate_ad_bits(pmap))
203 mask = EPT_PG_EMUL_V;
208 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
214 static __inline pt_entry_t
215 pmap_rw_bit(pmap_t pmap)
219 switch (pmap->pm_type) {
225 if (pmap_emulate_ad_bits(pmap))
226 mask = EPT_PG_EMUL_RW;
231 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
237 static pt_entry_t pg_g;
239 static __inline pt_entry_t
240 pmap_global_bit(pmap_t pmap)
244 switch (pmap->pm_type) {
253 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
259 static __inline pt_entry_t
260 pmap_accessed_bit(pmap_t pmap)
264 switch (pmap->pm_type) {
270 if (pmap_emulate_ad_bits(pmap))
276 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
282 static __inline pt_entry_t
283 pmap_modified_bit(pmap_t pmap)
287 switch (pmap->pm_type) {
293 if (pmap_emulate_ad_bits(pmap))
299 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
305 static __inline pt_entry_t
306 pmap_pku_mask_bit(pmap_t pmap)
309 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
312 #if !defined(DIAGNOSTIC)
313 #ifdef __GNUC_GNU_INLINE__
314 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
316 #define PMAP_INLINE extern inline
323 #define PV_STAT(x) do { x ; } while (0)
325 #define PV_STAT(x) do { } while (0)
330 #define pa_index(pa) ({ \
331 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
332 ("address %lx beyond the last segment", (pa))); \
335 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
336 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
337 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
338 struct rwlock *_lock; \
339 if (__predict_false((pa) > pmap_last_pa)) \
340 _lock = &pv_dummy_large.pv_lock; \
342 _lock = &(pa_to_pmdp(pa)->pv_lock); \
346 #define pa_index(pa) ((pa) >> PDRSHIFT)
347 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
349 #define NPV_LIST_LOCKS MAXCPU
351 #define PHYS_TO_PV_LIST_LOCK(pa) \
352 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
355 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
356 struct rwlock **_lockp = (lockp); \
357 struct rwlock *_new_lock; \
359 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
360 if (_new_lock != *_lockp) { \
361 if (*_lockp != NULL) \
362 rw_wunlock(*_lockp); \
363 *_lockp = _new_lock; \
368 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
369 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
371 #define RELEASE_PV_LIST_LOCK(lockp) do { \
372 struct rwlock **_lockp = (lockp); \
374 if (*_lockp != NULL) { \
375 rw_wunlock(*_lockp); \
380 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
381 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
383 struct pmap kernel_pmap_store;
385 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
386 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
389 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
390 "Number of kernel page table pages allocated on bootup");
393 vm_paddr_t dmaplimit;
394 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
397 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
398 "VM/pmap parameters");
400 static int pg_ps_enabled = 1;
401 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
402 &pg_ps_enabled, 0, "Are large page mappings enabled?");
404 int __read_frequently la57 = 0;
405 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
407 "5-level paging for host is enabled");
410 pmap_is_la57(pmap_t pmap)
412 if (pmap->pm_type == PT_X86)
414 return (false); /* XXXKIB handle EPT */
417 #define PAT_INDEX_SIZE 8
418 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
420 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
421 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
422 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
423 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
424 u_int64_t KPML5phys; /* phys addr of kernel level 5,
427 static pml4_entry_t *kernel_pml4;
428 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
429 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
430 static int ndmpdpphys; /* number of DMPDPphys pages */
432 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
435 * pmap_mapdev support pre initialization (i.e. console)
437 #define PMAP_PREINIT_MAPPING_COUNT 8
438 static struct pmap_preinit_mapping {
443 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
444 static int pmap_initialized;
447 * Data for the pv entry allocation mechanism.
448 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
452 pc_to_domain(struct pv_chunk *pc)
455 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
459 pc_to_domain(struct pv_chunk *pc __unused)
466 struct pv_chunks_list {
468 TAILQ_HEAD(pch, pv_chunk) pvc_list;
470 } __aligned(CACHE_LINE_SIZE);
472 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
475 struct pmap_large_md_page {
476 struct rwlock pv_lock;
477 struct md_page pv_page;
480 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
481 #define pv_dummy pv_dummy_large.pv_page
482 __read_mostly static struct pmap_large_md_page *pv_table;
483 __read_mostly vm_paddr_t pmap_last_pa;
485 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
486 static u_long pv_invl_gen[NPV_LIST_LOCKS];
487 static struct md_page *pv_table;
488 static struct md_page pv_dummy;
492 * All those kernel PT submaps that BSD is so fond of
494 pt_entry_t *CMAP1 = NULL;
496 static vm_offset_t qframe = 0;
497 static struct mtx qframe_mtx;
499 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
501 static vmem_t *large_vmem;
502 static u_int lm_ents;
503 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
504 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
506 int pmap_pcid_enabled = 1;
507 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
508 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
509 int invpcid_works = 0;
510 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
511 "Is the invpcid instruction available ?");
513 int __read_frequently pti = 0;
514 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
516 "Page Table Isolation enabled");
517 static vm_object_t pti_obj;
518 static pml4_entry_t *pti_pml4;
519 static vm_pindex_t pti_pg_idx;
520 static bool pti_finalized;
522 struct pmap_pkru_range {
523 struct rs_el pkru_rs_el;
528 static uma_zone_t pmap_pkru_ranges_zone;
529 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
530 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
531 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
532 static void *pkru_dup_range(void *ctx, void *data);
533 static void pkru_free_range(void *ctx, void *node);
534 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
535 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
536 static void pmap_pkru_deassign_all(pmap_t pmap);
538 static COUNTER_U64_DEFINE_EARLY(pcid_save_cnt);
539 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLFLAG_RD,
540 &pcid_save_cnt, "Count of saved TLB context on switch");
542 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
543 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
544 static struct mtx invl_gen_mtx;
545 /* Fake lock object to satisfy turnstiles interface. */
546 static struct lock_object invl_gen_ts = {
549 static struct pmap_invl_gen pmap_invl_gen_head = {
553 static u_long pmap_invl_gen = 1;
554 static int pmap_invl_waiters;
555 static struct callout pmap_invl_callout;
556 static bool pmap_invl_callout_inited;
558 #define PMAP_ASSERT_NOT_IN_DI() \
559 KASSERT(pmap_not_in_di(), ("DI already started"))
566 if ((cpu_feature2 & CPUID2_CX16) == 0)
569 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
574 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
578 locked = pmap_di_locked();
579 return (sysctl_handle_int(oidp, &locked, 0, req));
581 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
582 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
583 "Locked delayed invalidation");
585 static bool pmap_not_in_di_l(void);
586 static bool pmap_not_in_di_u(void);
587 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
590 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
594 pmap_not_in_di_l(void)
596 struct pmap_invl_gen *invl_gen;
598 invl_gen = &curthread->td_md.md_invl_gen;
599 return (invl_gen->gen == 0);
603 pmap_thread_init_invl_gen_l(struct thread *td)
605 struct pmap_invl_gen *invl_gen;
607 invl_gen = &td->td_md.md_invl_gen;
612 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
614 struct turnstile *ts;
616 ts = turnstile_trywait(&invl_gen_ts);
617 if (*m_gen > atomic_load_long(invl_gen))
618 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
620 turnstile_cancel(ts);
624 pmap_delayed_invl_finish_unblock(u_long new_gen)
626 struct turnstile *ts;
628 turnstile_chain_lock(&invl_gen_ts);
629 ts = turnstile_lookup(&invl_gen_ts);
631 pmap_invl_gen = new_gen;
633 turnstile_broadcast(ts, TS_SHARED_QUEUE);
634 turnstile_unpend(ts);
636 turnstile_chain_unlock(&invl_gen_ts);
640 * Start a new Delayed Invalidation (DI) block of code, executed by
641 * the current thread. Within a DI block, the current thread may
642 * destroy both the page table and PV list entries for a mapping and
643 * then release the corresponding PV list lock before ensuring that
644 * the mapping is flushed from the TLBs of any processors with the
648 pmap_delayed_invl_start_l(void)
650 struct pmap_invl_gen *invl_gen;
653 invl_gen = &curthread->td_md.md_invl_gen;
654 PMAP_ASSERT_NOT_IN_DI();
655 mtx_lock(&invl_gen_mtx);
656 if (LIST_EMPTY(&pmap_invl_gen_tracker))
657 currgen = pmap_invl_gen;
659 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
660 invl_gen->gen = currgen + 1;
661 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
662 mtx_unlock(&invl_gen_mtx);
666 * Finish the DI block, previously started by the current thread. All
667 * required TLB flushes for the pages marked by
668 * pmap_delayed_invl_page() must be finished before this function is
671 * This function works by bumping the global DI generation number to
672 * the generation number of the current thread's DI, unless there is a
673 * pending DI that started earlier. In the latter case, bumping the
674 * global DI generation number would incorrectly signal that the
675 * earlier DI had finished. Instead, this function bumps the earlier
676 * DI's generation number to match the generation number of the
677 * current thread's DI.
680 pmap_delayed_invl_finish_l(void)
682 struct pmap_invl_gen *invl_gen, *next;
684 invl_gen = &curthread->td_md.md_invl_gen;
685 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
686 mtx_lock(&invl_gen_mtx);
687 next = LIST_NEXT(invl_gen, link);
689 pmap_delayed_invl_finish_unblock(invl_gen->gen);
691 next->gen = invl_gen->gen;
692 LIST_REMOVE(invl_gen, link);
693 mtx_unlock(&invl_gen_mtx);
698 pmap_not_in_di_u(void)
700 struct pmap_invl_gen *invl_gen;
702 invl_gen = &curthread->td_md.md_invl_gen;
703 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
707 pmap_thread_init_invl_gen_u(struct thread *td)
709 struct pmap_invl_gen *invl_gen;
711 invl_gen = &td->td_md.md_invl_gen;
713 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
717 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
719 uint64_t new_high, new_low, old_high, old_low;
722 old_low = new_low = 0;
723 old_high = new_high = (uintptr_t)0;
725 __asm volatile("lock;cmpxchg16b\t%1"
726 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
727 : "b"(new_low), "c" (new_high)
730 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
733 out->next = (void *)old_high;
736 out->next = (void *)new_high;
742 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
743 struct pmap_invl_gen *new_val)
745 uint64_t new_high, new_low, old_high, old_low;
748 new_low = new_val->gen;
749 new_high = (uintptr_t)new_val->next;
750 old_low = old_val->gen;
751 old_high = (uintptr_t)old_val->next;
753 __asm volatile("lock;cmpxchg16b\t%1"
754 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
755 : "b"(new_low), "c" (new_high)
760 static COUNTER_U64_DEFINE_EARLY(pv_page_count);
761 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_page_count, CTLFLAG_RD,
762 &pv_page_count, "Current number of allocated pv pages");
764 static COUNTER_U64_DEFINE_EARLY(pt_page_count);
765 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pt_page_count, CTLFLAG_RD,
766 &pt_page_count, "Current number of allocated page table pages");
770 static COUNTER_U64_DEFINE_EARLY(invl_start_restart);
771 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_start_restart,
772 CTLFLAG_RD, &invl_start_restart,
773 "Number of delayed TLB invalidation request restarts");
775 static COUNTER_U64_DEFINE_EARLY(invl_finish_restart);
776 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
777 &invl_finish_restart,
778 "Number of delayed TLB invalidation completion restarts");
780 static int invl_max_qlen;
781 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
783 "Maximum delayed TLB invalidation request queue length");
786 #define di_delay locks_delay
789 pmap_delayed_invl_start_u(void)
791 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
793 struct lock_delay_arg lda;
801 invl_gen = &td->td_md.md_invl_gen;
802 PMAP_ASSERT_NOT_IN_DI();
803 lock_delay_arg_init(&lda, &di_delay);
804 invl_gen->saved_pri = 0;
805 pri = td->td_base_pri;
808 pri = td->td_base_pri;
810 invl_gen->saved_pri = pri;
817 for (p = &pmap_invl_gen_head;; p = prev.next) {
819 prevl = (uintptr_t)atomic_load_ptr(&p->next);
820 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
821 PV_STAT(counter_u64_add(invl_start_restart, 1));
827 prev.next = (void *)prevl;
830 if ((ii = invl_max_qlen) < i)
831 atomic_cmpset_int(&invl_max_qlen, ii, i);
834 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
835 PV_STAT(counter_u64_add(invl_start_restart, 1));
840 new_prev.gen = prev.gen;
841 new_prev.next = invl_gen;
842 invl_gen->gen = prev.gen + 1;
844 /* Formal fence between store to invl->gen and updating *p. */
845 atomic_thread_fence_rel();
848 * After inserting an invl_gen element with invalid bit set,
849 * this thread blocks any other thread trying to enter the
850 * delayed invalidation block. Do not allow to remove us from
851 * the CPU, because it causes starvation for other threads.
856 * ABA for *p is not possible there, since p->gen can only
857 * increase. So if the *p thread finished its di, then
858 * started a new one and got inserted into the list at the
859 * same place, its gen will appear greater than the previously
862 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
864 PV_STAT(counter_u64_add(invl_start_restart, 1));
870 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
871 * invl_gen->next, allowing other threads to iterate past us.
872 * pmap_di_store_invl() provides fence between the generation
873 * write and the update of next.
875 invl_gen->next = NULL;
880 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
881 struct pmap_invl_gen *p)
883 struct pmap_invl_gen prev, new_prev;
887 * Load invl_gen->gen after setting invl_gen->next
888 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
889 * generations to propagate to our invl_gen->gen. Lock prefix
890 * in atomic_set_ptr() worked as seq_cst fence.
892 mygen = atomic_load_long(&invl_gen->gen);
894 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
897 KASSERT(prev.gen < mygen,
898 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
899 new_prev.gen = mygen;
900 new_prev.next = (void *)((uintptr_t)invl_gen->next &
901 ~PMAP_INVL_GEN_NEXT_INVALID);
903 /* Formal fence between load of prev and storing update to it. */
904 atomic_thread_fence_rel();
906 return (pmap_di_store_invl(p, &prev, &new_prev));
910 pmap_delayed_invl_finish_u(void)
912 struct pmap_invl_gen *invl_gen, *p;
914 struct lock_delay_arg lda;
918 invl_gen = &td->td_md.md_invl_gen;
919 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
920 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
921 ("missed invl_start: INVALID"));
922 lock_delay_arg_init(&lda, &di_delay);
925 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
926 prevl = (uintptr_t)atomic_load_ptr(&p->next);
927 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
928 PV_STAT(counter_u64_add(invl_finish_restart, 1));
932 if ((void *)prevl == invl_gen)
937 * It is legitimate to not find ourself on the list if a
938 * thread before us finished its DI and started it again.
940 if (__predict_false(p == NULL)) {
941 PV_STAT(counter_u64_add(invl_finish_restart, 1));
947 atomic_set_ptr((uintptr_t *)&invl_gen->next,
948 PMAP_INVL_GEN_NEXT_INVALID);
949 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
950 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
951 PMAP_INVL_GEN_NEXT_INVALID);
953 PV_STAT(counter_u64_add(invl_finish_restart, 1));
958 if (atomic_load_int(&pmap_invl_waiters) > 0)
959 pmap_delayed_invl_finish_unblock(0);
960 if (invl_gen->saved_pri != 0) {
962 sched_prio(td, invl_gen->saved_pri);
968 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
970 struct pmap_invl_gen *p, *pn;
975 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
977 nextl = (uintptr_t)atomic_load_ptr(&p->next);
978 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
979 td = first ? NULL : __containerof(p, struct thread,
981 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
982 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
983 td != NULL ? td->td_tid : -1);
989 static COUNTER_U64_DEFINE_EARLY(invl_wait);
990 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait,
991 CTLFLAG_RD, &invl_wait,
992 "Number of times DI invalidation blocked pmap_remove_all/write");
994 static COUNTER_U64_DEFINE_EARLY(invl_wait_slow);
995 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD,
996 &invl_wait_slow, "Number of slow invalidation waits for lockless DI");
1002 pmap_delayed_invl_genp(vm_page_t m)
1007 pa = VM_PAGE_TO_PHYS(m);
1008 if (__predict_false((pa) > pmap_last_pa))
1009 gen = &pv_dummy_large.pv_invl_gen;
1011 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1017 pmap_delayed_invl_genp(vm_page_t m)
1020 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1025 pmap_delayed_invl_callout_func(void *arg __unused)
1028 if (atomic_load_int(&pmap_invl_waiters) == 0)
1030 pmap_delayed_invl_finish_unblock(0);
1034 pmap_delayed_invl_callout_init(void *arg __unused)
1037 if (pmap_di_locked())
1039 callout_init(&pmap_invl_callout, 1);
1040 pmap_invl_callout_inited = true;
1042 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1043 pmap_delayed_invl_callout_init, NULL);
1046 * Ensure that all currently executing DI blocks, that need to flush
1047 * TLB for the given page m, actually flushed the TLB at the time the
1048 * function returned. If the page m has an empty PV list and we call
1049 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1050 * valid mapping for the page m in either its page table or TLB.
1052 * This function works by blocking until the global DI generation
1053 * number catches up with the generation number associated with the
1054 * given page m and its PV list. Since this function's callers
1055 * typically own an object lock and sometimes own a page lock, it
1056 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1060 pmap_delayed_invl_wait_l(vm_page_t m)
1064 bool accounted = false;
1067 m_gen = pmap_delayed_invl_genp(m);
1068 while (*m_gen > pmap_invl_gen) {
1071 counter_u64_add(invl_wait, 1);
1075 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1080 pmap_delayed_invl_wait_u(vm_page_t m)
1083 struct lock_delay_arg lda;
1087 m_gen = pmap_delayed_invl_genp(m);
1088 lock_delay_arg_init(&lda, &di_delay);
1089 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1090 if (fast || !pmap_invl_callout_inited) {
1091 PV_STAT(counter_u64_add(invl_wait, 1));
1096 * The page's invalidation generation number
1097 * is still below the current thread's number.
1098 * Prepare to block so that we do not waste
1099 * CPU cycles or worse, suffer livelock.
1101 * Since it is impossible to block without
1102 * racing with pmap_delayed_invl_finish_u(),
1103 * prepare for the race by incrementing
1104 * pmap_invl_waiters and arming a 1-tick
1105 * callout which will unblock us if we lose
1108 atomic_add_int(&pmap_invl_waiters, 1);
1111 * Re-check the current thread's invalidation
1112 * generation after incrementing
1113 * pmap_invl_waiters, so that there is no race
1114 * with pmap_delayed_invl_finish_u() setting
1115 * the page generation and checking
1116 * pmap_invl_waiters. The only race allowed
1117 * is for a missed unblock, which is handled
1121 atomic_load_long(&pmap_invl_gen_head.gen)) {
1122 callout_reset(&pmap_invl_callout, 1,
1123 pmap_delayed_invl_callout_func, NULL);
1124 PV_STAT(counter_u64_add(invl_wait_slow, 1));
1125 pmap_delayed_invl_wait_block(m_gen,
1126 &pmap_invl_gen_head.gen);
1128 atomic_add_int(&pmap_invl_waiters, -1);
1133 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1136 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1137 pmap_thread_init_invl_gen_u);
1140 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1143 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1144 pmap_delayed_invl_start_u);
1147 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1150 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1151 pmap_delayed_invl_finish_u);
1154 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1157 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1158 pmap_delayed_invl_wait_u);
1162 * Mark the page m's PV list as participating in the current thread's
1163 * DI block. Any threads concurrently using m's PV list to remove or
1164 * restrict all mappings to m will wait for the current thread's DI
1165 * block to complete before proceeding.
1167 * The function works by setting the DI generation number for m's PV
1168 * list to at least the DI generation number of the current thread.
1169 * This forces a caller of pmap_delayed_invl_wait() to block until
1170 * current thread calls pmap_delayed_invl_finish().
1173 pmap_delayed_invl_page(vm_page_t m)
1177 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1178 gen = curthread->td_md.md_invl_gen.gen;
1181 m_gen = pmap_delayed_invl_genp(m);
1189 static caddr_t crashdumpmap;
1192 * Internal flags for pmap_enter()'s helper functions.
1194 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1195 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1198 * Internal flags for pmap_mapdev_internal() and
1199 * pmap_change_props_locked().
1201 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1202 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1203 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1205 TAILQ_HEAD(pv_chunklist, pv_chunk);
1207 static void free_pv_chunk(struct pv_chunk *pc);
1208 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1209 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1210 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1211 static int popcnt_pc_map_pq(uint64_t *map);
1212 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1213 static void reserve_pv_entries(pmap_t pmap, int needed,
1214 struct rwlock **lockp);
1215 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1216 struct rwlock **lockp);
1217 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1218 u_int flags, struct rwlock **lockp);
1219 #if VM_NRESERVLEVEL > 0
1220 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1221 struct rwlock **lockp);
1223 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1224 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1227 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1228 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1229 vm_prot_t prot, int mode, int flags);
1230 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1231 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1232 vm_offset_t va, struct rwlock **lockp);
1233 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1235 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1236 vm_prot_t prot, struct rwlock **lockp);
1237 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1238 u_int flags, vm_page_t m, struct rwlock **lockp);
1239 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1240 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1241 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1242 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1243 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1245 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1247 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1249 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1250 static vm_page_t pmap_large_map_getptp_unlocked(void);
1251 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1252 #if VM_NRESERVLEVEL > 0
1253 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1254 struct rwlock **lockp);
1256 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1258 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1259 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1261 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1262 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1263 static void pmap_pti_wire_pte(void *pte);
1264 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1265 struct spglist *free, struct rwlock **lockp);
1266 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1267 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1268 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1269 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1270 struct spglist *free);
1271 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1272 pd_entry_t *pde, struct spglist *free,
1273 struct rwlock **lockp);
1274 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1275 vm_page_t m, struct rwlock **lockp);
1276 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1278 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1280 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1281 struct rwlock **lockp);
1282 static vm_page_t pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex,
1283 struct rwlock **lockp, vm_offset_t va);
1284 static vm_page_t pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex,
1285 struct rwlock **lockp, vm_offset_t va);
1286 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1287 struct rwlock **lockp);
1289 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1290 struct spglist *free);
1291 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1293 /********************/
1294 /* Inline functions */
1295 /********************/
1298 * Return a non-clipped indexes for a given VA, which are page table
1299 * pages indexes at the corresponding level.
1301 static __inline vm_pindex_t
1302 pmap_pde_pindex(vm_offset_t va)
1304 return (va >> PDRSHIFT);
1307 static __inline vm_pindex_t
1308 pmap_pdpe_pindex(vm_offset_t va)
1310 return (NUPDE + (va >> PDPSHIFT));
1313 static __inline vm_pindex_t
1314 pmap_pml4e_pindex(vm_offset_t va)
1316 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1319 static __inline vm_pindex_t
1320 pmap_pml5e_pindex(vm_offset_t va)
1322 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1325 static __inline pml4_entry_t *
1326 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1329 MPASS(pmap_is_la57(pmap));
1330 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1333 static __inline pml4_entry_t *
1334 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1337 MPASS(pmap_is_la57(pmap));
1338 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1341 static __inline pml4_entry_t *
1342 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1344 pml4_entry_t *pml4e;
1346 /* XXX MPASS(pmap_is_la57(pmap); */
1347 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1348 return (&pml4e[pmap_pml4e_index(va)]);
1351 /* Return a pointer to the PML4 slot that corresponds to a VA */
1352 static __inline pml4_entry_t *
1353 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1355 pml5_entry_t *pml5e;
1356 pml4_entry_t *pml4e;
1359 if (pmap_is_la57(pmap)) {
1360 pml5e = pmap_pml5e(pmap, va);
1361 PG_V = pmap_valid_bit(pmap);
1362 if ((*pml5e & PG_V) == 0)
1364 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1366 pml4e = pmap->pm_pmltop;
1368 return (&pml4e[pmap_pml4e_index(va)]);
1371 static __inline pml4_entry_t *
1372 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1374 MPASS(!pmap_is_la57(pmap));
1375 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1378 /* Return a pointer to the PDP slot that corresponds to a VA */
1379 static __inline pdp_entry_t *
1380 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1384 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1385 return (&pdpe[pmap_pdpe_index(va)]);
1388 /* Return a pointer to the PDP slot that corresponds to a VA */
1389 static __inline pdp_entry_t *
1390 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1392 pml4_entry_t *pml4e;
1395 PG_V = pmap_valid_bit(pmap);
1396 pml4e = pmap_pml4e(pmap, va);
1397 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1399 return (pmap_pml4e_to_pdpe(pml4e, va));
1402 /* Return a pointer to the PD slot that corresponds to a VA */
1403 static __inline pd_entry_t *
1404 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1408 KASSERT((*pdpe & PG_PS) == 0,
1409 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1410 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1411 return (&pde[pmap_pde_index(va)]);
1414 /* Return a pointer to the PD slot that corresponds to a VA */
1415 static __inline pd_entry_t *
1416 pmap_pde(pmap_t pmap, vm_offset_t va)
1421 PG_V = pmap_valid_bit(pmap);
1422 pdpe = pmap_pdpe(pmap, va);
1423 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1425 KASSERT((*pdpe & PG_PS) == 0,
1426 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1427 return (pmap_pdpe_to_pde(pdpe, va));
1430 /* Return a pointer to the PT slot that corresponds to a VA */
1431 static __inline pt_entry_t *
1432 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1436 KASSERT((*pde & PG_PS) == 0,
1437 ("%s: pde %#lx is a leaf", __func__, *pde));
1438 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1439 return (&pte[pmap_pte_index(va)]);
1442 /* Return a pointer to the PT slot that corresponds to a VA */
1443 static __inline pt_entry_t *
1444 pmap_pte(pmap_t pmap, vm_offset_t va)
1449 PG_V = pmap_valid_bit(pmap);
1450 pde = pmap_pde(pmap, va);
1451 if (pde == NULL || (*pde & PG_V) == 0)
1453 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1454 return ((pt_entry_t *)pde);
1455 return (pmap_pde_to_pte(pde, va));
1458 static __inline void
1459 pmap_resident_count_inc(pmap_t pmap, int count)
1462 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1463 pmap->pm_stats.resident_count += count;
1466 static __inline void
1467 pmap_resident_count_dec(pmap_t pmap, int count)
1470 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1471 KASSERT(pmap->pm_stats.resident_count >= count,
1472 ("pmap %p resident count underflow %ld %d", pmap,
1473 pmap->pm_stats.resident_count, count));
1474 pmap->pm_stats.resident_count -= count;
1477 PMAP_INLINE pt_entry_t *
1478 vtopte(vm_offset_t va)
1482 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1485 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1486 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1487 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1489 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1490 NPML4EPGSHIFT)) - 1);
1491 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1495 static __inline pd_entry_t *
1496 vtopde(vm_offset_t va)
1500 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1503 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1504 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1505 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1507 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1508 NPML4EPGSHIFT)) - 1);
1509 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1514 allocpages(vm_paddr_t *firstaddr, int n)
1519 bzero((void *)ret, n * PAGE_SIZE);
1520 *firstaddr += n * PAGE_SIZE;
1524 CTASSERT(powerof2(NDMPML4E));
1526 /* number of kernel PDP slots */
1527 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1530 nkpt_init(vm_paddr_t addr)
1537 pt_pages = howmany(addr, 1 << PDRSHIFT);
1538 pt_pages += NKPDPE(pt_pages);
1541 * Add some slop beyond the bare minimum required for bootstrapping
1544 * This is quite important when allocating KVA for kernel modules.
1545 * The modules are required to be linked in the negative 2GB of
1546 * the address space. If we run out of KVA in this region then
1547 * pmap_growkernel() will need to allocate page table pages to map
1548 * the entire 512GB of KVA space which is an unnecessary tax on
1551 * Secondly, device memory mapped as part of setting up the low-
1552 * level console(s) is taken from KVA, starting at virtual_avail.
1553 * This is because cninit() is called after pmap_bootstrap() but
1554 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1557 pt_pages += 32; /* 64MB additional slop. */
1563 * Returns the proper write/execute permission for a physical page that is
1564 * part of the initial boot allocations.
1566 * If the page has kernel text, it is marked as read-only. If the page has
1567 * kernel read-only data, it is marked as read-only/not-executable. If the
1568 * page has only read-write data, it is marked as read-write/not-executable.
1569 * If the page is below/above the kernel range, it is marked as read-write.
1571 * This function operates on 2M pages, since we map the kernel space that
1574 static inline pt_entry_t
1575 bootaddr_rwx(vm_paddr_t pa)
1579 * The kernel is loaded at a 2MB-aligned address, and memory below that
1580 * need not be executable. The .bss section is padded to a 2MB
1581 * boundary, so memory following the kernel need not be executable
1582 * either. Preloaded kernel modules have their mapping permissions
1583 * fixed up by the linker.
1585 if (pa < trunc_2mpage(btext - KERNBASE) ||
1586 pa >= trunc_2mpage(_end - KERNBASE))
1587 return (X86_PG_RW | pg_nx);
1590 * The linker should ensure that the read-only and read-write
1591 * portions don't share the same 2M page, so this shouldn't
1592 * impact read-only data. However, in any case, any page with
1593 * read-write data needs to be read-write.
1595 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1596 return (X86_PG_RW | pg_nx);
1599 * Mark any 2M page containing kernel text as read-only. Mark
1600 * other pages with read-only data as read-only and not executable.
1601 * (It is likely a small portion of the read-only data section will
1602 * be marked as read-only, but executable. This should be acceptable
1603 * since the read-only protection will keep the data from changing.)
1604 * Note that fixups to the .text section will still work until we
1607 if (pa < round_2mpage(etext - KERNBASE))
1613 create_pagetables(vm_paddr_t *firstaddr)
1615 int i, j, ndm1g, nkpdpe, nkdmpde;
1619 uint64_t DMPDkernphys;
1621 /* Allocate page table pages for the direct map */
1622 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1623 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1625 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1626 if (ndmpdpphys > NDMPML4E) {
1628 * Each NDMPML4E allows 512 GB, so limit to that,
1629 * and then readjust ndmpdp and ndmpdpphys.
1631 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1632 Maxmem = atop(NDMPML4E * NBPML4);
1633 ndmpdpphys = NDMPML4E;
1634 ndmpdp = NDMPML4E * NPDEPG;
1636 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1638 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1640 * Calculate the number of 1G pages that will fully fit in
1643 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1646 * Allocate 2M pages for the kernel. These will be used in
1647 * place of the first one or more 1G pages from ndm1g.
1649 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1650 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1653 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1654 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1656 /* Allocate pages */
1657 KPML4phys = allocpages(firstaddr, 1);
1658 KPDPphys = allocpages(firstaddr, NKPML4E);
1661 * Allocate the initial number of kernel page table pages required to
1662 * bootstrap. We defer this until after all memory-size dependent
1663 * allocations are done (e.g. direct map), so that we don't have to
1664 * build in too much slop in our estimate.
1666 * Note that when NKPML4E > 1, we have an empty page underneath
1667 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1668 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1670 nkpt_init(*firstaddr);
1671 nkpdpe = NKPDPE(nkpt);
1673 KPTphys = allocpages(firstaddr, nkpt);
1674 KPDphys = allocpages(firstaddr, nkpdpe);
1677 * Connect the zero-filled PT pages to their PD entries. This
1678 * implicitly maps the PT pages at their correct locations within
1681 pd_p = (pd_entry_t *)KPDphys;
1682 for (i = 0; i < nkpt; i++)
1683 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1686 * Map from physical address zero to the end of loader preallocated
1687 * memory using 2MB pages. This replaces some of the PD entries
1690 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1691 /* Preset PG_M and PG_A because demotion expects it. */
1692 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1693 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1696 * Because we map the physical blocks in 2M pages, adjust firstaddr
1697 * to record the physical blocks we've actually mapped into kernel
1698 * virtual address space.
1700 if (*firstaddr < round_2mpage(KERNend))
1701 *firstaddr = round_2mpage(KERNend);
1703 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1704 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1705 for (i = 0; i < nkpdpe; i++)
1706 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1709 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1710 * the end of physical memory is not aligned to a 1GB page boundary,
1711 * then the residual physical memory is mapped with 2MB pages. Later,
1712 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1713 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1714 * that are partially used.
1716 pd_p = (pd_entry_t *)DMPDphys;
1717 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1718 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1719 /* Preset PG_M and PG_A because demotion expects it. */
1720 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1721 X86_PG_M | X86_PG_A | pg_nx;
1723 pdp_p = (pdp_entry_t *)DMPDPphys;
1724 for (i = 0; i < ndm1g; i++) {
1725 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1726 /* Preset PG_M and PG_A because demotion expects it. */
1727 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1728 X86_PG_M | X86_PG_A | pg_nx;
1730 for (j = 0; i < ndmpdp; i++, j++) {
1731 pdp_p[i] = DMPDphys + ptoa(j);
1732 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1736 * Instead of using a 1G page for the memory containing the kernel,
1737 * use 2M pages with read-only and no-execute permissions. (If using 1G
1738 * pages, this will partially overwrite the PDPEs above.)
1741 pd_p = (pd_entry_t *)DMPDkernphys;
1742 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1743 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1744 X86_PG_M | X86_PG_A | pg_nx |
1745 bootaddr_rwx(i << PDRSHIFT);
1746 for (i = 0; i < nkdmpde; i++)
1747 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1751 /* And recursively map PML4 to itself in order to get PTmap */
1752 p4_p = (pml4_entry_t *)KPML4phys;
1753 p4_p[PML4PML4I] = KPML4phys;
1754 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1756 /* Connect the Direct Map slot(s) up to the PML4. */
1757 for (i = 0; i < ndmpdpphys; i++) {
1758 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1759 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1762 /* Connect the KVA slots up to the PML4 */
1763 for (i = 0; i < NKPML4E; i++) {
1764 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1765 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1768 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1772 * Bootstrap the system enough to run with virtual memory.
1774 * On amd64 this is called after mapping has already been enabled
1775 * and just syncs the pmap module with what has already been done.
1776 * [We can't call it easily with mapping off since the kernel is not
1777 * mapped with PA == VA, hence we would have to relocate every address
1778 * from the linked base (virtual) address "KERNBASE" to the actual
1779 * (physical) address starting relative to 0]
1782 pmap_bootstrap(vm_paddr_t *firstaddr)
1785 pt_entry_t *pte, *pcpu_pte;
1786 struct region_descriptor r_gdt;
1787 uint64_t cr4, pcpu_phys;
1791 KERNend = *firstaddr;
1792 res = atop(KERNend - (vm_paddr_t)kernphys);
1798 * Create an initial set of page tables to run the kernel in.
1800 create_pagetables(firstaddr);
1802 pcpu_phys = allocpages(firstaddr, MAXCPU);
1805 * Add a physical memory segment (vm_phys_seg) corresponding to the
1806 * preallocated kernel page table pages so that vm_page structures
1807 * representing these pages will be created. The vm_page structures
1808 * are required for promotion of the corresponding kernel virtual
1809 * addresses to superpage mappings.
1811 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1814 * Account for the virtual addresses mapped by create_pagetables().
1816 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1817 virtual_end = VM_MAX_KERNEL_ADDRESS;
1820 * Enable PG_G global pages, then switch to the kernel page
1821 * table from the bootstrap page table. After the switch, it
1822 * is possible to enable SMEP and SMAP since PG_U bits are
1828 load_cr3(KPML4phys);
1829 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1831 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1836 * Initialize the kernel pmap (which is statically allocated).
1837 * Count bootstrap data as being resident in case any of this data is
1838 * later unmapped (using pmap_remove()) and freed.
1840 PMAP_LOCK_INIT(kernel_pmap);
1841 kernel_pmap->pm_pmltop = kernel_pml4;
1842 kernel_pmap->pm_cr3 = KPML4phys;
1843 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1844 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1845 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1846 kernel_pmap->pm_stats.resident_count = res;
1847 kernel_pmap->pm_flags = pmap_flags;
1850 * Initialize the TLB invalidations generation number lock.
1852 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1855 * Reserve some special page table entries/VA space for temporary
1858 #define SYSMAP(c, p, v, n) \
1859 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1865 * Crashdump maps. The first page is reused as CMAP1 for the
1868 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1869 CADDR1 = crashdumpmap;
1871 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1874 for (i = 0; i < MAXCPU; i++) {
1875 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1876 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1880 * Re-initialize PCPU area for BSP after switching.
1881 * Make hardware use gdt and common_tss from the new PCPU.
1883 STAILQ_INIT(&cpuhead);
1884 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1885 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1886 amd64_bsp_pcpu_init1(&__pcpu[0]);
1887 amd64_bsp_ist_init(&__pcpu[0]);
1888 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1890 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1891 sizeof(struct user_segment_descriptor));
1892 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1893 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1894 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1895 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1896 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1898 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1899 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1900 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1901 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1904 * Initialize the PAT MSR.
1905 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1906 * side-effect, invalidates stale PG_G TLB entries that might
1907 * have been created in our pre-boot environment.
1911 /* Initialize TLB Context Id. */
1912 if (pmap_pcid_enabled) {
1913 for (i = 0; i < MAXCPU; i++) {
1914 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1915 kernel_pmap->pm_pcids[i].pm_gen = 1;
1919 * PMAP_PCID_KERN + 1 is used for initialization of
1920 * proc0 pmap. The pmap' pcid state might be used by
1921 * EFIRT entry before first context switch, so it
1922 * needs to be valid.
1924 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1925 PCPU_SET(pcid_gen, 1);
1928 * pcpu area for APs is zeroed during AP startup.
1929 * pc_pcid_next and pc_pcid_gen are initialized by AP
1930 * during pcpu setup.
1932 load_cr4(rcr4() | CR4_PCIDE);
1937 * Setup the PAT MSR.
1946 /* Bail if this CPU doesn't implement PAT. */
1947 if ((cpu_feature & CPUID_PAT) == 0)
1950 /* Set default PAT index table. */
1951 for (i = 0; i < PAT_INDEX_SIZE; i++)
1953 pat_index[PAT_WRITE_BACK] = 0;
1954 pat_index[PAT_WRITE_THROUGH] = 1;
1955 pat_index[PAT_UNCACHEABLE] = 3;
1956 pat_index[PAT_WRITE_COMBINING] = 6;
1957 pat_index[PAT_WRITE_PROTECTED] = 5;
1958 pat_index[PAT_UNCACHED] = 2;
1961 * Initialize default PAT entries.
1962 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1963 * Program 5 and 6 as WP and WC.
1965 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1966 * mapping for a 2M page uses a PAT value with the bit 3 set due
1967 * to its overload with PG_PS.
1969 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1970 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1971 PAT_VALUE(2, PAT_UNCACHED) |
1972 PAT_VALUE(3, PAT_UNCACHEABLE) |
1973 PAT_VALUE(4, PAT_WRITE_BACK) |
1974 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1975 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1976 PAT_VALUE(7, PAT_UNCACHEABLE);
1980 load_cr4(cr4 & ~CR4_PGE);
1982 /* Disable caches (CD = 1, NW = 0). */
1984 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1986 /* Flushes caches and TLBs. */
1990 /* Update PAT and index table. */
1991 wrmsr(MSR_PAT, pat_msr);
1993 /* Flush caches and TLBs again. */
1997 /* Restore caches and PGE. */
2002 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
2003 la57_trampoline_gdt[], la57_trampoline_end[];
2006 pmap_bootstrap_la57(void *arg __unused)
2009 pml5_entry_t *v_pml5;
2010 pml4_entry_t *v_pml4;
2014 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2015 void (*la57_tramp)(uint64_t pml5);
2016 struct region_descriptor r_gdt;
2018 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2020 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2025 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2026 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2028 m_code = vm_page_alloc_contig(NULL, 0,
2029 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2030 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2031 if ((m_code->flags & PG_ZERO) == 0)
2032 pmap_zero_page(m_code);
2033 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2034 m_pml5 = vm_page_alloc_contig(NULL, 0,
2035 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2036 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2037 if ((m_pml5->flags & PG_ZERO) == 0)
2038 pmap_zero_page(m_pml5);
2039 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2040 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2041 m_pml4 = vm_page_alloc_contig(NULL, 0,
2042 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2043 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2044 if ((m_pml4->flags & PG_ZERO) == 0)
2045 pmap_zero_page(m_pml4);
2046 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2047 m_pdp = vm_page_alloc_contig(NULL, 0,
2048 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2049 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2050 if ((m_pdp->flags & PG_ZERO) == 0)
2051 pmap_zero_page(m_pdp);
2052 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2053 m_pd = vm_page_alloc_contig(NULL, 0,
2054 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2055 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2056 if ((m_pd->flags & PG_ZERO) == 0)
2057 pmap_zero_page(m_pd);
2058 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2059 m_pt = vm_page_alloc_contig(NULL, 0,
2060 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2061 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2062 if ((m_pt->flags & PG_ZERO) == 0)
2063 pmap_zero_page(m_pt);
2064 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2067 * Map m_code 1:1, it appears below 4G in KVA due to physical
2068 * address being below 4G. Since kernel KVA is in upper half,
2069 * the pml4e should be zero and free for temporary use.
2071 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2072 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2074 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2075 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2077 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2078 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2080 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2081 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2085 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2086 * entering all existing kernel mappings into level 5 table.
2088 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2089 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2092 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2094 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2095 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2097 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2098 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2102 * Copy and call the 48->57 trampoline, hope we return there, alive.
2104 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2105 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2106 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2107 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2108 la57_tramp(KPML5phys);
2111 * gdt was necessary reset, switch back to our gdt.
2114 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2118 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2119 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2120 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2123 * Now unmap the trampoline, and free the pages.
2124 * Clear pml5 entry used for 1:1 trampoline mapping.
2126 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2127 invlpg((vm_offset_t)v_code);
2128 vm_page_free(m_code);
2129 vm_page_free(m_pdp);
2134 * Recursively map PML5 to itself in order to get PTmap and
2137 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2139 kernel_pmap->pm_cr3 = KPML5phys;
2140 kernel_pmap->pm_pmltop = v_pml5;
2142 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2145 * Initialize a vm_page's machine-dependent fields.
2148 pmap_page_init(vm_page_t m)
2151 TAILQ_INIT(&m->md.pv_list);
2152 m->md.pat_mode = PAT_WRITE_BACK;
2155 static int pmap_allow_2m_x_ept;
2156 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2157 &pmap_allow_2m_x_ept, 0,
2158 "Allow executable superpage mappings in EPT");
2161 pmap_allow_2m_x_ept_recalculate(void)
2164 * SKL002, SKL012S. Since the EPT format is only used by
2165 * Intel CPUs, the vendor check is merely a formality.
2167 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2168 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2169 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2170 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2171 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2172 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2173 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2174 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2175 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2176 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2177 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2178 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2179 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2180 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2181 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2182 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2183 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2184 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2185 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2186 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2187 CPUID_TO_MODEL(cpu_id) == 0x85))))
2188 pmap_allow_2m_x_ept = 1;
2189 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2193 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2196 return (pmap->pm_type != PT_EPT || !executable ||
2197 !pmap_allow_2m_x_ept);
2202 pmap_init_pv_table(void)
2204 struct pmap_large_md_page *pvd;
2206 long start, end, highest, pv_npg;
2207 int domain, i, j, pages;
2210 * We strongly depend on the size being a power of two, so the assert
2211 * is overzealous. However, should the struct be resized to a
2212 * different power of two, the code below needs to be revisited.
2214 CTASSERT((sizeof(*pvd) == 64));
2217 * Calculate the size of the array.
2219 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2220 pv_npg = howmany(pmap_last_pa, NBPDR);
2221 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2223 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2224 if (pv_table == NULL)
2225 panic("%s: kva_alloc failed\n", __func__);
2228 * Iterate physical segments to allocate space for respective pages.
2232 for (i = 0; i < vm_phys_nsegs; i++) {
2233 end = vm_phys_segs[i].end / NBPDR;
2234 domain = vm_phys_segs[i].domain;
2239 start = highest + 1;
2240 pvd = &pv_table[start];
2242 pages = end - start + 1;
2243 s = round_page(pages * sizeof(*pvd));
2244 highest = start + (s / sizeof(*pvd)) - 1;
2246 for (j = 0; j < s; j += PAGE_SIZE) {
2247 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2248 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2250 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2251 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2254 for (j = 0; j < s / sizeof(*pvd); j++) {
2255 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2256 TAILQ_INIT(&pvd->pv_page.pv_list);
2257 pvd->pv_page.pv_gen = 0;
2258 pvd->pv_page.pat_mode = 0;
2259 pvd->pv_invl_gen = 0;
2263 pvd = &pv_dummy_large;
2264 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2265 TAILQ_INIT(&pvd->pv_page.pv_list);
2266 pvd->pv_page.pv_gen = 0;
2267 pvd->pv_page.pat_mode = 0;
2268 pvd->pv_invl_gen = 0;
2272 pmap_init_pv_table(void)
2278 * Initialize the pool of pv list locks.
2280 for (i = 0; i < NPV_LIST_LOCKS; i++)
2281 rw_init(&pv_list_locks[i], "pmap pv list");
2284 * Calculate the size of the pv head table for superpages.
2286 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2289 * Allocate memory for the pv head table for superpages.
2291 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2293 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2294 for (i = 0; i < pv_npg; i++)
2295 TAILQ_INIT(&pv_table[i].pv_list);
2296 TAILQ_INIT(&pv_dummy.pv_list);
2301 * Initialize the pmap module.
2302 * Called by vm_init, to initialize any structures that the pmap
2303 * system needs to map virtual memory.
2308 struct pmap_preinit_mapping *ppim;
2310 int error, i, ret, skz63;
2312 /* L1TF, reserve page @0 unconditionally */
2313 vm_page_blacklist_add(0, bootverbose);
2315 /* Detect bare-metal Skylake Server and Skylake-X. */
2316 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2317 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2319 * Skylake-X errata SKZ63. Processor May Hang When
2320 * Executing Code In an HLE Transaction Region between
2321 * 40000000H and 403FFFFFH.
2323 * Mark the pages in the range as preallocated. It
2324 * seems to be impossible to distinguish between
2325 * Skylake Server and Skylake X.
2328 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2331 printf("SKZ63: skipping 4M RAM starting "
2332 "at physical 1G\n");
2333 for (i = 0; i < atop(0x400000); i++) {
2334 ret = vm_page_blacklist_add(0x40000000 +
2336 if (!ret && bootverbose)
2337 printf("page at %#lx already used\n",
2338 0x40000000 + ptoa(i));
2344 pmap_allow_2m_x_ept_recalculate();
2347 * Initialize the vm page array entries for the kernel pmap's
2350 PMAP_LOCK(kernel_pmap);
2351 for (i = 0; i < nkpt; i++) {
2352 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2353 KASSERT(mpte >= vm_page_array &&
2354 mpte < &vm_page_array[vm_page_array_size],
2355 ("pmap_init: page table page is out of range"));
2356 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2357 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2358 mpte->ref_count = 1;
2361 * Collect the page table pages that were replaced by a 2MB
2362 * page in create_pagetables(). They are zero filled.
2364 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2365 pmap_insert_pt_page(kernel_pmap, mpte, false))
2366 panic("pmap_init: pmap_insert_pt_page failed");
2368 PMAP_UNLOCK(kernel_pmap);
2372 * If the kernel is running on a virtual machine, then it must assume
2373 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2374 * be prepared for the hypervisor changing the vendor and family that
2375 * are reported by CPUID. Consequently, the workaround for AMD Family
2376 * 10h Erratum 383 is enabled if the processor's feature set does not
2377 * include at least one feature that is only supported by older Intel
2378 * or newer AMD processors.
2380 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2381 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2382 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2384 workaround_erratum383 = 1;
2387 * Are large page mappings enabled?
2389 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2390 if (pg_ps_enabled) {
2391 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2392 ("pmap_init: can't assign to pagesizes[1]"));
2393 pagesizes[1] = NBPDR;
2394 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2395 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2396 ("pmap_init: can't assign to pagesizes[2]"));
2397 pagesizes[2] = NBPDP;
2402 * Initialize pv chunk lists.
2404 for (i = 0; i < PMAP_MEMDOM; i++) {
2405 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2406 TAILQ_INIT(&pv_chunks[i].pvc_list);
2408 pmap_init_pv_table();
2410 pmap_initialized = 1;
2411 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2412 ppim = pmap_preinit_mapping + i;
2415 /* Make the direct map consistent */
2416 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2417 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2418 ppim->sz, ppim->mode);
2422 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2423 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2426 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2427 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2428 (vmem_addr_t *)&qframe);
2430 panic("qframe allocation failed");
2433 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2434 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2435 lm_ents = LMEPML4I - LMSPML4I + 1;
2437 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2438 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2440 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2441 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2442 if (large_vmem == NULL) {
2443 printf("pmap: cannot create large map\n");
2446 for (i = 0; i < lm_ents; i++) {
2447 m = pmap_large_map_getptp_unlocked();
2449 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2450 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2456 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2457 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2458 "Maximum number of PML4 entries for use by large map (tunable). "
2459 "Each entry corresponds to 512GB of address space.");
2461 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2462 "2MB page mapping counters");
2464 static COUNTER_U64_DEFINE_EARLY(pmap_pde_demotions);
2465 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, demotions,
2466 CTLFLAG_RD, &pmap_pde_demotions, "2MB page demotions");
2468 static COUNTER_U64_DEFINE_EARLY(pmap_pde_mappings);
2469 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2470 &pmap_pde_mappings, "2MB page mappings");
2472 static COUNTER_U64_DEFINE_EARLY(pmap_pde_p_failures);
2473 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2474 &pmap_pde_p_failures, "2MB page promotion failures");
2476 static COUNTER_U64_DEFINE_EARLY(pmap_pde_promotions);
2477 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2478 &pmap_pde_promotions, "2MB page promotions");
2480 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2481 "1GB page mapping counters");
2483 static COUNTER_U64_DEFINE_EARLY(pmap_pdpe_demotions);
2484 SYSCTL_COUNTER_U64(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2485 &pmap_pdpe_demotions, "1GB page demotions");
2487 /***************************************************
2488 * Low level helper routines.....
2489 ***************************************************/
2492 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2494 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2496 switch (pmap->pm_type) {
2499 /* Verify that both PAT bits are not set at the same time */
2500 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2501 ("Invalid PAT bits in entry %#lx", entry));
2503 /* Swap the PAT bits if one of them is set */
2504 if ((entry & x86_pat_bits) != 0)
2505 entry ^= x86_pat_bits;
2509 * Nothing to do - the memory attributes are represented
2510 * the same way for regular pages and superpages.
2514 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2521 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2524 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2525 pat_index[(int)mode] >= 0);
2529 * Determine the appropriate bits to set in a PTE or PDE for a specified
2533 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2535 int cache_bits, pat_flag, pat_idx;
2537 if (!pmap_is_valid_memattr(pmap, mode))
2538 panic("Unknown caching mode %d\n", mode);
2540 switch (pmap->pm_type) {
2543 /* The PAT bit is different for PTE's and PDE's. */
2544 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2546 /* Map the caching mode to a PAT index. */
2547 pat_idx = pat_index[mode];
2549 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2552 cache_bits |= pat_flag;
2554 cache_bits |= PG_NC_PCD;
2556 cache_bits |= PG_NC_PWT;
2560 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2564 panic("unsupported pmap type %d", pmap->pm_type);
2567 return (cache_bits);
2571 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2575 switch (pmap->pm_type) {
2578 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2581 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2584 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2591 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2593 int pat_flag, pat_idx;
2596 switch (pmap->pm_type) {
2599 /* The PAT bit is different for PTE's and PDE's. */
2600 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2602 if ((pte & pat_flag) != 0)
2604 if ((pte & PG_NC_PCD) != 0)
2606 if ((pte & PG_NC_PWT) != 0)
2610 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2611 panic("EPT PTE %#lx has no PAT memory type", pte);
2612 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2616 /* See pmap_init_pat(). */
2626 pmap_ps_enabled(pmap_t pmap)
2629 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2633 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2636 switch (pmap->pm_type) {
2643 * This is a little bogus since the generation number is
2644 * supposed to be bumped up when a region of the address
2645 * space is invalidated in the page tables.
2647 * In this case the old PDE entry is valid but yet we want
2648 * to make sure that any mappings using the old entry are
2649 * invalidated in the TLB.
2651 * The reason this works as expected is because we rendezvous
2652 * "all" host cpus and force any vcpu context to exit as a
2655 atomic_add_long(&pmap->pm_eptgen, 1);
2658 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2660 pde_store(pde, newpde);
2664 * After changing the page size for the specified virtual address in the page
2665 * table, flush the corresponding entries from the processor's TLB. Only the
2666 * calling processor's TLB is affected.
2668 * The calling thread must be pinned to a processor.
2671 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2675 if (pmap_type_guest(pmap))
2678 KASSERT(pmap->pm_type == PT_X86,
2679 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2681 PG_G = pmap_global_bit(pmap);
2683 if ((newpde & PG_PS) == 0)
2684 /* Demotion: flush a specific 2MB page mapping. */
2686 else if ((newpde & PG_G) == 0)
2688 * Promotion: flush every 4KB page mapping from the TLB
2689 * because there are too many to flush individually.
2694 * Promotion: flush every 4KB page mapping from the TLB,
2695 * including any global (PG_G) mappings.
2702 * The amd64 pmap uses different approaches to TLB invalidation
2703 * depending on the kernel configuration, available hardware features,
2704 * and known hardware errata. The kernel configuration option that
2705 * has the greatest operational impact on TLB invalidation is PTI,
2706 * which is enabled automatically on affected Intel CPUs. The most
2707 * impactful hardware features are first PCID, and then INVPCID
2708 * instruction presence. PCID usage is quite different for PTI
2711 * * Kernel Page Table Isolation (PTI or KPTI) is used to mitigate
2712 * the Meltdown bug in some Intel CPUs. Under PTI, each user address
2713 * space is served by two page tables, user and kernel. The user
2714 * page table only maps user space and a kernel trampoline. The
2715 * kernel trampoline includes the entirety of the kernel text but
2716 * only the kernel data that is needed to switch from user to kernel
2717 * mode. The kernel page table maps the user and kernel address
2718 * spaces in their entirety. It is identical to the per-process
2719 * page table used in non-PTI mode.
2721 * User page tables are only used when the CPU is in user mode.
2722 * Consequently, some TLB invalidations can be postponed until the
2723 * switch from kernel to user mode. In contrast, the user
2724 * space part of the kernel page table is used for copyout(9), so
2725 * TLB invalidations on this page table cannot be similarly postponed.
2727 * The existence of a user mode page table for the given pmap is
2728 * indicated by a pm_ucr3 value that differs from PMAP_NO_CR3, in
2729 * which case pm_ucr3 contains the %cr3 register value for the user
2730 * mode page table's root.
2732 * * The pm_active bitmask indicates which CPUs currently have the
2733 * pmap active. A CPU's bit is set on context switch to the pmap, and
2734 * cleared on switching off this CPU. For the kernel page table,
2735 * the pm_active field is immutable and contains all CPUs. The
2736 * kernel page table is always logically active on every processor,
2737 * but not necessarily in use by the hardware, e.g., in PTI mode.
2739 * When requesting invalidation of virtual addresses with
2740 * pmap_invalidate_XXX() functions, the pmap sends shootdown IPIs to
2741 * all CPUs recorded as active in pm_active. Updates to and reads
2742 * from pm_active are not synchronized, and so they may race with
2743 * each other. Shootdown handlers are prepared to handle the race.
2745 * * PCID is an optional feature of the long mode x86 MMU where TLB
2746 * entries are tagged with the 'Process ID' of the address space
2747 * they belong to. This feature provides a limited namespace for
2748 * process identifiers, 12 bits, supporting 4095 simultaneous IDs
2751 * Allocation of a PCID to a pmap is done by an algorithm described
2752 * in section 15.12, "Other TLB Consistency Algorithms", of
2753 * Vahalia's book "Unix Internals". A PCID cannot be allocated for
2754 * the whole lifetime of a pmap in pmap_pinit() due to the limited
2755 * namespace. Instead, a per-CPU, per-pmap PCID is assigned when
2756 * the CPU is about to start caching TLB entries from a pmap,
2757 * i.e., on the context switch that activates the pmap on the CPU.
2759 * The PCID allocator maintains a per-CPU, per-pmap generation
2760 * count, pm_gen, which is incremented each time a new PCID is
2761 * allocated. On TLB invalidation, the generation counters for the
2762 * pmap are zeroed, which signals the context switch code that the
2763 * previously allocated PCID is no longer valid. Effectively,
2764 * zeroing any of these counters triggers a TLB shootdown for the
2765 * given CPU/address space, due to the allocation of a new PCID.
2767 * Zeroing can be performed remotely. Consequently, if a pmap is
2768 * inactive on a CPU, then a TLB shootdown for that pmap and CPU can
2769 * be initiated by an ordinary memory access to reset the target
2770 * CPU's generation count within the pmap. The CPU initiating the
2771 * TLB shootdown does not need to send an IPI to the target CPU.
2773 * * PTI + PCID. The available PCIDs are divided into two sets: PCIDs
2774 * for complete (kernel) page tables, and PCIDs for user mode page
2775 * tables. A user PCID value is obtained from the kernel PCID value
2776 * by setting the highest bit, 11, to 1 (0x800 == PMAP_PCID_USER_PT).
2778 * User space page tables are activated on return to user mode, by
2779 * loading pm_ucr3 into %cr3. If the PCPU(ucr3_load_mask) requests
2780 * clearing bit 63 of the loaded ucr3, this effectively causes
2781 * complete invalidation of the user mode TLB entries for the
2782 * current pmap. In which case, local invalidations of individual
2783 * pages in the user page table are skipped.
2785 * * Local invalidation, all modes. If the requested invalidation is
2786 * for a specific address or the total invalidation of a currently
2787 * active pmap, then the TLB is flushed using INVLPG for a kernel
2788 * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a
2789 * user space page table(s).
2791 * If the INVPCID instruction is available, it is used to flush entries
2792 * from the kernel page table.
2794 * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its
2795 * address space, all other 4095 PCIDs are used for user mode spaces
2796 * as described above. A context switch allocates a new PCID if
2797 * the recorded PCID is zero or the recorded generation does not match
2798 * the CPU's generation, effectively flushing the TLB for this address space.
2799 * Total remote invalidation is performed by zeroing pm_gen for all CPUs.
2800 * local user page: INVLPG
2801 * local kernel page: INVLPG
2802 * local user total: INVPCID(CTX)
2803 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2804 * remote user page, inactive pmap: zero pm_gen
2805 * remote user page, active pmap: zero pm_gen + IPI:INVLPG
2806 * (Both actions are required to handle the aforementioned pm_active races.)
2807 * remote kernel page: IPI:INVLPG
2808 * remote user total, inactive pmap: zero pm_gen
2809 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) or
2811 * (See note above about pm_active races.)
2812 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2814 * PTI enabled, PCID present.
2815 * local user page: INVLPG for kpt, INVPCID(ADDR) or (INVLPG for ucr3)
2817 * local kernel page: INVLPG
2818 * local user total: INVPCID(CTX) or reload %cr3 for kpt, clear PCID_SAVE
2819 * on loading UCR3 into %cr3 for upt
2820 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2821 * remote user page, inactive pmap: zero pm_gen
2822 * remote user page, active pmap: zero pm_gen + IPI:(INVLPG for kpt,
2823 * INVPCID(ADDR) for upt)
2824 * remote kernel page: IPI:INVLPG
2825 * remote user total, inactive pmap: zero pm_gen
2826 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) for kpt,
2827 * clear PCID_SAVE on loading UCR3 into $cr3 for upt)
2828 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2831 * local user page: INVLPG
2832 * local kernel page: INVLPG
2833 * local user total: reload %cr3
2834 * local kernel total: invltlb_glob()
2835 * remote user page, inactive pmap: -
2836 * remote user page, active pmap: IPI:INVLPG
2837 * remote kernel page: IPI:INVLPG
2838 * remote user total, inactive pmap: -
2839 * remote user total, active pmap: IPI:(reload %cr3)
2840 * remote kernel total: IPI:invltlb_glob()
2841 * Since on return to user mode, the reload of %cr3 with ucr3 causes
2842 * TLB invalidation, no specific action is required for user page table.
2844 * EPT. EPT pmaps do not map KVA, all mappings are userspace.
2850 * Interrupt the cpus that are executing in the guest context.
2851 * This will force the vcpu to exit and the cached EPT mappings
2852 * will be invalidated by the host before the next vmresume.
2854 static __inline void
2855 pmap_invalidate_ept(pmap_t pmap)
2861 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2862 ("pmap_invalidate_ept: absurd pm_active"));
2865 * The TLB mappings associated with a vcpu context are not
2866 * flushed each time a different vcpu is chosen to execute.
2868 * This is in contrast with a process's vtop mappings that
2869 * are flushed from the TLB on each context switch.
2871 * Therefore we need to do more than just a TLB shootdown on
2872 * the active cpus in 'pmap->pm_active'. To do this we keep
2873 * track of the number of invalidations performed on this pmap.
2875 * Each vcpu keeps a cache of this counter and compares it
2876 * just before a vmresume. If the counter is out-of-date an
2877 * invept will be done to flush stale mappings from the TLB.
2879 * To ensure that all vCPU threads have observed the new counter
2880 * value before returning, we use SMR. Ordering is important here:
2881 * the VMM enters an SMR read section before loading the counter
2882 * and after updating the pm_active bit set. Thus, pm_active is
2883 * a superset of active readers, and any reader that has observed
2884 * the goal has observed the new counter value.
2886 atomic_add_long(&pmap->pm_eptgen, 1);
2888 goal = smr_advance(pmap->pm_eptsmr);
2891 * Force the vcpu to exit and trap back into the hypervisor.
2893 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2894 ipi_selected(pmap->pm_active, ipinum);
2898 * Ensure that all active vCPUs will observe the new generation counter
2899 * value before executing any more guest instructions.
2901 smr_wait(pmap->pm_eptsmr, goal);
2905 pmap_invalidate_cpu_mask(pmap_t pmap)
2907 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2911 pmap_invalidate_preipi_pcid(pmap_t pmap)
2917 cpuid = PCPU_GET(cpuid);
2918 if (pmap != PCPU_GET(curpmap))
2919 cpuid = 0xffffffff; /* An impossible value */
2923 pmap->pm_pcids[i].pm_gen = 0;
2927 * The fence is between stores to pm_gen and the read of the
2928 * pm_active mask. We need to ensure that it is impossible
2929 * for us to miss the bit update in pm_active and
2930 * simultaneously observe a non-zero pm_gen in
2931 * pmap_activate_sw(), otherwise TLB update is missed.
2932 * Without the fence, IA32 allows such an outcome. Note that
2933 * pm_active is updated by a locked operation, which provides
2934 * the reciprocal fence.
2936 atomic_thread_fence_seq_cst();
2940 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
2945 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t))
2947 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
2948 pmap_invalidate_preipi_nopcid);
2952 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
2953 const bool invpcid_works1)
2955 struct invpcid_descr d;
2956 uint64_t kcr3, ucr3;
2961 * Because pm_pcid is recalculated on a context switch, we
2962 * must ensure there is no preemption, not just pinning.
2963 * Otherwise, we might use a stale value below.
2965 CRITICAL_ASSERT(curthread);
2968 * No need to do anything with user page tables invalidation
2969 * if there is no user page table, or invalidation is deferred
2970 * until the return to userspace. ucr3_load_mask is stable
2971 * because we have preemption disabled.
2973 if (pmap->pm_ucr3 == PMAP_NO_CR3 ||
2974 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
2977 cpuid = PCPU_GET(cpuid);
2979 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2980 if (invpcid_works1) {
2981 d.pcid = pcid | PMAP_PCID_USER_PT;
2984 invpcid(&d, INVPCID_ADDR);
2986 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2987 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2988 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2993 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
2995 pmap_invalidate_page_pcid_cb(pmap, va, true);
2999 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
3001 pmap_invalidate_page_pcid_cb(pmap, va, false);
3005 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
3009 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t))
3011 if (pmap_pcid_enabled)
3012 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
3013 pmap_invalidate_page_pcid_noinvpcid_cb);
3014 return (pmap_invalidate_page_nopcid_cb);
3018 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
3019 vm_offset_t addr2 __unused)
3021 if (pmap == kernel_pmap) {
3023 } else if (pmap == PCPU_GET(curpmap)) {
3025 pmap_invalidate_page_cb(pmap, va);
3030 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3032 if (pmap_type_guest(pmap)) {
3033 pmap_invalidate_ept(pmap);
3037 KASSERT(pmap->pm_type == PT_X86,
3038 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
3040 pmap_invalidate_preipi(pmap);
3041 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
3042 pmap_invalidate_page_curcpu_cb);
3045 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
3046 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
3049 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3050 const bool invpcid_works1)
3052 struct invpcid_descr d;
3053 uint64_t kcr3, ucr3;
3057 CRITICAL_ASSERT(curthread);
3059 if (pmap != PCPU_GET(curpmap) ||
3060 pmap->pm_ucr3 == PMAP_NO_CR3 ||
3061 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3064 cpuid = PCPU_GET(cpuid);
3066 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3067 if (invpcid_works1) {
3068 d.pcid = pcid | PMAP_PCID_USER_PT;
3070 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
3071 invpcid(&d, INVPCID_ADDR);
3073 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3074 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3075 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3080 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
3083 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
3087 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
3090 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
3094 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
3095 vm_offset_t eva __unused)
3099 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
3102 if (pmap_pcid_enabled)
3103 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
3104 pmap_invalidate_range_pcid_noinvpcid_cb);
3105 return (pmap_invalidate_range_nopcid_cb);
3109 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3113 if (pmap == kernel_pmap) {
3114 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3116 } else if (pmap == PCPU_GET(curpmap)) {
3117 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3119 pmap_invalidate_range_cb(pmap, sva, eva);
3124 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3126 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
3127 pmap_invalidate_all(pmap);
3131 if (pmap_type_guest(pmap)) {
3132 pmap_invalidate_ept(pmap);
3136 KASSERT(pmap->pm_type == PT_X86,
3137 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3139 pmap_invalidate_preipi(pmap);
3140 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
3141 pmap_invalidate_range_curcpu_cb);
3145 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
3147 struct invpcid_descr d;
3152 if (pmap == kernel_pmap) {
3153 if (invpcid_works1) {
3154 bzero(&d, sizeof(d));
3155 invpcid(&d, INVPCID_CTXGLOB);
3159 } else if (pmap == PCPU_GET(curpmap)) {
3160 CRITICAL_ASSERT(curthread);
3161 cpuid = PCPU_GET(cpuid);
3163 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3164 if (invpcid_works1) {
3168 invpcid(&d, INVPCID_CTX);
3170 kcr3 = pmap->pm_cr3 | pcid;
3173 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3174 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3179 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
3181 pmap_invalidate_all_pcid_cb(pmap, true);
3185 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
3187 pmap_invalidate_all_pcid_cb(pmap, false);
3191 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
3193 if (pmap == kernel_pmap)
3195 else if (pmap == PCPU_GET(curpmap))
3199 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t))
3201 if (pmap_pcid_enabled)
3202 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
3203 pmap_invalidate_all_pcid_noinvpcid_cb);
3204 return (pmap_invalidate_all_nopcid_cb);
3208 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3209 vm_offset_t addr2 __unused)
3211 pmap_invalidate_all_cb(pmap);
3215 pmap_invalidate_all(pmap_t pmap)
3217 if (pmap_type_guest(pmap)) {
3218 pmap_invalidate_ept(pmap);
3222 KASSERT(pmap->pm_type == PT_X86,
3223 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3225 pmap_invalidate_preipi(pmap);
3226 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3227 pmap_invalidate_all_curcpu_cb);
3231 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3232 vm_offset_t addr2 __unused)
3238 pmap_invalidate_cache(void)
3241 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3245 cpuset_t invalidate; /* processors that invalidate their TLB */
3250 u_int store; /* processor that updates the PDE */
3254 pmap_update_pde_action(void *arg)
3256 struct pde_action *act = arg;
3258 if (act->store == PCPU_GET(cpuid))
3259 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3263 pmap_update_pde_teardown(void *arg)
3265 struct pde_action *act = arg;
3267 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3268 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3272 * Change the page size for the specified virtual address in a way that
3273 * prevents any possibility of the TLB ever having two entries that map the
3274 * same virtual address using different page sizes. This is the recommended
3275 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3276 * machine check exception for a TLB state that is improperly diagnosed as a
3280 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3282 struct pde_action act;
3283 cpuset_t active, other_cpus;
3287 cpuid = PCPU_GET(cpuid);
3288 other_cpus = all_cpus;
3289 CPU_CLR(cpuid, &other_cpus);
3290 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3293 active = pmap->pm_active;
3295 if (CPU_OVERLAP(&active, &other_cpus)) {
3297 act.invalidate = active;
3301 act.newpde = newpde;
3302 CPU_SET(cpuid, &active);
3303 smp_rendezvous_cpus(active,
3304 smp_no_rendezvous_barrier, pmap_update_pde_action,
3305 pmap_update_pde_teardown, &act);
3307 pmap_update_pde_store(pmap, pde, newpde);
3308 if (CPU_ISSET(cpuid, &active))
3309 pmap_update_pde_invalidate(pmap, va, newpde);
3315 * Normal, non-SMP, invalidation functions.
3318 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3320 struct invpcid_descr d;
3321 uint64_t kcr3, ucr3;
3324 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3328 KASSERT(pmap->pm_type == PT_X86,
3329 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3331 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3333 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3334 pmap->pm_ucr3 != PMAP_NO_CR3) {
3336 pcid = pmap->pm_pcids[0].pm_pcid;
3337 if (invpcid_works) {
3338 d.pcid = pcid | PMAP_PCID_USER_PT;
3341 invpcid(&d, INVPCID_ADDR);
3343 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3344 ucr3 = pmap->pm_ucr3 | pcid |
3345 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3346 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3350 } else if (pmap_pcid_enabled)
3351 pmap->pm_pcids[0].pm_gen = 0;
3355 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3357 struct invpcid_descr d;
3359 uint64_t kcr3, ucr3;
3361 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3365 KASSERT(pmap->pm_type == PT_X86,
3366 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3368 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3369 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3371 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3372 pmap->pm_ucr3 != PMAP_NO_CR3) {
3374 if (invpcid_works) {
3375 d.pcid = pmap->pm_pcids[0].pm_pcid |
3379 for (; d.addr < eva; d.addr += PAGE_SIZE)
3380 invpcid(&d, INVPCID_ADDR);
3382 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3383 pm_pcid | CR3_PCID_SAVE;
3384 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3385 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3386 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3390 } else if (pmap_pcid_enabled) {
3391 pmap->pm_pcids[0].pm_gen = 0;
3396 pmap_invalidate_all(pmap_t pmap)
3398 struct invpcid_descr d;
3399 uint64_t kcr3, ucr3;
3401 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3405 KASSERT(pmap->pm_type == PT_X86,
3406 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3408 if (pmap == kernel_pmap) {
3409 if (pmap_pcid_enabled && invpcid_works) {
3410 bzero(&d, sizeof(d));
3411 invpcid(&d, INVPCID_CTXGLOB);
3415 } else if (pmap == PCPU_GET(curpmap)) {
3416 if (pmap_pcid_enabled) {
3418 if (invpcid_works) {
3419 d.pcid = pmap->pm_pcids[0].pm_pcid;
3422 invpcid(&d, INVPCID_CTX);
3423 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3424 d.pcid |= PMAP_PCID_USER_PT;
3425 invpcid(&d, INVPCID_CTX);
3428 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3429 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3430 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3431 0].pm_pcid | PMAP_PCID_USER_PT;
3432 pmap_pti_pcid_invalidate(ucr3, kcr3);
3440 } else if (pmap_pcid_enabled) {
3441 pmap->pm_pcids[0].pm_gen = 0;
3446 pmap_invalidate_cache(void)
3453 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3456 pmap_update_pde_store(pmap, pde, newpde);
3457 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3458 pmap_update_pde_invalidate(pmap, va, newpde);
3460 pmap->pm_pcids[0].pm_gen = 0;
3465 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3469 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3470 * by a promotion that did not invalidate the 512 4KB page mappings
3471 * that might exist in the TLB. Consequently, at this point, the TLB
3472 * may hold both 4KB and 2MB page mappings for the address range [va,
3473 * va + NBPDR). Therefore, the entire range must be invalidated here.
3474 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3475 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3476 * single INVLPG suffices to invalidate the 2MB page mapping from the
3479 if ((pde & PG_PROMOTED) != 0)
3480 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3482 pmap_invalidate_page(pmap, va);
3485 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3486 (vm_offset_t sva, vm_offset_t eva))
3489 if ((cpu_feature & CPUID_SS) != 0)
3490 return (pmap_invalidate_cache_range_selfsnoop);
3491 if ((cpu_feature & CPUID_CLFSH) != 0)
3492 return (pmap_force_invalidate_cache_range);
3493 return (pmap_invalidate_cache_range_all);
3496 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3499 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3502 KASSERT((sva & PAGE_MASK) == 0,
3503 ("pmap_invalidate_cache_range: sva not page-aligned"));
3504 KASSERT((eva & PAGE_MASK) == 0,
3505 ("pmap_invalidate_cache_range: eva not page-aligned"));
3509 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3512 pmap_invalidate_cache_range_check_align(sva, eva);
3516 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3519 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3522 * XXX: Some CPUs fault, hang, or trash the local APIC
3523 * registers if we use CLFLUSH on the local APIC range. The
3524 * local APIC is always uncached, so we don't need to flush
3525 * for that range anyway.
3527 if (pmap_kextract(sva) == lapic_paddr)
3530 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3532 * Do per-cache line flush. Use a locked
3533 * instruction to insure that previous stores are
3534 * included in the write-back. The processor
3535 * propagates flush to other processors in the cache
3538 atomic_thread_fence_seq_cst();
3539 for (; sva < eva; sva += cpu_clflush_line_size)
3541 atomic_thread_fence_seq_cst();
3544 * Writes are ordered by CLFLUSH on Intel CPUs.
3546 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3548 for (; sva < eva; sva += cpu_clflush_line_size)
3550 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3556 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3559 pmap_invalidate_cache_range_check_align(sva, eva);
3560 pmap_invalidate_cache();
3564 * Remove the specified set of pages from the data and instruction caches.
3566 * In contrast to pmap_invalidate_cache_range(), this function does not
3567 * rely on the CPU's self-snoop feature, because it is intended for use
3568 * when moving pages into a different cache domain.
3571 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3573 vm_offset_t daddr, eva;
3577 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3578 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3579 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3580 pmap_invalidate_cache();
3583 atomic_thread_fence_seq_cst();
3584 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3586 for (i = 0; i < count; i++) {
3587 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3588 eva = daddr + PAGE_SIZE;
3589 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3597 atomic_thread_fence_seq_cst();
3598 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3604 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3607 pmap_invalidate_cache_range_check_align(sva, eva);
3609 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3610 pmap_force_invalidate_cache_range(sva, eva);
3614 /* See comment in pmap_force_invalidate_cache_range(). */
3615 if (pmap_kextract(sva) == lapic_paddr)
3618 atomic_thread_fence_seq_cst();
3619 for (; sva < eva; sva += cpu_clflush_line_size)
3621 atomic_thread_fence_seq_cst();
3625 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3629 int error, pte_bits;
3631 KASSERT((spa & PAGE_MASK) == 0,
3632 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3633 KASSERT((epa & PAGE_MASK) == 0,
3634 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3636 if (spa < dmaplimit) {
3637 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3639 if (dmaplimit >= epa)
3644 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3646 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3648 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3649 pte = vtopte(vaddr);
3650 for (; spa < epa; spa += PAGE_SIZE) {
3652 pte_store(pte, spa | pte_bits);
3654 /* XXXKIB atomic inside flush_cache_range are excessive */
3655 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3658 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3662 * Routine: pmap_extract
3664 * Extract the physical page address associated
3665 * with the given map/virtual_address pair.
3668 pmap_extract(pmap_t pmap, vm_offset_t va)
3672 pt_entry_t *pte, PG_V;
3676 PG_V = pmap_valid_bit(pmap);
3678 pdpe = pmap_pdpe(pmap, va);
3679 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3680 if ((*pdpe & PG_PS) != 0)
3681 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3683 pde = pmap_pdpe_to_pde(pdpe, va);
3684 if ((*pde & PG_V) != 0) {
3685 if ((*pde & PG_PS) != 0) {
3686 pa = (*pde & PG_PS_FRAME) |
3689 pte = pmap_pde_to_pte(pde, va);
3690 pa = (*pte & PG_FRAME) |
3701 * Routine: pmap_extract_and_hold
3703 * Atomically extract and hold the physical page
3704 * with the given pmap and virtual address pair
3705 * if that mapping permits the given protection.
3708 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3710 pdp_entry_t pdpe, *pdpep;
3711 pd_entry_t pde, *pdep;
3712 pt_entry_t pte, PG_RW, PG_V;
3716 PG_RW = pmap_rw_bit(pmap);
3717 PG_V = pmap_valid_bit(pmap);
3720 pdpep = pmap_pdpe(pmap, va);
3721 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3723 if ((pdpe & PG_PS) != 0) {
3724 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3726 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3730 pdep = pmap_pdpe_to_pde(pdpep, va);
3731 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3733 if ((pde & PG_PS) != 0) {
3734 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3736 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3740 pte = *pmap_pde_to_pte(pdep, va);
3741 if ((pte & PG_V) == 0 ||
3742 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3744 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3747 if (m != NULL && !vm_page_wire_mapped(m))
3755 pmap_kextract(vm_offset_t va)
3760 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3761 pa = DMAP_TO_PHYS(va);
3762 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3763 pa = pmap_large_map_kextract(va);
3767 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3770 * Beware of a concurrent promotion that changes the
3771 * PDE at this point! For example, vtopte() must not
3772 * be used to access the PTE because it would use the
3773 * new PDE. It is, however, safe to use the old PDE
3774 * because the page table page is preserved by the
3777 pa = *pmap_pde_to_pte(&pde, va);
3778 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3784 /***************************************************
3785 * Low level mapping routines.....
3786 ***************************************************/
3789 * Add a wired page to the kva.
3790 * Note: not SMP coherent.
3793 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3798 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3801 static __inline void
3802 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3808 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3809 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3813 * Remove a page from the kernel pagetables.
3814 * Note: not SMP coherent.
3817 pmap_kremove(vm_offset_t va)
3826 * Used to map a range of physical addresses into kernel
3827 * virtual address space.
3829 * The value passed in '*virt' is a suggested virtual address for
3830 * the mapping. Architectures which can support a direct-mapped
3831 * physical to virtual region can return the appropriate address
3832 * within that region, leaving '*virt' unchanged. Other
3833 * architectures should map the pages starting at '*virt' and
3834 * update '*virt' with the first usable address after the mapped
3838 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3840 return PHYS_TO_DMAP(start);
3844 * Add a list of wired pages to the kva
3845 * this routine is only used for temporary
3846 * kernel mappings that do not need to have
3847 * page modification or references recorded.
3848 * Note that old mappings are simply written
3849 * over. The page *must* be wired.
3850 * Note: SMP coherent. Uses a ranged shootdown IPI.
3853 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3855 pt_entry_t *endpte, oldpte, pa, *pte;
3861 endpte = pte + count;
3862 while (pte < endpte) {
3864 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3865 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3866 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3868 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3872 if (__predict_false((oldpte & X86_PG_V) != 0))
3873 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3878 * This routine tears out page mappings from the
3879 * kernel -- it is meant only for temporary mappings.
3880 * Note: SMP coherent. Uses a ranged shootdown IPI.
3883 pmap_qremove(vm_offset_t sva, int count)
3888 while (count-- > 0) {
3889 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3893 pmap_invalidate_range(kernel_pmap, sva, va);
3896 /***************************************************
3897 * Page table page management routines.....
3898 ***************************************************/
3900 * Schedule the specified unused page table page to be freed. Specifically,
3901 * add the page to the specified list of pages that will be released to the
3902 * physical memory manager after the TLB has been updated.
3904 static __inline void
3905 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3906 boolean_t set_PG_ZERO)
3910 m->flags |= PG_ZERO;
3912 m->flags &= ~PG_ZERO;
3913 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3917 * Inserts the specified page table page into the specified pmap's collection
3918 * of idle page table pages. Each of a pmap's page table pages is responsible
3919 * for mapping a distinct range of virtual addresses. The pmap's collection is
3920 * ordered by this virtual address range.
3922 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3925 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3928 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3929 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3930 return (vm_radix_insert(&pmap->pm_root, mpte));
3934 * Removes the page table page mapping the specified virtual address from the
3935 * specified pmap's collection of idle page table pages, and returns it.
3936 * Otherwise, returns NULL if there is no page table page corresponding to the
3937 * specified virtual address.
3939 static __inline vm_page_t
3940 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3944 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3948 * Decrements a page table page's reference count, which is used to record the
3949 * number of valid page table entries within the page. If the reference count
3950 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3951 * page table page was unmapped and FALSE otherwise.
3953 static inline boolean_t
3954 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3958 if (m->ref_count == 0) {
3959 _pmap_unwire_ptp(pmap, va, m, free);
3966 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3972 vm_page_t pdpg, pdppg, pml4pg;
3974 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3977 * unmap the page table page
3979 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3981 MPASS(pmap_is_la57(pmap));
3982 pml5 = pmap_pml5e(pmap, va);
3984 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3985 pml5 = pmap_pml5e_u(pmap, va);
3988 } else if (m->pindex >= NUPDE + NUPDPE) {
3990 pml4 = pmap_pml4e(pmap, va);
3992 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3993 va <= VM_MAXUSER_ADDRESS) {
3994 pml4 = pmap_pml4e_u(pmap, va);
3997 } else if (m->pindex >= NUPDE) {
3999 pdp = pmap_pdpe(pmap, va);
4003 pd = pmap_pde(pmap, va);
4006 pmap_resident_count_dec(pmap, 1);
4007 if (m->pindex < NUPDE) {
4008 /* We just released a PT, unhold the matching PD */
4009 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
4010 pmap_unwire_ptp(pmap, va, pdpg, free);
4011 } else if (m->pindex < NUPDE + NUPDPE) {
4012 /* We just released a PD, unhold the matching PDP */
4013 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
4014 pmap_unwire_ptp(pmap, va, pdppg, free);
4015 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
4016 /* We just released a PDP, unhold the matching PML4 */
4017 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
4018 pmap_unwire_ptp(pmap, va, pml4pg, free);
4021 counter_u64_add(pt_page_count, -1);
4024 * Put page on a list so that it is released after
4025 * *ALL* TLB shootdown is done
4027 pmap_add_delayed_free_list(m, free, TRUE);
4031 * After removing a page table entry, this routine is used to
4032 * conditionally free the page, and manage the reference count.
4035 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
4036 struct spglist *free)
4040 if (va >= VM_MAXUSER_ADDRESS)
4042 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
4043 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
4044 return (pmap_unwire_ptp(pmap, va, mpte, free));
4048 * Release a page table page reference after a failed attempt to create a
4052 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
4054 struct spglist free;
4057 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4059 * Although "va" was never mapped, paging-structure caches
4060 * could nonetheless have entries that refer to the freed
4061 * page table pages. Invalidate those entries.
4063 pmap_invalidate_page(pmap, va);
4064 vm_page_free_pages_toq(&free, true);
4069 pmap_pinit0(pmap_t pmap)
4075 PMAP_LOCK_INIT(pmap);
4076 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
4077 pmap->pm_pmltopu = NULL;
4078 pmap->pm_cr3 = kernel_pmap->pm_cr3;
4079 /* hack to keep pmap_pti_pcid_invalidate() alive */
4080 pmap->pm_ucr3 = PMAP_NO_CR3;
4081 pmap->pm_root.rt_root = 0;
4082 CPU_ZERO(&pmap->pm_active);
4083 TAILQ_INIT(&pmap->pm_pvchunk);
4084 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4085 pmap->pm_flags = pmap_flags;
4087 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
4088 pmap->pm_pcids[i].pm_gen = 1;
4090 pmap_activate_boot(pmap);
4095 p->p_md.md_flags |= P_MD_KPTI;
4098 pmap_thread_init_invl_gen(td);
4100 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4101 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
4102 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
4108 pmap_pinit_pml4(vm_page_t pml4pg)
4110 pml4_entry_t *pm_pml4;
4113 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
4115 /* Wire in kernel global address entries. */
4116 for (i = 0; i < NKPML4E; i++) {
4117 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
4120 for (i = 0; i < ndmpdpphys; i++) {
4121 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
4125 /* install self-referential address mapping entry(s) */
4126 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
4127 X86_PG_A | X86_PG_M;
4129 /* install large map entries if configured */
4130 for (i = 0; i < lm_ents; i++)
4131 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4135 pmap_pinit_pml5(vm_page_t pml5pg)
4137 pml5_entry_t *pm_pml5;
4139 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4142 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4143 * entering all existing kernel mappings into level 5 table.
4145 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4146 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4147 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4150 * Install self-referential address mapping entry.
4152 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4153 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4154 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4158 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4160 pml4_entry_t *pm_pml4u;
4163 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4164 for (i = 0; i < NPML4EPG; i++)
4165 pm_pml4u[i] = pti_pml4[i];
4169 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4171 pml5_entry_t *pm_pml5u;
4173 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4176 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4177 * table, entering all kernel mappings needed for usermode
4178 * into level 5 table.
4180 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4181 pmap_kextract((vm_offset_t)pti_pml4) |
4182 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4183 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4187 * Initialize a preallocated and zeroed pmap structure,
4188 * such as one in a vmspace structure.
4191 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4193 vm_page_t pmltop_pg, pmltop_pgu;
4194 vm_paddr_t pmltop_phys;
4198 * allocate the page directory page
4200 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4201 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4203 counter_u64_add(pt_page_count, 1);
4205 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4206 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4209 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4210 pmap->pm_pcids[i].pm_gen = 0;
4212 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4213 pmap->pm_ucr3 = PMAP_NO_CR3;
4214 pmap->pm_pmltopu = NULL;
4216 pmap->pm_type = pm_type;
4217 if ((pmltop_pg->flags & PG_ZERO) == 0)
4218 pagezero(pmap->pm_pmltop);
4221 * Do not install the host kernel mappings in the nested page
4222 * tables. These mappings are meaningless in the guest physical
4224 * Install minimal kernel mappings in PTI case.
4228 pmap->pm_cr3 = pmltop_phys;
4229 if (pmap_is_la57(pmap))
4230 pmap_pinit_pml5(pmltop_pg);
4232 pmap_pinit_pml4(pmltop_pg);
4233 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4234 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4235 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4236 counter_u64_add(pt_page_count, 1);
4237 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4238 VM_PAGE_TO_PHYS(pmltop_pgu));
4239 if (pmap_is_la57(pmap))
4240 pmap_pinit_pml5_pti(pmltop_pgu);
4242 pmap_pinit_pml4_pti(pmltop_pgu);
4243 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4245 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4246 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4247 pkru_free_range, pmap, M_NOWAIT);
4252 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4256 pmap->pm_root.rt_root = 0;
4257 CPU_ZERO(&pmap->pm_active);
4258 TAILQ_INIT(&pmap->pm_pvchunk);
4259 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4260 pmap->pm_flags = flags;
4261 pmap->pm_eptgen = 0;
4267 pmap_pinit(pmap_t pmap)
4270 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4274 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4277 struct spglist free;
4279 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4280 if (mpg->ref_count != 0)
4283 _pmap_unwire_ptp(pmap, va, mpg, &free);
4284 pmap_invalidate_page(pmap, va);
4285 vm_page_free_pages_toq(&free, true);
4288 static pml4_entry_t *
4289 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4292 vm_pindex_t pml5index;
4299 if (!pmap_is_la57(pmap))
4300 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4302 PG_V = pmap_valid_bit(pmap);
4303 pml5index = pmap_pml5e_index(va);
4304 pml5 = &pmap->pm_pmltop[pml5index];
4305 if ((*pml5 & PG_V) == 0) {
4306 if (pmap_allocpte_nosleep(pmap, pmap_pml5e_pindex(va), lockp,
4313 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4314 pml4 = &pml4[pmap_pml4e_index(va)];
4315 if ((*pml4 & PG_V) == 0) {
4316 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4317 if (allocated && !addref)
4318 pml4pg->ref_count--;
4319 else if (!allocated && addref)
4320 pml4pg->ref_count++;
4325 static pdp_entry_t *
4326 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4335 PG_V = pmap_valid_bit(pmap);
4337 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4341 if ((*pml4 & PG_V) == 0) {
4342 /* Have to allocate a new pdp, recurse */
4343 if (pmap_allocpte_nosleep(pmap, pmap_pml4e_pindex(va), lockp,
4345 if (pmap_is_la57(pmap))
4346 pmap_allocpte_free_unref(pmap, va,
4347 pmap_pml5e(pmap, va));
4354 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4355 pdp = &pdp[pmap_pdpe_index(va)];
4356 if ((*pdp & PG_V) == 0) {
4357 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4358 if (allocated && !addref)
4360 else if (!allocated && addref)
4367 * The ptepindexes, i.e. page indices, of the page table pages encountered
4368 * while translating virtual address va are defined as follows:
4369 * - for the page table page (last level),
4370 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4371 * in other words, it is just the index of the PDE that maps the page
4373 * - for the page directory page,
4374 * ptepindex = NUPDE (number of userland PD entries) +
4375 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4376 * i.e. index of PDPE is put after the last index of PDE,
4377 * - for the page directory pointer page,
4378 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4380 * i.e. index of pml4e is put after the last index of PDPE,
4381 * - for the PML4 page (if LA57 mode is enabled),
4382 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4383 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4384 * i.e. index of pml5e is put after the last index of PML4E.
4386 * Define an order on the paging entries, where all entries of the
4387 * same height are put together, then heights are put from deepest to
4388 * root. Then ptexpindex is the sequential number of the
4389 * corresponding paging entry in this order.
4391 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4392 * LA57 paging structures even in LA48 paging mode. Moreover, the
4393 * ptepindexes are calculated as if the paging structures were 5-level
4394 * regardless of the actual mode of operation.
4396 * The root page at PML4/PML5 does not participate in this indexing scheme,
4397 * since it is statically allocated by pmap_pinit() and not by pmap_allocpte().
4400 pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4403 vm_pindex_t pml5index, pml4index;
4404 pml5_entry_t *pml5, *pml5u;
4405 pml4_entry_t *pml4, *pml4u;
4409 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4411 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4413 PG_A = pmap_accessed_bit(pmap);
4414 PG_M = pmap_modified_bit(pmap);
4415 PG_V = pmap_valid_bit(pmap);
4416 PG_RW = pmap_rw_bit(pmap);
4419 * Allocate a page table page.
4421 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4422 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
4425 if ((m->flags & PG_ZERO) == 0)
4429 * Map the pagetable page into the process address space, if
4430 * it isn't already there.
4432 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4433 MPASS(pmap_is_la57(pmap));
4435 pml5index = pmap_pml5e_index(va);
4436 pml5 = &pmap->pm_pmltop[pml5index];
4437 KASSERT((*pml5 & PG_V) == 0,
4438 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4439 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4441 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4442 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4445 pml5u = &pmap->pm_pmltopu[pml5index];
4446 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4449 } else if (ptepindex >= NUPDE + NUPDPE) {
4450 pml4index = pmap_pml4e_index(va);
4451 /* Wire up a new PDPE page */
4452 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4454 vm_page_unwire_noq(m);
4455 vm_page_free_zero(m);
4458 KASSERT((*pml4 & PG_V) == 0,
4459 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4460 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4462 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4463 pml4index < NUPML4E) {
4465 * PTI: Make all user-space mappings in the
4466 * kernel-mode page table no-execute so that
4467 * we detect any programming errors that leave
4468 * the kernel-mode page table active on return
4471 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4474 pml4u = &pmap->pm_pmltopu[pml4index];
4475 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4478 } else if (ptepindex >= NUPDE) {
4479 /* Wire up a new PDE page */
4480 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4482 vm_page_unwire_noq(m);
4483 vm_page_free_zero(m);
4486 KASSERT((*pdp & PG_V) == 0,
4487 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4488 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4490 /* Wire up a new PTE page */
4491 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4493 vm_page_unwire_noq(m);
4494 vm_page_free_zero(m);
4497 if ((*pdp & PG_V) == 0) {
4498 /* Have to allocate a new pd, recurse */
4499 if (pmap_allocpte_nosleep(pmap, pmap_pdpe_pindex(va),
4500 lockp, va) == NULL) {
4501 pmap_allocpte_free_unref(pmap, va,
4502 pmap_pml4e(pmap, va));
4503 vm_page_unwire_noq(m);
4504 vm_page_free_zero(m);
4508 /* Add reference to the pd page */
4509 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4512 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4514 /* Now we know where the page directory page is */
4515 pd = &pd[pmap_pde_index(va)];
4516 KASSERT((*pd & PG_V) == 0,
4517 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4518 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4521 pmap_resident_count_inc(pmap, 1);
4522 counter_u64_add(pt_page_count, 1);
4528 * This routine is called if the desired page table page does not exist.
4530 * If page table page allocation fails, this routine may sleep before
4531 * returning NULL. It sleeps only if a lock pointer was given. Sleep
4532 * occurs right before returning to the caller. This way, we never
4533 * drop pmap lock to sleep while a page table page has ref_count == 0,
4534 * which prevents the page from being freed under us.
4537 pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4542 m = pmap_allocpte_nosleep(pmap, ptepindex, lockp, va);
4543 if (m == NULL && lockp != NULL) {
4544 RELEASE_PV_LIST_LOCK(lockp);
4546 PMAP_ASSERT_NOT_IN_DI();
4554 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4555 struct rwlock **lockp)
4557 pdp_entry_t *pdpe, PG_V;
4560 vm_pindex_t pdpindex;
4562 PG_V = pmap_valid_bit(pmap);
4565 pdpe = pmap_pdpe(pmap, va);
4566 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4567 pde = pmap_pdpe_to_pde(pdpe, va);
4568 if (va < VM_MAXUSER_ADDRESS) {
4569 /* Add a reference to the pd page. */
4570 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4574 } else if (va < VM_MAXUSER_ADDRESS) {
4575 /* Allocate a pd page. */
4576 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4577 pdpg = pmap_allocpte_alloc(pmap, NUPDE + pdpindex, lockp, va);
4584 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4585 pde = &pde[pmap_pde_index(va)];
4587 panic("pmap_alloc_pde: missing page table page for va %#lx",
4594 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4596 vm_pindex_t ptepindex;
4597 pd_entry_t *pd, PG_V;
4600 PG_V = pmap_valid_bit(pmap);
4603 * Calculate pagetable page index
4605 ptepindex = pmap_pde_pindex(va);
4608 * Get the page directory entry
4610 pd = pmap_pde(pmap, va);
4613 * This supports switching from a 2MB page to a
4616 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4617 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4619 * Invalidation of the 2MB page mapping may have caused
4620 * the deallocation of the underlying PD page.
4627 * If the page table page is mapped, we just increment the
4628 * hold count, and activate it.
4630 if (pd != NULL && (*pd & PG_V) != 0) {
4631 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4635 * Here if the pte page isn't mapped, or if it has been
4638 m = pmap_allocpte_alloc(pmap, ptepindex, lockp, va);
4639 if (m == NULL && lockp != NULL)
4645 /***************************************************
4646 * Pmap allocation/deallocation routines.
4647 ***************************************************/
4650 * Release any resources held by the given physical map.
4651 * Called when a pmap initialized by pmap_pinit is being released.
4652 * Should only be called if the map contains no valid mappings.
4655 pmap_release(pmap_t pmap)
4660 KASSERT(pmap->pm_stats.resident_count == 0,
4661 ("pmap_release: pmap %p resident count %ld != 0",
4662 pmap, pmap->pm_stats.resident_count));
4663 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4664 ("pmap_release: pmap %p has reserved page table page(s)",
4666 KASSERT(CPU_EMPTY(&pmap->pm_active),
4667 ("releasing active pmap %p", pmap));
4669 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4671 if (pmap_is_la57(pmap)) {
4672 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4673 pmap->pm_pmltop[PML5PML5I] = 0;
4675 for (i = 0; i < NKPML4E; i++) /* KVA */
4676 pmap->pm_pmltop[KPML4BASE + i] = 0;
4677 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4678 pmap->pm_pmltop[DMPML4I + i] = 0;
4679 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4680 for (i = 0; i < lm_ents; i++) /* Large Map */
4681 pmap->pm_pmltop[LMSPML4I + i] = 0;
4684 vm_page_unwire_noq(m);
4685 vm_page_free_zero(m);
4686 counter_u64_add(pt_page_count, -1);
4688 if (pmap->pm_pmltopu != NULL) {
4689 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4691 vm_page_unwire_noq(m);
4693 counter_u64_add(pt_page_count, -1);
4695 if (pmap->pm_type == PT_X86 &&
4696 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4697 rangeset_fini(&pmap->pm_pkru);
4701 kvm_size(SYSCTL_HANDLER_ARGS)
4703 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4705 return sysctl_handle_long(oidp, &ksize, 0, req);
4707 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4708 0, 0, kvm_size, "LU",
4712 kvm_free(SYSCTL_HANDLER_ARGS)
4714 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4716 return sysctl_handle_long(oidp, &kfree, 0, req);
4718 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4719 0, 0, kvm_free, "LU",
4720 "Amount of KVM free");
4723 * Allocate physical memory for the vm_page array and map it into KVA,
4724 * attempting to back the vm_pages with domain-local memory.
4727 pmap_page_array_startup(long pages)
4730 pd_entry_t *pde, newpdir;
4731 vm_offset_t va, start, end;
4736 vm_page_array_size = pages;
4738 start = VM_MIN_KERNEL_ADDRESS;
4739 end = start + pages * sizeof(struct vm_page);
4740 for (va = start; va < end; va += NBPDR) {
4741 pfn = first_page + (va - start) / sizeof(struct vm_page);
4742 domain = vm_phys_domain(ptoa(pfn));
4743 pdpe = pmap_pdpe(kernel_pmap, va);
4744 if ((*pdpe & X86_PG_V) == 0) {
4745 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4747 pagezero((void *)PHYS_TO_DMAP(pa));
4748 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4749 X86_PG_A | X86_PG_M);
4751 pde = pmap_pdpe_to_pde(pdpe, va);
4752 if ((*pde & X86_PG_V) != 0)
4753 panic("Unexpected pde");
4754 pa = vm_phys_early_alloc(domain, NBPDR);
4755 for (i = 0; i < NPDEPG; i++)
4756 dump_add_page(pa + i * PAGE_SIZE);
4757 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4758 X86_PG_M | PG_PS | pg_g | pg_nx);
4759 pde_store(pde, newpdir);
4761 vm_page_array = (vm_page_t)start;
4765 * grow the number of kernel page table entries, if needed
4768 pmap_growkernel(vm_offset_t addr)
4772 pd_entry_t *pde, newpdir;
4775 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4778 * Return if "addr" is within the range of kernel page table pages
4779 * that were preallocated during pmap bootstrap. Moreover, leave
4780 * "kernel_vm_end" and the kernel page table as they were.
4782 * The correctness of this action is based on the following
4783 * argument: vm_map_insert() allocates contiguous ranges of the
4784 * kernel virtual address space. It calls this function if a range
4785 * ends after "kernel_vm_end". If the kernel is mapped between
4786 * "kernel_vm_end" and "addr", then the range cannot begin at
4787 * "kernel_vm_end". In fact, its beginning address cannot be less
4788 * than the kernel. Thus, there is no immediate need to allocate
4789 * any new kernel page table pages between "kernel_vm_end" and
4792 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4795 addr = roundup2(addr, NBPDR);
4796 if (addr - 1 >= vm_map_max(kernel_map))
4797 addr = vm_map_max(kernel_map);
4798 while (kernel_vm_end < addr) {
4799 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4800 if ((*pdpe & X86_PG_V) == 0) {
4801 /* We need a new PDP entry */
4802 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4803 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4804 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4806 panic("pmap_growkernel: no memory to grow kernel");
4807 if ((nkpg->flags & PG_ZERO) == 0)
4808 pmap_zero_page(nkpg);
4809 counter_u64_add(pt_page_count, 1);
4810 paddr = VM_PAGE_TO_PHYS(nkpg);
4811 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4812 X86_PG_A | X86_PG_M);
4813 continue; /* try again */
4815 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4816 if ((*pde & X86_PG_V) != 0) {
4817 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4818 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4819 kernel_vm_end = vm_map_max(kernel_map);
4825 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4826 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4829 panic("pmap_growkernel: no memory to grow kernel");
4830 if ((nkpg->flags & PG_ZERO) == 0)
4831 pmap_zero_page(nkpg);
4832 counter_u64_add(pt_page_count, 1);
4833 paddr = VM_PAGE_TO_PHYS(nkpg);
4834 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4835 pde_store(pde, newpdir);
4837 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4838 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4839 kernel_vm_end = vm_map_max(kernel_map);
4845 /***************************************************
4846 * page management routines.
4847 ***************************************************/
4849 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4850 CTASSERT(_NPCM == 3);
4851 CTASSERT(_NPCPV == 168);
4853 static __inline struct pv_chunk *
4854 pv_to_chunk(pv_entry_t pv)
4857 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4860 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4862 #define PC_FREE0 0xfffffffffffffffful
4863 #define PC_FREE1 0xfffffffffffffffful
4864 #define PC_FREE2 0x000000fffffffffful
4866 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4870 static COUNTER_U64_DEFINE_EARLY(pc_chunk_count);
4871 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD,
4872 &pc_chunk_count, "Current number of pv entry cnunks");
4874 static COUNTER_U64_DEFINE_EARLY(pc_chunk_allocs);
4875 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD,
4876 &pc_chunk_allocs, "Total number of pv entry chunks allocated");
4878 static COUNTER_U64_DEFINE_EARLY(pc_chunk_frees);
4879 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD,
4880 &pc_chunk_frees, "Total number of pv entry chunks freed");
4882 static COUNTER_U64_DEFINE_EARLY(pc_chunk_tryfail);
4883 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD,
4885 "Number of failed attempts to get a pv entry chunk page");
4887 static COUNTER_U64_DEFINE_EARLY(pv_entry_frees);
4888 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD,
4889 &pv_entry_frees, "Total number of pv entries freed");
4891 static COUNTER_U64_DEFINE_EARLY(pv_entry_allocs);
4892 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD,
4893 &pv_entry_allocs, "Total number of pv entries allocated");
4895 static COUNTER_U64_DEFINE_EARLY(pv_entry_count);
4896 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD,
4897 &pv_entry_count, "Current number of pv entries");
4899 static COUNTER_U64_DEFINE_EARLY(pv_entry_spare);
4900 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD,
4901 &pv_entry_spare, "Current number of spare pv entries");
4905 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4910 pmap_invalidate_all(pmap);
4911 if (pmap != locked_pmap)
4914 pmap_delayed_invl_finish();
4918 * We are in a serious low memory condition. Resort to
4919 * drastic measures to free some pages so we can allocate
4920 * another pv entry chunk.
4922 * Returns NULL if PV entries were reclaimed from the specified pmap.
4924 * We do not, however, unmap 2mpages because subsequent accesses will
4925 * allocate per-page pv entries until repromotion occurs, thereby
4926 * exacerbating the shortage of free pv entries.
4929 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4931 struct pv_chunks_list *pvc;
4932 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4933 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4934 struct md_page *pvh;
4936 pmap_t next_pmap, pmap;
4937 pt_entry_t *pte, tpte;
4938 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4942 struct spglist free;
4944 int bit, field, freed;
4945 bool start_di, restart;
4947 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4948 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4951 PG_G = PG_A = PG_M = PG_RW = 0;
4953 bzero(&pc_marker_b, sizeof(pc_marker_b));
4954 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4955 pc_marker = (struct pv_chunk *)&pc_marker_b;
4956 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4959 * A delayed invalidation block should already be active if
4960 * pmap_advise() or pmap_remove() called this function by way
4961 * of pmap_demote_pde_locked().
4963 start_di = pmap_not_in_di();
4965 pvc = &pv_chunks[domain];
4966 mtx_lock(&pvc->pvc_lock);
4967 pvc->active_reclaims++;
4968 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4969 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4970 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4971 SLIST_EMPTY(&free)) {
4972 next_pmap = pc->pc_pmap;
4973 if (next_pmap == NULL) {
4975 * The next chunk is a marker. However, it is
4976 * not our marker, so active_reclaims must be
4977 * > 1. Consequently, the next_chunk code
4978 * will not rotate the pv_chunks list.
4982 mtx_unlock(&pvc->pvc_lock);
4985 * A pv_chunk can only be removed from the pc_lru list
4986 * when both pc_chunks_mutex is owned and the
4987 * corresponding pmap is locked.
4989 if (pmap != next_pmap) {
4991 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4994 /* Avoid deadlock and lock recursion. */
4995 if (pmap > locked_pmap) {
4996 RELEASE_PV_LIST_LOCK(lockp);
4999 pmap_delayed_invl_start();
5000 mtx_lock(&pvc->pvc_lock);
5002 } else if (pmap != locked_pmap) {
5003 if (PMAP_TRYLOCK(pmap)) {
5005 pmap_delayed_invl_start();
5006 mtx_lock(&pvc->pvc_lock);
5009 pmap = NULL; /* pmap is not locked */
5010 mtx_lock(&pvc->pvc_lock);
5011 pc = TAILQ_NEXT(pc_marker, pc_lru);
5013 pc->pc_pmap != next_pmap)
5017 } else if (start_di)
5018 pmap_delayed_invl_start();
5019 PG_G = pmap_global_bit(pmap);
5020 PG_A = pmap_accessed_bit(pmap);
5021 PG_M = pmap_modified_bit(pmap);
5022 PG_RW = pmap_rw_bit(pmap);
5028 * Destroy every non-wired, 4 KB page mapping in the chunk.
5031 for (field = 0; field < _NPCM; field++) {
5032 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
5033 inuse != 0; inuse &= ~(1UL << bit)) {
5035 pv = &pc->pc_pventry[field * 64 + bit];
5037 pde = pmap_pde(pmap, va);
5038 if ((*pde & PG_PS) != 0)
5040 pte = pmap_pde_to_pte(pde, va);
5041 if ((*pte & PG_W) != 0)
5043 tpte = pte_load_clear(pte);
5044 if ((tpte & PG_G) != 0)
5045 pmap_invalidate_page(pmap, va);
5046 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
5047 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5049 if ((tpte & PG_A) != 0)
5050 vm_page_aflag_set(m, PGA_REFERENCED);
5051 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5052 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5054 if (TAILQ_EMPTY(&m->md.pv_list) &&
5055 (m->flags & PG_FICTITIOUS) == 0) {
5056 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5057 if (TAILQ_EMPTY(&pvh->pv_list)) {
5058 vm_page_aflag_clear(m,
5062 pmap_delayed_invl_page(m);
5063 pc->pc_map[field] |= 1UL << bit;
5064 pmap_unuse_pt(pmap, va, *pde, &free);
5069 mtx_lock(&pvc->pvc_lock);
5072 /* Every freed mapping is for a 4 KB page. */
5073 pmap_resident_count_dec(pmap, freed);
5074 PV_STAT(counter_u64_add(pv_entry_frees, freed));
5075 PV_STAT(counter_u64_add(pv_entry_spare, freed));
5076 PV_STAT(counter_u64_add(pv_entry_count, -freed));
5077 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5078 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
5079 pc->pc_map[2] == PC_FREE2) {
5080 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5081 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5082 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5083 /* Entire chunk is free; return it. */
5084 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5085 dump_drop_page(m_pc->phys_addr);
5086 mtx_lock(&pvc->pvc_lock);
5087 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5090 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5091 mtx_lock(&pvc->pvc_lock);
5092 /* One freed pv entry in locked_pmap is sufficient. */
5093 if (pmap == locked_pmap)
5096 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5097 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
5098 if (pvc->active_reclaims == 1 && pmap != NULL) {
5100 * Rotate the pv chunks list so that we do not
5101 * scan the same pv chunks that could not be
5102 * freed (because they contained a wired
5103 * and/or superpage mapping) on every
5104 * invocation of reclaim_pv_chunk().
5106 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
5107 MPASS(pc->pc_pmap != NULL);
5108 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5109 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5113 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5114 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
5115 pvc->active_reclaims--;
5116 mtx_unlock(&pvc->pvc_lock);
5117 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
5118 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
5119 m_pc = SLIST_FIRST(&free);
5120 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
5121 /* Recycle a freed page table page. */
5122 m_pc->ref_count = 1;
5124 vm_page_free_pages_toq(&free, true);
5129 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
5134 domain = PCPU_GET(domain);
5135 for (i = 0; i < vm_ndomains; i++) {
5136 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
5139 domain = (domain + 1) % vm_ndomains;
5146 * free the pv_entry back to the free list
5149 free_pv_entry(pmap_t pmap, pv_entry_t pv)
5151 struct pv_chunk *pc;
5152 int idx, field, bit;
5154 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5155 PV_STAT(counter_u64_add(pv_entry_frees, 1));
5156 PV_STAT(counter_u64_add(pv_entry_spare, 1));
5157 PV_STAT(counter_u64_add(pv_entry_count, -1));
5158 pc = pv_to_chunk(pv);
5159 idx = pv - &pc->pc_pventry[0];
5162 pc->pc_map[field] |= 1ul << bit;
5163 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5164 pc->pc_map[2] != PC_FREE2) {
5165 /* 98% of the time, pc is already at the head of the list. */
5166 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5167 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5168 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5172 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5177 free_pv_chunk_dequeued(struct pv_chunk *pc)
5181 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5182 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5183 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5184 counter_u64_add(pv_page_count, -1);
5185 /* entire chunk is free, return it */
5186 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5187 dump_drop_page(m->phys_addr);
5188 vm_page_unwire_noq(m);
5193 free_pv_chunk(struct pv_chunk *pc)
5195 struct pv_chunks_list *pvc;
5197 pvc = &pv_chunks[pc_to_domain(pc)];
5198 mtx_lock(&pvc->pvc_lock);
5199 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5200 mtx_unlock(&pvc->pvc_lock);
5201 free_pv_chunk_dequeued(pc);
5205 free_pv_chunk_batch(struct pv_chunklist *batch)
5207 struct pv_chunks_list *pvc;
5208 struct pv_chunk *pc, *npc;
5211 for (i = 0; i < vm_ndomains; i++) {
5212 if (TAILQ_EMPTY(&batch[i]))
5214 pvc = &pv_chunks[i];
5215 mtx_lock(&pvc->pvc_lock);
5216 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5217 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5219 mtx_unlock(&pvc->pvc_lock);
5222 for (i = 0; i < vm_ndomains; i++) {
5223 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5224 free_pv_chunk_dequeued(pc);
5230 * Returns a new PV entry, allocating a new PV chunk from the system when
5231 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5232 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5235 * The given PV list lock may be released.
5238 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5240 struct pv_chunks_list *pvc;
5243 struct pv_chunk *pc;
5246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5247 PV_STAT(counter_u64_add(pv_entry_allocs, 1));
5249 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5251 for (field = 0; field < _NPCM; field++) {
5252 if (pc->pc_map[field]) {
5253 bit = bsfq(pc->pc_map[field]);
5257 if (field < _NPCM) {
5258 pv = &pc->pc_pventry[field * 64 + bit];
5259 pc->pc_map[field] &= ~(1ul << bit);
5260 /* If this was the last item, move it to tail */
5261 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5262 pc->pc_map[2] == 0) {
5263 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5264 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5267 PV_STAT(counter_u64_add(pv_entry_count, 1));
5268 PV_STAT(counter_u64_add(pv_entry_spare, -1));
5272 /* No free items, allocate another chunk */
5273 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5276 if (lockp == NULL) {
5277 PV_STAT(counter_u64_add(pc_chunk_tryfail, 1));
5280 m = reclaim_pv_chunk(pmap, lockp);
5284 counter_u64_add(pv_page_count, 1);
5285 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5286 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5287 dump_add_page(m->phys_addr);
5288 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5290 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5291 pc->pc_map[1] = PC_FREE1;
5292 pc->pc_map[2] = PC_FREE2;
5293 pvc = &pv_chunks[vm_page_domain(m)];
5294 mtx_lock(&pvc->pvc_lock);
5295 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5296 mtx_unlock(&pvc->pvc_lock);
5297 pv = &pc->pc_pventry[0];
5298 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5299 PV_STAT(counter_u64_add(pv_entry_count, 1));
5300 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV - 1));
5305 * Returns the number of one bits within the given PV chunk map.
5307 * The erratas for Intel processors state that "POPCNT Instruction May
5308 * Take Longer to Execute Than Expected". It is believed that the
5309 * issue is the spurious dependency on the destination register.
5310 * Provide a hint to the register rename logic that the destination
5311 * value is overwritten, by clearing it, as suggested in the
5312 * optimization manual. It should be cheap for unaffected processors
5315 * Reference numbers for erratas are
5316 * 4th Gen Core: HSD146
5317 * 5th Gen Core: BDM85
5318 * 6th Gen Core: SKL029
5321 popcnt_pc_map_pq(uint64_t *map)
5325 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5326 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5327 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5328 : "=&r" (result), "=&r" (tmp)
5329 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5334 * Ensure that the number of spare PV entries in the specified pmap meets or
5335 * exceeds the given count, "needed".
5337 * The given PV list lock may be released.
5340 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5342 struct pv_chunks_list *pvc;
5343 struct pch new_tail[PMAP_MEMDOM];
5344 struct pv_chunk *pc;
5349 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5350 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5353 * Newly allocated PV chunks must be stored in a private list until
5354 * the required number of PV chunks have been allocated. Otherwise,
5355 * reclaim_pv_chunk() could recycle one of these chunks. In
5356 * contrast, these chunks must be added to the pmap upon allocation.
5358 for (i = 0; i < PMAP_MEMDOM; i++)
5359 TAILQ_INIT(&new_tail[i]);
5362 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5364 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5365 bit_count((bitstr_t *)pc->pc_map, 0,
5366 sizeof(pc->pc_map) * NBBY, &free);
5369 free = popcnt_pc_map_pq(pc->pc_map);
5373 if (avail >= needed)
5376 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5377 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5380 m = reclaim_pv_chunk(pmap, lockp);
5385 counter_u64_add(pv_page_count, 1);
5386 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5387 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5388 dump_add_page(m->phys_addr);
5389 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5391 pc->pc_map[0] = PC_FREE0;
5392 pc->pc_map[1] = PC_FREE1;
5393 pc->pc_map[2] = PC_FREE2;
5394 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5395 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
5396 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV));
5399 * The reclaim might have freed a chunk from the current pmap.
5400 * If that chunk contained available entries, we need to
5401 * re-count the number of available entries.
5406 for (i = 0; i < vm_ndomains; i++) {
5407 if (TAILQ_EMPTY(&new_tail[i]))
5409 pvc = &pv_chunks[i];
5410 mtx_lock(&pvc->pvc_lock);
5411 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5412 mtx_unlock(&pvc->pvc_lock);
5417 * First find and then remove the pv entry for the specified pmap and virtual
5418 * address from the specified pv list. Returns the pv entry if found and NULL
5419 * otherwise. This operation can be performed on pv lists for either 4KB or
5420 * 2MB page mappings.
5422 static __inline pv_entry_t
5423 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5427 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5428 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5429 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5438 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5439 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5440 * entries for each of the 4KB page mappings.
5443 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5444 struct rwlock **lockp)
5446 struct md_page *pvh;
5447 struct pv_chunk *pc;
5449 vm_offset_t va_last;
5453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5454 KASSERT((pa & PDRMASK) == 0,
5455 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5456 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5459 * Transfer the 2mpage's pv entry for this mapping to the first
5460 * page's pv list. Once this transfer begins, the pv list lock
5461 * must not be released until the last pv entry is reinstantiated.
5463 pvh = pa_to_pvh(pa);
5464 va = trunc_2mpage(va);
5465 pv = pmap_pvh_remove(pvh, pmap, va);
5466 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5467 m = PHYS_TO_VM_PAGE(pa);
5468 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5470 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5471 PV_STAT(counter_u64_add(pv_entry_allocs, NPTEPG - 1));
5472 va_last = va + NBPDR - PAGE_SIZE;
5474 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5475 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5476 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5477 for (field = 0; field < _NPCM; field++) {
5478 while (pc->pc_map[field]) {
5479 bit = bsfq(pc->pc_map[field]);
5480 pc->pc_map[field] &= ~(1ul << bit);
5481 pv = &pc->pc_pventry[field * 64 + bit];
5485 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5486 ("pmap_pv_demote_pde: page %p is not managed", m));
5487 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5493 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5494 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5497 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5498 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5499 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5501 PV_STAT(counter_u64_add(pv_entry_count, NPTEPG - 1));
5502 PV_STAT(counter_u64_add(pv_entry_spare, -(NPTEPG - 1)));
5505 #if VM_NRESERVLEVEL > 0
5507 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5508 * replace the many pv entries for the 4KB page mappings by a single pv entry
5509 * for the 2MB page mapping.
5512 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5513 struct rwlock **lockp)
5515 struct md_page *pvh;
5517 vm_offset_t va_last;
5520 KASSERT((pa & PDRMASK) == 0,
5521 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5522 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5525 * Transfer the first page's pv entry for this mapping to the 2mpage's
5526 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5527 * a transfer avoids the possibility that get_pv_entry() calls
5528 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5529 * mappings that is being promoted.
5531 m = PHYS_TO_VM_PAGE(pa);
5532 va = trunc_2mpage(va);
5533 pv = pmap_pvh_remove(&m->md, pmap, va);
5534 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5535 pvh = pa_to_pvh(pa);
5536 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5538 /* Free the remaining NPTEPG - 1 pv entries. */
5539 va_last = va + NBPDR - PAGE_SIZE;
5543 pmap_pvh_free(&m->md, pmap, va);
5544 } while (va < va_last);
5546 #endif /* VM_NRESERVLEVEL > 0 */
5549 * First find and then destroy the pv entry for the specified pmap and virtual
5550 * address. This operation can be performed on pv lists for either 4KB or 2MB
5554 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5558 pv = pmap_pvh_remove(pvh, pmap, va);
5559 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5560 free_pv_entry(pmap, pv);
5564 * Conditionally create the PV entry for a 4KB page mapping if the required
5565 * memory can be allocated without resorting to reclamation.
5568 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5569 struct rwlock **lockp)
5573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5574 /* Pass NULL instead of the lock pointer to disable reclamation. */
5575 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5577 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5578 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5586 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5587 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5588 * false if the PV entry cannot be allocated without resorting to reclamation.
5591 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5592 struct rwlock **lockp)
5594 struct md_page *pvh;
5598 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5599 /* Pass NULL instead of the lock pointer to disable reclamation. */
5600 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5601 NULL : lockp)) == NULL)
5604 pa = pde & PG_PS_FRAME;
5605 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5606 pvh = pa_to_pvh(pa);
5607 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5613 * Fills a page table page with mappings to consecutive physical pages.
5616 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5620 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5622 newpte += PAGE_SIZE;
5627 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5628 * mapping is invalidated.
5631 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5633 struct rwlock *lock;
5637 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5644 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5648 pt_entry_t *xpte, *ypte;
5650 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5651 xpte++, newpte += PAGE_SIZE) {
5652 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5653 printf("pmap_demote_pde: xpte %zd and newpte map "
5654 "different pages: found %#lx, expected %#lx\n",
5655 xpte - firstpte, *xpte, newpte);
5656 printf("page table dump\n");
5657 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5658 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5663 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5664 ("pmap_demote_pde: firstpte and newpte map different physical"
5671 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5672 pd_entry_t oldpde, struct rwlock **lockp)
5674 struct spglist free;
5678 sva = trunc_2mpage(va);
5679 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5680 if ((oldpde & pmap_global_bit(pmap)) == 0)
5681 pmap_invalidate_pde_page(pmap, sva, oldpde);
5682 vm_page_free_pages_toq(&free, true);
5683 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5688 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5689 struct rwlock **lockp)
5691 pd_entry_t newpde, oldpde;
5692 pt_entry_t *firstpte, newpte;
5693 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5699 PG_A = pmap_accessed_bit(pmap);
5700 PG_G = pmap_global_bit(pmap);
5701 PG_M = pmap_modified_bit(pmap);
5702 PG_RW = pmap_rw_bit(pmap);
5703 PG_V = pmap_valid_bit(pmap);
5704 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5705 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5707 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5708 in_kernel = va >= VM_MAXUSER_ADDRESS;
5710 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5711 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5714 * Invalidate the 2MB page mapping and return "failure" if the
5715 * mapping was never accessed.
5717 if ((oldpde & PG_A) == 0) {
5718 KASSERT((oldpde & PG_W) == 0,
5719 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5720 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5724 mpte = pmap_remove_pt_page(pmap, va);
5726 KASSERT((oldpde & PG_W) == 0,
5727 ("pmap_demote_pde: page table page for a wired mapping"
5731 * If the page table page is missing and the mapping
5732 * is for a kernel address, the mapping must belong to
5733 * the direct map. Page table pages are preallocated
5734 * for every other part of the kernel address space,
5735 * so the direct map region is the only part of the
5736 * kernel address space that must be handled here.
5738 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5739 va < DMAP_MAX_ADDRESS),
5740 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5743 * If the 2MB page mapping belongs to the direct map
5744 * region of the kernel's address space, then the page
5745 * allocation request specifies the highest possible
5746 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5747 * priority is normal.
5749 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5750 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5751 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5754 * If the allocation of the new page table page fails,
5755 * invalidate the 2MB page mapping and return "failure".
5758 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5762 counter_u64_add(pt_page_count, 1);
5765 mpte->ref_count = NPTEPG;
5766 pmap_resident_count_inc(pmap, 1);
5769 mptepa = VM_PAGE_TO_PHYS(mpte);
5770 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5771 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5772 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5773 ("pmap_demote_pde: oldpde is missing PG_M"));
5774 newpte = oldpde & ~PG_PS;
5775 newpte = pmap_swap_pat(pmap, newpte);
5778 * If the page table page is not leftover from an earlier promotion,
5781 if (mpte->valid == 0)
5782 pmap_fill_ptp(firstpte, newpte);
5784 pmap_demote_pde_check(firstpte, newpte);
5787 * If the mapping has changed attributes, update the page table
5790 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5791 pmap_fill_ptp(firstpte, newpte);
5794 * The spare PV entries must be reserved prior to demoting the
5795 * mapping, that is, prior to changing the PDE. Otherwise, the state
5796 * of the PDE and the PV lists will be inconsistent, which can result
5797 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5798 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5799 * PV entry for the 2MB page mapping that is being demoted.
5801 if ((oldpde & PG_MANAGED) != 0)
5802 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5805 * Demote the mapping. This pmap is locked. The old PDE has
5806 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5807 * set. Thus, there is no danger of a race with another
5808 * processor changing the setting of PG_A and/or PG_M between
5809 * the read above and the store below.
5811 if (workaround_erratum383)
5812 pmap_update_pde(pmap, va, pde, newpde);
5814 pde_store(pde, newpde);
5817 * Invalidate a stale recursive mapping of the page table page.
5820 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5823 * Demote the PV entry.
5825 if ((oldpde & PG_MANAGED) != 0)
5826 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5828 counter_u64_add(pmap_pde_demotions, 1);
5829 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5835 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5838 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5844 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5845 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5846 mpte = pmap_remove_pt_page(pmap, va);
5848 panic("pmap_remove_kernel_pde: Missing pt page.");
5850 mptepa = VM_PAGE_TO_PHYS(mpte);
5851 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5854 * If this page table page was unmapped by a promotion, then it
5855 * contains valid mappings. Zero it to invalidate those mappings.
5857 if (mpte->valid != 0)
5858 pagezero((void *)PHYS_TO_DMAP(mptepa));
5861 * Demote the mapping.
5863 if (workaround_erratum383)
5864 pmap_update_pde(pmap, va, pde, newpde);
5866 pde_store(pde, newpde);
5869 * Invalidate a stale recursive mapping of the page table page.
5871 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5875 * pmap_remove_pde: do the things to unmap a superpage in a process
5878 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5879 struct spglist *free, struct rwlock **lockp)
5881 struct md_page *pvh;
5883 vm_offset_t eva, va;
5885 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5887 PG_G = pmap_global_bit(pmap);
5888 PG_A = pmap_accessed_bit(pmap);
5889 PG_M = pmap_modified_bit(pmap);
5890 PG_RW = pmap_rw_bit(pmap);
5892 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5893 KASSERT((sva & PDRMASK) == 0,
5894 ("pmap_remove_pde: sva is not 2mpage aligned"));
5895 oldpde = pte_load_clear(pdq);
5897 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5898 if ((oldpde & PG_G) != 0)
5899 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5900 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5901 if (oldpde & PG_MANAGED) {
5902 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5903 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5904 pmap_pvh_free(pvh, pmap, sva);
5906 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5907 va < eva; va += PAGE_SIZE, m++) {
5908 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5911 vm_page_aflag_set(m, PGA_REFERENCED);
5912 if (TAILQ_EMPTY(&m->md.pv_list) &&
5913 TAILQ_EMPTY(&pvh->pv_list))
5914 vm_page_aflag_clear(m, PGA_WRITEABLE);
5915 pmap_delayed_invl_page(m);
5918 if (pmap == kernel_pmap) {
5919 pmap_remove_kernel_pde(pmap, pdq, sva);
5921 mpte = pmap_remove_pt_page(pmap, sva);
5923 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5924 ("pmap_remove_pde: pte page not promoted"));
5925 pmap_resident_count_dec(pmap, 1);
5926 KASSERT(mpte->ref_count == NPTEPG,
5927 ("pmap_remove_pde: pte page ref count error"));
5928 mpte->ref_count = 0;
5929 pmap_add_delayed_free_list(mpte, free, FALSE);
5932 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5936 * pmap_remove_pte: do the things to unmap a page in a process
5939 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5940 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5942 struct md_page *pvh;
5943 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5946 PG_A = pmap_accessed_bit(pmap);
5947 PG_M = pmap_modified_bit(pmap);
5948 PG_RW = pmap_rw_bit(pmap);
5950 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5951 oldpte = pte_load_clear(ptq);
5953 pmap->pm_stats.wired_count -= 1;
5954 pmap_resident_count_dec(pmap, 1);
5955 if (oldpte & PG_MANAGED) {
5956 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5957 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5960 vm_page_aflag_set(m, PGA_REFERENCED);
5961 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5962 pmap_pvh_free(&m->md, pmap, va);
5963 if (TAILQ_EMPTY(&m->md.pv_list) &&
5964 (m->flags & PG_FICTITIOUS) == 0) {
5965 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5966 if (TAILQ_EMPTY(&pvh->pv_list))
5967 vm_page_aflag_clear(m, PGA_WRITEABLE);
5969 pmap_delayed_invl_page(m);
5971 return (pmap_unuse_pt(pmap, va, ptepde, free));
5975 * Remove a single page from a process address space
5978 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5979 struct spglist *free)
5981 struct rwlock *lock;
5982 pt_entry_t *pte, PG_V;
5984 PG_V = pmap_valid_bit(pmap);
5985 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5986 if ((*pde & PG_V) == 0)
5988 pte = pmap_pde_to_pte(pde, va);
5989 if ((*pte & PG_V) == 0)
5992 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5995 pmap_invalidate_page(pmap, va);
5999 * Removes the specified range of addresses from the page table page.
6002 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
6003 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
6005 pt_entry_t PG_G, *pte;
6009 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6010 PG_G = pmap_global_bit(pmap);
6013 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
6017 pmap_invalidate_range(pmap, va, sva);
6022 if ((*pte & PG_G) == 0)
6026 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
6032 pmap_invalidate_range(pmap, va, sva);
6037 * Remove the given range of addresses from the specified map.
6039 * It is assumed that the start and end are properly
6040 * rounded to the page size.
6043 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6045 struct rwlock *lock;
6047 vm_offset_t va_next;
6048 pml5_entry_t *pml5e;
6049 pml4_entry_t *pml4e;
6051 pd_entry_t ptpaddr, *pde;
6052 pt_entry_t PG_G, PG_V;
6053 struct spglist free;
6056 PG_G = pmap_global_bit(pmap);
6057 PG_V = pmap_valid_bit(pmap);
6060 * Perform an unsynchronized read. This is, however, safe.
6062 if (pmap->pm_stats.resident_count == 0)
6068 pmap_delayed_invl_start();
6070 pmap_pkru_on_remove(pmap, sva, eva);
6073 * special handling of removing one page. a very
6074 * common operation and easy to short circuit some
6077 if (sva + PAGE_SIZE == eva) {
6078 pde = pmap_pde(pmap, sva);
6079 if (pde && (*pde & PG_PS) == 0) {
6080 pmap_remove_page(pmap, sva, pde, &free);
6086 for (; sva < eva; sva = va_next) {
6087 if (pmap->pm_stats.resident_count == 0)
6090 if (pmap_is_la57(pmap)) {
6091 pml5e = pmap_pml5e(pmap, sva);
6092 if ((*pml5e & PG_V) == 0) {
6093 va_next = (sva + NBPML5) & ~PML5MASK;
6098 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
6100 pml4e = pmap_pml4e(pmap, sva);
6102 if ((*pml4e & PG_V) == 0) {
6103 va_next = (sva + NBPML4) & ~PML4MASK;
6109 va_next = (sva + NBPDP) & ~PDPMASK;
6112 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6113 if ((*pdpe & PG_V) == 0)
6115 if ((*pdpe & PG_PS) != 0) {
6116 KASSERT(va_next <= eva,
6117 ("partial update of non-transparent 1G mapping "
6118 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6119 *pdpe, sva, eva, va_next));
6120 MPASS(pmap != kernel_pmap); /* XXXKIB */
6121 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
6124 pmap_resident_count_dec(pmap, NBPDP / PAGE_SIZE);
6125 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
6126 pmap_unwire_ptp(pmap, sva, mt, &free);
6131 * Calculate index for next page table.
6133 va_next = (sva + NBPDR) & ~PDRMASK;
6137 pde = pmap_pdpe_to_pde(pdpe, sva);
6141 * Weed out invalid mappings.
6147 * Check for large page.
6149 if ((ptpaddr & PG_PS) != 0) {
6151 * Are we removing the entire large page? If not,
6152 * demote the mapping and fall through.
6154 if (sva + NBPDR == va_next && eva >= va_next) {
6156 * The TLB entry for a PG_G mapping is
6157 * invalidated by pmap_remove_pde().
6159 if ((ptpaddr & PG_G) == 0)
6161 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6163 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6165 /* The large page mapping was destroyed. */
6172 * Limit our scan to either the end of the va represented
6173 * by the current page table page, or to the end of the
6174 * range being removed.
6179 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6186 pmap_invalidate_all(pmap);
6188 pmap_delayed_invl_finish();
6189 vm_page_free_pages_toq(&free, true);
6193 * Routine: pmap_remove_all
6195 * Removes this physical page from
6196 * all physical maps in which it resides.
6197 * Reflects back modify bits to the pager.
6200 * Original versions of this routine were very
6201 * inefficient because they iteratively called
6202 * pmap_remove (slow...)
6206 pmap_remove_all(vm_page_t m)
6208 struct md_page *pvh;
6211 struct rwlock *lock;
6212 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6215 struct spglist free;
6216 int pvh_gen, md_gen;
6218 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6219 ("pmap_remove_all: page %p is not managed", m));
6221 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6222 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6223 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6226 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6228 if (!PMAP_TRYLOCK(pmap)) {
6229 pvh_gen = pvh->pv_gen;
6233 if (pvh_gen != pvh->pv_gen) {
6240 pde = pmap_pde(pmap, va);
6241 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6244 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6246 if (!PMAP_TRYLOCK(pmap)) {
6247 pvh_gen = pvh->pv_gen;
6248 md_gen = m->md.pv_gen;
6252 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6258 PG_A = pmap_accessed_bit(pmap);
6259 PG_M = pmap_modified_bit(pmap);
6260 PG_RW = pmap_rw_bit(pmap);
6261 pmap_resident_count_dec(pmap, 1);
6262 pde = pmap_pde(pmap, pv->pv_va);
6263 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6264 " a 2mpage in page %p's pv list", m));
6265 pte = pmap_pde_to_pte(pde, pv->pv_va);
6266 tpte = pte_load_clear(pte);
6268 pmap->pm_stats.wired_count--;
6270 vm_page_aflag_set(m, PGA_REFERENCED);
6273 * Update the vm_page_t clean and reference bits.
6275 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6277 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6278 pmap_invalidate_page(pmap, pv->pv_va);
6279 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6281 free_pv_entry(pmap, pv);
6284 vm_page_aflag_clear(m, PGA_WRITEABLE);
6286 pmap_delayed_invl_wait(m);
6287 vm_page_free_pages_toq(&free, true);
6291 * pmap_protect_pde: do the things to protect a 2mpage in a process
6294 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6296 pd_entry_t newpde, oldpde;
6298 boolean_t anychanged;
6299 pt_entry_t PG_G, PG_M, PG_RW;
6301 PG_G = pmap_global_bit(pmap);
6302 PG_M = pmap_modified_bit(pmap);
6303 PG_RW = pmap_rw_bit(pmap);
6305 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6306 KASSERT((sva & PDRMASK) == 0,
6307 ("pmap_protect_pde: sva is not 2mpage aligned"));
6310 oldpde = newpde = *pde;
6311 if ((prot & VM_PROT_WRITE) == 0) {
6312 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6313 (PG_MANAGED | PG_M | PG_RW)) {
6314 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6315 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6318 newpde &= ~(PG_RW | PG_M);
6320 if ((prot & VM_PROT_EXECUTE) == 0)
6322 if (newpde != oldpde) {
6324 * As an optimization to future operations on this PDE, clear
6325 * PG_PROMOTED. The impending invalidation will remove any
6326 * lingering 4KB page mappings from the TLB.
6328 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6330 if ((oldpde & PG_G) != 0)
6331 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6335 return (anychanged);
6339 * Set the physical protection on the
6340 * specified range of this map as requested.
6343 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6346 vm_offset_t va_next;
6347 pml4_entry_t *pml4e;
6349 pd_entry_t ptpaddr, *pde;
6350 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6351 pt_entry_t obits, pbits;
6352 boolean_t anychanged;
6354 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6355 if (prot == VM_PROT_NONE) {
6356 pmap_remove(pmap, sva, eva);
6360 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6361 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6364 PG_G = pmap_global_bit(pmap);
6365 PG_M = pmap_modified_bit(pmap);
6366 PG_V = pmap_valid_bit(pmap);
6367 PG_RW = pmap_rw_bit(pmap);
6371 * Although this function delays and batches the invalidation
6372 * of stale TLB entries, it does not need to call
6373 * pmap_delayed_invl_start() and
6374 * pmap_delayed_invl_finish(), because it does not
6375 * ordinarily destroy mappings. Stale TLB entries from
6376 * protection-only changes need only be invalidated before the
6377 * pmap lock is released, because protection-only changes do
6378 * not destroy PV entries. Even operations that iterate over
6379 * a physical page's PV list of mappings, like
6380 * pmap_remove_write(), acquire the pmap lock for each
6381 * mapping. Consequently, for protection-only changes, the
6382 * pmap lock suffices to synchronize both page table and TLB
6385 * This function only destroys a mapping if pmap_demote_pde()
6386 * fails. In that case, stale TLB entries are immediately
6391 for (; sva < eva; sva = va_next) {
6392 pml4e = pmap_pml4e(pmap, sva);
6393 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6394 va_next = (sva + NBPML4) & ~PML4MASK;
6400 va_next = (sva + NBPDP) & ~PDPMASK;
6403 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6404 if ((*pdpe & PG_V) == 0)
6406 if ((*pdpe & PG_PS) != 0) {
6407 KASSERT(va_next <= eva,
6408 ("partial update of non-transparent 1G mapping "
6409 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6410 *pdpe, sva, eva, va_next));
6412 obits = pbits = *pdpe;
6413 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6414 MPASS(pmap != kernel_pmap); /* XXXKIB */
6415 if ((prot & VM_PROT_WRITE) == 0)
6416 pbits &= ~(PG_RW | PG_M);
6417 if ((prot & VM_PROT_EXECUTE) == 0)
6420 if (pbits != obits) {
6421 if (!atomic_cmpset_long(pdpe, obits, pbits))
6422 /* PG_PS cannot be cleared under us, */
6429 va_next = (sva + NBPDR) & ~PDRMASK;
6433 pde = pmap_pdpe_to_pde(pdpe, sva);
6437 * Weed out invalid mappings.
6443 * Check for large page.
6445 if ((ptpaddr & PG_PS) != 0) {
6447 * Are we protecting the entire large page? If not,
6448 * demote the mapping and fall through.
6450 if (sva + NBPDR == va_next && eva >= va_next) {
6452 * The TLB entry for a PG_G mapping is
6453 * invalidated by pmap_protect_pde().
6455 if (pmap_protect_pde(pmap, pde, sva, prot))
6458 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6460 * The large page mapping was destroyed.
6469 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6472 obits = pbits = *pte;
6473 if ((pbits & PG_V) == 0)
6476 if ((prot & VM_PROT_WRITE) == 0) {
6477 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6478 (PG_MANAGED | PG_M | PG_RW)) {
6479 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6482 pbits &= ~(PG_RW | PG_M);
6484 if ((prot & VM_PROT_EXECUTE) == 0)
6487 if (pbits != obits) {
6488 if (!atomic_cmpset_long(pte, obits, pbits))
6491 pmap_invalidate_page(pmap, sva);
6498 pmap_invalidate_all(pmap);
6502 #if VM_NRESERVLEVEL > 0
6504 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6507 if (pmap->pm_type != PT_EPT)
6509 return ((pde & EPT_PG_EXECUTE) != 0);
6513 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6514 * single page table page (PTP) to a single 2MB page mapping. For promotion
6515 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6516 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6517 * identical characteristics.
6520 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6521 struct rwlock **lockp)
6524 pt_entry_t *firstpte, oldpte, pa, *pte;
6525 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6529 PG_A = pmap_accessed_bit(pmap);
6530 PG_G = pmap_global_bit(pmap);
6531 PG_M = pmap_modified_bit(pmap);
6532 PG_V = pmap_valid_bit(pmap);
6533 PG_RW = pmap_rw_bit(pmap);
6534 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6535 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6537 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6540 * Examine the first PTE in the specified PTP. Abort if this PTE is
6541 * either invalid, unused, or does not map the first 4KB physical page
6542 * within a 2MB page.
6544 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6547 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6548 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6550 counter_u64_add(pmap_pde_p_failures, 1);
6551 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6552 " in pmap %p", va, pmap);
6555 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6557 * When PG_M is already clear, PG_RW can be cleared without
6558 * a TLB invalidation.
6560 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6566 * Examine each of the other PTEs in the specified PTP. Abort if this
6567 * PTE maps an unexpected 4KB physical page or does not have identical
6568 * characteristics to the first PTE.
6570 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6571 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6574 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6575 counter_u64_add(pmap_pde_p_failures, 1);
6576 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6577 " in pmap %p", va, pmap);
6580 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6582 * When PG_M is already clear, PG_RW can be cleared
6583 * without a TLB invalidation.
6585 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6588 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6589 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6590 (va & ~PDRMASK), pmap);
6592 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6593 counter_u64_add(pmap_pde_p_failures, 1);
6594 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6595 " in pmap %p", va, pmap);
6602 * Save the page table page in its current state until the PDE
6603 * mapping the superpage is demoted by pmap_demote_pde() or
6604 * destroyed by pmap_remove_pde().
6606 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6607 KASSERT(mpte >= vm_page_array &&
6608 mpte < &vm_page_array[vm_page_array_size],
6609 ("pmap_promote_pde: page table page is out of range"));
6610 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6611 ("pmap_promote_pde: page table page's pindex is wrong"));
6612 if (pmap_insert_pt_page(pmap, mpte, true)) {
6613 counter_u64_add(pmap_pde_p_failures, 1);
6615 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6621 * Promote the pv entries.
6623 if ((newpde & PG_MANAGED) != 0)
6624 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6627 * Propagate the PAT index to its proper position.
6629 newpde = pmap_swap_pat(pmap, newpde);
6632 * Map the superpage.
6634 if (workaround_erratum383)
6635 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6637 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6639 counter_u64_add(pmap_pde_promotions, 1);
6640 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6641 " in pmap %p", va, pmap);
6643 #endif /* VM_NRESERVLEVEL > 0 */
6646 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6650 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6652 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6653 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6654 ("psind %d unexpected", psind));
6655 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6656 ("unaligned phys address %#lx newpte %#lx psind %d",
6657 newpte & PG_FRAME, newpte, psind));
6658 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6659 ("unaligned va %#lx psind %d", va, psind));
6660 KASSERT(va < VM_MAXUSER_ADDRESS,
6661 ("kernel mode non-transparent superpage")); /* XXXKIB */
6662 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6663 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6665 PG_V = pmap_valid_bit(pmap);
6668 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6669 return (KERN_PROTECTION_FAILURE);
6671 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6672 pten |= pmap_pkru_get(pmap, va);
6674 if (psind == 2) { /* 1G */
6675 pml4e = pmap_pml4e(pmap, va);
6676 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6677 mp = pmap_allocpte_alloc(pmap, pmap_pml4e_pindex(va),
6681 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6682 pdpe = &pdpe[pmap_pdpe_index(va)];
6684 MPASS(origpte == 0);
6686 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6687 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6689 if ((origpte & PG_V) == 0) {
6690 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6695 } else /* (psind == 1) */ { /* 2M */
6696 pde = pmap_pde(pmap, va);
6698 mp = pmap_allocpte_alloc(pmap, pmap_pdpe_pindex(va),
6702 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6703 pde = &pde[pmap_pde_index(va)];
6705 MPASS(origpte == 0);
6708 if ((origpte & PG_V) == 0) {
6709 pdpe = pmap_pdpe(pmap, va);
6710 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6711 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6717 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6718 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6719 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6720 va, psind == 2 ? "1G" : "2M", origpte, pten));
6721 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6722 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6723 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6724 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6725 if ((origpte & PG_V) == 0)
6726 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
6728 return (KERN_SUCCESS);
6731 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6732 return (KERN_RESOURCE_SHORTAGE);
6740 * Insert the given physical page (p) at
6741 * the specified virtual address (v) in the
6742 * target physical map with the protection requested.
6744 * If specified, the page will be wired down, meaning
6745 * that the related pte can not be reclaimed.
6747 * NB: This is the only routine which MAY NOT lazy-evaluate
6748 * or lose information. That is, this routine must actually
6749 * insert this page into the given map NOW.
6751 * When destroying both a page table and PV entry, this function
6752 * performs the TLB invalidation before releasing the PV list
6753 * lock, so we do not need pmap_delayed_invl_page() calls here.
6756 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6757 u_int flags, int8_t psind)
6759 struct rwlock *lock;
6761 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6762 pt_entry_t newpte, origpte;
6769 PG_A = pmap_accessed_bit(pmap);
6770 PG_G = pmap_global_bit(pmap);
6771 PG_M = pmap_modified_bit(pmap);
6772 PG_V = pmap_valid_bit(pmap);
6773 PG_RW = pmap_rw_bit(pmap);
6775 va = trunc_page(va);
6776 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6777 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6778 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6780 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va),
6781 ("pmap_enter: managed mapping within the clean submap"));
6782 if ((m->oflags & VPO_UNMANAGED) == 0)
6783 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6784 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6785 ("pmap_enter: flags %u has reserved bits set", flags));
6786 pa = VM_PAGE_TO_PHYS(m);
6787 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6788 if ((flags & VM_PROT_WRITE) != 0)
6790 if ((prot & VM_PROT_WRITE) != 0)
6792 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6793 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6794 if ((prot & VM_PROT_EXECUTE) == 0)
6796 if ((flags & PMAP_ENTER_WIRED) != 0)
6798 if (va < VM_MAXUSER_ADDRESS)
6800 if (pmap == kernel_pmap)
6802 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6805 * Set modified bit gratuitously for writeable mappings if
6806 * the page is unmanaged. We do not want to take a fault
6807 * to do the dirty bit accounting for these mappings.
6809 if ((m->oflags & VPO_UNMANAGED) != 0) {
6810 if ((newpte & PG_RW) != 0)
6813 newpte |= PG_MANAGED;
6817 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6818 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6819 ("managed largepage va %#lx flags %#x", va, flags));
6820 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6825 /* Assert the required virtual and physical alignment. */
6826 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6827 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6828 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6834 * In the case that a page table page is not
6835 * resident, we are creating it here.
6838 pde = pmap_pde(pmap, va);
6839 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6840 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6841 pte = pmap_pde_to_pte(pde, va);
6842 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6843 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6846 } else if (va < VM_MAXUSER_ADDRESS) {
6848 * Here if the pte page isn't mapped, or if it has been
6851 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6852 mpte = pmap_allocpte_alloc(pmap, pmap_pde_pindex(va),
6853 nosleep ? NULL : &lock, va);
6854 if (mpte == NULL && nosleep) {
6855 rv = KERN_RESOURCE_SHORTAGE;
6860 panic("pmap_enter: invalid page directory va=%#lx", va);
6864 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6865 newpte |= pmap_pkru_get(pmap, va);
6868 * Is the specified virtual address already mapped?
6870 if ((origpte & PG_V) != 0) {
6872 * Wiring change, just update stats. We don't worry about
6873 * wiring PT pages as they remain resident as long as there
6874 * are valid mappings in them. Hence, if a user page is wired,
6875 * the PT page will be also.
6877 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6878 pmap->pm_stats.wired_count++;
6879 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6880 pmap->pm_stats.wired_count--;
6883 * Remove the extra PT page reference.
6887 KASSERT(mpte->ref_count > 0,
6888 ("pmap_enter: missing reference to page table page,"
6893 * Has the physical page changed?
6895 opa = origpte & PG_FRAME;
6898 * No, might be a protection or wiring change.
6900 if ((origpte & PG_MANAGED) != 0 &&
6901 (newpte & PG_RW) != 0)
6902 vm_page_aflag_set(m, PGA_WRITEABLE);
6903 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6909 * The physical page has changed. Temporarily invalidate
6910 * the mapping. This ensures that all threads sharing the
6911 * pmap keep a consistent view of the mapping, which is
6912 * necessary for the correct handling of COW faults. It
6913 * also permits reuse of the old mapping's PV entry,
6914 * avoiding an allocation.
6916 * For consistency, handle unmanaged mappings the same way.
6918 origpte = pte_load_clear(pte);
6919 KASSERT((origpte & PG_FRAME) == opa,
6920 ("pmap_enter: unexpected pa update for %#lx", va));
6921 if ((origpte & PG_MANAGED) != 0) {
6922 om = PHYS_TO_VM_PAGE(opa);
6925 * The pmap lock is sufficient to synchronize with
6926 * concurrent calls to pmap_page_test_mappings() and
6927 * pmap_ts_referenced().
6929 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6931 if ((origpte & PG_A) != 0) {
6932 pmap_invalidate_page(pmap, va);
6933 vm_page_aflag_set(om, PGA_REFERENCED);
6935 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6936 pv = pmap_pvh_remove(&om->md, pmap, va);
6938 ("pmap_enter: no PV entry for %#lx", va));
6939 if ((newpte & PG_MANAGED) == 0)
6940 free_pv_entry(pmap, pv);
6941 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6942 TAILQ_EMPTY(&om->md.pv_list) &&
6943 ((om->flags & PG_FICTITIOUS) != 0 ||
6944 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6945 vm_page_aflag_clear(om, PGA_WRITEABLE);
6948 * Since this mapping is unmanaged, assume that PG_A
6951 pmap_invalidate_page(pmap, va);
6956 * Increment the counters.
6958 if ((newpte & PG_W) != 0)
6959 pmap->pm_stats.wired_count++;
6960 pmap_resident_count_inc(pmap, 1);
6964 * Enter on the PV list if part of our managed memory.
6966 if ((newpte & PG_MANAGED) != 0) {
6968 pv = get_pv_entry(pmap, &lock);
6971 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6972 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6974 if ((newpte & PG_RW) != 0)
6975 vm_page_aflag_set(m, PGA_WRITEABLE);
6981 if ((origpte & PG_V) != 0) {
6983 origpte = pte_load_store(pte, newpte);
6984 KASSERT((origpte & PG_FRAME) == pa,
6985 ("pmap_enter: unexpected pa update for %#lx", va));
6986 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6988 if ((origpte & PG_MANAGED) != 0)
6992 * Although the PTE may still have PG_RW set, TLB
6993 * invalidation may nonetheless be required because
6994 * the PTE no longer has PG_M set.
6996 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6998 * This PTE change does not require TLB invalidation.
7002 if ((origpte & PG_A) != 0)
7003 pmap_invalidate_page(pmap, va);
7005 pte_store(pte, newpte);
7009 #if VM_NRESERVLEVEL > 0
7011 * If both the page table page and the reservation are fully
7012 * populated, then attempt promotion.
7014 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
7015 pmap_ps_enabled(pmap) &&
7016 (m->flags & PG_FICTITIOUS) == 0 &&
7017 vm_reserv_level_iffullpop(m) == 0)
7018 pmap_promote_pde(pmap, pde, va, &lock);
7030 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
7031 * if successful. Returns false if (1) a page table page cannot be allocated
7032 * without sleeping, (2) a mapping already exists at the specified virtual
7033 * address, or (3) a PV entry cannot be allocated without reclaiming another
7037 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
7038 struct rwlock **lockp)
7043 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7044 PG_V = pmap_valid_bit(pmap);
7045 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
7047 if ((m->oflags & VPO_UNMANAGED) == 0)
7048 newpde |= PG_MANAGED;
7049 if ((prot & VM_PROT_EXECUTE) == 0)
7051 if (va < VM_MAXUSER_ADDRESS)
7053 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
7054 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
7059 * Returns true if every page table entry in the specified page table page is
7063 pmap_every_pte_zero(vm_paddr_t pa)
7065 pt_entry_t *pt_end, *pte;
7067 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
7068 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
7069 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
7077 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
7078 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
7079 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
7080 * a mapping already exists at the specified virtual address. Returns
7081 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
7082 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
7083 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
7085 * The parameter "m" is only used when creating a managed, writeable mapping.
7088 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
7089 vm_page_t m, struct rwlock **lockp)
7091 struct spglist free;
7092 pd_entry_t oldpde, *pde;
7093 pt_entry_t PG_G, PG_RW, PG_V;
7096 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
7097 ("pmap_enter_pde: cannot create wired user mapping"));
7098 PG_G = pmap_global_bit(pmap);
7099 PG_RW = pmap_rw_bit(pmap);
7100 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
7101 ("pmap_enter_pde: newpde is missing PG_M"));
7102 PG_V = pmap_valid_bit(pmap);
7103 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7105 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
7107 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
7108 " in pmap %p", va, pmap);
7109 return (KERN_FAILURE);
7111 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
7112 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
7113 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7114 " in pmap %p", va, pmap);
7115 return (KERN_RESOURCE_SHORTAGE);
7119 * If pkru is not same for the whole pde range, return failure
7120 * and let vm_fault() cope. Check after pde allocation, since
7123 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
7124 pmap_abort_ptp(pmap, va, pdpg);
7125 return (KERN_FAILURE);
7127 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
7128 newpde &= ~X86_PG_PKU_MASK;
7129 newpde |= pmap_pkru_get(pmap, va);
7133 * If there are existing mappings, either abort or remove them.
7136 if ((oldpde & PG_V) != 0) {
7137 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
7138 ("pmap_enter_pde: pdpg's reference count is too low"));
7139 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
7140 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
7141 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
7144 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7145 " in pmap %p", va, pmap);
7146 return (KERN_FAILURE);
7148 /* Break the existing mapping(s). */
7150 if ((oldpde & PG_PS) != 0) {
7152 * The reference to the PD page that was acquired by
7153 * pmap_alloc_pde() ensures that it won't be freed.
7154 * However, if the PDE resulted from a promotion, then
7155 * a reserved PT page could be freed.
7157 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
7158 if ((oldpde & PG_G) == 0)
7159 pmap_invalidate_pde_page(pmap, va, oldpde);
7161 pmap_delayed_invl_start();
7162 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7164 pmap_invalidate_all(pmap);
7165 pmap_delayed_invl_finish();
7167 if (va < VM_MAXUSER_ADDRESS) {
7168 vm_page_free_pages_toq(&free, true);
7169 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7172 KASSERT(SLIST_EMPTY(&free),
7173 ("pmap_enter_pde: freed kernel page table page"));
7176 * Both pmap_remove_pde() and pmap_remove_ptes() will
7177 * leave the kernel page table page zero filled.
7179 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7180 if (pmap_insert_pt_page(pmap, mt, false))
7181 panic("pmap_enter_pde: trie insert failed");
7185 if ((newpde & PG_MANAGED) != 0) {
7187 * Abort this mapping if its PV entry could not be created.
7189 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7191 pmap_abort_ptp(pmap, va, pdpg);
7192 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7193 " in pmap %p", va, pmap);
7194 return (KERN_RESOURCE_SHORTAGE);
7196 if ((newpde & PG_RW) != 0) {
7197 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7198 vm_page_aflag_set(mt, PGA_WRITEABLE);
7203 * Increment counters.
7205 if ((newpde & PG_W) != 0)
7206 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7207 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7210 * Map the superpage. (This is not a promoted mapping; there will not
7211 * be any lingering 4KB page mappings in the TLB.)
7213 pde_store(pde, newpde);
7215 counter_u64_add(pmap_pde_mappings, 1);
7216 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7218 return (KERN_SUCCESS);
7222 * Maps a sequence of resident pages belonging to the same object.
7223 * The sequence begins with the given page m_start. This page is
7224 * mapped at the given virtual address start. Each subsequent page is
7225 * mapped at a virtual address that is offset from start by the same
7226 * amount as the page is offset from m_start within the object. The
7227 * last page in the sequence is the page with the largest offset from
7228 * m_start that can be mapped at a virtual address less than the given
7229 * virtual address end. Not every virtual page between start and end
7230 * is mapped; only those for which a resident page exists with the
7231 * corresponding offset from m_start are mapped.
7234 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7235 vm_page_t m_start, vm_prot_t prot)
7237 struct rwlock *lock;
7240 vm_pindex_t diff, psize;
7242 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7244 psize = atop(end - start);
7249 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7250 va = start + ptoa(diff);
7251 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7252 m->psind == 1 && pmap_ps_enabled(pmap) &&
7253 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7254 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7255 m = &m[NBPDR / PAGE_SIZE - 1];
7257 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7259 m = TAILQ_NEXT(m, listq);
7267 * this code makes some *MAJOR* assumptions:
7268 * 1. Current pmap & pmap exists.
7271 * 4. No page table pages.
7272 * but is *MUCH* faster than pmap_enter...
7276 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7278 struct rwlock *lock;
7282 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7289 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7290 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7292 pt_entry_t newpte, *pte, PG_V;
7294 KASSERT(!VA_IS_CLEANMAP(va) ||
7295 (m->oflags & VPO_UNMANAGED) != 0,
7296 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7297 PG_V = pmap_valid_bit(pmap);
7298 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7301 * In the case that a page table page is not
7302 * resident, we are creating it here.
7304 if (va < VM_MAXUSER_ADDRESS) {
7305 vm_pindex_t ptepindex;
7309 * Calculate pagetable page index
7311 ptepindex = pmap_pde_pindex(va);
7312 if (mpte && (mpte->pindex == ptepindex)) {
7316 * Get the page directory entry
7318 ptepa = pmap_pde(pmap, va);
7321 * If the page table page is mapped, we just increment
7322 * the hold count, and activate it. Otherwise, we
7323 * attempt to allocate a page table page. If this
7324 * attempt fails, we don't retry. Instead, we give up.
7326 if (ptepa && (*ptepa & PG_V) != 0) {
7329 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7333 * Pass NULL instead of the PV list lock
7334 * pointer, because we don't intend to sleep.
7336 mpte = pmap_allocpte_alloc(pmap, ptepindex,
7342 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7343 pte = &pte[pmap_pte_index(va)];
7355 * Enter on the PV list if part of our managed memory.
7357 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7358 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7360 pmap_abort_ptp(pmap, va, mpte);
7365 * Increment counters
7367 pmap_resident_count_inc(pmap, 1);
7369 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7370 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7371 if ((m->oflags & VPO_UNMANAGED) == 0)
7372 newpte |= PG_MANAGED;
7373 if ((prot & VM_PROT_EXECUTE) == 0)
7375 if (va < VM_MAXUSER_ADDRESS)
7376 newpte |= PG_U | pmap_pkru_get(pmap, va);
7377 pte_store(pte, newpte);
7382 * Make a temporary mapping for a physical address. This is only intended
7383 * to be used for panic dumps.
7386 pmap_kenter_temporary(vm_paddr_t pa, int i)
7390 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7391 pmap_kenter(va, pa);
7393 return ((void *)crashdumpmap);
7397 * This code maps large physical mmap regions into the
7398 * processor address space. Note that some shortcuts
7399 * are taken, but the code works.
7402 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7403 vm_pindex_t pindex, vm_size_t size)
7406 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7407 vm_paddr_t pa, ptepa;
7411 PG_A = pmap_accessed_bit(pmap);
7412 PG_M = pmap_modified_bit(pmap);
7413 PG_V = pmap_valid_bit(pmap);
7414 PG_RW = pmap_rw_bit(pmap);
7416 VM_OBJECT_ASSERT_WLOCKED(object);
7417 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7418 ("pmap_object_init_pt: non-device object"));
7419 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7420 if (!pmap_ps_enabled(pmap))
7422 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7424 p = vm_page_lookup(object, pindex);
7425 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7426 ("pmap_object_init_pt: invalid page %p", p));
7427 pat_mode = p->md.pat_mode;
7430 * Abort the mapping if the first page is not physically
7431 * aligned to a 2MB page boundary.
7433 ptepa = VM_PAGE_TO_PHYS(p);
7434 if (ptepa & (NBPDR - 1))
7438 * Skip the first page. Abort the mapping if the rest of
7439 * the pages are not physically contiguous or have differing
7440 * memory attributes.
7442 p = TAILQ_NEXT(p, listq);
7443 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7445 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7446 ("pmap_object_init_pt: invalid page %p", p));
7447 if (pa != VM_PAGE_TO_PHYS(p) ||
7448 pat_mode != p->md.pat_mode)
7450 p = TAILQ_NEXT(p, listq);
7454 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7455 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7456 * will not affect the termination of this loop.
7459 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7460 pa < ptepa + size; pa += NBPDR) {
7461 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7464 * The creation of mappings below is only an
7465 * optimization. If a page directory page
7466 * cannot be allocated without blocking,
7467 * continue on to the next mapping rather than
7473 if ((*pde & PG_V) == 0) {
7474 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7475 PG_U | PG_RW | PG_V);
7476 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7477 counter_u64_add(pmap_pde_mappings, 1);
7479 /* Continue on if the PDE is already valid. */
7481 KASSERT(pdpg->ref_count > 0,
7482 ("pmap_object_init_pt: missing reference "
7483 "to page directory page, va: 0x%lx", addr));
7492 * Clear the wired attribute from the mappings for the specified range of
7493 * addresses in the given pmap. Every valid mapping within that range
7494 * must have the wired attribute set. In contrast, invalid mappings
7495 * cannot have the wired attribute set, so they are ignored.
7497 * The wired attribute of the page table entry is not a hardware
7498 * feature, so there is no need to invalidate any TLB entries.
7499 * Since pmap_demote_pde() for the wired entry must never fail,
7500 * pmap_delayed_invl_start()/finish() calls around the
7501 * function are not needed.
7504 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7506 vm_offset_t va_next;
7507 pml4_entry_t *pml4e;
7510 pt_entry_t *pte, PG_V, PG_G;
7512 PG_V = pmap_valid_bit(pmap);
7513 PG_G = pmap_global_bit(pmap);
7515 for (; sva < eva; sva = va_next) {
7516 pml4e = pmap_pml4e(pmap, sva);
7517 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7518 va_next = (sva + NBPML4) & ~PML4MASK;
7524 va_next = (sva + NBPDP) & ~PDPMASK;
7527 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7528 if ((*pdpe & PG_V) == 0)
7530 if ((*pdpe & PG_PS) != 0) {
7531 KASSERT(va_next <= eva,
7532 ("partial update of non-transparent 1G mapping "
7533 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7534 *pdpe, sva, eva, va_next));
7535 MPASS(pmap != kernel_pmap); /* XXXKIB */
7536 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7537 atomic_clear_long(pdpe, PG_W);
7538 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7542 va_next = (sva + NBPDR) & ~PDRMASK;
7545 pde = pmap_pdpe_to_pde(pdpe, sva);
7546 if ((*pde & PG_V) == 0)
7548 if ((*pde & PG_PS) != 0) {
7549 if ((*pde & PG_W) == 0)
7550 panic("pmap_unwire: pde %#jx is missing PG_W",
7554 * Are we unwiring the entire large page? If not,
7555 * demote the mapping and fall through.
7557 if (sva + NBPDR == va_next && eva >= va_next) {
7558 atomic_clear_long(pde, PG_W);
7559 pmap->pm_stats.wired_count -= NBPDR /
7562 } else if (!pmap_demote_pde(pmap, pde, sva))
7563 panic("pmap_unwire: demotion failed");
7567 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7569 if ((*pte & PG_V) == 0)
7571 if ((*pte & PG_W) == 0)
7572 panic("pmap_unwire: pte %#jx is missing PG_W",
7576 * PG_W must be cleared atomically. Although the pmap
7577 * lock synchronizes access to PG_W, another processor
7578 * could be setting PG_M and/or PG_A concurrently.
7580 atomic_clear_long(pte, PG_W);
7581 pmap->pm_stats.wired_count--;
7588 * Copy the range specified by src_addr/len
7589 * from the source map to the range dst_addr/len
7590 * in the destination map.
7592 * This routine is only advisory and need not do anything.
7595 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7596 vm_offset_t src_addr)
7598 struct rwlock *lock;
7599 pml4_entry_t *pml4e;
7601 pd_entry_t *pde, srcptepaddr;
7602 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7603 vm_offset_t addr, end_addr, va_next;
7604 vm_page_t dst_pdpg, dstmpte, srcmpte;
7606 if (dst_addr != src_addr)
7609 if (dst_pmap->pm_type != src_pmap->pm_type)
7613 * EPT page table entries that require emulation of A/D bits are
7614 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7615 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7616 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7617 * implementations flag an EPT misconfiguration for exec-only
7618 * mappings we skip this function entirely for emulated pmaps.
7620 if (pmap_emulate_ad_bits(dst_pmap))
7623 end_addr = src_addr + len;
7625 if (dst_pmap < src_pmap) {
7626 PMAP_LOCK(dst_pmap);
7627 PMAP_LOCK(src_pmap);
7629 PMAP_LOCK(src_pmap);
7630 PMAP_LOCK(dst_pmap);
7633 PG_A = pmap_accessed_bit(dst_pmap);
7634 PG_M = pmap_modified_bit(dst_pmap);
7635 PG_V = pmap_valid_bit(dst_pmap);
7637 for (addr = src_addr; addr < end_addr; addr = va_next) {
7638 KASSERT(addr < UPT_MIN_ADDRESS,
7639 ("pmap_copy: invalid to pmap_copy page tables"));
7641 pml4e = pmap_pml4e(src_pmap, addr);
7642 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7643 va_next = (addr + NBPML4) & ~PML4MASK;
7649 va_next = (addr + NBPDP) & ~PDPMASK;
7652 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7653 if ((*pdpe & PG_V) == 0)
7655 if ((*pdpe & PG_PS) != 0) {
7656 KASSERT(va_next <= end_addr,
7657 ("partial update of non-transparent 1G mapping "
7658 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7659 *pdpe, addr, end_addr, va_next));
7660 MPASS((addr & PDPMASK) == 0);
7661 MPASS((*pdpe & PG_MANAGED) == 0);
7662 srcptepaddr = *pdpe;
7663 pdpe = pmap_pdpe(dst_pmap, addr);
7665 if (pmap_allocpte_alloc(dst_pmap,
7666 pmap_pml4e_pindex(addr), NULL, addr) ==
7669 pdpe = pmap_pdpe(dst_pmap, addr);
7671 pml4e = pmap_pml4e(dst_pmap, addr);
7672 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7673 dst_pdpg->ref_count++;
7676 ("1G mapping present in dst pmap "
7677 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7678 *pdpe, addr, end_addr, va_next));
7679 *pdpe = srcptepaddr & ~PG_W;
7680 pmap_resident_count_inc(dst_pmap, NBPDP / PAGE_SIZE);
7684 va_next = (addr + NBPDR) & ~PDRMASK;
7688 pde = pmap_pdpe_to_pde(pdpe, addr);
7690 if (srcptepaddr == 0)
7693 if (srcptepaddr & PG_PS) {
7694 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7696 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7699 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7700 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7701 PMAP_ENTER_NORECLAIM, &lock))) {
7702 *pde = srcptepaddr & ~PG_W;
7703 pmap_resident_count_inc(dst_pmap, NBPDR /
7705 counter_u64_add(pmap_pde_mappings, 1);
7707 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7711 srcptepaddr &= PG_FRAME;
7712 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7713 KASSERT(srcmpte->ref_count > 0,
7714 ("pmap_copy: source page table page is unused"));
7716 if (va_next > end_addr)
7719 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7720 src_pte = &src_pte[pmap_pte_index(addr)];
7722 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7726 * We only virtual copy managed pages.
7728 if ((ptetemp & PG_MANAGED) == 0)
7731 if (dstmpte != NULL) {
7732 KASSERT(dstmpte->pindex ==
7733 pmap_pde_pindex(addr),
7734 ("dstmpte pindex/addr mismatch"));
7735 dstmpte->ref_count++;
7736 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7739 dst_pte = (pt_entry_t *)
7740 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7741 dst_pte = &dst_pte[pmap_pte_index(addr)];
7742 if (*dst_pte == 0 &&
7743 pmap_try_insert_pv_entry(dst_pmap, addr,
7744 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7746 * Clear the wired, modified, and accessed
7747 * (referenced) bits during the copy.
7749 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7750 pmap_resident_count_inc(dst_pmap, 1);
7752 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7755 /* Have we copied all of the valid mappings? */
7756 if (dstmpte->ref_count >= srcmpte->ref_count)
7763 PMAP_UNLOCK(src_pmap);
7764 PMAP_UNLOCK(dst_pmap);
7768 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7772 if (dst_pmap->pm_type != src_pmap->pm_type ||
7773 dst_pmap->pm_type != PT_X86 ||
7774 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7777 if (dst_pmap < src_pmap) {
7778 PMAP_LOCK(dst_pmap);
7779 PMAP_LOCK(src_pmap);
7781 PMAP_LOCK(src_pmap);
7782 PMAP_LOCK(dst_pmap);
7784 error = pmap_pkru_copy(dst_pmap, src_pmap);
7785 /* Clean up partial copy on failure due to no memory. */
7786 if (error == ENOMEM)
7787 pmap_pkru_deassign_all(dst_pmap);
7788 PMAP_UNLOCK(src_pmap);
7789 PMAP_UNLOCK(dst_pmap);
7790 if (error != ENOMEM)
7798 * Zero the specified hardware page.
7801 pmap_zero_page(vm_page_t m)
7803 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7805 pagezero((void *)va);
7809 * Zero an an area within a single hardware page. off and size must not
7810 * cover an area beyond a single hardware page.
7813 pmap_zero_page_area(vm_page_t m, int off, int size)
7815 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7817 if (off == 0 && size == PAGE_SIZE)
7818 pagezero((void *)va);
7820 bzero((char *)va + off, size);
7824 * Copy 1 specified hardware page to another.
7827 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7829 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7830 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7832 pagecopy((void *)src, (void *)dst);
7835 int unmapped_buf_allowed = 1;
7838 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7839 vm_offset_t b_offset, int xfersize)
7843 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7847 while (xfersize > 0) {
7848 a_pg_offset = a_offset & PAGE_MASK;
7849 pages[0] = ma[a_offset >> PAGE_SHIFT];
7850 b_pg_offset = b_offset & PAGE_MASK;
7851 pages[1] = mb[b_offset >> PAGE_SHIFT];
7852 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7853 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7854 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7855 a_cp = (char *)vaddr[0] + a_pg_offset;
7856 b_cp = (char *)vaddr[1] + b_pg_offset;
7857 bcopy(a_cp, b_cp, cnt);
7858 if (__predict_false(mapped))
7859 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7867 * Returns true if the pmap's pv is one of the first
7868 * 16 pvs linked to from this page. This count may
7869 * be changed upwards or downwards in the future; it
7870 * is only necessary that true be returned for a small
7871 * subset of pmaps for proper page aging.
7874 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7876 struct md_page *pvh;
7877 struct rwlock *lock;
7882 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7883 ("pmap_page_exists_quick: page %p is not managed", m));
7885 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7887 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7888 if (PV_PMAP(pv) == pmap) {
7896 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7897 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7898 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7899 if (PV_PMAP(pv) == pmap) {
7913 * pmap_page_wired_mappings:
7915 * Return the number of managed mappings to the given physical page
7919 pmap_page_wired_mappings(vm_page_t m)
7921 struct rwlock *lock;
7922 struct md_page *pvh;
7926 int count, md_gen, pvh_gen;
7928 if ((m->oflags & VPO_UNMANAGED) != 0)
7930 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7934 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7936 if (!PMAP_TRYLOCK(pmap)) {
7937 md_gen = m->md.pv_gen;
7941 if (md_gen != m->md.pv_gen) {
7946 pte = pmap_pte(pmap, pv->pv_va);
7947 if ((*pte & PG_W) != 0)
7951 if ((m->flags & PG_FICTITIOUS) == 0) {
7952 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7953 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7955 if (!PMAP_TRYLOCK(pmap)) {
7956 md_gen = m->md.pv_gen;
7957 pvh_gen = pvh->pv_gen;
7961 if (md_gen != m->md.pv_gen ||
7962 pvh_gen != pvh->pv_gen) {
7967 pte = pmap_pde(pmap, pv->pv_va);
7968 if ((*pte & PG_W) != 0)
7978 * Returns TRUE if the given page is mapped individually or as part of
7979 * a 2mpage. Otherwise, returns FALSE.
7982 pmap_page_is_mapped(vm_page_t m)
7984 struct rwlock *lock;
7987 if ((m->oflags & VPO_UNMANAGED) != 0)
7989 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7991 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7992 ((m->flags & PG_FICTITIOUS) == 0 &&
7993 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7999 * Destroy all managed, non-wired mappings in the given user-space
8000 * pmap. This pmap cannot be active on any processor besides the
8003 * This function cannot be applied to the kernel pmap. Moreover, it
8004 * is not intended for general use. It is only to be used during
8005 * process termination. Consequently, it can be implemented in ways
8006 * that make it faster than pmap_remove(). First, it can more quickly
8007 * destroy mappings by iterating over the pmap's collection of PV
8008 * entries, rather than searching the page table. Second, it doesn't
8009 * have to test and clear the page table entries atomically, because
8010 * no processor is currently accessing the user address space. In
8011 * particular, a page table entry's dirty bit won't change state once
8012 * this function starts.
8014 * Although this function destroys all of the pmap's managed,
8015 * non-wired mappings, it can delay and batch the invalidation of TLB
8016 * entries without calling pmap_delayed_invl_start() and
8017 * pmap_delayed_invl_finish(). Because the pmap is not active on
8018 * any other processor, none of these TLB entries will ever be used
8019 * before their eventual invalidation. Consequently, there is no need
8020 * for either pmap_remove_all() or pmap_remove_write() to wait for
8021 * that eventual TLB invalidation.
8024 pmap_remove_pages(pmap_t pmap)
8027 pt_entry_t *pte, tpte;
8028 pt_entry_t PG_M, PG_RW, PG_V;
8029 struct spglist free;
8030 struct pv_chunklist free_chunks[PMAP_MEMDOM];
8031 vm_page_t m, mpte, mt;
8033 struct md_page *pvh;
8034 struct pv_chunk *pc, *npc;
8035 struct rwlock *lock;
8037 uint64_t inuse, bitmask;
8038 int allfree, field, freed, i, idx;
8039 boolean_t superpage;
8043 * Assert that the given pmap is only active on the current
8044 * CPU. Unfortunately, we cannot block another CPU from
8045 * activating the pmap while this function is executing.
8047 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
8050 cpuset_t other_cpus;
8052 other_cpus = all_cpus;
8054 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
8055 CPU_AND(&other_cpus, &pmap->pm_active);
8057 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
8062 PG_M = pmap_modified_bit(pmap);
8063 PG_V = pmap_valid_bit(pmap);
8064 PG_RW = pmap_rw_bit(pmap);
8066 for (i = 0; i < PMAP_MEMDOM; i++)
8067 TAILQ_INIT(&free_chunks[i]);
8070 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
8073 for (field = 0; field < _NPCM; field++) {
8074 inuse = ~pc->pc_map[field] & pc_freemask[field];
8075 while (inuse != 0) {
8077 bitmask = 1UL << bit;
8078 idx = field * 64 + bit;
8079 pv = &pc->pc_pventry[idx];
8082 pte = pmap_pdpe(pmap, pv->pv_va);
8084 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
8086 if ((tpte & (PG_PS | PG_V)) == PG_V) {
8089 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
8091 pte = &pte[pmap_pte_index(pv->pv_va)];
8095 * Keep track whether 'tpte' is a
8096 * superpage explicitly instead of
8097 * relying on PG_PS being set.
8099 * This is because PG_PS is numerically
8100 * identical to PG_PTE_PAT and thus a
8101 * regular page could be mistaken for
8107 if ((tpte & PG_V) == 0) {
8108 panic("bad pte va %lx pte %lx",
8113 * We cannot remove wired pages from a process' mapping at this time
8121 pa = tpte & PG_PS_FRAME;
8123 pa = tpte & PG_FRAME;
8125 m = PHYS_TO_VM_PAGE(pa);
8126 KASSERT(m->phys_addr == pa,
8127 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
8128 m, (uintmax_t)m->phys_addr,
8131 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
8132 m < &vm_page_array[vm_page_array_size],
8133 ("pmap_remove_pages: bad tpte %#jx",
8139 * Update the vm_page_t clean/reference bits.
8141 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8143 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8149 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
8152 pc->pc_map[field] |= bitmask;
8154 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
8155 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
8156 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8158 if (TAILQ_EMPTY(&pvh->pv_list)) {
8159 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8160 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8161 TAILQ_EMPTY(&mt->md.pv_list))
8162 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8164 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8166 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8167 ("pmap_remove_pages: pte page not promoted"));
8168 pmap_resident_count_dec(pmap, 1);
8169 KASSERT(mpte->ref_count == NPTEPG,
8170 ("pmap_remove_pages: pte page reference count error"));
8171 mpte->ref_count = 0;
8172 pmap_add_delayed_free_list(mpte, &free, FALSE);
8175 pmap_resident_count_dec(pmap, 1);
8176 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8178 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8179 TAILQ_EMPTY(&m->md.pv_list) &&
8180 (m->flags & PG_FICTITIOUS) == 0) {
8181 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8182 if (TAILQ_EMPTY(&pvh->pv_list))
8183 vm_page_aflag_clear(m, PGA_WRITEABLE);
8186 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8190 PV_STAT(counter_u64_add(pv_entry_frees, freed));
8191 PV_STAT(counter_u64_add(pv_entry_spare, freed));
8192 PV_STAT(counter_u64_add(pv_entry_count, -freed));
8194 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8195 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8200 pmap_invalidate_all(pmap);
8201 pmap_pkru_deassign_all(pmap);
8202 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8204 vm_page_free_pages_toq(&free, true);
8208 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8210 struct rwlock *lock;
8212 struct md_page *pvh;
8213 pt_entry_t *pte, mask;
8214 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8216 int md_gen, pvh_gen;
8220 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8223 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8225 if (!PMAP_TRYLOCK(pmap)) {
8226 md_gen = m->md.pv_gen;
8230 if (md_gen != m->md.pv_gen) {
8235 pte = pmap_pte(pmap, pv->pv_va);
8238 PG_M = pmap_modified_bit(pmap);
8239 PG_RW = pmap_rw_bit(pmap);
8240 mask |= PG_RW | PG_M;
8243 PG_A = pmap_accessed_bit(pmap);
8244 PG_V = pmap_valid_bit(pmap);
8245 mask |= PG_V | PG_A;
8247 rv = (*pte & mask) == mask;
8252 if ((m->flags & PG_FICTITIOUS) == 0) {
8253 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8254 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8256 if (!PMAP_TRYLOCK(pmap)) {
8257 md_gen = m->md.pv_gen;
8258 pvh_gen = pvh->pv_gen;
8262 if (md_gen != m->md.pv_gen ||
8263 pvh_gen != pvh->pv_gen) {
8268 pte = pmap_pde(pmap, pv->pv_va);
8271 PG_M = pmap_modified_bit(pmap);
8272 PG_RW = pmap_rw_bit(pmap);
8273 mask |= PG_RW | PG_M;
8276 PG_A = pmap_accessed_bit(pmap);
8277 PG_V = pmap_valid_bit(pmap);
8278 mask |= PG_V | PG_A;
8280 rv = (*pte & mask) == mask;
8294 * Return whether or not the specified physical page was modified
8295 * in any physical maps.
8298 pmap_is_modified(vm_page_t m)
8301 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8302 ("pmap_is_modified: page %p is not managed", m));
8305 * If the page is not busied then this check is racy.
8307 if (!pmap_page_is_write_mapped(m))
8309 return (pmap_page_test_mappings(m, FALSE, TRUE));
8313 * pmap_is_prefaultable:
8315 * Return whether or not the specified virtual address is eligible
8319 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8322 pt_entry_t *pte, PG_V;
8325 PG_V = pmap_valid_bit(pmap);
8328 pde = pmap_pde(pmap, addr);
8329 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8330 pte = pmap_pde_to_pte(pde, addr);
8331 rv = (*pte & PG_V) == 0;
8338 * pmap_is_referenced:
8340 * Return whether or not the specified physical page was referenced
8341 * in any physical maps.
8344 pmap_is_referenced(vm_page_t m)
8347 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8348 ("pmap_is_referenced: page %p is not managed", m));
8349 return (pmap_page_test_mappings(m, TRUE, FALSE));
8353 * Clear the write and modified bits in each of the given page's mappings.
8356 pmap_remove_write(vm_page_t m)
8358 struct md_page *pvh;
8360 struct rwlock *lock;
8361 pv_entry_t next_pv, pv;
8363 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8365 int pvh_gen, md_gen;
8367 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8368 ("pmap_remove_write: page %p is not managed", m));
8370 vm_page_assert_busied(m);
8371 if (!pmap_page_is_write_mapped(m))
8374 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8375 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8376 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8379 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8381 if (!PMAP_TRYLOCK(pmap)) {
8382 pvh_gen = pvh->pv_gen;
8386 if (pvh_gen != pvh->pv_gen) {
8392 PG_RW = pmap_rw_bit(pmap);
8394 pde = pmap_pde(pmap, va);
8395 if ((*pde & PG_RW) != 0)
8396 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8397 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8398 ("inconsistent pv lock %p %p for page %p",
8399 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8402 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8404 if (!PMAP_TRYLOCK(pmap)) {
8405 pvh_gen = pvh->pv_gen;
8406 md_gen = m->md.pv_gen;
8410 if (pvh_gen != pvh->pv_gen ||
8411 md_gen != m->md.pv_gen) {
8417 PG_M = pmap_modified_bit(pmap);
8418 PG_RW = pmap_rw_bit(pmap);
8419 pde = pmap_pde(pmap, pv->pv_va);
8420 KASSERT((*pde & PG_PS) == 0,
8421 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8423 pte = pmap_pde_to_pte(pde, pv->pv_va);
8426 if (oldpte & PG_RW) {
8427 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8430 if ((oldpte & PG_M) != 0)
8432 pmap_invalidate_page(pmap, pv->pv_va);
8437 vm_page_aflag_clear(m, PGA_WRITEABLE);
8438 pmap_delayed_invl_wait(m);
8441 static __inline boolean_t
8442 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8445 if (!pmap_emulate_ad_bits(pmap))
8448 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8451 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8452 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8453 * if the EPT_PG_WRITE bit is set.
8455 if ((pte & EPT_PG_WRITE) != 0)
8459 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8461 if ((pte & EPT_PG_EXECUTE) == 0 ||
8462 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8469 * pmap_ts_referenced:
8471 * Return a count of reference bits for a page, clearing those bits.
8472 * It is not necessary for every reference bit to be cleared, but it
8473 * is necessary that 0 only be returned when there are truly no
8474 * reference bits set.
8476 * As an optimization, update the page's dirty field if a modified bit is
8477 * found while counting reference bits. This opportunistic update can be
8478 * performed at low cost and can eliminate the need for some future calls
8479 * to pmap_is_modified(). However, since this function stops after
8480 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8481 * dirty pages. Those dirty pages will only be detected by a future call
8482 * to pmap_is_modified().
8484 * A DI block is not needed within this function, because
8485 * invalidations are performed before the PV list lock is
8489 pmap_ts_referenced(vm_page_t m)
8491 struct md_page *pvh;
8494 struct rwlock *lock;
8495 pd_entry_t oldpde, *pde;
8496 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8499 int cleared, md_gen, not_cleared, pvh_gen;
8500 struct spglist free;
8503 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8504 ("pmap_ts_referenced: page %p is not managed", m));
8507 pa = VM_PAGE_TO_PHYS(m);
8508 lock = PHYS_TO_PV_LIST_LOCK(pa);
8509 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8513 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8514 goto small_mappings;
8520 if (!PMAP_TRYLOCK(pmap)) {
8521 pvh_gen = pvh->pv_gen;
8525 if (pvh_gen != pvh->pv_gen) {
8530 PG_A = pmap_accessed_bit(pmap);
8531 PG_M = pmap_modified_bit(pmap);
8532 PG_RW = pmap_rw_bit(pmap);
8534 pde = pmap_pde(pmap, pv->pv_va);
8536 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8538 * Although "oldpde" is mapping a 2MB page, because
8539 * this function is called at a 4KB page granularity,
8540 * we only update the 4KB page under test.
8544 if ((oldpde & PG_A) != 0) {
8546 * Since this reference bit is shared by 512 4KB
8547 * pages, it should not be cleared every time it is
8548 * tested. Apply a simple "hash" function on the
8549 * physical page number, the virtual superpage number,
8550 * and the pmap address to select one 4KB page out of
8551 * the 512 on which testing the reference bit will
8552 * result in clearing that reference bit. This
8553 * function is designed to avoid the selection of the
8554 * same 4KB page for every 2MB page mapping.
8556 * On demotion, a mapping that hasn't been referenced
8557 * is simply destroyed. To avoid the possibility of a
8558 * subsequent page fault on a demoted wired mapping,
8559 * always leave its reference bit set. Moreover,
8560 * since the superpage is wired, the current state of
8561 * its reference bit won't affect page replacement.
8563 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8564 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8565 (oldpde & PG_W) == 0) {
8566 if (safe_to_clear_referenced(pmap, oldpde)) {
8567 atomic_clear_long(pde, PG_A);
8568 pmap_invalidate_page(pmap, pv->pv_va);
8570 } else if (pmap_demote_pde_locked(pmap, pde,
8571 pv->pv_va, &lock)) {
8573 * Remove the mapping to a single page
8574 * so that a subsequent access may
8575 * repromote. Since the underlying
8576 * page table page is fully populated,
8577 * this removal never frees a page
8581 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8583 pte = pmap_pde_to_pte(pde, va);
8584 pmap_remove_pte(pmap, pte, va, *pde,
8586 pmap_invalidate_page(pmap, va);
8592 * The superpage mapping was removed
8593 * entirely and therefore 'pv' is no
8601 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8602 ("inconsistent pv lock %p %p for page %p",
8603 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8608 /* Rotate the PV list if it has more than one entry. */
8609 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8610 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8611 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8614 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8616 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8618 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8625 if (!PMAP_TRYLOCK(pmap)) {
8626 pvh_gen = pvh->pv_gen;
8627 md_gen = m->md.pv_gen;
8631 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8636 PG_A = pmap_accessed_bit(pmap);
8637 PG_M = pmap_modified_bit(pmap);
8638 PG_RW = pmap_rw_bit(pmap);
8639 pde = pmap_pde(pmap, pv->pv_va);
8640 KASSERT((*pde & PG_PS) == 0,
8641 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8643 pte = pmap_pde_to_pte(pde, pv->pv_va);
8644 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8646 if ((*pte & PG_A) != 0) {
8647 if (safe_to_clear_referenced(pmap, *pte)) {
8648 atomic_clear_long(pte, PG_A);
8649 pmap_invalidate_page(pmap, pv->pv_va);
8651 } else if ((*pte & PG_W) == 0) {
8653 * Wired pages cannot be paged out so
8654 * doing accessed bit emulation for
8655 * them is wasted effort. We do the
8656 * hard work for unwired pages only.
8658 pmap_remove_pte(pmap, pte, pv->pv_va,
8659 *pde, &free, &lock);
8660 pmap_invalidate_page(pmap, pv->pv_va);
8665 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8666 ("inconsistent pv lock %p %p for page %p",
8667 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8672 /* Rotate the PV list if it has more than one entry. */
8673 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8674 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8675 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8678 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8679 not_cleared < PMAP_TS_REFERENCED_MAX);
8682 vm_page_free_pages_toq(&free, true);
8683 return (cleared + not_cleared);
8687 * Apply the given advice to the specified range of addresses within the
8688 * given pmap. Depending on the advice, clear the referenced and/or
8689 * modified flags in each mapping and set the mapped page's dirty field.
8692 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8694 struct rwlock *lock;
8695 pml4_entry_t *pml4e;
8697 pd_entry_t oldpde, *pde;
8698 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8699 vm_offset_t va, va_next;
8703 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8707 * A/D bit emulation requires an alternate code path when clearing
8708 * the modified and accessed bits below. Since this function is
8709 * advisory in nature we skip it entirely for pmaps that require
8710 * A/D bit emulation.
8712 if (pmap_emulate_ad_bits(pmap))
8715 PG_A = pmap_accessed_bit(pmap);
8716 PG_G = pmap_global_bit(pmap);
8717 PG_M = pmap_modified_bit(pmap);
8718 PG_V = pmap_valid_bit(pmap);
8719 PG_RW = pmap_rw_bit(pmap);
8721 pmap_delayed_invl_start();
8723 for (; sva < eva; sva = va_next) {
8724 pml4e = pmap_pml4e(pmap, sva);
8725 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8726 va_next = (sva + NBPML4) & ~PML4MASK;
8732 va_next = (sva + NBPDP) & ~PDPMASK;
8735 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8736 if ((*pdpe & PG_V) == 0)
8738 if ((*pdpe & PG_PS) != 0) {
8739 KASSERT(va_next <= eva,
8740 ("partial update of non-transparent 1G mapping "
8741 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8742 *pdpe, sva, eva, va_next));
8746 va_next = (sva + NBPDR) & ~PDRMASK;
8749 pde = pmap_pdpe_to_pde(pdpe, sva);
8751 if ((oldpde & PG_V) == 0)
8753 else if ((oldpde & PG_PS) != 0) {
8754 if ((oldpde & PG_MANAGED) == 0)
8757 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8762 * The large page mapping was destroyed.
8768 * Unless the page mappings are wired, remove the
8769 * mapping to a single page so that a subsequent
8770 * access may repromote. Choosing the last page
8771 * within the address range [sva, min(va_next, eva))
8772 * generally results in more repromotions. Since the
8773 * underlying page table page is fully populated, this
8774 * removal never frees a page table page.
8776 if ((oldpde & PG_W) == 0) {
8782 ("pmap_advise: no address gap"));
8783 pte = pmap_pde_to_pte(pde, va);
8784 KASSERT((*pte & PG_V) != 0,
8785 ("pmap_advise: invalid PTE"));
8786 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8796 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8798 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8800 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8801 if (advice == MADV_DONTNEED) {
8803 * Future calls to pmap_is_modified()
8804 * can be avoided by making the page
8807 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8810 atomic_clear_long(pte, PG_M | PG_A);
8811 } else if ((*pte & PG_A) != 0)
8812 atomic_clear_long(pte, PG_A);
8816 if ((*pte & PG_G) != 0) {
8823 if (va != va_next) {
8824 pmap_invalidate_range(pmap, va, sva);
8829 pmap_invalidate_range(pmap, va, sva);
8832 pmap_invalidate_all(pmap);
8834 pmap_delayed_invl_finish();
8838 * Clear the modify bits on the specified physical page.
8841 pmap_clear_modify(vm_page_t m)
8843 struct md_page *pvh;
8845 pv_entry_t next_pv, pv;
8846 pd_entry_t oldpde, *pde;
8847 pt_entry_t *pte, PG_M, PG_RW;
8848 struct rwlock *lock;
8850 int md_gen, pvh_gen;
8852 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8853 ("pmap_clear_modify: page %p is not managed", m));
8854 vm_page_assert_busied(m);
8856 if (!pmap_page_is_write_mapped(m))
8858 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8859 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8860 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8863 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8865 if (!PMAP_TRYLOCK(pmap)) {
8866 pvh_gen = pvh->pv_gen;
8870 if (pvh_gen != pvh->pv_gen) {
8875 PG_M = pmap_modified_bit(pmap);
8876 PG_RW = pmap_rw_bit(pmap);
8878 pde = pmap_pde(pmap, va);
8880 /* If oldpde has PG_RW set, then it also has PG_M set. */
8881 if ((oldpde & PG_RW) != 0 &&
8882 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8883 (oldpde & PG_W) == 0) {
8885 * Write protect the mapping to a single page so that
8886 * a subsequent write access may repromote.
8888 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8889 pte = pmap_pde_to_pte(pde, va);
8890 atomic_clear_long(pte, PG_M | PG_RW);
8892 pmap_invalidate_page(pmap, va);
8896 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8898 if (!PMAP_TRYLOCK(pmap)) {
8899 md_gen = m->md.pv_gen;
8900 pvh_gen = pvh->pv_gen;
8904 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8909 PG_M = pmap_modified_bit(pmap);
8910 PG_RW = pmap_rw_bit(pmap);
8911 pde = pmap_pde(pmap, pv->pv_va);
8912 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8913 " a 2mpage in page %p's pv list", m));
8914 pte = pmap_pde_to_pte(pde, pv->pv_va);
8915 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8916 atomic_clear_long(pte, PG_M);
8917 pmap_invalidate_page(pmap, pv->pv_va);
8925 * Miscellaneous support routines follow
8928 /* Adjust the properties for a leaf page table entry. */
8929 static __inline void
8930 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8934 opte = *(u_long *)pte;
8936 npte = opte & ~mask;
8938 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8943 * Map a set of physical memory pages into the kernel virtual
8944 * address space. Return a pointer to where it is mapped. This
8945 * routine is intended to be used for mapping device memory,
8949 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8951 struct pmap_preinit_mapping *ppim;
8952 vm_offset_t va, offset;
8956 offset = pa & PAGE_MASK;
8957 size = round_page(offset + size);
8958 pa = trunc_page(pa);
8960 if (!pmap_initialized) {
8962 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8963 ppim = pmap_preinit_mapping + i;
8964 if (ppim->va == 0) {
8968 ppim->va = virtual_avail;
8969 virtual_avail += size;
8975 panic("%s: too many preinit mappings", __func__);
8978 * If we have a preinit mapping, re-use it.
8980 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8981 ppim = pmap_preinit_mapping + i;
8982 if (ppim->pa == pa && ppim->sz == size &&
8983 (ppim->mode == mode ||
8984 (flags & MAPDEV_SETATTR) == 0))
8985 return ((void *)(ppim->va + offset));
8988 * If the specified range of physical addresses fits within
8989 * the direct map window, use the direct map.
8991 if (pa < dmaplimit && pa + size <= dmaplimit) {
8992 va = PHYS_TO_DMAP(pa);
8993 if ((flags & MAPDEV_SETATTR) != 0) {
8994 PMAP_LOCK(kernel_pmap);
8995 i = pmap_change_props_locked(va, size,
8996 PROT_NONE, mode, flags);
8997 PMAP_UNLOCK(kernel_pmap);
9001 return ((void *)(va + offset));
9003 va = kva_alloc(size);
9005 panic("%s: Couldn't allocate KVA", __func__);
9007 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
9008 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
9009 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
9010 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9011 pmap_invalidate_cache_range(va, va + tmpsize);
9012 return ((void *)(va + offset));
9016 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
9019 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
9024 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
9027 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
9031 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
9034 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
9039 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
9042 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
9043 MAPDEV_FLUSHCACHE));
9047 pmap_unmapdev(vm_offset_t va, vm_size_t size)
9049 struct pmap_preinit_mapping *ppim;
9053 /* If we gave a direct map region in pmap_mapdev, do nothing */
9054 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
9056 offset = va & PAGE_MASK;
9057 size = round_page(offset + size);
9058 va = trunc_page(va);
9059 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9060 ppim = pmap_preinit_mapping + i;
9061 if (ppim->va == va && ppim->sz == size) {
9062 if (pmap_initialized)
9068 if (va + size == virtual_avail)
9073 if (pmap_initialized) {
9074 pmap_qremove(va, atop(size));
9080 * Tries to demote a 1GB page mapping.
9083 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
9085 pdp_entry_t newpdpe, oldpdpe;
9086 pd_entry_t *firstpde, newpde, *pde;
9087 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
9091 PG_A = pmap_accessed_bit(pmap);
9092 PG_M = pmap_modified_bit(pmap);
9093 PG_V = pmap_valid_bit(pmap);
9094 PG_RW = pmap_rw_bit(pmap);
9096 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9098 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
9099 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
9100 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
9101 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
9102 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
9103 " in pmap %p", va, pmap);
9106 counter_u64_add(pt_page_count, 1);
9107 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
9108 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
9109 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
9110 KASSERT((oldpdpe & PG_A) != 0,
9111 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
9112 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
9113 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
9117 * Initialize the page directory page.
9119 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
9125 * Demote the mapping.
9130 * Invalidate a stale recursive mapping of the page directory page.
9132 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
9134 counter_u64_add(pmap_pdpe_demotions, 1);
9135 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
9136 " in pmap %p", va, pmap);
9141 * Sets the memory attribute for the specified page.
9144 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
9147 m->md.pat_mode = ma;
9150 * If "m" is a normal page, update its direct mapping. This update
9151 * can be relied upon to perform any cache operations that are
9152 * required for data coherence.
9154 if ((m->flags & PG_FICTITIOUS) == 0 &&
9155 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
9157 panic("memory attribute change on the direct map failed");
9161 * Changes the specified virtual address range's memory type to that given by
9162 * the parameter "mode". The specified virtual address range must be
9163 * completely contained within either the direct map or the kernel map. If
9164 * the virtual address range is contained within the kernel map, then the
9165 * memory type for each of the corresponding ranges of the direct map is also
9166 * changed. (The corresponding ranges of the direct map are those ranges that
9167 * map the same physical pages as the specified virtual address range.) These
9168 * changes to the direct map are necessary because Intel describes the
9169 * behavior of their processors as "undefined" if two or more mappings to the
9170 * same physical page have different memory types.
9172 * Returns zero if the change completed successfully, and either EINVAL or
9173 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9174 * of the virtual address range was not mapped, and ENOMEM is returned if
9175 * there was insufficient memory available to complete the change. In the
9176 * latter case, the memory type may have been changed on some part of the
9177 * virtual address range or the direct map.
9180 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9184 PMAP_LOCK(kernel_pmap);
9185 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9187 PMAP_UNLOCK(kernel_pmap);
9192 * Changes the specified virtual address range's protections to those
9193 * specified by "prot". Like pmap_change_attr(), protections for aliases
9194 * in the direct map are updated as well. Protections on aliasing mappings may
9195 * be a subset of the requested protections; for example, mappings in the direct
9196 * map are never executable.
9199 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9203 /* Only supported within the kernel map. */
9204 if (va < VM_MIN_KERNEL_ADDRESS)
9207 PMAP_LOCK(kernel_pmap);
9208 error = pmap_change_props_locked(va, size, prot, -1,
9209 MAPDEV_ASSERTVALID);
9210 PMAP_UNLOCK(kernel_pmap);
9215 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9216 int mode, int flags)
9218 vm_offset_t base, offset, tmpva;
9219 vm_paddr_t pa_start, pa_end, pa_end1;
9221 pd_entry_t *pde, pde_bits, pde_mask;
9222 pt_entry_t *pte, pte_bits, pte_mask;
9226 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9227 base = trunc_page(va);
9228 offset = va & PAGE_MASK;
9229 size = round_page(offset + size);
9232 * Only supported on kernel virtual addresses, including the direct
9233 * map but excluding the recursive map.
9235 if (base < DMAP_MIN_ADDRESS)
9239 * Construct our flag sets and masks. "bits" is the subset of
9240 * "mask" that will be set in each modified PTE.
9242 * Mappings in the direct map are never allowed to be executable.
9244 pde_bits = pte_bits = 0;
9245 pde_mask = pte_mask = 0;
9247 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9248 pde_mask |= X86_PG_PDE_CACHE;
9249 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9250 pte_mask |= X86_PG_PTE_CACHE;
9252 if (prot != VM_PROT_NONE) {
9253 if ((prot & VM_PROT_WRITE) != 0) {
9254 pde_bits |= X86_PG_RW;
9255 pte_bits |= X86_PG_RW;
9257 if ((prot & VM_PROT_EXECUTE) == 0 ||
9258 va < VM_MIN_KERNEL_ADDRESS) {
9262 pde_mask |= X86_PG_RW | pg_nx;
9263 pte_mask |= X86_PG_RW | pg_nx;
9267 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9268 * into 4KB pages if required.
9270 for (tmpva = base; tmpva < base + size; ) {
9271 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9272 if (pdpe == NULL || *pdpe == 0) {
9273 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9274 ("%s: addr %#lx is not mapped", __func__, tmpva));
9277 if (*pdpe & PG_PS) {
9279 * If the current 1GB page already has the required
9280 * properties, then we need not demote this page. Just
9281 * increment tmpva to the next 1GB page frame.
9283 if ((*pdpe & pde_mask) == pde_bits) {
9284 tmpva = trunc_1gpage(tmpva) + NBPDP;
9289 * If the current offset aligns with a 1GB page frame
9290 * and there is at least 1GB left within the range, then
9291 * we need not break down this page into 2MB pages.
9293 if ((tmpva & PDPMASK) == 0 &&
9294 tmpva + PDPMASK < base + size) {
9298 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9301 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9303 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9304 ("%s: addr %#lx is not mapped", __func__, tmpva));
9309 * If the current 2MB page already has the required
9310 * properties, then we need not demote this page. Just
9311 * increment tmpva to the next 2MB page frame.
9313 if ((*pde & pde_mask) == pde_bits) {
9314 tmpva = trunc_2mpage(tmpva) + NBPDR;
9319 * If the current offset aligns with a 2MB page frame
9320 * and there is at least 2MB left within the range, then
9321 * we need not break down this page into 4KB pages.
9323 if ((tmpva & PDRMASK) == 0 &&
9324 tmpva + PDRMASK < base + size) {
9328 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9331 pte = pmap_pde_to_pte(pde, tmpva);
9333 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9334 ("%s: addr %#lx is not mapped", __func__, tmpva));
9342 * Ok, all the pages exist, so run through them updating their
9343 * properties if required.
9346 pa_start = pa_end = 0;
9347 for (tmpva = base; tmpva < base + size; ) {
9348 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9349 if (*pdpe & PG_PS) {
9350 if ((*pdpe & pde_mask) != pde_bits) {
9351 pmap_pte_props(pdpe, pde_bits, pde_mask);
9354 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9355 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9356 if (pa_start == pa_end) {
9357 /* Start physical address run. */
9358 pa_start = *pdpe & PG_PS_FRAME;
9359 pa_end = pa_start + NBPDP;
9360 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9363 /* Run ended, update direct map. */
9364 error = pmap_change_props_locked(
9365 PHYS_TO_DMAP(pa_start),
9366 pa_end - pa_start, prot, mode,
9370 /* Start physical address run. */
9371 pa_start = *pdpe & PG_PS_FRAME;
9372 pa_end = pa_start + NBPDP;
9375 tmpva = trunc_1gpage(tmpva) + NBPDP;
9378 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9380 if ((*pde & pde_mask) != pde_bits) {
9381 pmap_pte_props(pde, pde_bits, pde_mask);
9384 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9385 (*pde & PG_PS_FRAME) < dmaplimit) {
9386 if (pa_start == pa_end) {
9387 /* Start physical address run. */
9388 pa_start = *pde & PG_PS_FRAME;
9389 pa_end = pa_start + NBPDR;
9390 } else if (pa_end == (*pde & PG_PS_FRAME))
9393 /* Run ended, update direct map. */
9394 error = pmap_change_props_locked(
9395 PHYS_TO_DMAP(pa_start),
9396 pa_end - pa_start, prot, mode,
9400 /* Start physical address run. */
9401 pa_start = *pde & PG_PS_FRAME;
9402 pa_end = pa_start + NBPDR;
9405 tmpva = trunc_2mpage(tmpva) + NBPDR;
9407 pte = pmap_pde_to_pte(pde, tmpva);
9408 if ((*pte & pte_mask) != pte_bits) {
9409 pmap_pte_props(pte, pte_bits, pte_mask);
9412 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9413 (*pte & PG_FRAME) < dmaplimit) {
9414 if (pa_start == pa_end) {
9415 /* Start physical address run. */
9416 pa_start = *pte & PG_FRAME;
9417 pa_end = pa_start + PAGE_SIZE;
9418 } else if (pa_end == (*pte & PG_FRAME))
9419 pa_end += PAGE_SIZE;
9421 /* Run ended, update direct map. */
9422 error = pmap_change_props_locked(
9423 PHYS_TO_DMAP(pa_start),
9424 pa_end - pa_start, prot, mode,
9428 /* Start physical address run. */
9429 pa_start = *pte & PG_FRAME;
9430 pa_end = pa_start + PAGE_SIZE;
9436 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9437 pa_end1 = MIN(pa_end, dmaplimit);
9438 if (pa_start != pa_end1)
9439 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9440 pa_end1 - pa_start, prot, mode, flags);
9444 * Flush CPU caches if required to make sure any data isn't cached that
9445 * shouldn't be, etc.
9448 pmap_invalidate_range(kernel_pmap, base, tmpva);
9449 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9450 pmap_invalidate_cache_range(base, tmpva);
9456 * Demotes any mapping within the direct map region that covers more than the
9457 * specified range of physical addresses. This range's size must be a power
9458 * of two and its starting address must be a multiple of its size. Since the
9459 * demotion does not change any attributes of the mapping, a TLB invalidation
9460 * is not mandatory. The caller may, however, request a TLB invalidation.
9463 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9472 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9473 KASSERT((base & (len - 1)) == 0,
9474 ("pmap_demote_DMAP: base is not a multiple of len"));
9475 if (len < NBPDP && base < dmaplimit) {
9476 va = PHYS_TO_DMAP(base);
9478 PMAP_LOCK(kernel_pmap);
9479 pdpe = pmap_pdpe(kernel_pmap, va);
9480 if ((*pdpe & X86_PG_V) == 0)
9481 panic("pmap_demote_DMAP: invalid PDPE");
9482 if ((*pdpe & PG_PS) != 0) {
9483 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9484 panic("pmap_demote_DMAP: PDPE failed");
9488 pde = pmap_pdpe_to_pde(pdpe, va);
9489 if ((*pde & X86_PG_V) == 0)
9490 panic("pmap_demote_DMAP: invalid PDE");
9491 if ((*pde & PG_PS) != 0) {
9492 if (!pmap_demote_pde(kernel_pmap, pde, va))
9493 panic("pmap_demote_DMAP: PDE failed");
9497 if (changed && invalidate)
9498 pmap_invalidate_page(kernel_pmap, va);
9499 PMAP_UNLOCK(kernel_pmap);
9504 * Perform the pmap work for mincore(2). If the page is not both referenced and
9505 * modified by this pmap, returns its physical address so that the caller can
9506 * find other mappings.
9509 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9513 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9517 PG_A = pmap_accessed_bit(pmap);
9518 PG_M = pmap_modified_bit(pmap);
9519 PG_V = pmap_valid_bit(pmap);
9520 PG_RW = pmap_rw_bit(pmap);
9526 pdpe = pmap_pdpe(pmap, addr);
9529 if ((*pdpe & PG_V) != 0) {
9530 if ((*pdpe & PG_PS) != 0) {
9532 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9534 val = MINCORE_PSIND(2);
9536 pdep = pmap_pde(pmap, addr);
9537 if (pdep != NULL && (*pdep & PG_V) != 0) {
9538 if ((*pdep & PG_PS) != 0) {
9540 /* Compute the physical address of the 4KB page. */
9541 pa = ((pte & PG_PS_FRAME) | (addr &
9542 PDRMASK)) & PG_FRAME;
9543 val = MINCORE_PSIND(1);
9545 pte = *pmap_pde_to_pte(pdep, addr);
9546 pa = pte & PG_FRAME;
9552 if ((pte & PG_V) != 0) {
9553 val |= MINCORE_INCORE;
9554 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9555 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9556 if ((pte & PG_A) != 0)
9557 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9559 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9560 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9561 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9570 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9572 uint32_t gen, new_gen, pcid_next;
9574 CRITICAL_ASSERT(curthread);
9575 gen = PCPU_GET(pcid_gen);
9576 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9577 return (pti ? 0 : CR3_PCID_SAVE);
9578 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9579 return (CR3_PCID_SAVE);
9580 pcid_next = PCPU_GET(pcid_next);
9581 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9582 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9583 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9584 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9585 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9589 PCPU_SET(pcid_gen, new_gen);
9590 pcid_next = PMAP_PCID_KERN + 1;
9594 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9595 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9596 PCPU_SET(pcid_next, pcid_next + 1);
9601 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9605 cached = pmap_pcid_alloc(pmap, cpuid);
9606 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9607 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9608 pmap->pm_pcids[cpuid].pm_pcid));
9609 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9610 pmap == kernel_pmap,
9611 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9612 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9617 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9620 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9621 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9625 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9628 uint64_t cached, cr3, kcr3, ucr3;
9630 KASSERT((read_rflags() & PSL_I) == 0,
9631 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9633 /* See the comment in pmap_invalidate_page_pcid(). */
9634 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9635 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9636 old_pmap = PCPU_GET(curpmap);
9637 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9638 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9641 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9643 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9644 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9645 PCPU_SET(curpmap, pmap);
9646 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9647 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9650 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9651 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9653 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9654 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9656 counter_u64_add(pcid_save_cnt, 1);
9658 pmap_activate_sw_pti_post(td, pmap);
9662 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9665 uint64_t cached, cr3;
9667 KASSERT((read_rflags() & PSL_I) == 0,
9668 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9670 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9672 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9673 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9675 PCPU_SET(curpmap, pmap);
9677 counter_u64_add(pcid_save_cnt, 1);
9681 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9682 u_int cpuid __unused)
9685 load_cr3(pmap->pm_cr3);
9686 PCPU_SET(curpmap, pmap);
9690 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9691 u_int cpuid __unused)
9694 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9695 PCPU_SET(kcr3, pmap->pm_cr3);
9696 PCPU_SET(ucr3, pmap->pm_ucr3);
9697 pmap_activate_sw_pti_post(td, pmap);
9700 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9704 if (pmap_pcid_enabled && pti)
9705 return (pmap_activate_sw_pcid_pti);
9706 else if (pmap_pcid_enabled && !pti)
9707 return (pmap_activate_sw_pcid_nopti);
9708 else if (!pmap_pcid_enabled && pti)
9709 return (pmap_activate_sw_nopcid_pti);
9710 else /* if (!pmap_pcid_enabled && !pti) */
9711 return (pmap_activate_sw_nopcid_nopti);
9715 pmap_activate_sw(struct thread *td)
9717 pmap_t oldpmap, pmap;
9720 oldpmap = PCPU_GET(curpmap);
9721 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9722 if (oldpmap == pmap) {
9723 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9727 cpuid = PCPU_GET(cpuid);
9729 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9731 CPU_SET(cpuid, &pmap->pm_active);
9733 pmap_activate_sw_mode(td, pmap, cpuid);
9735 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9737 CPU_CLR(cpuid, &oldpmap->pm_active);
9742 pmap_activate(struct thread *td)
9745 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9746 * invalidate_all IPI, which checks for curpmap ==
9747 * smp_tlb_pmap. The below sequence of operations has a
9748 * window where %CR3 is loaded with the new pmap's PML4
9749 * address, but the curpmap value has not yet been updated.
9750 * This causes the invltlb IPI handler, which is called
9751 * between the updates, to execute as a NOP, which leaves
9752 * stale TLB entries.
9754 * Note that the most common use of pmap_activate_sw(), from
9755 * a context switch, is immune to this race, because
9756 * interrupts are disabled (while the thread lock is owned),
9757 * so the IPI is delayed until after curpmap is updated. Protect
9758 * other callers in a similar way, by disabling interrupts
9759 * around the %cr3 register reload and curpmap assignment.
9762 pmap_activate_sw(td);
9767 pmap_activate_boot(pmap_t pmap)
9773 * kernel_pmap must be never deactivated, and we ensure that
9774 * by never activating it at all.
9776 MPASS(pmap != kernel_pmap);
9778 cpuid = PCPU_GET(cpuid);
9780 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9782 CPU_SET(cpuid, &pmap->pm_active);
9784 PCPU_SET(curpmap, pmap);
9786 kcr3 = pmap->pm_cr3;
9787 if (pmap_pcid_enabled)
9788 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9792 PCPU_SET(kcr3, kcr3);
9793 PCPU_SET(ucr3, PMAP_NO_CR3);
9797 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9802 * Increase the starting virtual address of the given mapping if a
9803 * different alignment might result in more superpage mappings.
9806 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9807 vm_offset_t *addr, vm_size_t size)
9809 vm_offset_t superpage_offset;
9813 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9814 offset += ptoa(object->pg_color);
9815 superpage_offset = offset & PDRMASK;
9816 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9817 (*addr & PDRMASK) == superpage_offset)
9819 if ((*addr & PDRMASK) < superpage_offset)
9820 *addr = (*addr & ~PDRMASK) + superpage_offset;
9822 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9826 static unsigned long num_dirty_emulations;
9827 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9828 &num_dirty_emulations, 0, NULL);
9830 static unsigned long num_accessed_emulations;
9831 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9832 &num_accessed_emulations, 0, NULL);
9834 static unsigned long num_superpage_accessed_emulations;
9835 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9836 &num_superpage_accessed_emulations, 0, NULL);
9838 static unsigned long ad_emulation_superpage_promotions;
9839 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9840 &ad_emulation_superpage_promotions, 0, NULL);
9841 #endif /* INVARIANTS */
9844 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9847 struct rwlock *lock;
9848 #if VM_NRESERVLEVEL > 0
9852 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9854 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9855 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9857 if (!pmap_emulate_ad_bits(pmap))
9860 PG_A = pmap_accessed_bit(pmap);
9861 PG_M = pmap_modified_bit(pmap);
9862 PG_V = pmap_valid_bit(pmap);
9863 PG_RW = pmap_rw_bit(pmap);
9869 pde = pmap_pde(pmap, va);
9870 if (pde == NULL || (*pde & PG_V) == 0)
9873 if ((*pde & PG_PS) != 0) {
9874 if (ftype == VM_PROT_READ) {
9876 atomic_add_long(&num_superpage_accessed_emulations, 1);
9884 pte = pmap_pde_to_pte(pde, va);
9885 if ((*pte & PG_V) == 0)
9888 if (ftype == VM_PROT_WRITE) {
9889 if ((*pte & PG_RW) == 0)
9892 * Set the modified and accessed bits simultaneously.
9894 * Intel EPT PTEs that do software emulation of A/D bits map
9895 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9896 * An EPT misconfiguration is triggered if the PTE is writable
9897 * but not readable (WR=10). This is avoided by setting PG_A
9898 * and PG_M simultaneously.
9900 *pte |= PG_M | PG_A;
9905 #if VM_NRESERVLEVEL > 0
9906 /* try to promote the mapping */
9907 if (va < VM_MAXUSER_ADDRESS)
9908 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9912 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9914 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9915 pmap_ps_enabled(pmap) &&
9916 (m->flags & PG_FICTITIOUS) == 0 &&
9917 vm_reserv_level_iffullpop(m) == 0) {
9918 pmap_promote_pde(pmap, pde, va, &lock);
9920 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9926 if (ftype == VM_PROT_WRITE)
9927 atomic_add_long(&num_dirty_emulations, 1);
9929 atomic_add_long(&num_accessed_emulations, 1);
9931 rv = 0; /* success */
9940 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9945 pt_entry_t *pte, PG_V;
9949 PG_V = pmap_valid_bit(pmap);
9952 pml4 = pmap_pml4e(pmap, va);
9956 if ((*pml4 & PG_V) == 0)
9959 pdp = pmap_pml4e_to_pdpe(pml4, va);
9961 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9964 pde = pmap_pdpe_to_pde(pdp, va);
9966 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9969 pte = pmap_pde_to_pte(pde, va);
9978 * Get the kernel virtual address of a set of physical pages. If there are
9979 * physical addresses not covered by the DMAP perform a transient mapping
9980 * that will be removed when calling pmap_unmap_io_transient.
9982 * \param page The pages the caller wishes to obtain the virtual
9983 * address on the kernel memory map.
9984 * \param vaddr On return contains the kernel virtual memory address
9985 * of the pages passed in the page parameter.
9986 * \param count Number of pages passed in.
9987 * \param can_fault TRUE if the thread using the mapped pages can take
9988 * page faults, FALSE otherwise.
9990 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9991 * finished or FALSE otherwise.
9995 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9996 boolean_t can_fault)
9999 boolean_t needs_mapping;
10001 int cache_bits, error __unused, i;
10004 * Allocate any KVA space that we need, this is done in a separate
10005 * loop to prevent calling vmem_alloc while pinned.
10007 needs_mapping = FALSE;
10008 for (i = 0; i < count; i++) {
10009 paddr = VM_PAGE_TO_PHYS(page[i]);
10010 if (__predict_false(paddr >= dmaplimit)) {
10011 error = vmem_alloc(kernel_arena, PAGE_SIZE,
10012 M_BESTFIT | M_WAITOK, &vaddr[i]);
10013 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
10014 needs_mapping = TRUE;
10016 vaddr[i] = PHYS_TO_DMAP(paddr);
10020 /* Exit early if everything is covered by the DMAP */
10021 if (!needs_mapping)
10025 * NB: The sequence of updating a page table followed by accesses
10026 * to the corresponding pages used in the !DMAP case is subject to
10027 * the situation described in the "AMD64 Architecture Programmer's
10028 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
10029 * Coherency Considerations". Therefore, issuing the INVLPG right
10030 * after modifying the PTE bits is crucial.
10034 for (i = 0; i < count; i++) {
10035 paddr = VM_PAGE_TO_PHYS(page[i]);
10036 if (paddr >= dmaplimit) {
10039 * Slow path, since we can get page faults
10040 * while mappings are active don't pin the
10041 * thread to the CPU and instead add a global
10042 * mapping visible to all CPUs.
10044 pmap_qenter(vaddr[i], &page[i], 1);
10046 pte = vtopte(vaddr[i]);
10047 cache_bits = pmap_cache_bits(kernel_pmap,
10048 page[i]->md.pat_mode, 0);
10049 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
10056 return (needs_mapping);
10060 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10061 boolean_t can_fault)
10068 for (i = 0; i < count; i++) {
10069 paddr = VM_PAGE_TO_PHYS(page[i]);
10070 if (paddr >= dmaplimit) {
10072 pmap_qremove(vaddr[i], 1);
10073 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
10079 pmap_quick_enter_page(vm_page_t m)
10083 paddr = VM_PAGE_TO_PHYS(m);
10084 if (paddr < dmaplimit)
10085 return (PHYS_TO_DMAP(paddr));
10086 mtx_lock_spin(&qframe_mtx);
10087 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
10088 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
10089 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
10094 pmap_quick_remove_page(vm_offset_t addr)
10097 if (addr != qframe)
10099 pte_store(vtopte(qframe), 0);
10101 mtx_unlock_spin(&qframe_mtx);
10105 * Pdp pages from the large map are managed differently from either
10106 * kernel or user page table pages. They are permanently allocated at
10107 * initialization time, and their reference count is permanently set to
10108 * zero. The pml4 entries pointing to those pages are copied into
10109 * each allocated pmap.
10111 * In contrast, pd and pt pages are managed like user page table
10112 * pages. They are dynamically allocated, and their reference count
10113 * represents the number of valid entries within the page.
10116 pmap_large_map_getptp_unlocked(void)
10120 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
10123 if ((m->flags & PG_ZERO) == 0)
10125 counter_u64_add(pt_page_count, 1);
10131 pmap_large_map_getptp(void)
10135 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
10136 m = pmap_large_map_getptp_unlocked();
10138 PMAP_UNLOCK(kernel_pmap);
10140 PMAP_LOCK(kernel_pmap);
10141 /* Callers retry. */
10146 static pdp_entry_t *
10147 pmap_large_map_pdpe(vm_offset_t va)
10149 vm_pindex_t pml4_idx;
10152 pml4_idx = pmap_pml4e_index(va);
10153 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
10154 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
10156 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10157 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
10158 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
10159 "LMSPML4I %#jx lm_ents %d",
10160 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10161 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
10162 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
10165 static pd_entry_t *
10166 pmap_large_map_pde(vm_offset_t va)
10173 pdpe = pmap_large_map_pdpe(va);
10175 m = pmap_large_map_getptp();
10178 mphys = VM_PAGE_TO_PHYS(m);
10179 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10181 MPASS((*pdpe & X86_PG_PS) == 0);
10182 mphys = *pdpe & PG_FRAME;
10184 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10187 static pt_entry_t *
10188 pmap_large_map_pte(vm_offset_t va)
10195 pde = pmap_large_map_pde(va);
10197 m = pmap_large_map_getptp();
10200 mphys = VM_PAGE_TO_PHYS(m);
10201 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10202 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10204 MPASS((*pde & X86_PG_PS) == 0);
10205 mphys = *pde & PG_FRAME;
10207 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10211 pmap_large_map_kextract(vm_offset_t va)
10213 pdp_entry_t *pdpe, pdp;
10214 pd_entry_t *pde, pd;
10215 pt_entry_t *pte, pt;
10217 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10218 ("not largemap range %#lx", (u_long)va));
10219 pdpe = pmap_large_map_pdpe(va);
10221 KASSERT((pdp & X86_PG_V) != 0,
10222 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10223 (u_long)pdpe, pdp));
10224 if ((pdp & X86_PG_PS) != 0) {
10225 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10226 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10227 (u_long)pdpe, pdp));
10228 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10230 pde = pmap_pdpe_to_pde(pdpe, va);
10232 KASSERT((pd & X86_PG_V) != 0,
10233 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10234 if ((pd & X86_PG_PS) != 0)
10235 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10236 pte = pmap_pde_to_pte(pde, va);
10238 KASSERT((pt & X86_PG_V) != 0,
10239 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10240 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10244 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10245 vmem_addr_t *vmem_res)
10249 * Large mappings are all but static. Consequently, there
10250 * is no point in waiting for an earlier allocation to be
10253 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10254 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10258 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10259 vm_memattr_t mattr)
10264 vm_offset_t va, inc;
10265 vmem_addr_t vmem_res;
10269 if (len == 0 || spa + len < spa)
10272 /* See if DMAP can serve. */
10273 if (spa + len <= dmaplimit) {
10274 va = PHYS_TO_DMAP(spa);
10275 *addr = (void *)va;
10276 return (pmap_change_attr(va, len, mattr));
10280 * No, allocate KVA. Fit the address with best possible
10281 * alignment for superpages. Fall back to worse align if
10285 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10286 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10287 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10289 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10291 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10294 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10299 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10300 * in the pagetable to minimize flushing. No need to
10301 * invalidate TLB, since we only update invalid entries.
10303 PMAP_LOCK(kernel_pmap);
10304 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10306 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10307 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10308 pdpe = pmap_large_map_pdpe(va);
10310 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10311 X86_PG_V | X86_PG_A | pg_nx |
10312 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10314 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10315 (va & PDRMASK) == 0) {
10316 pde = pmap_large_map_pde(va);
10318 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10319 X86_PG_V | X86_PG_A | pg_nx |
10320 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10321 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10325 pte = pmap_large_map_pte(va);
10327 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10328 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10330 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10335 PMAP_UNLOCK(kernel_pmap);
10338 *addr = (void *)vmem_res;
10343 pmap_large_unmap(void *svaa, vm_size_t len)
10345 vm_offset_t sva, va;
10347 pdp_entry_t *pdpe, pdp;
10348 pd_entry_t *pde, pd;
10351 struct spglist spgf;
10353 sva = (vm_offset_t)svaa;
10354 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10355 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10359 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10360 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10361 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10362 PMAP_LOCK(kernel_pmap);
10363 for (va = sva; va < sva + len; va += inc) {
10364 pdpe = pmap_large_map_pdpe(va);
10366 KASSERT((pdp & X86_PG_V) != 0,
10367 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10368 (u_long)pdpe, pdp));
10369 if ((pdp & X86_PG_PS) != 0) {
10370 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10371 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10372 (u_long)pdpe, pdp));
10373 KASSERT((va & PDPMASK) == 0,
10374 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10375 (u_long)pdpe, pdp));
10376 KASSERT(va + NBPDP <= sva + len,
10377 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10378 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10379 (u_long)pdpe, pdp, len));
10384 pde = pmap_pdpe_to_pde(pdpe, va);
10386 KASSERT((pd & X86_PG_V) != 0,
10387 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10389 if ((pd & X86_PG_PS) != 0) {
10390 KASSERT((va & PDRMASK) == 0,
10391 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10393 KASSERT(va + NBPDR <= sva + len,
10394 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10395 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10399 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10401 if (m->ref_count == 0) {
10403 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10407 pte = pmap_pde_to_pte(pde, va);
10408 KASSERT((*pte & X86_PG_V) != 0,
10409 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10410 (u_long)pte, *pte));
10413 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10415 if (m->ref_count == 0) {
10417 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10418 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10420 if (m->ref_count == 0) {
10422 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10426 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10427 PMAP_UNLOCK(kernel_pmap);
10428 vm_page_free_pages_toq(&spgf, false);
10429 vmem_free(large_vmem, sva, len);
10433 pmap_large_map_wb_fence_mfence(void)
10440 pmap_large_map_wb_fence_atomic(void)
10443 atomic_thread_fence_seq_cst();
10447 pmap_large_map_wb_fence_nop(void)
10451 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10454 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10455 return (pmap_large_map_wb_fence_mfence);
10456 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10457 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10458 return (pmap_large_map_wb_fence_atomic);
10460 /* clflush is strongly enough ordered */
10461 return (pmap_large_map_wb_fence_nop);
10465 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10468 for (; len > 0; len -= cpu_clflush_line_size,
10469 va += cpu_clflush_line_size)
10474 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10477 for (; len > 0; len -= cpu_clflush_line_size,
10478 va += cpu_clflush_line_size)
10483 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10486 for (; len > 0; len -= cpu_clflush_line_size,
10487 va += cpu_clflush_line_size)
10492 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10496 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10499 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10500 return (pmap_large_map_flush_range_clwb);
10501 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10502 return (pmap_large_map_flush_range_clflushopt);
10503 else if ((cpu_feature & CPUID_CLFSH) != 0)
10504 return (pmap_large_map_flush_range_clflush);
10506 return (pmap_large_map_flush_range_nop);
10510 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10512 volatile u_long *pe;
10518 for (va = sva; va < eva; va += inc) {
10520 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10521 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10523 if ((p & X86_PG_PS) != 0)
10527 pe = (volatile u_long *)pmap_large_map_pde(va);
10529 if ((p & X86_PG_PS) != 0)
10533 pe = (volatile u_long *)pmap_large_map_pte(va);
10537 seen_other = false;
10539 if ((p & X86_PG_AVAIL1) != 0) {
10541 * Spin-wait for the end of a parallel
10548 * If we saw other write-back
10549 * occuring, we cannot rely on PG_M to
10550 * indicate state of the cache. The
10551 * PG_M bit is cleared before the
10552 * flush to avoid ignoring new writes,
10553 * and writes which are relevant for
10554 * us might happen after.
10560 if ((p & X86_PG_M) != 0 || seen_other) {
10561 if (!atomic_fcmpset_long(pe, &p,
10562 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10564 * If we saw PG_M without
10565 * PG_AVAIL1, and then on the
10566 * next attempt we do not
10567 * observe either PG_M or
10568 * PG_AVAIL1, the other
10569 * write-back started after us
10570 * and finished before us. We
10571 * can rely on it doing our
10575 pmap_large_map_flush_range(va, inc);
10576 atomic_clear_long(pe, X86_PG_AVAIL1);
10585 * Write-back cache lines for the given address range.
10587 * Must be called only on the range or sub-range returned from
10588 * pmap_large_map(). Must not be called on the coalesced ranges.
10590 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10591 * instructions support.
10594 pmap_large_map_wb(void *svap, vm_size_t len)
10596 vm_offset_t eva, sva;
10598 sva = (vm_offset_t)svap;
10600 pmap_large_map_wb_fence();
10601 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10602 pmap_large_map_flush_range(sva, len);
10604 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10605 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10606 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10607 pmap_large_map_wb_large(sva, eva);
10609 pmap_large_map_wb_fence();
10613 pmap_pti_alloc_page(void)
10617 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10618 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10619 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10624 pmap_pti_free_page(vm_page_t m)
10627 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10628 if (!vm_page_unwire_noq(m))
10630 vm_page_free_zero(m);
10635 pmap_pti_init(void)
10644 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10645 VM_OBJECT_WLOCK(pti_obj);
10646 pml4_pg = pmap_pti_alloc_page();
10647 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10648 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10649 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10650 pdpe = pmap_pti_pdpe(va);
10651 pmap_pti_wire_pte(pdpe);
10653 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10654 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10655 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10656 sizeof(struct gate_descriptor) * NIDT, false);
10658 /* Doublefault stack IST 1 */
10659 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10660 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10661 /* NMI stack IST 2 */
10662 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10663 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10664 /* MC# stack IST 3 */
10665 va = __pcpu[i].pc_common_tss.tss_ist3 +
10666 sizeof(struct nmi_pcpu);
10667 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10668 /* DB# stack IST 4 */
10669 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10670 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10672 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10673 (vm_offset_t)etext, true);
10674 pti_finalized = true;
10675 VM_OBJECT_WUNLOCK(pti_obj);
10677 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10679 static pdp_entry_t *
10680 pmap_pti_pdpe(vm_offset_t va)
10682 pml4_entry_t *pml4e;
10685 vm_pindex_t pml4_idx;
10688 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10690 pml4_idx = pmap_pml4e_index(va);
10691 pml4e = &pti_pml4[pml4_idx];
10695 panic("pml4 alloc after finalization\n");
10696 m = pmap_pti_alloc_page();
10698 pmap_pti_free_page(m);
10699 mphys = *pml4e & ~PAGE_MASK;
10701 mphys = VM_PAGE_TO_PHYS(m);
10702 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10705 mphys = *pml4e & ~PAGE_MASK;
10707 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10712 pmap_pti_wire_pte(void *pte)
10716 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10717 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10722 pmap_pti_unwire_pde(void *pde, bool only_ref)
10726 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10727 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10728 MPASS(m->ref_count > 0);
10729 MPASS(only_ref || m->ref_count > 1);
10730 pmap_pti_free_page(m);
10734 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10739 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10740 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10741 MPASS(m->ref_count > 0);
10742 if (pmap_pti_free_page(m)) {
10743 pde = pmap_pti_pde(va);
10744 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10746 pmap_pti_unwire_pde(pde, false);
10750 static pd_entry_t *
10751 pmap_pti_pde(vm_offset_t va)
10756 vm_pindex_t pd_idx;
10759 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10761 pdpe = pmap_pti_pdpe(va);
10763 m = pmap_pti_alloc_page();
10765 pmap_pti_free_page(m);
10766 MPASS((*pdpe & X86_PG_PS) == 0);
10767 mphys = *pdpe & ~PAGE_MASK;
10769 mphys = VM_PAGE_TO_PHYS(m);
10770 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10773 MPASS((*pdpe & X86_PG_PS) == 0);
10774 mphys = *pdpe & ~PAGE_MASK;
10777 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10778 pd_idx = pmap_pde_index(va);
10783 static pt_entry_t *
10784 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10791 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10793 pde = pmap_pti_pde(va);
10794 if (unwire_pde != NULL) {
10795 *unwire_pde = true;
10796 pmap_pti_wire_pte(pde);
10799 m = pmap_pti_alloc_page();
10801 pmap_pti_free_page(m);
10802 MPASS((*pde & X86_PG_PS) == 0);
10803 mphys = *pde & ~(PAGE_MASK | pg_nx);
10805 mphys = VM_PAGE_TO_PHYS(m);
10806 *pde = mphys | X86_PG_RW | X86_PG_V;
10807 if (unwire_pde != NULL)
10808 *unwire_pde = false;
10811 MPASS((*pde & X86_PG_PS) == 0);
10812 mphys = *pde & ~(PAGE_MASK | pg_nx);
10815 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10816 pte += pmap_pte_index(va);
10822 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10826 pt_entry_t *pte, ptev;
10829 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10831 sva = trunc_page(sva);
10832 MPASS(sva > VM_MAXUSER_ADDRESS);
10833 eva = round_page(eva);
10835 for (; sva < eva; sva += PAGE_SIZE) {
10836 pte = pmap_pti_pte(sva, &unwire_pde);
10837 pa = pmap_kextract(sva);
10838 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10839 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10840 VM_MEMATTR_DEFAULT, FALSE);
10842 pte_store(pte, ptev);
10843 pmap_pti_wire_pte(pte);
10845 KASSERT(!pti_finalized,
10846 ("pti overlap after fin %#lx %#lx %#lx",
10848 KASSERT(*pte == ptev,
10849 ("pti non-identical pte after fin %#lx %#lx %#lx",
10853 pde = pmap_pti_pde(sva);
10854 pmap_pti_unwire_pde(pde, true);
10860 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10865 VM_OBJECT_WLOCK(pti_obj);
10866 pmap_pti_add_kva_locked(sva, eva, exec);
10867 VM_OBJECT_WUNLOCK(pti_obj);
10871 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10878 sva = rounddown2(sva, PAGE_SIZE);
10879 MPASS(sva > VM_MAXUSER_ADDRESS);
10880 eva = roundup2(eva, PAGE_SIZE);
10882 VM_OBJECT_WLOCK(pti_obj);
10883 for (va = sva; va < eva; va += PAGE_SIZE) {
10884 pte = pmap_pti_pte(va, NULL);
10885 KASSERT((*pte & X86_PG_V) != 0,
10886 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10887 (u_long)pte, *pte));
10889 pmap_pti_unwire_pte(pte, va);
10891 pmap_invalidate_range(kernel_pmap, sva, eva);
10892 VM_OBJECT_WUNLOCK(pti_obj);
10896 pkru_dup_range(void *ctx __unused, void *data)
10898 struct pmap_pkru_range *node, *new_node;
10900 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10901 if (new_node == NULL)
10904 memcpy(new_node, node, sizeof(*node));
10909 pkru_free_range(void *ctx __unused, void *node)
10912 uma_zfree(pmap_pkru_ranges_zone, node);
10916 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10919 struct pmap_pkru_range *ppr;
10922 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10923 MPASS(pmap->pm_type == PT_X86);
10924 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10925 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10926 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10928 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10931 ppr->pkru_keyidx = keyidx;
10932 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10933 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10935 uma_zfree(pmap_pkru_ranges_zone, ppr);
10940 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10944 MPASS(pmap->pm_type == PT_X86);
10945 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10946 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10950 pmap_pkru_deassign_all(pmap_t pmap)
10953 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10954 if (pmap->pm_type == PT_X86 &&
10955 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10956 rangeset_remove_all(&pmap->pm_pkru);
10960 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10962 struct pmap_pkru_range *ppr, *prev_ppr;
10965 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10966 if (pmap->pm_type != PT_X86 ||
10967 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10968 sva >= VM_MAXUSER_ADDRESS)
10970 MPASS(eva <= VM_MAXUSER_ADDRESS);
10971 for (va = sva; va < eva; prev_ppr = ppr) {
10972 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10975 else if ((ppr == NULL) ^ (prev_ppr == NULL))
10981 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10983 va = ppr->pkru_rs_el.re_end;
10989 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10991 struct pmap_pkru_range *ppr;
10993 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10994 if (pmap->pm_type != PT_X86 ||
10995 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10996 va >= VM_MAXUSER_ADDRESS)
10998 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11000 return (X86_PG_PKU(ppr->pkru_keyidx));
11005 pred_pkru_on_remove(void *ctx __unused, void *r)
11007 struct pmap_pkru_range *ppr;
11010 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
11014 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11017 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11018 if (pmap->pm_type == PT_X86 &&
11019 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
11020 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
11021 pred_pkru_on_remove);
11026 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
11029 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
11030 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
11031 MPASS(dst_pmap->pm_type == PT_X86);
11032 MPASS(src_pmap->pm_type == PT_X86);
11033 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11034 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
11036 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
11040 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11043 pml4_entry_t *pml4e;
11045 pd_entry_t newpde, ptpaddr, *pde;
11046 pt_entry_t newpte, *ptep, pte;
11047 vm_offset_t va, va_next;
11050 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11051 MPASS(pmap->pm_type == PT_X86);
11052 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
11054 for (changed = false, va = sva; va < eva; va = va_next) {
11055 pml4e = pmap_pml4e(pmap, va);
11056 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
11057 va_next = (va + NBPML4) & ~PML4MASK;
11063 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
11064 if ((*pdpe & X86_PG_V) == 0) {
11065 va_next = (va + NBPDP) & ~PDPMASK;
11071 va_next = (va + NBPDR) & ~PDRMASK;
11075 pde = pmap_pdpe_to_pde(pdpe, va);
11080 MPASS((ptpaddr & X86_PG_V) != 0);
11081 if ((ptpaddr & PG_PS) != 0) {
11082 if (va + NBPDR == va_next && eva >= va_next) {
11083 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
11084 X86_PG_PKU(keyidx);
11085 if (newpde != ptpaddr) {
11090 } else if (!pmap_demote_pde(pmap, pde, va)) {
11098 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
11099 ptep++, va += PAGE_SIZE) {
11101 if ((pte & X86_PG_V) == 0)
11103 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
11104 if (newpte != pte) {
11111 pmap_invalidate_range(pmap, sva, eva);
11115 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11116 u_int keyidx, int flags)
11119 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
11120 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
11122 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
11124 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
11130 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11135 sva = trunc_page(sva);
11136 eva = round_page(eva);
11137 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
11142 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
11144 pmap_pkru_update_range(pmap, sva, eva, keyidx);
11146 if (error != ENOMEM)
11154 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11158 sva = trunc_page(sva);
11159 eva = round_page(eva);
11160 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
11165 error = pmap_pkru_deassign(pmap, sva, eva);
11167 pmap_pkru_update_range(pmap, sva, eva, 0);
11169 if (error != ENOMEM)
11177 * Track a range of the kernel's virtual address space that is contiguous
11178 * in various mapping attributes.
11180 struct pmap_kernel_map_range {
11189 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11195 if (eva <= range->sva)
11198 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11199 for (i = 0; i < PAT_INDEX_SIZE; i++)
11200 if (pat_index[i] == pat_idx)
11204 case PAT_WRITE_BACK:
11207 case PAT_WRITE_THROUGH:
11210 case PAT_UNCACHEABLE:
11216 case PAT_WRITE_PROTECTED:
11219 case PAT_WRITE_COMBINING:
11223 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11224 __func__, pat_idx, range->sva, eva);
11229 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11231 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11232 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11233 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11234 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11235 mode, range->pdpes, range->pdes, range->ptes);
11237 /* Reset to sentinel value. */
11238 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11239 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11240 NPDEPG - 1, NPTEPG - 1);
11244 * Determine whether the attributes specified by a page table entry match those
11245 * being tracked by the current range. This is not quite as simple as a direct
11246 * flag comparison since some PAT modes have multiple representations.
11249 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11251 pt_entry_t diff, mask;
11253 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11254 diff = (range->attrs ^ attrs) & mask;
11257 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11258 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11259 pmap_pat_index(kernel_pmap, attrs, true))
11265 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11269 memset(range, 0, sizeof(*range));
11271 range->attrs = attrs;
11275 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11276 * those of the current run, dump the address range and its attributes, and
11280 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11281 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11286 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11288 attrs |= pdpe & pg_nx;
11289 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11290 if ((pdpe & PG_PS) != 0) {
11291 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11292 } else if (pde != 0) {
11293 attrs |= pde & pg_nx;
11294 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11296 if ((pde & PG_PS) != 0) {
11297 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11298 } else if (pte != 0) {
11299 attrs |= pte & pg_nx;
11300 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11301 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11303 /* Canonicalize by always using the PDE PAT bit. */
11304 if ((attrs & X86_PG_PTE_PAT) != 0)
11305 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11308 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11309 sysctl_kmaps_dump(sb, range, va);
11310 sysctl_kmaps_reinit(range, va, attrs);
11315 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11317 struct pmap_kernel_map_range range;
11318 struct sbuf sbuf, *sb;
11319 pml4_entry_t pml4e;
11320 pdp_entry_t *pdp, pdpe;
11321 pd_entry_t *pd, pde;
11322 pt_entry_t *pt, pte;
11325 int error, i, j, k, l;
11327 error = sysctl_wire_old_buffer(req, 0);
11331 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11333 /* Sentinel value. */
11334 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11335 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11336 NPDEPG - 1, NPTEPG - 1);
11339 * Iterate over the kernel page tables without holding the kernel pmap
11340 * lock. Outside of the large map, kernel page table pages are never
11341 * freed, so at worst we will observe inconsistencies in the output.
11342 * Within the large map, ensure that PDP and PD page addresses are
11343 * valid before descending.
11345 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11348 sbuf_printf(sb, "\nRecursive map:\n");
11351 sbuf_printf(sb, "\nDirect map:\n");
11354 sbuf_printf(sb, "\nKernel map:\n");
11357 sbuf_printf(sb, "\nLarge map:\n");
11361 /* Convert to canonical form. */
11362 if (sva == 1ul << 47)
11366 pml4e = kernel_pml4[i];
11367 if ((pml4e & X86_PG_V) == 0) {
11368 sva = rounddown2(sva, NBPML4);
11369 sysctl_kmaps_dump(sb, &range, sva);
11373 pa = pml4e & PG_FRAME;
11374 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11376 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11378 if ((pdpe & X86_PG_V) == 0) {
11379 sva = rounddown2(sva, NBPDP);
11380 sysctl_kmaps_dump(sb, &range, sva);
11384 pa = pdpe & PG_FRAME;
11385 if ((pdpe & PG_PS) != 0) {
11386 sva = rounddown2(sva, NBPDP);
11387 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11393 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11394 vm_phys_paddr_to_vm_page(pa) == NULL) {
11396 * Page table pages for the large map may be
11397 * freed. Validate the next-level address
11398 * before descending.
11402 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11404 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11406 if ((pde & X86_PG_V) == 0) {
11407 sva = rounddown2(sva, NBPDR);
11408 sysctl_kmaps_dump(sb, &range, sva);
11412 pa = pde & PG_FRAME;
11413 if ((pde & PG_PS) != 0) {
11414 sva = rounddown2(sva, NBPDR);
11415 sysctl_kmaps_check(sb, &range, sva,
11416 pml4e, pdpe, pde, 0);
11421 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11422 vm_phys_paddr_to_vm_page(pa) == NULL) {
11424 * Page table pages for the large map
11425 * may be freed. Validate the
11426 * next-level address before descending.
11430 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11432 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11433 sva += PAGE_SIZE) {
11435 if ((pte & X86_PG_V) == 0) {
11436 sysctl_kmaps_dump(sb, &range,
11440 sysctl_kmaps_check(sb, &range, sva,
11441 pml4e, pdpe, pde, pte);
11448 error = sbuf_finish(sb);
11452 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11453 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
11454 NULL, 0, sysctl_kmaps, "A",
11455 "Dump kernel address layout");
11458 DB_SHOW_COMMAND(pte, pmap_print_pte)
11461 pml5_entry_t *pml5;
11462 pml4_entry_t *pml4;
11465 pt_entry_t *pte, PG_V;
11469 db_printf("show pte addr\n");
11472 va = (vm_offset_t)addr;
11474 if (kdb_thread != NULL)
11475 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11477 pmap = PCPU_GET(curpmap);
11479 PG_V = pmap_valid_bit(pmap);
11480 db_printf("VA 0x%016lx", va);
11482 if (pmap_is_la57(pmap)) {
11483 pml5 = pmap_pml5e(pmap, va);
11484 db_printf(" pml5e 0x%016lx", *pml5);
11485 if ((*pml5 & PG_V) == 0) {
11489 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11491 pml4 = pmap_pml4e(pmap, va);
11493 db_printf(" pml4e 0x%016lx", *pml4);
11494 if ((*pml4 & PG_V) == 0) {
11498 pdp = pmap_pml4e_to_pdpe(pml4, va);
11499 db_printf(" pdpe 0x%016lx", *pdp);
11500 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11504 pde = pmap_pdpe_to_pde(pdp, va);
11505 db_printf(" pde 0x%016lx", *pde);
11506 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11510 pte = pmap_pde_to_pte(pde, va);
11511 db_printf(" pte 0x%016lx\n", *pte);
11514 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11519 a = (vm_paddr_t)addr;
11520 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11522 db_printf("show phys2dmap addr\n");
11527 ptpages_show_page(int level, int idx, vm_page_t pg)
11529 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11530 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11534 ptpages_show_complain(int level, int idx, uint64_t pte)
11536 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11540 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11542 vm_page_t pg3, pg2, pg1;
11543 pml4_entry_t *pml4;
11548 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11549 for (i4 = 0; i4 < num_entries; i4++) {
11550 if ((pml4[i4] & PG_V) == 0)
11552 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11554 ptpages_show_complain(3, i4, pml4[i4]);
11557 ptpages_show_page(3, i4, pg3);
11558 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11559 for (i3 = 0; i3 < NPDPEPG; i3++) {
11560 if ((pdp[i3] & PG_V) == 0)
11562 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11564 ptpages_show_complain(2, i3, pdp[i3]);
11567 ptpages_show_page(2, i3, pg2);
11568 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11569 for (i2 = 0; i2 < NPDEPG; i2++) {
11570 if ((pd[i2] & PG_V) == 0)
11572 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11574 ptpages_show_complain(1, i2, pd[i2]);
11577 ptpages_show_page(1, i2, pg1);
11583 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11587 pml5_entry_t *pml5;
11592 pmap = (pmap_t)addr;
11594 pmap = PCPU_GET(curpmap);
11596 PG_V = pmap_valid_bit(pmap);
11598 if (pmap_is_la57(pmap)) {
11599 pml5 = pmap->pm_pmltop;
11600 for (i5 = 0; i5 < NUPML5E; i5++) {
11601 if ((pml5[i5] & PG_V) == 0)
11603 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11605 ptpages_show_complain(4, i5, pml5[i5]);
11608 ptpages_show_page(4, i5, pg);
11609 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11612 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11613 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);