2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/_unrhdr.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
132 #include <vm/vm_pager.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
137 #include <machine/intr_machdep.h>
138 #include <x86/apicvar.h>
139 #include <machine/cpu.h>
140 #include <machine/cputypes.h>
141 #include <machine/md_var.h>
142 #include <machine/pcb.h>
143 #include <machine/specialreg.h>
145 #include <machine/smp.h>
148 static __inline boolean_t
149 pmap_emulate_ad_bits(pmap_t pmap)
152 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
155 static __inline pt_entry_t
156 pmap_valid_bit(pmap_t pmap)
160 switch (pmap->pm_type) {
165 if (pmap_emulate_ad_bits(pmap))
166 mask = EPT_PG_EMUL_V;
171 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
177 static __inline pt_entry_t
178 pmap_rw_bit(pmap_t pmap)
182 switch (pmap->pm_type) {
187 if (pmap_emulate_ad_bits(pmap))
188 mask = EPT_PG_EMUL_RW;
193 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
199 static __inline pt_entry_t
200 pmap_global_bit(pmap_t pmap)
204 switch (pmap->pm_type) {
212 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
218 static __inline pt_entry_t
219 pmap_accessed_bit(pmap_t pmap)
223 switch (pmap->pm_type) {
228 if (pmap_emulate_ad_bits(pmap))
234 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
240 static __inline pt_entry_t
241 pmap_modified_bit(pmap_t pmap)
245 switch (pmap->pm_type) {
250 if (pmap_emulate_ad_bits(pmap))
256 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
262 #if !defined(DIAGNOSTIC)
263 #ifdef __GNUC_GNU_INLINE__
264 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
266 #define PMAP_INLINE extern inline
273 #define PV_STAT(x) do { x ; } while (0)
275 #define PV_STAT(x) do { } while (0)
278 #define pa_index(pa) ((pa) >> PDRSHIFT)
279 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
281 #define NPV_LIST_LOCKS MAXCPU
283 #define PHYS_TO_PV_LIST_LOCK(pa) \
284 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
286 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
287 struct rwlock **_lockp = (lockp); \
288 struct rwlock *_new_lock; \
290 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
291 if (_new_lock != *_lockp) { \
292 if (*_lockp != NULL) \
293 rw_wunlock(*_lockp); \
294 *_lockp = _new_lock; \
299 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
300 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
302 #define RELEASE_PV_LIST_LOCK(lockp) do { \
303 struct rwlock **_lockp = (lockp); \
305 if (*_lockp != NULL) { \
306 rw_wunlock(*_lockp); \
311 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
312 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
314 struct pmap kernel_pmap_store;
316 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
317 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
320 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
321 "Number of kernel page table pages allocated on bootup");
324 static vm_paddr_t dmaplimit;
325 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
328 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
330 static int pat_works = 1;
331 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
332 "Is page attribute table fully functional?");
334 static int pg_ps_enabled = 1;
335 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
336 "Are large page mappings enabled?");
338 #define PAT_INDEX_SIZE 8
339 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
341 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
342 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
343 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
344 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
346 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
347 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
348 static int ndmpdpphys; /* number of DMPDPphys pages */
350 static struct rwlock_padalign pvh_global_lock;
353 * Data for the pv entry allocation mechanism
355 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
356 static struct mtx pv_chunks_mutex;
357 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
358 static struct md_page *pv_table;
361 * All those kernel PT submaps that BSD is so fond of
363 pt_entry_t *CMAP1 = 0;
366 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
368 static struct unrhdr pcid_unr;
369 static struct mtx pcid_mtx;
370 int pmap_pcid_enabled = 1;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN, &pmap_pcid_enabled,
372 0, "Is TLB Context ID enabled ?");
373 int invpcid_works = 0;
374 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
375 "Is the invpcid instruction available ?");
378 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
385 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
387 return (sysctl_handle_64(oidp, &res, 0, req));
389 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
390 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
391 "Count of saved TLB context on switch");
396 static caddr_t crashdumpmap;
398 static void free_pv_chunk(struct pv_chunk *pc);
399 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
400 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
401 static int popcnt_pc_map_elem(uint64_t elem);
402 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
403 static void reserve_pv_entries(pmap_t pmap, int needed,
404 struct rwlock **lockp);
405 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
406 struct rwlock **lockp);
407 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
408 struct rwlock **lockp);
409 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
410 struct rwlock **lockp);
411 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
412 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
415 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
416 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
417 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
418 vm_offset_t va, struct rwlock **lockp);
419 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
421 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
422 vm_prot_t prot, struct rwlock **lockp);
423 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
424 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
425 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
426 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
427 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
428 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
429 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
430 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
431 struct rwlock **lockp);
432 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
434 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
435 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
436 struct spglist *free, struct rwlock **lockp);
437 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
438 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
439 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
440 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
441 struct spglist *free);
442 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
443 vm_page_t m, struct rwlock **lockp);
444 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
446 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
448 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
449 struct rwlock **lockp);
450 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
451 struct rwlock **lockp);
452 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
453 struct rwlock **lockp);
455 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
456 struct spglist *free);
457 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
458 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
461 * Move the kernel virtual free pointer to the next
462 * 2MB. This is used to help improve performance
463 * by using a large (2MB) page for much of the kernel
464 * (.text, .data, .bss)
467 pmap_kmem_choose(vm_offset_t addr)
469 vm_offset_t newaddr = addr;
471 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
475 /********************/
476 /* Inline functions */
477 /********************/
479 /* Return a non-clipped PD index for a given VA */
480 static __inline vm_pindex_t
481 pmap_pde_pindex(vm_offset_t va)
483 return (va >> PDRSHIFT);
487 /* Return various clipped indexes for a given VA */
488 static __inline vm_pindex_t
489 pmap_pte_index(vm_offset_t va)
492 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
495 static __inline vm_pindex_t
496 pmap_pde_index(vm_offset_t va)
499 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
502 static __inline vm_pindex_t
503 pmap_pdpe_index(vm_offset_t va)
506 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
509 static __inline vm_pindex_t
510 pmap_pml4e_index(vm_offset_t va)
513 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
516 /* Return a pointer to the PML4 slot that corresponds to a VA */
517 static __inline pml4_entry_t *
518 pmap_pml4e(pmap_t pmap, vm_offset_t va)
521 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
524 /* Return a pointer to the PDP slot that corresponds to a VA */
525 static __inline pdp_entry_t *
526 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
530 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
531 return (&pdpe[pmap_pdpe_index(va)]);
534 /* Return a pointer to the PDP slot that corresponds to a VA */
535 static __inline pdp_entry_t *
536 pmap_pdpe(pmap_t pmap, vm_offset_t va)
541 PG_V = pmap_valid_bit(pmap);
542 pml4e = pmap_pml4e(pmap, va);
543 if ((*pml4e & PG_V) == 0)
545 return (pmap_pml4e_to_pdpe(pml4e, va));
548 /* Return a pointer to the PD slot that corresponds to a VA */
549 static __inline pd_entry_t *
550 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
554 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
555 return (&pde[pmap_pde_index(va)]);
558 /* Return a pointer to the PD slot that corresponds to a VA */
559 static __inline pd_entry_t *
560 pmap_pde(pmap_t pmap, vm_offset_t va)
565 PG_V = pmap_valid_bit(pmap);
566 pdpe = pmap_pdpe(pmap, va);
567 if (pdpe == NULL || (*pdpe & PG_V) == 0)
569 return (pmap_pdpe_to_pde(pdpe, va));
572 /* Return a pointer to the PT slot that corresponds to a VA */
573 static __inline pt_entry_t *
574 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
578 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
579 return (&pte[pmap_pte_index(va)]);
582 /* Return a pointer to the PT slot that corresponds to a VA */
583 static __inline pt_entry_t *
584 pmap_pte(pmap_t pmap, vm_offset_t va)
589 PG_V = pmap_valid_bit(pmap);
590 pde = pmap_pde(pmap, va);
591 if (pde == NULL || (*pde & PG_V) == 0)
593 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
594 return ((pt_entry_t *)pde);
595 return (pmap_pde_to_pte(pde, va));
599 pmap_resident_count_inc(pmap_t pmap, int count)
602 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
603 pmap->pm_stats.resident_count += count;
607 pmap_resident_count_dec(pmap_t pmap, int count)
610 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
611 KASSERT(pmap->pm_stats.resident_count >= count,
612 ("pmap %p resident count underflow %ld %d", pmap,
613 pmap->pm_stats.resident_count, count));
614 pmap->pm_stats.resident_count -= count;
617 PMAP_INLINE pt_entry_t *
618 vtopte(vm_offset_t va)
620 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
622 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
624 return (PTmap + ((va >> PAGE_SHIFT) & mask));
627 static __inline pd_entry_t *
628 vtopde(vm_offset_t va)
630 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
632 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
634 return (PDmap + ((va >> PDRSHIFT) & mask));
638 allocpages(vm_paddr_t *firstaddr, int n)
643 bzero((void *)ret, n * PAGE_SIZE);
644 *firstaddr += n * PAGE_SIZE;
648 CTASSERT(powerof2(NDMPML4E));
650 /* number of kernel PDP slots */
651 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
654 nkpt_init(vm_paddr_t addr)
661 pt_pages = howmany(addr, 1 << PDRSHIFT);
662 pt_pages += NKPDPE(pt_pages);
665 * Add some slop beyond the bare minimum required for bootstrapping
668 * This is quite important when allocating KVA for kernel modules.
669 * The modules are required to be linked in the negative 2GB of
670 * the address space. If we run out of KVA in this region then
671 * pmap_growkernel() will need to allocate page table pages to map
672 * the entire 512GB of KVA space which is an unnecessary tax on
675 pt_pages += 8; /* 16MB additional slop for kernel modules */
681 create_pagetables(vm_paddr_t *firstaddr)
683 int i, j, ndm1g, nkpdpe;
689 /* Allocate page table pages for the direct map */
690 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
691 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
693 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
694 if (ndmpdpphys > NDMPML4E) {
696 * Each NDMPML4E allows 512 GB, so limit to that,
697 * and then readjust ndmpdp and ndmpdpphys.
699 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
700 Maxmem = atop(NDMPML4E * NBPML4);
701 ndmpdpphys = NDMPML4E;
702 ndmpdp = NDMPML4E * NPDEPG;
704 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
706 if ((amd_feature & AMDID_PAGE1GB) != 0)
707 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
709 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
710 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
713 KPML4phys = allocpages(firstaddr, 1);
714 KPDPphys = allocpages(firstaddr, NKPML4E);
717 * Allocate the initial number of kernel page table pages required to
718 * bootstrap. We defer this until after all memory-size dependent
719 * allocations are done (e.g. direct map), so that we don't have to
720 * build in too much slop in our estimate.
722 * Note that when NKPML4E > 1, we have an empty page underneath
723 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
724 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
726 nkpt_init(*firstaddr);
727 nkpdpe = NKPDPE(nkpt);
729 KPTphys = allocpages(firstaddr, nkpt);
730 KPDphys = allocpages(firstaddr, nkpdpe);
732 /* Fill in the underlying page table pages */
733 /* Nominally read-only (but really R/W) from zero to physfree */
734 /* XXX not fully used, underneath 2M pages */
735 pt_p = (pt_entry_t *)KPTphys;
736 for (i = 0; ptoa(i) < *firstaddr; i++)
737 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
739 /* Now map the page tables at their location within PTmap */
740 pd_p = (pd_entry_t *)KPDphys;
741 for (i = 0; i < nkpt; i++)
742 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
744 /* Map from zero to end of allocations under 2M pages */
745 /* This replaces some of the KPTphys entries above */
746 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
747 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
750 /* And connect up the PD to the PDP (leaving room for L4 pages) */
751 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
752 for (i = 0; i < nkpdpe; i++)
753 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
757 * Now, set up the direct map region using 2MB and/or 1GB pages. If
758 * the end of physical memory is not aligned to a 1GB page boundary,
759 * then the residual physical memory is mapped with 2MB pages. Later,
760 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
761 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
762 * that are partially used.
764 pd_p = (pd_entry_t *)DMPDphys;
765 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
766 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
767 /* Preset PG_M and PG_A because demotion expects it. */
768 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
771 pdp_p = (pdp_entry_t *)DMPDPphys;
772 for (i = 0; i < ndm1g; i++) {
773 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
774 /* Preset PG_M and PG_A because demotion expects it. */
775 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
778 for (j = 0; i < ndmpdp; i++, j++) {
779 pdp_p[i] = DMPDphys + ptoa(j);
780 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
783 /* And recursively map PML4 to itself in order to get PTmap */
784 p4_p = (pml4_entry_t *)KPML4phys;
785 p4_p[PML4PML4I] = KPML4phys;
786 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
788 /* Connect the Direct Map slot(s) up to the PML4. */
789 for (i = 0; i < ndmpdpphys; i++) {
790 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
791 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
794 /* Connect the KVA slots up to the PML4 */
795 for (i = 0; i < NKPML4E; i++) {
796 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
797 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
802 * Bootstrap the system enough to run with virtual memory.
804 * On amd64 this is called after mapping has already been enabled
805 * and just syncs the pmap module with what has already been done.
806 * [We can't call it easily with mapping off since the kernel is not
807 * mapped with PA == VA, hence we would have to relocate every address
808 * from the linked base (virtual) address "KERNBASE" to the actual
809 * (physical) address starting relative to 0]
812 pmap_bootstrap(vm_paddr_t *firstaddr)
818 * Create an initial set of page tables to run the kernel in.
820 create_pagetables(firstaddr);
822 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
823 virtual_avail = pmap_kmem_choose(virtual_avail);
825 virtual_end = VM_MAX_KERNEL_ADDRESS;
828 /* XXX do %cr0 as well */
829 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
831 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
832 load_cr4(rcr4() | CR4_SMEP);
835 * Initialize the kernel pmap (which is statically allocated).
837 PMAP_LOCK_INIT(kernel_pmap);
838 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
839 kernel_pmap->pm_cr3 = KPML4phys;
840 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
841 CPU_ZERO(&kernel_pmap->pm_save);
842 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
843 kernel_pmap->pm_flags = pmap_flags;
846 * Initialize the global pv list lock.
848 rw_init(&pvh_global_lock, "pmap pv global");
851 * Reserve some special page table entries/VA space for temporary
854 #define SYSMAP(c, p, v, n) \
855 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
861 * Crashdump maps. The first page is reused as CMAP1 for the
864 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
865 CADDR1 = crashdumpmap;
869 /* Initialize the PAT MSR. */
872 /* Initialize TLB Context Id. */
873 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
874 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
875 load_cr4(rcr4() | CR4_PCIDE);
876 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
877 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
878 /* Check for INVPCID support */
879 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
881 kernel_pmap->pm_pcid = 0;
883 pmap_pcid_enabled = 0;
886 pmap_pcid_enabled = 0;
895 int pat_table[PAT_INDEX_SIZE];
900 /* Bail if this CPU doesn't implement PAT. */
901 if ((cpu_feature & CPUID_PAT) == 0)
904 /* Set default PAT index table. */
905 for (i = 0; i < PAT_INDEX_SIZE; i++)
907 pat_table[PAT_WRITE_BACK] = 0;
908 pat_table[PAT_WRITE_THROUGH] = 1;
909 pat_table[PAT_UNCACHEABLE] = 3;
910 pat_table[PAT_WRITE_COMBINING] = 3;
911 pat_table[PAT_WRITE_PROTECTED] = 3;
912 pat_table[PAT_UNCACHED] = 3;
914 /* Initialize default PAT entries. */
915 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
916 PAT_VALUE(1, PAT_WRITE_THROUGH) |
917 PAT_VALUE(2, PAT_UNCACHED) |
918 PAT_VALUE(3, PAT_UNCACHEABLE) |
919 PAT_VALUE(4, PAT_WRITE_BACK) |
920 PAT_VALUE(5, PAT_WRITE_THROUGH) |
921 PAT_VALUE(6, PAT_UNCACHED) |
922 PAT_VALUE(7, PAT_UNCACHEABLE);
926 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
927 * Program 5 and 6 as WP and WC.
928 * Leave 4 and 7 as WB and UC.
930 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
931 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
932 PAT_VALUE(6, PAT_WRITE_COMBINING);
933 pat_table[PAT_UNCACHED] = 2;
934 pat_table[PAT_WRITE_PROTECTED] = 5;
935 pat_table[PAT_WRITE_COMBINING] = 6;
938 * Just replace PAT Index 2 with WC instead of UC-.
940 pat_msr &= ~PAT_MASK(2);
941 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
942 pat_table[PAT_WRITE_COMBINING] = 2;
947 load_cr4(cr4 & ~CR4_PGE);
949 /* Disable caches (CD = 1, NW = 0). */
951 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
953 /* Flushes caches and TLBs. */
957 /* Update PAT and index table. */
958 wrmsr(MSR_PAT, pat_msr);
959 for (i = 0; i < PAT_INDEX_SIZE; i++)
960 pat_index[i] = pat_table[i];
962 /* Flush caches and TLBs again. */
966 /* Restore caches and PGE. */
972 * Initialize a vm_page's machine-dependent fields.
975 pmap_page_init(vm_page_t m)
978 TAILQ_INIT(&m->md.pv_list);
979 m->md.pat_mode = PAT_WRITE_BACK;
983 * Initialize the pmap module.
984 * Called by vm_init, to initialize any structures that the pmap
985 * system needs to map virtual memory.
995 * Initialize the vm page array entries for the kernel pmap's
998 for (i = 0; i < nkpt; i++) {
999 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1000 KASSERT(mpte >= vm_page_array &&
1001 mpte < &vm_page_array[vm_page_array_size],
1002 ("pmap_init: page table page is out of range"));
1003 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1004 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1008 * If the kernel is running on a virtual machine, then it must assume
1009 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1010 * be prepared for the hypervisor changing the vendor and family that
1011 * are reported by CPUID. Consequently, the workaround for AMD Family
1012 * 10h Erratum 383 is enabled if the processor's feature set does not
1013 * include at least one feature that is only supported by older Intel
1014 * or newer AMD processors.
1016 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1017 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1018 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1020 workaround_erratum383 = 1;
1023 * Are large page mappings enabled?
1025 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1026 if (pg_ps_enabled) {
1027 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1028 ("pmap_init: can't assign to pagesizes[1]"));
1029 pagesizes[1] = NBPDR;
1033 * Initialize the pv chunk list mutex.
1035 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1038 * Initialize the pool of pv list locks.
1040 for (i = 0; i < NPV_LIST_LOCKS; i++)
1041 rw_init(&pv_list_locks[i], "pmap pv list");
1044 * Calculate the size of the pv head table for superpages.
1046 for (i = 0; phys_avail[i + 1]; i += 2);
1047 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
1050 * Allocate memory for the pv head table for superpages.
1052 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1054 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1056 for (i = 0; i < pv_npg; i++)
1057 TAILQ_INIT(&pv_table[i].pv_list);
1060 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1061 "2MB page mapping counters");
1063 static u_long pmap_pde_demotions;
1064 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1065 &pmap_pde_demotions, 0, "2MB page demotions");
1067 static u_long pmap_pde_mappings;
1068 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1069 &pmap_pde_mappings, 0, "2MB page mappings");
1071 static u_long pmap_pde_p_failures;
1072 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1073 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1075 static u_long pmap_pde_promotions;
1076 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1077 &pmap_pde_promotions, 0, "2MB page promotions");
1079 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1080 "1GB page mapping counters");
1082 static u_long pmap_pdpe_demotions;
1083 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1084 &pmap_pdpe_demotions, 0, "1GB page demotions");
1086 /***************************************************
1087 * Low level helper routines.....
1088 ***************************************************/
1091 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1093 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1095 switch (pmap->pm_type) {
1097 /* Verify that both PAT bits are not set at the same time */
1098 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1099 ("Invalid PAT bits in entry %#lx", entry));
1101 /* Swap the PAT bits if one of them is set */
1102 if ((entry & x86_pat_bits) != 0)
1103 entry ^= x86_pat_bits;
1107 * Nothing to do - the memory attributes are represented
1108 * the same way for regular pages and superpages.
1112 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1119 * Determine the appropriate bits to set in a PTE or PDE for a specified
1123 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1125 int cache_bits, pat_flag, pat_idx;
1127 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1128 panic("Unknown caching mode %d\n", mode);
1130 switch (pmap->pm_type) {
1132 /* The PAT bit is different for PTE's and PDE's. */
1133 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1135 /* Map the caching mode to a PAT index. */
1136 pat_idx = pat_index[mode];
1138 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1141 cache_bits |= pat_flag;
1143 cache_bits |= PG_NC_PCD;
1145 cache_bits |= PG_NC_PWT;
1149 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1153 panic("unsupported pmap type %d", pmap->pm_type);
1156 return (cache_bits);
1160 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1164 switch (pmap->pm_type) {
1166 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1169 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1172 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1178 static __inline boolean_t
1179 pmap_ps_enabled(pmap_t pmap)
1182 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1186 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1189 switch (pmap->pm_type) {
1195 * This is a little bogus since the generation number is
1196 * supposed to be bumped up when a region of the address
1197 * space is invalidated in the page tables.
1199 * In this case the old PDE entry is valid but yet we want
1200 * to make sure that any mappings using the old entry are
1201 * invalidated in the TLB.
1203 * The reason this works as expected is because we rendezvous
1204 * "all" host cpus and force any vcpu context to exit as a
1207 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1210 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1212 pde_store(pde, newpde);
1216 * After changing the page size for the specified virtual address in the page
1217 * table, flush the corresponding entries from the processor's TLB. Only the
1218 * calling processor's TLB is affected.
1220 * The calling thread must be pinned to a processor.
1223 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1227 if (pmap->pm_type == PT_EPT)
1230 KASSERT(pmap->pm_type == PT_X86,
1231 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1233 PG_G = pmap_global_bit(pmap);
1235 if ((newpde & PG_PS) == 0)
1236 /* Demotion: flush a specific 2MB page mapping. */
1238 else if ((newpde & PG_G) == 0)
1240 * Promotion: flush every 4KB page mapping from the TLB
1241 * because there are too many to flush individually.
1246 * Promotion: flush every 4KB page mapping from the TLB,
1247 * including any global (PG_G) mappings.
1255 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1257 struct invpcid_descr d;
1260 if (invpcid_works) {
1261 d.pcid = pmap->pm_pcid;
1264 invpcid(&d, INVPCID_ADDR);
1270 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1272 load_cr3(cr3 | CR3_PCID_SAVE);
1277 * For SMP, these functions have to use the IPI mechanism for coherence.
1279 * N.B.: Before calling any of the following TLB invalidation functions,
1280 * the calling processor must ensure that all stores updating a non-
1281 * kernel page table are globally performed. Otherwise, another
1282 * processor could cache an old, pre-update entry without being
1283 * invalidated. This can happen one of two ways: (1) The pmap becomes
1284 * active on another processor after its pm_active field is checked by
1285 * one of the following functions but before a store updating the page
1286 * table is globally performed. (2) The pmap becomes active on another
1287 * processor before its pm_active field is checked but due to
1288 * speculative loads one of the following functions stills reads the
1289 * pmap as inactive on the other processor.
1291 * The kernel page table is exempt because its pm_active field is
1292 * immutable. The kernel page table is always active on every
1297 * Interrupt the cpus that are executing in the guest context.
1298 * This will force the vcpu to exit and the cached EPT mappings
1299 * will be invalidated by the host before the next vmresume.
1301 static __inline void
1302 pmap_invalidate_ept(pmap_t pmap)
1307 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1308 ("pmap_invalidate_ept: absurd pm_active"));
1311 * The TLB mappings associated with a vcpu context are not
1312 * flushed each time a different vcpu is chosen to execute.
1314 * This is in contrast with a process's vtop mappings that
1315 * are flushed from the TLB on each context switch.
1317 * Therefore we need to do more than just a TLB shootdown on
1318 * the active cpus in 'pmap->pm_active'. To do this we keep
1319 * track of the number of invalidations performed on this pmap.
1321 * Each vcpu keeps a cache of this counter and compares it
1322 * just before a vmresume. If the counter is out-of-date an
1323 * invept will be done to flush stale mappings from the TLB.
1325 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1328 * Force the vcpu to exit and trap back into the hypervisor.
1330 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1331 ipi_selected(pmap->pm_active, ipinum);
1336 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1338 cpuset_t other_cpus;
1341 if (pmap->pm_type == PT_EPT) {
1342 pmap_invalidate_ept(pmap);
1346 KASSERT(pmap->pm_type == PT_X86,
1347 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1350 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1351 if (!pmap_pcid_enabled) {
1354 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1355 if (pmap == PCPU_GET(curpmap))
1358 pmap_invalidate_page_pcid(pmap, va);
1363 smp_invlpg(pmap, va);
1365 cpuid = PCPU_GET(cpuid);
1366 other_cpus = all_cpus;
1367 CPU_CLR(cpuid, &other_cpus);
1368 if (CPU_ISSET(cpuid, &pmap->pm_active))
1370 else if (pmap_pcid_enabled) {
1371 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1372 pmap_invalidate_page_pcid(pmap, va);
1376 if (pmap_pcid_enabled)
1377 CPU_AND(&other_cpus, &pmap->pm_save);
1379 CPU_AND(&other_cpus, &pmap->pm_active);
1380 if (!CPU_EMPTY(&other_cpus))
1381 smp_masked_invlpg(other_cpus, pmap, va);
1387 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1389 struct invpcid_descr d;
1393 if (invpcid_works) {
1394 d.pcid = pmap->pm_pcid;
1396 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1398 invpcid(&d, INVPCID_ADDR);
1405 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1406 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1408 load_cr3(cr3 | CR3_PCID_SAVE);
1413 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1415 cpuset_t other_cpus;
1419 if (pmap->pm_type == PT_EPT) {
1420 pmap_invalidate_ept(pmap);
1424 KASSERT(pmap->pm_type == PT_X86,
1425 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1428 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1429 if (!pmap_pcid_enabled) {
1430 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1433 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1434 if (pmap == PCPU_GET(curpmap)) {
1435 for (addr = sva; addr < eva;
1439 pmap_invalidate_range_pcid(pmap,
1446 smp_invlpg_range(pmap, sva, eva);
1448 cpuid = PCPU_GET(cpuid);
1449 other_cpus = all_cpus;
1450 CPU_CLR(cpuid, &other_cpus);
1451 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1452 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1454 } else if (pmap_pcid_enabled) {
1455 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1456 pmap_invalidate_range_pcid(pmap, sva, eva);
1460 if (pmap_pcid_enabled)
1461 CPU_AND(&other_cpus, &pmap->pm_save);
1463 CPU_AND(&other_cpus, &pmap->pm_active);
1464 if (!CPU_EMPTY(&other_cpus))
1465 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1471 pmap_invalidate_all(pmap_t pmap)
1473 cpuset_t other_cpus;
1474 struct invpcid_descr d;
1478 if (pmap->pm_type == PT_EPT) {
1479 pmap_invalidate_ept(pmap);
1483 KASSERT(pmap->pm_type == PT_X86,
1484 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1487 cpuid = PCPU_GET(cpuid);
1488 if (pmap == kernel_pmap ||
1489 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1490 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1491 if (invpcid_works) {
1492 bzero(&d, sizeof(d));
1493 invpcid(&d, INVPCID_CTXGLOB);
1497 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1500 other_cpus = all_cpus;
1501 CPU_CLR(cpuid, &other_cpus);
1504 * This logic is duplicated in the Xinvltlb shootdown
1507 if (pmap_pcid_enabled) {
1508 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1509 if (invpcid_works) {
1510 d.pcid = pmap->pm_pcid;
1513 invpcid(&d, INVPCID_CTX);
1519 * Bit 63 is clear, pcid TLB
1520 * entries are invalidated.
1522 load_cr3(pmap->pm_cr3);
1523 load_cr3(cr3 | CR3_PCID_SAVE);
1529 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1531 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1532 if (pmap_pcid_enabled)
1533 CPU_AND(&other_cpus, &pmap->pm_save);
1535 CPU_AND(&other_cpus, &pmap->pm_active);
1536 if (!CPU_EMPTY(&other_cpus))
1537 smp_masked_invltlb(other_cpus, pmap);
1543 pmap_invalidate_cache(void)
1553 cpuset_t invalidate; /* processors that invalidate their TLB */
1558 u_int store; /* processor that updates the PDE */
1562 pmap_update_pde_action(void *arg)
1564 struct pde_action *act = arg;
1566 if (act->store == PCPU_GET(cpuid))
1567 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1571 pmap_update_pde_teardown(void *arg)
1573 struct pde_action *act = arg;
1575 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1576 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1580 * Change the page size for the specified virtual address in a way that
1581 * prevents any possibility of the TLB ever having two entries that map the
1582 * same virtual address using different page sizes. This is the recommended
1583 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1584 * machine check exception for a TLB state that is improperly diagnosed as a
1588 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1590 struct pde_action act;
1591 cpuset_t active, other_cpus;
1595 cpuid = PCPU_GET(cpuid);
1596 other_cpus = all_cpus;
1597 CPU_CLR(cpuid, &other_cpus);
1598 if (pmap == kernel_pmap || pmap->pm_type == PT_EPT)
1601 active = pmap->pm_active;
1602 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1604 if (CPU_OVERLAP(&active, &other_cpus)) {
1606 act.invalidate = active;
1610 act.newpde = newpde;
1611 CPU_SET(cpuid, &active);
1612 smp_rendezvous_cpus(active,
1613 smp_no_rendevous_barrier, pmap_update_pde_action,
1614 pmap_update_pde_teardown, &act);
1616 pmap_update_pde_store(pmap, pde, newpde);
1617 if (CPU_ISSET(cpuid, &active))
1618 pmap_update_pde_invalidate(pmap, va, newpde);
1624 * Normal, non-SMP, invalidation functions.
1625 * We inline these within pmap.c for speed.
1628 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1631 switch (pmap->pm_type) {
1633 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1640 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type);
1645 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1649 switch (pmap->pm_type) {
1651 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1652 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1659 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type);
1664 pmap_invalidate_all(pmap_t pmap)
1667 switch (pmap->pm_type) {
1669 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1676 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type);
1681 pmap_invalidate_cache(void)
1688 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1691 pmap_update_pde_store(pmap, pde, newpde);
1692 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1693 pmap_update_pde_invalidate(pmap, va, newpde);
1695 CPU_ZERO(&pmap->pm_save);
1699 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1702 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1705 KASSERT((sva & PAGE_MASK) == 0,
1706 ("pmap_invalidate_cache_range: sva not page-aligned"));
1707 KASSERT((eva & PAGE_MASK) == 0,
1708 ("pmap_invalidate_cache_range: eva not page-aligned"));
1710 if (cpu_feature & CPUID_SS)
1711 ; /* If "Self Snoop" is supported, do nothing. */
1712 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1713 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1716 * XXX: Some CPUs fault, hang, or trash the local APIC
1717 * registers if we use CLFLUSH on the local APIC
1718 * range. The local APIC is always uncached, so we
1719 * don't need to flush for that range anyway.
1721 if (pmap_kextract(sva) == lapic_paddr)
1725 * Otherwise, do per-cache line flush. Use the mfence
1726 * instruction to insure that previous stores are
1727 * included in the write-back. The processor
1728 * propagates flush to other processors in the cache
1732 for (; sva < eva; sva += cpu_clflush_line_size)
1738 * No targeted cache flush methods are supported by CPU,
1739 * or the supplied range is bigger than 2MB.
1740 * Globally invalidate cache.
1742 pmap_invalidate_cache();
1747 * Remove the specified set of pages from the data and instruction caches.
1749 * In contrast to pmap_invalidate_cache_range(), this function does not
1750 * rely on the CPU's self-snoop feature, because it is intended for use
1751 * when moving pages into a different cache domain.
1754 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1756 vm_offset_t daddr, eva;
1759 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1760 (cpu_feature & CPUID_CLFSH) == 0)
1761 pmap_invalidate_cache();
1764 for (i = 0; i < count; i++) {
1765 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1766 eva = daddr + PAGE_SIZE;
1767 for (; daddr < eva; daddr += cpu_clflush_line_size)
1775 * Routine: pmap_extract
1777 * Extract the physical page address associated
1778 * with the given map/virtual_address pair.
1781 pmap_extract(pmap_t pmap, vm_offset_t va)
1785 pt_entry_t *pte, PG_V;
1789 PG_V = pmap_valid_bit(pmap);
1791 pdpe = pmap_pdpe(pmap, va);
1792 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1793 if ((*pdpe & PG_PS) != 0)
1794 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1796 pde = pmap_pdpe_to_pde(pdpe, va);
1797 if ((*pde & PG_V) != 0) {
1798 if ((*pde & PG_PS) != 0) {
1799 pa = (*pde & PG_PS_FRAME) |
1802 pte = pmap_pde_to_pte(pde, va);
1803 pa = (*pte & PG_FRAME) |
1814 * Routine: pmap_extract_and_hold
1816 * Atomically extract and hold the physical page
1817 * with the given pmap and virtual address pair
1818 * if that mapping permits the given protection.
1821 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1823 pd_entry_t pde, *pdep;
1824 pt_entry_t pte, PG_RW, PG_V;
1830 PG_RW = pmap_rw_bit(pmap);
1831 PG_V = pmap_valid_bit(pmap);
1834 pdep = pmap_pde(pmap, va);
1835 if (pdep != NULL && (pde = *pdep)) {
1837 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1838 if (vm_page_pa_tryrelock(pmap, (pde &
1839 PG_PS_FRAME) | (va & PDRMASK), &pa))
1841 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1846 pte = *pmap_pde_to_pte(pdep, va);
1848 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1849 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1852 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1863 pmap_kextract(vm_offset_t va)
1868 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1869 pa = DMAP_TO_PHYS(va);
1873 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1876 * Beware of a concurrent promotion that changes the
1877 * PDE at this point! For example, vtopte() must not
1878 * be used to access the PTE because it would use the
1879 * new PDE. It is, however, safe to use the old PDE
1880 * because the page table page is preserved by the
1883 pa = *pmap_pde_to_pte(&pde, va);
1884 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1890 /***************************************************
1891 * Low level mapping routines.....
1892 ***************************************************/
1895 * Add a wired page to the kva.
1896 * Note: not SMP coherent.
1899 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1904 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1907 static __inline void
1908 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1914 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1915 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1919 * Remove a page from the kernel pagetables.
1920 * Note: not SMP coherent.
1923 pmap_kremove(vm_offset_t va)
1932 * Used to map a range of physical addresses into kernel
1933 * virtual address space.
1935 * The value passed in '*virt' is a suggested virtual address for
1936 * the mapping. Architectures which can support a direct-mapped
1937 * physical to virtual region can return the appropriate address
1938 * within that region, leaving '*virt' unchanged. Other
1939 * architectures should map the pages starting at '*virt' and
1940 * update '*virt' with the first usable address after the mapped
1944 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1946 return PHYS_TO_DMAP(start);
1951 * Add a list of wired pages to the kva
1952 * this routine is only used for temporary
1953 * kernel mappings that do not need to have
1954 * page modification or references recorded.
1955 * Note that old mappings are simply written
1956 * over. The page *must* be wired.
1957 * Note: SMP coherent. Uses a ranged shootdown IPI.
1960 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1962 pt_entry_t *endpte, oldpte, pa, *pte;
1968 endpte = pte + count;
1969 while (pte < endpte) {
1971 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
1972 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
1973 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
1975 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
1979 if (__predict_false((oldpte & X86_PG_V) != 0))
1980 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1985 * This routine tears out page mappings from the
1986 * kernel -- it is meant only for temporary mappings.
1987 * Note: SMP coherent. Uses a ranged shootdown IPI.
1990 pmap_qremove(vm_offset_t sva, int count)
1995 while (count-- > 0) {
1996 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2000 pmap_invalidate_range(kernel_pmap, sva, va);
2003 /***************************************************
2004 * Page table page management routines.....
2005 ***************************************************/
2006 static __inline void
2007 pmap_free_zero_pages(struct spglist *free)
2011 while ((m = SLIST_FIRST(free)) != NULL) {
2012 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2013 /* Preserve the page's PG_ZERO setting. */
2014 vm_page_free_toq(m);
2019 * Schedule the specified unused page table page to be freed. Specifically,
2020 * add the page to the specified list of pages that will be released to the
2021 * physical memory manager after the TLB has been updated.
2023 static __inline void
2024 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2025 boolean_t set_PG_ZERO)
2029 m->flags |= PG_ZERO;
2031 m->flags &= ~PG_ZERO;
2032 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2036 * Inserts the specified page table page into the specified pmap's collection
2037 * of idle page table pages. Each of a pmap's page table pages is responsible
2038 * for mapping a distinct range of virtual addresses. The pmap's collection is
2039 * ordered by this virtual address range.
2042 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2045 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2046 return (vm_radix_insert(&pmap->pm_root, mpte));
2050 * Looks for a page table page mapping the specified virtual address in the
2051 * specified pmap's collection of idle page table pages. Returns NULL if there
2052 * is no page table page corresponding to the specified virtual address.
2054 static __inline vm_page_t
2055 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2058 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2059 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2063 * Removes the specified page table page from the specified pmap's collection
2064 * of idle page table pages. The specified page table page must be a member of
2065 * the pmap's collection.
2067 static __inline void
2068 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2071 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2072 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2076 * Decrements a page table page's wire count, which is used to record the
2077 * number of valid page table entries within the page. If the wire count
2078 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2079 * page table page was unmapped and FALSE otherwise.
2081 static inline boolean_t
2082 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2086 if (m->wire_count == 0) {
2087 _pmap_unwire_ptp(pmap, va, m, free);
2094 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2097 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2099 * unmap the page table page
2101 if (m->pindex >= (NUPDE + NUPDPE)) {
2104 pml4 = pmap_pml4e(pmap, va);
2106 } else if (m->pindex >= NUPDE) {
2109 pdp = pmap_pdpe(pmap, va);
2114 pd = pmap_pde(pmap, va);
2117 pmap_resident_count_dec(pmap, 1);
2118 if (m->pindex < NUPDE) {
2119 /* We just released a PT, unhold the matching PD */
2122 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2123 pmap_unwire_ptp(pmap, va, pdpg, free);
2125 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2126 /* We just released a PD, unhold the matching PDP */
2129 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2130 pmap_unwire_ptp(pmap, va, pdppg, free);
2134 * This is a release store so that the ordinary store unmapping
2135 * the page table page is globally performed before TLB shoot-
2138 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
2141 * Put page on a list so that it is released after
2142 * *ALL* TLB shootdown is done
2144 pmap_add_delayed_free_list(m, free, TRUE);
2148 * After removing a page table entry, this routine is used to
2149 * conditionally free the page, and manage the hold/wire counts.
2152 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2153 struct spglist *free)
2157 if (va >= VM_MAXUSER_ADDRESS)
2159 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2160 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2161 return (pmap_unwire_ptp(pmap, va, mpte, free));
2165 pmap_pinit0(pmap_t pmap)
2168 PMAP_LOCK_INIT(pmap);
2169 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2170 pmap->pm_cr3 = KPML4phys;
2171 pmap->pm_root.rt_root = 0;
2172 CPU_ZERO(&pmap->pm_active);
2173 CPU_ZERO(&pmap->pm_save);
2174 PCPU_SET(curpmap, pmap);
2175 TAILQ_INIT(&pmap->pm_pvchunk);
2176 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2177 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
2178 pmap->pm_flags = pmap_flags;
2182 * Initialize a preallocated and zeroed pmap structure,
2183 * such as one in a vmspace structure.
2186 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2189 vm_paddr_t pml4phys;
2193 * allocate the page directory page
2195 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2196 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2199 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2200 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2202 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2204 if ((pml4pg->flags & PG_ZERO) == 0)
2205 pagezero(pmap->pm_pml4);
2208 * Do not install the host kernel mappings in the nested page
2209 * tables. These mappings are meaningless in the guest physical
2212 if ((pmap->pm_type = pm_type) == PT_X86) {
2213 pmap->pm_cr3 = pml4phys;
2215 /* Wire in kernel global address entries. */
2216 for (i = 0; i < NKPML4E; i++) {
2217 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2218 X86_PG_RW | X86_PG_V | PG_U;
2220 for (i = 0; i < ndmpdpphys; i++) {
2221 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2222 X86_PG_RW | X86_PG_V | PG_U;
2225 /* install self-referential address mapping entry(s) */
2226 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2227 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2229 if (pmap_pcid_enabled) {
2230 pmap->pm_pcid = alloc_unr(&pcid_unr);
2231 if (pmap->pm_pcid != -1)
2232 pmap->pm_cr3 |= pmap->pm_pcid;
2236 pmap->pm_root.rt_root = 0;
2237 CPU_ZERO(&pmap->pm_active);
2238 TAILQ_INIT(&pmap->pm_pvchunk);
2239 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2240 pmap->pm_flags = flags;
2241 pmap->pm_eptgen = 0;
2242 CPU_ZERO(&pmap->pm_save);
2248 pmap_pinit(pmap_t pmap)
2251 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2255 * This routine is called if the desired page table page does not exist.
2257 * If page table page allocation fails, this routine may sleep before
2258 * returning NULL. It sleeps only if a lock pointer was given.
2260 * Note: If a page allocation fails at page table level two or three,
2261 * one or two pages may be held during the wait, only to be released
2262 * afterwards. This conservative approach is easily argued to avoid
2266 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2268 vm_page_t m, pdppg, pdpg;
2269 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2271 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2273 PG_A = pmap_accessed_bit(pmap);
2274 PG_M = pmap_modified_bit(pmap);
2275 PG_V = pmap_valid_bit(pmap);
2276 PG_RW = pmap_rw_bit(pmap);
2279 * Allocate a page table page.
2281 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2282 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2283 if (lockp != NULL) {
2284 RELEASE_PV_LIST_LOCK(lockp);
2286 rw_runlock(&pvh_global_lock);
2288 rw_rlock(&pvh_global_lock);
2293 * Indicate the need to retry. While waiting, the page table
2294 * page may have been allocated.
2298 if ((m->flags & PG_ZERO) == 0)
2302 * Map the pagetable page into the process address space, if
2303 * it isn't already there.
2306 if (ptepindex >= (NUPDE + NUPDPE)) {
2308 vm_pindex_t pml4index;
2310 /* Wire up a new PDPE page */
2311 pml4index = ptepindex - (NUPDE + NUPDPE);
2312 pml4 = &pmap->pm_pml4[pml4index];
2313 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2315 } else if (ptepindex >= NUPDE) {
2316 vm_pindex_t pml4index;
2317 vm_pindex_t pdpindex;
2321 /* Wire up a new PDE page */
2322 pdpindex = ptepindex - NUPDE;
2323 pml4index = pdpindex >> NPML4EPGSHIFT;
2325 pml4 = &pmap->pm_pml4[pml4index];
2326 if ((*pml4 & PG_V) == 0) {
2327 /* Have to allocate a new pdp, recurse */
2328 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2331 atomic_subtract_int(&cnt.v_wire_count, 1);
2332 vm_page_free_zero(m);
2336 /* Add reference to pdp page */
2337 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2338 pdppg->wire_count++;
2340 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2342 /* Now find the pdp page */
2343 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2344 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2347 vm_pindex_t pml4index;
2348 vm_pindex_t pdpindex;
2353 /* Wire up a new PTE page */
2354 pdpindex = ptepindex >> NPDPEPGSHIFT;
2355 pml4index = pdpindex >> NPML4EPGSHIFT;
2357 /* First, find the pdp and check that its valid. */
2358 pml4 = &pmap->pm_pml4[pml4index];
2359 if ((*pml4 & PG_V) == 0) {
2360 /* Have to allocate a new pd, recurse */
2361 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2364 atomic_subtract_int(&cnt.v_wire_count, 1);
2365 vm_page_free_zero(m);
2368 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2369 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2371 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2372 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2373 if ((*pdp & PG_V) == 0) {
2374 /* Have to allocate a new pd, recurse */
2375 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2378 atomic_subtract_int(&cnt.v_wire_count,
2380 vm_page_free_zero(m);
2384 /* Add reference to the pd page */
2385 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2389 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2391 /* Now we know where the page directory page is */
2392 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2393 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2396 pmap_resident_count_inc(pmap, 1);
2402 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2404 vm_pindex_t pdpindex, ptepindex;
2405 pdp_entry_t *pdpe, PG_V;
2408 PG_V = pmap_valid_bit(pmap);
2411 pdpe = pmap_pdpe(pmap, va);
2412 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2413 /* Add a reference to the pd page. */
2414 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2417 /* Allocate a pd page. */
2418 ptepindex = pmap_pde_pindex(va);
2419 pdpindex = ptepindex >> NPDPEPGSHIFT;
2420 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2421 if (pdpg == NULL && lockp != NULL)
2428 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2430 vm_pindex_t ptepindex;
2431 pd_entry_t *pd, PG_V;
2434 PG_V = pmap_valid_bit(pmap);
2437 * Calculate pagetable page index
2439 ptepindex = pmap_pde_pindex(va);
2442 * Get the page directory entry
2444 pd = pmap_pde(pmap, va);
2447 * This supports switching from a 2MB page to a
2450 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2451 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2453 * Invalidation of the 2MB page mapping may have caused
2454 * the deallocation of the underlying PD page.
2461 * If the page table page is mapped, we just increment the
2462 * hold count, and activate it.
2464 if (pd != NULL && (*pd & PG_V) != 0) {
2465 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2469 * Here if the pte page isn't mapped, or if it has been
2472 m = _pmap_allocpte(pmap, ptepindex, lockp);
2473 if (m == NULL && lockp != NULL)
2480 /***************************************************
2481 * Pmap allocation/deallocation routines.
2482 ***************************************************/
2485 * Release any resources held by the given physical map.
2486 * Called when a pmap initialized by pmap_pinit is being released.
2487 * Should only be called if the map contains no valid mappings.
2490 pmap_release(pmap_t pmap)
2495 KASSERT(pmap->pm_stats.resident_count == 0,
2496 ("pmap_release: pmap resident count %ld != 0",
2497 pmap->pm_stats.resident_count));
2498 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2499 ("pmap_release: pmap has reserved page table page(s)"));
2501 if (pmap_pcid_enabled) {
2503 * Invalidate any left TLB entries, to allow the reuse
2506 pmap_invalidate_all(pmap);
2509 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2511 for (i = 0; i < NKPML4E; i++) /* KVA */
2512 pmap->pm_pml4[KPML4BASE + i] = 0;
2513 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2514 pmap->pm_pml4[DMPML4I + i] = 0;
2515 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2518 atomic_subtract_int(&cnt.v_wire_count, 1);
2519 vm_page_free_zero(m);
2520 if (pmap->pm_pcid != -1)
2521 free_unr(&pcid_unr, pmap->pm_pcid);
2525 kvm_size(SYSCTL_HANDLER_ARGS)
2527 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2529 return sysctl_handle_long(oidp, &ksize, 0, req);
2531 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2532 0, 0, kvm_size, "LU", "Size of KVM");
2535 kvm_free(SYSCTL_HANDLER_ARGS)
2537 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2539 return sysctl_handle_long(oidp, &kfree, 0, req);
2541 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2542 0, 0, kvm_free, "LU", "Amount of KVM free");
2545 * grow the number of kernel page table entries, if needed
2548 pmap_growkernel(vm_offset_t addr)
2552 pd_entry_t *pde, newpdir;
2555 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2558 * Return if "addr" is within the range of kernel page table pages
2559 * that were preallocated during pmap bootstrap. Moreover, leave
2560 * "kernel_vm_end" and the kernel page table as they were.
2562 * The correctness of this action is based on the following
2563 * argument: vm_map_findspace() allocates contiguous ranges of the
2564 * kernel virtual address space. It calls this function if a range
2565 * ends after "kernel_vm_end". If the kernel is mapped between
2566 * "kernel_vm_end" and "addr", then the range cannot begin at
2567 * "kernel_vm_end". In fact, its beginning address cannot be less
2568 * than the kernel. Thus, there is no immediate need to allocate
2569 * any new kernel page table pages between "kernel_vm_end" and
2572 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2575 addr = roundup2(addr, NBPDR);
2576 if (addr - 1 >= kernel_map->max_offset)
2577 addr = kernel_map->max_offset;
2578 while (kernel_vm_end < addr) {
2579 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2580 if ((*pdpe & X86_PG_V) == 0) {
2581 /* We need a new PDP entry */
2582 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2583 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2584 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2586 panic("pmap_growkernel: no memory to grow kernel");
2587 if ((nkpg->flags & PG_ZERO) == 0)
2588 pmap_zero_page(nkpg);
2589 paddr = VM_PAGE_TO_PHYS(nkpg);
2590 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2591 X86_PG_A | X86_PG_M);
2592 continue; /* try again */
2594 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2595 if ((*pde & X86_PG_V) != 0) {
2596 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2597 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2598 kernel_vm_end = kernel_map->max_offset;
2604 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2605 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2608 panic("pmap_growkernel: no memory to grow kernel");
2609 if ((nkpg->flags & PG_ZERO) == 0)
2610 pmap_zero_page(nkpg);
2611 paddr = VM_PAGE_TO_PHYS(nkpg);
2612 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2613 pde_store(pde, newpdir);
2615 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2616 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2617 kernel_vm_end = kernel_map->max_offset;
2624 /***************************************************
2625 * page management routines.
2626 ***************************************************/
2628 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2629 CTASSERT(_NPCM == 3);
2630 CTASSERT(_NPCPV == 168);
2632 static __inline struct pv_chunk *
2633 pv_to_chunk(pv_entry_t pv)
2636 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2639 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2641 #define PC_FREE0 0xfffffffffffffffful
2642 #define PC_FREE1 0xfffffffffffffffful
2643 #define PC_FREE2 0x000000fffffffffful
2645 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2648 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2650 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2651 "Current number of pv entry chunks");
2652 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2653 "Current number of pv entry chunks allocated");
2654 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2655 "Current number of pv entry chunks frees");
2656 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2657 "Number of times tried to get a chunk page but failed.");
2659 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2660 static int pv_entry_spare;
2662 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2663 "Current number of pv entry frees");
2664 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2665 "Current number of pv entry allocs");
2666 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2667 "Current number of pv entries");
2668 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2669 "Current number of spare pv entries");
2673 * We are in a serious low memory condition. Resort to
2674 * drastic measures to free some pages so we can allocate
2675 * another pv entry chunk.
2677 * Returns NULL if PV entries were reclaimed from the specified pmap.
2679 * We do not, however, unmap 2mpages because subsequent accesses will
2680 * allocate per-page pv entries until repromotion occurs, thereby
2681 * exacerbating the shortage of free pv entries.
2684 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2686 struct pch new_tail;
2687 struct pv_chunk *pc;
2688 struct md_page *pvh;
2691 pt_entry_t *pte, tpte;
2692 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2696 struct spglist free;
2698 int bit, field, freed;
2700 rw_assert(&pvh_global_lock, RA_LOCKED);
2701 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2702 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2705 PG_G = PG_A = PG_M = PG_RW = 0;
2707 TAILQ_INIT(&new_tail);
2708 mtx_lock(&pv_chunks_mutex);
2709 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2710 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2711 mtx_unlock(&pv_chunks_mutex);
2712 if (pmap != pc->pc_pmap) {
2714 pmap_invalidate_all(pmap);
2715 if (pmap != locked_pmap)
2719 /* Avoid deadlock and lock recursion. */
2720 if (pmap > locked_pmap) {
2721 RELEASE_PV_LIST_LOCK(lockp);
2723 } else if (pmap != locked_pmap &&
2724 !PMAP_TRYLOCK(pmap)) {
2726 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2727 mtx_lock(&pv_chunks_mutex);
2730 PG_G = pmap_global_bit(pmap);
2731 PG_A = pmap_accessed_bit(pmap);
2732 PG_M = pmap_modified_bit(pmap);
2733 PG_RW = pmap_rw_bit(pmap);
2737 * Destroy every non-wired, 4 KB page mapping in the chunk.
2740 for (field = 0; field < _NPCM; field++) {
2741 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2742 inuse != 0; inuse &= ~(1UL << bit)) {
2744 pv = &pc->pc_pventry[field * 64 + bit];
2746 pde = pmap_pde(pmap, va);
2747 if ((*pde & PG_PS) != 0)
2749 pte = pmap_pde_to_pte(pde, va);
2750 if ((*pte & PG_W) != 0)
2752 tpte = pte_load_clear(pte);
2753 if ((tpte & PG_G) != 0)
2754 pmap_invalidate_page(pmap, va);
2755 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2756 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2758 if ((tpte & PG_A) != 0)
2759 vm_page_aflag_set(m, PGA_REFERENCED);
2760 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2761 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2763 if (TAILQ_EMPTY(&m->md.pv_list) &&
2764 (m->flags & PG_FICTITIOUS) == 0) {
2765 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2766 if (TAILQ_EMPTY(&pvh->pv_list)) {
2767 vm_page_aflag_clear(m,
2771 pc->pc_map[field] |= 1UL << bit;
2772 pmap_unuse_pt(pmap, va, *pde, &free);
2777 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2778 mtx_lock(&pv_chunks_mutex);
2781 /* Every freed mapping is for a 4 KB page. */
2782 pmap_resident_count_dec(pmap, freed);
2783 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2784 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2785 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2786 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2787 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2788 pc->pc_map[2] == PC_FREE2) {
2789 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2790 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2791 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2792 /* Entire chunk is free; return it. */
2793 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2794 dump_drop_page(m_pc->phys_addr);
2795 mtx_lock(&pv_chunks_mutex);
2798 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2799 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2800 mtx_lock(&pv_chunks_mutex);
2801 /* One freed pv entry in locked_pmap is sufficient. */
2802 if (pmap == locked_pmap)
2805 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2806 mtx_unlock(&pv_chunks_mutex);
2808 pmap_invalidate_all(pmap);
2809 if (pmap != locked_pmap)
2812 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2813 m_pc = SLIST_FIRST(&free);
2814 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2815 /* Recycle a freed page table page. */
2816 m_pc->wire_count = 1;
2817 atomic_add_int(&cnt.v_wire_count, 1);
2819 pmap_free_zero_pages(&free);
2824 * free the pv_entry back to the free list
2827 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2829 struct pv_chunk *pc;
2830 int idx, field, bit;
2832 rw_assert(&pvh_global_lock, RA_LOCKED);
2833 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2834 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2835 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2836 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2837 pc = pv_to_chunk(pv);
2838 idx = pv - &pc->pc_pventry[0];
2841 pc->pc_map[field] |= 1ul << bit;
2842 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2843 pc->pc_map[2] != PC_FREE2) {
2844 /* 98% of the time, pc is already at the head of the list. */
2845 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2846 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2847 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2851 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2856 free_pv_chunk(struct pv_chunk *pc)
2860 mtx_lock(&pv_chunks_mutex);
2861 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2862 mtx_unlock(&pv_chunks_mutex);
2863 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2864 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2865 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2866 /* entire chunk is free, return it */
2867 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2868 dump_drop_page(m->phys_addr);
2869 vm_page_unwire(m, 0);
2874 * Returns a new PV entry, allocating a new PV chunk from the system when
2875 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2876 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2879 * The given PV list lock may be released.
2882 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2886 struct pv_chunk *pc;
2889 rw_assert(&pvh_global_lock, RA_LOCKED);
2890 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2891 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2893 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2895 for (field = 0; field < _NPCM; field++) {
2896 if (pc->pc_map[field]) {
2897 bit = bsfq(pc->pc_map[field]);
2901 if (field < _NPCM) {
2902 pv = &pc->pc_pventry[field * 64 + bit];
2903 pc->pc_map[field] &= ~(1ul << bit);
2904 /* If this was the last item, move it to tail */
2905 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2906 pc->pc_map[2] == 0) {
2907 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2908 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2911 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2912 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2916 /* No free items, allocate another chunk */
2917 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2920 if (lockp == NULL) {
2921 PV_STAT(pc_chunk_tryfail++);
2924 m = reclaim_pv_chunk(pmap, lockp);
2928 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2929 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2930 dump_add_page(m->phys_addr);
2931 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2933 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2934 pc->pc_map[1] = PC_FREE1;
2935 pc->pc_map[2] = PC_FREE2;
2936 mtx_lock(&pv_chunks_mutex);
2937 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2938 mtx_unlock(&pv_chunks_mutex);
2939 pv = &pc->pc_pventry[0];
2940 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2941 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2942 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2947 * Returns the number of one bits within the given PV chunk map element.
2950 popcnt_pc_map_elem(uint64_t elem)
2955 * This simple method of counting the one bits performs well because
2956 * the given element typically contains more zero bits than one bits.
2959 for (; elem != 0; elem &= elem - 1)
2965 * Ensure that the number of spare PV entries in the specified pmap meets or
2966 * exceeds the given count, "needed".
2968 * The given PV list lock may be released.
2971 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2973 struct pch new_tail;
2974 struct pv_chunk *pc;
2978 rw_assert(&pvh_global_lock, RA_LOCKED);
2979 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2980 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2983 * Newly allocated PV chunks must be stored in a private list until
2984 * the required number of PV chunks have been allocated. Otherwise,
2985 * reclaim_pv_chunk() could recycle one of these chunks. In
2986 * contrast, these chunks must be added to the pmap upon allocation.
2988 TAILQ_INIT(&new_tail);
2991 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2992 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
2993 free = popcnt_pc_map_elem(pc->pc_map[0]);
2994 free += popcnt_pc_map_elem(pc->pc_map[1]);
2995 free += popcnt_pc_map_elem(pc->pc_map[2]);
2997 free = popcntq(pc->pc_map[0]);
2998 free += popcntq(pc->pc_map[1]);
2999 free += popcntq(pc->pc_map[2]);
3004 if (avail >= needed)
3007 for (; avail < needed; avail += _NPCPV) {
3008 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3011 m = reclaim_pv_chunk(pmap, lockp);
3015 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3016 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3017 dump_add_page(m->phys_addr);
3018 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3020 pc->pc_map[0] = PC_FREE0;
3021 pc->pc_map[1] = PC_FREE1;
3022 pc->pc_map[2] = PC_FREE2;
3023 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3024 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3025 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3027 if (!TAILQ_EMPTY(&new_tail)) {
3028 mtx_lock(&pv_chunks_mutex);
3029 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3030 mtx_unlock(&pv_chunks_mutex);
3035 * First find and then remove the pv entry for the specified pmap and virtual
3036 * address from the specified pv list. Returns the pv entry if found and NULL
3037 * otherwise. This operation can be performed on pv lists for either 4KB or
3038 * 2MB page mappings.
3040 static __inline pv_entry_t
3041 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3045 rw_assert(&pvh_global_lock, RA_LOCKED);
3046 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3047 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3048 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3057 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3058 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3059 * entries for each of the 4KB page mappings.
3062 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3063 struct rwlock **lockp)
3065 struct md_page *pvh;
3066 struct pv_chunk *pc;
3068 vm_offset_t va_last;
3072 rw_assert(&pvh_global_lock, RA_LOCKED);
3073 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3074 KASSERT((pa & PDRMASK) == 0,
3075 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3076 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3079 * Transfer the 2mpage's pv entry for this mapping to the first
3080 * page's pv list. Once this transfer begins, the pv list lock
3081 * must not be released until the last pv entry is reinstantiated.
3083 pvh = pa_to_pvh(pa);
3084 va = trunc_2mpage(va);
3085 pv = pmap_pvh_remove(pvh, pmap, va);
3086 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3087 m = PHYS_TO_VM_PAGE(pa);
3088 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3090 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3091 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3092 va_last = va + NBPDR - PAGE_SIZE;
3094 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3095 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3096 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3097 for (field = 0; field < _NPCM; field++) {
3098 while (pc->pc_map[field]) {
3099 bit = bsfq(pc->pc_map[field]);
3100 pc->pc_map[field] &= ~(1ul << bit);
3101 pv = &pc->pc_pventry[field * 64 + bit];
3105 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3106 ("pmap_pv_demote_pde: page %p is not managed", m));
3107 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3113 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3114 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3117 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3118 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3119 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3121 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3122 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3126 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3127 * replace the many pv entries for the 4KB page mappings by a single pv entry
3128 * for the 2MB page mapping.
3131 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3132 struct rwlock **lockp)
3134 struct md_page *pvh;
3136 vm_offset_t va_last;
3139 rw_assert(&pvh_global_lock, RA_LOCKED);
3140 KASSERT((pa & PDRMASK) == 0,
3141 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3142 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3145 * Transfer the first page's pv entry for this mapping to the 2mpage's
3146 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3147 * a transfer avoids the possibility that get_pv_entry() calls
3148 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3149 * mappings that is being promoted.
3151 m = PHYS_TO_VM_PAGE(pa);
3152 va = trunc_2mpage(va);
3153 pv = pmap_pvh_remove(&m->md, pmap, va);
3154 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3155 pvh = pa_to_pvh(pa);
3156 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3158 /* Free the remaining NPTEPG - 1 pv entries. */
3159 va_last = va + NBPDR - PAGE_SIZE;
3163 pmap_pvh_free(&m->md, pmap, va);
3164 } while (va < va_last);
3168 * First find and then destroy the pv entry for the specified pmap and virtual
3169 * address. This operation can be performed on pv lists for either 4KB or 2MB
3173 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3177 pv = pmap_pvh_remove(pvh, pmap, va);
3178 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3179 free_pv_entry(pmap, pv);
3183 * Conditionally create the PV entry for a 4KB page mapping if the required
3184 * memory can be allocated without resorting to reclamation.
3187 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3188 struct rwlock **lockp)
3192 rw_assert(&pvh_global_lock, RA_LOCKED);
3193 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3194 /* Pass NULL instead of the lock pointer to disable reclamation. */
3195 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3197 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3198 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3206 * Conditionally create the PV entry for a 2MB page mapping if the required
3207 * memory can be allocated without resorting to reclamation.
3210 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3211 struct rwlock **lockp)
3213 struct md_page *pvh;
3216 rw_assert(&pvh_global_lock, RA_LOCKED);
3217 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3218 /* Pass NULL instead of the lock pointer to disable reclamation. */
3219 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3221 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3222 pvh = pa_to_pvh(pa);
3223 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3231 * Fills a page table page with mappings to consecutive physical pages.
3234 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3238 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3240 newpte += PAGE_SIZE;
3245 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3246 * mapping is invalidated.
3249 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3251 struct rwlock *lock;
3255 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3262 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3263 struct rwlock **lockp)
3265 pd_entry_t newpde, oldpde;
3266 pt_entry_t *firstpte, newpte;
3267 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3270 struct spglist free;
3273 PG_G = pmap_global_bit(pmap);
3274 PG_A = pmap_accessed_bit(pmap);
3275 PG_M = pmap_modified_bit(pmap);
3276 PG_RW = pmap_rw_bit(pmap);
3277 PG_V = pmap_valid_bit(pmap);
3278 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3280 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3282 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3283 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3284 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3286 pmap_remove_pt_page(pmap, mpte);
3288 KASSERT((oldpde & PG_W) == 0,
3289 ("pmap_demote_pde: page table page for a wired mapping"
3293 * Invalidate the 2MB page mapping and return "failure" if the
3294 * mapping was never accessed or the allocation of the new
3295 * page table page fails. If the 2MB page mapping belongs to
3296 * the direct map region of the kernel's address space, then
3297 * the page allocation request specifies the highest possible
3298 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3299 * normal. Page table pages are preallocated for every other
3300 * part of the kernel address space, so the direct map region
3301 * is the only part of the kernel address space that must be
3304 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3305 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3306 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3307 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3309 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3311 pmap_invalidate_page(pmap, trunc_2mpage(va));
3312 pmap_free_zero_pages(&free);
3313 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3314 " in pmap %p", va, pmap);
3317 if (va < VM_MAXUSER_ADDRESS)
3318 pmap_resident_count_inc(pmap, 1);
3320 mptepa = VM_PAGE_TO_PHYS(mpte);
3321 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3322 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3323 KASSERT((oldpde & PG_A) != 0,
3324 ("pmap_demote_pde: oldpde is missing PG_A"));
3325 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3326 ("pmap_demote_pde: oldpde is missing PG_M"));
3327 newpte = oldpde & ~PG_PS;
3328 newpte = pmap_swap_pat(pmap, newpte);
3331 * If the page table page is new, initialize it.
3333 if (mpte->wire_count == 1) {
3334 mpte->wire_count = NPTEPG;
3335 pmap_fill_ptp(firstpte, newpte);
3337 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3338 ("pmap_demote_pde: firstpte and newpte map different physical"
3342 * If the mapping has changed attributes, update the page table
3345 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3346 pmap_fill_ptp(firstpte, newpte);
3349 * The spare PV entries must be reserved prior to demoting the
3350 * mapping, that is, prior to changing the PDE. Otherwise, the state
3351 * of the PDE and the PV lists will be inconsistent, which can result
3352 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3353 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3354 * PV entry for the 2MB page mapping that is being demoted.
3356 if ((oldpde & PG_MANAGED) != 0)
3357 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3360 * Demote the mapping. This pmap is locked. The old PDE has
3361 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3362 * set. Thus, there is no danger of a race with another
3363 * processor changing the setting of PG_A and/or PG_M between
3364 * the read above and the store below.
3366 if (workaround_erratum383)
3367 pmap_update_pde(pmap, va, pde, newpde);
3369 pde_store(pde, newpde);
3372 * Invalidate a stale recursive mapping of the page table page.
3374 if (va >= VM_MAXUSER_ADDRESS)
3375 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3378 * Demote the PV entry.
3380 if ((oldpde & PG_MANAGED) != 0)
3381 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3383 atomic_add_long(&pmap_pde_demotions, 1);
3384 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3385 " in pmap %p", va, pmap);
3390 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3393 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3399 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3400 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3401 mpte = pmap_lookup_pt_page(pmap, va);
3403 panic("pmap_remove_kernel_pde: Missing pt page.");
3405 pmap_remove_pt_page(pmap, mpte);
3406 mptepa = VM_PAGE_TO_PHYS(mpte);
3407 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3410 * Initialize the page table page.
3412 pagezero((void *)PHYS_TO_DMAP(mptepa));
3415 * Demote the mapping.
3417 if (workaround_erratum383)
3418 pmap_update_pde(pmap, va, pde, newpde);
3420 pde_store(pde, newpde);
3423 * Invalidate a stale recursive mapping of the page table page.
3425 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3429 * pmap_remove_pde: do the things to unmap a superpage in a process
3432 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3433 struct spglist *free, struct rwlock **lockp)
3435 struct md_page *pvh;
3437 vm_offset_t eva, va;
3439 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3441 PG_G = pmap_global_bit(pmap);
3442 PG_A = pmap_accessed_bit(pmap);
3443 PG_M = pmap_modified_bit(pmap);
3444 PG_RW = pmap_rw_bit(pmap);
3446 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3447 KASSERT((sva & PDRMASK) == 0,
3448 ("pmap_remove_pde: sva is not 2mpage aligned"));
3449 oldpde = pte_load_clear(pdq);
3451 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3454 * Machines that don't support invlpg, also don't support
3458 pmap_invalidate_page(kernel_pmap, sva);
3459 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3460 if (oldpde & PG_MANAGED) {
3461 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3462 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3463 pmap_pvh_free(pvh, pmap, sva);
3465 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3466 va < eva; va += PAGE_SIZE, m++) {
3467 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3470 vm_page_aflag_set(m, PGA_REFERENCED);
3471 if (TAILQ_EMPTY(&m->md.pv_list) &&
3472 TAILQ_EMPTY(&pvh->pv_list))
3473 vm_page_aflag_clear(m, PGA_WRITEABLE);
3476 if (pmap == kernel_pmap) {
3477 pmap_remove_kernel_pde(pmap, pdq, sva);
3479 mpte = pmap_lookup_pt_page(pmap, sva);
3481 pmap_remove_pt_page(pmap, mpte);
3482 pmap_resident_count_dec(pmap, 1);
3483 KASSERT(mpte->wire_count == NPTEPG,
3484 ("pmap_remove_pde: pte page wire count error"));
3485 mpte->wire_count = 0;
3486 pmap_add_delayed_free_list(mpte, free, FALSE);
3487 atomic_subtract_int(&cnt.v_wire_count, 1);
3490 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3494 * pmap_remove_pte: do the things to unmap a page in a process
3497 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3498 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3500 struct md_page *pvh;
3501 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3504 PG_A = pmap_accessed_bit(pmap);
3505 PG_M = pmap_modified_bit(pmap);
3506 PG_RW = pmap_rw_bit(pmap);
3508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3509 oldpte = pte_load_clear(ptq);
3511 pmap->pm_stats.wired_count -= 1;
3512 pmap_resident_count_dec(pmap, 1);
3513 if (oldpte & PG_MANAGED) {
3514 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3515 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3518 vm_page_aflag_set(m, PGA_REFERENCED);
3519 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3520 pmap_pvh_free(&m->md, pmap, va);
3521 if (TAILQ_EMPTY(&m->md.pv_list) &&
3522 (m->flags & PG_FICTITIOUS) == 0) {
3523 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3524 if (TAILQ_EMPTY(&pvh->pv_list))
3525 vm_page_aflag_clear(m, PGA_WRITEABLE);
3528 return (pmap_unuse_pt(pmap, va, ptepde, free));
3532 * Remove a single page from a process address space
3535 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3536 struct spglist *free)
3538 struct rwlock *lock;
3539 pt_entry_t *pte, PG_V;
3541 PG_V = pmap_valid_bit(pmap);
3542 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3543 if ((*pde & PG_V) == 0)
3545 pte = pmap_pde_to_pte(pde, va);
3546 if ((*pte & PG_V) == 0)
3549 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3552 pmap_invalidate_page(pmap, va);
3556 * Remove the given range of addresses from the specified map.
3558 * It is assumed that the start and end are properly
3559 * rounded to the page size.
3562 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3564 struct rwlock *lock;
3565 vm_offset_t va, va_next;
3566 pml4_entry_t *pml4e;
3568 pd_entry_t ptpaddr, *pde;
3569 pt_entry_t *pte, PG_G, PG_V;
3570 struct spglist free;
3573 PG_G = pmap_global_bit(pmap);
3574 PG_V = pmap_valid_bit(pmap);
3577 * Perform an unsynchronized read. This is, however, safe.
3579 if (pmap->pm_stats.resident_count == 0)
3585 rw_rlock(&pvh_global_lock);
3589 * special handling of removing one page. a very
3590 * common operation and easy to short circuit some
3593 if (sva + PAGE_SIZE == eva) {
3594 pde = pmap_pde(pmap, sva);
3595 if (pde && (*pde & PG_PS) == 0) {
3596 pmap_remove_page(pmap, sva, pde, &free);
3602 for (; sva < eva; sva = va_next) {
3604 if (pmap->pm_stats.resident_count == 0)
3607 pml4e = pmap_pml4e(pmap, sva);
3608 if ((*pml4e & PG_V) == 0) {
3609 va_next = (sva + NBPML4) & ~PML4MASK;
3615 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3616 if ((*pdpe & PG_V) == 0) {
3617 va_next = (sva + NBPDP) & ~PDPMASK;
3624 * Calculate index for next page table.
3626 va_next = (sva + NBPDR) & ~PDRMASK;
3630 pde = pmap_pdpe_to_pde(pdpe, sva);
3634 * Weed out invalid mappings.
3640 * Check for large page.
3642 if ((ptpaddr & PG_PS) != 0) {
3644 * Are we removing the entire large page? If not,
3645 * demote the mapping and fall through.
3647 if (sva + NBPDR == va_next && eva >= va_next) {
3649 * The TLB entry for a PG_G mapping is
3650 * invalidated by pmap_remove_pde().
3652 if ((ptpaddr & PG_G) == 0)
3654 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3656 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3658 /* The large page mapping was destroyed. */
3665 * Limit our scan to either the end of the va represented
3666 * by the current page table page, or to the end of the
3667 * range being removed.
3673 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3676 if (va != va_next) {
3677 pmap_invalidate_range(pmap, va, sva);
3682 if ((*pte & PG_G) == 0)
3684 else if (va == va_next)
3686 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3693 pmap_invalidate_range(pmap, va, sva);
3699 pmap_invalidate_all(pmap);
3700 rw_runlock(&pvh_global_lock);
3702 pmap_free_zero_pages(&free);
3706 * Routine: pmap_remove_all
3708 * Removes this physical page from
3709 * all physical maps in which it resides.
3710 * Reflects back modify bits to the pager.
3713 * Original versions of this routine were very
3714 * inefficient because they iteratively called
3715 * pmap_remove (slow...)
3719 pmap_remove_all(vm_page_t m)
3721 struct md_page *pvh;
3724 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3727 struct spglist free;
3729 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3730 ("pmap_remove_all: page %p is not managed", m));
3732 rw_wlock(&pvh_global_lock);
3733 if ((m->flags & PG_FICTITIOUS) != 0)
3734 goto small_mappings;
3735 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3736 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3740 pde = pmap_pde(pmap, va);
3741 (void)pmap_demote_pde(pmap, pde, va);
3745 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3748 PG_A = pmap_accessed_bit(pmap);
3749 PG_M = pmap_modified_bit(pmap);
3750 PG_RW = pmap_rw_bit(pmap);
3751 pmap_resident_count_dec(pmap, 1);
3752 pde = pmap_pde(pmap, pv->pv_va);
3753 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3754 " a 2mpage in page %p's pv list", m));
3755 pte = pmap_pde_to_pte(pde, pv->pv_va);
3756 tpte = pte_load_clear(pte);
3758 pmap->pm_stats.wired_count--;
3760 vm_page_aflag_set(m, PGA_REFERENCED);
3763 * Update the vm_page_t clean and reference bits.
3765 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3767 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3768 pmap_invalidate_page(pmap, pv->pv_va);
3769 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3771 free_pv_entry(pmap, pv);
3774 vm_page_aflag_clear(m, PGA_WRITEABLE);
3775 rw_wunlock(&pvh_global_lock);
3776 pmap_free_zero_pages(&free);
3780 * pmap_protect_pde: do the things to protect a 2mpage in a process
3783 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3785 pd_entry_t newpde, oldpde;
3786 vm_offset_t eva, va;
3788 boolean_t anychanged;
3789 pt_entry_t PG_G, PG_M, PG_RW;
3791 PG_G = pmap_global_bit(pmap);
3792 PG_M = pmap_modified_bit(pmap);
3793 PG_RW = pmap_rw_bit(pmap);
3795 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3796 KASSERT((sva & PDRMASK) == 0,
3797 ("pmap_protect_pde: sva is not 2mpage aligned"));
3800 oldpde = newpde = *pde;
3801 if (oldpde & PG_MANAGED) {
3803 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3804 va < eva; va += PAGE_SIZE, m++)
3805 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3808 if ((prot & VM_PROT_WRITE) == 0)
3809 newpde &= ~(PG_RW | PG_M);
3810 if ((prot & VM_PROT_EXECUTE) == 0)
3812 if (newpde != oldpde) {
3813 if (!atomic_cmpset_long(pde, oldpde, newpde))
3816 pmap_invalidate_page(pmap, sva);
3820 return (anychanged);
3824 * Set the physical protection on the
3825 * specified range of this map as requested.
3828 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3830 vm_offset_t va_next;
3831 pml4_entry_t *pml4e;
3833 pd_entry_t ptpaddr, *pde;
3834 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3835 boolean_t anychanged, pv_lists_locked;
3837 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3838 pmap_remove(pmap, sva, eva);
3842 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3843 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3846 PG_G = pmap_global_bit(pmap);
3847 PG_M = pmap_modified_bit(pmap);
3848 PG_V = pmap_valid_bit(pmap);
3849 PG_RW = pmap_rw_bit(pmap);
3850 pv_lists_locked = FALSE;
3855 for (; sva < eva; sva = va_next) {
3857 pml4e = pmap_pml4e(pmap, sva);
3858 if ((*pml4e & PG_V) == 0) {
3859 va_next = (sva + NBPML4) & ~PML4MASK;
3865 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3866 if ((*pdpe & PG_V) == 0) {
3867 va_next = (sva + NBPDP) & ~PDPMASK;
3873 va_next = (sva + NBPDR) & ~PDRMASK;
3877 pde = pmap_pdpe_to_pde(pdpe, sva);
3881 * Weed out invalid mappings.
3887 * Check for large page.
3889 if ((ptpaddr & PG_PS) != 0) {
3891 * Are we protecting the entire large page? If not,
3892 * demote the mapping and fall through.
3894 if (sva + NBPDR == va_next && eva >= va_next) {
3896 * The TLB entry for a PG_G mapping is
3897 * invalidated by pmap_protect_pde().
3899 if (pmap_protect_pde(pmap, pde, sva, prot))
3903 if (!pv_lists_locked) {
3904 pv_lists_locked = TRUE;
3905 if (!rw_try_rlock(&pvh_global_lock)) {
3907 pmap_invalidate_all(
3910 rw_rlock(&pvh_global_lock);
3914 if (!pmap_demote_pde(pmap, pde, sva)) {
3916 * The large page mapping was
3927 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3929 pt_entry_t obits, pbits;
3933 obits = pbits = *pte;
3934 if ((pbits & PG_V) == 0)
3937 if ((prot & VM_PROT_WRITE) == 0) {
3938 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3939 (PG_MANAGED | PG_M | PG_RW)) {
3940 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3943 pbits &= ~(PG_RW | PG_M);
3945 if ((prot & VM_PROT_EXECUTE) == 0)
3948 if (pbits != obits) {
3949 if (!atomic_cmpset_long(pte, obits, pbits))
3952 pmap_invalidate_page(pmap, sva);
3959 pmap_invalidate_all(pmap);
3960 if (pv_lists_locked)
3961 rw_runlock(&pvh_global_lock);
3966 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3967 * single page table page (PTP) to a single 2MB page mapping. For promotion
3968 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3969 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3970 * identical characteristics.
3973 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3974 struct rwlock **lockp)
3977 pt_entry_t *firstpte, oldpte, pa, *pte;
3978 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
3979 vm_offset_t oldpteva;
3983 PG_A = pmap_accessed_bit(pmap);
3984 PG_G = pmap_global_bit(pmap);
3985 PG_M = pmap_modified_bit(pmap);
3986 PG_V = pmap_valid_bit(pmap);
3987 PG_RW = pmap_rw_bit(pmap);
3988 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3990 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3993 * Examine the first PTE in the specified PTP. Abort if this PTE is
3994 * either invalid, unused, or does not map the first 4KB physical page
3995 * within a 2MB page.
3997 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4000 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4001 atomic_add_long(&pmap_pde_p_failures, 1);
4002 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4003 " in pmap %p", va, pmap);
4006 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4008 * When PG_M is already clear, PG_RW can be cleared without
4009 * a TLB invalidation.
4011 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4017 * Examine each of the other PTEs in the specified PTP. Abort if this
4018 * PTE maps an unexpected 4KB physical page or does not have identical
4019 * characteristics to the first PTE.
4021 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4022 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4025 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4026 atomic_add_long(&pmap_pde_p_failures, 1);
4027 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4028 " in pmap %p", va, pmap);
4031 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4033 * When PG_M is already clear, PG_RW can be cleared
4034 * without a TLB invalidation.
4036 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4039 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
4041 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4042 " in pmap %p", oldpteva, pmap);
4044 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4045 atomic_add_long(&pmap_pde_p_failures, 1);
4046 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4047 " in pmap %p", va, pmap);
4054 * Save the page table page in its current state until the PDE
4055 * mapping the superpage is demoted by pmap_demote_pde() or
4056 * destroyed by pmap_remove_pde().
4058 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4059 KASSERT(mpte >= vm_page_array &&
4060 mpte < &vm_page_array[vm_page_array_size],
4061 ("pmap_promote_pde: page table page is out of range"));
4062 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4063 ("pmap_promote_pde: page table page's pindex is wrong"));
4064 if (pmap_insert_pt_page(pmap, mpte)) {
4065 atomic_add_long(&pmap_pde_p_failures, 1);
4067 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4073 * Promote the pv entries.
4075 if ((newpde & PG_MANAGED) != 0)
4076 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4079 * Propagate the PAT index to its proper position.
4081 newpde = pmap_swap_pat(pmap, newpde);
4084 * Map the superpage.
4086 if (workaround_erratum383)
4087 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4089 pde_store(pde, PG_PS | newpde);
4091 atomic_add_long(&pmap_pde_promotions, 1);
4092 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4093 " in pmap %p", va, pmap);
4097 * Insert the given physical page (p) at
4098 * the specified virtual address (v) in the
4099 * target physical map with the protection requested.
4101 * If specified, the page will be wired down, meaning
4102 * that the related pte can not be reclaimed.
4104 * NB: This is the only routine which MAY NOT lazy-evaluate
4105 * or lose information. That is, this routine must actually
4106 * insert this page into the given map NOW.
4109 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
4110 vm_prot_t prot, boolean_t wired)
4112 struct rwlock *lock;
4114 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4115 pt_entry_t newpte, origpte;
4120 PG_A = pmap_accessed_bit(pmap);
4121 PG_G = pmap_global_bit(pmap);
4122 PG_M = pmap_modified_bit(pmap);
4123 PG_V = pmap_valid_bit(pmap);
4124 PG_RW = pmap_rw_bit(pmap);
4126 va = trunc_page(va);
4127 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4128 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4129 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4131 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4132 va >= kmi.clean_eva,
4133 ("pmap_enter: managed mapping within the clean submap"));
4134 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4135 VM_OBJECT_ASSERT_WLOCKED(m->object);
4136 pa = VM_PAGE_TO_PHYS(m);
4137 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4138 if ((access & VM_PROT_WRITE) != 0)
4140 if ((prot & VM_PROT_WRITE) != 0)
4142 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4143 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't"));
4144 if ((prot & VM_PROT_EXECUTE) == 0)
4148 if (va < VM_MAXUSER_ADDRESS)
4150 if (pmap == kernel_pmap)
4152 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4155 * Set modified bit gratuitously for writeable mappings if
4156 * the page is unmanaged. We do not want to take a fault
4157 * to do the dirty bit accounting for these mappings.
4159 if ((m->oflags & VPO_UNMANAGED) != 0) {
4160 if ((newpte & PG_RW) != 0)
4167 rw_rlock(&pvh_global_lock);
4171 * In the case that a page table page is not
4172 * resident, we are creating it here.
4175 pde = pmap_pde(pmap, va);
4176 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4177 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4178 pte = pmap_pde_to_pte(pde, va);
4179 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4180 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4183 } else if (va < VM_MAXUSER_ADDRESS) {
4185 * Here if the pte page isn't mapped, or if it has been
4188 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock);
4191 panic("pmap_enter: invalid page directory va=%#lx", va);
4196 * Is the specified virtual address already mapped?
4198 if ((origpte & PG_V) != 0) {
4200 * Wiring change, just update stats. We don't worry about
4201 * wiring PT pages as they remain resident as long as there
4202 * are valid mappings in them. Hence, if a user page is wired,
4203 * the PT page will be also.
4205 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4206 pmap->pm_stats.wired_count++;
4207 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4208 pmap->pm_stats.wired_count--;
4211 * Remove the extra PT page reference.
4215 KASSERT(mpte->wire_count > 0,
4216 ("pmap_enter: missing reference to page table page,"
4221 * Has the physical page changed?
4223 opa = origpte & PG_FRAME;
4226 * No, might be a protection or wiring change.
4228 if ((origpte & PG_MANAGED) != 0) {
4229 newpte |= PG_MANAGED;
4230 if ((newpte & PG_RW) != 0)
4231 vm_page_aflag_set(m, PGA_WRITEABLE);
4233 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4239 * Increment the counters.
4241 if ((newpte & PG_W) != 0)
4242 pmap->pm_stats.wired_count++;
4243 pmap_resident_count_inc(pmap, 1);
4247 * Enter on the PV list if part of our managed memory.
4249 if ((m->oflags & VPO_UNMANAGED) == 0) {
4250 newpte |= PG_MANAGED;
4251 pv = get_pv_entry(pmap, &lock);
4253 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4254 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4256 if ((newpte & PG_RW) != 0)
4257 vm_page_aflag_set(m, PGA_WRITEABLE);
4263 if ((origpte & PG_V) != 0) {
4265 origpte = pte_load_store(pte, newpte);
4266 opa = origpte & PG_FRAME;
4268 if ((origpte & PG_MANAGED) != 0) {
4269 om = PHYS_TO_VM_PAGE(opa);
4270 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4273 if ((origpte & PG_A) != 0)
4274 vm_page_aflag_set(om, PGA_REFERENCED);
4275 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4276 pmap_pvh_free(&om->md, pmap, va);
4277 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4278 TAILQ_EMPTY(&om->md.pv_list) &&
4279 ((om->flags & PG_FICTITIOUS) != 0 ||
4280 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4281 vm_page_aflag_clear(om, PGA_WRITEABLE);
4283 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4284 PG_RW)) == (PG_M | PG_RW)) {
4285 if ((origpte & PG_MANAGED) != 0)
4289 * Although the PTE may still have PG_RW set, TLB
4290 * invalidation may nonetheless be required because
4291 * the PTE no longer has PG_M set.
4293 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4295 * This PTE change does not require TLB invalidation.
4299 if ((origpte & PG_A) != 0)
4300 pmap_invalidate_page(pmap, va);
4302 pte_store(pte, newpte);
4307 * If both the page table page and the reservation are fully
4308 * populated, then attempt promotion.
4310 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4311 pmap_ps_enabled(pmap) &&
4312 (m->flags & PG_FICTITIOUS) == 0 &&
4313 vm_reserv_level_iffullpop(m) == 0)
4314 pmap_promote_pde(pmap, pde, va, &lock);
4318 rw_runlock(&pvh_global_lock);
4323 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4324 * otherwise. Fails if (1) a page table page cannot be allocated without
4325 * blocking, (2) a mapping already exists at the specified virtual address, or
4326 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4329 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4330 struct rwlock **lockp)
4332 pd_entry_t *pde, newpde;
4335 struct spglist free;
4337 PG_V = pmap_valid_bit(pmap);
4338 rw_assert(&pvh_global_lock, RA_LOCKED);
4339 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4341 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4342 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4343 " in pmap %p", va, pmap);
4346 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4347 pde = &pde[pmap_pde_index(va)];
4348 if ((*pde & PG_V) != 0) {
4349 KASSERT(mpde->wire_count > 1,
4350 ("pmap_enter_pde: mpde's wire count is too low"));
4352 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4353 " in pmap %p", va, pmap);
4356 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4358 if ((m->oflags & VPO_UNMANAGED) == 0) {
4359 newpde |= PG_MANAGED;
4362 * Abort this mapping if its PV entry could not be created.
4364 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4367 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4368 pmap_invalidate_page(pmap, va);
4369 pmap_free_zero_pages(&free);
4371 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4372 " in pmap %p", va, pmap);
4376 if ((prot & VM_PROT_EXECUTE) == 0)
4378 if (va < VM_MAXUSER_ADDRESS)
4382 * Increment counters.
4384 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4387 * Map the superpage.
4389 pde_store(pde, newpde);
4391 atomic_add_long(&pmap_pde_mappings, 1);
4392 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4393 " in pmap %p", va, pmap);
4398 * Maps a sequence of resident pages belonging to the same object.
4399 * The sequence begins with the given page m_start. This page is
4400 * mapped at the given virtual address start. Each subsequent page is
4401 * mapped at a virtual address that is offset from start by the same
4402 * amount as the page is offset from m_start within the object. The
4403 * last page in the sequence is the page with the largest offset from
4404 * m_start that can be mapped at a virtual address less than the given
4405 * virtual address end. Not every virtual page between start and end
4406 * is mapped; only those for which a resident page exists with the
4407 * corresponding offset from m_start are mapped.
4410 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4411 vm_page_t m_start, vm_prot_t prot)
4413 struct rwlock *lock;
4416 vm_pindex_t diff, psize;
4418 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4420 psize = atop(end - start);
4424 rw_rlock(&pvh_global_lock);
4426 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4427 va = start + ptoa(diff);
4428 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4429 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
4430 pmap_ps_enabled(pmap) &&
4431 vm_reserv_level_iffullpop(m) == 0 &&
4432 pmap_enter_pde(pmap, va, m, prot, &lock))
4433 m = &m[NBPDR / PAGE_SIZE - 1];
4435 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4437 m = TAILQ_NEXT(m, listq);
4441 rw_runlock(&pvh_global_lock);
4446 * this code makes some *MAJOR* assumptions:
4447 * 1. Current pmap & pmap exists.
4450 * 4. No page table pages.
4451 * but is *MUCH* faster than pmap_enter...
4455 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4457 struct rwlock *lock;
4460 rw_rlock(&pvh_global_lock);
4462 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4465 rw_runlock(&pvh_global_lock);
4470 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4471 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4473 struct spglist free;
4474 pt_entry_t *pte, PG_V;
4477 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4478 (m->oflags & VPO_UNMANAGED) != 0,
4479 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4480 PG_V = pmap_valid_bit(pmap);
4481 rw_assert(&pvh_global_lock, RA_LOCKED);
4482 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4485 * In the case that a page table page is not
4486 * resident, we are creating it here.
4488 if (va < VM_MAXUSER_ADDRESS) {
4489 vm_pindex_t ptepindex;
4493 * Calculate pagetable page index
4495 ptepindex = pmap_pde_pindex(va);
4496 if (mpte && (mpte->pindex == ptepindex)) {
4500 * Get the page directory entry
4502 ptepa = pmap_pde(pmap, va);
4505 * If the page table page is mapped, we just increment
4506 * the hold count, and activate it. Otherwise, we
4507 * attempt to allocate a page table page. If this
4508 * attempt fails, we don't retry. Instead, we give up.
4510 if (ptepa && (*ptepa & PG_V) != 0) {
4513 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4517 * Pass NULL instead of the PV list lock
4518 * pointer, because we don't intend to sleep.
4520 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4525 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4526 pte = &pte[pmap_pte_index(va)];
4540 * Enter on the PV list if part of our managed memory.
4542 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4543 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4546 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4547 pmap_invalidate_page(pmap, va);
4548 pmap_free_zero_pages(&free);
4556 * Increment counters
4558 pmap_resident_count_inc(pmap, 1);
4560 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4561 if ((prot & VM_PROT_EXECUTE) == 0)
4565 * Now validate mapping with RO protection
4567 if ((m->oflags & VPO_UNMANAGED) != 0)
4568 pte_store(pte, pa | PG_V | PG_U);
4570 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4575 * Make a temporary mapping for a physical address. This is only intended
4576 * to be used for panic dumps.
4579 pmap_kenter_temporary(vm_paddr_t pa, int i)
4583 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4584 pmap_kenter(va, pa);
4586 return ((void *)crashdumpmap);
4590 * This code maps large physical mmap regions into the
4591 * processor address space. Note that some shortcuts
4592 * are taken, but the code works.
4595 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4596 vm_pindex_t pindex, vm_size_t size)
4599 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4600 vm_paddr_t pa, ptepa;
4604 PG_A = pmap_accessed_bit(pmap);
4605 PG_M = pmap_modified_bit(pmap);
4606 PG_V = pmap_valid_bit(pmap);
4607 PG_RW = pmap_rw_bit(pmap);
4609 VM_OBJECT_ASSERT_WLOCKED(object);
4610 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4611 ("pmap_object_init_pt: non-device object"));
4612 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4613 if (!pmap_ps_enabled(pmap))
4615 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4617 p = vm_page_lookup(object, pindex);
4618 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4619 ("pmap_object_init_pt: invalid page %p", p));
4620 pat_mode = p->md.pat_mode;
4623 * Abort the mapping if the first page is not physically
4624 * aligned to a 2MB page boundary.
4626 ptepa = VM_PAGE_TO_PHYS(p);
4627 if (ptepa & (NBPDR - 1))
4631 * Skip the first page. Abort the mapping if the rest of
4632 * the pages are not physically contiguous or have differing
4633 * memory attributes.
4635 p = TAILQ_NEXT(p, listq);
4636 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4638 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4639 ("pmap_object_init_pt: invalid page %p", p));
4640 if (pa != VM_PAGE_TO_PHYS(p) ||
4641 pat_mode != p->md.pat_mode)
4643 p = TAILQ_NEXT(p, listq);
4647 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4648 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4649 * will not affect the termination of this loop.
4652 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4653 pa < ptepa + size; pa += NBPDR) {
4654 pdpg = pmap_allocpde(pmap, addr, NULL);
4657 * The creation of mappings below is only an
4658 * optimization. If a page directory page
4659 * cannot be allocated without blocking,
4660 * continue on to the next mapping rather than
4666 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4667 pde = &pde[pmap_pde_index(addr)];
4668 if ((*pde & PG_V) == 0) {
4669 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4670 PG_U | PG_RW | PG_V);
4671 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4672 atomic_add_long(&pmap_pde_mappings, 1);
4674 /* Continue on if the PDE is already valid. */
4676 KASSERT(pdpg->wire_count > 0,
4677 ("pmap_object_init_pt: missing reference "
4678 "to page directory page, va: 0x%lx", addr));
4687 * Routine: pmap_change_wiring
4688 * Function: Change the wiring attribute for a map/virtual-address
4690 * In/out conditions:
4691 * The mapping must already exist in the pmap.
4694 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
4698 boolean_t pv_lists_locked;
4700 pv_lists_locked = FALSE;
4703 * Wiring is not a hardware characteristic so there is no need to
4708 pde = pmap_pde(pmap, va);
4709 if ((*pde & PG_PS) != 0) {
4710 if (!wired != ((*pde & PG_W) == 0)) {
4711 if (!pv_lists_locked) {
4712 pv_lists_locked = TRUE;
4713 if (!rw_try_rlock(&pvh_global_lock)) {
4715 rw_rlock(&pvh_global_lock);
4719 if (!pmap_demote_pde(pmap, pde, va))
4720 panic("pmap_change_wiring: demotion failed");
4724 pte = pmap_pde_to_pte(pde, va);
4725 if (wired && (*pte & PG_W) == 0) {
4726 pmap->pm_stats.wired_count++;
4727 atomic_set_long(pte, PG_W);
4728 } else if (!wired && (*pte & PG_W) != 0) {
4729 pmap->pm_stats.wired_count--;
4730 atomic_clear_long(pte, PG_W);
4733 if (pv_lists_locked)
4734 rw_runlock(&pvh_global_lock);
4739 * Copy the range specified by src_addr/len
4740 * from the source map to the range dst_addr/len
4741 * in the destination map.
4743 * This routine is only advisory and need not do anything.
4747 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4748 vm_offset_t src_addr)
4750 struct rwlock *lock;
4751 struct spglist free;
4753 vm_offset_t end_addr = src_addr + len;
4754 vm_offset_t va_next;
4755 pt_entry_t PG_A, PG_M, PG_V;
4757 if (dst_addr != src_addr)
4760 if (dst_pmap->pm_type != src_pmap->pm_type)
4764 * EPT page table entries that require emulation of A/D bits are
4765 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4766 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4767 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4768 * implementations flag an EPT misconfiguration for exec-only
4769 * mappings we skip this function entirely for emulated pmaps.
4771 if (pmap_emulate_ad_bits(dst_pmap))
4775 rw_rlock(&pvh_global_lock);
4776 if (dst_pmap < src_pmap) {
4777 PMAP_LOCK(dst_pmap);
4778 PMAP_LOCK(src_pmap);
4780 PMAP_LOCK(src_pmap);
4781 PMAP_LOCK(dst_pmap);
4784 PG_A = pmap_accessed_bit(dst_pmap);
4785 PG_M = pmap_modified_bit(dst_pmap);
4786 PG_V = pmap_valid_bit(dst_pmap);
4788 for (addr = src_addr; addr < end_addr; addr = va_next) {
4789 pt_entry_t *src_pte, *dst_pte;
4790 vm_page_t dstmpde, dstmpte, srcmpte;
4791 pml4_entry_t *pml4e;
4793 pd_entry_t srcptepaddr, *pde;
4795 KASSERT(addr < UPT_MIN_ADDRESS,
4796 ("pmap_copy: invalid to pmap_copy page tables"));
4798 pml4e = pmap_pml4e(src_pmap, addr);
4799 if ((*pml4e & PG_V) == 0) {
4800 va_next = (addr + NBPML4) & ~PML4MASK;
4806 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4807 if ((*pdpe & PG_V) == 0) {
4808 va_next = (addr + NBPDP) & ~PDPMASK;
4814 va_next = (addr + NBPDR) & ~PDRMASK;
4818 pde = pmap_pdpe_to_pde(pdpe, addr);
4820 if (srcptepaddr == 0)
4823 if (srcptepaddr & PG_PS) {
4824 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4826 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4827 if (dstmpde == NULL)
4829 pde = (pd_entry_t *)
4830 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4831 pde = &pde[pmap_pde_index(addr)];
4832 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4833 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4834 PG_PS_FRAME, &lock))) {
4835 *pde = srcptepaddr & ~PG_W;
4836 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4838 dstmpde->wire_count--;
4842 srcptepaddr &= PG_FRAME;
4843 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4844 KASSERT(srcmpte->wire_count > 0,
4845 ("pmap_copy: source page table page is unused"));
4847 if (va_next > end_addr)
4850 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4851 src_pte = &src_pte[pmap_pte_index(addr)];
4853 while (addr < va_next) {
4857 * we only virtual copy managed pages
4859 if ((ptetemp & PG_MANAGED) != 0) {
4860 if (dstmpte != NULL &&
4861 dstmpte->pindex == pmap_pde_pindex(addr))
4862 dstmpte->wire_count++;
4863 else if ((dstmpte = pmap_allocpte(dst_pmap,
4864 addr, NULL)) == NULL)
4866 dst_pte = (pt_entry_t *)
4867 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4868 dst_pte = &dst_pte[pmap_pte_index(addr)];
4869 if (*dst_pte == 0 &&
4870 pmap_try_insert_pv_entry(dst_pmap, addr,
4871 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4874 * Clear the wired, modified, and
4875 * accessed (referenced) bits
4878 *dst_pte = ptetemp & ~(PG_W | PG_M |
4880 pmap_resident_count_inc(dst_pmap, 1);
4883 if (pmap_unwire_ptp(dst_pmap, addr,
4885 pmap_invalidate_page(dst_pmap,
4887 pmap_free_zero_pages(&free);
4891 if (dstmpte->wire_count >= srcmpte->wire_count)
4901 rw_runlock(&pvh_global_lock);
4902 PMAP_UNLOCK(src_pmap);
4903 PMAP_UNLOCK(dst_pmap);
4907 * pmap_zero_page zeros the specified hardware page by mapping
4908 * the page into KVM and using bzero to clear its contents.
4911 pmap_zero_page(vm_page_t m)
4913 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4915 pagezero((void *)va);
4919 * pmap_zero_page_area zeros the specified hardware page by mapping
4920 * the page into KVM and using bzero to clear its contents.
4922 * off and size may not cover an area beyond a single hardware page.
4925 pmap_zero_page_area(vm_page_t m, int off, int size)
4927 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4929 if (off == 0 && size == PAGE_SIZE)
4930 pagezero((void *)va);
4932 bzero((char *)va + off, size);
4936 * pmap_zero_page_idle zeros the specified hardware page by mapping
4937 * the page into KVM and using bzero to clear its contents. This
4938 * is intended to be called from the vm_pagezero process only and
4942 pmap_zero_page_idle(vm_page_t m)
4944 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4946 pagezero((void *)va);
4950 * pmap_copy_page copies the specified (machine independent)
4951 * page by mapping the page into virtual memory and using
4952 * bcopy to copy the page, one machine dependent page at a
4956 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4958 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4959 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4961 pagecopy((void *)src, (void *)dst);
4964 int unmapped_buf_allowed = 1;
4967 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4968 vm_offset_t b_offset, int xfersize)
4971 vm_offset_t a_pg_offset, b_pg_offset;
4974 while (xfersize > 0) {
4975 a_pg_offset = a_offset & PAGE_MASK;
4976 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4977 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]->
4978 phys_addr) + a_pg_offset;
4979 b_pg_offset = b_offset & PAGE_MASK;
4980 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4981 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]->
4982 phys_addr) + b_pg_offset;
4983 bcopy(a_cp, b_cp, cnt);
4991 * Returns true if the pmap's pv is one of the first
4992 * 16 pvs linked to from this page. This count may
4993 * be changed upwards or downwards in the future; it
4994 * is only necessary that true be returned for a small
4995 * subset of pmaps for proper page aging.
4998 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5000 struct md_page *pvh;
5001 struct rwlock *lock;
5006 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5007 ("pmap_page_exists_quick: page %p is not managed", m));
5009 rw_rlock(&pvh_global_lock);
5010 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5012 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5013 if (PV_PMAP(pv) == pmap) {
5021 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5022 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5023 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5024 if (PV_PMAP(pv) == pmap) {
5034 rw_runlock(&pvh_global_lock);
5039 * pmap_page_wired_mappings:
5041 * Return the number of managed mappings to the given physical page
5045 pmap_page_wired_mappings(vm_page_t m)
5047 struct rwlock *lock;
5048 struct md_page *pvh;
5052 int count, md_gen, pvh_gen;
5054 if ((m->oflags & VPO_UNMANAGED) != 0)
5056 rw_rlock(&pvh_global_lock);
5057 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5061 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5063 if (!PMAP_TRYLOCK(pmap)) {
5064 md_gen = m->md.pv_gen;
5068 if (md_gen != m->md.pv_gen) {
5073 pte = pmap_pte(pmap, pv->pv_va);
5074 if ((*pte & PG_W) != 0)
5078 if ((m->flags & PG_FICTITIOUS) == 0) {
5079 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5080 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5082 if (!PMAP_TRYLOCK(pmap)) {
5083 md_gen = m->md.pv_gen;
5084 pvh_gen = pvh->pv_gen;
5088 if (md_gen != m->md.pv_gen ||
5089 pvh_gen != pvh->pv_gen) {
5094 pte = pmap_pde(pmap, pv->pv_va);
5095 if ((*pte & PG_W) != 0)
5101 rw_runlock(&pvh_global_lock);
5106 * Returns TRUE if the given page is mapped individually or as part of
5107 * a 2mpage. Otherwise, returns FALSE.
5110 pmap_page_is_mapped(vm_page_t m)
5112 struct rwlock *lock;
5115 if ((m->oflags & VPO_UNMANAGED) != 0)
5117 rw_rlock(&pvh_global_lock);
5118 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5120 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5121 ((m->flags & PG_FICTITIOUS) == 0 &&
5122 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5124 rw_runlock(&pvh_global_lock);
5129 * Destroy all managed, non-wired mappings in the given user-space
5130 * pmap. This pmap cannot be active on any processor besides the
5133 * This function cannot be applied to the kernel pmap. Moreover, it
5134 * is not intended for general use. It is only to be used during
5135 * process termination. Consequently, it can be implemented in ways
5136 * that make it faster than pmap_remove(). First, it can more quickly
5137 * destroy mappings by iterating over the pmap's collection of PV
5138 * entries, rather than searching the page table. Second, it doesn't
5139 * have to test and clear the page table entries atomically, because
5140 * no processor is currently accessing the user address space. In
5141 * particular, a page table entry's dirty bit won't change state once
5142 * this function starts.
5145 pmap_remove_pages(pmap_t pmap)
5148 pt_entry_t *pte, tpte;
5149 pt_entry_t PG_M, PG_RW, PG_V;
5150 struct spglist free;
5151 vm_page_t m, mpte, mt;
5153 struct md_page *pvh;
5154 struct pv_chunk *pc, *npc;
5155 struct rwlock *lock;
5157 uint64_t inuse, bitmask;
5158 int allfree, field, freed, idx;
5159 boolean_t superpage;
5163 * Assert that the given pmap is only active on the current
5164 * CPU. Unfortunately, we cannot block another CPU from
5165 * activating the pmap while this function is executing.
5167 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5170 cpuset_t other_cpus;
5172 other_cpus = all_cpus;
5174 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5175 CPU_AND(&other_cpus, &pmap->pm_active);
5177 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5182 PG_M = pmap_modified_bit(pmap);
5183 PG_V = pmap_valid_bit(pmap);
5184 PG_RW = pmap_rw_bit(pmap);
5187 rw_rlock(&pvh_global_lock);
5189 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5192 for (field = 0; field < _NPCM; field++) {
5193 inuse = ~pc->pc_map[field] & pc_freemask[field];
5194 while (inuse != 0) {
5196 bitmask = 1UL << bit;
5197 idx = field * 64 + bit;
5198 pv = &pc->pc_pventry[idx];
5201 pte = pmap_pdpe(pmap, pv->pv_va);
5203 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5205 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5208 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5210 pte = &pte[pmap_pte_index(pv->pv_va)];
5214 * Keep track whether 'tpte' is a
5215 * superpage explicitly instead of
5216 * relying on PG_PS being set.
5218 * This is because PG_PS is numerically
5219 * identical to PG_PTE_PAT and thus a
5220 * regular page could be mistaken for
5226 if ((tpte & PG_V) == 0) {
5227 panic("bad pte va %lx pte %lx",
5232 * We cannot remove wired pages from a process' mapping at this time
5240 pa = tpte & PG_PS_FRAME;
5242 pa = tpte & PG_FRAME;
5244 m = PHYS_TO_VM_PAGE(pa);
5245 KASSERT(m->phys_addr == pa,
5246 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5247 m, (uintmax_t)m->phys_addr,
5250 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5251 m < &vm_page_array[vm_page_array_size],
5252 ("pmap_remove_pages: bad tpte %#jx",
5258 * Update the vm_page_t clean/reference bits.
5260 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5262 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5268 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5271 pc->pc_map[field] |= bitmask;
5273 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5274 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5275 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5277 if (TAILQ_EMPTY(&pvh->pv_list)) {
5278 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5279 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5280 TAILQ_EMPTY(&mt->md.pv_list))
5281 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5283 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5285 pmap_remove_pt_page(pmap, mpte);
5286 pmap_resident_count_dec(pmap, 1);
5287 KASSERT(mpte->wire_count == NPTEPG,
5288 ("pmap_remove_pages: pte page wire count error"));
5289 mpte->wire_count = 0;
5290 pmap_add_delayed_free_list(mpte, &free, FALSE);
5291 atomic_subtract_int(&cnt.v_wire_count, 1);
5294 pmap_resident_count_dec(pmap, 1);
5295 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5297 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5298 TAILQ_EMPTY(&m->md.pv_list) &&
5299 (m->flags & PG_FICTITIOUS) == 0) {
5300 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5301 if (TAILQ_EMPTY(&pvh->pv_list))
5302 vm_page_aflag_clear(m, PGA_WRITEABLE);
5305 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5309 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5310 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5311 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5313 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5319 pmap_invalidate_all(pmap);
5320 rw_runlock(&pvh_global_lock);
5322 pmap_free_zero_pages(&free);
5326 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5328 struct rwlock *lock;
5330 struct md_page *pvh;
5331 pt_entry_t *pte, mask;
5332 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5334 int md_gen, pvh_gen;
5338 rw_rlock(&pvh_global_lock);
5339 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5342 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5344 if (!PMAP_TRYLOCK(pmap)) {
5345 md_gen = m->md.pv_gen;
5349 if (md_gen != m->md.pv_gen) {
5354 pte = pmap_pte(pmap, pv->pv_va);
5357 PG_M = pmap_modified_bit(pmap);
5358 PG_RW = pmap_rw_bit(pmap);
5359 mask |= PG_RW | PG_M;
5362 PG_A = pmap_accessed_bit(pmap);
5363 PG_V = pmap_valid_bit(pmap);
5364 mask |= PG_V | PG_A;
5366 rv = (*pte & mask) == mask;
5371 if ((m->flags & PG_FICTITIOUS) == 0) {
5372 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5373 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5375 if (!PMAP_TRYLOCK(pmap)) {
5376 md_gen = m->md.pv_gen;
5377 pvh_gen = pvh->pv_gen;
5381 if (md_gen != m->md.pv_gen ||
5382 pvh_gen != pvh->pv_gen) {
5387 pte = pmap_pde(pmap, pv->pv_va);
5390 PG_M = pmap_modified_bit(pmap);
5391 PG_RW = pmap_rw_bit(pmap);
5392 mask |= PG_RW | PG_M;
5395 PG_A = pmap_accessed_bit(pmap);
5396 PG_V = pmap_valid_bit(pmap);
5397 mask |= PG_V | PG_A;
5399 rv = (*pte & mask) == mask;
5407 rw_runlock(&pvh_global_lock);
5414 * Return whether or not the specified physical page was modified
5415 * in any physical maps.
5418 pmap_is_modified(vm_page_t m)
5421 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5422 ("pmap_is_modified: page %p is not managed", m));
5425 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5426 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5427 * is clear, no PTEs can have PG_M set.
5429 VM_OBJECT_ASSERT_WLOCKED(m->object);
5430 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5432 return (pmap_page_test_mappings(m, FALSE, TRUE));
5436 * pmap_is_prefaultable:
5438 * Return whether or not the specified virtual address is eligible
5442 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5445 pt_entry_t *pte, PG_V;
5448 PG_V = pmap_valid_bit(pmap);
5451 pde = pmap_pde(pmap, addr);
5452 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5453 pte = pmap_pde_to_pte(pde, addr);
5454 rv = (*pte & PG_V) == 0;
5461 * pmap_is_referenced:
5463 * Return whether or not the specified physical page was referenced
5464 * in any physical maps.
5467 pmap_is_referenced(vm_page_t m)
5470 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5471 ("pmap_is_referenced: page %p is not managed", m));
5472 return (pmap_page_test_mappings(m, TRUE, FALSE));
5476 * Clear the write and modified bits in each of the given page's mappings.
5479 pmap_remove_write(vm_page_t m)
5481 struct md_page *pvh;
5483 struct rwlock *lock;
5484 pv_entry_t next_pv, pv;
5486 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5488 int pvh_gen, md_gen;
5490 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5491 ("pmap_remove_write: page %p is not managed", m));
5494 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5495 * set by another thread while the object is locked. Thus,
5496 * if PGA_WRITEABLE is clear, no page table entries need updating.
5498 VM_OBJECT_ASSERT_WLOCKED(m->object);
5499 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5501 rw_rlock(&pvh_global_lock);
5502 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5503 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5506 if ((m->flags & PG_FICTITIOUS) != 0)
5507 goto small_mappings;
5508 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5510 if (!PMAP_TRYLOCK(pmap)) {
5511 pvh_gen = pvh->pv_gen;
5515 if (pvh_gen != pvh->pv_gen) {
5521 PG_RW = pmap_rw_bit(pmap);
5523 pde = pmap_pde(pmap, va);
5524 if ((*pde & PG_RW) != 0)
5525 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5526 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5527 ("inconsistent pv lock %p %p for page %p",
5528 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5532 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5534 if (!PMAP_TRYLOCK(pmap)) {
5535 pvh_gen = pvh->pv_gen;
5536 md_gen = m->md.pv_gen;
5540 if (pvh_gen != pvh->pv_gen ||
5541 md_gen != m->md.pv_gen) {
5547 PG_M = pmap_modified_bit(pmap);
5548 PG_RW = pmap_rw_bit(pmap);
5549 pde = pmap_pde(pmap, pv->pv_va);
5550 KASSERT((*pde & PG_PS) == 0,
5551 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5553 pte = pmap_pde_to_pte(pde, pv->pv_va);
5556 if (oldpte & PG_RW) {
5557 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5560 if ((oldpte & PG_M) != 0)
5562 pmap_invalidate_page(pmap, pv->pv_va);
5567 vm_page_aflag_clear(m, PGA_WRITEABLE);
5568 rw_runlock(&pvh_global_lock);
5571 static __inline boolean_t
5572 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5575 if (!pmap_emulate_ad_bits(pmap))
5578 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5581 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
5582 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5583 * if the EPT_PG_WRITE bit is set.
5585 if ((pte & EPT_PG_WRITE) != 0)
5589 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5591 if ((pte & EPT_PG_EXECUTE) == 0 ||
5592 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5598 #define PMAP_TS_REFERENCED_MAX 5
5601 * pmap_ts_referenced:
5603 * Return a count of reference bits for a page, clearing those bits.
5604 * It is not necessary for every reference bit to be cleared, but it
5605 * is necessary that 0 only be returned when there are truly no
5606 * reference bits set.
5608 * XXX: The exact number of bits to check and clear is a matter that
5609 * should be tested and standardized at some point in the future for
5610 * optimal aging of shared pages.
5613 pmap_ts_referenced(vm_page_t m)
5615 struct md_page *pvh;
5618 struct rwlock *lock;
5619 pd_entry_t oldpde, *pde;
5620 pt_entry_t *pte, PG_A;
5623 int cleared, md_gen, not_cleared, pvh_gen;
5624 struct spglist free;
5627 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5628 ("pmap_ts_referenced: page %p is not managed", m));
5631 pa = VM_PAGE_TO_PHYS(m);
5632 lock = PHYS_TO_PV_LIST_LOCK(pa);
5633 pvh = pa_to_pvh(pa);
5634 rw_rlock(&pvh_global_lock);
5638 if ((m->flags & PG_FICTITIOUS) != 0 ||
5639 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5640 goto small_mappings;
5646 if (!PMAP_TRYLOCK(pmap)) {
5647 pvh_gen = pvh->pv_gen;
5651 if (pvh_gen != pvh->pv_gen) {
5656 PG_A = pmap_accessed_bit(pmap);
5658 pde = pmap_pde(pmap, pv->pv_va);
5660 if ((*pde & PG_A) != 0) {
5662 * Since this reference bit is shared by 512 4KB
5663 * pages, it should not be cleared every time it is
5664 * tested. Apply a simple "hash" function on the
5665 * physical page number, the virtual superpage number,
5666 * and the pmap address to select one 4KB page out of
5667 * the 512 on which testing the reference bit will
5668 * result in clearing that reference bit. This
5669 * function is designed to avoid the selection of the
5670 * same 4KB page for every 2MB page mapping.
5672 * On demotion, a mapping that hasn't been referenced
5673 * is simply destroyed. To avoid the possibility of a
5674 * subsequent page fault on a demoted wired mapping,
5675 * always leave its reference bit set. Moreover,
5676 * since the superpage is wired, the current state of
5677 * its reference bit won't affect page replacement.
5679 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5680 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5681 (*pde & PG_W) == 0) {
5682 if (safe_to_clear_referenced(pmap, oldpde)) {
5683 atomic_clear_long(pde, PG_A);
5684 pmap_invalidate_page(pmap, pv->pv_va);
5686 } else if (pmap_demote_pde_locked(pmap, pde,
5687 pv->pv_va, &lock)) {
5689 * Remove the mapping to a single page
5690 * so that a subsequent access may
5691 * repromote. Since the underlying
5692 * page table page is fully populated,
5693 * this removal never frees a page
5697 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5699 pte = pmap_pde_to_pte(pde, va);
5700 pmap_remove_pte(pmap, pte, va, *pde,
5702 pmap_invalidate_page(pmap, va);
5708 * The superpage mapping was removed
5709 * entirely and therefore 'pv' is no
5717 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5718 ("inconsistent pv lock %p %p for page %p",
5719 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5724 /* Rotate the PV list if it has more than one entry. */
5725 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5726 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5727 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5730 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5732 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5734 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5741 if (!PMAP_TRYLOCK(pmap)) {
5742 pvh_gen = pvh->pv_gen;
5743 md_gen = m->md.pv_gen;
5747 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5752 PG_A = pmap_accessed_bit(pmap);
5753 pde = pmap_pde(pmap, pv->pv_va);
5754 KASSERT((*pde & PG_PS) == 0,
5755 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5757 pte = pmap_pde_to_pte(pde, pv->pv_va);
5758 if ((*pte & PG_A) != 0) {
5759 if (safe_to_clear_referenced(pmap, *pte)) {
5760 atomic_clear_long(pte, PG_A);
5761 pmap_invalidate_page(pmap, pv->pv_va);
5763 } else if ((*pte & PG_W) == 0) {
5765 * Wired pages cannot be paged out so
5766 * doing accessed bit emulation for
5767 * them is wasted effort. We do the
5768 * hard work for unwired pages only.
5770 pmap_remove_pte(pmap, pte, pv->pv_va,
5771 *pde, &free, &lock);
5772 pmap_invalidate_page(pmap, pv->pv_va);
5777 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5778 ("inconsistent pv lock %p %p for page %p",
5779 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5784 /* Rotate the PV list if it has more than one entry. */
5785 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5786 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5787 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5790 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5791 not_cleared < PMAP_TS_REFERENCED_MAX);
5794 rw_runlock(&pvh_global_lock);
5795 pmap_free_zero_pages(&free);
5796 return (cleared + not_cleared);
5800 * Apply the given advice to the specified range of addresses within the
5801 * given pmap. Depending on the advice, clear the referenced and/or
5802 * modified flags in each mapping and set the mapped page's dirty field.
5805 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5807 struct rwlock *lock;
5808 pml4_entry_t *pml4e;
5810 pd_entry_t oldpde, *pde;
5811 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5812 vm_offset_t va_next;
5814 boolean_t anychanged, pv_lists_locked;
5816 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5820 * A/D bit emulation requires an alternate code path when clearing
5821 * the modified and accessed bits below. Since this function is
5822 * advisory in nature we skip it entirely for pmaps that require
5823 * A/D bit emulation.
5825 if (pmap_emulate_ad_bits(pmap))
5828 PG_A = pmap_accessed_bit(pmap);
5829 PG_G = pmap_global_bit(pmap);
5830 PG_M = pmap_modified_bit(pmap);
5831 PG_V = pmap_valid_bit(pmap);
5832 PG_RW = pmap_rw_bit(pmap);
5834 pv_lists_locked = FALSE;
5838 for (; sva < eva; sva = va_next) {
5839 pml4e = pmap_pml4e(pmap, sva);
5840 if ((*pml4e & PG_V) == 0) {
5841 va_next = (sva + NBPML4) & ~PML4MASK;
5846 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5847 if ((*pdpe & PG_V) == 0) {
5848 va_next = (sva + NBPDP) & ~PDPMASK;
5853 va_next = (sva + NBPDR) & ~PDRMASK;
5856 pde = pmap_pdpe_to_pde(pdpe, sva);
5858 if ((oldpde & PG_V) == 0)
5860 else if ((oldpde & PG_PS) != 0) {
5861 if ((oldpde & PG_MANAGED) == 0)
5863 if (!pv_lists_locked) {
5864 pv_lists_locked = TRUE;
5865 if (!rw_try_rlock(&pvh_global_lock)) {
5867 pmap_invalidate_all(pmap);
5869 rw_rlock(&pvh_global_lock);
5874 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5879 * The large page mapping was destroyed.
5885 * Unless the page mappings are wired, remove the
5886 * mapping to a single page so that a subsequent
5887 * access may repromote. Since the underlying page
5888 * table page is fully populated, this removal never
5889 * frees a page table page.
5891 if ((oldpde & PG_W) == 0) {
5892 pte = pmap_pde_to_pte(pde, sva);
5893 KASSERT((*pte & PG_V) != 0,
5894 ("pmap_advise: invalid PTE"));
5895 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
5904 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5906 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
5909 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5910 if (advice == MADV_DONTNEED) {
5912 * Future calls to pmap_is_modified()
5913 * can be avoided by making the page
5916 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5919 atomic_clear_long(pte, PG_M | PG_A);
5920 } else if ((*pte & PG_A) != 0)
5921 atomic_clear_long(pte, PG_A);
5924 if ((*pte & PG_G) != 0)
5925 pmap_invalidate_page(pmap, sva);
5931 pmap_invalidate_all(pmap);
5932 if (pv_lists_locked)
5933 rw_runlock(&pvh_global_lock);
5938 * Clear the modify bits on the specified physical page.
5941 pmap_clear_modify(vm_page_t m)
5943 struct md_page *pvh;
5945 pv_entry_t next_pv, pv;
5946 pd_entry_t oldpde, *pde;
5947 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
5948 struct rwlock *lock;
5950 int md_gen, pvh_gen;
5952 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5953 ("pmap_clear_modify: page %p is not managed", m));
5954 VM_OBJECT_ASSERT_WLOCKED(m->object);
5955 KASSERT(!vm_page_xbusied(m),
5956 ("pmap_clear_modify: page %p is exclusive busied", m));
5959 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5960 * If the object containing the page is locked and the page is not
5961 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5963 if ((m->aflags & PGA_WRITEABLE) == 0)
5965 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5966 rw_rlock(&pvh_global_lock);
5967 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5970 if ((m->flags & PG_FICTITIOUS) != 0)
5971 goto small_mappings;
5972 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5974 if (!PMAP_TRYLOCK(pmap)) {
5975 pvh_gen = pvh->pv_gen;
5979 if (pvh_gen != pvh->pv_gen) {
5984 PG_M = pmap_modified_bit(pmap);
5985 PG_V = pmap_valid_bit(pmap);
5986 PG_RW = pmap_rw_bit(pmap);
5988 pde = pmap_pde(pmap, va);
5990 if ((oldpde & PG_RW) != 0) {
5991 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
5992 if ((oldpde & PG_W) == 0) {
5994 * Write protect the mapping to a
5995 * single page so that a subsequent
5996 * write access may repromote.
5998 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6000 pte = pmap_pde_to_pte(pde, va);
6002 if ((oldpte & PG_V) != 0) {
6003 while (!atomic_cmpset_long(pte,
6005 oldpte & ~(PG_M | PG_RW)))
6008 pmap_invalidate_page(pmap, va);
6016 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6018 if (!PMAP_TRYLOCK(pmap)) {
6019 md_gen = m->md.pv_gen;
6020 pvh_gen = pvh->pv_gen;
6024 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6029 PG_M = pmap_modified_bit(pmap);
6030 PG_RW = pmap_rw_bit(pmap);
6031 pde = pmap_pde(pmap, pv->pv_va);
6032 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6033 " a 2mpage in page %p's pv list", m));
6034 pte = pmap_pde_to_pte(pde, pv->pv_va);
6035 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6036 atomic_clear_long(pte, PG_M);
6037 pmap_invalidate_page(pmap, pv->pv_va);
6042 rw_runlock(&pvh_global_lock);
6046 * Miscellaneous support routines follow
6049 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6050 static __inline void
6051 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6056 * The cache mode bits are all in the low 32-bits of the
6057 * PTE, so we can just spin on updating the low 32-bits.
6060 opte = *(u_int *)pte;
6061 npte = opte & ~mask;
6063 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6066 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6067 static __inline void
6068 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6073 * The cache mode bits are all in the low 32-bits of the
6074 * PDE, so we can just spin on updating the low 32-bits.
6077 opde = *(u_int *)pde;
6078 npde = opde & ~mask;
6080 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6084 * Map a set of physical memory pages into the kernel virtual
6085 * address space. Return a pointer to where it is mapped. This
6086 * routine is intended to be used for mapping device memory,
6090 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6092 vm_offset_t va, offset;
6096 * If the specified range of physical addresses fits within the direct
6097 * map window, use the direct map.
6099 if (pa < dmaplimit && pa + size < dmaplimit) {
6100 va = PHYS_TO_DMAP(pa);
6101 if (!pmap_change_attr(va, size, mode))
6102 return ((void *)va);
6104 offset = pa & PAGE_MASK;
6105 size = round_page(offset + size);
6106 va = kva_alloc(size);
6108 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
6109 pa = trunc_page(pa);
6110 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6111 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6112 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6113 pmap_invalidate_cache_range(va, va + tmpsize);
6114 return ((void *)(va + offset));
6118 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6121 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6125 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6128 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6132 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6134 vm_offset_t base, offset;
6136 /* If we gave a direct map region in pmap_mapdev, do nothing */
6137 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6139 base = trunc_page(va);
6140 offset = va & PAGE_MASK;
6141 size = round_page(offset + size);
6142 kva_free(base, size);
6146 * Tries to demote a 1GB page mapping.
6149 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6151 pdp_entry_t newpdpe, oldpdpe;
6152 pd_entry_t *firstpde, newpde, *pde;
6153 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6157 PG_A = pmap_accessed_bit(pmap);
6158 PG_M = pmap_modified_bit(pmap);
6159 PG_V = pmap_valid_bit(pmap);
6160 PG_RW = pmap_rw_bit(pmap);
6162 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6164 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6165 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6166 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6167 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6168 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6169 " in pmap %p", va, pmap);
6172 mpdepa = VM_PAGE_TO_PHYS(mpde);
6173 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6174 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6175 KASSERT((oldpdpe & PG_A) != 0,
6176 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6177 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6178 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6182 * Initialize the page directory page.
6184 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6190 * Demote the mapping.
6195 * Invalidate a stale recursive mapping of the page directory page.
6197 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6199 pmap_pdpe_demotions++;
6200 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6201 " in pmap %p", va, pmap);
6206 * Sets the memory attribute for the specified page.
6209 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6212 m->md.pat_mode = ma;
6215 * If "m" is a normal page, update its direct mapping. This update
6216 * can be relied upon to perform any cache operations that are
6217 * required for data coherence.
6219 if ((m->flags & PG_FICTITIOUS) == 0 &&
6220 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6222 panic("memory attribute change on the direct map failed");
6226 * Changes the specified virtual address range's memory type to that given by
6227 * the parameter "mode". The specified virtual address range must be
6228 * completely contained within either the direct map or the kernel map. If
6229 * the virtual address range is contained within the kernel map, then the
6230 * memory type for each of the corresponding ranges of the direct map is also
6231 * changed. (The corresponding ranges of the direct map are those ranges that
6232 * map the same physical pages as the specified virtual address range.) These
6233 * changes to the direct map are necessary because Intel describes the
6234 * behavior of their processors as "undefined" if two or more mappings to the
6235 * same physical page have different memory types.
6237 * Returns zero if the change completed successfully, and either EINVAL or
6238 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6239 * of the virtual address range was not mapped, and ENOMEM is returned if
6240 * there was insufficient memory available to complete the change. In the
6241 * latter case, the memory type may have been changed on some part of the
6242 * virtual address range or the direct map.
6245 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6249 PMAP_LOCK(kernel_pmap);
6250 error = pmap_change_attr_locked(va, size, mode);
6251 PMAP_UNLOCK(kernel_pmap);
6256 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6258 vm_offset_t base, offset, tmpva;
6259 vm_paddr_t pa_start, pa_end;
6263 int cache_bits_pte, cache_bits_pde, error;
6266 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6267 base = trunc_page(va);
6268 offset = va & PAGE_MASK;
6269 size = round_page(offset + size);
6272 * Only supported on kernel virtual addresses, including the direct
6273 * map but excluding the recursive map.
6275 if (base < DMAP_MIN_ADDRESS)
6278 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6279 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6283 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6284 * into 4KB pages if required.
6286 for (tmpva = base; tmpva < base + size; ) {
6287 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6290 if (*pdpe & PG_PS) {
6292 * If the current 1GB page already has the required
6293 * memory type, then we need not demote this page. Just
6294 * increment tmpva to the next 1GB page frame.
6296 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6297 tmpva = trunc_1gpage(tmpva) + NBPDP;
6302 * If the current offset aligns with a 1GB page frame
6303 * and there is at least 1GB left within the range, then
6304 * we need not break down this page into 2MB pages.
6306 if ((tmpva & PDPMASK) == 0 &&
6307 tmpva + PDPMASK < base + size) {
6311 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6314 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6319 * If the current 2MB page already has the required
6320 * memory type, then we need not demote this page. Just
6321 * increment tmpva to the next 2MB page frame.
6323 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6324 tmpva = trunc_2mpage(tmpva) + NBPDR;
6329 * If the current offset aligns with a 2MB page frame
6330 * and there is at least 2MB left within the range, then
6331 * we need not break down this page into 4KB pages.
6333 if ((tmpva & PDRMASK) == 0 &&
6334 tmpva + PDRMASK < base + size) {
6338 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6341 pte = pmap_pde_to_pte(pde, tmpva);
6349 * Ok, all the pages exist, so run through them updating their
6350 * cache mode if required.
6352 pa_start = pa_end = 0;
6353 for (tmpva = base; tmpva < base + size; ) {
6354 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6355 if (*pdpe & PG_PS) {
6356 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6357 pmap_pde_attr(pdpe, cache_bits_pde,
6361 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6362 if (pa_start == pa_end) {
6363 /* Start physical address run. */
6364 pa_start = *pdpe & PG_PS_FRAME;
6365 pa_end = pa_start + NBPDP;
6366 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6369 /* Run ended, update direct map. */
6370 error = pmap_change_attr_locked(
6371 PHYS_TO_DMAP(pa_start),
6372 pa_end - pa_start, mode);
6375 /* Start physical address run. */
6376 pa_start = *pdpe & PG_PS_FRAME;
6377 pa_end = pa_start + NBPDP;
6380 tmpva = trunc_1gpage(tmpva) + NBPDP;
6383 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6385 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6386 pmap_pde_attr(pde, cache_bits_pde,
6390 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6391 if (pa_start == pa_end) {
6392 /* Start physical address run. */
6393 pa_start = *pde & PG_PS_FRAME;
6394 pa_end = pa_start + NBPDR;
6395 } else if (pa_end == (*pde & PG_PS_FRAME))
6398 /* Run ended, update direct map. */
6399 error = pmap_change_attr_locked(
6400 PHYS_TO_DMAP(pa_start),
6401 pa_end - pa_start, mode);
6404 /* Start physical address run. */
6405 pa_start = *pde & PG_PS_FRAME;
6406 pa_end = pa_start + NBPDR;
6409 tmpva = trunc_2mpage(tmpva) + NBPDR;
6411 pte = pmap_pde_to_pte(pde, tmpva);
6412 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6413 pmap_pte_attr(pte, cache_bits_pte,
6417 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6418 if (pa_start == pa_end) {
6419 /* Start physical address run. */
6420 pa_start = *pte & PG_FRAME;
6421 pa_end = pa_start + PAGE_SIZE;
6422 } else if (pa_end == (*pte & PG_FRAME))
6423 pa_end += PAGE_SIZE;
6425 /* Run ended, update direct map. */
6426 error = pmap_change_attr_locked(
6427 PHYS_TO_DMAP(pa_start),
6428 pa_end - pa_start, mode);
6431 /* Start physical address run. */
6432 pa_start = *pte & PG_FRAME;
6433 pa_end = pa_start + PAGE_SIZE;
6439 if (error == 0 && pa_start != pa_end)
6440 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6441 pa_end - pa_start, mode);
6444 * Flush CPU caches if required to make sure any data isn't cached that
6445 * shouldn't be, etc.
6448 pmap_invalidate_range(kernel_pmap, base, tmpva);
6449 pmap_invalidate_cache_range(base, tmpva);
6455 * Demotes any mapping within the direct map region that covers more than the
6456 * specified range of physical addresses. This range's size must be a power
6457 * of two and its starting address must be a multiple of its size. Since the
6458 * demotion does not change any attributes of the mapping, a TLB invalidation
6459 * is not mandatory. The caller may, however, request a TLB invalidation.
6462 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6471 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6472 KASSERT((base & (len - 1)) == 0,
6473 ("pmap_demote_DMAP: base is not a multiple of len"));
6474 if (len < NBPDP && base < dmaplimit) {
6475 va = PHYS_TO_DMAP(base);
6477 PMAP_LOCK(kernel_pmap);
6478 pdpe = pmap_pdpe(kernel_pmap, va);
6479 if ((*pdpe & X86_PG_V) == 0)
6480 panic("pmap_demote_DMAP: invalid PDPE");
6481 if ((*pdpe & PG_PS) != 0) {
6482 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6483 panic("pmap_demote_DMAP: PDPE failed");
6487 pde = pmap_pdpe_to_pde(pdpe, va);
6488 if ((*pde & X86_PG_V) == 0)
6489 panic("pmap_demote_DMAP: invalid PDE");
6490 if ((*pde & PG_PS) != 0) {
6491 if (!pmap_demote_pde(kernel_pmap, pde, va))
6492 panic("pmap_demote_DMAP: PDE failed");
6496 if (changed && invalidate)
6497 pmap_invalidate_page(kernel_pmap, va);
6498 PMAP_UNLOCK(kernel_pmap);
6503 * perform the pmap work for mincore
6506 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6509 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6513 PG_A = pmap_accessed_bit(pmap);
6514 PG_M = pmap_modified_bit(pmap);
6515 PG_V = pmap_valid_bit(pmap);
6516 PG_RW = pmap_rw_bit(pmap);
6520 pdep = pmap_pde(pmap, addr);
6521 if (pdep != NULL && (*pdep & PG_V)) {
6522 if (*pdep & PG_PS) {
6524 /* Compute the physical address of the 4KB page. */
6525 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6527 val = MINCORE_SUPER;
6529 pte = *pmap_pde_to_pte(pdep, addr);
6530 pa = pte & PG_FRAME;
6538 if ((pte & PG_V) != 0) {
6539 val |= MINCORE_INCORE;
6540 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6541 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6542 if ((pte & PG_A) != 0)
6543 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6545 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6546 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6547 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6548 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6549 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6552 PA_UNLOCK_COND(*locked_pa);
6558 pmap_activate(struct thread *td)
6560 pmap_t pmap, oldpmap;
6564 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6565 oldpmap = PCPU_GET(curpmap);
6566 cpuid = PCPU_GET(cpuid);
6568 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6569 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6570 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
6572 CPU_CLR(cpuid, &oldpmap->pm_active);
6573 CPU_SET(cpuid, &pmap->pm_active);
6574 CPU_SET(cpuid, &pmap->pm_save);
6576 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
6577 load_cr3(pmap->pm_cr3);
6578 PCPU_SET(curpmap, pmap);
6583 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6588 * Increase the starting virtual address of the given mapping if a
6589 * different alignment might result in more superpage mappings.
6592 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6593 vm_offset_t *addr, vm_size_t size)
6595 vm_offset_t superpage_offset;
6599 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6600 offset += ptoa(object->pg_color);
6601 superpage_offset = offset & PDRMASK;
6602 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6603 (*addr & PDRMASK) == superpage_offset)
6605 if ((*addr & PDRMASK) < superpage_offset)
6606 *addr = (*addr & ~PDRMASK) + superpage_offset;
6608 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6612 static unsigned long num_dirty_emulations;
6613 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6614 &num_dirty_emulations, 0, NULL);
6616 static unsigned long num_accessed_emulations;
6617 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6618 &num_accessed_emulations, 0, NULL);
6620 static unsigned long num_superpage_accessed_emulations;
6621 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6622 &num_superpage_accessed_emulations, 0, NULL);
6624 static unsigned long ad_emulation_superpage_promotions;
6625 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6626 &ad_emulation_superpage_promotions, 0, NULL);
6627 #endif /* INVARIANTS */
6630 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6633 struct rwlock *lock;
6636 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6637 boolean_t pv_lists_locked;
6639 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6640 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6642 if (!pmap_emulate_ad_bits(pmap))
6645 PG_A = pmap_accessed_bit(pmap);
6646 PG_M = pmap_modified_bit(pmap);
6647 PG_V = pmap_valid_bit(pmap);
6648 PG_RW = pmap_rw_bit(pmap);
6652 pv_lists_locked = FALSE;
6656 pde = pmap_pde(pmap, va);
6657 if (pde == NULL || (*pde & PG_V) == 0)
6660 if ((*pde & PG_PS) != 0) {
6661 if (ftype == VM_PROT_READ) {
6663 atomic_add_long(&num_superpage_accessed_emulations, 1);
6671 pte = pmap_pde_to_pte(pde, va);
6672 if ((*pte & PG_V) == 0)
6675 if (ftype == VM_PROT_WRITE) {
6676 if ((*pte & PG_RW) == 0)
6682 /* try to promote the mapping */
6683 if (va < VM_MAXUSER_ADDRESS)
6684 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6688 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6690 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6691 pmap_ps_enabled(pmap) &&
6692 (m->flags & PG_FICTITIOUS) == 0 &&
6693 vm_reserv_level_iffullpop(m) == 0) {
6694 if (!pv_lists_locked) {
6695 pv_lists_locked = TRUE;
6696 if (!rw_try_rlock(&pvh_global_lock)) {
6698 rw_rlock(&pvh_global_lock);
6702 pmap_promote_pde(pmap, pde, va, &lock);
6704 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6708 if (ftype == VM_PROT_WRITE)
6709 atomic_add_long(&num_dirty_emulations, 1);
6711 atomic_add_long(&num_accessed_emulations, 1);
6713 rv = 0; /* success */
6717 if (pv_lists_locked)
6718 rw_runlock(&pvh_global_lock);
6724 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6729 pt_entry_t *pte, PG_V;
6733 PG_V = pmap_valid_bit(pmap);
6736 pml4 = pmap_pml4e(pmap, va);
6738 if ((*pml4 & PG_V) == 0)
6741 pdp = pmap_pml4e_to_pdpe(pml4, va);
6743 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6746 pde = pmap_pdpe_to_pde(pdp, va);
6748 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6751 pte = pmap_pde_to_pte(pde, va);
6759 #include "opt_ddb.h"
6761 #include <ddb/ddb.h>
6763 DB_SHOW_COMMAND(pte, pmap_print_pte)
6769 pt_entry_t *pte, PG_V;
6773 va = (vm_offset_t)addr;
6774 pmap = PCPU_GET(curpmap); /* XXX */
6776 db_printf("show pte addr\n");
6779 PG_V = pmap_valid_bit(pmap);
6780 pml4 = pmap_pml4e(pmap, va);
6781 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
6782 if ((*pml4 & PG_V) == 0) {
6786 pdp = pmap_pml4e_to_pdpe(pml4, va);
6787 db_printf(" pdpe %#016lx", *pdp);
6788 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
6792 pde = pmap_pdpe_to_pde(pdp, va);
6793 db_printf(" pde %#016lx", *pde);
6794 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
6798 pte = pmap_pde_to_pte(pde, va);
6799 db_printf(" pte %#016lx\n", *pte);
6802 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
6807 a = (vm_paddr_t)addr;
6808 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
6810 db_printf("show phys2dmap addr\n");