2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2018 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
126 #include <sys/turnstile.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/intr_machdep.h>
148 #include <x86/apicvar.h>
149 #include <machine/cpu.h>
150 #include <machine/cputypes.h>
151 #include <machine/md_var.h>
152 #include <machine/pcb.h>
153 #include <machine/specialreg.h>
155 #include <machine/smp.h>
157 #include <machine/tss.h>
159 static __inline boolean_t
160 pmap_type_guest(pmap_t pmap)
163 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
166 static __inline boolean_t
167 pmap_emulate_ad_bits(pmap_t pmap)
170 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
173 static __inline pt_entry_t
174 pmap_valid_bit(pmap_t pmap)
178 switch (pmap->pm_type) {
184 if (pmap_emulate_ad_bits(pmap))
185 mask = EPT_PG_EMUL_V;
190 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
196 static __inline pt_entry_t
197 pmap_rw_bit(pmap_t pmap)
201 switch (pmap->pm_type) {
207 if (pmap_emulate_ad_bits(pmap))
208 mask = EPT_PG_EMUL_RW;
213 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
219 static pt_entry_t pg_g;
221 static __inline pt_entry_t
222 pmap_global_bit(pmap_t pmap)
226 switch (pmap->pm_type) {
235 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
241 static __inline pt_entry_t
242 pmap_accessed_bit(pmap_t pmap)
246 switch (pmap->pm_type) {
252 if (pmap_emulate_ad_bits(pmap))
258 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
264 static __inline pt_entry_t
265 pmap_modified_bit(pmap_t pmap)
269 switch (pmap->pm_type) {
275 if (pmap_emulate_ad_bits(pmap))
281 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
287 #if !defined(DIAGNOSTIC)
288 #ifdef __GNUC_GNU_INLINE__
289 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
291 #define PMAP_INLINE extern inline
298 #define PV_STAT(x) do { x ; } while (0)
300 #define PV_STAT(x) do { } while (0)
303 #define pa_index(pa) ((pa) >> PDRSHIFT)
304 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
306 #define NPV_LIST_LOCKS MAXCPU
308 #define PHYS_TO_PV_LIST_LOCK(pa) \
309 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
311 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
312 struct rwlock **_lockp = (lockp); \
313 struct rwlock *_new_lock; \
315 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
316 if (_new_lock != *_lockp) { \
317 if (*_lockp != NULL) \
318 rw_wunlock(*_lockp); \
319 *_lockp = _new_lock; \
324 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
325 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
327 #define RELEASE_PV_LIST_LOCK(lockp) do { \
328 struct rwlock **_lockp = (lockp); \
330 if (*_lockp != NULL) { \
331 rw_wunlock(*_lockp); \
336 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
337 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
339 struct pmap kernel_pmap_store;
341 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
342 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
345 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
346 "Number of kernel page table pages allocated on bootup");
349 vm_paddr_t dmaplimit;
350 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
353 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
355 static int pat_works = 1;
356 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
357 "Is page attribute table fully functional?");
359 static int pg_ps_enabled = 1;
360 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
361 &pg_ps_enabled, 0, "Are large page mappings enabled?");
363 #define PAT_INDEX_SIZE 8
364 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
366 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
367 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
368 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
369 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
371 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
372 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
373 static int ndmpdpphys; /* number of DMPDPphys pages */
375 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
378 * pmap_mapdev support pre initialization (i.e. console)
380 #define PMAP_PREINIT_MAPPING_COUNT 8
381 static struct pmap_preinit_mapping {
386 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
387 static int pmap_initialized;
390 * Data for the pv entry allocation mechanism.
391 * Updates to pv_invl_gen are protected by the pv_list_locks[]
392 * elements, but reads are not.
394 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
395 static struct mtx __exclusive_cache_line pv_chunks_mutex;
396 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
397 static u_long pv_invl_gen[NPV_LIST_LOCKS];
398 static struct md_page *pv_table;
399 static struct md_page pv_dummy;
402 * All those kernel PT submaps that BSD is so fond of
404 pt_entry_t *CMAP1 = NULL;
406 static vm_offset_t qframe = 0;
407 static struct mtx qframe_mtx;
409 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
411 int pmap_pcid_enabled = 1;
412 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
413 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
414 int invpcid_works = 0;
415 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
416 "Is the invpcid instruction available ?");
418 int __read_frequently pti = 0;
419 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
421 "Page Table Isolation enabled");
422 static vm_object_t pti_obj;
423 static pml4_entry_t *pti_pml4;
424 static vm_pindex_t pti_pg_idx;
425 static bool pti_finalized;
428 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
435 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
437 return (sysctl_handle_64(oidp, &res, 0, req));
439 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
440 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
441 "Count of saved TLB context on switch");
443 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
444 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
445 static struct mtx invl_gen_mtx;
446 static u_long pmap_invl_gen = 0;
447 /* Fake lock object to satisfy turnstiles interface. */
448 static struct lock_object invl_gen_ts = {
456 return (curthread->td_md.md_invl_gen.gen == 0);
459 #define PMAP_ASSERT_NOT_IN_DI() \
460 KASSERT(pmap_not_in_di(), ("DI already started"))
463 * Start a new Delayed Invalidation (DI) block of code, executed by
464 * the current thread. Within a DI block, the current thread may
465 * destroy both the page table and PV list entries for a mapping and
466 * then release the corresponding PV list lock before ensuring that
467 * the mapping is flushed from the TLBs of any processors with the
471 pmap_delayed_invl_started(void)
473 struct pmap_invl_gen *invl_gen;
476 invl_gen = &curthread->td_md.md_invl_gen;
477 PMAP_ASSERT_NOT_IN_DI();
478 mtx_lock(&invl_gen_mtx);
479 if (LIST_EMPTY(&pmap_invl_gen_tracker))
480 currgen = pmap_invl_gen;
482 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
483 invl_gen->gen = currgen + 1;
484 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
485 mtx_unlock(&invl_gen_mtx);
489 * Finish the DI block, previously started by the current thread. All
490 * required TLB flushes for the pages marked by
491 * pmap_delayed_invl_page() must be finished before this function is
494 * This function works by bumping the global DI generation number to
495 * the generation number of the current thread's DI, unless there is a
496 * pending DI that started earlier. In the latter case, bumping the
497 * global DI generation number would incorrectly signal that the
498 * earlier DI had finished. Instead, this function bumps the earlier
499 * DI's generation number to match the generation number of the
500 * current thread's DI.
503 pmap_delayed_invl_finished(void)
505 struct pmap_invl_gen *invl_gen, *next;
506 struct turnstile *ts;
508 invl_gen = &curthread->td_md.md_invl_gen;
509 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
510 mtx_lock(&invl_gen_mtx);
511 next = LIST_NEXT(invl_gen, link);
513 turnstile_chain_lock(&invl_gen_ts);
514 ts = turnstile_lookup(&invl_gen_ts);
515 pmap_invl_gen = invl_gen->gen;
517 turnstile_broadcast(ts, TS_SHARED_QUEUE);
518 turnstile_unpend(ts);
520 turnstile_chain_unlock(&invl_gen_ts);
522 next->gen = invl_gen->gen;
524 LIST_REMOVE(invl_gen, link);
525 mtx_unlock(&invl_gen_mtx);
530 static long invl_wait;
531 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
532 "Number of times DI invalidation blocked pmap_remove_all/write");
536 pmap_delayed_invl_genp(vm_page_t m)
539 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
543 * Ensure that all currently executing DI blocks, that need to flush
544 * TLB for the given page m, actually flushed the TLB at the time the
545 * function returned. If the page m has an empty PV list and we call
546 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
547 * valid mapping for the page m in either its page table or TLB.
549 * This function works by blocking until the global DI generation
550 * number catches up with the generation number associated with the
551 * given page m and its PV list. Since this function's callers
552 * typically own an object lock and sometimes own a page lock, it
553 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
557 pmap_delayed_invl_wait(vm_page_t m)
559 struct turnstile *ts;
562 bool accounted = false;
565 m_gen = pmap_delayed_invl_genp(m);
566 while (*m_gen > pmap_invl_gen) {
569 atomic_add_long(&invl_wait, 1);
573 ts = turnstile_trywait(&invl_gen_ts);
574 if (*m_gen > pmap_invl_gen)
575 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
577 turnstile_cancel(ts);
582 * Mark the page m's PV list as participating in the current thread's
583 * DI block. Any threads concurrently using m's PV list to remove or
584 * restrict all mappings to m will wait for the current thread's DI
585 * block to complete before proceeding.
587 * The function works by setting the DI generation number for m's PV
588 * list to at least the DI generation number of the current thread.
589 * This forces a caller of pmap_delayed_invl_wait() to block until
590 * current thread calls pmap_delayed_invl_finished().
593 pmap_delayed_invl_page(vm_page_t m)
597 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
598 gen = curthread->td_md.md_invl_gen.gen;
601 m_gen = pmap_delayed_invl_genp(m);
609 static caddr_t crashdumpmap;
612 * Internal flags for pmap_enter()'s helper functions.
614 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
615 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
617 static void free_pv_chunk(struct pv_chunk *pc);
618 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
619 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
620 static int popcnt_pc_map_pq(uint64_t *map);
621 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
622 static void reserve_pv_entries(pmap_t pmap, int needed,
623 struct rwlock **lockp);
624 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
625 struct rwlock **lockp);
626 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
627 u_int flags, struct rwlock **lockp);
628 #if VM_NRESERVLEVEL > 0
629 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
630 struct rwlock **lockp);
632 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
633 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
636 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
637 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
638 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
639 vm_offset_t va, struct rwlock **lockp);
640 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
642 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
643 vm_prot_t prot, struct rwlock **lockp);
644 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
645 u_int flags, vm_page_t m, struct rwlock **lockp);
646 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
647 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
648 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
649 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
650 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
652 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
653 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
654 #if VM_NRESERVLEVEL > 0
655 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
656 struct rwlock **lockp);
658 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
660 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
661 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
663 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
664 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
665 static void pmap_pti_wire_pte(void *pte);
666 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
667 struct spglist *free, struct rwlock **lockp);
668 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
669 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
670 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
671 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
672 struct spglist *free);
673 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
674 pd_entry_t *pde, struct spglist *free,
675 struct rwlock **lockp);
676 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
677 vm_page_t m, struct rwlock **lockp);
678 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
680 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
682 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
683 struct rwlock **lockp);
684 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
685 struct rwlock **lockp);
686 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
687 struct rwlock **lockp);
689 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
690 struct spglist *free);
691 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
693 /********************/
694 /* Inline functions */
695 /********************/
697 /* Return a non-clipped PD index for a given VA */
698 static __inline vm_pindex_t
699 pmap_pde_pindex(vm_offset_t va)
701 return (va >> PDRSHIFT);
705 /* Return a pointer to the PML4 slot that corresponds to a VA */
706 static __inline pml4_entry_t *
707 pmap_pml4e(pmap_t pmap, vm_offset_t va)
710 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
713 /* Return a pointer to the PDP slot that corresponds to a VA */
714 static __inline pdp_entry_t *
715 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
719 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
720 return (&pdpe[pmap_pdpe_index(va)]);
723 /* Return a pointer to the PDP slot that corresponds to a VA */
724 static __inline pdp_entry_t *
725 pmap_pdpe(pmap_t pmap, vm_offset_t va)
730 PG_V = pmap_valid_bit(pmap);
731 pml4e = pmap_pml4e(pmap, va);
732 if ((*pml4e & PG_V) == 0)
734 return (pmap_pml4e_to_pdpe(pml4e, va));
737 /* Return a pointer to the PD slot that corresponds to a VA */
738 static __inline pd_entry_t *
739 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
743 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
744 return (&pde[pmap_pde_index(va)]);
747 /* Return a pointer to the PD slot that corresponds to a VA */
748 static __inline pd_entry_t *
749 pmap_pde(pmap_t pmap, vm_offset_t va)
754 PG_V = pmap_valid_bit(pmap);
755 pdpe = pmap_pdpe(pmap, va);
756 if (pdpe == NULL || (*pdpe & PG_V) == 0)
758 return (pmap_pdpe_to_pde(pdpe, va));
761 /* Return a pointer to the PT slot that corresponds to a VA */
762 static __inline pt_entry_t *
763 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
767 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
768 return (&pte[pmap_pte_index(va)]);
771 /* Return a pointer to the PT slot that corresponds to a VA */
772 static __inline pt_entry_t *
773 pmap_pte(pmap_t pmap, vm_offset_t va)
778 PG_V = pmap_valid_bit(pmap);
779 pde = pmap_pde(pmap, va);
780 if (pde == NULL || (*pde & PG_V) == 0)
782 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
783 return ((pt_entry_t *)pde);
784 return (pmap_pde_to_pte(pde, va));
788 pmap_resident_count_inc(pmap_t pmap, int count)
791 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
792 pmap->pm_stats.resident_count += count;
796 pmap_resident_count_dec(pmap_t pmap, int count)
799 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
800 KASSERT(pmap->pm_stats.resident_count >= count,
801 ("pmap %p resident count underflow %ld %d", pmap,
802 pmap->pm_stats.resident_count, count));
803 pmap->pm_stats.resident_count -= count;
806 PMAP_INLINE pt_entry_t *
807 vtopte(vm_offset_t va)
809 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
811 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
813 return (PTmap + ((va >> PAGE_SHIFT) & mask));
816 static __inline pd_entry_t *
817 vtopde(vm_offset_t va)
819 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
821 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
823 return (PDmap + ((va >> PDRSHIFT) & mask));
827 allocpages(vm_paddr_t *firstaddr, int n)
832 bzero((void *)ret, n * PAGE_SIZE);
833 *firstaddr += n * PAGE_SIZE;
837 CTASSERT(powerof2(NDMPML4E));
839 /* number of kernel PDP slots */
840 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
843 nkpt_init(vm_paddr_t addr)
850 pt_pages = howmany(addr, 1 << PDRSHIFT);
851 pt_pages += NKPDPE(pt_pages);
854 * Add some slop beyond the bare minimum required for bootstrapping
857 * This is quite important when allocating KVA for kernel modules.
858 * The modules are required to be linked in the negative 2GB of
859 * the address space. If we run out of KVA in this region then
860 * pmap_growkernel() will need to allocate page table pages to map
861 * the entire 512GB of KVA space which is an unnecessary tax on
864 * Secondly, device memory mapped as part of setting up the low-
865 * level console(s) is taken from KVA, starting at virtual_avail.
866 * This is because cninit() is called after pmap_bootstrap() but
867 * before vm_init() and pmap_init(). 20MB for a frame buffer is
870 pt_pages += 32; /* 64MB additional slop. */
876 * Returns the proper write/execute permission for a physical page that is
877 * part of the initial boot allocations.
879 * If the page has kernel text, it is marked as read-only. If the page has
880 * kernel read-only data, it is marked as read-only/not-executable. If the
881 * page has only read-write data, it is marked as read-write/not-executable.
882 * If the page is below/above the kernel range, it is marked as read-write.
884 * This function operates on 2M pages, since we map the kernel space that
887 * Note that this doesn't currently provide any protection for modules.
889 static inline pt_entry_t
890 bootaddr_rwx(vm_paddr_t pa)
894 * Everything in the same 2M page as the start of the kernel
895 * should be static. On the other hand, things in the same 2M
896 * page as the end of the kernel could be read-write/executable,
897 * as the kernel image is not guaranteed to end on a 2M boundary.
899 if (pa < trunc_2mpage(btext - KERNBASE) ||
900 pa >= trunc_2mpage(_end - KERNBASE))
903 * The linker should ensure that the read-only and read-write
904 * portions don't share the same 2M page, so this shouldn't
905 * impact read-only data. However, in any case, any page with
906 * read-write data needs to be read-write.
908 if (pa >= trunc_2mpage(brwsection - KERNBASE))
909 return (X86_PG_RW | pg_nx);
911 * Mark any 2M page containing kernel text as read-only. Mark
912 * other pages with read-only data as read-only and not executable.
913 * (It is likely a small portion of the read-only data section will
914 * be marked as read-only, but executable. This should be acceptable
915 * since the read-only protection will keep the data from changing.)
916 * Note that fixups to the .text section will still work until we
919 if (pa < round_2mpage(etext - KERNBASE))
925 create_pagetables(vm_paddr_t *firstaddr)
927 int i, j, ndm1g, nkpdpe, nkdmpde;
932 uint64_t DMPDkernphys;
934 /* Allocate page table pages for the direct map */
935 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
936 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
938 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
939 if (ndmpdpphys > NDMPML4E) {
941 * Each NDMPML4E allows 512 GB, so limit to that,
942 * and then readjust ndmpdp and ndmpdpphys.
944 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
945 Maxmem = atop(NDMPML4E * NBPML4);
946 ndmpdpphys = NDMPML4E;
947 ndmpdp = NDMPML4E * NPDEPG;
949 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
951 if ((amd_feature & AMDID_PAGE1GB) != 0) {
953 * Calculate the number of 1G pages that will fully fit in
956 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
959 * Allocate 2M pages for the kernel. These will be used in
960 * place of the first one or more 1G pages from ndm1g.
962 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
963 DMPDkernphys = allocpages(firstaddr, nkdmpde);
966 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
967 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
970 KPML4phys = allocpages(firstaddr, 1);
971 KPDPphys = allocpages(firstaddr, NKPML4E);
974 * Allocate the initial number of kernel page table pages required to
975 * bootstrap. We defer this until after all memory-size dependent
976 * allocations are done (e.g. direct map), so that we don't have to
977 * build in too much slop in our estimate.
979 * Note that when NKPML4E > 1, we have an empty page underneath
980 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
981 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
983 nkpt_init(*firstaddr);
984 nkpdpe = NKPDPE(nkpt);
986 KPTphys = allocpages(firstaddr, nkpt);
987 KPDphys = allocpages(firstaddr, nkpdpe);
989 /* Fill in the underlying page table pages */
990 /* XXX not fully used, underneath 2M pages */
991 pt_p = (pt_entry_t *)KPTphys;
992 for (i = 0; ptoa(i) < *firstaddr; i++)
993 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
995 /* Now map the page tables at their location within PTmap */
996 pd_p = (pd_entry_t *)KPDphys;
997 for (i = 0; i < nkpt; i++)
998 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1000 /* Map from zero to end of allocations under 2M pages */
1001 /* This replaces some of the KPTphys entries above */
1002 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1003 /* Preset PG_M and PG_A because demotion expects it. */
1004 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1005 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1008 * Because we map the physical blocks in 2M pages, adjust firstaddr
1009 * to record the physical blocks we've actually mapped into kernel
1010 * virtual address space.
1012 *firstaddr = round_2mpage(*firstaddr);
1014 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1015 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1016 for (i = 0; i < nkpdpe; i++)
1017 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1020 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1021 * the end of physical memory is not aligned to a 1GB page boundary,
1022 * then the residual physical memory is mapped with 2MB pages. Later,
1023 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1024 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1025 * that are partially used.
1027 pd_p = (pd_entry_t *)DMPDphys;
1028 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1029 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1030 /* Preset PG_M and PG_A because demotion expects it. */
1031 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1032 X86_PG_M | X86_PG_A | pg_nx;
1034 pdp_p = (pdp_entry_t *)DMPDPphys;
1035 for (i = 0; i < ndm1g; i++) {
1036 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1037 /* Preset PG_M and PG_A because demotion expects it. */
1038 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1039 X86_PG_M | X86_PG_A | pg_nx;
1041 for (j = 0; i < ndmpdp; i++, j++) {
1042 pdp_p[i] = DMPDphys + ptoa(j);
1043 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1047 * Instead of using a 1G page for the memory containing the kernel,
1048 * use 2M pages with appropriate permissions. (If using 1G pages,
1049 * this will partially overwrite the PDPEs above.)
1052 pd_p = (pd_entry_t *)DMPDkernphys;
1053 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1054 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1055 X86_PG_M | X86_PG_A | pg_nx |
1056 bootaddr_rwx(i << PDRSHIFT);
1057 for (i = 0; i < nkdmpde; i++)
1058 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1062 /* And recursively map PML4 to itself in order to get PTmap */
1063 p4_p = (pml4_entry_t *)KPML4phys;
1064 p4_p[PML4PML4I] = KPML4phys;
1065 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1067 /* Connect the Direct Map slot(s) up to the PML4. */
1068 for (i = 0; i < ndmpdpphys; i++) {
1069 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1070 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1073 /* Connect the KVA slots up to the PML4 */
1074 for (i = 0; i < NKPML4E; i++) {
1075 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1076 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1081 * Bootstrap the system enough to run with virtual memory.
1083 * On amd64 this is called after mapping has already been enabled
1084 * and just syncs the pmap module with what has already been done.
1085 * [We can't call it easily with mapping off since the kernel is not
1086 * mapped with PA == VA, hence we would have to relocate every address
1087 * from the linked base (virtual) address "KERNBASE" to the actual
1088 * (physical) address starting relative to 0]
1091 pmap_bootstrap(vm_paddr_t *firstaddr)
1098 KERNend = *firstaddr;
1104 * Create an initial set of page tables to run the kernel in.
1106 create_pagetables(firstaddr);
1109 * Add a physical memory segment (vm_phys_seg) corresponding to the
1110 * preallocated kernel page table pages so that vm_page structures
1111 * representing these pages will be created. The vm_page structures
1112 * are required for promotion of the corresponding kernel virtual
1113 * addresses to superpage mappings.
1115 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1117 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1119 virtual_end = VM_MAX_KERNEL_ADDRESS;
1123 * Enable PG_G global pages, then switch to the kernel page
1124 * table from the bootstrap page table. After the switch, it
1125 * is possible to enable SMEP and SMAP since PG_U bits are
1131 load_cr3(KPML4phys);
1132 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1134 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1139 * Initialize the kernel pmap (which is statically allocated).
1141 PMAP_LOCK_INIT(kernel_pmap);
1142 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1143 kernel_pmap->pm_cr3 = KPML4phys;
1144 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1145 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1146 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1147 kernel_pmap->pm_flags = pmap_flags;
1150 * Initialize the TLB invalidations generation number lock.
1152 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1155 * Reserve some special page table entries/VA space for temporary
1158 #define SYSMAP(c, p, v, n) \
1159 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1165 * Crashdump maps. The first page is reused as CMAP1 for the
1168 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1169 CADDR1 = crashdumpmap;
1174 * Initialize the PAT MSR.
1175 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1176 * side-effect, invalidates stale PG_G TLB entries that might
1177 * have been created in our pre-boot environment.
1181 /* Initialize TLB Context Id. */
1182 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
1183 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
1184 /* Check for INVPCID support */
1185 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
1187 for (i = 0; i < MAXCPU; i++) {
1188 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1189 kernel_pmap->pm_pcids[i].pm_gen = 1;
1191 PCPU_SET(pcid_next, PMAP_PCID_KERN + 1);
1192 PCPU_SET(pcid_gen, 1);
1194 * pcpu area for APs is zeroed during AP startup.
1195 * pc_pcid_next and pc_pcid_gen are initialized by AP
1196 * during pcpu setup.
1198 load_cr4(rcr4() | CR4_PCIDE);
1200 pmap_pcid_enabled = 0;
1205 * Setup the PAT MSR.
1210 int pat_table[PAT_INDEX_SIZE];
1215 /* Bail if this CPU doesn't implement PAT. */
1216 if ((cpu_feature & CPUID_PAT) == 0)
1219 /* Set default PAT index table. */
1220 for (i = 0; i < PAT_INDEX_SIZE; i++)
1222 pat_table[PAT_WRITE_BACK] = 0;
1223 pat_table[PAT_WRITE_THROUGH] = 1;
1224 pat_table[PAT_UNCACHEABLE] = 3;
1225 pat_table[PAT_WRITE_COMBINING] = 3;
1226 pat_table[PAT_WRITE_PROTECTED] = 3;
1227 pat_table[PAT_UNCACHED] = 3;
1229 /* Initialize default PAT entries. */
1230 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1231 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1232 PAT_VALUE(2, PAT_UNCACHED) |
1233 PAT_VALUE(3, PAT_UNCACHEABLE) |
1234 PAT_VALUE(4, PAT_WRITE_BACK) |
1235 PAT_VALUE(5, PAT_WRITE_THROUGH) |
1236 PAT_VALUE(6, PAT_UNCACHED) |
1237 PAT_VALUE(7, PAT_UNCACHEABLE);
1241 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1242 * Program 5 and 6 as WP and WC.
1243 * Leave 4 and 7 as WB and UC.
1245 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
1246 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1247 PAT_VALUE(6, PAT_WRITE_COMBINING);
1248 pat_table[PAT_UNCACHED] = 2;
1249 pat_table[PAT_WRITE_PROTECTED] = 5;
1250 pat_table[PAT_WRITE_COMBINING] = 6;
1253 * Just replace PAT Index 2 with WC instead of UC-.
1255 pat_msr &= ~PAT_MASK(2);
1256 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
1257 pat_table[PAT_WRITE_COMBINING] = 2;
1262 load_cr4(cr4 & ~CR4_PGE);
1264 /* Disable caches (CD = 1, NW = 0). */
1266 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1268 /* Flushes caches and TLBs. */
1272 /* Update PAT and index table. */
1273 wrmsr(MSR_PAT, pat_msr);
1274 for (i = 0; i < PAT_INDEX_SIZE; i++)
1275 pat_index[i] = pat_table[i];
1277 /* Flush caches and TLBs again. */
1281 /* Restore caches and PGE. */
1287 * Initialize a vm_page's machine-dependent fields.
1290 pmap_page_init(vm_page_t m)
1293 TAILQ_INIT(&m->md.pv_list);
1294 m->md.pat_mode = PAT_WRITE_BACK;
1298 * Initialize the pmap module.
1299 * Called by vm_init, to initialize any structures that the pmap
1300 * system needs to map virtual memory.
1305 struct pmap_preinit_mapping *ppim;
1308 int error, i, pv_npg, ret, skz63;
1310 /* Detect bare-metal Skylake Server and Skylake-X. */
1311 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1312 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1314 * Skylake-X errata SKZ63. Processor May Hang When
1315 * Executing Code In an HLE Transaction Region between
1316 * 40000000H and 403FFFFFH.
1318 * Mark the pages in the range as preallocated. It
1319 * seems to be impossible to distinguish between
1320 * Skylake Server and Skylake X.
1323 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1326 printf("SKZ63: skipping 4M RAM starting "
1327 "at physical 1G\n");
1328 for (i = 0; i < atop(0x400000); i++) {
1329 ret = vm_page_blacklist_add(0x40000000 +
1331 if (!ret && bootverbose)
1332 printf("page at %#lx already used\n",
1333 0x40000000 + ptoa(i));
1339 * Initialize the vm page array entries for the kernel pmap's
1342 PMAP_LOCK(kernel_pmap);
1343 for (i = 0; i < nkpt; i++) {
1344 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1345 KASSERT(mpte >= vm_page_array &&
1346 mpte < &vm_page_array[vm_page_array_size],
1347 ("pmap_init: page table page is out of range"));
1348 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1349 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1350 mpte->wire_count = 1;
1351 if (i << PDRSHIFT < KERNend &&
1352 pmap_insert_pt_page(kernel_pmap, mpte))
1353 panic("pmap_init: pmap_insert_pt_page failed");
1355 PMAP_UNLOCK(kernel_pmap);
1359 * If the kernel is running on a virtual machine, then it must assume
1360 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1361 * be prepared for the hypervisor changing the vendor and family that
1362 * are reported by CPUID. Consequently, the workaround for AMD Family
1363 * 10h Erratum 383 is enabled if the processor's feature set does not
1364 * include at least one feature that is only supported by older Intel
1365 * or newer AMD processors.
1367 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1368 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1369 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1371 workaround_erratum383 = 1;
1374 * Are large page mappings enabled?
1376 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1377 if (pg_ps_enabled) {
1378 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1379 ("pmap_init: can't assign to pagesizes[1]"));
1380 pagesizes[1] = NBPDR;
1384 * Initialize the pv chunk list mutex.
1386 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1389 * Initialize the pool of pv list locks.
1391 for (i = 0; i < NPV_LIST_LOCKS; i++)
1392 rw_init(&pv_list_locks[i], "pmap pv list");
1395 * Calculate the size of the pv head table for superpages.
1397 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1400 * Allocate memory for the pv head table for superpages.
1402 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1404 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1406 for (i = 0; i < pv_npg; i++)
1407 TAILQ_INIT(&pv_table[i].pv_list);
1408 TAILQ_INIT(&pv_dummy.pv_list);
1410 pmap_initialized = 1;
1411 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1412 ppim = pmap_preinit_mapping + i;
1415 /* Make the direct map consistent */
1416 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1417 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1418 ppim->sz, ppim->mode);
1422 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1423 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1426 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1427 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1428 (vmem_addr_t *)&qframe);
1430 panic("qframe allocation failed");
1433 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1434 "2MB page mapping counters");
1436 static u_long pmap_pde_demotions;
1437 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1438 &pmap_pde_demotions, 0, "2MB page demotions");
1440 static u_long pmap_pde_mappings;
1441 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1442 &pmap_pde_mappings, 0, "2MB page mappings");
1444 static u_long pmap_pde_p_failures;
1445 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1446 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1448 static u_long pmap_pde_promotions;
1449 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1450 &pmap_pde_promotions, 0, "2MB page promotions");
1452 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1453 "1GB page mapping counters");
1455 static u_long pmap_pdpe_demotions;
1456 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1457 &pmap_pdpe_demotions, 0, "1GB page demotions");
1459 /***************************************************
1460 * Low level helper routines.....
1461 ***************************************************/
1464 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1466 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1468 switch (pmap->pm_type) {
1471 /* Verify that both PAT bits are not set at the same time */
1472 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1473 ("Invalid PAT bits in entry %#lx", entry));
1475 /* Swap the PAT bits if one of them is set */
1476 if ((entry & x86_pat_bits) != 0)
1477 entry ^= x86_pat_bits;
1481 * Nothing to do - the memory attributes are represented
1482 * the same way for regular pages and superpages.
1486 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1493 * Determine the appropriate bits to set in a PTE or PDE for a specified
1497 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1499 int cache_bits, pat_flag, pat_idx;
1501 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1502 panic("Unknown caching mode %d\n", mode);
1504 switch (pmap->pm_type) {
1507 /* The PAT bit is different for PTE's and PDE's. */
1508 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1510 /* Map the caching mode to a PAT index. */
1511 pat_idx = pat_index[mode];
1513 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1516 cache_bits |= pat_flag;
1518 cache_bits |= PG_NC_PCD;
1520 cache_bits |= PG_NC_PWT;
1524 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1528 panic("unsupported pmap type %d", pmap->pm_type);
1531 return (cache_bits);
1535 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1539 switch (pmap->pm_type) {
1542 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1545 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1548 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1555 pmap_ps_enabled(pmap_t pmap)
1558 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1562 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1565 switch (pmap->pm_type) {
1572 * This is a little bogus since the generation number is
1573 * supposed to be bumped up when a region of the address
1574 * space is invalidated in the page tables.
1576 * In this case the old PDE entry is valid but yet we want
1577 * to make sure that any mappings using the old entry are
1578 * invalidated in the TLB.
1580 * The reason this works as expected is because we rendezvous
1581 * "all" host cpus and force any vcpu context to exit as a
1584 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1587 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1589 pde_store(pde, newpde);
1593 * After changing the page size for the specified virtual address in the page
1594 * table, flush the corresponding entries from the processor's TLB. Only the
1595 * calling processor's TLB is affected.
1597 * The calling thread must be pinned to a processor.
1600 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1604 if (pmap_type_guest(pmap))
1607 KASSERT(pmap->pm_type == PT_X86,
1608 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1610 PG_G = pmap_global_bit(pmap);
1612 if ((newpde & PG_PS) == 0)
1613 /* Demotion: flush a specific 2MB page mapping. */
1615 else if ((newpde & PG_G) == 0)
1617 * Promotion: flush every 4KB page mapping from the TLB
1618 * because there are too many to flush individually.
1623 * Promotion: flush every 4KB page mapping from the TLB,
1624 * including any global (PG_G) mappings.
1632 * For SMP, these functions have to use the IPI mechanism for coherence.
1634 * N.B.: Before calling any of the following TLB invalidation functions,
1635 * the calling processor must ensure that all stores updating a non-
1636 * kernel page table are globally performed. Otherwise, another
1637 * processor could cache an old, pre-update entry without being
1638 * invalidated. This can happen one of two ways: (1) The pmap becomes
1639 * active on another processor after its pm_active field is checked by
1640 * one of the following functions but before a store updating the page
1641 * table is globally performed. (2) The pmap becomes active on another
1642 * processor before its pm_active field is checked but due to
1643 * speculative loads one of the following functions stills reads the
1644 * pmap as inactive on the other processor.
1646 * The kernel page table is exempt because its pm_active field is
1647 * immutable. The kernel page table is always active on every
1652 * Interrupt the cpus that are executing in the guest context.
1653 * This will force the vcpu to exit and the cached EPT mappings
1654 * will be invalidated by the host before the next vmresume.
1656 static __inline void
1657 pmap_invalidate_ept(pmap_t pmap)
1662 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1663 ("pmap_invalidate_ept: absurd pm_active"));
1666 * The TLB mappings associated with a vcpu context are not
1667 * flushed each time a different vcpu is chosen to execute.
1669 * This is in contrast with a process's vtop mappings that
1670 * are flushed from the TLB on each context switch.
1672 * Therefore we need to do more than just a TLB shootdown on
1673 * the active cpus in 'pmap->pm_active'. To do this we keep
1674 * track of the number of invalidations performed on this pmap.
1676 * Each vcpu keeps a cache of this counter and compares it
1677 * just before a vmresume. If the counter is out-of-date an
1678 * invept will be done to flush stale mappings from the TLB.
1680 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1683 * Force the vcpu to exit and trap back into the hypervisor.
1685 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1686 ipi_selected(pmap->pm_active, ipinum);
1691 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1694 struct invpcid_descr d;
1695 uint64_t kcr3, ucr3;
1699 if (pmap_type_guest(pmap)) {
1700 pmap_invalidate_ept(pmap);
1704 KASSERT(pmap->pm_type == PT_X86,
1705 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1708 if (pmap == kernel_pmap) {
1712 cpuid = PCPU_GET(cpuid);
1713 if (pmap == PCPU_GET(curpmap)) {
1715 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1717 * Disable context switching. pm_pcid
1718 * is recalculated on switch, which
1719 * might make us use wrong pcid below.
1722 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1724 if (invpcid_works) {
1725 d.pcid = pcid | PMAP_PCID_USER_PT;
1728 invpcid(&d, INVPCID_ADDR);
1730 kcr3 = pmap->pm_cr3 | pcid |
1732 ucr3 = pmap->pm_ucr3 | pcid |
1733 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1734 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1738 } else if (pmap_pcid_enabled)
1739 pmap->pm_pcids[cpuid].pm_gen = 0;
1740 if (pmap_pcid_enabled) {
1743 pmap->pm_pcids[i].pm_gen = 0;
1747 * The fence is between stores to pm_gen and the read of
1748 * the pm_active mask. We need to ensure that it is
1749 * impossible for us to miss the bit update in pm_active
1750 * and simultaneously observe a non-zero pm_gen in
1751 * pmap_activate_sw(), otherwise TLB update is missed.
1752 * Without the fence, IA32 allows such an outcome.
1753 * Note that pm_active is updated by a locked operation,
1754 * which provides the reciprocal fence.
1756 atomic_thread_fence_seq_cst();
1758 mask = &pmap->pm_active;
1760 smp_masked_invlpg(*mask, va, pmap);
1764 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1765 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1768 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1771 struct invpcid_descr d;
1773 uint64_t kcr3, ucr3;
1777 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1778 pmap_invalidate_all(pmap);
1782 if (pmap_type_guest(pmap)) {
1783 pmap_invalidate_ept(pmap);
1787 KASSERT(pmap->pm_type == PT_X86,
1788 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1791 cpuid = PCPU_GET(cpuid);
1792 if (pmap == kernel_pmap) {
1793 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1797 if (pmap == PCPU_GET(curpmap)) {
1798 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1800 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1802 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1803 if (invpcid_works) {
1804 d.pcid = pcid | PMAP_PCID_USER_PT;
1807 for (; d.addr < eva; d.addr +=
1809 invpcid(&d, INVPCID_ADDR);
1811 kcr3 = pmap->pm_cr3 | pcid |
1813 ucr3 = pmap->pm_ucr3 | pcid |
1814 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1815 pmap_pti_pcid_invlrng(ucr3, kcr3, sva,
1820 } else if (pmap_pcid_enabled) {
1821 pmap->pm_pcids[cpuid].pm_gen = 0;
1823 if (pmap_pcid_enabled) {
1826 pmap->pm_pcids[i].pm_gen = 0;
1828 /* See the comment in pmap_invalidate_page(). */
1829 atomic_thread_fence_seq_cst();
1831 mask = &pmap->pm_active;
1833 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1838 pmap_invalidate_all(pmap_t pmap)
1841 struct invpcid_descr d;
1842 uint64_t kcr3, ucr3;
1846 if (pmap_type_guest(pmap)) {
1847 pmap_invalidate_ept(pmap);
1851 KASSERT(pmap->pm_type == PT_X86,
1852 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1855 if (pmap == kernel_pmap) {
1856 if (pmap_pcid_enabled && invpcid_works) {
1857 bzero(&d, sizeof(d));
1858 invpcid(&d, INVPCID_CTXGLOB);
1864 cpuid = PCPU_GET(cpuid);
1865 if (pmap == PCPU_GET(curpmap)) {
1866 if (pmap_pcid_enabled) {
1868 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1869 if (invpcid_works) {
1873 invpcid(&d, INVPCID_CTX);
1874 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1875 d.pcid |= PMAP_PCID_USER_PT;
1876 invpcid(&d, INVPCID_CTX);
1879 kcr3 = pmap->pm_cr3 | pcid;
1880 ucr3 = pmap->pm_ucr3;
1881 if (ucr3 != PMAP_NO_CR3) {
1882 ucr3 |= pcid | PMAP_PCID_USER_PT;
1883 pmap_pti_pcid_invalidate(ucr3,
1893 } else if (pmap_pcid_enabled) {
1894 pmap->pm_pcids[cpuid].pm_gen = 0;
1896 if (pmap_pcid_enabled) {
1899 pmap->pm_pcids[i].pm_gen = 0;
1901 /* See the comment in pmap_invalidate_page(). */
1902 atomic_thread_fence_seq_cst();
1904 mask = &pmap->pm_active;
1906 smp_masked_invltlb(*mask, pmap);
1911 pmap_invalidate_cache(void)
1921 cpuset_t invalidate; /* processors that invalidate their TLB */
1926 u_int store; /* processor that updates the PDE */
1930 pmap_update_pde_action(void *arg)
1932 struct pde_action *act = arg;
1934 if (act->store == PCPU_GET(cpuid))
1935 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1939 pmap_update_pde_teardown(void *arg)
1941 struct pde_action *act = arg;
1943 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1944 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1948 * Change the page size for the specified virtual address in a way that
1949 * prevents any possibility of the TLB ever having two entries that map the
1950 * same virtual address using different page sizes. This is the recommended
1951 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1952 * machine check exception for a TLB state that is improperly diagnosed as a
1956 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1958 struct pde_action act;
1959 cpuset_t active, other_cpus;
1963 cpuid = PCPU_GET(cpuid);
1964 other_cpus = all_cpus;
1965 CPU_CLR(cpuid, &other_cpus);
1966 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1969 active = pmap->pm_active;
1971 if (CPU_OVERLAP(&active, &other_cpus)) {
1973 act.invalidate = active;
1977 act.newpde = newpde;
1978 CPU_SET(cpuid, &active);
1979 smp_rendezvous_cpus(active,
1980 smp_no_rendezvous_barrier, pmap_update_pde_action,
1981 pmap_update_pde_teardown, &act);
1983 pmap_update_pde_store(pmap, pde, newpde);
1984 if (CPU_ISSET(cpuid, &active))
1985 pmap_update_pde_invalidate(pmap, va, newpde);
1991 * Normal, non-SMP, invalidation functions.
1994 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1996 struct invpcid_descr d;
1997 uint64_t kcr3, ucr3;
2000 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2004 KASSERT(pmap->pm_type == PT_X86,
2005 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2007 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2009 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2010 pmap->pm_ucr3 != PMAP_NO_CR3) {
2012 pcid = pmap->pm_pcids[0].pm_pcid;
2013 if (invpcid_works) {
2014 d.pcid = pcid | PMAP_PCID_USER_PT;
2017 invpcid(&d, INVPCID_ADDR);
2019 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2020 ucr3 = pmap->pm_ucr3 | pcid |
2021 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2022 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2026 } else if (pmap_pcid_enabled)
2027 pmap->pm_pcids[0].pm_gen = 0;
2031 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2033 struct invpcid_descr d;
2035 uint64_t kcr3, ucr3;
2037 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2041 KASSERT(pmap->pm_type == PT_X86,
2042 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2044 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2045 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2047 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2048 pmap->pm_ucr3 != PMAP_NO_CR3) {
2050 if (invpcid_works) {
2051 d.pcid = pmap->pm_pcids[0].pm_pcid |
2055 for (; d.addr < eva; d.addr += PAGE_SIZE)
2056 invpcid(&d, INVPCID_ADDR);
2058 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2059 pm_pcid | CR3_PCID_SAVE;
2060 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2061 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2062 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2066 } else if (pmap_pcid_enabled) {
2067 pmap->pm_pcids[0].pm_gen = 0;
2072 pmap_invalidate_all(pmap_t pmap)
2074 struct invpcid_descr d;
2075 uint64_t kcr3, ucr3;
2077 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2081 KASSERT(pmap->pm_type == PT_X86,
2082 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2084 if (pmap == kernel_pmap) {
2085 if (pmap_pcid_enabled && invpcid_works) {
2086 bzero(&d, sizeof(d));
2087 invpcid(&d, INVPCID_CTXGLOB);
2091 } else if (pmap == PCPU_GET(curpmap)) {
2092 if (pmap_pcid_enabled) {
2094 if (invpcid_works) {
2095 d.pcid = pmap->pm_pcids[0].pm_pcid;
2098 invpcid(&d, INVPCID_CTX);
2099 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2100 d.pcid |= PMAP_PCID_USER_PT;
2101 invpcid(&d, INVPCID_CTX);
2104 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2105 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2106 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2107 0].pm_pcid | PMAP_PCID_USER_PT;
2108 pmap_pti_pcid_invalidate(ucr3, kcr3);
2116 } else if (pmap_pcid_enabled) {
2117 pmap->pm_pcids[0].pm_gen = 0;
2122 pmap_invalidate_cache(void)
2129 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2132 pmap_update_pde_store(pmap, pde, newpde);
2133 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2134 pmap_update_pde_invalidate(pmap, va, newpde);
2136 pmap->pm_pcids[0].pm_gen = 0;
2141 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2145 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2146 * by a promotion that did not invalidate the 512 4KB page mappings
2147 * that might exist in the TLB. Consequently, at this point, the TLB
2148 * may hold both 4KB and 2MB page mappings for the address range [va,
2149 * va + NBPDR). Therefore, the entire range must be invalidated here.
2150 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2151 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2152 * single INVLPG suffices to invalidate the 2MB page mapping from the
2155 if ((pde & PG_PROMOTED) != 0)
2156 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2158 pmap_invalidate_page(pmap, va);
2161 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2164 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
2168 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2170 KASSERT((sva & PAGE_MASK) == 0,
2171 ("pmap_invalidate_cache_range: sva not page-aligned"));
2172 KASSERT((eva & PAGE_MASK) == 0,
2173 ("pmap_invalidate_cache_range: eva not page-aligned"));
2176 if ((cpu_feature & CPUID_SS) != 0 && !force)
2177 ; /* If "Self Snoop" is supported and allowed, do nothing. */
2178 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
2179 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2181 * XXX: Some CPUs fault, hang, or trash the local APIC
2182 * registers if we use CLFLUSH on the local APIC
2183 * range. The local APIC is always uncached, so we
2184 * don't need to flush for that range anyway.
2186 if (pmap_kextract(sva) == lapic_paddr)
2190 * Otherwise, do per-cache line flush. Use the sfence
2191 * instruction to insure that previous stores are
2192 * included in the write-back. The processor
2193 * propagates flush to other processors in the cache
2197 for (; sva < eva; sva += cpu_clflush_line_size)
2200 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
2201 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2202 if (pmap_kextract(sva) == lapic_paddr)
2205 * Writes are ordered by CLFLUSH on Intel CPUs.
2207 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2209 for (; sva < eva; sva += cpu_clflush_line_size)
2211 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2216 * No targeted cache flush methods are supported by CPU,
2217 * or the supplied range is bigger than 2MB.
2218 * Globally invalidate cache.
2220 pmap_invalidate_cache();
2225 * Remove the specified set of pages from the data and instruction caches.
2227 * In contrast to pmap_invalidate_cache_range(), this function does not
2228 * rely on the CPU's self-snoop feature, because it is intended for use
2229 * when moving pages into a different cache domain.
2232 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2234 vm_offset_t daddr, eva;
2238 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2239 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2240 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2241 pmap_invalidate_cache();
2245 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2247 for (i = 0; i < count; i++) {
2248 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2249 eva = daddr + PAGE_SIZE;
2250 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2259 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2265 * Routine: pmap_extract
2267 * Extract the physical page address associated
2268 * with the given map/virtual_address pair.
2271 pmap_extract(pmap_t pmap, vm_offset_t va)
2275 pt_entry_t *pte, PG_V;
2279 PG_V = pmap_valid_bit(pmap);
2281 pdpe = pmap_pdpe(pmap, va);
2282 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2283 if ((*pdpe & PG_PS) != 0)
2284 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2286 pde = pmap_pdpe_to_pde(pdpe, va);
2287 if ((*pde & PG_V) != 0) {
2288 if ((*pde & PG_PS) != 0) {
2289 pa = (*pde & PG_PS_FRAME) |
2292 pte = pmap_pde_to_pte(pde, va);
2293 pa = (*pte & PG_FRAME) |
2304 * Routine: pmap_extract_and_hold
2306 * Atomically extract and hold the physical page
2307 * with the given pmap and virtual address pair
2308 * if that mapping permits the given protection.
2311 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2313 pd_entry_t pde, *pdep;
2314 pt_entry_t pte, PG_RW, PG_V;
2320 PG_RW = pmap_rw_bit(pmap);
2321 PG_V = pmap_valid_bit(pmap);
2324 pdep = pmap_pde(pmap, va);
2325 if (pdep != NULL && (pde = *pdep)) {
2327 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2328 if (vm_page_pa_tryrelock(pmap, (pde &
2329 PG_PS_FRAME) | (va & PDRMASK), &pa))
2331 m = PHYS_TO_VM_PAGE(pa);
2334 pte = *pmap_pde_to_pte(pdep, va);
2336 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2337 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2340 m = PHYS_TO_VM_PAGE(pa);
2352 pmap_kextract(vm_offset_t va)
2357 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2358 pa = DMAP_TO_PHYS(va);
2362 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2365 * Beware of a concurrent promotion that changes the
2366 * PDE at this point! For example, vtopte() must not
2367 * be used to access the PTE because it would use the
2368 * new PDE. It is, however, safe to use the old PDE
2369 * because the page table page is preserved by the
2372 pa = *pmap_pde_to_pte(&pde, va);
2373 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2379 /***************************************************
2380 * Low level mapping routines.....
2381 ***************************************************/
2384 * Add a wired page to the kva.
2385 * Note: not SMP coherent.
2388 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2393 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2396 static __inline void
2397 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2403 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2404 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2408 * Remove a page from the kernel pagetables.
2409 * Note: not SMP coherent.
2412 pmap_kremove(vm_offset_t va)
2421 * Used to map a range of physical addresses into kernel
2422 * virtual address space.
2424 * The value passed in '*virt' is a suggested virtual address for
2425 * the mapping. Architectures which can support a direct-mapped
2426 * physical to virtual region can return the appropriate address
2427 * within that region, leaving '*virt' unchanged. Other
2428 * architectures should map the pages starting at '*virt' and
2429 * update '*virt' with the first usable address after the mapped
2433 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2435 return PHYS_TO_DMAP(start);
2440 * Add a list of wired pages to the kva
2441 * this routine is only used for temporary
2442 * kernel mappings that do not need to have
2443 * page modification or references recorded.
2444 * Note that old mappings are simply written
2445 * over. The page *must* be wired.
2446 * Note: SMP coherent. Uses a ranged shootdown IPI.
2449 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2451 pt_entry_t *endpte, oldpte, pa, *pte;
2457 endpte = pte + count;
2458 while (pte < endpte) {
2460 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2461 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2462 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2464 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2468 if (__predict_false((oldpte & X86_PG_V) != 0))
2469 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2474 * This routine tears out page mappings from the
2475 * kernel -- it is meant only for temporary mappings.
2476 * Note: SMP coherent. Uses a ranged shootdown IPI.
2479 pmap_qremove(vm_offset_t sva, int count)
2484 while (count-- > 0) {
2485 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2489 pmap_invalidate_range(kernel_pmap, sva, va);
2492 /***************************************************
2493 * Page table page management routines.....
2494 ***************************************************/
2496 * Schedule the specified unused page table page to be freed. Specifically,
2497 * add the page to the specified list of pages that will be released to the
2498 * physical memory manager after the TLB has been updated.
2500 static __inline void
2501 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2502 boolean_t set_PG_ZERO)
2506 m->flags |= PG_ZERO;
2508 m->flags &= ~PG_ZERO;
2509 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2513 * Inserts the specified page table page into the specified pmap's collection
2514 * of idle page table pages. Each of a pmap's page table pages is responsible
2515 * for mapping a distinct range of virtual addresses. The pmap's collection is
2516 * ordered by this virtual address range.
2519 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2522 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2523 return (vm_radix_insert(&pmap->pm_root, mpte));
2527 * Removes the page table page mapping the specified virtual address from the
2528 * specified pmap's collection of idle page table pages, and returns it.
2529 * Otherwise, returns NULL if there is no page table page corresponding to the
2530 * specified virtual address.
2532 static __inline vm_page_t
2533 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2536 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2537 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2541 * Decrements a page table page's wire count, which is used to record the
2542 * number of valid page table entries within the page. If the wire count
2543 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2544 * page table page was unmapped and FALSE otherwise.
2546 static inline boolean_t
2547 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2551 if (m->wire_count == 0) {
2552 _pmap_unwire_ptp(pmap, va, m, free);
2559 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2562 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2564 * unmap the page table page
2566 if (m->pindex >= (NUPDE + NUPDPE)) {
2569 pml4 = pmap_pml4e(pmap, va);
2571 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2572 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2575 } else if (m->pindex >= NUPDE) {
2578 pdp = pmap_pdpe(pmap, va);
2583 pd = pmap_pde(pmap, va);
2586 pmap_resident_count_dec(pmap, 1);
2587 if (m->pindex < NUPDE) {
2588 /* We just released a PT, unhold the matching PD */
2591 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2592 pmap_unwire_ptp(pmap, va, pdpg, free);
2594 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2595 /* We just released a PD, unhold the matching PDP */
2598 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2599 pmap_unwire_ptp(pmap, va, pdppg, free);
2603 * Put page on a list so that it is released after
2604 * *ALL* TLB shootdown is done
2606 pmap_add_delayed_free_list(m, free, TRUE);
2610 * After removing a page table entry, this routine is used to
2611 * conditionally free the page, and manage the hold/wire counts.
2614 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2615 struct spglist *free)
2619 if (va >= VM_MAXUSER_ADDRESS)
2621 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2622 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2623 return (pmap_unwire_ptp(pmap, va, mpte, free));
2627 pmap_pinit0(pmap_t pmap)
2631 PMAP_LOCK_INIT(pmap);
2632 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2633 pmap->pm_pml4u = NULL;
2634 pmap->pm_cr3 = KPML4phys;
2635 /* hack to keep pmap_pti_pcid_invalidate() alive */
2636 pmap->pm_ucr3 = PMAP_NO_CR3;
2637 pmap->pm_root.rt_root = 0;
2638 CPU_ZERO(&pmap->pm_active);
2639 TAILQ_INIT(&pmap->pm_pvchunk);
2640 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2641 pmap->pm_flags = pmap_flags;
2643 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2644 pmap->pm_pcids[i].pm_gen = 0;
2646 __pcpu[i].pc_kcr3 = PMAP_NO_CR3;
2647 __pcpu[i].pc_ucr3 = PMAP_NO_CR3;
2650 PCPU_SET(curpmap, kernel_pmap);
2651 pmap_activate(curthread);
2652 CPU_FILL(&kernel_pmap->pm_active);
2656 pmap_pinit_pml4(vm_page_t pml4pg)
2658 pml4_entry_t *pm_pml4;
2661 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2663 /* Wire in kernel global address entries. */
2664 for (i = 0; i < NKPML4E; i++) {
2665 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2668 for (i = 0; i < ndmpdpphys; i++) {
2669 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2673 /* install self-referential address mapping entry(s) */
2674 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2675 X86_PG_A | X86_PG_M;
2679 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2681 pml4_entry_t *pm_pml4;
2684 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2685 for (i = 0; i < NPML4EPG; i++)
2686 pm_pml4[i] = pti_pml4[i];
2690 * Initialize a preallocated and zeroed pmap structure,
2691 * such as one in a vmspace structure.
2694 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2696 vm_page_t pml4pg, pml4pgu;
2697 vm_paddr_t pml4phys;
2701 * allocate the page directory page
2703 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2704 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2706 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2707 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2709 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2710 pmap->pm_pcids[i].pm_gen = 0;
2712 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2713 pmap->pm_ucr3 = PMAP_NO_CR3;
2714 pmap->pm_pml4u = NULL;
2716 pmap->pm_type = pm_type;
2717 if ((pml4pg->flags & PG_ZERO) == 0)
2718 pagezero(pmap->pm_pml4);
2721 * Do not install the host kernel mappings in the nested page
2722 * tables. These mappings are meaningless in the guest physical
2724 * Install minimal kernel mappings in PTI case.
2726 if (pm_type == PT_X86) {
2727 pmap->pm_cr3 = pml4phys;
2728 pmap_pinit_pml4(pml4pg);
2730 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2731 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2732 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2733 VM_PAGE_TO_PHYS(pml4pgu));
2734 pmap_pinit_pml4_pti(pml4pgu);
2735 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2739 pmap->pm_root.rt_root = 0;
2740 CPU_ZERO(&pmap->pm_active);
2741 TAILQ_INIT(&pmap->pm_pvchunk);
2742 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2743 pmap->pm_flags = flags;
2744 pmap->pm_eptgen = 0;
2750 pmap_pinit(pmap_t pmap)
2753 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2757 * This routine is called if the desired page table page does not exist.
2759 * If page table page allocation fails, this routine may sleep before
2760 * returning NULL. It sleeps only if a lock pointer was given.
2762 * Note: If a page allocation fails at page table level two or three,
2763 * one or two pages may be held during the wait, only to be released
2764 * afterwards. This conservative approach is easily argued to avoid
2768 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2770 vm_page_t m, pdppg, pdpg;
2771 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2775 PG_A = pmap_accessed_bit(pmap);
2776 PG_M = pmap_modified_bit(pmap);
2777 PG_V = pmap_valid_bit(pmap);
2778 PG_RW = pmap_rw_bit(pmap);
2781 * Allocate a page table page.
2783 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2784 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2785 if (lockp != NULL) {
2786 RELEASE_PV_LIST_LOCK(lockp);
2788 PMAP_ASSERT_NOT_IN_DI();
2794 * Indicate the need to retry. While waiting, the page table
2795 * page may have been allocated.
2799 if ((m->flags & PG_ZERO) == 0)
2803 * Map the pagetable page into the process address space, if
2804 * it isn't already there.
2807 if (ptepindex >= (NUPDE + NUPDPE)) {
2808 pml4_entry_t *pml4, *pml4u;
2809 vm_pindex_t pml4index;
2811 /* Wire up a new PDPE page */
2812 pml4index = ptepindex - (NUPDE + NUPDPE);
2813 pml4 = &pmap->pm_pml4[pml4index];
2814 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2815 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
2817 * PTI: Make all user-space mappings in the
2818 * kernel-mode page table no-execute so that
2819 * we detect any programming errors that leave
2820 * the kernel-mode page table active on return
2823 if (pmap->pm_ucr3 != PMAP_NO_CR3)
2826 pml4u = &pmap->pm_pml4u[pml4index];
2827 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
2831 } else if (ptepindex >= NUPDE) {
2832 vm_pindex_t pml4index;
2833 vm_pindex_t pdpindex;
2837 /* Wire up a new PDE page */
2838 pdpindex = ptepindex - NUPDE;
2839 pml4index = pdpindex >> NPML4EPGSHIFT;
2841 pml4 = &pmap->pm_pml4[pml4index];
2842 if ((*pml4 & PG_V) == 0) {
2843 /* Have to allocate a new pdp, recurse */
2844 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2846 vm_page_unwire_noq(m);
2847 vm_page_free_zero(m);
2851 /* Add reference to pdp page */
2852 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2853 pdppg->wire_count++;
2855 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2857 /* Now find the pdp page */
2858 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2859 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2862 vm_pindex_t pml4index;
2863 vm_pindex_t pdpindex;
2868 /* Wire up a new PTE page */
2869 pdpindex = ptepindex >> NPDPEPGSHIFT;
2870 pml4index = pdpindex >> NPML4EPGSHIFT;
2872 /* First, find the pdp and check that its valid. */
2873 pml4 = &pmap->pm_pml4[pml4index];
2874 if ((*pml4 & PG_V) == 0) {
2875 /* Have to allocate a new pd, recurse */
2876 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2878 vm_page_unwire_noq(m);
2879 vm_page_free_zero(m);
2882 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2883 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2885 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2886 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2887 if ((*pdp & PG_V) == 0) {
2888 /* Have to allocate a new pd, recurse */
2889 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2891 vm_page_unwire_noq(m);
2892 vm_page_free_zero(m);
2896 /* Add reference to the pd page */
2897 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2901 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2903 /* Now we know where the page directory page is */
2904 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2905 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2908 pmap_resident_count_inc(pmap, 1);
2914 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2916 vm_pindex_t pdpindex, ptepindex;
2917 pdp_entry_t *pdpe, PG_V;
2920 PG_V = pmap_valid_bit(pmap);
2923 pdpe = pmap_pdpe(pmap, va);
2924 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2925 /* Add a reference to the pd page. */
2926 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2929 /* Allocate a pd page. */
2930 ptepindex = pmap_pde_pindex(va);
2931 pdpindex = ptepindex >> NPDPEPGSHIFT;
2932 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2933 if (pdpg == NULL && lockp != NULL)
2940 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2942 vm_pindex_t ptepindex;
2943 pd_entry_t *pd, PG_V;
2946 PG_V = pmap_valid_bit(pmap);
2949 * Calculate pagetable page index
2951 ptepindex = pmap_pde_pindex(va);
2954 * Get the page directory entry
2956 pd = pmap_pde(pmap, va);
2959 * This supports switching from a 2MB page to a
2962 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2963 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2965 * Invalidation of the 2MB page mapping may have caused
2966 * the deallocation of the underlying PD page.
2973 * If the page table page is mapped, we just increment the
2974 * hold count, and activate it.
2976 if (pd != NULL && (*pd & PG_V) != 0) {
2977 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2981 * Here if the pte page isn't mapped, or if it has been
2984 m = _pmap_allocpte(pmap, ptepindex, lockp);
2985 if (m == NULL && lockp != NULL)
2992 /***************************************************
2993 * Pmap allocation/deallocation routines.
2994 ***************************************************/
2997 * Release any resources held by the given physical map.
2998 * Called when a pmap initialized by pmap_pinit is being released.
2999 * Should only be called if the map contains no valid mappings.
3002 pmap_release(pmap_t pmap)
3007 KASSERT(pmap->pm_stats.resident_count == 0,
3008 ("pmap_release: pmap resident count %ld != 0",
3009 pmap->pm_stats.resident_count));
3010 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3011 ("pmap_release: pmap has reserved page table page(s)"));
3012 KASSERT(CPU_EMPTY(&pmap->pm_active),
3013 ("releasing active pmap %p", pmap));
3015 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3017 for (i = 0; i < NKPML4E; i++) /* KVA */
3018 pmap->pm_pml4[KPML4BASE + i] = 0;
3019 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3020 pmap->pm_pml4[DMPML4I + i] = 0;
3021 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3023 vm_page_unwire_noq(m);
3024 vm_page_free_zero(m);
3026 if (pmap->pm_pml4u != NULL) {
3027 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3028 vm_page_unwire_noq(m);
3034 kvm_size(SYSCTL_HANDLER_ARGS)
3036 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3038 return sysctl_handle_long(oidp, &ksize, 0, req);
3040 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3041 0, 0, kvm_size, "LU", "Size of KVM");
3044 kvm_free(SYSCTL_HANDLER_ARGS)
3046 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3048 return sysctl_handle_long(oidp, &kfree, 0, req);
3050 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3051 0, 0, kvm_free, "LU", "Amount of KVM free");
3054 * grow the number of kernel page table entries, if needed
3057 pmap_growkernel(vm_offset_t addr)
3061 pd_entry_t *pde, newpdir;
3064 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3067 * Return if "addr" is within the range of kernel page table pages
3068 * that were preallocated during pmap bootstrap. Moreover, leave
3069 * "kernel_vm_end" and the kernel page table as they were.
3071 * The correctness of this action is based on the following
3072 * argument: vm_map_insert() allocates contiguous ranges of the
3073 * kernel virtual address space. It calls this function if a range
3074 * ends after "kernel_vm_end". If the kernel is mapped between
3075 * "kernel_vm_end" and "addr", then the range cannot begin at
3076 * "kernel_vm_end". In fact, its beginning address cannot be less
3077 * than the kernel. Thus, there is no immediate need to allocate
3078 * any new kernel page table pages between "kernel_vm_end" and
3081 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3084 addr = roundup2(addr, NBPDR);
3085 if (addr - 1 >= kernel_map->max_offset)
3086 addr = kernel_map->max_offset;
3087 while (kernel_vm_end < addr) {
3088 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3089 if ((*pdpe & X86_PG_V) == 0) {
3090 /* We need a new PDP entry */
3091 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3092 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3093 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3095 panic("pmap_growkernel: no memory to grow kernel");
3096 if ((nkpg->flags & PG_ZERO) == 0)
3097 pmap_zero_page(nkpg);
3098 paddr = VM_PAGE_TO_PHYS(nkpg);
3099 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3100 X86_PG_A | X86_PG_M);
3101 continue; /* try again */
3103 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3104 if ((*pde & X86_PG_V) != 0) {
3105 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3106 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
3107 kernel_vm_end = kernel_map->max_offset;
3113 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3114 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3117 panic("pmap_growkernel: no memory to grow kernel");
3118 if ((nkpg->flags & PG_ZERO) == 0)
3119 pmap_zero_page(nkpg);
3120 paddr = VM_PAGE_TO_PHYS(nkpg);
3121 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3122 pde_store(pde, newpdir);
3124 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3125 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
3126 kernel_vm_end = kernel_map->max_offset;
3133 /***************************************************
3134 * page management routines.
3135 ***************************************************/
3137 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3138 CTASSERT(_NPCM == 3);
3139 CTASSERT(_NPCPV == 168);
3141 static __inline struct pv_chunk *
3142 pv_to_chunk(pv_entry_t pv)
3145 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3148 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3150 #define PC_FREE0 0xfffffffffffffffful
3151 #define PC_FREE1 0xfffffffffffffffful
3152 #define PC_FREE2 0x000000fffffffffful
3154 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3157 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3159 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3160 "Current number of pv entry chunks");
3161 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3162 "Current number of pv entry chunks allocated");
3163 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3164 "Current number of pv entry chunks frees");
3165 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3166 "Number of times tried to get a chunk page but failed.");
3168 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3169 static int pv_entry_spare;
3171 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3172 "Current number of pv entry frees");
3173 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3174 "Current number of pv entry allocs");
3175 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3176 "Current number of pv entries");
3177 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3178 "Current number of spare pv entries");
3182 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3187 pmap_invalidate_all(pmap);
3188 if (pmap != locked_pmap)
3191 pmap_delayed_invl_finished();
3195 * We are in a serious low memory condition. Resort to
3196 * drastic measures to free some pages so we can allocate
3197 * another pv entry chunk.
3199 * Returns NULL if PV entries were reclaimed from the specified pmap.
3201 * We do not, however, unmap 2mpages because subsequent accesses will
3202 * allocate per-page pv entries until repromotion occurs, thereby
3203 * exacerbating the shortage of free pv entries.
3206 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3208 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3209 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3210 struct md_page *pvh;
3212 pmap_t next_pmap, pmap;
3213 pt_entry_t *pte, tpte;
3214 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3218 struct spglist free;
3220 int bit, field, freed;
3222 static int active_reclaims = 0;
3224 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3225 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3228 PG_G = PG_A = PG_M = PG_RW = 0;
3230 bzero(&pc_marker_b, sizeof(pc_marker_b));
3231 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3232 pc_marker = (struct pv_chunk *)&pc_marker_b;
3233 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3236 * A delayed invalidation block should already be active if
3237 * pmap_advise() or pmap_remove() called this function by way
3238 * of pmap_demote_pde_locked().
3240 start_di = pmap_not_in_di();
3242 mtx_lock(&pv_chunks_mutex);
3244 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3245 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3246 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3247 SLIST_EMPTY(&free)) {
3248 next_pmap = pc->pc_pmap;
3249 if (next_pmap == NULL) {
3251 * The next chunk is a marker. However, it is
3252 * not our marker, so active_reclaims must be
3253 * > 1. Consequently, the next_chunk code
3254 * will not rotate the pv_chunks list.
3258 mtx_unlock(&pv_chunks_mutex);
3261 * A pv_chunk can only be removed from the pc_lru list
3262 * when both pc_chunks_mutex is owned and the
3263 * corresponding pmap is locked.
3265 if (pmap != next_pmap) {
3266 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3269 /* Avoid deadlock and lock recursion. */
3270 if (pmap > locked_pmap) {
3271 RELEASE_PV_LIST_LOCK(lockp);
3274 pmap_delayed_invl_started();
3275 mtx_lock(&pv_chunks_mutex);
3277 } else if (pmap != locked_pmap) {
3278 if (PMAP_TRYLOCK(pmap)) {
3280 pmap_delayed_invl_started();
3281 mtx_lock(&pv_chunks_mutex);
3284 pmap = NULL; /* pmap is not locked */
3285 mtx_lock(&pv_chunks_mutex);
3286 pc = TAILQ_NEXT(pc_marker, pc_lru);
3288 pc->pc_pmap != next_pmap)
3292 } else if (start_di)
3293 pmap_delayed_invl_started();
3294 PG_G = pmap_global_bit(pmap);
3295 PG_A = pmap_accessed_bit(pmap);
3296 PG_M = pmap_modified_bit(pmap);
3297 PG_RW = pmap_rw_bit(pmap);
3301 * Destroy every non-wired, 4 KB page mapping in the chunk.
3304 for (field = 0; field < _NPCM; field++) {
3305 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3306 inuse != 0; inuse &= ~(1UL << bit)) {
3308 pv = &pc->pc_pventry[field * 64 + bit];
3310 pde = pmap_pde(pmap, va);
3311 if ((*pde & PG_PS) != 0)
3313 pte = pmap_pde_to_pte(pde, va);
3314 if ((*pte & PG_W) != 0)
3316 tpte = pte_load_clear(pte);
3317 if ((tpte & PG_G) != 0)
3318 pmap_invalidate_page(pmap, va);
3319 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3320 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3322 if ((tpte & PG_A) != 0)
3323 vm_page_aflag_set(m, PGA_REFERENCED);
3324 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3325 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3327 if (TAILQ_EMPTY(&m->md.pv_list) &&
3328 (m->flags & PG_FICTITIOUS) == 0) {
3329 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3330 if (TAILQ_EMPTY(&pvh->pv_list)) {
3331 vm_page_aflag_clear(m,
3335 pmap_delayed_invl_page(m);
3336 pc->pc_map[field] |= 1UL << bit;
3337 pmap_unuse_pt(pmap, va, *pde, &free);
3342 mtx_lock(&pv_chunks_mutex);
3345 /* Every freed mapping is for a 4 KB page. */
3346 pmap_resident_count_dec(pmap, freed);
3347 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3348 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3349 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3350 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3351 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3352 pc->pc_map[2] == PC_FREE2) {
3353 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3354 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3355 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3356 /* Entire chunk is free; return it. */
3357 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3358 dump_drop_page(m_pc->phys_addr);
3359 mtx_lock(&pv_chunks_mutex);
3360 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3363 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3364 mtx_lock(&pv_chunks_mutex);
3365 /* One freed pv entry in locked_pmap is sufficient. */
3366 if (pmap == locked_pmap)
3369 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3370 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3371 if (active_reclaims == 1 && pmap != NULL) {
3373 * Rotate the pv chunks list so that we do not
3374 * scan the same pv chunks that could not be
3375 * freed (because they contained a wired
3376 * and/or superpage mapping) on every
3377 * invocation of reclaim_pv_chunk().
3379 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3380 MPASS(pc->pc_pmap != NULL);
3381 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3382 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3386 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3387 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3389 mtx_unlock(&pv_chunks_mutex);
3390 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3391 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3392 m_pc = SLIST_FIRST(&free);
3393 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3394 /* Recycle a freed page table page. */
3395 m_pc->wire_count = 1;
3397 vm_page_free_pages_toq(&free, true);
3402 * free the pv_entry back to the free list
3405 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3407 struct pv_chunk *pc;
3408 int idx, field, bit;
3410 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3411 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3412 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3413 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3414 pc = pv_to_chunk(pv);
3415 idx = pv - &pc->pc_pventry[0];
3418 pc->pc_map[field] |= 1ul << bit;
3419 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3420 pc->pc_map[2] != PC_FREE2) {
3421 /* 98% of the time, pc is already at the head of the list. */
3422 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3423 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3424 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3428 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3433 free_pv_chunk(struct pv_chunk *pc)
3437 mtx_lock(&pv_chunks_mutex);
3438 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3439 mtx_unlock(&pv_chunks_mutex);
3440 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3441 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3442 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3443 /* entire chunk is free, return it */
3444 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3445 dump_drop_page(m->phys_addr);
3446 vm_page_unwire(m, PQ_NONE);
3451 * Returns a new PV entry, allocating a new PV chunk from the system when
3452 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3453 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3456 * The given PV list lock may be released.
3459 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3463 struct pv_chunk *pc;
3466 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3467 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3469 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3471 for (field = 0; field < _NPCM; field++) {
3472 if (pc->pc_map[field]) {
3473 bit = bsfq(pc->pc_map[field]);
3477 if (field < _NPCM) {
3478 pv = &pc->pc_pventry[field * 64 + bit];
3479 pc->pc_map[field] &= ~(1ul << bit);
3480 /* If this was the last item, move it to tail */
3481 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3482 pc->pc_map[2] == 0) {
3483 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3484 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3487 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3488 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3492 /* No free items, allocate another chunk */
3493 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3496 if (lockp == NULL) {
3497 PV_STAT(pc_chunk_tryfail++);
3500 m = reclaim_pv_chunk(pmap, lockp);
3504 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3505 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3506 dump_add_page(m->phys_addr);
3507 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3509 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3510 pc->pc_map[1] = PC_FREE1;
3511 pc->pc_map[2] = PC_FREE2;
3512 mtx_lock(&pv_chunks_mutex);
3513 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3514 mtx_unlock(&pv_chunks_mutex);
3515 pv = &pc->pc_pventry[0];
3516 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3517 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3518 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3523 * Returns the number of one bits within the given PV chunk map.
3525 * The erratas for Intel processors state that "POPCNT Instruction May
3526 * Take Longer to Execute Than Expected". It is believed that the
3527 * issue is the spurious dependency on the destination register.
3528 * Provide a hint to the register rename logic that the destination
3529 * value is overwritten, by clearing it, as suggested in the
3530 * optimization manual. It should be cheap for unaffected processors
3533 * Reference numbers for erratas are
3534 * 4th Gen Core: HSD146
3535 * 5th Gen Core: BDM85
3536 * 6th Gen Core: SKL029
3539 popcnt_pc_map_pq(uint64_t *map)
3543 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3544 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3545 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3546 : "=&r" (result), "=&r" (tmp)
3547 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3552 * Ensure that the number of spare PV entries in the specified pmap meets or
3553 * exceeds the given count, "needed".
3555 * The given PV list lock may be released.
3558 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3560 struct pch new_tail;
3561 struct pv_chunk *pc;
3566 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3567 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3570 * Newly allocated PV chunks must be stored in a private list until
3571 * the required number of PV chunks have been allocated. Otherwise,
3572 * reclaim_pv_chunk() could recycle one of these chunks. In
3573 * contrast, these chunks must be added to the pmap upon allocation.
3575 TAILQ_INIT(&new_tail);
3578 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3580 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3581 bit_count((bitstr_t *)pc->pc_map, 0,
3582 sizeof(pc->pc_map) * NBBY, &free);
3585 free = popcnt_pc_map_pq(pc->pc_map);
3589 if (avail >= needed)
3592 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3593 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3596 m = reclaim_pv_chunk(pmap, lockp);
3601 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3602 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3603 dump_add_page(m->phys_addr);
3604 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3606 pc->pc_map[0] = PC_FREE0;
3607 pc->pc_map[1] = PC_FREE1;
3608 pc->pc_map[2] = PC_FREE2;
3609 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3610 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3611 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3614 * The reclaim might have freed a chunk from the current pmap.
3615 * If that chunk contained available entries, we need to
3616 * re-count the number of available entries.
3621 if (!TAILQ_EMPTY(&new_tail)) {
3622 mtx_lock(&pv_chunks_mutex);
3623 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3624 mtx_unlock(&pv_chunks_mutex);
3629 * First find and then remove the pv entry for the specified pmap and virtual
3630 * address from the specified pv list. Returns the pv entry if found and NULL
3631 * otherwise. This operation can be performed on pv lists for either 4KB or
3632 * 2MB page mappings.
3634 static __inline pv_entry_t
3635 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3639 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3640 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3641 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3650 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3651 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3652 * entries for each of the 4KB page mappings.
3655 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3656 struct rwlock **lockp)
3658 struct md_page *pvh;
3659 struct pv_chunk *pc;
3661 vm_offset_t va_last;
3665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3666 KASSERT((pa & PDRMASK) == 0,
3667 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3668 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3671 * Transfer the 2mpage's pv entry for this mapping to the first
3672 * page's pv list. Once this transfer begins, the pv list lock
3673 * must not be released until the last pv entry is reinstantiated.
3675 pvh = pa_to_pvh(pa);
3676 va = trunc_2mpage(va);
3677 pv = pmap_pvh_remove(pvh, pmap, va);
3678 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3679 m = PHYS_TO_VM_PAGE(pa);
3680 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3682 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3683 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3684 va_last = va + NBPDR - PAGE_SIZE;
3686 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3687 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3688 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3689 for (field = 0; field < _NPCM; field++) {
3690 while (pc->pc_map[field]) {
3691 bit = bsfq(pc->pc_map[field]);
3692 pc->pc_map[field] &= ~(1ul << bit);
3693 pv = &pc->pc_pventry[field * 64 + bit];
3697 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3698 ("pmap_pv_demote_pde: page %p is not managed", m));
3699 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3705 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3706 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3709 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3710 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3711 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3713 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3714 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3717 #if VM_NRESERVLEVEL > 0
3719 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3720 * replace the many pv entries for the 4KB page mappings by a single pv entry
3721 * for the 2MB page mapping.
3724 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3725 struct rwlock **lockp)
3727 struct md_page *pvh;
3729 vm_offset_t va_last;
3732 KASSERT((pa & PDRMASK) == 0,
3733 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3734 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3737 * Transfer the first page's pv entry for this mapping to the 2mpage's
3738 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3739 * a transfer avoids the possibility that get_pv_entry() calls
3740 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3741 * mappings that is being promoted.
3743 m = PHYS_TO_VM_PAGE(pa);
3744 va = trunc_2mpage(va);
3745 pv = pmap_pvh_remove(&m->md, pmap, va);
3746 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3747 pvh = pa_to_pvh(pa);
3748 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3750 /* Free the remaining NPTEPG - 1 pv entries. */
3751 va_last = va + NBPDR - PAGE_SIZE;
3755 pmap_pvh_free(&m->md, pmap, va);
3756 } while (va < va_last);
3758 #endif /* VM_NRESERVLEVEL > 0 */
3761 * First find and then destroy the pv entry for the specified pmap and virtual
3762 * address. This operation can be performed on pv lists for either 4KB or 2MB
3766 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3770 pv = pmap_pvh_remove(pvh, pmap, va);
3771 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3772 free_pv_entry(pmap, pv);
3776 * Conditionally create the PV entry for a 4KB page mapping if the required
3777 * memory can be allocated without resorting to reclamation.
3780 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3781 struct rwlock **lockp)
3785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3786 /* Pass NULL instead of the lock pointer to disable reclamation. */
3787 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3789 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3790 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3798 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3799 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3800 * false if the PV entry cannot be allocated without resorting to reclamation.
3803 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
3804 struct rwlock **lockp)
3806 struct md_page *pvh;
3810 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3811 /* Pass NULL instead of the lock pointer to disable reclamation. */
3812 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3813 NULL : lockp)) == NULL)
3816 pa = pde & PG_PS_FRAME;
3817 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3818 pvh = pa_to_pvh(pa);
3819 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3825 * Fills a page table page with mappings to consecutive physical pages.
3828 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3832 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3834 newpte += PAGE_SIZE;
3839 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3840 * mapping is invalidated.
3843 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3845 struct rwlock *lock;
3849 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3856 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3857 struct rwlock **lockp)
3859 pd_entry_t newpde, oldpde;
3860 pt_entry_t *firstpte, newpte;
3861 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3864 struct spglist free;
3868 PG_G = pmap_global_bit(pmap);
3869 PG_A = pmap_accessed_bit(pmap);
3870 PG_M = pmap_modified_bit(pmap);
3871 PG_RW = pmap_rw_bit(pmap);
3872 PG_V = pmap_valid_bit(pmap);
3873 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3875 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3877 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3878 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3879 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
3881 KASSERT((oldpde & PG_W) == 0,
3882 ("pmap_demote_pde: page table page for a wired mapping"
3886 * Invalidate the 2MB page mapping and return "failure" if the
3887 * mapping was never accessed or the allocation of the new
3888 * page table page fails. If the 2MB page mapping belongs to
3889 * the direct map region of the kernel's address space, then
3890 * the page allocation request specifies the highest possible
3891 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3892 * normal. Page table pages are preallocated for every other
3893 * part of the kernel address space, so the direct map region
3894 * is the only part of the kernel address space that must be
3897 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3898 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3899 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3900 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3902 sva = trunc_2mpage(va);
3903 pmap_remove_pde(pmap, pde, sva, &free, lockp);
3904 if ((oldpde & PG_G) == 0)
3905 pmap_invalidate_pde_page(pmap, sva, oldpde);
3906 vm_page_free_pages_toq(&free, true);
3907 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3908 " in pmap %p", va, pmap);
3911 if (va < VM_MAXUSER_ADDRESS)
3912 pmap_resident_count_inc(pmap, 1);
3914 mptepa = VM_PAGE_TO_PHYS(mpte);
3915 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3916 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3917 KASSERT((oldpde & PG_A) != 0,
3918 ("pmap_demote_pde: oldpde is missing PG_A"));
3919 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3920 ("pmap_demote_pde: oldpde is missing PG_M"));
3921 newpte = oldpde & ~PG_PS;
3922 newpte = pmap_swap_pat(pmap, newpte);
3925 * If the page table page is new, initialize it.
3927 if (mpte->wire_count == 1) {
3928 mpte->wire_count = NPTEPG;
3929 pmap_fill_ptp(firstpte, newpte);
3931 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3932 ("pmap_demote_pde: firstpte and newpte map different physical"
3936 * If the mapping has changed attributes, update the page table
3939 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3940 pmap_fill_ptp(firstpte, newpte);
3943 * The spare PV entries must be reserved prior to demoting the
3944 * mapping, that is, prior to changing the PDE. Otherwise, the state
3945 * of the PDE and the PV lists will be inconsistent, which can result
3946 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3947 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3948 * PV entry for the 2MB page mapping that is being demoted.
3950 if ((oldpde & PG_MANAGED) != 0)
3951 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3954 * Demote the mapping. This pmap is locked. The old PDE has
3955 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3956 * set. Thus, there is no danger of a race with another
3957 * processor changing the setting of PG_A and/or PG_M between
3958 * the read above and the store below.
3960 if (workaround_erratum383)
3961 pmap_update_pde(pmap, va, pde, newpde);
3963 pde_store(pde, newpde);
3966 * Invalidate a stale recursive mapping of the page table page.
3968 if (va >= VM_MAXUSER_ADDRESS)
3969 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3972 * Demote the PV entry.
3974 if ((oldpde & PG_MANAGED) != 0)
3975 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3977 atomic_add_long(&pmap_pde_demotions, 1);
3978 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3979 " in pmap %p", va, pmap);
3984 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3987 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3993 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3994 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3995 mpte = pmap_remove_pt_page(pmap, va);
3997 panic("pmap_remove_kernel_pde: Missing pt page.");
3999 mptepa = VM_PAGE_TO_PHYS(mpte);
4000 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4003 * Initialize the page table page.
4005 pagezero((void *)PHYS_TO_DMAP(mptepa));
4008 * Demote the mapping.
4010 if (workaround_erratum383)
4011 pmap_update_pde(pmap, va, pde, newpde);
4013 pde_store(pde, newpde);
4016 * Invalidate a stale recursive mapping of the page table page.
4018 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4022 * pmap_remove_pde: do the things to unmap a superpage in a process
4025 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4026 struct spglist *free, struct rwlock **lockp)
4028 struct md_page *pvh;
4030 vm_offset_t eva, va;
4032 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4034 PG_G = pmap_global_bit(pmap);
4035 PG_A = pmap_accessed_bit(pmap);
4036 PG_M = pmap_modified_bit(pmap);
4037 PG_RW = pmap_rw_bit(pmap);
4039 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4040 KASSERT((sva & PDRMASK) == 0,
4041 ("pmap_remove_pde: sva is not 2mpage aligned"));
4042 oldpde = pte_load_clear(pdq);
4044 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4045 if ((oldpde & PG_G) != 0)
4046 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4047 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4048 if (oldpde & PG_MANAGED) {
4049 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4050 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4051 pmap_pvh_free(pvh, pmap, sva);
4053 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4054 va < eva; va += PAGE_SIZE, m++) {
4055 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4058 vm_page_aflag_set(m, PGA_REFERENCED);
4059 if (TAILQ_EMPTY(&m->md.pv_list) &&
4060 TAILQ_EMPTY(&pvh->pv_list))
4061 vm_page_aflag_clear(m, PGA_WRITEABLE);
4062 pmap_delayed_invl_page(m);
4065 if (pmap == kernel_pmap) {
4066 pmap_remove_kernel_pde(pmap, pdq, sva);
4068 mpte = pmap_remove_pt_page(pmap, sva);
4070 pmap_resident_count_dec(pmap, 1);
4071 KASSERT(mpte->wire_count == NPTEPG,
4072 ("pmap_remove_pde: pte page wire count error"));
4073 mpte->wire_count = 0;
4074 pmap_add_delayed_free_list(mpte, free, FALSE);
4077 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4081 * pmap_remove_pte: do the things to unmap a page in a process
4084 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4085 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4087 struct md_page *pvh;
4088 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4091 PG_A = pmap_accessed_bit(pmap);
4092 PG_M = pmap_modified_bit(pmap);
4093 PG_RW = pmap_rw_bit(pmap);
4095 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4096 oldpte = pte_load_clear(ptq);
4098 pmap->pm_stats.wired_count -= 1;
4099 pmap_resident_count_dec(pmap, 1);
4100 if (oldpte & PG_MANAGED) {
4101 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4102 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4105 vm_page_aflag_set(m, PGA_REFERENCED);
4106 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4107 pmap_pvh_free(&m->md, pmap, va);
4108 if (TAILQ_EMPTY(&m->md.pv_list) &&
4109 (m->flags & PG_FICTITIOUS) == 0) {
4110 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4111 if (TAILQ_EMPTY(&pvh->pv_list))
4112 vm_page_aflag_clear(m, PGA_WRITEABLE);
4114 pmap_delayed_invl_page(m);
4116 return (pmap_unuse_pt(pmap, va, ptepde, free));
4120 * Remove a single page from a process address space
4123 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4124 struct spglist *free)
4126 struct rwlock *lock;
4127 pt_entry_t *pte, PG_V;
4129 PG_V = pmap_valid_bit(pmap);
4130 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4131 if ((*pde & PG_V) == 0)
4133 pte = pmap_pde_to_pte(pde, va);
4134 if ((*pte & PG_V) == 0)
4137 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4140 pmap_invalidate_page(pmap, va);
4144 * Removes the specified range of addresses from the page table page.
4147 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4148 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4150 pt_entry_t PG_G, *pte;
4154 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4155 PG_G = pmap_global_bit(pmap);
4158 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4162 pmap_invalidate_range(pmap, va, sva);
4167 if ((*pte & PG_G) == 0)
4171 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4177 pmap_invalidate_range(pmap, va, sva);
4182 * Remove the given range of addresses from the specified map.
4184 * It is assumed that the start and end are properly
4185 * rounded to the page size.
4188 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4190 struct rwlock *lock;
4191 vm_offset_t va_next;
4192 pml4_entry_t *pml4e;
4194 pd_entry_t ptpaddr, *pde;
4195 pt_entry_t PG_G, PG_V;
4196 struct spglist free;
4199 PG_G = pmap_global_bit(pmap);
4200 PG_V = pmap_valid_bit(pmap);
4203 * Perform an unsynchronized read. This is, however, safe.
4205 if (pmap->pm_stats.resident_count == 0)
4211 pmap_delayed_invl_started();
4215 * special handling of removing one page. a very
4216 * common operation and easy to short circuit some
4219 if (sva + PAGE_SIZE == eva) {
4220 pde = pmap_pde(pmap, sva);
4221 if (pde && (*pde & PG_PS) == 0) {
4222 pmap_remove_page(pmap, sva, pde, &free);
4228 for (; sva < eva; sva = va_next) {
4230 if (pmap->pm_stats.resident_count == 0)
4233 pml4e = pmap_pml4e(pmap, sva);
4234 if ((*pml4e & PG_V) == 0) {
4235 va_next = (sva + NBPML4) & ~PML4MASK;
4241 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4242 if ((*pdpe & PG_V) == 0) {
4243 va_next = (sva + NBPDP) & ~PDPMASK;
4250 * Calculate index for next page table.
4252 va_next = (sva + NBPDR) & ~PDRMASK;
4256 pde = pmap_pdpe_to_pde(pdpe, sva);
4260 * Weed out invalid mappings.
4266 * Check for large page.
4268 if ((ptpaddr & PG_PS) != 0) {
4270 * Are we removing the entire large page? If not,
4271 * demote the mapping and fall through.
4273 if (sva + NBPDR == va_next && eva >= va_next) {
4275 * The TLB entry for a PG_G mapping is
4276 * invalidated by pmap_remove_pde().
4278 if ((ptpaddr & PG_G) == 0)
4280 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4282 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4284 /* The large page mapping was destroyed. */
4291 * Limit our scan to either the end of the va represented
4292 * by the current page table page, or to the end of the
4293 * range being removed.
4298 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4305 pmap_invalidate_all(pmap);
4307 pmap_delayed_invl_finished();
4308 vm_page_free_pages_toq(&free, true);
4312 * Routine: pmap_remove_all
4314 * Removes this physical page from
4315 * all physical maps in which it resides.
4316 * Reflects back modify bits to the pager.
4319 * Original versions of this routine were very
4320 * inefficient because they iteratively called
4321 * pmap_remove (slow...)
4325 pmap_remove_all(vm_page_t m)
4327 struct md_page *pvh;
4330 struct rwlock *lock;
4331 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4334 struct spglist free;
4335 int pvh_gen, md_gen;
4337 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4338 ("pmap_remove_all: page %p is not managed", m));
4340 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4341 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4342 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4345 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4347 if (!PMAP_TRYLOCK(pmap)) {
4348 pvh_gen = pvh->pv_gen;
4352 if (pvh_gen != pvh->pv_gen) {
4359 pde = pmap_pde(pmap, va);
4360 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4363 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4365 if (!PMAP_TRYLOCK(pmap)) {
4366 pvh_gen = pvh->pv_gen;
4367 md_gen = m->md.pv_gen;
4371 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4377 PG_A = pmap_accessed_bit(pmap);
4378 PG_M = pmap_modified_bit(pmap);
4379 PG_RW = pmap_rw_bit(pmap);
4380 pmap_resident_count_dec(pmap, 1);
4381 pde = pmap_pde(pmap, pv->pv_va);
4382 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4383 " a 2mpage in page %p's pv list", m));
4384 pte = pmap_pde_to_pte(pde, pv->pv_va);
4385 tpte = pte_load_clear(pte);
4387 pmap->pm_stats.wired_count--;
4389 vm_page_aflag_set(m, PGA_REFERENCED);
4392 * Update the vm_page_t clean and reference bits.
4394 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4396 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4397 pmap_invalidate_page(pmap, pv->pv_va);
4398 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4400 free_pv_entry(pmap, pv);
4403 vm_page_aflag_clear(m, PGA_WRITEABLE);
4405 pmap_delayed_invl_wait(m);
4406 vm_page_free_pages_toq(&free, true);
4410 * pmap_protect_pde: do the things to protect a 2mpage in a process
4413 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4415 pd_entry_t newpde, oldpde;
4416 vm_offset_t eva, va;
4418 boolean_t anychanged;
4419 pt_entry_t PG_G, PG_M, PG_RW;
4421 PG_G = pmap_global_bit(pmap);
4422 PG_M = pmap_modified_bit(pmap);
4423 PG_RW = pmap_rw_bit(pmap);
4425 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4426 KASSERT((sva & PDRMASK) == 0,
4427 ("pmap_protect_pde: sva is not 2mpage aligned"));
4430 oldpde = newpde = *pde;
4431 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4432 (PG_MANAGED | PG_M | PG_RW)) {
4434 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4435 va < eva; va += PAGE_SIZE, m++)
4438 if ((prot & VM_PROT_WRITE) == 0)
4439 newpde &= ~(PG_RW | PG_M);
4440 if ((prot & VM_PROT_EXECUTE) == 0)
4442 if (newpde != oldpde) {
4444 * As an optimization to future operations on this PDE, clear
4445 * PG_PROMOTED. The impending invalidation will remove any
4446 * lingering 4KB page mappings from the TLB.
4448 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4450 if ((oldpde & PG_G) != 0)
4451 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4455 return (anychanged);
4459 * Set the physical protection on the
4460 * specified range of this map as requested.
4463 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4465 vm_offset_t va_next;
4466 pml4_entry_t *pml4e;
4468 pd_entry_t ptpaddr, *pde;
4469 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4470 boolean_t anychanged;
4472 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4473 if (prot == VM_PROT_NONE) {
4474 pmap_remove(pmap, sva, eva);
4478 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4479 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4482 PG_G = pmap_global_bit(pmap);
4483 PG_M = pmap_modified_bit(pmap);
4484 PG_V = pmap_valid_bit(pmap);
4485 PG_RW = pmap_rw_bit(pmap);
4489 * Although this function delays and batches the invalidation
4490 * of stale TLB entries, it does not need to call
4491 * pmap_delayed_invl_started() and
4492 * pmap_delayed_invl_finished(), because it does not
4493 * ordinarily destroy mappings. Stale TLB entries from
4494 * protection-only changes need only be invalidated before the
4495 * pmap lock is released, because protection-only changes do
4496 * not destroy PV entries. Even operations that iterate over
4497 * a physical page's PV list of mappings, like
4498 * pmap_remove_write(), acquire the pmap lock for each
4499 * mapping. Consequently, for protection-only changes, the
4500 * pmap lock suffices to synchronize both page table and TLB
4503 * This function only destroys a mapping if pmap_demote_pde()
4504 * fails. In that case, stale TLB entries are immediately
4509 for (; sva < eva; sva = va_next) {
4511 pml4e = pmap_pml4e(pmap, sva);
4512 if ((*pml4e & PG_V) == 0) {
4513 va_next = (sva + NBPML4) & ~PML4MASK;
4519 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4520 if ((*pdpe & PG_V) == 0) {
4521 va_next = (sva + NBPDP) & ~PDPMASK;
4527 va_next = (sva + NBPDR) & ~PDRMASK;
4531 pde = pmap_pdpe_to_pde(pdpe, sva);
4535 * Weed out invalid mappings.
4541 * Check for large page.
4543 if ((ptpaddr & PG_PS) != 0) {
4545 * Are we protecting the entire large page? If not,
4546 * demote the mapping and fall through.
4548 if (sva + NBPDR == va_next && eva >= va_next) {
4550 * The TLB entry for a PG_G mapping is
4551 * invalidated by pmap_protect_pde().
4553 if (pmap_protect_pde(pmap, pde, sva, prot))
4556 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4558 * The large page mapping was destroyed.
4567 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4569 pt_entry_t obits, pbits;
4573 obits = pbits = *pte;
4574 if ((pbits & PG_V) == 0)
4577 if ((prot & VM_PROT_WRITE) == 0) {
4578 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4579 (PG_MANAGED | PG_M | PG_RW)) {
4580 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4583 pbits &= ~(PG_RW | PG_M);
4585 if ((prot & VM_PROT_EXECUTE) == 0)
4588 if (pbits != obits) {
4589 if (!atomic_cmpset_long(pte, obits, pbits))
4592 pmap_invalidate_page(pmap, sva);
4599 pmap_invalidate_all(pmap);
4603 #if VM_NRESERVLEVEL > 0
4605 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4606 * single page table page (PTP) to a single 2MB page mapping. For promotion
4607 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4608 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4609 * identical characteristics.
4612 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4613 struct rwlock **lockp)
4616 pt_entry_t *firstpte, oldpte, pa, *pte;
4617 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4621 PG_A = pmap_accessed_bit(pmap);
4622 PG_G = pmap_global_bit(pmap);
4623 PG_M = pmap_modified_bit(pmap);
4624 PG_V = pmap_valid_bit(pmap);
4625 PG_RW = pmap_rw_bit(pmap);
4626 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4628 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4631 * Examine the first PTE in the specified PTP. Abort if this PTE is
4632 * either invalid, unused, or does not map the first 4KB physical page
4633 * within a 2MB page.
4635 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4638 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4639 atomic_add_long(&pmap_pde_p_failures, 1);
4640 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4641 " in pmap %p", va, pmap);
4644 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4646 * When PG_M is already clear, PG_RW can be cleared without
4647 * a TLB invalidation.
4649 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4655 * Examine each of the other PTEs in the specified PTP. Abort if this
4656 * PTE maps an unexpected 4KB physical page or does not have identical
4657 * characteristics to the first PTE.
4659 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4660 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4663 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4664 atomic_add_long(&pmap_pde_p_failures, 1);
4665 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4666 " in pmap %p", va, pmap);
4669 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4671 * When PG_M is already clear, PG_RW can be cleared
4672 * without a TLB invalidation.
4674 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4677 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4678 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4679 (va & ~PDRMASK), pmap);
4681 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4682 atomic_add_long(&pmap_pde_p_failures, 1);
4683 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4684 " in pmap %p", va, pmap);
4691 * Save the page table page in its current state until the PDE
4692 * mapping the superpage is demoted by pmap_demote_pde() or
4693 * destroyed by pmap_remove_pde().
4695 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4696 KASSERT(mpte >= vm_page_array &&
4697 mpte < &vm_page_array[vm_page_array_size],
4698 ("pmap_promote_pde: page table page is out of range"));
4699 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4700 ("pmap_promote_pde: page table page's pindex is wrong"));
4701 if (pmap_insert_pt_page(pmap, mpte)) {
4702 atomic_add_long(&pmap_pde_p_failures, 1);
4704 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4710 * Promote the pv entries.
4712 if ((newpde & PG_MANAGED) != 0)
4713 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4716 * Propagate the PAT index to its proper position.
4718 newpde = pmap_swap_pat(pmap, newpde);
4721 * Map the superpage.
4723 if (workaround_erratum383)
4724 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4726 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4728 atomic_add_long(&pmap_pde_promotions, 1);
4729 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4730 " in pmap %p", va, pmap);
4732 #endif /* VM_NRESERVLEVEL > 0 */
4735 * Insert the given physical page (p) at
4736 * the specified virtual address (v) in the
4737 * target physical map with the protection requested.
4739 * If specified, the page will be wired down, meaning
4740 * that the related pte can not be reclaimed.
4742 * NB: This is the only routine which MAY NOT lazy-evaluate
4743 * or lose information. That is, this routine must actually
4744 * insert this page into the given map NOW.
4746 * When destroying both a page table and PV entry, this function
4747 * performs the TLB invalidation before releasing the PV list
4748 * lock, so we do not need pmap_delayed_invl_page() calls here.
4751 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4752 u_int flags, int8_t psind)
4754 struct rwlock *lock;
4756 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4757 pt_entry_t newpte, origpte;
4764 PG_A = pmap_accessed_bit(pmap);
4765 PG_G = pmap_global_bit(pmap);
4766 PG_M = pmap_modified_bit(pmap);
4767 PG_V = pmap_valid_bit(pmap);
4768 PG_RW = pmap_rw_bit(pmap);
4770 va = trunc_page(va);
4771 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4772 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4773 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4775 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4776 va >= kmi.clean_eva,
4777 ("pmap_enter: managed mapping within the clean submap"));
4778 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4779 VM_OBJECT_ASSERT_LOCKED(m->object);
4780 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
4781 ("pmap_enter: flags %u has reserved bits set", flags));
4782 pa = VM_PAGE_TO_PHYS(m);
4783 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4784 if ((flags & VM_PROT_WRITE) != 0)
4786 if ((prot & VM_PROT_WRITE) != 0)
4788 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4789 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4790 if ((prot & VM_PROT_EXECUTE) == 0)
4792 if ((flags & PMAP_ENTER_WIRED) != 0)
4794 if (va < VM_MAXUSER_ADDRESS)
4796 if (pmap == kernel_pmap)
4798 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
4801 * Set modified bit gratuitously for writeable mappings if
4802 * the page is unmanaged. We do not want to take a fault
4803 * to do the dirty bit accounting for these mappings.
4805 if ((m->oflags & VPO_UNMANAGED) != 0) {
4806 if ((newpte & PG_RW) != 0)
4809 newpte |= PG_MANAGED;
4814 /* Assert the required virtual and physical alignment. */
4815 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
4816 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4817 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
4823 * In the case that a page table page is not
4824 * resident, we are creating it here.
4827 pde = pmap_pde(pmap, va);
4828 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4829 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4830 pte = pmap_pde_to_pte(pde, va);
4831 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4832 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4835 } else if (va < VM_MAXUSER_ADDRESS) {
4837 * Here if the pte page isn't mapped, or if it has been
4840 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4841 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4842 nosleep ? NULL : &lock);
4843 if (mpte == NULL && nosleep) {
4844 rv = KERN_RESOURCE_SHORTAGE;
4849 panic("pmap_enter: invalid page directory va=%#lx", va);
4855 * Is the specified virtual address already mapped?
4857 if ((origpte & PG_V) != 0) {
4859 * Wiring change, just update stats. We don't worry about
4860 * wiring PT pages as they remain resident as long as there
4861 * are valid mappings in them. Hence, if a user page is wired,
4862 * the PT page will be also.
4864 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4865 pmap->pm_stats.wired_count++;
4866 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4867 pmap->pm_stats.wired_count--;
4870 * Remove the extra PT page reference.
4874 KASSERT(mpte->wire_count > 0,
4875 ("pmap_enter: missing reference to page table page,"
4880 * Has the physical page changed?
4882 opa = origpte & PG_FRAME;
4885 * No, might be a protection or wiring change.
4887 if ((origpte & PG_MANAGED) != 0 &&
4888 (newpte & PG_RW) != 0)
4889 vm_page_aflag_set(m, PGA_WRITEABLE);
4890 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4896 * The physical page has changed. Temporarily invalidate
4897 * the mapping. This ensures that all threads sharing the
4898 * pmap keep a consistent view of the mapping, which is
4899 * necessary for the correct handling of COW faults. It
4900 * also permits reuse of the old mapping's PV entry,
4901 * avoiding an allocation.
4903 * For consistency, handle unmanaged mappings the same way.
4905 origpte = pte_load_clear(pte);
4906 KASSERT((origpte & PG_FRAME) == opa,
4907 ("pmap_enter: unexpected pa update for %#lx", va));
4908 if ((origpte & PG_MANAGED) != 0) {
4909 om = PHYS_TO_VM_PAGE(opa);
4912 * The pmap lock is sufficient to synchronize with
4913 * concurrent calls to pmap_page_test_mappings() and
4914 * pmap_ts_referenced().
4916 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4918 if ((origpte & PG_A) != 0)
4919 vm_page_aflag_set(om, PGA_REFERENCED);
4920 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4921 pv = pmap_pvh_remove(&om->md, pmap, va);
4922 if ((newpte & PG_MANAGED) == 0)
4923 free_pv_entry(pmap, pv);
4924 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4925 TAILQ_EMPTY(&om->md.pv_list) &&
4926 ((om->flags & PG_FICTITIOUS) != 0 ||
4927 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4928 vm_page_aflag_clear(om, PGA_WRITEABLE);
4930 if ((origpte & PG_A) != 0)
4931 pmap_invalidate_page(pmap, va);
4935 * Increment the counters.
4937 if ((newpte & PG_W) != 0)
4938 pmap->pm_stats.wired_count++;
4939 pmap_resident_count_inc(pmap, 1);
4943 * Enter on the PV list if part of our managed memory.
4945 if ((newpte & PG_MANAGED) != 0) {
4947 pv = get_pv_entry(pmap, &lock);
4950 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4951 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4953 if ((newpte & PG_RW) != 0)
4954 vm_page_aflag_set(m, PGA_WRITEABLE);
4960 if ((origpte & PG_V) != 0) {
4962 origpte = pte_load_store(pte, newpte);
4963 KASSERT((origpte & PG_FRAME) == pa,
4964 ("pmap_enter: unexpected pa update for %#lx", va));
4965 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
4967 if ((origpte & PG_MANAGED) != 0)
4971 * Although the PTE may still have PG_RW set, TLB
4972 * invalidation may nonetheless be required because
4973 * the PTE no longer has PG_M set.
4975 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4977 * This PTE change does not require TLB invalidation.
4981 if ((origpte & PG_A) != 0)
4982 pmap_invalidate_page(pmap, va);
4984 pte_store(pte, newpte);
4988 #if VM_NRESERVLEVEL > 0
4990 * If both the page table page and the reservation are fully
4991 * populated, then attempt promotion.
4993 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4994 pmap_ps_enabled(pmap) &&
4995 (m->flags & PG_FICTITIOUS) == 0 &&
4996 vm_reserv_level_iffullpop(m) == 0)
4997 pmap_promote_pde(pmap, pde, va, &lock);
5009 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5010 * if successful. Returns false if (1) a page table page cannot be allocated
5011 * without sleeping, (2) a mapping already exists at the specified virtual
5012 * address, or (3) a PV entry cannot be allocated without reclaiming another
5016 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5017 struct rwlock **lockp)
5022 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5023 PG_V = pmap_valid_bit(pmap);
5024 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5026 if ((m->oflags & VPO_UNMANAGED) == 0)
5027 newpde |= PG_MANAGED;
5028 if ((prot & VM_PROT_EXECUTE) == 0)
5030 if (va < VM_MAXUSER_ADDRESS)
5032 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5033 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5038 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5039 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5040 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5041 * a mapping already exists at the specified virtual address. Returns
5042 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5043 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5044 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5046 * The parameter "m" is only used when creating a managed, writeable mapping.
5049 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5050 vm_page_t m, struct rwlock **lockp)
5052 struct spglist free;
5053 pd_entry_t oldpde, *pde;
5054 pt_entry_t PG_G, PG_RW, PG_V;
5057 PG_G = pmap_global_bit(pmap);
5058 PG_RW = pmap_rw_bit(pmap);
5059 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5060 ("pmap_enter_pde: newpde is missing PG_M"));
5061 PG_V = pmap_valid_bit(pmap);
5062 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5064 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5065 NULL : lockp)) == NULL) {
5066 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5067 " in pmap %p", va, pmap);
5068 return (KERN_RESOURCE_SHORTAGE);
5070 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5071 pde = &pde[pmap_pde_index(va)];
5073 if ((oldpde & PG_V) != 0) {
5074 KASSERT(pdpg->wire_count > 1,
5075 ("pmap_enter_pde: pdpg's wire count is too low"));
5076 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5078 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5079 " in pmap %p", va, pmap);
5080 return (KERN_FAILURE);
5082 /* Break the existing mapping(s). */
5084 if ((oldpde & PG_PS) != 0) {
5086 * The reference to the PD page that was acquired by
5087 * pmap_allocpde() ensures that it won't be freed.
5088 * However, if the PDE resulted from a promotion, then
5089 * a reserved PT page could be freed.
5091 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5092 if ((oldpde & PG_G) == 0)
5093 pmap_invalidate_pde_page(pmap, va, oldpde);
5095 pmap_delayed_invl_started();
5096 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5098 pmap_invalidate_all(pmap);
5099 pmap_delayed_invl_finished();
5101 vm_page_free_pages_toq(&free, true);
5102 if (va >= VM_MAXUSER_ADDRESS) {
5103 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5104 if (pmap_insert_pt_page(pmap, mt)) {
5106 * XXX Currently, this can't happen because
5107 * we do not perform pmap_enter(psind == 1)
5108 * on the kernel pmap.
5110 panic("pmap_enter_pde: trie insert failed");
5113 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5116 if ((newpde & PG_MANAGED) != 0) {
5118 * Abort this mapping if its PV entry could not be created.
5120 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5122 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5124 * Although "va" is not mapped, paging-
5125 * structure caches could nonetheless have
5126 * entries that refer to the freed page table
5127 * pages. Invalidate those entries.
5129 pmap_invalidate_page(pmap, va);
5130 vm_page_free_pages_toq(&free, true);
5132 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5133 " in pmap %p", va, pmap);
5134 return (KERN_RESOURCE_SHORTAGE);
5136 if ((newpde & PG_RW) != 0) {
5137 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5138 vm_page_aflag_set(mt, PGA_WRITEABLE);
5143 * Increment counters.
5145 if ((newpde & PG_W) != 0)
5146 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5147 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5150 * Map the superpage. (This is not a promoted mapping; there will not
5151 * be any lingering 4KB page mappings in the TLB.)
5153 pde_store(pde, newpde);
5155 atomic_add_long(&pmap_pde_mappings, 1);
5156 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5157 " in pmap %p", va, pmap);
5158 return (KERN_SUCCESS);
5162 * Maps a sequence of resident pages belonging to the same object.
5163 * The sequence begins with the given page m_start. This page is
5164 * mapped at the given virtual address start. Each subsequent page is
5165 * mapped at a virtual address that is offset from start by the same
5166 * amount as the page is offset from m_start within the object. The
5167 * last page in the sequence is the page with the largest offset from
5168 * m_start that can be mapped at a virtual address less than the given
5169 * virtual address end. Not every virtual page between start and end
5170 * is mapped; only those for which a resident page exists with the
5171 * corresponding offset from m_start are mapped.
5174 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5175 vm_page_t m_start, vm_prot_t prot)
5177 struct rwlock *lock;
5180 vm_pindex_t diff, psize;
5182 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5184 psize = atop(end - start);
5189 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5190 va = start + ptoa(diff);
5191 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5192 m->psind == 1 && pmap_ps_enabled(pmap) &&
5193 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5194 m = &m[NBPDR / PAGE_SIZE - 1];
5196 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5198 m = TAILQ_NEXT(m, listq);
5206 * this code makes some *MAJOR* assumptions:
5207 * 1. Current pmap & pmap exists.
5210 * 4. No page table pages.
5211 * but is *MUCH* faster than pmap_enter...
5215 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5217 struct rwlock *lock;
5221 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5228 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5229 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5231 struct spglist free;
5232 pt_entry_t *pte, PG_V;
5235 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5236 (m->oflags & VPO_UNMANAGED) != 0,
5237 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5238 PG_V = pmap_valid_bit(pmap);
5239 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5242 * In the case that a page table page is not
5243 * resident, we are creating it here.
5245 if (va < VM_MAXUSER_ADDRESS) {
5246 vm_pindex_t ptepindex;
5250 * Calculate pagetable page index
5252 ptepindex = pmap_pde_pindex(va);
5253 if (mpte && (mpte->pindex == ptepindex)) {
5257 * Get the page directory entry
5259 ptepa = pmap_pde(pmap, va);
5262 * If the page table page is mapped, we just increment
5263 * the hold count, and activate it. Otherwise, we
5264 * attempt to allocate a page table page. If this
5265 * attempt fails, we don't retry. Instead, we give up.
5267 if (ptepa && (*ptepa & PG_V) != 0) {
5270 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5274 * Pass NULL instead of the PV list lock
5275 * pointer, because we don't intend to sleep.
5277 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5282 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5283 pte = &pte[pmap_pte_index(va)];
5297 * Enter on the PV list if part of our managed memory.
5299 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5300 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5303 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5305 * Although "va" is not mapped, paging-
5306 * structure caches could nonetheless have
5307 * entries that refer to the freed page table
5308 * pages. Invalidate those entries.
5310 pmap_invalidate_page(pmap, va);
5311 vm_page_free_pages_toq(&free, true);
5319 * Increment counters
5321 pmap_resident_count_inc(pmap, 1);
5323 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
5324 if ((prot & VM_PROT_EXECUTE) == 0)
5328 * Now validate mapping with RO protection
5330 if ((m->oflags & VPO_UNMANAGED) != 0)
5331 pte_store(pte, pa | PG_V | PG_U);
5333 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
5338 * Make a temporary mapping for a physical address. This is only intended
5339 * to be used for panic dumps.
5342 pmap_kenter_temporary(vm_paddr_t pa, int i)
5346 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5347 pmap_kenter(va, pa);
5349 return ((void *)crashdumpmap);
5353 * This code maps large physical mmap regions into the
5354 * processor address space. Note that some shortcuts
5355 * are taken, but the code works.
5358 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5359 vm_pindex_t pindex, vm_size_t size)
5362 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5363 vm_paddr_t pa, ptepa;
5367 PG_A = pmap_accessed_bit(pmap);
5368 PG_M = pmap_modified_bit(pmap);
5369 PG_V = pmap_valid_bit(pmap);
5370 PG_RW = pmap_rw_bit(pmap);
5372 VM_OBJECT_ASSERT_WLOCKED(object);
5373 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5374 ("pmap_object_init_pt: non-device object"));
5375 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5376 if (!pmap_ps_enabled(pmap))
5378 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5380 p = vm_page_lookup(object, pindex);
5381 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5382 ("pmap_object_init_pt: invalid page %p", p));
5383 pat_mode = p->md.pat_mode;
5386 * Abort the mapping if the first page is not physically
5387 * aligned to a 2MB page boundary.
5389 ptepa = VM_PAGE_TO_PHYS(p);
5390 if (ptepa & (NBPDR - 1))
5394 * Skip the first page. Abort the mapping if the rest of
5395 * the pages are not physically contiguous or have differing
5396 * memory attributes.
5398 p = TAILQ_NEXT(p, listq);
5399 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5401 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5402 ("pmap_object_init_pt: invalid page %p", p));
5403 if (pa != VM_PAGE_TO_PHYS(p) ||
5404 pat_mode != p->md.pat_mode)
5406 p = TAILQ_NEXT(p, listq);
5410 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5411 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5412 * will not affect the termination of this loop.
5415 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5416 pa < ptepa + size; pa += NBPDR) {
5417 pdpg = pmap_allocpde(pmap, addr, NULL);
5420 * The creation of mappings below is only an
5421 * optimization. If a page directory page
5422 * cannot be allocated without blocking,
5423 * continue on to the next mapping rather than
5429 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5430 pde = &pde[pmap_pde_index(addr)];
5431 if ((*pde & PG_V) == 0) {
5432 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5433 PG_U | PG_RW | PG_V);
5434 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5435 atomic_add_long(&pmap_pde_mappings, 1);
5437 /* Continue on if the PDE is already valid. */
5439 KASSERT(pdpg->wire_count > 0,
5440 ("pmap_object_init_pt: missing reference "
5441 "to page directory page, va: 0x%lx", addr));
5450 * Clear the wired attribute from the mappings for the specified range of
5451 * addresses in the given pmap. Every valid mapping within that range
5452 * must have the wired attribute set. In contrast, invalid mappings
5453 * cannot have the wired attribute set, so they are ignored.
5455 * The wired attribute of the page table entry is not a hardware
5456 * feature, so there is no need to invalidate any TLB entries.
5457 * Since pmap_demote_pde() for the wired entry must never fail,
5458 * pmap_delayed_invl_started()/finished() calls around the
5459 * function are not needed.
5462 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5464 vm_offset_t va_next;
5465 pml4_entry_t *pml4e;
5468 pt_entry_t *pte, PG_V;
5470 PG_V = pmap_valid_bit(pmap);
5472 for (; sva < eva; sva = va_next) {
5473 pml4e = pmap_pml4e(pmap, sva);
5474 if ((*pml4e & PG_V) == 0) {
5475 va_next = (sva + NBPML4) & ~PML4MASK;
5480 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5481 if ((*pdpe & PG_V) == 0) {
5482 va_next = (sva + NBPDP) & ~PDPMASK;
5487 va_next = (sva + NBPDR) & ~PDRMASK;
5490 pde = pmap_pdpe_to_pde(pdpe, sva);
5491 if ((*pde & PG_V) == 0)
5493 if ((*pde & PG_PS) != 0) {
5494 if ((*pde & PG_W) == 0)
5495 panic("pmap_unwire: pde %#jx is missing PG_W",
5499 * Are we unwiring the entire large page? If not,
5500 * demote the mapping and fall through.
5502 if (sva + NBPDR == va_next && eva >= va_next) {
5503 atomic_clear_long(pde, PG_W);
5504 pmap->pm_stats.wired_count -= NBPDR /
5507 } else if (!pmap_demote_pde(pmap, pde, sva))
5508 panic("pmap_unwire: demotion failed");
5512 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5514 if ((*pte & PG_V) == 0)
5516 if ((*pte & PG_W) == 0)
5517 panic("pmap_unwire: pte %#jx is missing PG_W",
5521 * PG_W must be cleared atomically. Although the pmap
5522 * lock synchronizes access to PG_W, another processor
5523 * could be setting PG_M and/or PG_A concurrently.
5525 atomic_clear_long(pte, PG_W);
5526 pmap->pm_stats.wired_count--;
5533 * Copy the range specified by src_addr/len
5534 * from the source map to the range dst_addr/len
5535 * in the destination map.
5537 * This routine is only advisory and need not do anything.
5541 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5542 vm_offset_t src_addr)
5544 struct rwlock *lock;
5545 struct spglist free;
5547 vm_offset_t end_addr = src_addr + len;
5548 vm_offset_t va_next;
5549 vm_page_t dst_pdpg, dstmpte, srcmpte;
5550 pt_entry_t PG_A, PG_M, PG_V;
5552 if (dst_addr != src_addr)
5555 if (dst_pmap->pm_type != src_pmap->pm_type)
5559 * EPT page table entries that require emulation of A/D bits are
5560 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5561 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5562 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5563 * implementations flag an EPT misconfiguration for exec-only
5564 * mappings we skip this function entirely for emulated pmaps.
5566 if (pmap_emulate_ad_bits(dst_pmap))
5570 if (dst_pmap < src_pmap) {
5571 PMAP_LOCK(dst_pmap);
5572 PMAP_LOCK(src_pmap);
5574 PMAP_LOCK(src_pmap);
5575 PMAP_LOCK(dst_pmap);
5578 PG_A = pmap_accessed_bit(dst_pmap);
5579 PG_M = pmap_modified_bit(dst_pmap);
5580 PG_V = pmap_valid_bit(dst_pmap);
5582 for (addr = src_addr; addr < end_addr; addr = va_next) {
5583 pt_entry_t *src_pte, *dst_pte;
5584 pml4_entry_t *pml4e;
5586 pd_entry_t srcptepaddr, *pde;
5588 KASSERT(addr < UPT_MIN_ADDRESS,
5589 ("pmap_copy: invalid to pmap_copy page tables"));
5591 pml4e = pmap_pml4e(src_pmap, addr);
5592 if ((*pml4e & PG_V) == 0) {
5593 va_next = (addr + NBPML4) & ~PML4MASK;
5599 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5600 if ((*pdpe & PG_V) == 0) {
5601 va_next = (addr + NBPDP) & ~PDPMASK;
5607 va_next = (addr + NBPDR) & ~PDRMASK;
5611 pde = pmap_pdpe_to_pde(pdpe, addr);
5613 if (srcptepaddr == 0)
5616 if (srcptepaddr & PG_PS) {
5617 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5619 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5620 if (dst_pdpg == NULL)
5622 pde = (pd_entry_t *)
5623 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5624 pde = &pde[pmap_pde_index(addr)];
5625 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5626 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5627 PMAP_ENTER_NORECLAIM, &lock))) {
5628 *pde = srcptepaddr & ~PG_W;
5629 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5630 atomic_add_long(&pmap_pde_mappings, 1);
5632 dst_pdpg->wire_count--;
5636 srcptepaddr &= PG_FRAME;
5637 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5638 KASSERT(srcmpte->wire_count > 0,
5639 ("pmap_copy: source page table page is unused"));
5641 if (va_next > end_addr)
5644 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5645 src_pte = &src_pte[pmap_pte_index(addr)];
5647 while (addr < va_next) {
5651 * we only virtual copy managed pages
5653 if ((ptetemp & PG_MANAGED) != 0) {
5654 if (dstmpte != NULL &&
5655 dstmpte->pindex == pmap_pde_pindex(addr))
5656 dstmpte->wire_count++;
5657 else if ((dstmpte = pmap_allocpte(dst_pmap,
5658 addr, NULL)) == NULL)
5660 dst_pte = (pt_entry_t *)
5661 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5662 dst_pte = &dst_pte[pmap_pte_index(addr)];
5663 if (*dst_pte == 0 &&
5664 pmap_try_insert_pv_entry(dst_pmap, addr,
5665 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5668 * Clear the wired, modified, and
5669 * accessed (referenced) bits
5672 *dst_pte = ptetemp & ~(PG_W | PG_M |
5674 pmap_resident_count_inc(dst_pmap, 1);
5677 if (pmap_unwire_ptp(dst_pmap, addr,
5680 * Although "addr" is not
5681 * mapped, paging-structure
5682 * caches could nonetheless
5683 * have entries that refer to
5684 * the freed page table pages.
5685 * Invalidate those entries.
5687 pmap_invalidate_page(dst_pmap,
5689 vm_page_free_pages_toq(&free,
5694 if (dstmpte->wire_count >= srcmpte->wire_count)
5704 PMAP_UNLOCK(src_pmap);
5705 PMAP_UNLOCK(dst_pmap);
5709 * Zero the specified hardware page.
5712 pmap_zero_page(vm_page_t m)
5714 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5716 pagezero((void *)va);
5720 * Zero an an area within a single hardware page. off and size must not
5721 * cover an area beyond a single hardware page.
5724 pmap_zero_page_area(vm_page_t m, int off, int size)
5726 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5728 if (off == 0 && size == PAGE_SIZE)
5729 pagezero((void *)va);
5731 bzero((char *)va + off, size);
5735 * Copy 1 specified hardware page to another.
5738 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5740 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5741 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5743 pagecopy((void *)src, (void *)dst);
5746 int unmapped_buf_allowed = 1;
5749 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5750 vm_offset_t b_offset, int xfersize)
5754 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5758 while (xfersize > 0) {
5759 a_pg_offset = a_offset & PAGE_MASK;
5760 pages[0] = ma[a_offset >> PAGE_SHIFT];
5761 b_pg_offset = b_offset & PAGE_MASK;
5762 pages[1] = mb[b_offset >> PAGE_SHIFT];
5763 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5764 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5765 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5766 a_cp = (char *)vaddr[0] + a_pg_offset;
5767 b_cp = (char *)vaddr[1] + b_pg_offset;
5768 bcopy(a_cp, b_cp, cnt);
5769 if (__predict_false(mapped))
5770 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5778 * Returns true if the pmap's pv is one of the first
5779 * 16 pvs linked to from this page. This count may
5780 * be changed upwards or downwards in the future; it
5781 * is only necessary that true be returned for a small
5782 * subset of pmaps for proper page aging.
5785 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5787 struct md_page *pvh;
5788 struct rwlock *lock;
5793 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5794 ("pmap_page_exists_quick: page %p is not managed", m));
5796 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5798 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5799 if (PV_PMAP(pv) == pmap) {
5807 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5808 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5809 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5810 if (PV_PMAP(pv) == pmap) {
5824 * pmap_page_wired_mappings:
5826 * Return the number of managed mappings to the given physical page
5830 pmap_page_wired_mappings(vm_page_t m)
5832 struct rwlock *lock;
5833 struct md_page *pvh;
5837 int count, md_gen, pvh_gen;
5839 if ((m->oflags & VPO_UNMANAGED) != 0)
5841 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5845 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5847 if (!PMAP_TRYLOCK(pmap)) {
5848 md_gen = m->md.pv_gen;
5852 if (md_gen != m->md.pv_gen) {
5857 pte = pmap_pte(pmap, pv->pv_va);
5858 if ((*pte & PG_W) != 0)
5862 if ((m->flags & PG_FICTITIOUS) == 0) {
5863 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5864 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5866 if (!PMAP_TRYLOCK(pmap)) {
5867 md_gen = m->md.pv_gen;
5868 pvh_gen = pvh->pv_gen;
5872 if (md_gen != m->md.pv_gen ||
5873 pvh_gen != pvh->pv_gen) {
5878 pte = pmap_pde(pmap, pv->pv_va);
5879 if ((*pte & PG_W) != 0)
5889 * Returns TRUE if the given page is mapped individually or as part of
5890 * a 2mpage. Otherwise, returns FALSE.
5893 pmap_page_is_mapped(vm_page_t m)
5895 struct rwlock *lock;
5898 if ((m->oflags & VPO_UNMANAGED) != 0)
5900 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5902 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5903 ((m->flags & PG_FICTITIOUS) == 0 &&
5904 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5910 * Destroy all managed, non-wired mappings in the given user-space
5911 * pmap. This pmap cannot be active on any processor besides the
5914 * This function cannot be applied to the kernel pmap. Moreover, it
5915 * is not intended for general use. It is only to be used during
5916 * process termination. Consequently, it can be implemented in ways
5917 * that make it faster than pmap_remove(). First, it can more quickly
5918 * destroy mappings by iterating over the pmap's collection of PV
5919 * entries, rather than searching the page table. Second, it doesn't
5920 * have to test and clear the page table entries atomically, because
5921 * no processor is currently accessing the user address space. In
5922 * particular, a page table entry's dirty bit won't change state once
5923 * this function starts.
5925 * Although this function destroys all of the pmap's managed,
5926 * non-wired mappings, it can delay and batch the invalidation of TLB
5927 * entries without calling pmap_delayed_invl_started() and
5928 * pmap_delayed_invl_finished(). Because the pmap is not active on
5929 * any other processor, none of these TLB entries will ever be used
5930 * before their eventual invalidation. Consequently, there is no need
5931 * for either pmap_remove_all() or pmap_remove_write() to wait for
5932 * that eventual TLB invalidation.
5935 pmap_remove_pages(pmap_t pmap)
5938 pt_entry_t *pte, tpte;
5939 pt_entry_t PG_M, PG_RW, PG_V;
5940 struct spglist free;
5941 vm_page_t m, mpte, mt;
5943 struct md_page *pvh;
5944 struct pv_chunk *pc, *npc;
5945 struct rwlock *lock;
5947 uint64_t inuse, bitmask;
5948 int allfree, field, freed, idx;
5949 boolean_t superpage;
5953 * Assert that the given pmap is only active on the current
5954 * CPU. Unfortunately, we cannot block another CPU from
5955 * activating the pmap while this function is executing.
5957 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5960 cpuset_t other_cpus;
5962 other_cpus = all_cpus;
5964 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5965 CPU_AND(&other_cpus, &pmap->pm_active);
5967 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5972 PG_M = pmap_modified_bit(pmap);
5973 PG_V = pmap_valid_bit(pmap);
5974 PG_RW = pmap_rw_bit(pmap);
5978 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5981 for (field = 0; field < _NPCM; field++) {
5982 inuse = ~pc->pc_map[field] & pc_freemask[field];
5983 while (inuse != 0) {
5985 bitmask = 1UL << bit;
5986 idx = field * 64 + bit;
5987 pv = &pc->pc_pventry[idx];
5990 pte = pmap_pdpe(pmap, pv->pv_va);
5992 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5994 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5997 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5999 pte = &pte[pmap_pte_index(pv->pv_va)];
6003 * Keep track whether 'tpte' is a
6004 * superpage explicitly instead of
6005 * relying on PG_PS being set.
6007 * This is because PG_PS is numerically
6008 * identical to PG_PTE_PAT and thus a
6009 * regular page could be mistaken for
6015 if ((tpte & PG_V) == 0) {
6016 panic("bad pte va %lx pte %lx",
6021 * We cannot remove wired pages from a process' mapping at this time
6029 pa = tpte & PG_PS_FRAME;
6031 pa = tpte & PG_FRAME;
6033 m = PHYS_TO_VM_PAGE(pa);
6034 KASSERT(m->phys_addr == pa,
6035 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6036 m, (uintmax_t)m->phys_addr,
6039 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6040 m < &vm_page_array[vm_page_array_size],
6041 ("pmap_remove_pages: bad tpte %#jx",
6047 * Update the vm_page_t clean/reference bits.
6049 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6051 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6057 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6060 pc->pc_map[field] |= bitmask;
6062 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6063 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6064 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6066 if (TAILQ_EMPTY(&pvh->pv_list)) {
6067 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6068 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6069 TAILQ_EMPTY(&mt->md.pv_list))
6070 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6072 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6074 pmap_resident_count_dec(pmap, 1);
6075 KASSERT(mpte->wire_count == NPTEPG,
6076 ("pmap_remove_pages: pte page wire count error"));
6077 mpte->wire_count = 0;
6078 pmap_add_delayed_free_list(mpte, &free, FALSE);
6081 pmap_resident_count_dec(pmap, 1);
6082 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6084 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6085 TAILQ_EMPTY(&m->md.pv_list) &&
6086 (m->flags & PG_FICTITIOUS) == 0) {
6087 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6088 if (TAILQ_EMPTY(&pvh->pv_list))
6089 vm_page_aflag_clear(m, PGA_WRITEABLE);
6092 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6096 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6097 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6098 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6100 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6106 pmap_invalidate_all(pmap);
6108 vm_page_free_pages_toq(&free, true);
6112 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6114 struct rwlock *lock;
6116 struct md_page *pvh;
6117 pt_entry_t *pte, mask;
6118 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6120 int md_gen, pvh_gen;
6124 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6127 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6129 if (!PMAP_TRYLOCK(pmap)) {
6130 md_gen = m->md.pv_gen;
6134 if (md_gen != m->md.pv_gen) {
6139 pte = pmap_pte(pmap, pv->pv_va);
6142 PG_M = pmap_modified_bit(pmap);
6143 PG_RW = pmap_rw_bit(pmap);
6144 mask |= PG_RW | PG_M;
6147 PG_A = pmap_accessed_bit(pmap);
6148 PG_V = pmap_valid_bit(pmap);
6149 mask |= PG_V | PG_A;
6151 rv = (*pte & mask) == mask;
6156 if ((m->flags & PG_FICTITIOUS) == 0) {
6157 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6158 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6160 if (!PMAP_TRYLOCK(pmap)) {
6161 md_gen = m->md.pv_gen;
6162 pvh_gen = pvh->pv_gen;
6166 if (md_gen != m->md.pv_gen ||
6167 pvh_gen != pvh->pv_gen) {
6172 pte = pmap_pde(pmap, pv->pv_va);
6175 PG_M = pmap_modified_bit(pmap);
6176 PG_RW = pmap_rw_bit(pmap);
6177 mask |= PG_RW | PG_M;
6180 PG_A = pmap_accessed_bit(pmap);
6181 PG_V = pmap_valid_bit(pmap);
6182 mask |= PG_V | PG_A;
6184 rv = (*pte & mask) == mask;
6198 * Return whether or not the specified physical page was modified
6199 * in any physical maps.
6202 pmap_is_modified(vm_page_t m)
6205 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6206 ("pmap_is_modified: page %p is not managed", m));
6209 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6210 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6211 * is clear, no PTEs can have PG_M set.
6213 VM_OBJECT_ASSERT_WLOCKED(m->object);
6214 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6216 return (pmap_page_test_mappings(m, FALSE, TRUE));
6220 * pmap_is_prefaultable:
6222 * Return whether or not the specified virtual address is eligible
6226 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6229 pt_entry_t *pte, PG_V;
6232 PG_V = pmap_valid_bit(pmap);
6235 pde = pmap_pde(pmap, addr);
6236 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6237 pte = pmap_pde_to_pte(pde, addr);
6238 rv = (*pte & PG_V) == 0;
6245 * pmap_is_referenced:
6247 * Return whether or not the specified physical page was referenced
6248 * in any physical maps.
6251 pmap_is_referenced(vm_page_t m)
6254 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6255 ("pmap_is_referenced: page %p is not managed", m));
6256 return (pmap_page_test_mappings(m, TRUE, FALSE));
6260 * Clear the write and modified bits in each of the given page's mappings.
6263 pmap_remove_write(vm_page_t m)
6265 struct md_page *pvh;
6267 struct rwlock *lock;
6268 pv_entry_t next_pv, pv;
6270 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6272 int pvh_gen, md_gen;
6274 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6275 ("pmap_remove_write: page %p is not managed", m));
6278 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6279 * set by another thread while the object is locked. Thus,
6280 * if PGA_WRITEABLE is clear, no page table entries need updating.
6282 VM_OBJECT_ASSERT_WLOCKED(m->object);
6283 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6285 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6286 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6287 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6290 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6292 if (!PMAP_TRYLOCK(pmap)) {
6293 pvh_gen = pvh->pv_gen;
6297 if (pvh_gen != pvh->pv_gen) {
6303 PG_RW = pmap_rw_bit(pmap);
6305 pde = pmap_pde(pmap, va);
6306 if ((*pde & PG_RW) != 0)
6307 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6308 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6309 ("inconsistent pv lock %p %p for page %p",
6310 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6313 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6315 if (!PMAP_TRYLOCK(pmap)) {
6316 pvh_gen = pvh->pv_gen;
6317 md_gen = m->md.pv_gen;
6321 if (pvh_gen != pvh->pv_gen ||
6322 md_gen != m->md.pv_gen) {
6328 PG_M = pmap_modified_bit(pmap);
6329 PG_RW = pmap_rw_bit(pmap);
6330 pde = pmap_pde(pmap, pv->pv_va);
6331 KASSERT((*pde & PG_PS) == 0,
6332 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6334 pte = pmap_pde_to_pte(pde, pv->pv_va);
6337 if (oldpte & PG_RW) {
6338 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6341 if ((oldpte & PG_M) != 0)
6343 pmap_invalidate_page(pmap, pv->pv_va);
6348 vm_page_aflag_clear(m, PGA_WRITEABLE);
6349 pmap_delayed_invl_wait(m);
6352 static __inline boolean_t
6353 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6356 if (!pmap_emulate_ad_bits(pmap))
6359 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6362 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6363 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6364 * if the EPT_PG_WRITE bit is set.
6366 if ((pte & EPT_PG_WRITE) != 0)
6370 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6372 if ((pte & EPT_PG_EXECUTE) == 0 ||
6373 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6380 * pmap_ts_referenced:
6382 * Return a count of reference bits for a page, clearing those bits.
6383 * It is not necessary for every reference bit to be cleared, but it
6384 * is necessary that 0 only be returned when there are truly no
6385 * reference bits set.
6387 * As an optimization, update the page's dirty field if a modified bit is
6388 * found while counting reference bits. This opportunistic update can be
6389 * performed at low cost and can eliminate the need for some future calls
6390 * to pmap_is_modified(). However, since this function stops after
6391 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6392 * dirty pages. Those dirty pages will only be detected by a future call
6393 * to pmap_is_modified().
6395 * A DI block is not needed within this function, because
6396 * invalidations are performed before the PV list lock is
6400 pmap_ts_referenced(vm_page_t m)
6402 struct md_page *pvh;
6405 struct rwlock *lock;
6406 pd_entry_t oldpde, *pde;
6407 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6410 int cleared, md_gen, not_cleared, pvh_gen;
6411 struct spglist free;
6414 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6415 ("pmap_ts_referenced: page %p is not managed", m));
6418 pa = VM_PAGE_TO_PHYS(m);
6419 lock = PHYS_TO_PV_LIST_LOCK(pa);
6420 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6424 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6425 goto small_mappings;
6431 if (!PMAP_TRYLOCK(pmap)) {
6432 pvh_gen = pvh->pv_gen;
6436 if (pvh_gen != pvh->pv_gen) {
6441 PG_A = pmap_accessed_bit(pmap);
6442 PG_M = pmap_modified_bit(pmap);
6443 PG_RW = pmap_rw_bit(pmap);
6445 pde = pmap_pde(pmap, pv->pv_va);
6447 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6449 * Although "oldpde" is mapping a 2MB page, because
6450 * this function is called at a 4KB page granularity,
6451 * we only update the 4KB page under test.
6455 if ((oldpde & PG_A) != 0) {
6457 * Since this reference bit is shared by 512 4KB
6458 * pages, it should not be cleared every time it is
6459 * tested. Apply a simple "hash" function on the
6460 * physical page number, the virtual superpage number,
6461 * and the pmap address to select one 4KB page out of
6462 * the 512 on which testing the reference bit will
6463 * result in clearing that reference bit. This
6464 * function is designed to avoid the selection of the
6465 * same 4KB page for every 2MB page mapping.
6467 * On demotion, a mapping that hasn't been referenced
6468 * is simply destroyed. To avoid the possibility of a
6469 * subsequent page fault on a demoted wired mapping,
6470 * always leave its reference bit set. Moreover,
6471 * since the superpage is wired, the current state of
6472 * its reference bit won't affect page replacement.
6474 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6475 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6476 (oldpde & PG_W) == 0) {
6477 if (safe_to_clear_referenced(pmap, oldpde)) {
6478 atomic_clear_long(pde, PG_A);
6479 pmap_invalidate_page(pmap, pv->pv_va);
6481 } else if (pmap_demote_pde_locked(pmap, pde,
6482 pv->pv_va, &lock)) {
6484 * Remove the mapping to a single page
6485 * so that a subsequent access may
6486 * repromote. Since the underlying
6487 * page table page is fully populated,
6488 * this removal never frees a page
6492 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6494 pte = pmap_pde_to_pte(pde, va);
6495 pmap_remove_pte(pmap, pte, va, *pde,
6497 pmap_invalidate_page(pmap, va);
6503 * The superpage mapping was removed
6504 * entirely and therefore 'pv' is no
6512 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6513 ("inconsistent pv lock %p %p for page %p",
6514 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6519 /* Rotate the PV list if it has more than one entry. */
6520 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6521 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6522 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6525 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6527 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6529 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6536 if (!PMAP_TRYLOCK(pmap)) {
6537 pvh_gen = pvh->pv_gen;
6538 md_gen = m->md.pv_gen;
6542 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6547 PG_A = pmap_accessed_bit(pmap);
6548 PG_M = pmap_modified_bit(pmap);
6549 PG_RW = pmap_rw_bit(pmap);
6550 pde = pmap_pde(pmap, pv->pv_va);
6551 KASSERT((*pde & PG_PS) == 0,
6552 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6554 pte = pmap_pde_to_pte(pde, pv->pv_va);
6555 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6557 if ((*pte & PG_A) != 0) {
6558 if (safe_to_clear_referenced(pmap, *pte)) {
6559 atomic_clear_long(pte, PG_A);
6560 pmap_invalidate_page(pmap, pv->pv_va);
6562 } else if ((*pte & PG_W) == 0) {
6564 * Wired pages cannot be paged out so
6565 * doing accessed bit emulation for
6566 * them is wasted effort. We do the
6567 * hard work for unwired pages only.
6569 pmap_remove_pte(pmap, pte, pv->pv_va,
6570 *pde, &free, &lock);
6571 pmap_invalidate_page(pmap, pv->pv_va);
6576 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6577 ("inconsistent pv lock %p %p for page %p",
6578 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6583 /* Rotate the PV list if it has more than one entry. */
6584 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6585 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6586 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6589 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6590 not_cleared < PMAP_TS_REFERENCED_MAX);
6593 vm_page_free_pages_toq(&free, true);
6594 return (cleared + not_cleared);
6598 * Apply the given advice to the specified range of addresses within the
6599 * given pmap. Depending on the advice, clear the referenced and/or
6600 * modified flags in each mapping and set the mapped page's dirty field.
6603 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6605 struct rwlock *lock;
6606 pml4_entry_t *pml4e;
6608 pd_entry_t oldpde, *pde;
6609 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6610 vm_offset_t va, va_next;
6612 boolean_t anychanged;
6614 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6618 * A/D bit emulation requires an alternate code path when clearing
6619 * the modified and accessed bits below. Since this function is
6620 * advisory in nature we skip it entirely for pmaps that require
6621 * A/D bit emulation.
6623 if (pmap_emulate_ad_bits(pmap))
6626 PG_A = pmap_accessed_bit(pmap);
6627 PG_G = pmap_global_bit(pmap);
6628 PG_M = pmap_modified_bit(pmap);
6629 PG_V = pmap_valid_bit(pmap);
6630 PG_RW = pmap_rw_bit(pmap);
6632 pmap_delayed_invl_started();
6634 for (; sva < eva; sva = va_next) {
6635 pml4e = pmap_pml4e(pmap, sva);
6636 if ((*pml4e & PG_V) == 0) {
6637 va_next = (sva + NBPML4) & ~PML4MASK;
6642 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6643 if ((*pdpe & PG_V) == 0) {
6644 va_next = (sva + NBPDP) & ~PDPMASK;
6649 va_next = (sva + NBPDR) & ~PDRMASK;
6652 pde = pmap_pdpe_to_pde(pdpe, sva);
6654 if ((oldpde & PG_V) == 0)
6656 else if ((oldpde & PG_PS) != 0) {
6657 if ((oldpde & PG_MANAGED) == 0)
6660 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6665 * The large page mapping was destroyed.
6671 * Unless the page mappings are wired, remove the
6672 * mapping to a single page so that a subsequent
6673 * access may repromote. Since the underlying page
6674 * table page is fully populated, this removal never
6675 * frees a page table page.
6677 if ((oldpde & PG_W) == 0) {
6678 pte = pmap_pde_to_pte(pde, sva);
6679 KASSERT((*pte & PG_V) != 0,
6680 ("pmap_advise: invalid PTE"));
6681 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6691 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6693 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6695 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6696 if (advice == MADV_DONTNEED) {
6698 * Future calls to pmap_is_modified()
6699 * can be avoided by making the page
6702 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6705 atomic_clear_long(pte, PG_M | PG_A);
6706 } else if ((*pte & PG_A) != 0)
6707 atomic_clear_long(pte, PG_A);
6711 if ((*pte & PG_G) != 0) {
6718 if (va != va_next) {
6719 pmap_invalidate_range(pmap, va, sva);
6724 pmap_invalidate_range(pmap, va, sva);
6727 pmap_invalidate_all(pmap);
6729 pmap_delayed_invl_finished();
6733 * Clear the modify bits on the specified physical page.
6736 pmap_clear_modify(vm_page_t m)
6738 struct md_page *pvh;
6740 pv_entry_t next_pv, pv;
6741 pd_entry_t oldpde, *pde;
6742 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6743 struct rwlock *lock;
6745 int md_gen, pvh_gen;
6747 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6748 ("pmap_clear_modify: page %p is not managed", m));
6749 VM_OBJECT_ASSERT_WLOCKED(m->object);
6750 KASSERT(!vm_page_xbusied(m),
6751 ("pmap_clear_modify: page %p is exclusive busied", m));
6754 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6755 * If the object containing the page is locked and the page is not
6756 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6758 if ((m->aflags & PGA_WRITEABLE) == 0)
6760 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6761 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6762 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6765 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6767 if (!PMAP_TRYLOCK(pmap)) {
6768 pvh_gen = pvh->pv_gen;
6772 if (pvh_gen != pvh->pv_gen) {
6777 PG_M = pmap_modified_bit(pmap);
6778 PG_V = pmap_valid_bit(pmap);
6779 PG_RW = pmap_rw_bit(pmap);
6781 pde = pmap_pde(pmap, va);
6783 if ((oldpde & PG_RW) != 0) {
6784 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6785 if ((oldpde & PG_W) == 0) {
6787 * Write protect the mapping to a
6788 * single page so that a subsequent
6789 * write access may repromote.
6791 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6793 pte = pmap_pde_to_pte(pde, va);
6795 if ((oldpte & PG_V) != 0) {
6796 while (!atomic_cmpset_long(pte,
6798 oldpte & ~(PG_M | PG_RW)))
6801 pmap_invalidate_page(pmap, va);
6808 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6810 if (!PMAP_TRYLOCK(pmap)) {
6811 md_gen = m->md.pv_gen;
6812 pvh_gen = pvh->pv_gen;
6816 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6821 PG_M = pmap_modified_bit(pmap);
6822 PG_RW = pmap_rw_bit(pmap);
6823 pde = pmap_pde(pmap, pv->pv_va);
6824 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6825 " a 2mpage in page %p's pv list", m));
6826 pte = pmap_pde_to_pte(pde, pv->pv_va);
6827 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6828 atomic_clear_long(pte, PG_M);
6829 pmap_invalidate_page(pmap, pv->pv_va);
6837 * Miscellaneous support routines follow
6840 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6841 static __inline void
6842 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6847 * The cache mode bits are all in the low 32-bits of the
6848 * PTE, so we can just spin on updating the low 32-bits.
6851 opte = *(u_int *)pte;
6852 npte = opte & ~mask;
6854 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6857 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6858 static __inline void
6859 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6864 * The cache mode bits are all in the low 32-bits of the
6865 * PDE, so we can just spin on updating the low 32-bits.
6868 opde = *(u_int *)pde;
6869 npde = opde & ~mask;
6871 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6875 * Map a set of physical memory pages into the kernel virtual
6876 * address space. Return a pointer to where it is mapped. This
6877 * routine is intended to be used for mapping device memory,
6881 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6883 struct pmap_preinit_mapping *ppim;
6884 vm_offset_t va, offset;
6888 offset = pa & PAGE_MASK;
6889 size = round_page(offset + size);
6890 pa = trunc_page(pa);
6892 if (!pmap_initialized) {
6894 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6895 ppim = pmap_preinit_mapping + i;
6896 if (ppim->va == 0) {
6900 ppim->va = virtual_avail;
6901 virtual_avail += size;
6907 panic("%s: too many preinit mappings", __func__);
6910 * If we have a preinit mapping, re-use it.
6912 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6913 ppim = pmap_preinit_mapping + i;
6914 if (ppim->pa == pa && ppim->sz == size &&
6916 return ((void *)(ppim->va + offset));
6919 * If the specified range of physical addresses fits within
6920 * the direct map window, use the direct map.
6922 if (pa < dmaplimit && pa + size < dmaplimit) {
6923 va = PHYS_TO_DMAP(pa);
6924 if (!pmap_change_attr(va, size, mode))
6925 return ((void *)(va + offset));
6927 va = kva_alloc(size);
6929 panic("%s: Couldn't allocate KVA", __func__);
6931 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6932 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6933 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6934 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6935 return ((void *)(va + offset));
6939 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6942 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6946 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6949 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6953 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6955 struct pmap_preinit_mapping *ppim;
6959 /* If we gave a direct map region in pmap_mapdev, do nothing */
6960 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6962 offset = va & PAGE_MASK;
6963 size = round_page(offset + size);
6964 va = trunc_page(va);
6965 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6966 ppim = pmap_preinit_mapping + i;
6967 if (ppim->va == va && ppim->sz == size) {
6968 if (pmap_initialized)
6974 if (va + size == virtual_avail)
6979 if (pmap_initialized)
6984 * Tries to demote a 1GB page mapping.
6987 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6989 pdp_entry_t newpdpe, oldpdpe;
6990 pd_entry_t *firstpde, newpde, *pde;
6991 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6995 PG_A = pmap_accessed_bit(pmap);
6996 PG_M = pmap_modified_bit(pmap);
6997 PG_V = pmap_valid_bit(pmap);
6998 PG_RW = pmap_rw_bit(pmap);
7000 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7002 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7003 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7004 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7005 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7006 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7007 " in pmap %p", va, pmap);
7010 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7011 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7012 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7013 KASSERT((oldpdpe & PG_A) != 0,
7014 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7015 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7016 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7020 * Initialize the page directory page.
7022 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7028 * Demote the mapping.
7033 * Invalidate a stale recursive mapping of the page directory page.
7035 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7037 pmap_pdpe_demotions++;
7038 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7039 " in pmap %p", va, pmap);
7044 * Sets the memory attribute for the specified page.
7047 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7050 m->md.pat_mode = ma;
7053 * If "m" is a normal page, update its direct mapping. This update
7054 * can be relied upon to perform any cache operations that are
7055 * required for data coherence.
7057 if ((m->flags & PG_FICTITIOUS) == 0 &&
7058 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7060 panic("memory attribute change on the direct map failed");
7064 * Changes the specified virtual address range's memory type to that given by
7065 * the parameter "mode". The specified virtual address range must be
7066 * completely contained within either the direct map or the kernel map. If
7067 * the virtual address range is contained within the kernel map, then the
7068 * memory type for each of the corresponding ranges of the direct map is also
7069 * changed. (The corresponding ranges of the direct map are those ranges that
7070 * map the same physical pages as the specified virtual address range.) These
7071 * changes to the direct map are necessary because Intel describes the
7072 * behavior of their processors as "undefined" if two or more mappings to the
7073 * same physical page have different memory types.
7075 * Returns zero if the change completed successfully, and either EINVAL or
7076 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7077 * of the virtual address range was not mapped, and ENOMEM is returned if
7078 * there was insufficient memory available to complete the change. In the
7079 * latter case, the memory type may have been changed on some part of the
7080 * virtual address range or the direct map.
7083 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7087 PMAP_LOCK(kernel_pmap);
7088 error = pmap_change_attr_locked(va, size, mode);
7089 PMAP_UNLOCK(kernel_pmap);
7094 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
7096 vm_offset_t base, offset, tmpva;
7097 vm_paddr_t pa_start, pa_end, pa_end1;
7101 int cache_bits_pte, cache_bits_pde, error;
7104 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7105 base = trunc_page(va);
7106 offset = va & PAGE_MASK;
7107 size = round_page(offset + size);
7110 * Only supported on kernel virtual addresses, including the direct
7111 * map but excluding the recursive map.
7113 if (base < DMAP_MIN_ADDRESS)
7116 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7117 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7121 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7122 * into 4KB pages if required.
7124 for (tmpva = base; tmpva < base + size; ) {
7125 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7126 if (pdpe == NULL || *pdpe == 0)
7128 if (*pdpe & PG_PS) {
7130 * If the current 1GB page already has the required
7131 * memory type, then we need not demote this page. Just
7132 * increment tmpva to the next 1GB page frame.
7134 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7135 tmpva = trunc_1gpage(tmpva) + NBPDP;
7140 * If the current offset aligns with a 1GB page frame
7141 * and there is at least 1GB left within the range, then
7142 * we need not break down this page into 2MB pages.
7144 if ((tmpva & PDPMASK) == 0 &&
7145 tmpva + PDPMASK < base + size) {
7149 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7152 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7157 * If the current 2MB page already has the required
7158 * memory type, then we need not demote this page. Just
7159 * increment tmpva to the next 2MB page frame.
7161 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7162 tmpva = trunc_2mpage(tmpva) + NBPDR;
7167 * If the current offset aligns with a 2MB page frame
7168 * and there is at least 2MB left within the range, then
7169 * we need not break down this page into 4KB pages.
7171 if ((tmpva & PDRMASK) == 0 &&
7172 tmpva + PDRMASK < base + size) {
7176 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7179 pte = pmap_pde_to_pte(pde, tmpva);
7187 * Ok, all the pages exist, so run through them updating their
7188 * cache mode if required.
7190 pa_start = pa_end = 0;
7191 for (tmpva = base; tmpva < base + size; ) {
7192 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7193 if (*pdpe & PG_PS) {
7194 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7195 pmap_pde_attr(pdpe, cache_bits_pde,
7199 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7200 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7201 if (pa_start == pa_end) {
7202 /* Start physical address run. */
7203 pa_start = *pdpe & PG_PS_FRAME;
7204 pa_end = pa_start + NBPDP;
7205 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7208 /* Run ended, update direct map. */
7209 error = pmap_change_attr_locked(
7210 PHYS_TO_DMAP(pa_start),
7211 pa_end - pa_start, mode);
7214 /* Start physical address run. */
7215 pa_start = *pdpe & PG_PS_FRAME;
7216 pa_end = pa_start + NBPDP;
7219 tmpva = trunc_1gpage(tmpva) + NBPDP;
7222 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7224 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7225 pmap_pde_attr(pde, cache_bits_pde,
7229 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7230 (*pde & PG_PS_FRAME) < dmaplimit) {
7231 if (pa_start == pa_end) {
7232 /* Start physical address run. */
7233 pa_start = *pde & PG_PS_FRAME;
7234 pa_end = pa_start + NBPDR;
7235 } else if (pa_end == (*pde & PG_PS_FRAME))
7238 /* Run ended, update direct map. */
7239 error = pmap_change_attr_locked(
7240 PHYS_TO_DMAP(pa_start),
7241 pa_end - pa_start, mode);
7244 /* Start physical address run. */
7245 pa_start = *pde & PG_PS_FRAME;
7246 pa_end = pa_start + NBPDR;
7249 tmpva = trunc_2mpage(tmpva) + NBPDR;
7251 pte = pmap_pde_to_pte(pde, tmpva);
7252 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7253 pmap_pte_attr(pte, cache_bits_pte,
7257 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7258 (*pte & PG_FRAME) < dmaplimit) {
7259 if (pa_start == pa_end) {
7260 /* Start physical address run. */
7261 pa_start = *pte & PG_FRAME;
7262 pa_end = pa_start + PAGE_SIZE;
7263 } else if (pa_end == (*pte & PG_FRAME))
7264 pa_end += PAGE_SIZE;
7266 /* Run ended, update direct map. */
7267 error = pmap_change_attr_locked(
7268 PHYS_TO_DMAP(pa_start),
7269 pa_end - pa_start, mode);
7272 /* Start physical address run. */
7273 pa_start = *pte & PG_FRAME;
7274 pa_end = pa_start + PAGE_SIZE;
7280 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7281 pa_end1 = MIN(pa_end, dmaplimit);
7282 if (pa_start != pa_end1)
7283 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7284 pa_end1 - pa_start, mode);
7288 * Flush CPU caches if required to make sure any data isn't cached that
7289 * shouldn't be, etc.
7292 pmap_invalidate_range(kernel_pmap, base, tmpva);
7293 pmap_invalidate_cache_range(base, tmpva, FALSE);
7299 * Demotes any mapping within the direct map region that covers more than the
7300 * specified range of physical addresses. This range's size must be a power
7301 * of two and its starting address must be a multiple of its size. Since the
7302 * demotion does not change any attributes of the mapping, a TLB invalidation
7303 * is not mandatory. The caller may, however, request a TLB invalidation.
7306 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7315 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7316 KASSERT((base & (len - 1)) == 0,
7317 ("pmap_demote_DMAP: base is not a multiple of len"));
7318 if (len < NBPDP && base < dmaplimit) {
7319 va = PHYS_TO_DMAP(base);
7321 PMAP_LOCK(kernel_pmap);
7322 pdpe = pmap_pdpe(kernel_pmap, va);
7323 if ((*pdpe & X86_PG_V) == 0)
7324 panic("pmap_demote_DMAP: invalid PDPE");
7325 if ((*pdpe & PG_PS) != 0) {
7326 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7327 panic("pmap_demote_DMAP: PDPE failed");
7331 pde = pmap_pdpe_to_pde(pdpe, va);
7332 if ((*pde & X86_PG_V) == 0)
7333 panic("pmap_demote_DMAP: invalid PDE");
7334 if ((*pde & PG_PS) != 0) {
7335 if (!pmap_demote_pde(kernel_pmap, pde, va))
7336 panic("pmap_demote_DMAP: PDE failed");
7340 if (changed && invalidate)
7341 pmap_invalidate_page(kernel_pmap, va);
7342 PMAP_UNLOCK(kernel_pmap);
7347 * perform the pmap work for mincore
7350 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7353 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7357 PG_A = pmap_accessed_bit(pmap);
7358 PG_M = pmap_modified_bit(pmap);
7359 PG_V = pmap_valid_bit(pmap);
7360 PG_RW = pmap_rw_bit(pmap);
7364 pdep = pmap_pde(pmap, addr);
7365 if (pdep != NULL && (*pdep & PG_V)) {
7366 if (*pdep & PG_PS) {
7368 /* Compute the physical address of the 4KB page. */
7369 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7371 val = MINCORE_SUPER;
7373 pte = *pmap_pde_to_pte(pdep, addr);
7374 pa = pte & PG_FRAME;
7382 if ((pte & PG_V) != 0) {
7383 val |= MINCORE_INCORE;
7384 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7385 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7386 if ((pte & PG_A) != 0)
7387 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7389 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7390 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7391 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7392 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7393 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7396 PA_UNLOCK_COND(*locked_pa);
7402 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7404 uint32_t gen, new_gen, pcid_next;
7406 CRITICAL_ASSERT(curthread);
7407 gen = PCPU_GET(pcid_gen);
7408 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7409 return (pti ? 0 : CR3_PCID_SAVE);
7410 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7411 return (CR3_PCID_SAVE);
7412 pcid_next = PCPU_GET(pcid_next);
7413 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7414 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7415 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7416 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7417 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7421 PCPU_SET(pcid_gen, new_gen);
7422 pcid_next = PMAP_PCID_KERN + 1;
7426 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7427 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7428 PCPU_SET(pcid_next, pcid_next + 1);
7433 pmap_activate_sw(struct thread *td)
7435 pmap_t oldpmap, pmap;
7436 struct invpcid_descr d;
7437 uint64_t cached, cr3, kcr3, kern_pti_cached, rsp0, ucr3;
7440 struct amd64tss *tssp;
7443 oldpmap = PCPU_GET(curpmap);
7444 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7445 if (oldpmap == pmap)
7447 cpuid = PCPU_GET(cpuid);
7449 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7451 CPU_SET(cpuid, &pmap->pm_active);
7454 if (pmap_pcid_enabled) {
7455 cached = pmap_pcid_alloc(pmap, cpuid);
7456 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
7457 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7458 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7459 pmap->pm_pcids[cpuid].pm_pcid));
7460 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7461 pmap == kernel_pmap,
7462 ("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
7463 td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7466 * If the INVPCID instruction is not available,
7467 * invltlb_pcid_handler() is used for handle
7468 * invalidate_all IPI, which checks for curpmap ==
7469 * smp_tlb_pmap. Below operations sequence has a
7470 * window where %CR3 is loaded with the new pmap's
7471 * PML4 address, but curpmap value is not yet updated.
7472 * This causes invltlb IPI handler, called between the
7473 * updates, to execute as NOP, which leaves stale TLB
7476 * Note that the most typical use of
7477 * pmap_activate_sw(), from the context switch, is
7478 * immune to this race, because interrupts are
7479 * disabled (while the thread lock is owned), and IPI
7480 * happends after curpmap is updated. Protect other
7481 * callers in a similar way, by disabling interrupts
7482 * around the %cr3 register reload and curpmap
7486 rflags = intr_disable();
7488 kern_pti_cached = pti ? 0 : cached;
7489 if (!kern_pti_cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
7490 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7493 PCPU_SET(curpmap, pmap);
7495 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7496 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7499 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7501 * Manually invalidate translations cached
7502 * from the user page table. They are not
7503 * flushed by reload of cr3 with the kernel
7504 * page table pointer above.
7506 if (invpcid_works) {
7507 d.pcid = PMAP_PCID_USER_PT |
7508 pmap->pm_pcids[cpuid].pm_pcid;
7511 invpcid(&d, INVPCID_CTX);
7513 pmap_pti_pcid_invalidate(ucr3, kcr3);
7517 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7518 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7521 intr_restore(rflags);
7523 PCPU_INC(pm_save_cnt);
7524 } else if (cr3 != pmap->pm_cr3) {
7525 load_cr3(pmap->pm_cr3);
7526 PCPU_SET(curpmap, pmap);
7528 PCPU_SET(kcr3, pmap->pm_cr3);
7529 PCPU_SET(ucr3, pmap->pm_ucr3);
7532 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
7533 rsp0 = ((vm_offset_t)PCPU_PTR(pti_stack) +
7534 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful;
7535 tssp = PCPU_GET(tssp);
7536 tssp->tss_rsp0 = rsp0;
7539 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7541 CPU_CLR(cpuid, &oldpmap->pm_active);
7546 pmap_activate(struct thread *td)
7550 pmap_activate_sw(td);
7555 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7560 * Increase the starting virtual address of the given mapping if a
7561 * different alignment might result in more superpage mappings.
7564 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7565 vm_offset_t *addr, vm_size_t size)
7567 vm_offset_t superpage_offset;
7571 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7572 offset += ptoa(object->pg_color);
7573 superpage_offset = offset & PDRMASK;
7574 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
7575 (*addr & PDRMASK) == superpage_offset)
7577 if ((*addr & PDRMASK) < superpage_offset)
7578 *addr = (*addr & ~PDRMASK) + superpage_offset;
7580 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
7584 static unsigned long num_dirty_emulations;
7585 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
7586 &num_dirty_emulations, 0, NULL);
7588 static unsigned long num_accessed_emulations;
7589 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
7590 &num_accessed_emulations, 0, NULL);
7592 static unsigned long num_superpage_accessed_emulations;
7593 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
7594 &num_superpage_accessed_emulations, 0, NULL);
7596 static unsigned long ad_emulation_superpage_promotions;
7597 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
7598 &ad_emulation_superpage_promotions, 0, NULL);
7599 #endif /* INVARIANTS */
7602 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
7605 struct rwlock *lock;
7606 #if VM_NRESERVLEVEL > 0
7610 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
7612 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
7613 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
7615 if (!pmap_emulate_ad_bits(pmap))
7618 PG_A = pmap_accessed_bit(pmap);
7619 PG_M = pmap_modified_bit(pmap);
7620 PG_V = pmap_valid_bit(pmap);
7621 PG_RW = pmap_rw_bit(pmap);
7627 pde = pmap_pde(pmap, va);
7628 if (pde == NULL || (*pde & PG_V) == 0)
7631 if ((*pde & PG_PS) != 0) {
7632 if (ftype == VM_PROT_READ) {
7634 atomic_add_long(&num_superpage_accessed_emulations, 1);
7642 pte = pmap_pde_to_pte(pde, va);
7643 if ((*pte & PG_V) == 0)
7646 if (ftype == VM_PROT_WRITE) {
7647 if ((*pte & PG_RW) == 0)
7650 * Set the modified and accessed bits simultaneously.
7652 * Intel EPT PTEs that do software emulation of A/D bits map
7653 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
7654 * An EPT misconfiguration is triggered if the PTE is writable
7655 * but not readable (WR=10). This is avoided by setting PG_A
7656 * and PG_M simultaneously.
7658 *pte |= PG_M | PG_A;
7663 #if VM_NRESERVLEVEL > 0
7664 /* try to promote the mapping */
7665 if (va < VM_MAXUSER_ADDRESS)
7666 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7670 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7672 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
7673 pmap_ps_enabled(pmap) &&
7674 (m->flags & PG_FICTITIOUS) == 0 &&
7675 vm_reserv_level_iffullpop(m) == 0) {
7676 pmap_promote_pde(pmap, pde, va, &lock);
7678 atomic_add_long(&ad_emulation_superpage_promotions, 1);
7684 if (ftype == VM_PROT_WRITE)
7685 atomic_add_long(&num_dirty_emulations, 1);
7687 atomic_add_long(&num_accessed_emulations, 1);
7689 rv = 0; /* success */
7698 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
7703 pt_entry_t *pte, PG_V;
7707 PG_V = pmap_valid_bit(pmap);
7710 pml4 = pmap_pml4e(pmap, va);
7712 if ((*pml4 & PG_V) == 0)
7715 pdp = pmap_pml4e_to_pdpe(pml4, va);
7717 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
7720 pde = pmap_pdpe_to_pde(pdp, va);
7722 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
7725 pte = pmap_pde_to_pte(pde, va);
7734 * Get the kernel virtual address of a set of physical pages. If there are
7735 * physical addresses not covered by the DMAP perform a transient mapping
7736 * that will be removed when calling pmap_unmap_io_transient.
7738 * \param page The pages the caller wishes to obtain the virtual
7739 * address on the kernel memory map.
7740 * \param vaddr On return contains the kernel virtual memory address
7741 * of the pages passed in the page parameter.
7742 * \param count Number of pages passed in.
7743 * \param can_fault TRUE if the thread using the mapped pages can take
7744 * page faults, FALSE otherwise.
7746 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7747 * finished or FALSE otherwise.
7751 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7752 boolean_t can_fault)
7755 boolean_t needs_mapping;
7757 int cache_bits, error __unused, i;
7760 * Allocate any KVA space that we need, this is done in a separate
7761 * loop to prevent calling vmem_alloc while pinned.
7763 needs_mapping = FALSE;
7764 for (i = 0; i < count; i++) {
7765 paddr = VM_PAGE_TO_PHYS(page[i]);
7766 if (__predict_false(paddr >= dmaplimit)) {
7767 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7768 M_BESTFIT | M_WAITOK, &vaddr[i]);
7769 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7770 needs_mapping = TRUE;
7772 vaddr[i] = PHYS_TO_DMAP(paddr);
7776 /* Exit early if everything is covered by the DMAP */
7781 * NB: The sequence of updating a page table followed by accesses
7782 * to the corresponding pages used in the !DMAP case is subject to
7783 * the situation described in the "AMD64 Architecture Programmer's
7784 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7785 * Coherency Considerations". Therefore, issuing the INVLPG right
7786 * after modifying the PTE bits is crucial.
7790 for (i = 0; i < count; i++) {
7791 paddr = VM_PAGE_TO_PHYS(page[i]);
7792 if (paddr >= dmaplimit) {
7795 * Slow path, since we can get page faults
7796 * while mappings are active don't pin the
7797 * thread to the CPU and instead add a global
7798 * mapping visible to all CPUs.
7800 pmap_qenter(vaddr[i], &page[i], 1);
7802 pte = vtopte(vaddr[i]);
7803 cache_bits = pmap_cache_bits(kernel_pmap,
7804 page[i]->md.pat_mode, 0);
7805 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7812 return (needs_mapping);
7816 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7817 boolean_t can_fault)
7824 for (i = 0; i < count; i++) {
7825 paddr = VM_PAGE_TO_PHYS(page[i]);
7826 if (paddr >= dmaplimit) {
7828 pmap_qremove(vaddr[i], 1);
7829 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7835 pmap_quick_enter_page(vm_page_t m)
7839 paddr = VM_PAGE_TO_PHYS(m);
7840 if (paddr < dmaplimit)
7841 return (PHYS_TO_DMAP(paddr));
7842 mtx_lock_spin(&qframe_mtx);
7843 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7844 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7845 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7850 pmap_quick_remove_page(vm_offset_t addr)
7855 pte_store(vtopte(qframe), 0);
7857 mtx_unlock_spin(&qframe_mtx);
7861 pmap_pti_alloc_page(void)
7865 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7866 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
7867 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
7872 pmap_pti_free_page(vm_page_t m)
7875 KASSERT(m->wire_count > 0, ("page %p not wired", m));
7876 if (!vm_page_unwire_noq(m))
7878 vm_page_free_zero(m);
7892 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
7893 VM_OBJECT_WLOCK(pti_obj);
7894 pml4_pg = pmap_pti_alloc_page();
7895 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
7896 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
7897 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
7898 pdpe = pmap_pti_pdpe(va);
7899 pmap_pti_wire_pte(pdpe);
7901 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
7902 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
7903 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
7904 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
7905 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
7906 sizeof(struct gate_descriptor) * NIDT, false);
7907 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
7908 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
7910 /* Doublefault stack IST 1 */
7911 va = common_tss[i].tss_ist1;
7912 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7913 /* NMI stack IST 2 */
7914 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
7915 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7916 /* MC# stack IST 3 */
7917 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
7918 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7919 /* DB# stack IST 4 */
7920 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
7921 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
7923 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
7924 (vm_offset_t)etext, true);
7925 pti_finalized = true;
7926 VM_OBJECT_WUNLOCK(pti_obj);
7928 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
7930 static pdp_entry_t *
7931 pmap_pti_pdpe(vm_offset_t va)
7933 pml4_entry_t *pml4e;
7936 vm_pindex_t pml4_idx;
7939 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7941 pml4_idx = pmap_pml4e_index(va);
7942 pml4e = &pti_pml4[pml4_idx];
7946 panic("pml4 alloc after finalization\n");
7947 m = pmap_pti_alloc_page();
7949 pmap_pti_free_page(m);
7950 mphys = *pml4e & ~PAGE_MASK;
7952 mphys = VM_PAGE_TO_PHYS(m);
7953 *pml4e = mphys | X86_PG_RW | X86_PG_V;
7956 mphys = *pml4e & ~PAGE_MASK;
7958 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
7963 pmap_pti_wire_pte(void *pte)
7967 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7968 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
7973 pmap_pti_unwire_pde(void *pde, bool only_ref)
7977 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7978 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
7979 MPASS(m->wire_count > 0);
7980 MPASS(only_ref || m->wire_count > 1);
7981 pmap_pti_free_page(m);
7985 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
7990 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7991 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
7992 MPASS(m->wire_count > 0);
7993 if (pmap_pti_free_page(m)) {
7994 pde = pmap_pti_pde(va);
7995 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
7997 pmap_pti_unwire_pde(pde, false);
8002 pmap_pti_pde(vm_offset_t va)
8010 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8012 pdpe = pmap_pti_pdpe(va);
8014 m = pmap_pti_alloc_page();
8016 pmap_pti_free_page(m);
8017 MPASS((*pdpe & X86_PG_PS) == 0);
8018 mphys = *pdpe & ~PAGE_MASK;
8020 mphys = VM_PAGE_TO_PHYS(m);
8021 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8024 MPASS((*pdpe & X86_PG_PS) == 0);
8025 mphys = *pdpe & ~PAGE_MASK;
8028 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8029 pd_idx = pmap_pde_index(va);
8035 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8042 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8044 pde = pmap_pti_pde(va);
8045 if (unwire_pde != NULL) {
8047 pmap_pti_wire_pte(pde);
8050 m = pmap_pti_alloc_page();
8052 pmap_pti_free_page(m);
8053 MPASS((*pde & X86_PG_PS) == 0);
8054 mphys = *pde & ~(PAGE_MASK | pg_nx);
8056 mphys = VM_PAGE_TO_PHYS(m);
8057 *pde = mphys | X86_PG_RW | X86_PG_V;
8058 if (unwire_pde != NULL)
8059 *unwire_pde = false;
8062 MPASS((*pde & X86_PG_PS) == 0);
8063 mphys = *pde & ~(PAGE_MASK | pg_nx);
8066 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8067 pte += pmap_pte_index(va);
8073 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8077 pt_entry_t *pte, ptev;
8080 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8082 sva = trunc_page(sva);
8083 MPASS(sva > VM_MAXUSER_ADDRESS);
8084 eva = round_page(eva);
8086 for (; sva < eva; sva += PAGE_SIZE) {
8087 pte = pmap_pti_pte(sva, &unwire_pde);
8088 pa = pmap_kextract(sva);
8089 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8090 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8091 VM_MEMATTR_DEFAULT, FALSE);
8093 pte_store(pte, ptev);
8094 pmap_pti_wire_pte(pte);
8096 KASSERT(!pti_finalized,
8097 ("pti overlap after fin %#lx %#lx %#lx",
8099 KASSERT(*pte == ptev,
8100 ("pti non-identical pte after fin %#lx %#lx %#lx",
8104 pde = pmap_pti_pde(sva);
8105 pmap_pti_unwire_pde(pde, true);
8111 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
8116 VM_OBJECT_WLOCK(pti_obj);
8117 pmap_pti_add_kva_locked(sva, eva, exec);
8118 VM_OBJECT_WUNLOCK(pti_obj);
8122 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
8129 sva = rounddown2(sva, PAGE_SIZE);
8130 MPASS(sva > VM_MAXUSER_ADDRESS);
8131 eva = roundup2(eva, PAGE_SIZE);
8133 VM_OBJECT_WLOCK(pti_obj);
8134 for (va = sva; va < eva; va += PAGE_SIZE) {
8135 pte = pmap_pti_pte(va, NULL);
8136 KASSERT((*pte & X86_PG_V) != 0,
8137 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8138 (u_long)pte, *pte));
8140 pmap_pti_unwire_pte(pte, va);
8142 pmap_invalidate_range(kernel_pmap, sva, eva);
8143 VM_OBJECT_WUNLOCK(pti_obj);
8146 #include "opt_ddb.h"
8148 #include <sys/kdb.h>
8149 #include <ddb/ddb.h>
8151 DB_SHOW_COMMAND(pte, pmap_print_pte)
8157 pt_entry_t *pte, PG_V;
8161 db_printf("show pte addr\n");
8164 va = (vm_offset_t)addr;
8166 if (kdb_thread != NULL)
8167 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
8169 pmap = PCPU_GET(curpmap);
8171 PG_V = pmap_valid_bit(pmap);
8172 pml4 = pmap_pml4e(pmap, va);
8173 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
8174 if ((*pml4 & PG_V) == 0) {
8178 pdp = pmap_pml4e_to_pdpe(pml4, va);
8179 db_printf(" pdpe %#016lx", *pdp);
8180 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
8184 pde = pmap_pdpe_to_pde(pdp, va);
8185 db_printf(" pde %#016lx", *pde);
8186 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
8190 pte = pmap_pde_to_pte(pde, va);
8191 db_printf(" pte %#016lx\n", *pte);
8194 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
8199 a = (vm_paddr_t)addr;
8200 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
8202 db_printf("show phys2dmap addr\n");