2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
39 #ifndef _MACHINE_CPUFUNC_H_
40 #define _MACHINE_CPUFUNC_H_
43 #error this file needs sys/cdefs.h as a prerequisite
46 struct region_descriptor;
48 #define readb(va) (*(volatile uint8_t *) (va))
49 #define readw(va) (*(volatile uint16_t *) (va))
50 #define readl(va) (*(volatile uint32_t *) (va))
51 #define readq(va) (*(volatile uint64_t *) (va))
53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
63 __asm __volatile("int $3");
71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
75 static __inline u_long
80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
93 static __inline u_long
98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
106 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
110 clflushopt(u_long addr)
113 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
120 __asm __volatile("clwb %0" : : "m" (*(char *)addr));
127 __asm __volatile("clts");
133 __asm __volatile("cli" : : : "memory");
137 do_cpuid(u_int ax, u_int *p)
139 __asm __volatile("cpuid"
140 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
145 cpuid_count(u_int ax, u_int cx, u_int *p)
147 __asm __volatile("cpuid"
148 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
149 : "0" (ax), "c" (cx));
155 __asm __volatile("sti");
160 #define HAVE_INLINE_FFS
161 #define ffs(x) __builtin_ffs(x)
163 #define HAVE_INLINE_FFSL
168 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
171 #define HAVE_INLINE_FFSLL
174 ffsll(long long mask)
176 return (ffsl((long)mask));
179 #define HAVE_INLINE_FLS
184 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
187 #define HAVE_INLINE_FLSL
192 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
195 #define HAVE_INLINE_FLSLL
198 flsll(long long mask)
200 return (flsl((long)mask));
208 __asm __volatile("hlt");
211 static __inline u_char
216 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
220 static __inline u_int
225 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
230 insb(u_int port, void *addr, size_t count)
232 __asm __volatile("cld; rep; insb"
233 : "+D" (addr), "+c" (count)
239 insw(u_int port, void *addr, size_t count)
241 __asm __volatile("cld; rep; insw"
242 : "+D" (addr), "+c" (count)
248 insl(u_int port, void *addr, size_t count)
250 __asm __volatile("cld; rep; insl"
251 : "+D" (addr), "+c" (count)
259 __asm __volatile("invd");
262 static __inline u_short
267 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
272 outb(u_int port, u_char data)
274 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
278 outl(u_int port, u_int data)
280 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
284 outsb(u_int port, const void *addr, size_t count)
286 __asm __volatile("cld; rep; outsb"
287 : "+S" (addr), "+c" (count)
292 outsw(u_int port, const void *addr, size_t count)
294 __asm __volatile("cld; rep; outsw"
295 : "+S" (addr), "+c" (count)
300 outsl(u_int port, const void *addr, size_t count)
302 __asm __volatile("cld; rep; outsl"
303 : "+S" (addr), "+c" (count)
308 outw(u_int port, u_short data)
310 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
313 static __inline u_long
318 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
326 __asm __volatile("lfence" : : : "memory");
333 __asm __volatile("mfence" : : : "memory");
340 __asm __volatile("sfence" : : : "memory");
346 __asm __volatile("pause");
349 static __inline u_long
354 __asm __volatile("pushfq; popq %0" : "=r" (rf));
358 static __inline uint64_t
363 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
364 return (low | ((uint64_t)high << 32));
367 static __inline uint32_t
372 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
376 static __inline uint64_t
381 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
382 return (low | ((uint64_t)high << 32));
385 static __inline uint64_t
390 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
391 return (low | ((uint64_t)high << 32));
394 static __inline uint32_t
399 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
406 __asm __volatile("wbinvd");
410 write_rflags(u_long rf)
412 __asm __volatile("pushq %0; popfq" : : "r" (rf));
416 wrmsr(u_int msr, uint64_t newval)
422 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
426 load_cr0(u_long data)
429 __asm __volatile("movq %0,%%cr0" : : "r" (data));
432 static __inline u_long
437 __asm __volatile("movq %%cr0,%0" : "=r" (data));
441 static __inline u_long
446 __asm __volatile("movq %%cr2,%0" : "=r" (data));
451 load_cr3(u_long data)
454 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
457 static __inline u_long
462 __asm __volatile("movq %%cr3,%0" : "=r" (data));
467 load_cr4(u_long data)
469 __asm __volatile("movq %0,%%cr4" : : "r" (data));
472 static __inline u_long
477 __asm __volatile("movq %%cr4,%0" : "=r" (data));
481 static __inline u_long
486 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
487 return (low | ((uint64_t)high << 32));
491 load_xcr(u_int reg, u_long val)
497 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
501 * Global TLB flush (except for thise for pages marked PG_G)
511 #define CR4_PGE 0x00000080 /* Page global enable */
515 * Perform the guaranteed invalidation of all TLB entries. This
516 * includes the global entries, and entries in all PCIDs, not only the
517 * current context. The function works both on non-PCID CPUs and CPUs
518 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
519 * Operations that Invalidate TLBs and Paging-Structure Caches.
527 load_cr4(cr4 & ~CR4_PGE);
529 * Although preemption at this point could be detrimental to
530 * performance, it would not lead to an error. PG_G is simply
531 * ignored if CR4.PGE is clear. Moreover, in case this block
532 * is re-entered, the load_cr4() either above or below will
533 * modify CR4.PGE flushing the TLB.
535 load_cr4(cr4 | CR4_PGE);
539 * TLB flush for an individual page (even if it has PG_G).
540 * Only works on 486+ CPUs (i386 does not have PG_G).
546 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
549 #define INVPCID_ADDR 0
550 #define INVPCID_CTX 1
551 #define INVPCID_CTXGLOB 2
552 #define INVPCID_ALLCTX 3
554 struct invpcid_descr {
555 uint64_t pcid:12 __packed;
556 uint64_t pad:52 __packed;
561 invpcid(struct invpcid_descr *d, int type)
564 __asm __volatile("invpcid (%0),%1"
565 : : "r" (d), "r" ((u_long)type) : "memory");
568 static __inline u_short
572 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
576 static __inline u_short
580 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
584 static __inline u_short
588 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
595 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
601 __asm __volatile("movw %0,%%es" : : "rm" (sel));
605 cpu_monitor(const void *addr, u_long extensions, u_int hints)
608 __asm __volatile("monitor"
609 : : "a" (addr), "c" (extensions), "d" (hints));
613 cpu_mwait(u_long extensions, u_int hints)
616 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
620 /* This is defined in <machine/specialreg.h> but is too painful to get to */
622 #define MSR_FSBASE 0xc0000100
627 /* Preserve the fsbase value across the selector load */
628 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
629 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
633 #define MSR_GSBASE 0xc0000101
639 * Preserve the gsbase value across the selector load.
640 * Note that we have to disable interrupts because the gsbase
641 * being trashed happens to be the kernel gsbase at the time.
643 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
644 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
647 /* Usable by userland */
651 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
657 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
661 static __inline uint64_t
666 __asm __volatile("rdfsbase %0" : "=r" (x));
674 __asm __volatile("wrfsbase %0" : : "r" (x));
677 static __inline uint64_t
682 __asm __volatile("rdgsbase %0" : "=r" (x));
690 __asm __volatile("wrgsbase %0" : : "r" (x));
694 bare_lgdt(struct region_descriptor *addr)
696 __asm __volatile("lgdt (%0)" : : "r" (addr));
700 sgdt(struct region_descriptor *addr)
705 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
709 lidt(struct region_descriptor *addr)
711 __asm __volatile("lidt (%0)" : : "r" (addr));
715 sidt(struct region_descriptor *addr)
720 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
726 __asm __volatile("lldt %0" : : "r" (sel));
729 static __inline u_short
734 __asm __volatile("sldt %0" : "=r" (sel));
741 __asm __volatile("ltr %0" : : "r" (sel));
744 static __inline uint32_t
749 __asm __volatile("str %0" : "=r" (sel));
753 static __inline uint64_t
757 __asm __volatile("movq %%dr0,%0" : "=r" (data));
762 load_dr0(uint64_t dr0)
764 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
767 static __inline uint64_t
771 __asm __volatile("movq %%dr1,%0" : "=r" (data));
776 load_dr1(uint64_t dr1)
778 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
781 static __inline uint64_t
785 __asm __volatile("movq %%dr2,%0" : "=r" (data));
790 load_dr2(uint64_t dr2)
792 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
795 static __inline uint64_t
799 __asm __volatile("movq %%dr3,%0" : "=r" (data));
804 load_dr3(uint64_t dr3)
806 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
809 static __inline uint64_t
813 __asm __volatile("movq %%dr4,%0" : "=r" (data));
818 load_dr4(uint64_t dr4)
820 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
823 static __inline uint64_t
827 __asm __volatile("movq %%dr5,%0" : "=r" (data));
832 load_dr5(uint64_t dr5)
834 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
837 static __inline uint64_t
841 __asm __volatile("movq %%dr6,%0" : "=r" (data));
846 load_dr6(uint64_t dr6)
848 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
851 static __inline uint64_t
855 __asm __volatile("movq %%dr7,%0" : "=r" (data));
860 load_dr7(uint64_t dr7)
862 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
865 static __inline register_t
870 rflags = read_rflags();
876 intr_restore(register_t rflags)
878 write_rflags(rflags);
885 __asm __volatile("stac" : : : "cc");
892 __asm __volatile("clac" : : : "cc");
895 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
897 int breakpoint(void);
898 u_int bsfl(u_int mask);
899 u_int bsrl(u_int mask);
900 void clflush(u_long addr);
902 void cpuid_count(u_int ax, u_int cx, u_int *p);
903 void disable_intr(void);
904 void do_cpuid(u_int ax, u_int *p);
905 void enable_intr(void);
907 void ia32_pause(void);
908 u_char inb(u_int port);
909 u_int inl(u_int port);
910 void insb(u_int port, void *addr, size_t count);
911 void insl(u_int port, void *addr, size_t count);
912 void insw(u_int port, void *addr, size_t count);
913 register_t intr_disable(void);
914 void intr_restore(register_t rf);
916 void invlpg(u_int addr);
918 u_short inw(u_int port);
919 void lidt(struct region_descriptor *addr);
920 void lldt(u_short sel);
921 void load_cr0(u_long cr0);
922 void load_cr3(u_long cr3);
923 void load_cr4(u_long cr4);
924 void load_dr0(uint64_t dr0);
925 void load_dr1(uint64_t dr1);
926 void load_dr2(uint64_t dr2);
927 void load_dr3(uint64_t dr3);
928 void load_dr4(uint64_t dr4);
929 void load_dr5(uint64_t dr5);
930 void load_dr6(uint64_t dr6);
931 void load_dr7(uint64_t dr7);
932 void load_fs(u_short sel);
933 void load_gs(u_short sel);
934 void ltr(u_short sel);
935 void outb(u_int port, u_char data);
936 void outl(u_int port, u_int data);
937 void outsb(u_int port, const void *addr, size_t count);
938 void outsl(u_int port, const void *addr, size_t count);
939 void outsw(u_int port, const void *addr, size_t count);
940 void outw(u_int port, u_short data);
945 uint64_t rdmsr(u_int msr);
946 uint32_t rdmsr32(u_int msr);
947 uint64_t rdpmc(u_int pmc);
956 uint64_t rdtsc(void);
957 u_long read_rflags(void);
961 void write_rflags(u_int rf);
962 void wrmsr(u_int msr, uint64_t newval);
964 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
966 void reset_dbregs(void);
969 int rdmsr_safe(u_int msr, uint64_t *val);
970 int wrmsr_safe(u_int msr, uint64_t newval);
973 #endif /* !_MACHINE_CPUFUNC_H_ */