2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1993 The Regents of the University of California.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Functions to provide access to special i386 instructions.
37 * This in included in sys/systm.h, and that file should be
38 * used in preference to this.
41 #ifndef _MACHINE_CPUFUNC_H_
42 #define _MACHINE_CPUFUNC_H_
45 #error this file needs sys/cdefs.h as a prerequisite
48 struct region_descriptor;
50 #define readb(va) (*(volatile uint8_t *) (va))
51 #define readw(va) (*(volatile uint16_t *) (va))
52 #define readl(va) (*(volatile uint32_t *) (va))
53 #define readq(va) (*(volatile uint64_t *) (va))
55 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
58 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
60 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
65 __asm __volatile("int $3");
68 static __inline __pure2 u_int
73 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
77 static __inline __pure2 u_long
82 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
86 static __inline __pure2 u_int
91 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
95 static __inline __pure2 u_long
100 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
108 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
112 clflushopt(u_long addr)
115 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
122 __asm __volatile("clwb %0" : : "m" (*(char *)addr));
129 __asm __volatile("clts");
135 __asm __volatile("cli" : : : "memory");
139 do_cpuid(u_int ax, u_int *p)
141 __asm __volatile("cpuid"
142 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
147 cpuid_count(u_int ax, u_int cx, u_int *p)
149 __asm __volatile("cpuid"
150 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
151 : "0" (ax), "c" (cx));
157 __asm __volatile("sti");
162 #define HAVE_INLINE_FFS
163 #define ffs(x) __builtin_ffs(x)
165 #define HAVE_INLINE_FFSL
167 static __inline __pure2 int
171 return (__builtin_ffsl(mask));
174 #define HAVE_INLINE_FFSLL
176 static __inline __pure2 int
177 ffsll(long long mask)
179 return (ffsl((long)mask));
182 #define HAVE_INLINE_FLS
184 static __inline __pure2 int
187 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
190 #define HAVE_INLINE_FLSL
192 static __inline __pure2 int
195 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
198 #define HAVE_INLINE_FLSLL
200 static __inline __pure2 int
201 flsll(long long mask)
203 return (flsl((long)mask));
211 __asm __volatile("hlt");
214 static __inline u_char
219 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
223 static __inline u_int
228 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
233 insb(u_int port, void *addr, size_t count)
235 __asm __volatile("rep; insb"
236 : "+D" (addr), "+c" (count)
242 insw(u_int port, void *addr, size_t count)
244 __asm __volatile("rep; insw"
245 : "+D" (addr), "+c" (count)
251 insl(u_int port, void *addr, size_t count)
253 __asm __volatile("rep; insl"
254 : "+D" (addr), "+c" (count)
262 __asm __volatile("invd");
265 static __inline u_short
270 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
275 outb(u_int port, u_char data)
277 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
281 outl(u_int port, u_int data)
283 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
287 outsb(u_int port, const void *addr, size_t count)
289 __asm __volatile("rep; outsb"
290 : "+S" (addr), "+c" (count)
295 outsw(u_int port, const void *addr, size_t count)
297 __asm __volatile("rep; outsw"
298 : "+S" (addr), "+c" (count)
303 outsl(u_int port, const void *addr, size_t count)
305 __asm __volatile("rep; outsl"
306 : "+S" (addr), "+c" (count)
311 outw(u_int port, u_short data)
313 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
316 static __inline u_long
321 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
329 __asm __volatile("lfence" : : : "memory");
336 __asm __volatile("mfence" : : : "memory");
343 __asm __volatile("sfence" : : : "memory");
349 __asm __volatile("pause");
352 static __inline u_long
357 __asm __volatile("pushfq; popq %0" : "=r" (rf));
361 static __inline uint64_t
366 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
367 return (low | ((uint64_t)high << 32));
370 static __inline uint32_t
375 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
379 static __inline uint64_t
384 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
385 return (low | ((uint64_t)high << 32));
388 static __inline uint64_t
393 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
394 return (low | ((uint64_t)high << 32));
397 static __inline uint64_t
402 __asm __volatile("rdtscp" : "=a" (low), "=d" (high) : : "ecx");
403 return (low | ((uint64_t)high << 32));
406 static __inline uint32_t
411 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
418 __asm __volatile("wbinvd");
422 write_rflags(u_long rf)
424 __asm __volatile("pushq %0; popfq" : : "r" (rf));
428 wrmsr(u_int msr, uint64_t newval)
434 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
438 load_cr0(u_long data)
441 __asm __volatile("movq %0,%%cr0" : : "r" (data));
444 static __inline u_long
449 __asm __volatile("movq %%cr0,%0" : "=r" (data));
453 static __inline u_long
458 __asm __volatile("movq %%cr2,%0" : "=r" (data));
463 load_cr3(u_long data)
466 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
469 static __inline u_long
474 __asm __volatile("movq %%cr3,%0" : "=r" (data));
479 load_cr4(u_long data)
481 __asm __volatile("movq %0,%%cr4" : : "r" (data));
484 static __inline u_long
489 __asm __volatile("movq %%cr4,%0" : "=r" (data));
493 static __inline u_long
498 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
499 return (low | ((uint64_t)high << 32));
503 load_xcr(u_int reg, u_long val)
509 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
513 * Global TLB flush (except for thise for pages marked PG_G)
523 #define CR4_PGE 0x00000080 /* Page global enable */
527 * Perform the guaranteed invalidation of all TLB entries. This
528 * includes the global entries, and entries in all PCIDs, not only the
529 * current context. The function works both on non-PCID CPUs and CPUs
530 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
531 * Operations that Invalidate TLBs and Paging-Structure Caches.
539 load_cr4(cr4 & ~CR4_PGE);
541 * Although preemption at this point could be detrimental to
542 * performance, it would not lead to an error. PG_G is simply
543 * ignored if CR4.PGE is clear. Moreover, in case this block
544 * is re-entered, the load_cr4() either above or below will
545 * modify CR4.PGE flushing the TLB.
547 load_cr4(cr4 | CR4_PGE);
551 * TLB flush for an individual page (even if it has PG_G).
552 * Only works on 486+ CPUs (i386 does not have PG_G).
558 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
561 #define INVPCID_ADDR 0
562 #define INVPCID_CTX 1
563 #define INVPCID_CTXGLOB 2
564 #define INVPCID_ALLCTX 3
566 struct invpcid_descr {
567 uint64_t pcid:12 __packed;
568 uint64_t pad:52 __packed;
573 invpcid(struct invpcid_descr *d, int type)
576 __asm __volatile("invpcid (%0),%1"
577 : : "r" (d), "r" ((u_long)type) : "memory");
580 static __inline u_short
584 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
588 static __inline u_short
592 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
596 static __inline u_short
600 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
607 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
613 __asm __volatile("movw %0,%%es" : : "rm" (sel));
617 cpu_monitor(const void *addr, u_long extensions, u_int hints)
620 __asm __volatile("monitor"
621 : : "a" (addr), "c" (extensions), "d" (hints));
625 cpu_mwait(u_long extensions, u_int hints)
628 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
631 static __inline uint32_t
636 __asm __volatile("rdpkru" : "=a" (res) : "c" (0) : "edx");
641 wrpkru(uint32_t mask)
644 __asm __volatile("wrpkru" : : "a" (mask), "c" (0), "d" (0));
648 /* This is defined in <machine/specialreg.h> but is too painful to get to */
650 #define MSR_FSBASE 0xc0000100
655 /* Preserve the fsbase value across the selector load */
656 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
657 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
661 #define MSR_GSBASE 0xc0000101
667 * Preserve the gsbase value across the selector load.
668 * Note that we have to disable interrupts because the gsbase
669 * being trashed happens to be the kernel gsbase at the time.
671 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
672 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
675 /* Usable by userland */
679 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
685 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
689 static __inline uint64_t
694 __asm __volatile("rdfsbase %0" : "=r" (x));
702 __asm __volatile("wrfsbase %0" : : "r" (x));
705 static __inline uint64_t
710 __asm __volatile("rdgsbase %0" : "=r" (x));
718 __asm __volatile("wrgsbase %0" : : "r" (x));
722 bare_lgdt(struct region_descriptor *addr)
724 __asm __volatile("lgdt (%0)" : : "r" (addr));
728 sgdt(struct region_descriptor *addr)
733 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
737 lidt(struct region_descriptor *addr)
739 __asm __volatile("lidt (%0)" : : "r" (addr));
743 sidt(struct region_descriptor *addr)
748 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
754 __asm __volatile("lldt %0" : : "r" (sel));
757 static __inline u_short
762 __asm __volatile("sldt %0" : "=r" (sel));
769 __asm __volatile("ltr %0" : : "r" (sel));
772 static __inline uint32_t
777 __asm __volatile("str %0" : "=r" (sel));
781 static __inline uint64_t
785 __asm __volatile("movq %%dr0,%0" : "=r" (data));
790 load_dr0(uint64_t dr0)
792 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
795 static __inline uint64_t
799 __asm __volatile("movq %%dr1,%0" : "=r" (data));
804 load_dr1(uint64_t dr1)
806 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
809 static __inline uint64_t
813 __asm __volatile("movq %%dr2,%0" : "=r" (data));
818 load_dr2(uint64_t dr2)
820 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
823 static __inline uint64_t
827 __asm __volatile("movq %%dr3,%0" : "=r" (data));
832 load_dr3(uint64_t dr3)
834 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
837 static __inline uint64_t
841 __asm __volatile("movq %%dr6,%0" : "=r" (data));
846 load_dr6(uint64_t dr6)
848 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
851 static __inline uint64_t
855 __asm __volatile("movq %%dr7,%0" : "=r" (data));
860 load_dr7(uint64_t dr7)
862 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
865 static __inline register_t
870 rflags = read_rflags();
876 intr_restore(register_t rflags)
878 write_rflags(rflags);
885 __asm __volatile("stac" : : : "cc");
892 __asm __volatile("clac" : : : "cc");
918 int sgx_encls(uint32_t eax, uint64_t rbx, uint64_t rcx, uint64_t rdx);
921 sgx_ecreate(void *pginfo, void *secs)
924 return (sgx_encls(SGX_ECREATE, (uint64_t)pginfo,
929 sgx_eadd(void *pginfo, void *epc)
932 return (sgx_encls(SGX_EADD, (uint64_t)pginfo,
937 sgx_einit(void *sigstruct, void *secs, void *einittoken)
940 return (sgx_encls(SGX_EINIT, (uint64_t)sigstruct,
941 (uint64_t)secs, (uint64_t)einittoken));
945 sgx_eextend(void *secs, void *epc)
948 return (sgx_encls(SGX_EEXTEND, (uint64_t)secs,
956 return (sgx_encls(SGX_EPA, SGX_PT_VA, (uint64_t)epc, 0));
960 sgx_eldu(uint64_t rbx, uint64_t rcx,
964 return (sgx_encls(SGX_ELDU, rbx, rcx, rdx));
968 sgx_eremove(void *epc)
971 return (sgx_encls(SGX_EREMOVE, 0, (uint64_t)epc, 0));
974 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
976 int breakpoint(void);
977 u_int bsfl(u_int mask);
978 u_int bsrl(u_int mask);
979 void clflush(u_long addr);
981 void cpuid_count(u_int ax, u_int cx, u_int *p);
982 void disable_intr(void);
983 void do_cpuid(u_int ax, u_int *p);
984 void enable_intr(void);
986 void ia32_pause(void);
987 u_char inb(u_int port);
988 u_int inl(u_int port);
989 void insb(u_int port, void *addr, size_t count);
990 void insl(u_int port, void *addr, size_t count);
991 void insw(u_int port, void *addr, size_t count);
992 register_t intr_disable(void);
993 void intr_restore(register_t rf);
995 void invlpg(u_int addr);
997 u_short inw(u_int port);
998 void lidt(struct region_descriptor *addr);
999 void lldt(u_short sel);
1000 void load_cr0(u_long cr0);
1001 void load_cr3(u_long cr3);
1002 void load_cr4(u_long cr4);
1003 void load_dr0(uint64_t dr0);
1004 void load_dr1(uint64_t dr1);
1005 void load_dr2(uint64_t dr2);
1006 void load_dr3(uint64_t dr3);
1007 void load_dr6(uint64_t dr6);
1008 void load_dr7(uint64_t dr7);
1009 void load_fs(u_short sel);
1010 void load_gs(u_short sel);
1011 void ltr(u_short sel);
1012 void outb(u_int port, u_char data);
1013 void outl(u_int port, u_int data);
1014 void outsb(u_int port, const void *addr, size_t count);
1015 void outsl(u_int port, const void *addr, size_t count);
1016 void outsw(u_int port, const void *addr, size_t count);
1017 void outw(u_int port, u_short data);
1022 uint64_t rdmsr(u_int msr);
1023 uint32_t rdmsr32(u_int msr);
1024 uint64_t rdpmc(u_int pmc);
1025 uint64_t rdr0(void);
1026 uint64_t rdr1(void);
1027 uint64_t rdr2(void);
1028 uint64_t rdr3(void);
1029 uint64_t rdr6(void);
1030 uint64_t rdr7(void);
1031 uint64_t rdtsc(void);
1032 u_long read_rflags(void);
1036 void write_rflags(u_int rf);
1037 void wrmsr(u_int msr, uint64_t newval);
1039 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
1041 void reset_dbregs(void);
1044 int rdmsr_safe(u_int msr, uint64_t *val);
1045 int wrmsr_safe(u_int msr, uint64_t newval);
1048 #endif /* !_MACHINE_CPUFUNC_H_ */