2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1993 The Regents of the University of California.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Functions to provide access to special i386 instructions.
37 * This in included in sys/systm.h, and that file should be
38 * used in preference to this.
41 #ifndef _MACHINE_CPUFUNC_H_
42 #define _MACHINE_CPUFUNC_H_
45 #error this file needs sys/cdefs.h as a prerequisite
48 struct region_descriptor;
50 #define readb(va) (*(volatile uint8_t *) (va))
51 #define readw(va) (*(volatile uint16_t *) (va))
52 #define readl(va) (*(volatile uint32_t *) (va))
53 #define readq(va) (*(volatile uint64_t *) (va))
55 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
58 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
60 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
65 __asm __volatile("int $3");
68 #define bsfl(mask) __builtin_ctz(mask)
70 #define bsfq(mask) __builtin_ctzl(mask)
72 #define bsrl(mask) (__builtin_clz(mask) ^ 0x1f)
74 #define bsrq(mask) (__builtin_clzl(mask) ^ 0x3f)
80 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
84 clflushopt(u_long addr)
87 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
94 __asm __volatile("clwb %0" : : "m" (*(char *)addr));
101 __asm __volatile("clts");
107 __asm __volatile("cli" : : : "memory");
111 do_cpuid(u_int ax, u_int *p)
113 __asm __volatile("cpuid"
114 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
119 cpuid_count(u_int ax, u_int cx, u_int *p)
121 __asm __volatile("cpuid"
122 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
123 : "0" (ax), "c" (cx));
129 __asm __volatile("sti");
134 #define HAVE_INLINE_FFS
135 #define ffs(x) __builtin_ffs(x)
137 #define HAVE_INLINE_FFSL
138 #define ffsl(x) __builtin_ffsl(x)
140 #define HAVE_INLINE_FFSLL
141 #define ffsll(x) __builtin_ffsll(x)
143 #define HAVE_INLINE_FLS
145 static __inline __pure2 int
148 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
151 #define HAVE_INLINE_FLSL
153 static __inline __pure2 int
156 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
159 #define HAVE_INLINE_FLSLL
161 static __inline __pure2 int
162 flsll(long long mask)
164 return (flsl((long)mask));
172 __asm __volatile("hlt");
175 static __inline u_char
180 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
184 static __inline u_int
189 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
194 insb(u_int port, void *addr, size_t count)
196 __asm __volatile("rep; insb"
197 : "+D" (addr), "+c" (count)
203 insw(u_int port, void *addr, size_t count)
205 __asm __volatile("rep; insw"
206 : "+D" (addr), "+c" (count)
212 insl(u_int port, void *addr, size_t count)
214 __asm __volatile("rep; insl"
215 : "+D" (addr), "+c" (count)
223 __asm __volatile("invd");
226 static __inline u_short
231 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
236 outb(u_int port, u_char data)
238 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
242 outl(u_int port, u_int data)
244 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
248 outsb(u_int port, const void *addr, size_t count)
250 __asm __volatile("rep; outsb"
251 : "+S" (addr), "+c" (count)
256 outsw(u_int port, const void *addr, size_t count)
258 __asm __volatile("rep; outsw"
259 : "+S" (addr), "+c" (count)
264 outsl(u_int port, const void *addr, size_t count)
266 __asm __volatile("rep; outsl"
267 : "+S" (addr), "+c" (count)
272 outw(u_int port, u_short data)
274 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
277 static __inline u_long
282 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
290 __asm __volatile("lfence" : : : "memory");
297 __asm __volatile("mfence" : : : "memory");
304 __asm __volatile("sfence" : : : "memory");
310 __asm __volatile("pause");
313 static __inline u_long
318 __asm __volatile("pushfq; popq %0" : "=r" (rf));
322 static __inline uint64_t
327 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
328 return (low | ((uint64_t)high << 32));
331 static __inline uint32_t
336 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
340 static __inline uint64_t
345 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
346 return (low | ((uint64_t)high << 32));
349 static __inline uint64_t
354 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
355 return (low | ((uint64_t)high << 32));
358 static __inline uint64_t
359 rdtsc_ordered_lfence(void)
365 static __inline uint64_t
366 rdtsc_ordered_mfence(void)
372 static __inline uint64_t
377 __asm __volatile("rdtscp" : "=a" (low), "=d" (high) : : "ecx");
378 return (low | ((uint64_t)high << 32));
381 static __inline uint64_t
382 rdtscp_aux(uint32_t *aux)
386 __asm __volatile("rdtscp" : "=a" (low), "=d" (high), "=c" (*aux));
387 return (low | ((uint64_t)high << 32));
390 static __inline uint32_t
395 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
399 static __inline uint32_t
404 __asm __volatile("rdtscp" : "=a" (rv) : : "ecx", "edx");
411 __asm __volatile("wbinvd");
415 write_rflags(u_long rf)
417 __asm __volatile("pushq %0; popfq" : : "r" (rf));
421 wrmsr(u_int msr, uint64_t newval)
427 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
431 load_cr0(u_long data)
434 __asm __volatile("movq %0,%%cr0" : : "r" (data));
437 static __inline u_long
442 __asm __volatile("movq %%cr0,%0" : "=r" (data));
446 static __inline u_long
451 __asm __volatile("movq %%cr2,%0" : "=r" (data));
456 load_cr3(u_long data)
459 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
462 static __inline u_long
467 __asm __volatile("movq %%cr3,%0" : "=r" (data));
472 load_cr4(u_long data)
474 __asm __volatile("movq %0,%%cr4" : : "r" (data));
477 static __inline u_long
482 __asm __volatile("movq %%cr4,%0" : "=r" (data));
486 static __inline u_long
491 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
492 return (low | ((uint64_t)high << 32));
496 load_xcr(u_int reg, u_long val)
502 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
506 * Global TLB flush (except for thise for pages marked PG_G)
516 #define CR4_PGE 0x00000080 /* Page global enable */
520 * Perform the guaranteed invalidation of all TLB entries. This
521 * includes the global entries, and entries in all PCIDs, not only the
522 * current context. The function works both on non-PCID CPUs and CPUs
523 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
524 * Operations that Invalidate TLBs and Paging-Structure Caches.
532 load_cr4(cr4 & ~CR4_PGE);
534 * Although preemption at this point could be detrimental to
535 * performance, it would not lead to an error. PG_G is simply
536 * ignored if CR4.PGE is clear. Moreover, in case this block
537 * is re-entered, the load_cr4() either above or below will
538 * modify CR4.PGE flushing the TLB.
540 load_cr4(cr4 | CR4_PGE);
544 * TLB flush for an individual page (even if it has PG_G).
545 * Only works on 486+ CPUs (i386 does not have PG_G).
551 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
554 #define INVPCID_ADDR 0
555 #define INVPCID_CTX 1
556 #define INVPCID_CTXGLOB 2
557 #define INVPCID_ALLCTX 3
559 struct invpcid_descr {
560 uint64_t pcid:12 __packed;
561 uint64_t pad:52 __packed;
566 invpcid(struct invpcid_descr *d, int type)
569 __asm __volatile("invpcid (%0),%1"
570 : : "r" (d), "r" ((u_long)type) : "memory");
573 static __inline u_short
577 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
581 static __inline u_short
585 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
589 static __inline u_short
593 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
600 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
606 __asm __volatile("movw %0,%%es" : : "rm" (sel));
610 cpu_monitor(const void *addr, u_long extensions, u_int hints)
613 __asm __volatile("monitor"
614 : : "a" (addr), "c" (extensions), "d" (hints));
618 cpu_mwait(u_long extensions, u_int hints)
621 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
624 static __inline uint32_t
629 __asm __volatile("rdpkru" : "=a" (res) : "c" (0) : "edx");
634 wrpkru(uint32_t mask)
637 __asm __volatile("wrpkru" : : "a" (mask), "c" (0), "d" (0));
641 /* This is defined in <machine/specialreg.h> but is too painful to get to */
643 #define MSR_FSBASE 0xc0000100
648 /* Preserve the fsbase value across the selector load */
649 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
650 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
654 #define MSR_GSBASE 0xc0000101
660 * Preserve the gsbase value across the selector load.
661 * Note that we have to disable interrupts because the gsbase
662 * being trashed happens to be the kernel gsbase at the time.
664 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
665 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
668 /* Usable by userland */
672 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
678 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
682 static __inline uint64_t
687 __asm __volatile("rdfsbase %0" : "=r" (x));
695 __asm __volatile("wrfsbase %0" : : "r" (x));
698 static __inline uint64_t
703 __asm __volatile("rdgsbase %0" : "=r" (x));
711 __asm __volatile("wrgsbase %0" : : "r" (x));
715 bare_lgdt(struct region_descriptor *addr)
717 __asm __volatile("lgdt (%0)" : : "r" (addr));
721 sgdt(struct region_descriptor *addr)
726 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
730 lidt(struct region_descriptor *addr)
732 __asm __volatile("lidt (%0)" : : "r" (addr));
736 sidt(struct region_descriptor *addr)
741 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
747 __asm __volatile("lldt %0" : : "r" (sel));
750 static __inline u_short
755 __asm __volatile("sldt %0" : "=r" (sel));
762 __asm __volatile("ltr %0" : : "r" (sel));
765 static __inline uint32_t
770 __asm __volatile("str %0" : "=r" (sel));
774 static __inline uint64_t
778 __asm __volatile("movq %%dr0,%0" : "=r" (data));
783 load_dr0(uint64_t dr0)
785 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
788 static __inline uint64_t
792 __asm __volatile("movq %%dr1,%0" : "=r" (data));
797 load_dr1(uint64_t dr1)
799 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
802 static __inline uint64_t
806 __asm __volatile("movq %%dr2,%0" : "=r" (data));
811 load_dr2(uint64_t dr2)
813 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
816 static __inline uint64_t
820 __asm __volatile("movq %%dr3,%0" : "=r" (data));
825 load_dr3(uint64_t dr3)
827 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
830 static __inline uint64_t
834 __asm __volatile("movq %%dr6,%0" : "=r" (data));
839 load_dr6(uint64_t dr6)
841 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
844 static __inline uint64_t
848 __asm __volatile("movq %%dr7,%0" : "=r" (data));
853 load_dr7(uint64_t dr7)
855 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
858 static __inline register_t
863 rflags = read_rflags();
869 intr_restore(register_t rflags)
871 write_rflags(rflags);
878 __asm __volatile("stac" : : : "cc");
885 __asm __volatile("clac" : : : "cc");
911 int sgx_encls(uint32_t eax, uint64_t rbx, uint64_t rcx, uint64_t rdx);
914 sgx_ecreate(void *pginfo, void *secs)
917 return (sgx_encls(SGX_ECREATE, (uint64_t)pginfo,
922 sgx_eadd(void *pginfo, void *epc)
925 return (sgx_encls(SGX_EADD, (uint64_t)pginfo,
930 sgx_einit(void *sigstruct, void *secs, void *einittoken)
933 return (sgx_encls(SGX_EINIT, (uint64_t)sigstruct,
934 (uint64_t)secs, (uint64_t)einittoken));
938 sgx_eextend(void *secs, void *epc)
941 return (sgx_encls(SGX_EEXTEND, (uint64_t)secs,
949 return (sgx_encls(SGX_EPA, SGX_PT_VA, (uint64_t)epc, 0));
953 sgx_eldu(uint64_t rbx, uint64_t rcx,
957 return (sgx_encls(SGX_ELDU, rbx, rcx, rdx));
961 sgx_eremove(void *epc)
964 return (sgx_encls(SGX_EREMOVE, 0, (uint64_t)epc, 0));
967 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
969 int breakpoint(void);
970 u_int bsfl(u_int mask);
971 u_int bsrl(u_int mask);
972 void clflush(u_long addr);
974 void cpuid_count(u_int ax, u_int cx, u_int *p);
975 void disable_intr(void);
976 void do_cpuid(u_int ax, u_int *p);
977 void enable_intr(void);
979 void ia32_pause(void);
980 u_char inb(u_int port);
981 u_int inl(u_int port);
982 void insb(u_int port, void *addr, size_t count);
983 void insl(u_int port, void *addr, size_t count);
984 void insw(u_int port, void *addr, size_t count);
985 register_t intr_disable(void);
986 void intr_restore(register_t rf);
988 void invlpg(u_int addr);
990 u_short inw(u_int port);
991 void lidt(struct region_descriptor *addr);
992 void lldt(u_short sel);
993 void load_cr0(u_long cr0);
994 void load_cr3(u_long cr3);
995 void load_cr4(u_long cr4);
996 void load_dr0(uint64_t dr0);
997 void load_dr1(uint64_t dr1);
998 void load_dr2(uint64_t dr2);
999 void load_dr3(uint64_t dr3);
1000 void load_dr6(uint64_t dr6);
1001 void load_dr7(uint64_t dr7);
1002 void load_fs(u_short sel);
1003 void load_gs(u_short sel);
1004 void ltr(u_short sel);
1005 void outb(u_int port, u_char data);
1006 void outl(u_int port, u_int data);
1007 void outsb(u_int port, const void *addr, size_t count);
1008 void outsl(u_int port, const void *addr, size_t count);
1009 void outsw(u_int port, const void *addr, size_t count);
1010 void outw(u_int port, u_short data);
1015 uint64_t rdmsr(u_int msr);
1016 uint32_t rdmsr32(u_int msr);
1017 uint64_t rdpmc(u_int pmc);
1018 uint64_t rdr0(void);
1019 uint64_t rdr1(void);
1020 uint64_t rdr2(void);
1021 uint64_t rdr3(void);
1022 uint64_t rdr6(void);
1023 uint64_t rdr7(void);
1024 uint64_t rdtsc(void);
1025 u_long read_rflags(void);
1029 void write_rflags(u_int rf);
1030 void wrmsr(u_int msr, uint64_t newval);
1032 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
1034 void reset_dbregs(void);
1037 int rdmsr_safe(u_int msr, uint64_t *val);
1038 int wrmsr_safe(u_int msr, uint64_t newval);
1041 #endif /* !_MACHINE_CPUFUNC_H_ */