2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
39 #ifndef _MACHINE_CPUFUNC_H_
40 #define _MACHINE_CPUFUNC_H_
43 #error this file needs sys/cdefs.h as a prerequisite
46 struct region_descriptor;
48 #define readb(va) (*(volatile uint8_t *) (va))
49 #define readw(va) (*(volatile uint16_t *) (va))
50 #define readl(va) (*(volatile uint32_t *) (va))
51 #define readq(va) (*(volatile uint64_t *) (va))
53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
63 __asm __volatile("int $3");
71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
75 static __inline u_long
80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
93 static __inline u_long
98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
106 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
113 __asm __volatile("clts");
119 __asm __volatile("cli" : : : "memory");
123 do_cpuid(u_int ax, u_int *p)
125 __asm __volatile("cpuid"
126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
131 cpuid_count(u_int ax, u_int cx, u_int *p)
133 __asm __volatile("cpuid"
134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
135 : "0" (ax), "c" (cx));
141 __asm __volatile("sti");
146 #define HAVE_INLINE_FFS
147 #define ffs(x) __builtin_ffs(x)
149 #define HAVE_INLINE_FFSL
154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
157 #define HAVE_INLINE_FFSLL
160 ffsll(long long mask)
162 return (ffsl((long)mask));
165 #define HAVE_INLINE_FLS
170 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
173 #define HAVE_INLINE_FLSL
178 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
181 #define HAVE_INLINE_FLSLL
184 flsll(long long mask)
186 return (flsl((long)mask));
194 __asm __volatile("hlt");
197 static __inline u_char
202 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
206 static __inline u_int
211 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
216 insb(u_int port, void *addr, size_t count)
218 __asm __volatile("cld; rep; insb"
219 : "+D" (addr), "+c" (count)
225 insw(u_int port, void *addr, size_t count)
227 __asm __volatile("cld; rep; insw"
228 : "+D" (addr), "+c" (count)
234 insl(u_int port, void *addr, size_t count)
236 __asm __volatile("cld; rep; insl"
237 : "+D" (addr), "+c" (count)
245 __asm __volatile("invd");
248 static __inline u_short
253 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
258 outb(u_int port, u_char data)
260 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
264 outl(u_int port, u_int data)
266 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
270 outsb(u_int port, const void *addr, size_t count)
272 __asm __volatile("cld; rep; outsb"
273 : "+S" (addr), "+c" (count)
278 outsw(u_int port, const void *addr, size_t count)
280 __asm __volatile("cld; rep; outsw"
281 : "+S" (addr), "+c" (count)
286 outsl(u_int port, const void *addr, size_t count)
288 __asm __volatile("cld; rep; outsl"
289 : "+S" (addr), "+c" (count)
294 outw(u_int port, u_short data)
296 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
299 static __inline u_long
304 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
312 __asm __volatile("lfence" : : : "memory");
319 __asm __volatile("mfence" : : : "memory");
325 __asm __volatile("pause");
328 static __inline u_long
333 __asm __volatile("pushfq; popq %0" : "=r" (rf));
337 static __inline uint64_t
342 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
343 return (low | ((uint64_t)high << 32));
346 static __inline uint32_t
351 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
355 static __inline uint64_t
360 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
361 return (low | ((uint64_t)high << 32));
364 static __inline uint64_t
369 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
370 return (low | ((uint64_t)high << 32));
373 static __inline uint32_t
378 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
385 __asm __volatile("wbinvd");
389 write_rflags(u_long rf)
391 __asm __volatile("pushq %0; popfq" : : "r" (rf));
395 wrmsr(u_int msr, uint64_t newval)
401 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
405 load_cr0(u_long data)
408 __asm __volatile("movq %0,%%cr0" : : "r" (data));
411 static __inline u_long
416 __asm __volatile("movq %%cr0,%0" : "=r" (data));
420 static __inline u_long
425 __asm __volatile("movq %%cr2,%0" : "=r" (data));
430 load_cr3(u_long data)
433 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
436 static __inline u_long
441 __asm __volatile("movq %%cr3,%0" : "=r" (data));
446 load_cr4(u_long data)
448 __asm __volatile("movq %0,%%cr4" : : "r" (data));
451 static __inline u_long
456 __asm __volatile("movq %%cr4,%0" : "=r" (data));
460 static __inline u_long
465 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
466 return (low | ((uint64_t)high << 32));
470 load_xcr(u_int reg, u_long val)
476 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
480 * Global TLB flush (except for thise for pages marked PG_G)
490 #define CR4_PGE 0x00000080 /* Page global enable */
494 * Perform the guaranteed invalidation of all TLB entries. This
495 * includes the global entries, and entries in all PCIDs, not only the
496 * current context. The function works both on non-PCID CPUs and CPUs
497 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
498 * Operations that Invalidate TLBs and Paging-Structure Caches.
501 invltlb_globpcid(void)
506 load_cr4(cr4 & ~CR4_PGE);
508 * Although preemption at this point could be detrimental to
509 * performance, it would not lead to an error. PG_G is simply
510 * ignored if CR4.PGE is clear. Moreover, in case this block
511 * is re-entered, the load_cr4() either above or below will
512 * modify CR4.PGE flushing the TLB.
514 load_cr4(cr4 | CR4_PGE);
518 * TLB flush for an individual page (even if it has PG_G).
519 * Only works on 486+ CPUs (i386 does not have PG_G).
525 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
528 #define INVPCID_ADDR 0
529 #define INVPCID_CTX 1
530 #define INVPCID_CTXGLOB 2
531 #define INVPCID_ALLCTX 3
533 struct invpcid_descr {
534 uint64_t pcid:12 __packed;
535 uint64_t pad:52 __packed;
540 invpcid(struct invpcid_descr *d, int type)
543 __asm __volatile("invpcid (%0),%1"
544 : : "r" (d), "r" ((u_long)type) : "memory");
547 static __inline u_short
551 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
555 static __inline u_short
559 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
563 static __inline u_short
567 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
574 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
580 __asm __volatile("movw %0,%%es" : : "rm" (sel));
584 cpu_monitor(const void *addr, u_long extensions, u_int hints)
587 __asm __volatile("monitor"
588 : : "a" (addr), "c" (extensions), "d" (hints));
592 cpu_mwait(u_long extensions, u_int hints)
595 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
599 /* This is defined in <machine/specialreg.h> but is too painful to get to */
601 #define MSR_FSBASE 0xc0000100
606 /* Preserve the fsbase value across the selector load */
607 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
608 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
612 #define MSR_GSBASE 0xc0000101
618 * Preserve the gsbase value across the selector load.
619 * Note that we have to disable interrupts because the gsbase
620 * being trashed happens to be the kernel gsbase at the time.
622 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
623 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
626 /* Usable by userland */
630 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
636 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
641 lidt(struct region_descriptor *addr)
643 __asm __volatile("lidt (%0)" : : "r" (addr));
649 __asm __volatile("lldt %0" : : "r" (sel));
655 __asm __volatile("ltr %0" : : "r" (sel));
658 static __inline uint64_t
662 __asm __volatile("movq %%dr0,%0" : "=r" (data));
667 load_dr0(uint64_t dr0)
669 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
672 static __inline uint64_t
676 __asm __volatile("movq %%dr1,%0" : "=r" (data));
681 load_dr1(uint64_t dr1)
683 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
686 static __inline uint64_t
690 __asm __volatile("movq %%dr2,%0" : "=r" (data));
695 load_dr2(uint64_t dr2)
697 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
700 static __inline uint64_t
704 __asm __volatile("movq %%dr3,%0" : "=r" (data));
709 load_dr3(uint64_t dr3)
711 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
714 static __inline uint64_t
718 __asm __volatile("movq %%dr4,%0" : "=r" (data));
723 load_dr4(uint64_t dr4)
725 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
728 static __inline uint64_t
732 __asm __volatile("movq %%dr5,%0" : "=r" (data));
737 load_dr5(uint64_t dr5)
739 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
742 static __inline uint64_t
746 __asm __volatile("movq %%dr6,%0" : "=r" (data));
751 load_dr6(uint64_t dr6)
753 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
756 static __inline uint64_t
760 __asm __volatile("movq %%dr7,%0" : "=r" (data));
765 load_dr7(uint64_t dr7)
767 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
770 static __inline register_t
775 rflags = read_rflags();
781 intr_restore(register_t rflags)
783 write_rflags(rflags);
786 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
788 int breakpoint(void);
789 u_int bsfl(u_int mask);
790 u_int bsrl(u_int mask);
791 void clflush(u_long addr);
793 void cpuid_count(u_int ax, u_int cx, u_int *p);
794 void disable_intr(void);
795 void do_cpuid(u_int ax, u_int *p);
796 void enable_intr(void);
798 void ia32_pause(void);
799 u_char inb(u_int port);
800 u_int inl(u_int port);
801 void insb(u_int port, void *addr, size_t count);
802 void insl(u_int port, void *addr, size_t count);
803 void insw(u_int port, void *addr, size_t count);
804 register_t intr_disable(void);
805 void intr_restore(register_t rf);
807 void invlpg(u_int addr);
809 u_short inw(u_int port);
810 void lidt(struct region_descriptor *addr);
811 void lldt(u_short sel);
812 void load_cr0(u_long cr0);
813 void load_cr3(u_long cr3);
814 void load_cr4(u_long cr4);
815 void load_dr0(uint64_t dr0);
816 void load_dr1(uint64_t dr1);
817 void load_dr2(uint64_t dr2);
818 void load_dr3(uint64_t dr3);
819 void load_dr4(uint64_t dr4);
820 void load_dr5(uint64_t dr5);
821 void load_dr6(uint64_t dr6);
822 void load_dr7(uint64_t dr7);
823 void load_fs(u_short sel);
824 void load_gs(u_short sel);
825 void ltr(u_short sel);
826 void outb(u_int port, u_char data);
827 void outl(u_int port, u_int data);
828 void outsb(u_int port, const void *addr, size_t count);
829 void outsl(u_int port, const void *addr, size_t count);
830 void outsw(u_int port, const void *addr, size_t count);
831 void outw(u_int port, u_short data);
836 uint64_t rdmsr(u_int msr);
837 uint32_t rdmsr32(u_int msr);
838 uint64_t rdpmc(u_int pmc);
847 uint64_t rdtsc(void);
848 u_long read_rflags(void);
852 void write_rflags(u_int rf);
853 void wrmsr(u_int msr, uint64_t newval);
855 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
857 void reset_dbregs(void);
860 int rdmsr_safe(u_int msr, uint64_t *val);
861 int wrmsr_safe(u_int msr, uint64_t newval);
864 #endif /* !_MACHINE_CPUFUNC_H_ */