2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1993 The Regents of the University of California.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Functions to provide access to special i386 instructions.
37 * This in included in sys/systm.h, and that file should be
38 * used in preference to this.
41 #ifndef _MACHINE_CPUFUNC_H_
42 #define _MACHINE_CPUFUNC_H_
45 #error this file needs sys/cdefs.h as a prerequisite
48 struct region_descriptor;
50 #define readb(va) (*(volatile uint8_t *) (va))
51 #define readw(va) (*(volatile uint16_t *) (va))
52 #define readl(va) (*(volatile uint32_t *) (va))
53 #define readq(va) (*(volatile uint64_t *) (va))
55 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
58 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
60 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
65 __asm __volatile("int $3");
68 static __inline __pure2 u_int
73 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
77 static __inline __pure2 u_long
82 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
86 static __inline __pure2 u_int
91 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
95 static __inline __pure2 u_long
100 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
108 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
112 clflushopt(u_long addr)
115 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
122 __asm __volatile("clts");
128 __asm __volatile("cli" : : : "memory");
132 do_cpuid(u_int ax, u_int *p)
134 __asm __volatile("cpuid"
135 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
140 cpuid_count(u_int ax, u_int cx, u_int *p)
142 __asm __volatile("cpuid"
143 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
144 : "0" (ax), "c" (cx));
150 __asm __volatile("sti");
155 #define HAVE_INLINE_FFS
156 #define ffs(x) __builtin_ffs(x)
158 #define HAVE_INLINE_FFSL
160 static __inline __pure2 int
163 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
166 #define HAVE_INLINE_FFSLL
168 static __inline __pure2 int
169 ffsll(long long mask)
171 return (ffsl((long)mask));
174 #define HAVE_INLINE_FLS
176 static __inline __pure2 int
179 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
182 #define HAVE_INLINE_FLSL
184 static __inline __pure2 int
187 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
190 #define HAVE_INLINE_FLSLL
192 static __inline __pure2 int
193 flsll(long long mask)
195 return (flsl((long)mask));
203 __asm __volatile("hlt");
206 static __inline u_char
211 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
215 static __inline u_int
220 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
225 insb(u_int port, void *addr, size_t count)
227 __asm __volatile("cld; rep; insb"
228 : "+D" (addr), "+c" (count)
234 insw(u_int port, void *addr, size_t count)
236 __asm __volatile("cld; rep; insw"
237 : "+D" (addr), "+c" (count)
243 insl(u_int port, void *addr, size_t count)
245 __asm __volatile("cld; rep; insl"
246 : "+D" (addr), "+c" (count)
254 __asm __volatile("invd");
257 static __inline u_short
262 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
267 outb(u_int port, u_char data)
269 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
273 outl(u_int port, u_int data)
275 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
279 outsb(u_int port, const void *addr, size_t count)
281 __asm __volatile("cld; rep; outsb"
282 : "+S" (addr), "+c" (count)
287 outsw(u_int port, const void *addr, size_t count)
289 __asm __volatile("cld; rep; outsw"
290 : "+S" (addr), "+c" (count)
295 outsl(u_int port, const void *addr, size_t count)
297 __asm __volatile("cld; rep; outsl"
298 : "+S" (addr), "+c" (count)
303 outw(u_int port, u_short data)
305 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
308 static __inline u_long
313 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
321 __asm __volatile("lfence" : : : "memory");
328 __asm __volatile("mfence" : : : "memory");
335 __asm __volatile("sfence" : : : "memory");
341 __asm __volatile("pause");
344 static __inline u_long
349 __asm __volatile("pushfq; popq %0" : "=r" (rf));
353 static __inline uint64_t
358 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
359 return (low | ((uint64_t)high << 32));
362 static __inline uint32_t
367 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
371 static __inline uint64_t
376 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
377 return (low | ((uint64_t)high << 32));
380 static __inline uint64_t
385 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
386 return (low | ((uint64_t)high << 32));
389 static __inline uint32_t
394 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
401 __asm __volatile("wbinvd");
405 write_rflags(u_long rf)
407 __asm __volatile("pushq %0; popfq" : : "r" (rf));
411 wrmsr(u_int msr, uint64_t newval)
417 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
421 load_cr0(u_long data)
424 __asm __volatile("movq %0,%%cr0" : : "r" (data));
427 static __inline u_long
432 __asm __volatile("movq %%cr0,%0" : "=r" (data));
436 static __inline u_long
441 __asm __volatile("movq %%cr2,%0" : "=r" (data));
446 load_cr3(u_long data)
449 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
452 static __inline u_long
457 __asm __volatile("movq %%cr3,%0" : "=r" (data));
462 load_cr4(u_long data)
464 __asm __volatile("movq %0,%%cr4" : : "r" (data));
467 static __inline u_long
472 __asm __volatile("movq %%cr4,%0" : "=r" (data));
476 static __inline u_long
481 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
482 return (low | ((uint64_t)high << 32));
486 load_xcr(u_int reg, u_long val)
492 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
496 * Global TLB flush (except for thise for pages marked PG_G)
506 #define CR4_PGE 0x00000080 /* Page global enable */
510 * Perform the guaranteed invalidation of all TLB entries. This
511 * includes the global entries, and entries in all PCIDs, not only the
512 * current context. The function works both on non-PCID CPUs and CPUs
513 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
514 * Operations that Invalidate TLBs and Paging-Structure Caches.
522 load_cr4(cr4 & ~CR4_PGE);
524 * Although preemption at this point could be detrimental to
525 * performance, it would not lead to an error. PG_G is simply
526 * ignored if CR4.PGE is clear. Moreover, in case this block
527 * is re-entered, the load_cr4() either above or below will
528 * modify CR4.PGE flushing the TLB.
530 load_cr4(cr4 | CR4_PGE);
534 * TLB flush for an individual page (even if it has PG_G).
535 * Only works on 486+ CPUs (i386 does not have PG_G).
541 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
544 #define INVPCID_ADDR 0
545 #define INVPCID_CTX 1
546 #define INVPCID_CTXGLOB 2
547 #define INVPCID_ALLCTX 3
549 struct invpcid_descr {
550 uint64_t pcid:12 __packed;
551 uint64_t pad:52 __packed;
556 invpcid(struct invpcid_descr *d, int type)
559 __asm __volatile("invpcid (%0),%1"
560 : : "r" (d), "r" ((u_long)type) : "memory");
563 static __inline u_short
567 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
571 static __inline u_short
575 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
579 static __inline u_short
583 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
590 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
596 __asm __volatile("movw %0,%%es" : : "rm" (sel));
600 cpu_monitor(const void *addr, u_long extensions, u_int hints)
603 __asm __volatile("monitor"
604 : : "a" (addr), "c" (extensions), "d" (hints));
608 cpu_mwait(u_long extensions, u_int hints)
611 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
615 /* This is defined in <machine/specialreg.h> but is too painful to get to */
617 #define MSR_FSBASE 0xc0000100
622 /* Preserve the fsbase value across the selector load */
623 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
624 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
628 #define MSR_GSBASE 0xc0000101
634 * Preserve the gsbase value across the selector load.
635 * Note that we have to disable interrupts because the gsbase
636 * being trashed happens to be the kernel gsbase at the time.
638 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
639 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
642 /* Usable by userland */
646 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
652 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
656 static __inline uint64_t
661 __asm __volatile("rdfsbase %0" : "=r" (x));
669 __asm __volatile("wrfsbase %0" : : "r" (x));
672 static __inline uint64_t
677 __asm __volatile("rdgsbase %0" : "=r" (x));
685 __asm __volatile("wrgsbase %0" : : "r" (x));
689 bare_lgdt(struct region_descriptor *addr)
691 __asm __volatile("lgdt (%0)" : : "r" (addr));
695 sgdt(struct region_descriptor *addr)
700 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
704 lidt(struct region_descriptor *addr)
706 __asm __volatile("lidt (%0)" : : "r" (addr));
710 sidt(struct region_descriptor *addr)
715 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
721 __asm __volatile("lldt %0" : : "r" (sel));
727 __asm __volatile("ltr %0" : : "r" (sel));
730 static __inline uint32_t
735 __asm __volatile("str %0" : "=r" (sel));
739 static __inline uint64_t
743 __asm __volatile("movq %%dr0,%0" : "=r" (data));
748 load_dr0(uint64_t dr0)
750 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
753 static __inline uint64_t
757 __asm __volatile("movq %%dr1,%0" : "=r" (data));
762 load_dr1(uint64_t dr1)
764 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
767 static __inline uint64_t
771 __asm __volatile("movq %%dr2,%0" : "=r" (data));
776 load_dr2(uint64_t dr2)
778 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
781 static __inline uint64_t
785 __asm __volatile("movq %%dr3,%0" : "=r" (data));
790 load_dr3(uint64_t dr3)
792 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
795 static __inline uint64_t
799 __asm __volatile("movq %%dr6,%0" : "=r" (data));
804 load_dr6(uint64_t dr6)
806 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
809 static __inline uint64_t
813 __asm __volatile("movq %%dr7,%0" : "=r" (data));
818 load_dr7(uint64_t dr7)
820 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
823 static __inline register_t
828 rflags = read_rflags();
834 intr_restore(register_t rflags)
836 write_rflags(rflags);
843 __asm __volatile("stac" : : : "cc");
850 __asm __volatile("clac" : : : "cc");
876 int sgx_encls(uint32_t eax, uint64_t rbx, uint64_t rcx, uint64_t rdx);
879 sgx_ecreate(void *pginfo, void *secs)
882 return (sgx_encls(SGX_ECREATE, (uint64_t)pginfo,
887 sgx_eadd(void *pginfo, void *epc)
890 return (sgx_encls(SGX_EADD, (uint64_t)pginfo,
895 sgx_einit(void *sigstruct, void *secs, void *einittoken)
898 return (sgx_encls(SGX_EINIT, (uint64_t)sigstruct,
899 (uint64_t)secs, (uint64_t)einittoken));
903 sgx_eextend(void *secs, void *epc)
906 return (sgx_encls(SGX_EEXTEND, (uint64_t)secs,
914 return (sgx_encls(SGX_EPA, SGX_PT_VA, (uint64_t)epc, 0));
918 sgx_eldu(uint64_t rbx, uint64_t rcx,
922 return (sgx_encls(SGX_ELDU, rbx, rcx, rdx));
926 sgx_eremove(void *epc)
929 return (sgx_encls(SGX_EREMOVE, 0, (uint64_t)epc, 0));
932 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
934 int breakpoint(void);
935 u_int bsfl(u_int mask);
936 u_int bsrl(u_int mask);
937 void clflush(u_long addr);
939 void cpuid_count(u_int ax, u_int cx, u_int *p);
940 void disable_intr(void);
941 void do_cpuid(u_int ax, u_int *p);
942 void enable_intr(void);
944 void ia32_pause(void);
945 u_char inb(u_int port);
946 u_int inl(u_int port);
947 void insb(u_int port, void *addr, size_t count);
948 void insl(u_int port, void *addr, size_t count);
949 void insw(u_int port, void *addr, size_t count);
950 register_t intr_disable(void);
951 void intr_restore(register_t rf);
953 void invlpg(u_int addr);
955 u_short inw(u_int port);
956 void lidt(struct region_descriptor *addr);
957 void lldt(u_short sel);
958 void load_cr0(u_long cr0);
959 void load_cr3(u_long cr3);
960 void load_cr4(u_long cr4);
961 void load_dr0(uint64_t dr0);
962 void load_dr1(uint64_t dr1);
963 void load_dr2(uint64_t dr2);
964 void load_dr3(uint64_t dr3);
965 void load_dr6(uint64_t dr6);
966 void load_dr7(uint64_t dr7);
967 void load_fs(u_short sel);
968 void load_gs(u_short sel);
969 void ltr(u_short sel);
970 void outb(u_int port, u_char data);
971 void outl(u_int port, u_int data);
972 void outsb(u_int port, const void *addr, size_t count);
973 void outsl(u_int port, const void *addr, size_t count);
974 void outsw(u_int port, const void *addr, size_t count);
975 void outw(u_int port, u_short data);
980 uint64_t rdmsr(u_int msr);
981 uint32_t rdmsr32(u_int msr);
982 uint64_t rdpmc(u_int pmc);
989 uint64_t rdtsc(void);
990 u_long read_rflags(void);
994 void write_rflags(u_int rf);
995 void wrmsr(u_int msr, uint64_t newval);
997 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
999 void reset_dbregs(void);
1002 int rdmsr_safe(u_int msr, uint64_t *val);
1003 int wrmsr_safe(u_int msr, uint64_t newval);
1006 #endif /* !_MACHINE_CPUFUNC_H_ */