2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
39 #ifndef _MACHINE_CPUFUNC_H_
40 #define _MACHINE_CPUFUNC_H_
43 #error this file needs sys/cdefs.h as a prerequisite
46 struct region_descriptor;
48 #define readb(va) (*(volatile uint8_t *) (va))
49 #define readw(va) (*(volatile uint16_t *) (va))
50 #define readl(va) (*(volatile uint32_t *) (va))
51 #define readq(va) (*(volatile uint64_t *) (va))
53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
63 __asm __volatile("int $3");
71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
75 static __inline u_long
80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
93 static __inline u_long
98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
106 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
113 __asm __volatile("clts");
119 __asm __volatile("cli" : : : "memory");
123 do_cpuid(u_int ax, u_int *p)
125 __asm __volatile("cpuid"
126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
131 cpuid_count(u_int ax, u_int cx, u_int *p)
133 __asm __volatile("cpuid"
134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
135 : "0" (ax), "c" (cx));
141 __asm __volatile("sti");
146 #define HAVE_INLINE_FFS
147 #define ffs(x) __builtin_ffs(x)
149 #define HAVE_INLINE_FFSL
154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
157 #define HAVE_INLINE_FFSLL
160 ffsll(long long mask)
162 return (ffsl((long)mask));
165 #define HAVE_INLINE_FLS
170 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
173 #define HAVE_INLINE_FLSL
178 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
181 #define HAVE_INLINE_FLSLL
184 flsll(long long mask)
186 return (flsl((long)mask));
194 __asm __volatile("hlt");
197 static __inline u_char
202 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
206 static __inline u_int
211 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
216 insb(u_int port, void *addr, size_t count)
218 __asm __volatile("cld; rep; insb"
219 : "+D" (addr), "+c" (count)
225 insw(u_int port, void *addr, size_t count)
227 __asm __volatile("cld; rep; insw"
228 : "+D" (addr), "+c" (count)
234 insl(u_int port, void *addr, size_t count)
236 __asm __volatile("cld; rep; insl"
237 : "+D" (addr), "+c" (count)
245 __asm __volatile("invd");
248 static __inline u_short
253 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
258 outb(u_int port, u_char data)
260 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
264 outl(u_int port, u_int data)
266 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
270 outsb(u_int port, const void *addr, size_t count)
272 __asm __volatile("cld; rep; outsb"
273 : "+S" (addr), "+c" (count)
278 outsw(u_int port, const void *addr, size_t count)
280 __asm __volatile("cld; rep; outsw"
281 : "+S" (addr), "+c" (count)
286 outsl(u_int port, const void *addr, size_t count)
288 __asm __volatile("cld; rep; outsl"
289 : "+S" (addr), "+c" (count)
294 outw(u_int port, u_short data)
296 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
299 static __inline u_long
304 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
312 __asm __volatile("lfence" : : : "memory");
319 __asm __volatile("mfence" : : : "memory");
325 __asm __volatile("pause");
328 static __inline u_long
333 __asm __volatile("pushfq; popq %0" : "=r" (rf));
337 static __inline uint64_t
342 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
343 return (low | ((uint64_t)high << 32));
346 static __inline uint64_t
351 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
352 return (low | ((uint64_t)high << 32));
355 static __inline uint64_t
360 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
361 return (low | ((uint64_t)high << 32));
364 static __inline uint32_t
369 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
376 __asm __volatile("wbinvd");
380 write_rflags(u_long rf)
382 __asm __volatile("pushq %0; popfq" : : "r" (rf));
386 wrmsr(u_int msr, uint64_t newval)
392 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
396 load_cr0(u_long data)
399 __asm __volatile("movq %0,%%cr0" : : "r" (data));
402 static __inline u_long
407 __asm __volatile("movq %%cr0,%0" : "=r" (data));
411 static __inline u_long
416 __asm __volatile("movq %%cr2,%0" : "=r" (data));
421 load_cr3(u_long data)
424 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
427 static __inline u_long
432 __asm __volatile("movq %%cr3,%0" : "=r" (data));
437 load_cr4(u_long data)
439 __asm __volatile("movq %0,%%cr4" : : "r" (data));
442 static __inline u_long
447 __asm __volatile("movq %%cr4,%0" : "=r" (data));
451 static __inline u_long
456 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
457 return (low | ((uint64_t)high << 32));
461 load_xcr(u_int reg, u_long val)
467 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
471 * Global TLB flush (except for thise for pages marked PG_G)
481 #define CR4_PGE 0x00000080 /* Page global enable */
485 * Perform the guaranteed invalidation of all TLB entries. This
486 * includes the global entries, and entries in all PCIDs, not only the
487 * current context. The function works both on non-PCID CPUs and CPUs
488 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
489 * Operations that Invalidate TLBs and Paging-Structure Caches.
492 invltlb_globpcid(void)
497 load_cr4(cr4 & ~CR4_PGE);
499 * Although preemption at this point could be detrimental to
500 * performance, it would not lead to an error. PG_G is simply
501 * ignored if CR4.PGE is clear. Moreover, in case this block
502 * is re-entered, the load_cr4() either above or below will
503 * modify CR4.PGE flushing the TLB.
505 load_cr4(cr4 | CR4_PGE);
509 * TLB flush for an individual page (even if it has PG_G).
510 * Only works on 486+ CPUs (i386 does not have PG_G).
516 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
519 #define INVPCID_ADDR 0
520 #define INVPCID_CTX 1
521 #define INVPCID_CTXGLOB 2
522 #define INVPCID_ALLCTX 3
524 struct invpcid_descr {
525 uint64_t pcid:12 __packed;
526 uint64_t pad:52 __packed;
531 invpcid(struct invpcid_descr *d, int type)
534 /* invpcid (%rdx),%rax */
535 __asm __volatile(".byte 0x66,0x0f,0x38,0x82,0x02"
536 : : "d" (d), "a" ((u_long)type) : "memory");
539 static __inline u_short
543 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
547 static __inline u_short
551 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
555 static __inline u_short
559 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
566 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
572 __asm __volatile("movw %0,%%es" : : "rm" (sel));
576 cpu_monitor(const void *addr, u_long extensions, u_int hints)
579 __asm __volatile("monitor"
580 : : "a" (addr), "c" (extensions), "d" (hints));
584 cpu_mwait(u_long extensions, u_int hints)
587 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
591 /* This is defined in <machine/specialreg.h> but is too painful to get to */
593 #define MSR_FSBASE 0xc0000100
598 /* Preserve the fsbase value across the selector load */
599 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
600 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
604 #define MSR_GSBASE 0xc0000101
610 * Preserve the gsbase value across the selector load.
611 * Note that we have to disable interrupts because the gsbase
612 * being trashed happens to be the kernel gsbase at the time.
614 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
615 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
618 /* Usable by userland */
622 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
628 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
633 lidt(struct region_descriptor *addr)
635 __asm __volatile("lidt (%0)" : : "r" (addr));
641 __asm __volatile("lldt %0" : : "r" (sel));
647 __asm __volatile("ltr %0" : : "r" (sel));
650 static __inline uint64_t
654 __asm __volatile("movq %%dr0,%0" : "=r" (data));
659 load_dr0(uint64_t dr0)
661 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
664 static __inline uint64_t
668 __asm __volatile("movq %%dr1,%0" : "=r" (data));
673 load_dr1(uint64_t dr1)
675 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
678 static __inline uint64_t
682 __asm __volatile("movq %%dr2,%0" : "=r" (data));
687 load_dr2(uint64_t dr2)
689 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
692 static __inline uint64_t
696 __asm __volatile("movq %%dr3,%0" : "=r" (data));
701 load_dr3(uint64_t dr3)
703 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
706 static __inline uint64_t
710 __asm __volatile("movq %%dr4,%0" : "=r" (data));
715 load_dr4(uint64_t dr4)
717 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
720 static __inline uint64_t
724 __asm __volatile("movq %%dr5,%0" : "=r" (data));
729 load_dr5(uint64_t dr5)
731 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
734 static __inline uint64_t
738 __asm __volatile("movq %%dr6,%0" : "=r" (data));
743 load_dr6(uint64_t dr6)
745 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
748 static __inline uint64_t
752 __asm __volatile("movq %%dr7,%0" : "=r" (data));
757 load_dr7(uint64_t dr7)
759 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
762 static __inline register_t
767 rflags = read_rflags();
773 intr_restore(register_t rflags)
775 write_rflags(rflags);
778 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
780 int breakpoint(void);
781 u_int bsfl(u_int mask);
782 u_int bsrl(u_int mask);
783 void clflush(u_long addr);
785 void cpuid_count(u_int ax, u_int cx, u_int *p);
786 void disable_intr(void);
787 void do_cpuid(u_int ax, u_int *p);
788 void enable_intr(void);
790 void ia32_pause(void);
791 u_char inb(u_int port);
792 u_int inl(u_int port);
793 void insb(u_int port, void *addr, size_t count);
794 void insl(u_int port, void *addr, size_t count);
795 void insw(u_int port, void *addr, size_t count);
796 register_t intr_disable(void);
797 void intr_restore(register_t rf);
799 void invlpg(u_int addr);
801 u_short inw(u_int port);
802 void lidt(struct region_descriptor *addr);
803 void lldt(u_short sel);
804 void load_cr0(u_long cr0);
805 void load_cr3(u_long cr3);
806 void load_cr4(u_long cr4);
807 void load_dr0(uint64_t dr0);
808 void load_dr1(uint64_t dr1);
809 void load_dr2(uint64_t dr2);
810 void load_dr3(uint64_t dr3);
811 void load_dr4(uint64_t dr4);
812 void load_dr5(uint64_t dr5);
813 void load_dr6(uint64_t dr6);
814 void load_dr7(uint64_t dr7);
815 void load_fs(u_short sel);
816 void load_gs(u_short sel);
817 void ltr(u_short sel);
818 void outb(u_int port, u_char data);
819 void outl(u_int port, u_int data);
820 void outsb(u_int port, const void *addr, size_t count);
821 void outsl(u_int port, const void *addr, size_t count);
822 void outsw(u_int port, const void *addr, size_t count);
823 void outw(u_int port, u_short data);
828 uint64_t rdmsr(u_int msr);
829 uint64_t rdpmc(u_int pmc);
838 uint64_t rdtsc(void);
839 u_long read_rflags(void);
843 void write_rflags(u_int rf);
844 void wrmsr(u_int msr, uint64_t newval);
846 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
848 void reset_dbregs(void);
851 int rdmsr_safe(u_int msr, uint64_t *val);
852 int wrmsr_safe(u_int msr, uint64_t newval);
855 #endif /* !_MACHINE_CPUFUNC_H_ */