2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
39 #ifndef _MACHINE_CPUFUNC_H_
40 #define _MACHINE_CPUFUNC_H_
43 #error this file needs sys/cdefs.h as a prerequisite
46 struct region_descriptor;
48 #define readb(va) (*(volatile uint8_t *) (va))
49 #define readw(va) (*(volatile uint16_t *) (va))
50 #define readl(va) (*(volatile uint32_t *) (va))
51 #define readq(va) (*(volatile uint64_t *) (va))
53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
63 __asm __volatile("int $3");
66 static __inline __pure2 u_int
71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
75 static __inline __pure2 u_long
80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
84 static __inline __pure2 u_int
89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
93 static __inline __pure2 u_long
98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
106 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
110 clflushopt(u_long addr)
113 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
120 __asm __volatile("clts");
126 __asm __volatile("cli" : : : "memory");
130 do_cpuid(u_int ax, u_int *p)
132 __asm __volatile("cpuid"
133 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
138 cpuid_count(u_int ax, u_int cx, u_int *p)
140 __asm __volatile("cpuid"
141 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
142 : "0" (ax), "c" (cx));
148 __asm __volatile("sti");
153 #define HAVE_INLINE_FFS
154 #define ffs(x) __builtin_ffs(x)
156 #define HAVE_INLINE_FFSL
158 static __inline __pure2 int
161 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
164 #define HAVE_INLINE_FFSLL
166 static __inline __pure2 int
167 ffsll(long long mask)
169 return (ffsl((long)mask));
172 #define HAVE_INLINE_FLS
174 static __inline __pure2 int
177 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
180 #define HAVE_INLINE_FLSL
182 static __inline __pure2 int
185 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
188 #define HAVE_INLINE_FLSLL
190 static __inline __pure2 int
191 flsll(long long mask)
193 return (flsl((long)mask));
201 __asm __volatile("hlt");
204 static __inline u_char
209 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
213 static __inline u_int
218 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
223 insb(u_int port, void *addr, size_t count)
225 __asm __volatile("cld; rep; insb"
226 : "+D" (addr), "+c" (count)
232 insw(u_int port, void *addr, size_t count)
234 __asm __volatile("cld; rep; insw"
235 : "+D" (addr), "+c" (count)
241 insl(u_int port, void *addr, size_t count)
243 __asm __volatile("cld; rep; insl"
244 : "+D" (addr), "+c" (count)
252 __asm __volatile("invd");
255 static __inline u_short
260 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
265 outb(u_int port, u_char data)
267 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
271 outl(u_int port, u_int data)
273 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
277 outsb(u_int port, const void *addr, size_t count)
279 __asm __volatile("cld; rep; outsb"
280 : "+S" (addr), "+c" (count)
285 outsw(u_int port, const void *addr, size_t count)
287 __asm __volatile("cld; rep; outsw"
288 : "+S" (addr), "+c" (count)
293 outsl(u_int port, const void *addr, size_t count)
295 __asm __volatile("cld; rep; outsl"
296 : "+S" (addr), "+c" (count)
301 outw(u_int port, u_short data)
303 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
306 static __inline u_long
311 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
319 __asm __volatile("lfence" : : : "memory");
326 __asm __volatile("mfence" : : : "memory");
333 __asm __volatile("sfence" : : : "memory");
339 __asm __volatile("pause");
342 static __inline u_long
347 __asm __volatile("pushfq; popq %0" : "=r" (rf));
351 static __inline uint64_t
356 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
357 return (low | ((uint64_t)high << 32));
360 static __inline uint32_t
365 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
369 static __inline uint64_t
374 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
375 return (low | ((uint64_t)high << 32));
378 static __inline uint64_t
383 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
384 return (low | ((uint64_t)high << 32));
387 static __inline uint32_t
392 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
399 __asm __volatile("wbinvd");
403 write_rflags(u_long rf)
405 __asm __volatile("pushq %0; popfq" : : "r" (rf));
409 wrmsr(u_int msr, uint64_t newval)
415 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
419 load_cr0(u_long data)
422 __asm __volatile("movq %0,%%cr0" : : "r" (data));
425 static __inline u_long
430 __asm __volatile("movq %%cr0,%0" : "=r" (data));
434 static __inline u_long
439 __asm __volatile("movq %%cr2,%0" : "=r" (data));
444 load_cr3(u_long data)
447 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
450 static __inline u_long
455 __asm __volatile("movq %%cr3,%0" : "=r" (data));
460 load_cr4(u_long data)
462 __asm __volatile("movq %0,%%cr4" : : "r" (data));
465 static __inline u_long
470 __asm __volatile("movq %%cr4,%0" : "=r" (data));
474 static __inline u_long
479 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
480 return (low | ((uint64_t)high << 32));
484 load_xcr(u_int reg, u_long val)
490 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
494 * Global TLB flush (except for thise for pages marked PG_G)
504 #define CR4_PGE 0x00000080 /* Page global enable */
508 * Perform the guaranteed invalidation of all TLB entries. This
509 * includes the global entries, and entries in all PCIDs, not only the
510 * current context. The function works both on non-PCID CPUs and CPUs
511 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
512 * Operations that Invalidate TLBs and Paging-Structure Caches.
520 load_cr4(cr4 & ~CR4_PGE);
522 * Although preemption at this point could be detrimental to
523 * performance, it would not lead to an error. PG_G is simply
524 * ignored if CR4.PGE is clear. Moreover, in case this block
525 * is re-entered, the load_cr4() either above or below will
526 * modify CR4.PGE flushing the TLB.
528 load_cr4(cr4 | CR4_PGE);
532 * TLB flush for an individual page (even if it has PG_G).
533 * Only works on 486+ CPUs (i386 does not have PG_G).
539 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
542 #define INVPCID_ADDR 0
543 #define INVPCID_CTX 1
544 #define INVPCID_CTXGLOB 2
545 #define INVPCID_ALLCTX 3
547 struct invpcid_descr {
548 uint64_t pcid:12 __packed;
549 uint64_t pad:52 __packed;
554 invpcid(struct invpcid_descr *d, int type)
557 __asm __volatile("invpcid (%0),%1"
558 : : "r" (d), "r" ((u_long)type) : "memory");
561 static __inline u_short
565 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
569 static __inline u_short
573 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
577 static __inline u_short
581 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
588 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
594 __asm __volatile("movw %0,%%es" : : "rm" (sel));
598 cpu_monitor(const void *addr, u_long extensions, u_int hints)
601 __asm __volatile("monitor"
602 : : "a" (addr), "c" (extensions), "d" (hints));
606 cpu_mwait(u_long extensions, u_int hints)
609 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
613 /* This is defined in <machine/specialreg.h> but is too painful to get to */
615 #define MSR_FSBASE 0xc0000100
620 /* Preserve the fsbase value across the selector load */
621 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
622 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
626 #define MSR_GSBASE 0xc0000101
632 * Preserve the gsbase value across the selector load.
633 * Note that we have to disable interrupts because the gsbase
634 * being trashed happens to be the kernel gsbase at the time.
636 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
637 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
640 /* Usable by userland */
644 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
650 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
654 static __inline uint64_t
659 __asm __volatile("rdfsbase %0" : "=r" (x));
667 __asm __volatile("wrfsbase %0" : : "r" (x));
670 static __inline uint64_t
675 __asm __volatile("rdgsbase %0" : "=r" (x));
683 __asm __volatile("wrgsbase %0" : : "r" (x));
687 bare_lgdt(struct region_descriptor *addr)
689 __asm __volatile("lgdt (%0)" : : "r" (addr));
693 sgdt(struct region_descriptor *addr)
698 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
702 lidt(struct region_descriptor *addr)
704 __asm __volatile("lidt (%0)" : : "r" (addr));
708 sidt(struct region_descriptor *addr)
713 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
719 __asm __volatile("lldt %0" : : "r" (sel));
725 __asm __volatile("ltr %0" : : "r" (sel));
728 static __inline uint32_t
733 __asm __volatile("str %0" : "=r" (sel));
737 static __inline uint64_t
741 __asm __volatile("movq %%dr0,%0" : "=r" (data));
746 load_dr0(uint64_t dr0)
748 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
751 static __inline uint64_t
755 __asm __volatile("movq %%dr1,%0" : "=r" (data));
760 load_dr1(uint64_t dr1)
762 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
765 static __inline uint64_t
769 __asm __volatile("movq %%dr2,%0" : "=r" (data));
774 load_dr2(uint64_t dr2)
776 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
779 static __inline uint64_t
783 __asm __volatile("movq %%dr3,%0" : "=r" (data));
788 load_dr3(uint64_t dr3)
790 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
793 static __inline uint64_t
797 __asm __volatile("movq %%dr6,%0" : "=r" (data));
802 load_dr6(uint64_t dr6)
804 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
807 static __inline uint64_t
811 __asm __volatile("movq %%dr7,%0" : "=r" (data));
816 load_dr7(uint64_t dr7)
818 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
821 static __inline register_t
826 rflags = read_rflags();
832 intr_restore(register_t rflags)
834 write_rflags(rflags);
837 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
839 int breakpoint(void);
840 u_int bsfl(u_int mask);
841 u_int bsrl(u_int mask);
842 void clflush(u_long addr);
844 void cpuid_count(u_int ax, u_int cx, u_int *p);
845 void disable_intr(void);
846 void do_cpuid(u_int ax, u_int *p);
847 void enable_intr(void);
849 void ia32_pause(void);
850 u_char inb(u_int port);
851 u_int inl(u_int port);
852 void insb(u_int port, void *addr, size_t count);
853 void insl(u_int port, void *addr, size_t count);
854 void insw(u_int port, void *addr, size_t count);
855 register_t intr_disable(void);
856 void intr_restore(register_t rf);
858 void invlpg(u_int addr);
860 u_short inw(u_int port);
861 void lidt(struct region_descriptor *addr);
862 void lldt(u_short sel);
863 void load_cr0(u_long cr0);
864 void load_cr3(u_long cr3);
865 void load_cr4(u_long cr4);
866 void load_dr0(uint64_t dr0);
867 void load_dr1(uint64_t dr1);
868 void load_dr2(uint64_t dr2);
869 void load_dr3(uint64_t dr3);
870 void load_dr6(uint64_t dr6);
871 void load_dr7(uint64_t dr7);
872 void load_fs(u_short sel);
873 void load_gs(u_short sel);
874 void ltr(u_short sel);
875 void outb(u_int port, u_char data);
876 void outl(u_int port, u_int data);
877 void outsb(u_int port, const void *addr, size_t count);
878 void outsl(u_int port, const void *addr, size_t count);
879 void outsw(u_int port, const void *addr, size_t count);
880 void outw(u_int port, u_short data);
885 uint64_t rdmsr(u_int msr);
886 uint32_t rdmsr32(u_int msr);
887 uint64_t rdpmc(u_int pmc);
894 uint64_t rdtsc(void);
895 u_long read_rflags(void);
899 void write_rflags(u_int rf);
900 void wrmsr(u_int msr, uint64_t newval);
902 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
904 void reset_dbregs(void);
907 int rdmsr_safe(u_int msr, uint64_t *val);
908 int wrmsr_safe(u_int msr, uint64_t newval);
911 #endif /* !_MACHINE_CPUFUNC_H_ */