2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1993 The Regents of the University of California.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Functions to provide access to special i386 instructions.
37 * This in included in sys/systm.h, and that file should be
38 * used in preference to this.
41 #ifndef _MACHINE_CPUFUNC_H_
42 #define _MACHINE_CPUFUNC_H_
45 #error this file needs sys/cdefs.h as a prerequisite
48 struct region_descriptor;
50 #define readb(va) (*(volatile uint8_t *) (va))
51 #define readw(va) (*(volatile uint16_t *) (va))
52 #define readl(va) (*(volatile uint32_t *) (va))
53 #define readq(va) (*(volatile uint64_t *) (va))
55 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
58 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
60 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
65 __asm __volatile("int $3");
68 #define bsfl(mask) __builtin_ctz(mask)
70 #define bsfq(mask) __builtin_ctzl(mask)
72 #define bsrl(mask) (__builtin_clz(mask) ^ 0x1f)
74 #define bsrq(mask) (__builtin_clzl(mask) ^ 0x3f)
80 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
84 clflushopt(u_long addr)
87 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
94 __asm __volatile("clwb %0" : : "m" (*(char *)addr));
101 __asm __volatile("clts");
107 __asm __volatile("cli" : : : "memory");
111 do_cpuid(u_int ax, u_int *p)
113 __asm __volatile("cpuid"
114 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
119 cpuid_count(u_int ax, u_int cx, u_int *p)
121 __asm __volatile("cpuid"
122 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
123 : "0" (ax), "c" (cx));
129 __asm __volatile("sti");
134 #define HAVE_INLINE_FFS
135 #define ffs(x) __builtin_ffs(x)
137 #define HAVE_INLINE_FFSL
138 #define ffsl(x) __builtin_ffsl(x)
140 #define HAVE_INLINE_FFSLL
141 #define ffsll(x) __builtin_ffsll(x)
143 #define HAVE_INLINE_FLS
145 static __inline __pure2 int
148 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
151 #define HAVE_INLINE_FLSL
153 static __inline __pure2 int
156 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
159 #define HAVE_INLINE_FLSLL
161 static __inline __pure2 int
162 flsll(long long mask)
164 return (flsl((long)mask));
172 __asm __volatile("hlt");
175 static __inline u_char
180 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
184 static __inline u_int
189 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
194 insb(u_int port, void *addr, size_t count)
196 __asm __volatile("rep; insb"
197 : "+D" (addr), "+c" (count)
203 insw(u_int port, void *addr, size_t count)
205 __asm __volatile("rep; insw"
206 : "+D" (addr), "+c" (count)
212 insl(u_int port, void *addr, size_t count)
214 __asm __volatile("rep; insl"
215 : "+D" (addr), "+c" (count)
223 __asm __volatile("invd");
226 static __inline u_short
231 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
236 outb(u_int port, u_char data)
238 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
242 outl(u_int port, u_int data)
244 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
248 outsb(u_int port, const void *addr, size_t count)
250 __asm __volatile("rep; outsb"
251 : "+S" (addr), "+c" (count)
256 outsw(u_int port, const void *addr, size_t count)
258 __asm __volatile("rep; outsw"
259 : "+S" (addr), "+c" (count)
264 outsl(u_int port, const void *addr, size_t count)
266 __asm __volatile("rep; outsl"
267 : "+S" (addr), "+c" (count)
272 outw(u_int port, u_short data)
274 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
277 static __inline u_long
282 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
290 __asm __volatile("lfence" : : : "memory");
297 __asm __volatile("mfence" : : : "memory");
304 __asm __volatile("sfence" : : : "memory");
310 __asm __volatile("pause");
313 static __inline u_long
318 __asm __volatile("pushfq; popq %0" : "=r" (rf));
322 static __inline uint64_t
327 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
328 return (low | ((uint64_t)high << 32));
331 static __inline uint32_t
336 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
340 static __inline uint64_t
345 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
346 return (low | ((uint64_t)high << 32));
349 static __inline uint64_t
354 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
355 return (low | ((uint64_t)high << 32));
358 static __inline uint64_t
363 __asm __volatile("rdtscp" : "=a" (low), "=d" (high) : : "ecx");
364 return (low | ((uint64_t)high << 32));
367 static __inline uint32_t
372 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
376 static __inline uint32_t
381 __asm __volatile("rdtscp" : "=a" (rv) : : "ecx", "edx");
388 __asm __volatile("wbinvd");
392 write_rflags(u_long rf)
394 __asm __volatile("pushq %0; popfq" : : "r" (rf));
398 wrmsr(u_int msr, uint64_t newval)
404 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
408 load_cr0(u_long data)
411 __asm __volatile("movq %0,%%cr0" : : "r" (data));
414 static __inline u_long
419 __asm __volatile("movq %%cr0,%0" : "=r" (data));
423 static __inline u_long
428 __asm __volatile("movq %%cr2,%0" : "=r" (data));
433 load_cr3(u_long data)
436 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
439 static __inline u_long
444 __asm __volatile("movq %%cr3,%0" : "=r" (data));
449 load_cr4(u_long data)
451 __asm __volatile("movq %0,%%cr4" : : "r" (data));
454 static __inline u_long
459 __asm __volatile("movq %%cr4,%0" : "=r" (data));
463 static __inline u_long
468 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
469 return (low | ((uint64_t)high << 32));
473 load_xcr(u_int reg, u_long val)
479 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
483 * Global TLB flush (except for thise for pages marked PG_G)
493 #define CR4_PGE 0x00000080 /* Page global enable */
497 * Perform the guaranteed invalidation of all TLB entries. This
498 * includes the global entries, and entries in all PCIDs, not only the
499 * current context. The function works both on non-PCID CPUs and CPUs
500 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
501 * Operations that Invalidate TLBs and Paging-Structure Caches.
509 load_cr4(cr4 & ~CR4_PGE);
511 * Although preemption at this point could be detrimental to
512 * performance, it would not lead to an error. PG_G is simply
513 * ignored if CR4.PGE is clear. Moreover, in case this block
514 * is re-entered, the load_cr4() either above or below will
515 * modify CR4.PGE flushing the TLB.
517 load_cr4(cr4 | CR4_PGE);
521 * TLB flush for an individual page (even if it has PG_G).
522 * Only works on 486+ CPUs (i386 does not have PG_G).
528 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
531 #define INVPCID_ADDR 0
532 #define INVPCID_CTX 1
533 #define INVPCID_CTXGLOB 2
534 #define INVPCID_ALLCTX 3
536 struct invpcid_descr {
537 uint64_t pcid:12 __packed;
538 uint64_t pad:52 __packed;
543 invpcid(struct invpcid_descr *d, int type)
546 __asm __volatile("invpcid (%0),%1"
547 : : "r" (d), "r" ((u_long)type) : "memory");
550 static __inline u_short
554 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
558 static __inline u_short
562 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
566 static __inline u_short
570 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
577 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
583 __asm __volatile("movw %0,%%es" : : "rm" (sel));
587 cpu_monitor(const void *addr, u_long extensions, u_int hints)
590 __asm __volatile("monitor"
591 : : "a" (addr), "c" (extensions), "d" (hints));
595 cpu_mwait(u_long extensions, u_int hints)
598 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
601 static __inline uint32_t
606 __asm __volatile("rdpkru" : "=a" (res) : "c" (0) : "edx");
611 wrpkru(uint32_t mask)
614 __asm __volatile("wrpkru" : : "a" (mask), "c" (0), "d" (0));
618 /* This is defined in <machine/specialreg.h> but is too painful to get to */
620 #define MSR_FSBASE 0xc0000100
625 /* Preserve the fsbase value across the selector load */
626 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
627 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
631 #define MSR_GSBASE 0xc0000101
637 * Preserve the gsbase value across the selector load.
638 * Note that we have to disable interrupts because the gsbase
639 * being trashed happens to be the kernel gsbase at the time.
641 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
642 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
645 /* Usable by userland */
649 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
655 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
659 static __inline uint64_t
664 __asm __volatile("rdfsbase %0" : "=r" (x));
672 __asm __volatile("wrfsbase %0" : : "r" (x));
675 static __inline uint64_t
680 __asm __volatile("rdgsbase %0" : "=r" (x));
688 __asm __volatile("wrgsbase %0" : : "r" (x));
692 bare_lgdt(struct region_descriptor *addr)
694 __asm __volatile("lgdt (%0)" : : "r" (addr));
698 sgdt(struct region_descriptor *addr)
703 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
707 lidt(struct region_descriptor *addr)
709 __asm __volatile("lidt (%0)" : : "r" (addr));
713 sidt(struct region_descriptor *addr)
718 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
724 __asm __volatile("lldt %0" : : "r" (sel));
727 static __inline u_short
732 __asm __volatile("sldt %0" : "=r" (sel));
739 __asm __volatile("ltr %0" : : "r" (sel));
742 static __inline uint32_t
747 __asm __volatile("str %0" : "=r" (sel));
751 static __inline uint64_t
755 __asm __volatile("movq %%dr0,%0" : "=r" (data));
760 load_dr0(uint64_t dr0)
762 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
765 static __inline uint64_t
769 __asm __volatile("movq %%dr1,%0" : "=r" (data));
774 load_dr1(uint64_t dr1)
776 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
779 static __inline uint64_t
783 __asm __volatile("movq %%dr2,%0" : "=r" (data));
788 load_dr2(uint64_t dr2)
790 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
793 static __inline uint64_t
797 __asm __volatile("movq %%dr3,%0" : "=r" (data));
802 load_dr3(uint64_t dr3)
804 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
807 static __inline uint64_t
811 __asm __volatile("movq %%dr6,%0" : "=r" (data));
816 load_dr6(uint64_t dr6)
818 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
821 static __inline uint64_t
825 __asm __volatile("movq %%dr7,%0" : "=r" (data));
830 load_dr7(uint64_t dr7)
832 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
835 static __inline register_t
840 rflags = read_rflags();
846 intr_restore(register_t rflags)
848 write_rflags(rflags);
855 __asm __volatile("stac" : : : "cc");
862 __asm __volatile("clac" : : : "cc");
888 int sgx_encls(uint32_t eax, uint64_t rbx, uint64_t rcx, uint64_t rdx);
891 sgx_ecreate(void *pginfo, void *secs)
894 return (sgx_encls(SGX_ECREATE, (uint64_t)pginfo,
899 sgx_eadd(void *pginfo, void *epc)
902 return (sgx_encls(SGX_EADD, (uint64_t)pginfo,
907 sgx_einit(void *sigstruct, void *secs, void *einittoken)
910 return (sgx_encls(SGX_EINIT, (uint64_t)sigstruct,
911 (uint64_t)secs, (uint64_t)einittoken));
915 sgx_eextend(void *secs, void *epc)
918 return (sgx_encls(SGX_EEXTEND, (uint64_t)secs,
926 return (sgx_encls(SGX_EPA, SGX_PT_VA, (uint64_t)epc, 0));
930 sgx_eldu(uint64_t rbx, uint64_t rcx,
934 return (sgx_encls(SGX_ELDU, rbx, rcx, rdx));
938 sgx_eremove(void *epc)
941 return (sgx_encls(SGX_EREMOVE, 0, (uint64_t)epc, 0));
944 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
946 int breakpoint(void);
947 u_int bsfl(u_int mask);
948 u_int bsrl(u_int mask);
949 void clflush(u_long addr);
951 void cpuid_count(u_int ax, u_int cx, u_int *p);
952 void disable_intr(void);
953 void do_cpuid(u_int ax, u_int *p);
954 void enable_intr(void);
956 void ia32_pause(void);
957 u_char inb(u_int port);
958 u_int inl(u_int port);
959 void insb(u_int port, void *addr, size_t count);
960 void insl(u_int port, void *addr, size_t count);
961 void insw(u_int port, void *addr, size_t count);
962 register_t intr_disable(void);
963 void intr_restore(register_t rf);
965 void invlpg(u_int addr);
967 u_short inw(u_int port);
968 void lidt(struct region_descriptor *addr);
969 void lldt(u_short sel);
970 void load_cr0(u_long cr0);
971 void load_cr3(u_long cr3);
972 void load_cr4(u_long cr4);
973 void load_dr0(uint64_t dr0);
974 void load_dr1(uint64_t dr1);
975 void load_dr2(uint64_t dr2);
976 void load_dr3(uint64_t dr3);
977 void load_dr6(uint64_t dr6);
978 void load_dr7(uint64_t dr7);
979 void load_fs(u_short sel);
980 void load_gs(u_short sel);
981 void ltr(u_short sel);
982 void outb(u_int port, u_char data);
983 void outl(u_int port, u_int data);
984 void outsb(u_int port, const void *addr, size_t count);
985 void outsl(u_int port, const void *addr, size_t count);
986 void outsw(u_int port, const void *addr, size_t count);
987 void outw(u_int port, u_short data);
992 uint64_t rdmsr(u_int msr);
993 uint32_t rdmsr32(u_int msr);
994 uint64_t rdpmc(u_int pmc);
1000 uint64_t rdr7(void);
1001 uint64_t rdtsc(void);
1002 u_long read_rflags(void);
1006 void write_rflags(u_int rf);
1007 void wrmsr(u_int msr, uint64_t newval);
1009 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
1011 void reset_dbregs(void);
1014 int rdmsr_safe(u_int msr, uint64_t *val);
1015 int wrmsr_safe(u_int msr, uint64_t newval);
1018 #endif /* !_MACHINE_CPUFUNC_H_ */