2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __MACHINE_INTR_MACHDEP_H__
32 #define __MACHINE_INTR_MACHDEP_H__
37 * The maximum number of I/O interrupts we allow. This number is rather
38 * arbitrary as it is just the maximum IRQ resource value. The interrupt
39 * source for a given IRQ maps that I/O interrupt to device interrupt
40 * source whether it be a pin on an interrupt controller or an MSI interrupt.
41 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
42 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT
43 * vectors available for device interrupts. On many systems with I/O APICs,
44 * a lot of the IRQs are not used, so this number can be much larger than
45 * 191 and still be safe since only interrupt sources in actual use will
46 * allocate IDT vectors.
48 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
49 * IRQ values from 256 to 767 are used by MSI. When running under the Xen
50 * Hypervisor, IRQ values from 768 to 4863 are available for binding to
51 * event channel events. We leave 255 unused to avoid confusion since 255 is
52 * used in PCI to indicate an invalid IRQ.
54 #define NUM_MSI_INTS 512
55 #define FIRST_MSI_INT 256
57 #include <xen/xen-os.h>
58 #include <xen/interface/event_channel.h>
59 #define NUM_EVTCHN_INTS NR_EVENT_CHANNELS
60 #define FIRST_EVTCHN_INT \
61 (FIRST_MSI_INT + NUM_MSI_INTS)
62 #define LAST_EVTCHN_INT \
63 (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1)
65 #define NUM_EVTCHN_INTS 0
67 #define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS)
70 * Default base address for MSI messages on x86 platforms.
72 #define MSI_INTEL_ADDR_BASE 0xfee00000
75 * - 1 ??? dummy counter.
76 * - 2 counters for each I/O interrupt.
77 * - 1 counter for each CPU for lapic timer.
78 * - 8 counters for each CPU for IPI counters for SMP.
81 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU)
83 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
88 typedef void inthand_t(void);
90 #define IDTVEC(name) __CONCAT(X,name)
95 * Methods that a PIC provides to mask/unmask a given interrupt source,
96 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
97 * return the vector associated with this source.
100 void (*pic_enable_source)(struct intsrc *);
101 void (*pic_disable_source)(struct intsrc *, int);
102 void (*pic_eoi_source)(struct intsrc *);
103 void (*pic_enable_intr)(struct intsrc *);
104 void (*pic_disable_intr)(struct intsrc *);
105 int (*pic_vector)(struct intsrc *);
106 int (*pic_source_pending)(struct intsrc *);
107 void (*pic_suspend)(struct pic *);
108 void (*pic_resume)(struct pic *, bool suspend_cancelled);
109 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
111 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
112 void (*pic_reprogram_pin)(struct intsrc *);
113 TAILQ_ENTRY(pic) pics;
116 /* Flags for pic_disable_source() */
123 * An interrupt source. The upper-layer code uses the PIC methods to
124 * control a given source. The lower-layer PIC drivers can store additional
125 * private data in a given interrupt source such as an interrupt pin number
126 * or an I/O APIC pointer.
130 struct intr_event *is_event;
132 u_long *is_straycount;
141 * The following data structure holds per-cpu data, and is placed just
142 * above the top of the space used for the NMI and MC# stacks.
146 register_t __padding; /* pad to 16 bytes */
150 extern cpuset_t intr_cpus;
152 extern struct mtx icu_lock;
153 extern int elcr_found;
155 extern int msix_disable_migration;
159 void atpic_reset(void);
161 /* XXX: The elcr_* prototypes probably belong somewhere else. */
162 int elcr_probe(void);
163 enum intr_trigger elcr_read_trigger(u_int irq);
164 void elcr_resume(void);
165 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
167 void intr_add_cpu(u_int cpu);
169 int intr_add_handler(const char *name, int vector, driver_filter_t filter,
170 driver_intr_t handler, void *arg, enum intr_type flags,
173 int intr_bind(u_int vector, u_char cpu);
175 int intr_config_intr(int vector, enum intr_trigger trig,
176 enum intr_polarity pol);
177 int intr_describe(u_int vector, void *ih, const char *descr);
178 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
179 u_int intr_next_cpu(void);
180 struct intsrc *intr_lookup_source(int vector);
181 int intr_register_pic(struct pic *pic);
182 int intr_register_source(struct intsrc *isrc);
183 int intr_remove_handler(void *cookie);
184 void intr_resume(bool suspend_cancelled);
185 void intr_suspend(void);
186 void intr_reprogram(void);
187 void intrcnt_add(const char *name, u_long **countp);
188 void nexus_add_irq(u_long irq);
189 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
191 int msi_map(int irq, uint64_t *addr, uint32_t *data);
192 int msi_release(int *irqs, int count);
193 int msix_alloc(device_t dev, int *irq);
194 int msix_release(int irq);
198 #endif /* !__MACHINE_INTR_MACHDEP_H__ */