2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include "opt_user_ldt.h"
33 #include <machine/smptests.h>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
46 #include <sys/dkstat.h>
48 #include <sys/cons.h> /* cngetc() */
51 #include <vm/vm_param.h>
53 #include <vm/vm_kern.h>
54 #include <vm/vm_extern.h>
57 #include <vm/vm_map.h>
64 #include <machine/smp.h>
65 #include <machine/apic.h>
66 #include <machine/atomic.h>
67 #include <machine/cpufunc.h>
68 #include <machine/mpapic.h>
69 #include <machine/psl.h>
70 #include <machine/segments.h>
71 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
72 #include <machine/tss.h>
73 #include <machine/specialreg.h>
74 #include <machine/globaldata.h>
77 #include <machine/md_var.h> /* setidt() */
78 #include <i386/isa/icu.h> /* IPIs */
79 #include <i386/isa/intr_machdep.h> /* IPIs */
82 #if defined(TEST_DEFAULT_CONFIG)
83 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
85 #define MPFPS_MPFB1 mpfps->mpfb1
86 #endif /* TEST_DEFAULT_CONFIG */
88 #define WARMBOOT_TARGET 0
89 #define WARMBOOT_OFF (KERNBASE + 0x0467)
90 #define WARMBOOT_SEG (KERNBASE + 0x0469)
93 #define BIOS_BASE (0xe8000)
94 #define BIOS_SIZE (0x18000)
96 #define BIOS_BASE (0xf0000)
97 #define BIOS_SIZE (0x10000)
99 #define BIOS_COUNT (BIOS_SIZE/4)
101 #define CMOS_REG (0x70)
102 #define CMOS_DATA (0x71)
103 #define BIOS_RESET (0x0f)
104 #define BIOS_WARM (0x0a)
106 #define PROCENTRY_FLAG_EN 0x01
107 #define PROCENTRY_FLAG_BP 0x02
108 #define IOAPICENTRY_FLAG_EN 0x01
111 /* MP Floating Pointer Structure */
112 typedef struct MPFPS {
125 /* MP Configuration Table Header */
126 typedef struct MPCTH {
128 u_short base_table_length;
132 u_char product_id[12];
133 void *oem_table_pointer;
134 u_short oem_table_size;
137 u_short extended_table_length;
138 u_char extended_table_checksum;
143 typedef struct PROCENTRY {
148 u_long cpu_signature;
149 u_long feature_flags;
154 typedef struct BUSENTRY {
160 typedef struct IOAPICENTRY {
166 } *io_apic_entry_ptr;
168 typedef struct INTENTRY {
178 /* descriptions of MP basetable entries */
179 typedef struct BASETABLE_ENTRY {
186 * this code MUST be enabled here and in mpboot.s.
187 * it follows the very early stages of AP boot by placing values in CMOS ram.
188 * it NORMALLY will never be needed and thus the primitive method for enabling.
193 #if defined(CHECK_POINTS) && !defined(PC98)
194 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
195 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
197 #define CHECK_INIT(D); \
198 CHECK_WRITE(0x34, (D)); \
199 CHECK_WRITE(0x35, (D)); \
200 CHECK_WRITE(0x36, (D)); \
201 CHECK_WRITE(0x37, (D)); \
202 CHECK_WRITE(0x38, (D)); \
203 CHECK_WRITE(0x39, (D));
205 #define CHECK_PRINT(S); \
206 printf("%s: %d, %d, %d, %d, %d, %d\n", \
215 #else /* CHECK_POINTS */
217 #define CHECK_INIT(D)
218 #define CHECK_PRINT(S)
220 #endif /* CHECK_POINTS */
223 * Values to send to the POST hardware.
225 #define MP_BOOTADDRESS_POST 0x10
226 #define MP_PROBE_POST 0x11
227 #define MPTABLE_PASS1_POST 0x12
229 #define MP_START_POST 0x13
230 #define MP_ENABLE_POST 0x14
231 #define MPTABLE_PASS2_POST 0x15
233 #define START_ALL_APS_POST 0x16
234 #define INSTALL_AP_TRAMP_POST 0x17
235 #define START_AP_POST 0x18
237 #define MP_ANNOUNCE_POST 0x19
240 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
241 int current_postcode;
243 /** XXX FIXME: what system files declare these??? */
244 extern struct region_descriptor r_gdt, r_idt;
246 int bsp_apic_ready = 0; /* flags useability of BSP apic */
247 int mp_ncpus; /* # of CPUs, including BSP */
248 int mp_naps; /* # of Applications processors */
249 int mp_nbusses; /* # of busses */
250 int mp_napics; /* # of IO APICs */
251 int boot_cpu_id; /* designated BSP */
252 vm_offset_t cpu_apic_address;
253 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
256 u_int32_t cpu_apic_versions[NCPU];
257 u_int32_t io_apic_versions[NAPIC];
259 #ifdef APIC_INTR_DIAGNOSTIC
260 int apic_itrace_enter[32];
261 int apic_itrace_tryisrlock[32];
262 int apic_itrace_gotisrlock[32];
263 int apic_itrace_active[32];
264 int apic_itrace_masked[32];
265 int apic_itrace_noisrlock[32];
266 int apic_itrace_masked2[32];
267 int apic_itrace_unmask[32];
268 int apic_itrace_noforward[32];
269 int apic_itrace_leave[32];
270 int apic_itrace_enter2[32];
271 int apic_itrace_doreti[32];
272 int apic_itrace_splz[32];
273 int apic_itrace_eoi[32];
274 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
275 unsigned short apic_itrace_debugbuffer[32768];
276 int apic_itrace_debugbuffer_idx;
277 struct simplelock apic_itrace_debuglock;
281 #ifdef APIC_INTR_REORDER
283 volatile int *location;
285 } apic_isrbit_location[32];
288 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
291 * APIC ID logical/physical mapping structures.
292 * We oversize these to simplify boot-time config.
294 int cpu_num_to_apic_id[NAPICID];
295 int io_num_to_apic_id[NAPICID];
296 int apic_id_to_logical[NAPICID];
299 /* Bitmap of all available CPUs */
302 /* AP uses this during bootstrap. Do not staticize. */
306 /* Hotwire a 0->4MB V==P mapping */
307 extern pt_entry_t *KPTphys;
309 /* SMP page table page */
310 extern pt_entry_t *SMPpt;
312 struct pcb stoppcbs[NCPU];
314 int smp_started; /* has the system started? */
317 * Local data and functions.
320 static int mp_capable;
321 static u_int boot_address;
322 static u_int base_memory;
324 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
325 static mpfps_t mpfps;
326 static int search_for_sig(u_int32_t target, int count);
327 static void mp_enable(u_int boot_addr);
329 static int mptable_pass1(void);
330 static int mptable_pass2(void);
331 static void default_mp_table(int type);
332 static void fix_mp_table(void);
333 static void setup_apic_irq_mapping(void);
334 static void init_locks(void);
335 static int start_all_aps(u_int boot_addr);
336 static void install_ap_tramp(u_int boot_addr);
337 static int start_ap(int logicalCpu, u_int boot_addr);
340 * Calculate usable address in base memory for AP trampoline code.
343 mp_bootaddress(u_int basemem)
345 POSTCODE(MP_BOOTADDRESS_POST);
347 base_memory = basemem * 1024; /* convert to bytes */
349 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
350 if ((base_memory - boot_address) < bootMP_size)
351 boot_address -= 4096; /* not enough, lower by 4k */
358 * Look for an Intel MP spec table (ie, SMP capable hardware).
367 POSTCODE(MP_PROBE_POST);
369 /* see if EBDA exists */
370 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
371 /* search first 1K of EBDA */
372 target = (u_int32_t) (segment << 4);
373 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
376 /* last 1K of base memory, effective 'top of base' passed in */
377 target = (u_int32_t) (base_memory - 0x400);
378 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
382 /* search the BIOS */
383 target = (u_int32_t) BIOS_BASE;
384 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
393 /* calculate needed resources */
396 panic("you must reconfigure your kernel");
398 /* flag fact that we are running multiple processors */
405 * Startup the SMP processors.
410 POSTCODE(MP_START_POST);
412 /* look for MP capable motherboard */
414 mp_enable(boot_address);
416 panic("MP hardware not found!");
421 * Print various information about the SMP system hardware and setup.
428 POSTCODE(MP_ANNOUNCE_POST);
430 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
431 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
432 printf(", version: 0x%08x", cpu_apic_versions[0]);
433 printf(", at 0x%08x\n", cpu_apic_address);
434 for (x = 1; x <= mp_naps; ++x) {
435 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
436 printf(", version: 0x%08x", cpu_apic_versions[x]);
437 printf(", at 0x%08x\n", cpu_apic_address);
441 for (x = 0; x < mp_napics; ++x) {
442 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
443 printf(", version: 0x%08x", io_apic_versions[x]);
444 printf(", at 0x%08x\n", io_apic_address[x]);
447 printf(" Warning: APIC I/O disabled\n");
452 * AP cpu's call this to sync up protected mode.
458 int x, myid = bootAP;
460 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
461 gdt_segs[GPROC0_SEL].ssd_base =
462 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
463 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid];
465 for (x = 0; x < NGDT; x++) {
466 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
469 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
470 r_gdt.rd_base = (int) &gdt[myid * NGDT];
471 lgdt(&r_gdt); /* does magic intra-segment return */
477 currentldt = _default_ldt;
480 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
481 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
482 common_tss.tss_esp0 = 0; /* not used until after switch */
483 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
484 common_tss.tss_ioopt = (sizeof common_tss) << 16;
485 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
486 common_tssd = *tss_gdt;
489 load_cr0(0x8005003b); /* XXX! */
497 * Final configuration of the BSP's local APIC:
498 * - disable 'pic mode'.
499 * - disable 'virtual wire mode'.
503 bsp_apic_configure(void)
508 /* leave 'pic mode' if necessary */
510 outb(0x22, 0x70); /* select IMCR */
511 byte = inb(0x23); /* current contents */
512 byte |= 0x01; /* mask external INTR */
513 outb(0x23, byte); /* disconnect 8259s/NMI */
516 /* mask lint0 (the 8259 'virtual wire' connection) */
517 temp = lapic.lvt_lint0;
518 temp |= APIC_LVT_M; /* set the mask */
519 lapic.lvt_lint0 = temp;
521 /* setup lint1 to handle NMI */
522 temp = lapic.lvt_lint1;
523 temp &= ~APIC_LVT_M; /* clear the mask */
524 lapic.lvt_lint1 = temp;
527 apic_dump("bsp_apic_configure()");
532 /*******************************************************************
533 * local functions and data
537 * start the SMP system
540 mp_enable(u_int boot_addr)
548 POSTCODE(MP_ENABLE_POST);
550 /* turn on 4MB of V == P addressing so we can get to MP table */
551 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
554 /* examine the MP table for needed info, uses physical addresses */
560 /* can't process default configs till the CPU APIC is pmapped */
564 /* post scan cleanup */
566 setup_apic_irq_mapping();
570 /* fill the LOGICAL io_apic_versions table */
571 for (apic = 0; apic < mp_napics; ++apic) {
572 ux = io_apic_read(apic, IOAPIC_VER);
573 io_apic_versions[apic] = ux;
576 /* program each IO APIC in the system */
577 for (apic = 0; apic < mp_napics; ++apic)
578 if (io_apic_setup(apic) < 0)
579 panic("IO APIC setup failure");
581 /* install a 'Spurious INTerrupt' vector */
582 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
585 /* install an inter-CPU IPI for TLB invalidation */
586 setidt(XINVLTLB_OFFSET, Xinvltlb,
587 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
590 /* install an inter-CPU IPI for reading processor state */
591 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
595 /* install an inter-CPU IPI for all-CPU rendezvous */
596 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599 /* install an inter-CPU IPI for forcing an additional software trap */
600 setidt(XCPUAST_OFFSET, Xcpuast,
601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
603 /* install an inter-CPU IPI for interrupt forwarding */
604 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
605 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
607 /* install an inter-CPU IPI for CPU stop/restart */
608 setidt(XCPUSTOP_OFFSET, Xcpustop,
609 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
611 #if defined(TEST_TEST1)
612 /* install a "fake hardware INTerrupt" vector */
613 setidt(XTEST1_OFFSET, Xtest1,
614 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
615 #endif /** TEST_TEST1 */
619 /* initialize all SMP locks */
622 /* start each Application Processor */
623 start_all_aps(boot_addr);
626 * The init process might be started on a different CPU now,
627 * and the boot CPU might not call prepare_usermode to get
628 * cr0 correctly configured. Thus we initialize cr0 here.
630 load_cr0(rcr0() | CR0_WP | CR0_AM);
635 * look for the MP spec signature
638 /* string defined by the Intel MP Spec as identifying the MP table */
639 #define MP_SIG 0x5f504d5f /* _MP_ */
640 #define NEXT(X) ((X) += 4)
642 search_for_sig(u_int32_t target, int count)
645 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
647 for (x = 0; x < count; NEXT(x))
648 if (addr[x] == MP_SIG)
649 /* make array index a byte index */
650 return (target + (x * sizeof(u_int32_t)));
656 static basetable_entry basetable_entry_types[] =
658 {0, 20, "Processor"},
665 typedef struct BUSDATA {
667 enum busTypes bus_type;
670 typedef struct INTDATA {
680 typedef struct BUSTYPENAME {
685 static bus_type_name bus_type_table[] =
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
703 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"}
707 /* from MP spec v1.4, table 5-1 */
708 static int default_data[7][5] =
710 /* nbus, id0, type0, id1, type1 */
711 {1, 0, ISA, 255, 255},
712 {1, 0, EISA, 255, 255},
713 {1, 0, EISA, 255, 255},
714 {0, 255, 255, 255, 255},/* MCA not supported */
716 {2, 0, EISA, 1, PCI},
717 {0, 255, 255, 255, 255} /* MCA not supported */
722 static bus_datum bus_data[NBUS];
724 /* the IO INT data, one entry per possible APIC INTerrupt */
725 static io_int io_apic_ints[NINTR];
729 static int processor_entry __P((proc_entry_ptr entry, int cpu));
730 static int bus_entry __P((bus_entry_ptr entry, int bus));
731 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
732 static int int_entry __P((int_entry_ptr entry, int intr));
733 static int lookup_bus_type __P((char *name));
737 * 1st pass on motherboard's Intel MP specification table.
743 * cpu_apic_address (common to all CPUs)
761 POSTCODE(MPTABLE_PASS1_POST);
765 /* clear various tables */
766 for (x = 0; x < NAPICID; ++x) {
767 io_apic_address[x] = ~0; /* IO APIC address table */
770 /* init everything to empty */
776 /* check for use of 'default' configuration */
777 if (MPFPS_MPFB1 != 0) {
778 /* use default addresses */
779 cpu_apic_address = DEFAULT_APIC_BASE;
780 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
782 /* fill in with defaults */
783 mp_naps = 2; /* includes BSP */
784 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
791 if ((cth = mpfps->pap) == 0)
792 panic("MP Configuration Table Header MISSING!");
794 cpu_apic_address = (vm_offset_t) cth->apic_address;
796 /* walk the table, recording info of interest */
797 totalSize = cth->base_table_length - sizeof(struct MPCTH);
798 position = (u_char *) cth + sizeof(struct MPCTH);
799 count = cth->entry_count;
802 switch (type = *(u_char *) position) {
803 case 0: /* processor_entry */
804 if (((proc_entry_ptr)position)->cpu_flags
808 case 1: /* bus_entry */
811 case 2: /* io_apic_entry */
812 if (((io_apic_entry_ptr)position)->apic_flags
813 & IOAPICENTRY_FLAG_EN)
814 io_apic_address[mp_napics++] =
815 (vm_offset_t)((io_apic_entry_ptr)
816 position)->apic_address;
818 case 3: /* int_entry */
821 case 4: /* int_entry */
824 panic("mpfps Base Table HOSED!");
828 totalSize -= basetable_entry_types[type].length;
829 (u_char*)position += basetable_entry_types[type].length;
833 /* qualify the numbers */
834 if (mp_naps > NCPU) {
835 printf("Warning: only using %d of %d available CPUs!\n",
839 if (mp_nbusses > NBUS) {
840 printf("found %d busses, increase NBUS\n", mp_nbusses);
843 if (mp_napics > NAPIC) {
844 printf("found %d apics, increase NAPIC\n", mp_napics);
847 if (nintrs > NINTR) {
848 printf("found %d intrs, increase NINTR\n", nintrs);
854 * This is also used as a counter while starting the APs.
858 --mp_naps; /* subtract the BSP */
865 * 2nd pass on motherboard's Intel MP specification table.
869 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
870 * CPU_TO_ID(N), logical CPU to APIC ID table
871 * IO_TO_ID(N), logical IO to APIC ID table
884 int apic, bus, cpu, intr;
886 POSTCODE(MPTABLE_PASS2_POST);
888 /* clear various tables */
889 for (x = 0; x < NAPICID; ++x) {
890 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
891 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
892 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
895 /* clear bus data table */
896 for (x = 0; x < NBUS; ++x)
897 bus_data[x].bus_id = 0xff;
899 /* clear IO APIC INT table */
900 for (x = 0; x < NINTR; ++x) {
901 io_apic_ints[x].int_type = 0xff;
902 io_apic_ints[x].int_vector = 0xff;
905 /* setup the cpu/apic mapping arrays */
908 /* record whether PIC or virtual-wire mode */
909 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
911 /* check for use of 'default' configuration */
912 if (MPFPS_MPFB1 != 0)
913 return MPFPS_MPFB1; /* return default configuration type */
915 if ((cth = mpfps->pap) == 0)
916 panic("MP Configuration Table Header MISSING!");
918 /* walk the table, recording info of interest */
919 totalSize = cth->base_table_length - sizeof(struct MPCTH);
920 position = (u_char *) cth + sizeof(struct MPCTH);
921 count = cth->entry_count;
922 apic = bus = intr = 0;
923 cpu = 1; /* pre-count the BSP */
926 switch (type = *(u_char *) position) {
928 if (processor_entry(position, cpu))
932 if (bus_entry(position, bus))
936 if (io_apic_entry(position, apic))
940 if (int_entry(position, intr))
944 /* int_entry(position); */
947 panic("mpfps Base Table HOSED!");
951 totalSize -= basetable_entry_types[type].length;
952 (u_char *) position += basetable_entry_types[type].length;
955 if (boot_cpu_id == -1)
956 panic("NO BSP found!");
958 /* report fact that its NOT a default configuration */
964 assign_apic_irq(int apic, int intpin, int irq)
968 if (int_to_apicintpin[irq].ioapic != -1)
969 panic("assign_apic_irq: inconsistent table");
971 int_to_apicintpin[irq].ioapic = apic;
972 int_to_apicintpin[irq].int_pin = intpin;
973 int_to_apicintpin[irq].apic_address = ioapic[apic];
974 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
976 for (x = 0; x < nintrs; x++) {
977 if ((io_apic_ints[x].int_type == 0 ||
978 io_apic_ints[x].int_type == 3) &&
979 io_apic_ints[x].int_vector == 0xff &&
980 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
981 io_apic_ints[x].dst_apic_int == intpin)
982 io_apic_ints[x].int_vector = irq;
987 * parse an Intel MP specification table
994 int bus_0 = 0; /* Stop GCC warning */
995 int bus_pci = 0; /* Stop GCC warning */
999 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1000 * did it wrong. The MP spec says that when more than 1 PCI bus
1001 * exists the BIOS must begin with bus entries for the PCI bus and use
1002 * actual PCI bus numbering. This implies that when only 1 PCI bus
1003 * exists the BIOS can choose to ignore this ordering, and indeed many
1004 * MP motherboards do ignore it. This causes a problem when the PCI
1005 * sub-system makes requests of the MP sub-system based on PCI bus
1006 * numbers. So here we look for the situation and renumber the
1007 * busses and associated INTs in an effort to "make it right".
1010 /* find bus 0, PCI bus, count the number of PCI busses */
1011 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1012 if (bus_data[x].bus_id == 0) {
1015 if (bus_data[x].bus_type == PCI) {
1021 * bus_0 == slot of bus with ID of 0
1022 * bus_pci == slot of last PCI bus encountered
1025 /* check the 1 PCI bus case for sanity */
1026 if (num_pci_bus == 1) {
1028 /* if it is number 0 all is well */
1029 if (bus_data[bus_pci].bus_id == 0)
1032 /* mis-numbered, swap with whichever bus uses slot 0 */
1034 /* swap the bus entry types */
1035 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1036 bus_data[bus_0].bus_type = PCI;
1038 /* swap each relavant INTerrupt entry */
1039 id = bus_data[bus_pci].bus_id;
1040 for (x = 0; x < nintrs; ++x) {
1041 if (io_apic_ints[x].src_bus_id == id) {
1042 io_apic_ints[x].src_bus_id = 0;
1044 else if (io_apic_ints[x].src_bus_id == 0) {
1045 io_apic_ints[x].src_bus_id = id;
1049 /* sanity check if more than 1 PCI bus */
1050 else if (num_pci_bus > 1) {
1051 for (x = 0; x < mp_nbusses; ++x) {
1052 if (bus_data[x].bus_type != PCI)
1060 setup_apic_irq_mapping(void)
1065 /* Assign low level interrupt handlers */
1066 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1067 int_to_apicintpin[x].ioapic = -1;
1068 int_to_apicintpin[x].int_pin = 0;
1069 int_to_apicintpin[x].apic_address = NULL;
1070 int_to_apicintpin[x].redirindex = 0;
1072 for (x = 0; x < nintrs; x++) {
1073 if (io_apic_ints[x].dst_apic_int < APIC_INTMAPSIZE &&
1074 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1075 io_apic_ints[x].int_vector == 0xff &&
1076 (io_apic_ints[x].int_type == 0 ||
1077 io_apic_ints[x].int_type == 3)) {
1079 io_apic_ints[x].dst_apic_int,
1080 io_apic_ints[x].dst_apic_int);
1084 while (int_vector < APIC_INTMAPSIZE &&
1085 int_to_apicintpin[int_vector].ioapic != -1)
1087 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1088 if ((io_apic_ints[x].int_type == 0 ||
1089 io_apic_ints[x].int_type == 3) &&
1090 io_apic_ints[x].int_vector == 0xff) {
1091 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1092 io_apic_ints[x].dst_apic_int,
1095 while (int_vector < APIC_INTMAPSIZE &&
1096 int_to_apicintpin[int_vector].ioapic != -1)
1104 processor_entry(proc_entry_ptr entry, int cpu)
1106 /* check for usability */
1107 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN))
1110 /* check for BSP flag */
1111 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1112 boot_cpu_id = entry->apic_id;
1113 CPU_TO_ID(0) = entry->apic_id;
1114 ID_TO_CPU(entry->apic_id) = 0;
1115 return 0; /* its already been counted */
1118 /* add another AP to list, if less than max number of CPUs */
1120 CPU_TO_ID(cpu) = entry->apic_id;
1121 ID_TO_CPU(entry->apic_id) = cpu;
1128 bus_entry(bus_entry_ptr entry, int bus)
1133 /* encode the name into an index */
1134 for (x = 0; x < 6; ++x) {
1135 if ((c = entry->bus_type[x]) == ' ')
1141 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1142 panic("unknown bus type: '%s'", name);
1144 bus_data[bus].bus_id = entry->bus_id;
1145 bus_data[bus].bus_type = x;
1152 io_apic_entry(io_apic_entry_ptr entry, int apic)
1154 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1157 IO_TO_ID(apic) = entry->apic_id;
1158 ID_TO_IO(entry->apic_id) = apic;
1165 lookup_bus_type(char *name)
1169 for (x = 0; x < MAX_BUSTYPE; ++x)
1170 if (strcmp(bus_type_table[x].name, name) == 0)
1171 return bus_type_table[x].type;
1173 return UNKNOWN_BUSTYPE;
1178 int_entry(int_entry_ptr entry, int intr)
1182 io_apic_ints[intr].int_type = entry->int_type;
1183 io_apic_ints[intr].int_flags = entry->int_flags;
1184 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1185 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1186 if (entry->dst_apic_id == 255) {
1187 /* This signal goes to all IO APICS. Select an IO APIC
1188 with sufficient number of interrupt pins */
1189 for (apic = 0; apic < mp_napics; apic++)
1190 if (((io_apic_read(apic, IOAPIC_VER) &
1191 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1192 entry->dst_apic_int)
1194 if (apic < mp_napics)
1195 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1197 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1199 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1200 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1207 apic_int_is_bus_type(int intr, int bus_type)
1211 for (bus = 0; bus < mp_nbusses; ++bus)
1212 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1213 && ((int) bus_data[bus].bus_type == bus_type))
1221 * Given a traditional ISA INT mask, return an APIC mask.
1224 isa_apic_mask(u_int isa_mask)
1229 #if defined(SKIP_IRQ15_REDIRECT)
1230 if (isa_mask == (1 << 15)) {
1231 printf("skipping ISA IRQ15 redirect\n");
1234 #endif /* SKIP_IRQ15_REDIRECT */
1236 isa_irq = ffs(isa_mask); /* find its bit position */
1237 if (isa_irq == 0) /* doesn't exist */
1239 --isa_irq; /* make it zero based */
1241 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1245 return (1 << apic_pin); /* convert pin# to a mask */
1250 * Determine which APIC pin an ISA/EISA INT is attached to.
1252 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1253 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1254 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1255 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1257 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1259 isa_apic_irq(int isa_irq)
1263 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1264 if (INTTYPE(intr) == 0) { /* standard INT */
1265 if (SRCBUSIRQ(intr) == isa_irq) {
1266 if (apic_int_is_bus_type(intr, ISA) ||
1267 apic_int_is_bus_type(intr, EISA))
1268 return INTIRQ(intr); /* found */
1272 return -1; /* NOT found */
1277 * Determine which APIC pin a PCI INT is attached to.
1279 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1280 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1281 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1283 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1287 --pciInt; /* zero based */
1289 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1290 if ((INTTYPE(intr) == 0) /* standard INT */
1291 && (SRCBUSID(intr) == pciBus)
1292 && (SRCBUSDEVICE(intr) == pciDevice)
1293 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1294 if (apic_int_is_bus_type(intr, PCI))
1295 return INTIRQ(intr); /* exact match */
1297 return -1; /* NOT found */
1301 next_apic_irq(int irq)
1308 for (intr = 0; intr < nintrs; intr++) {
1309 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1311 bus = SRCBUSID(intr);
1312 bustype = apic_bus_type(bus);
1313 if (bustype != ISA &&
1319 if (intr >= nintrs) {
1322 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1323 if (INTTYPE(ointr) != 0)
1325 if (bus != SRCBUSID(ointr))
1327 if (bustype == PCI) {
1328 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1330 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1333 if (bustype == ISA || bustype == EISA) {
1334 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1337 if (INTPIN(intr) == INTPIN(ointr))
1341 if (ointr >= nintrs) {
1344 return INTIRQ(ointr);
1358 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1361 * Exactly what this means is unclear at this point. It is a solution
1362 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1363 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1364 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1368 undirect_isa_irq(int rirq)
1372 printf("Freeing redirected ISA irq %d.\n", rirq);
1373 /** FIXME: tickle the MB redirector chip */
1377 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1384 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1387 undirect_pci_irq(int rirq)
1391 printf("Freeing redirected PCI irq %d.\n", rirq);
1393 /** FIXME: tickle the MB redirector chip */
1397 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1405 * given a bus ID, return:
1406 * the bus type if found
1410 apic_bus_type(int id)
1414 for (x = 0; x < mp_nbusses; ++x)
1415 if (bus_data[x].bus_id == id)
1416 return bus_data[x].bus_type;
1423 * given a LOGICAL APIC# and pin#, return:
1424 * the associated src bus ID if found
1428 apic_src_bus_id(int apic, int pin)
1432 /* search each of the possible INTerrupt sources */
1433 for (x = 0; x < nintrs; ++x)
1434 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1435 (pin == io_apic_ints[x].dst_apic_int))
1436 return (io_apic_ints[x].src_bus_id);
1438 return -1; /* NOT found */
1443 * given a LOGICAL APIC# and pin#, return:
1444 * the associated src bus IRQ if found
1448 apic_src_bus_irq(int apic, int pin)
1452 for (x = 0; x < nintrs; x++)
1453 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1454 (pin == io_apic_ints[x].dst_apic_int))
1455 return (io_apic_ints[x].src_bus_irq);
1457 return -1; /* NOT found */
1462 * given a LOGICAL APIC# and pin#, return:
1463 * the associated INTerrupt type if found
1467 apic_int_type(int apic, int pin)
1471 /* search each of the possible INTerrupt sources */
1472 for (x = 0; x < nintrs; ++x)
1473 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1474 (pin == io_apic_ints[x].dst_apic_int))
1475 return (io_apic_ints[x].int_type);
1477 return -1; /* NOT found */
1481 apic_irq(int apic, int pin)
1486 for (x = 0; x < nintrs; ++x)
1487 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1488 (pin == io_apic_ints[x].dst_apic_int)) {
1489 res = io_apic_ints[x].int_vector;
1492 if (apic != int_to_apicintpin[res].ioapic)
1493 panic("apic_irq: inconsistent table");
1494 if (pin != int_to_apicintpin[res].int_pin)
1495 panic("apic_irq inconsistent table (2)");
1503 * given a LOGICAL APIC# and pin#, return:
1504 * the associated trigger mode if found
1508 apic_trigger(int apic, int pin)
1512 /* search each of the possible INTerrupt sources */
1513 for (x = 0; x < nintrs; ++x)
1514 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1515 (pin == io_apic_ints[x].dst_apic_int))
1516 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1518 return -1; /* NOT found */
1523 * given a LOGICAL APIC# and pin#, return:
1524 * the associated 'active' level if found
1528 apic_polarity(int apic, int pin)
1532 /* search each of the possible INTerrupt sources */
1533 for (x = 0; x < nintrs; ++x)
1534 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1535 (pin == io_apic_ints[x].dst_apic_int))
1536 return (io_apic_ints[x].int_flags & 0x03);
1538 return -1; /* NOT found */
1543 * set data according to MP defaults
1544 * FIXME: probably not complete yet...
1547 default_mp_table(int type)
1550 #if defined(APIC_IO)
1554 #endif /* APIC_IO */
1557 printf(" MP default config type: %d\n", type);
1560 printf(" bus: ISA, APIC: 82489DX\n");
1563 printf(" bus: EISA, APIC: 82489DX\n");
1566 printf(" bus: EISA, APIC: 82489DX\n");
1569 printf(" bus: MCA, APIC: 82489DX\n");
1572 printf(" bus: ISA+PCI, APIC: Integrated\n");
1575 printf(" bus: EISA+PCI, APIC: Integrated\n");
1578 printf(" bus: MCA+PCI, APIC: Integrated\n");
1581 printf(" future type\n");
1587 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1588 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1591 CPU_TO_ID(0) = boot_cpu_id;
1592 ID_TO_CPU(boot_cpu_id) = 0;
1594 /* one and only AP */
1595 CPU_TO_ID(1) = ap_cpu_id;
1596 ID_TO_CPU(ap_cpu_id) = 1;
1598 #if defined(APIC_IO)
1599 /* one and only IO APIC */
1600 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1603 * sanity check, refer to MP spec section 3.6.6, last paragraph
1604 * necessary as some hardware isn't properly setting up the IO APIC
1606 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1607 if (io_apic_id != 2) {
1609 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1610 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1611 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
1612 ux &= ~APIC_ID_MASK; /* clear the ID field */
1613 ux |= 0x02000000; /* set it to '2' */
1614 io_apic_write(0, IOAPIC_ID, ux); /* write new value */
1615 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
1616 if ((ux & APIC_ID_MASK) != 0x02000000)
1617 panic("can't control IO APIC ID, reg: 0x%08x", ux);
1620 IO_TO_ID(0) = io_apic_id;
1621 ID_TO_IO(io_apic_id) = 0;
1622 #endif /* APIC_IO */
1624 /* fill out bus entries */
1631 bus_data[0].bus_id = default_data[type - 1][1];
1632 bus_data[0].bus_type = default_data[type - 1][2];
1633 bus_data[1].bus_id = default_data[type - 1][3];
1634 bus_data[1].bus_type = default_data[type - 1][4];
1637 /* case 4: case 7: MCA NOT supported */
1638 default: /* illegal/reserved */
1639 panic("BAD default MP config: %d", type);
1643 #if defined(APIC_IO)
1644 /* general cases from MP v1.4, table 5-2 */
1645 for (pin = 0; pin < 16; ++pin) {
1646 io_apic_ints[pin].int_type = 0;
1647 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1648 io_apic_ints[pin].src_bus_id = 0;
1649 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1650 io_apic_ints[pin].dst_apic_id = io_apic_id;
1651 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1654 /* special cases from MP v1.4, table 5-2 */
1656 io_apic_ints[2].int_type = 0xff; /* N/C */
1657 io_apic_ints[13].int_type = 0xff; /* N/C */
1658 #if !defined(APIC_MIXED_MODE)
1660 panic("sorry, can't support type 2 default yet");
1661 #endif /* APIC_MIXED_MODE */
1664 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1667 io_apic_ints[0].int_type = 0xff; /* N/C */
1669 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1670 #endif /* APIC_IO */
1675 * initialize all the SMP locks
1678 /* critical region around IO APIC, apic_imen */
1679 struct simplelock imen_lock;
1681 /* critical region around splxx(), cpl, cml, cil, ipending */
1682 struct simplelock cpl_lock;
1684 /* Make FAST_INTR() routines sequential */
1685 struct simplelock fast_intr_lock;
1687 /* critical region around INTR() routines */
1688 struct simplelock intr_lock;
1690 /* lock regions protected in UP kernel via cli/sti */
1691 struct simplelock mpintr_lock;
1693 /* lock region used by kernel profiling */
1694 struct simplelock mcount_lock;
1697 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1698 struct simplelock com_lock;
1699 #endif /* USE_COMLOCK */
1701 #ifdef USE_CLOCKLOCK
1702 /* lock regions around the clock hardware */
1703 struct simplelock clock_lock;
1704 #endif /* USE_CLOCKLOCK */
1706 /* lock around the MP rendezvous */
1707 static struct simplelock smp_rv_lock;
1713 * Get the initial mp_lock with a count of 1 for the BSP.
1714 * This uses a LOGICAL cpu ID, ie BSP == 0.
1716 mp_lock = 0x00000001;
1718 /* ISR uses its own "giant lock" */
1719 isr_lock = FREE_LOCK;
1721 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1722 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1725 s_lock_init((struct simplelock*)&mpintr_lock);
1727 s_lock_init((struct simplelock*)&mcount_lock);
1729 s_lock_init((struct simplelock*)&fast_intr_lock);
1730 s_lock_init((struct simplelock*)&intr_lock);
1731 s_lock_init((struct simplelock*)&imen_lock);
1732 s_lock_init((struct simplelock*)&cpl_lock);
1733 s_lock_init(&smp_rv_lock);
1736 s_lock_init((struct simplelock*)&com_lock);
1737 #endif /* USE_COMLOCK */
1738 #ifdef USE_CLOCKLOCK
1739 s_lock_init((struct simplelock*)&clock_lock);
1740 #endif /* USE_CLOCKLOCK */
1744 /* Wait for all APs to be fully initialized */
1745 extern int wait_ap(unsigned int);
1748 * start each AP in our list
1751 start_all_aps(u_int boot_addr)
1754 u_char mpbiosreason;
1755 u_long mpbioswarmvec;
1756 struct globaldata *gd;
1759 POSTCODE(START_ALL_APS_POST);
1761 /* initialize BSP's local APIC */
1765 /* install the AP 1st level boot code */
1766 install_ap_tramp(boot_addr);
1769 /* save the current value of the warm-start vector */
1770 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1772 outb(CMOS_REG, BIOS_RESET);
1773 mpbiosreason = inb(CMOS_DATA);
1776 /* record BSP in CPU map */
1779 /* set up 0 -> 4MB P==V mapping for AP boot */
1780 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
1784 for (x = 1; x <= mp_naps; ++x) {
1786 /* This is a bit verbose, it will go away soon. */
1788 /* first page of AP's private space */
1789 pg = x * i386_btop(sizeof(struct privatespace));
1791 /* allocate a new private data page */
1792 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1794 /* wire it into the private page table page */
1795 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1797 /* allocate and set up an idle stack data page */
1798 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1799 for (i = 0; i < UPAGES; i++)
1800 SMPpt[pg + 5 + i] = (pt_entry_t)
1801 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1803 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */
1804 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */
1805 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */
1806 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */
1808 /* prime data page for it to use */
1810 gd->gd_cpu_lockid = x << 24;
1811 gd->gd_prv_CMAP1 = &SMPpt[pg + 1];
1812 gd->gd_prv_CMAP2 = &SMPpt[pg + 2];
1813 gd->gd_prv_CMAP3 = &SMPpt[pg + 3];
1814 gd->gd_prv_PMAP1 = &SMPpt[pg + 4];
1815 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1;
1816 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2;
1817 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3;
1818 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1;
1820 /* setup a vector to our boot code */
1821 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1822 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1824 outb(CMOS_REG, BIOS_RESET);
1825 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1828 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
1831 /* attempt to start the Application Processor */
1832 CHECK_INIT(99); /* setup checkpoints */
1833 if (!start_ap(x, boot_addr)) {
1834 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1835 CHECK_PRINT("trace"); /* show checkpoints */
1836 /* better panic as the AP may be running loose */
1837 printf("panic y/n? [y] ");
1838 if (cngetc() != 'n')
1841 CHECK_PRINT("trace"); /* show checkpoints */
1843 /* record its version info */
1844 cpu_apic_versions[x] = cpu_apic_versions[0];
1846 all_cpus |= (1 << x); /* record AP in CPU map */
1849 /* build our map of 'other' CPUs */
1850 other_cpus = all_cpus & ~(1 << cpuid);
1852 /* fill in our (BSP) APIC version */
1853 cpu_apic_versions[0] = lapic.version;
1855 /* restore the warmstart vector */
1856 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1858 outb(CMOS_REG, BIOS_RESET);
1859 outb(CMOS_DATA, mpbiosreason);
1863 * Set up the idle context for the BSP. Similar to above except
1864 * that some was done by locore, some by pmap.c and some is implicit
1865 * because the BSP is cpu#0 and the page is initially zero, and also
1866 * because we can refer to variables by name on the BSP..
1869 /* Allocate and setup BSP idle stack */
1870 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
1871 for (i = 0; i < UPAGES; i++)
1872 SMPpt[5 + i] = (pt_entry_t)
1873 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1878 /* number of APs actually started */
1879 return mp_ncpus - 1;
1884 * load the 1st level AP boot code into base memory.
1887 /* targets for relocation */
1888 extern void bigJump(void);
1889 extern void bootCodeSeg(void);
1890 extern void bootDataSeg(void);
1891 extern void MPentry(void);
1892 extern u_int MP_GDT;
1893 extern u_int mp_gdtbase;
1896 install_ap_tramp(u_int boot_addr)
1899 int size = *(int *) ((u_long) & bootMP_size);
1900 u_char *src = (u_char *) ((u_long) bootMP);
1901 u_char *dst = (u_char *) boot_addr + KERNBASE;
1902 u_int boot_base = (u_int) bootMP;
1907 POSTCODE(INSTALL_AP_TRAMP_POST);
1909 for (x = 0; x < size; ++x)
1913 * modify addresses in code we just moved to basemem. unfortunately we
1914 * need fairly detailed info about mpboot.s for this to work. changes
1915 * to mpboot.s might require changes here.
1918 /* boot code is located in KERNEL space */
1919 dst = (u_char *) boot_addr + KERNBASE;
1921 /* modify the lgdt arg */
1922 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1923 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1925 /* modify the ljmp target for MPentry() */
1926 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1927 *dst32 = ((u_int) MPentry - KERNBASE);
1929 /* modify the target for boot code segment */
1930 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1931 dst8 = (u_int8_t *) (dst16 + 1);
1932 *dst16 = (u_int) boot_addr & 0xffff;
1933 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1935 /* modify the target for boot data segment */
1936 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1937 dst8 = (u_int8_t *) (dst16 + 1);
1938 *dst16 = (u_int) boot_addr & 0xffff;
1939 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1944 * this function starts the AP (application processor) identified
1945 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1946 * to accomplish this. This is necessary because of the nuances
1947 * of the different hardware we might encounter. It ain't pretty,
1948 * but it seems to work.
1951 start_ap(int logical_cpu, u_int boot_addr)
1956 u_long icr_lo, icr_hi;
1958 POSTCODE(START_AP_POST);
1960 /* get the PHYSICAL APIC ID# */
1961 physical_cpu = CPU_TO_ID(logical_cpu);
1963 /* calculate the vector */
1964 vector = (boot_addr >> 12) & 0xff;
1966 /* used as a watchpoint to signal AP startup */
1970 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1971 * and running the target CPU. OR this INIT IPI might be latched (P5
1972 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1976 /* setup the address for the target AP */
1977 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1978 icr_hi |= (physical_cpu << 24);
1979 lapic.icr_hi = icr_hi;
1981 /* do an INIT IPI: assert RESET */
1982 icr_lo = lapic.icr_lo & 0xfff00000;
1983 lapic.icr_lo = icr_lo | 0x0000c500;
1985 /* wait for pending status end */
1986 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1989 /* do an INIT IPI: deassert RESET */
1990 lapic.icr_lo = icr_lo | 0x00008500;
1992 /* wait for pending status end */
1993 u_sleep(10000); /* wait ~10mS */
1994 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1998 * next we do a STARTUP IPI: the previous INIT IPI might still be
1999 * latched, (P5 bug) this 1st STARTUP would then terminate
2000 * immediately, and the previously started INIT IPI would continue. OR
2001 * the previous INIT IPI has already run. and this STARTUP IPI will
2002 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2006 /* do a STARTUP IPI */
2007 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2008 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2010 u_sleep(200); /* wait ~200uS */
2013 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2014 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2015 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2016 * recognized after hardware RESET or INIT IPI.
2019 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2020 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2022 u_sleep(200); /* wait ~200uS */
2024 /* wait for it to start */
2025 set_apic_timer(5000000);/* == 5 seconds */
2026 while (read_apic_timer())
2027 if (mp_ncpus > cpus)
2028 return 1; /* return SUCCESS */
2030 return 0; /* return FAILURE */
2035 * Flush the TLB on all other CPU's
2037 * XXX: Needs to handshake and wait for completion before proceding.
2042 #if defined(APIC_IO)
2043 if (smp_started && invltlb_ok)
2044 all_but_self_ipi(XINVLTLB_OFFSET);
2045 #endif /* APIC_IO */
2051 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2053 /* send a message to the other CPUs */
2063 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2066 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2068 /* send a message to the other CPUs */
2074 * When called the executing CPU will send an IPI to all other CPUs
2075 * requesting that they halt execution.
2077 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2079 * - Signals all CPUs in map to stop.
2080 * - Waits for each to stop.
2087 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2088 * from executing at same time.
2091 stop_cpus(u_int map)
2096 /* send the Xcpustop IPI to all CPUs in map */
2097 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2099 while ((stopped_cpus & map) != map)
2107 * Called by a CPU to restart stopped CPUs.
2109 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2111 * - Signals all CPUs in map to restart.
2112 * - Waits for each to restart.
2120 restart_cpus(u_int map)
2125 started_cpus = map; /* signal other cpus to restart */
2127 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2133 int smp_active = 0; /* are the APs allowed to run? */
2134 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2136 /* XXX maybe should be hw.ncpu */
2137 static int smp_cpus = 1; /* how many cpu's running */
2138 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2140 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2141 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2143 /* Warning: Do not staticize. Used from swtch.s */
2144 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2145 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2146 &do_page_zero_idle, 0, "");
2148 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2149 int forward_irq_enabled = 1;
2150 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2151 &forward_irq_enabled, 0, "");
2153 /* Enable forwarding of a signal to a process running on a different CPU */
2154 static int forward_signal_enabled = 1;
2155 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2156 &forward_signal_enabled, 0, "");
2158 /* Enable forwarding of roundrobin to all other cpus */
2159 static int forward_roundrobin_enabled = 1;
2160 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2161 &forward_roundrobin_enabled, 0, "");
2164 * This is called once the rest of the system is up and running and we're
2165 * ready to let the AP's out of the pen.
2174 /* BSP may have changed PTD while we're waiting for the lock */
2179 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2183 /* Build our map of 'other' CPUs. */
2184 other_cpus = all_cpus & ~(1 << cpuid);
2186 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2188 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
2189 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
2191 /* set up FPU state on the AP */
2192 npxinit(__INITIAL_NPXCW__);
2194 /* A quick check from sanity claus */
2195 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2196 if (cpuid != apic_id) {
2197 printf("SMP: cpuid = %d\n", cpuid);
2198 printf("SMP: apic_id = %d\n", apic_id);
2199 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2200 panic("cpuid mismatch! boom!!");
2203 /* Init local apic for irq's */
2206 /* Set memory range attributes for this CPU to match the BSP */
2207 mem_range_AP_init();
2210 * Activate smp_invltlb, although strictly speaking, this isn't
2211 * quite correct yet. We should have a bitfield for cpus willing
2212 * to accept TLB flush IPI's or something and sync them.
2214 if (smp_cpus == mp_ncpus) {
2216 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2217 smp_active = 1; /* historic */
2223 #define CHECKSTATE_USER 0
2224 #define CHECKSTATE_SYS 1
2225 #define CHECKSTATE_INTR 2
2227 /* Do not staticize. Used from apic_vector.s */
2228 struct proc* checkstate_curproc[NCPU];
2229 int checkstate_cpustate[NCPU];
2230 u_long checkstate_pc[NCPU];
2232 extern long cp_time[CPUSTATES];
2234 #define PC_TO_INDEX(pc, prof) \
2235 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2236 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2239 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2245 pc = checkstate_pc[id];
2246 prof = &p->p_stats->p_prof;
2247 if (pc >= prof->pr_off &&
2248 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2249 if ((p->p_flag & P_OWEUPC) == 0) {
2252 p->p_flag |= P_OWEUPC;
2254 *astmap |= (1 << id);
2259 forwarded_statclock(int id, int pscnt, int *astmap)
2261 struct pstats *pstats;
2268 register struct gmonparam *g;
2272 p = checkstate_curproc[id];
2273 cpustate = checkstate_cpustate[id];
2276 case CHECKSTATE_USER:
2277 if (p->p_flag & P_PROFIL)
2278 addupc_intr_forwarded(p, id, astmap);
2282 if (p->p_nice > NZERO)
2287 case CHECKSTATE_SYS:
2290 * Kernel statistics are just like addupc_intr, only easier.
2293 if (g->state == GMON_PROF_ON) {
2294 i = checkstate_pc[id] - g->lowpc;
2295 if (i < g->textsize) {
2296 i /= HISTFRACTION * sizeof(*g->kcount);
2311 case CHECKSTATE_INTR:
2315 * Kernel statistics are just like addupc_intr, only easier.
2318 if (g->state == GMON_PROF_ON) {
2319 i = checkstate_pc[id] - g->lowpc;
2320 if (i < g->textsize) {
2321 i /= HISTFRACTION * sizeof(*g->kcount);
2334 if (++p->p_estcpu == 0)
2336 if ((p->p_estcpu & 3) == 0) {
2338 if (p->p_priority >= PUSER)
2339 p->p_priority = p->p_usrpri;
2342 /* Update resource usage integrals and maximums. */
2343 if ((pstats = p->p_stats) != NULL &&
2344 (ru = &pstats->p_ru) != NULL &&
2345 (vm = p->p_vmspace) != NULL) {
2346 ru->ru_ixrss += pgtok(vm->vm_tsize);
2347 ru->ru_idrss += pgtok(vm->vm_dsize);
2348 ru->ru_isrss += pgtok(vm->vm_ssize);
2349 rss = pgtok(vmspace_resident_count(vm));
2350 if (ru->ru_maxrss < rss)
2351 ru->ru_maxrss = rss;
2357 forward_statclock(int pscnt)
2363 /* Kludge. We don't yet have separate locks for the interrupts
2364 * and the kernel. This means that we cannot let the other processors
2365 * handle complex interrupts while inhibiting them from entering
2366 * the kernel in a non-interrupt context.
2368 * What we can do, without changing the locking mechanisms yet,
2369 * is letting the other processors handle a very simple interrupt
2370 * (wich determines the processor states), and do the main
2374 if (!smp_started || !invltlb_ok || cold || panicstr)
2377 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2379 map = other_cpus & ~stopped_cpus ;
2380 checkstate_probed_cpus = 0;
2382 selected_apic_ipi(map,
2383 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2386 while (checkstate_probed_cpus != map) {
2390 #ifdef BETTER_CLOCK_DIAGNOSTIC
2391 printf("forward_statclock: checkstate %x\n",
2392 checkstate_probed_cpus);
2399 * Step 2: walk through other processors processes, update ticks and
2404 for (id = 0; id < mp_ncpus; id++) {
2407 if (((1 << id) & checkstate_probed_cpus) == 0)
2409 forwarded_statclock(id, pscnt, &map);
2412 checkstate_need_ast |= map;
2413 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2415 while ((checkstate_need_ast & map) != 0) {
2419 #ifdef BETTER_CLOCK_DIAGNOSTIC
2420 printf("forward_statclock: dropped ast 0x%x\n",
2421 checkstate_need_ast & map);
2430 forward_hardclock(int pscnt)
2435 struct pstats *pstats;
2438 /* Kludge. We don't yet have separate locks for the interrupts
2439 * and the kernel. This means that we cannot let the other processors
2440 * handle complex interrupts while inhibiting them from entering
2441 * the kernel in a non-interrupt context.
2443 * What we can do, without changing the locking mechanisms yet,
2444 * is letting the other processors handle a very simple interrupt
2445 * (wich determines the processor states), and do the main
2449 if (!smp_started || !invltlb_ok || cold || panicstr)
2452 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2454 map = other_cpus & ~stopped_cpus ;
2455 checkstate_probed_cpus = 0;
2457 selected_apic_ipi(map,
2458 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2461 while (checkstate_probed_cpus != map) {
2465 #ifdef BETTER_CLOCK_DIAGNOSTIC
2466 printf("forward_hardclock: checkstate %x\n",
2467 checkstate_probed_cpus);
2474 * Step 2: walk through other processors processes, update virtual
2475 * timer and profiling timer. If stathz == 0, also update ticks and
2480 for (id = 0; id < mp_ncpus; id++) {
2483 if (((1 << id) & checkstate_probed_cpus) == 0)
2485 p = checkstate_curproc[id];
2487 pstats = p->p_stats;
2488 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2489 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2490 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2491 psignal(p, SIGVTALRM);
2494 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2495 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2496 psignal(p, SIGPROF);
2501 forwarded_statclock( id, pscnt, &map);
2505 checkstate_need_ast |= map;
2506 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2508 while ((checkstate_need_ast & map) != 0) {
2512 #ifdef BETTER_CLOCK_DIAGNOSTIC
2513 printf("forward_hardclock: dropped ast 0x%x\n",
2514 checkstate_need_ast & map);
2522 #endif /* BETTER_CLOCK */
2525 forward_signal(struct proc *p)
2531 /* Kludge. We don't yet have separate locks for the interrupts
2532 * and the kernel. This means that we cannot let the other processors
2533 * handle complex interrupts while inhibiting them from entering
2534 * the kernel in a non-interrupt context.
2536 * What we can do, without changing the locking mechanisms yet,
2537 * is letting the other processors handle a very simple interrupt
2538 * (wich determines the processor states), and do the main
2542 if (!smp_started || !invltlb_ok || cold || panicstr)
2544 if (!forward_signal_enabled)
2547 if (p->p_stat != SRUN)
2553 checkstate_need_ast |= map;
2554 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2556 while ((checkstate_need_ast & map) != 0) {
2561 printf("forward_signal: dropped ast 0x%x\n",
2562 checkstate_need_ast & map);
2567 if (id == p->p_oncpu)
2573 forward_roundrobin(void)
2578 if (!smp_started || !invltlb_ok || cold || panicstr)
2580 if (!forward_roundrobin_enabled)
2582 resched_cpus |= other_cpus;
2583 map = other_cpus & ~stopped_cpus ;
2585 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2587 (void) all_but_self_ipi(XCPUAST_OFFSET);
2590 while ((checkstate_need_ast & map) != 0) {
2595 printf("forward_roundrobin: dropped ast 0x%x\n",
2596 checkstate_need_ast & map);
2604 #ifdef APIC_INTR_REORDER
2606 * Maintain mapping from softintr vector to isr bit in local apic.
2609 set_lapic_isrloc(int intr, int vector)
2611 if (intr < 0 || intr > 32)
2612 panic("set_apic_isrloc: bad intr argument: %d",intr);
2613 if (vector < ICU_OFFSET || vector > 255)
2614 panic("set_apic_isrloc: bad vector argument: %d",vector);
2615 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2616 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2621 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2622 * (if specified), rendezvous, execute the action function (if specified),
2623 * rendezvous again, execute the teardown function (if specified), and then
2626 * Note that the supplied external functions _must_ be reentrant and aware
2627 * that they are running in parallel and in an unknown lock context.
2629 static void (*smp_rv_setup_func)(void *arg);
2630 static void (*smp_rv_action_func)(void *arg);
2631 static void (*smp_rv_teardown_func)(void *arg);
2632 static void *smp_rv_func_arg;
2633 static volatile int smp_rv_waiters[2];
2636 smp_rendezvous_action(void)
2638 /* setup function */
2639 if (smp_rv_setup_func != NULL)
2640 smp_rv_setup_func(smp_rv_func_arg);
2641 /* spin on entry rendezvous */
2642 atomic_add_int(&smp_rv_waiters[0], 1);
2643 while (smp_rv_waiters[0] < mp_ncpus)
2645 /* action function */
2646 if (smp_rv_action_func != NULL)
2647 smp_rv_action_func(smp_rv_func_arg);
2648 /* spin on exit rendezvous */
2649 atomic_add_int(&smp_rv_waiters[1], 1);
2650 while (smp_rv_waiters[1] < mp_ncpus)
2652 /* teardown function */
2653 if (smp_rv_teardown_func != NULL)
2654 smp_rv_teardown_func(smp_rv_func_arg);
2658 smp_rendezvous(void (* setup_func)(void *),
2659 void (* action_func)(void *),
2660 void (* teardown_func)(void *),
2665 /* obtain rendezvous lock */
2666 s_lock(&smp_rv_lock); /* XXX sleep here? NOWAIT flag? */
2668 /* set static function pointers */
2669 smp_rv_setup_func = setup_func;
2670 smp_rv_action_func = action_func;
2671 smp_rv_teardown_func = teardown_func;
2672 smp_rv_func_arg = arg;
2673 smp_rv_waiters[0] = 0;
2674 smp_rv_waiters[1] = 0;
2676 /* disable interrupts on this CPU, save interrupt status */
2677 efl = read_eflags();
2678 write_eflags(efl & ~PSL_I);
2680 /* signal other processors, which will enter the IPI with interrupts off */
2681 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2683 /* call executor function */
2684 smp_rendezvous_action();
2686 /* restore interrupt flag */
2690 s_unlock(&smp_rv_lock);