2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2002 David E. O'Brien. All rights reserved.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * @(#)param.h 8.1 (Berkeley) 6/10/93
45 #ifndef _AMD64_INCLUDE_PARAM_H_
46 #define _AMD64_INCLUDE_PARAM_H_
48 #include <machine/_align.h>
51 * Machine dependent constants for AMD64.
56 #define __PCI_REROUTE_INTERRUPT
59 #define MACHINE "amd64"
62 #define MACHINE_ARCH "amd64"
64 #ifndef MACHINE_ARCH32
65 #define MACHINE_ARCH32 "i386"
68 #if defined(SMP) || defined(KLD_MODULE)
80 #define ALIGNBYTES _ALIGNBYTES
81 #define ALIGN(p) _ALIGN(p)
83 * ALIGNED_POINTER is a boolean macro that checks whether an address
84 * is valid to fetch data elements of type t from on this architecture.
85 * This does not reflect the optimal alignment, just the possibility
86 * (within reasonable limits).
88 #define ALIGNED_POINTER(p, t) 1
91 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
92 * architecture. It should be used with appropriate caution.
94 #define CACHE_LINE_SHIFT 6
95 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
97 /* Size of the level 1 page table units */
98 #define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
99 #define NPTEPGSHIFT 9 /* LOG2(NPTEPG) */
100 #define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
101 #define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
102 #define PAGE_MASK (PAGE_SIZE-1)
103 /* Size of the level 2 page directory units */
104 #define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
105 #define NPDEPGSHIFT 9 /* LOG2(NPDEPG) */
106 #define PDRSHIFT 21 /* LOG2(NBPDR) */
107 #define NBPDR (1<<PDRSHIFT) /* bytes/page dir */
108 #define PDRMASK (NBPDR-1)
109 /* Size of the level 3 page directory pointer table units */
110 #define NPDPEPG (PAGE_SIZE/(sizeof (pdp_entry_t)))
111 #define NPDPEPGSHIFT 9 /* LOG2(NPDPEPG) */
112 #define PDPSHIFT 30 /* LOG2(NBPDP) */
113 #define NBPDP (1<<PDPSHIFT) /* bytes/page dir ptr table */
114 #define PDPMASK (NBPDP-1)
115 /* Size of the level 4 page-map level-4 table units */
116 #define NPML4EPG (PAGE_SIZE/(sizeof (pml4_entry_t)))
117 #define NPML4EPGSHIFT 9 /* LOG2(NPML4EPG) */
118 #define PML4SHIFT 39 /* LOG2(NBPML4) */
119 #define NBPML4 (1UL<<PML4SHIFT)/* bytes/page map lev4 table */
120 #define PML4MASK (NBPML4-1)
122 #define MAXPAGESIZES 3 /* maximum number of supported page sizes */
124 #define IOPAGES 2 /* pages of i/o permission bitmap */
126 * I/O permission bitmap has a bit for each I/O port plus an additional
127 * byte at the end with all bits set. See section "I/O Permission Bit Map"
128 * in the Intel SDM for more details.
130 #define IOPERM_BITMAP_SIZE (IOPAGES * PAGE_SIZE + 1)
133 #define KSTACK_PAGES 4 /* pages of kstack (with pcb) */
135 #define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
138 * Mach derived conversion macros
140 #define round_page(x) ((((unsigned long)(x)) + PAGE_MASK) & ~(PAGE_MASK))
141 #define trunc_page(x) ((unsigned long)(x) & ~(PAGE_MASK))
142 #define trunc_2mpage(x) ((unsigned long)(x) & ~PDRMASK)
143 #define round_2mpage(x) ((((unsigned long)(x)) + PDRMASK) & ~PDRMASK)
144 #define trunc_1gpage(x) ((unsigned long)(x) & ~PDPMASK)
146 #define atop(x) ((unsigned long)(x) >> PAGE_SHIFT)
147 #define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT)
149 #define amd64_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
150 #define amd64_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
152 #define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024))
154 #define INKERNEL(va) (((va) >= DMAP_MIN_ADDRESS && (va) < DMAP_MAX_ADDRESS) \
155 || ((va) >= VM_MIN_KERNEL_ADDRESS && (va) < VM_MAX_KERNEL_ADDRESS))
158 #define SC_TABLESIZE 1024 /* Must be power of 2. */
161 #endif /* !_AMD64_INCLUDE_PARAM_H_ */