2 * Copyright (c) 2002 David E. O'Brien. All rights reserved.
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
6 * This code is derived from software contributed to Berkeley by
7 * the Systems Programming Group of the University of Utah Computer
8 * Science Department and Ralph Campbell.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * @(#)param.h 8.1 (Berkeley) 6/10/93
43 #ifndef _AMD64_INCLUDE_PARAM_H_
44 #define _AMD64_INCLUDE_PARAM_H_
46 #include <machine/_align.h>
49 * Machine dependent constants for AMD64.
54 #define __PCI_REROUTE_INTERRUPT
57 #define MACHINE "amd64"
60 #define MACHINE_ARCH "amd64"
62 #ifndef MACHINE_ARCH32
63 #define MACHINE_ARCH32 "i386"
66 #if defined(SMP) || defined(KLD_MODULE)
78 #define ALIGNBYTES _ALIGNBYTES
79 #define ALIGN(p) _ALIGN(p)
81 * ALIGNED_POINTER is a boolean macro that checks whether an address
82 * is valid to fetch data elements of type t from on this architecture.
83 * This does not reflect the optimal alignment, just the possibility
84 * (within reasonable limits).
86 #define ALIGNED_POINTER(p, t) 1
89 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
90 * architecture. It should be used with appropriate caution.
92 #define CACHE_LINE_SHIFT 7
93 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
95 /* Size of the level 1 page table units */
96 #define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
97 #define NPTEPGSHIFT 9 /* LOG2(NPTEPG) */
98 #define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
99 #define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
100 #define PAGE_MASK (PAGE_SIZE-1)
101 /* Size of the level 2 page directory units */
102 #define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
103 #define NPDEPGSHIFT 9 /* LOG2(NPDEPG) */
104 #define PDRSHIFT 21 /* LOG2(NBPDR) */
105 #define NBPDR (1<<PDRSHIFT) /* bytes/page dir */
106 #define PDRMASK (NBPDR-1)
107 /* Size of the level 3 page directory pointer table units */
108 #define NPDPEPG (PAGE_SIZE/(sizeof (pdp_entry_t)))
109 #define NPDPEPGSHIFT 9 /* LOG2(NPDPEPG) */
110 #define PDPSHIFT 30 /* LOG2(NBPDP) */
111 #define NBPDP (1<<PDPSHIFT) /* bytes/page dir ptr table */
112 #define PDPMASK (NBPDP-1)
113 /* Size of the level 4 page-map level-4 table units */
114 #define NPML4EPG (PAGE_SIZE/(sizeof (pml4_entry_t)))
115 #define NPML4EPGSHIFT 9 /* LOG2(NPML4EPG) */
116 #define PML4SHIFT 39 /* LOG2(NBPML4) */
117 #define NBPML4 (1UL<<PML4SHIFT)/* bytes/page map lev4 table */
118 #define PML4MASK (NBPML4-1)
120 #define MAXPAGESIZES 3 /* maximum number of supported page sizes */
122 #define IOPAGES 2 /* pages of i/o permission bitmap */
124 * I/O permission bitmap has a bit for each I/O port plus an additional
125 * byte at the end with all bits set. See section "I/O Permission Bit Map"
126 * in the Intel SDM for more details.
128 #define IOPERM_BITMAP_SIZE (IOPAGES * PAGE_SIZE + 1)
131 #define KSTACK_PAGES 4 /* pages of kstack (with pcb) */
133 #define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
136 * Mach derived conversion macros
138 #define round_page(x) ((((unsigned long)(x)) + PAGE_MASK) & ~(PAGE_MASK))
139 #define trunc_page(x) ((unsigned long)(x) & ~(PAGE_MASK))
140 #define trunc_2mpage(x) ((unsigned long)(x) & ~PDRMASK)
141 #define round_2mpage(x) ((((unsigned long)(x)) + PDRMASK) & ~PDRMASK)
142 #define trunc_1gpage(x) ((unsigned long)(x) & ~PDPMASK)
144 #define atop(x) ((unsigned long)(x) >> PAGE_SHIFT)
145 #define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT)
147 #define amd64_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
148 #define amd64_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
150 #define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024))
152 #define INKERNEL(va) (((va) >= DMAP_MIN_ADDRESS && (va) < DMAP_MAX_ADDRESS) \
153 || ((va) >= VM_MIN_KERNEL_ADDRESS && (va) < VM_MAX_KERNEL_ADDRESS))
155 #endif /* !_AMD64_INCLUDE_PARAM_H_ */