2 * Copyright (c) 2003-2008 Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 /* Machine dependent interfaces */
35 #ifndef _MACHINE_PMC_MDEP_H
36 #define _MACHINE_PMC_MDEP_H 1
42 #include <dev/hwpmc/hwpmc_amd.h>
43 #include <dev/hwpmc/hwpmc_core.h>
44 #include <dev/hwpmc/hwpmc_piv.h>
45 #include <dev/hwpmc/hwpmc_tsc.h>
46 #include <dev/hwpmc/hwpmc_uncore.h>
49 * Intel processors implementing V2 and later of the Intel performance
50 * measurement architecture have PMCs of the following classes: TSC,
51 * IAF, IAP, UCF and UCP.
53 #define PMC_MDEP_CLASS_INDEX_TSC 1
54 #define PMC_MDEP_CLASS_INDEX_K8 2
55 #define PMC_MDEP_CLASS_INDEX_F17H 2
56 #define PMC_MDEP_CLASS_INDEX_P4 2
57 #define PMC_MDEP_CLASS_INDEX_IAP 2
58 #define PMC_MDEP_CLASS_INDEX_IAF 3
59 #define PMC_MDEP_CLASS_INDEX_UCP 4
60 #define PMC_MDEP_CLASS_INDEX_UCF 5
63 * On the amd64 platform we support the following PMCs.
65 * TSC The timestamp counter
66 * K8 AMD Athlon64 and Opteron PMCs in 64 bit mode.
67 * PIV Intel P4/HTT and P4/EMT64
68 * IAP Intel Core/Core2/Atom CPUs in 64 bits mode.
69 * IAF Intel fixed-function PMCs in Core2 and later CPUs.
70 * UCP Intel Uncore programmable PMCs.
71 * UCF Intel Uncore fixed-function PMCs.
74 union pmc_md_op_pmcallocate {
75 struct pmc_md_amd_op_pmcallocate pm_amd;
76 struct pmc_md_iaf_op_pmcallocate pm_iaf;
77 struct pmc_md_iap_op_pmcallocate pm_iap;
78 struct pmc_md_ucf_op_pmcallocate pm_ucf;
79 struct pmc_md_ucp_op_pmcallocate pm_ucp;
80 struct pmc_md_p4_op_pmcallocate pm_p4;
85 #define PMCLOG_READADDR PMCLOG_READ64
86 #define PMCLOG_EMITADDR PMCLOG_EMIT64
91 struct pmc_md_amd_pmc pm_amd;
92 struct pmc_md_iaf_pmc pm_iaf;
93 struct pmc_md_iap_pmc pm_iap;
94 struct pmc_md_ucf_pmc pm_ucf;
95 struct pmc_md_ucp_pmc pm_ucp;
96 struct pmc_md_p4_pmc pm_p4;
99 #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_rip)
100 #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_rbp)
101 #define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_rsp)
102 #define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((TF)->tf_rsp)
104 #define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \
105 (((I) & 0xffffffff) == 0xe5894855) /* pushq %rbp; movq %rsp,%rbp */
106 #define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \
107 (((I) & 0x00ffffff) == 0x00e58948) /* movq %rsp,%rbp */
108 #define PMC_AT_FUNCTION_EPILOGUE_RET(I) \
109 (((I) & 0xFF) == 0xC3) /* ret */
111 #define PMC_IN_TRAP_HANDLER(PC) \
112 ((PC) >= (uintptr_t) start_exceptions && \
113 (PC) < (uintptr_t) end_exceptions)
115 #define PMC_IN_KERNEL_STACK(S,START,END) \
116 ((S) >= (START) && (S) < (END))
117 #define PMC_IN_KERNEL(va) INKERNEL(va)
119 #define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
121 /* Build a fake kernel trapframe from current instruction pointer. */
122 #define PMC_FAKE_TRAPFRAME(TF) \
124 (TF)->tf_cs = 0; (TF)->tf_rflags = 0; \
125 __asm __volatile("movq %%rbp,%0" : "=r" ((TF)->tf_rbp)); \
126 __asm __volatile("movq %%rsp,%0" : "=r" ((TF)->tf_rsp)); \
127 __asm __volatile("call 1f \n\t1: pop %0" : "=r"((TF)->tf_rip)); \
134 void start_exceptions(void), end_exceptions(void);
136 struct pmc_mdep *pmc_amd_initialize(void);
137 void pmc_amd_finalize(struct pmc_mdep *_md);
138 struct pmc_mdep *pmc_intel_initialize(void);
139 void pmc_intel_finalize(struct pmc_mdep *_md);
142 #endif /* _MACHINE_PMC_MDEP_H */