2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
56 * Bits in PPro special registers
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 * Bits in AMD64 special registers. EFER is 64 bits wide.
73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
75 #define EFER_LMA 0x000000400 /* Long mode active (R) */
76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
79 * CPUID instruction features register
81 #define CPUID_FPU 0x00000001
82 #define CPUID_VME 0x00000002
83 #define CPUID_DE 0x00000004
84 #define CPUID_PSE 0x00000008
85 #define CPUID_TSC 0x00000010
86 #define CPUID_MSR 0x00000020
87 #define CPUID_PAE 0x00000040
88 #define CPUID_MCE 0x00000080
89 #define CPUID_CX8 0x00000100
90 #define CPUID_APIC 0x00000200
91 #define CPUID_B10 0x00000400
92 #define CPUID_SEP 0x00000800
93 #define CPUID_MTRR 0x00001000
94 #define CPUID_PGE 0x00002000
95 #define CPUID_MCA 0x00004000
96 #define CPUID_CMOV 0x00008000
97 #define CPUID_PAT 0x00010000
98 #define CPUID_PSE36 0x00020000
99 #define CPUID_PSN 0x00040000
100 #define CPUID_CLFSH 0x00080000
101 #define CPUID_B20 0x00100000
102 #define CPUID_DS 0x00200000
103 #define CPUID_ACPI 0x00400000
104 #define CPUID_MMX 0x00800000
105 #define CPUID_FXSR 0x01000000
106 #define CPUID_SSE 0x02000000
107 #define CPUID_XMM 0x02000000
108 #define CPUID_SSE2 0x04000000
109 #define CPUID_SS 0x08000000
110 #define CPUID_HTT 0x10000000
111 #define CPUID_TM 0x20000000
112 #define CPUID_IA64 0x40000000
113 #define CPUID_PBE 0x80000000
115 #define CPUID2_SSE3 0x00000001
116 #define CPUID2_DTES64 0x00000004
117 #define CPUID2_MON 0x00000008
118 #define CPUID2_DS_CPL 0x00000010
119 #define CPUID2_VMX 0x00000020
120 #define CPUID2_SMX 0x00000040
121 #define CPUID2_EST 0x00000080
122 #define CPUID2_TM2 0x00000100
123 #define CPUID2_SSSE3 0x00000200
124 #define CPUID2_CNXTID 0x00000400
125 #define CPUID2_CX16 0x00002000
126 #define CPUID2_XTPR 0x00004000
127 #define CPUID2_PDCM 0x00008000
128 #define CPUID2_DCA 0x00040000
129 #define CPUID2_SSE41 0x00080000
130 #define CPUID2_SSE42 0x00100000
131 #define CPUID2_X2APIC 0x00200000
132 #define CPUID2_POPCNT 0x00800000
135 * Important bits in the AMD extended cpuid flags
137 #define AMDID_SYSCALL 0x00000800
138 #define AMDID_MP 0x00080000
139 #define AMDID_NX 0x00100000
140 #define AMDID_EXT_MMX 0x00400000
141 #define AMDID_FFXSR 0x01000000
142 #define AMDID_PAGE1GB 0x04000000
143 #define AMDID_RDTSCP 0x08000000
144 #define AMDID_LM 0x20000000
145 #define AMDID_EXT_3DNOW 0x40000000
146 #define AMDID_3DNOW 0x80000000
148 #define AMDID2_LAHF 0x00000001
149 #define AMDID2_CMP 0x00000002
150 #define AMDID2_SVM 0x00000004
151 #define AMDID2_EXT_APIC 0x00000008
152 #define AMDID2_CR8 0x00000010
153 #define AMDID2_PREFETCH 0x00000100
156 * CPUID instruction 1 ebx info
158 #define CPUID_BRAND_INDEX 0x000000ff
159 #define CPUID_CLFUSH_SIZE 0x0000ff00
160 #define CPUID_HTT_CORES 0x00ff0000
161 #define CPUID_LOCAL_APIC_ID 0xff000000
164 * AMD extended function 8000_0008h ecx info
166 #define AMDID_CMP_CORES 0x000000ff
169 * CPUID manufacturers identifiers
171 #define INTEL_VENDOR_ID "GenuineIntel"
172 #define AMD_VENDOR_ID "AuthenticAMD"
175 * Model-specific registers for the i386 family
177 #define MSR_P5_MC_ADDR 0x000
178 #define MSR_P5_MC_TYPE 0x001
179 #define MSR_TSC 0x010
180 #define MSR_P5_CESR 0x011
181 #define MSR_P5_CTR0 0x012
182 #define MSR_P5_CTR1 0x013
183 #define MSR_IA32_PLATFORM_ID 0x017
184 #define MSR_APICBASE 0x01b
185 #define MSR_EBL_CR_POWERON 0x02a
186 #define MSR_TEST_CTL 0x033
187 #define MSR_BIOS_UPDT_TRIG 0x079
188 #define MSR_BBL_CR_D0 0x088
189 #define MSR_BBL_CR_D1 0x089
190 #define MSR_BBL_CR_D2 0x08a
191 #define MSR_BIOS_SIGN 0x08b
192 #define MSR_PERFCTR0 0x0c1
193 #define MSR_PERFCTR1 0x0c2
194 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
195 #define MSR_MTRRcap 0x0fe
196 #define MSR_BBL_CR_ADDR 0x116
197 #define MSR_BBL_CR_DECC 0x118
198 #define MSR_BBL_CR_CTL 0x119
199 #define MSR_BBL_CR_TRIG 0x11a
200 #define MSR_BBL_CR_BUSY 0x11b
201 #define MSR_BBL_CR_CTL3 0x11e
202 #define MSR_SYSENTER_CS_MSR 0x174
203 #define MSR_SYSENTER_ESP_MSR 0x175
204 #define MSR_SYSENTER_EIP_MSR 0x176
205 #define MSR_MCG_CAP 0x179
206 #define MSR_MCG_STATUS 0x17a
207 #define MSR_MCG_CTL 0x17b
208 #define MSR_EVNTSEL0 0x186
209 #define MSR_EVNTSEL1 0x187
210 #define MSR_THERM_CONTROL 0x19a
211 #define MSR_THERM_INTERRUPT 0x19b
212 #define MSR_THERM_STATUS 0x19c
213 #define MSR_IA32_MISC_ENABLE 0x1a0
214 #define MSR_DEBUGCTLMSR 0x1d9
215 #define MSR_LASTBRANCHFROMIP 0x1db
216 #define MSR_LASTBRANCHTOIP 0x1dc
217 #define MSR_LASTINTFROMIP 0x1dd
218 #define MSR_LASTINTTOIP 0x1de
219 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
220 #define MSR_MTRRVarBase 0x200
221 #define MSR_MTRR64kBase 0x250
222 #define MSR_MTRR16kBase 0x258
223 #define MSR_MTRR4kBase 0x268
224 #define MSR_PAT 0x277
225 #define MSR_MTRRdefType 0x2ff
226 #define MSR_MC0_CTL 0x400
227 #define MSR_MC0_STATUS 0x401
228 #define MSR_MC0_ADDR 0x402
229 #define MSR_MC0_MISC 0x403
230 #define MSR_MC1_CTL 0x404
231 #define MSR_MC1_STATUS 0x405
232 #define MSR_MC1_ADDR 0x406
233 #define MSR_MC1_MISC 0x407
234 #define MSR_MC2_CTL 0x408
235 #define MSR_MC2_STATUS 0x409
236 #define MSR_MC2_ADDR 0x40a
237 #define MSR_MC2_MISC 0x40b
238 #define MSR_MC3_CTL 0x40c
239 #define MSR_MC3_STATUS 0x40d
240 #define MSR_MC3_ADDR 0x40e
241 #define MSR_MC3_MISC 0x40f
242 #define MSR_MC4_CTL 0x410
243 #define MSR_MC4_STATUS 0x411
244 #define MSR_MC4_ADDR 0x412
245 #define MSR_MC4_MISC 0x413
248 * Constants related to MSR's.
250 #define APICBASE_RESERVED 0x000006ff
251 #define APICBASE_BSP 0x00000100
252 #define APICBASE_ENABLED 0x00000800
253 #define APICBASE_ADDRESS 0xfffff000
258 #define PAT_UNCACHEABLE 0x00
259 #define PAT_WRITE_COMBINING 0x01
260 #define PAT_WRITE_THROUGH 0x04
261 #define PAT_WRITE_PROTECTED 0x05
262 #define PAT_WRITE_BACK 0x06
263 #define PAT_UNCACHED 0x07
264 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
265 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
268 * Constants related to MTRRs
270 #define MTRR_UNCACHEABLE 0x00
271 #define MTRR_WRITE_COMBINING 0x01
272 #define MTRR_WRITE_THROUGH 0x04
273 #define MTRR_WRITE_PROTECTED 0x05
274 #define MTRR_WRITE_BACK 0x06
275 #define MTRR_N64K 8 /* numbers of fixed-size entries */
278 #define MTRR_CAP_WC 0x0000000000000400UL
279 #define MTRR_CAP_FIXED 0x0000000000000100UL
280 #define MTRR_CAP_VCNT 0x00000000000000ffUL
281 #define MTRR_DEF_ENABLE 0x0000000000000800UL
282 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL
283 #define MTRR_DEF_TYPE 0x00000000000000ffUL
284 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL
285 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL
286 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL
287 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL
289 /* Performance Control Register (5x86 only). */
291 #define PCR0_RSTK 0x01 /* Enables return stack */
292 #define PCR0_BTB 0x02 /* Enables branch target buffer */
293 #define PCR0_LOOP 0x04 /* Enables loop */
294 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
296 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
297 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
298 #define PCR0_LSSER 0x80 /* Disable reorder */
300 /* Device Identification Registers */
305 * The following four 3-byte registers control the non-cacheable regions.
306 * These registers must be written as three separate bytes.
308 * NCRx+0: A31-A24 of starting address
309 * NCRx+1: A23-A16 of starting address
310 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
312 * The non-cacheable region's starting address must be aligned to the
313 * size indicated by the NCR_SIZE_xx field.
320 #define NCR_SIZE_0K 0
321 #define NCR_SIZE_4K 1
322 #define NCR_SIZE_8K 2
323 #define NCR_SIZE_16K 3
324 #define NCR_SIZE_32K 4
325 #define NCR_SIZE_64K 5
326 #define NCR_SIZE_128K 6
327 #define NCR_SIZE_256K 7
328 #define NCR_SIZE_512K 8
329 #define NCR_SIZE_1M 9
330 #define NCR_SIZE_2M 10
331 #define NCR_SIZE_4M 11
332 #define NCR_SIZE_8M 12
333 #define NCR_SIZE_16M 13
334 #define NCR_SIZE_32M 14
335 #define NCR_SIZE_4G 15
338 * The address region registers are used to specify the location and
339 * size for the eight address regions.
341 * ARRx + 0: A31-A24 of start address
342 * ARRx + 1: A23-A16 of start address
343 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
354 #define ARR_SIZE_0K 0
355 #define ARR_SIZE_4K 1
356 #define ARR_SIZE_8K 2
357 #define ARR_SIZE_16K 3
358 #define ARR_SIZE_32K 4
359 #define ARR_SIZE_64K 5
360 #define ARR_SIZE_128K 6
361 #define ARR_SIZE_256K 7
362 #define ARR_SIZE_512K 8
363 #define ARR_SIZE_1M 9
364 #define ARR_SIZE_2M 10
365 #define ARR_SIZE_4M 11
366 #define ARR_SIZE_8M 12
367 #define ARR_SIZE_16M 13
368 #define ARR_SIZE_32M 14
369 #define ARR_SIZE_4G 15
372 * The region control registers specify the attributes associated with
373 * the ARRx addres regions.
384 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
385 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
386 #define RCR_WWO 0x02 /* Weak write ordering. */
387 #define RCR_WL 0x04 /* Weak locking. */
388 #define RCR_WG 0x08 /* Write gathering. */
389 #define RCR_WT 0x10 /* Write-through. */
390 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
392 /* AMD Write Allocate Top-Of-Memory and Control Register */
393 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
394 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
395 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
398 #define MSR_EFER 0xc0000080 /* extended features */
399 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
400 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
401 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
402 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
403 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
404 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
405 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
406 #define MSR_PERFEVSEL0 0xc0010000
407 #define MSR_PERFEVSEL1 0xc0010001
408 #define MSR_PERFEVSEL2 0xc0010002
409 #define MSR_PERFEVSEL3 0xc0010003
412 #define MSR_PERFCTR0 0xc0010004
413 #define MSR_PERFCTR1 0xc0010005
414 #define MSR_PERFCTR2 0xc0010006
415 #define MSR_PERFCTR3 0xc0010007
416 #define MSR_SYSCFG 0xc0010010
417 #define MSR_IORRBASE0 0xc0010016
418 #define MSR_IORRMASK0 0xc0010017
419 #define MSR_IORRBASE1 0xc0010018
420 #define MSR_IORRMASK1 0xc0010019
421 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
422 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
423 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
425 #endif /* !_MACHINE_SPECIALREG_H_ */