2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 void vmmdev_init(void);
34 int vmmdev_cleanup(void);
37 struct vm_memory_segment {
38 vm_paddr_t gpa; /* in */
45 int regnum; /* enum vm_reg_name */
49 struct vm_seg_desc { /* data or code segment */
51 int regnum; /* enum vm_reg_name */
57 uint64_t rip; /* start running here */
58 struct vm_exit vm_exit;
78 struct vm_ioapic_irq {
87 struct vm_isa_irq_trigger {
89 enum vm_intr_trigger trigger;
92 struct vm_capability {
94 enum vm_cap_type captype;
105 struct vm_pptdev_mmio {
114 struct vm_pptdev_msi {
119 int numvec; /* 0 means disabled */
124 struct vm_pptdev_msix {
131 uint32_t vector_control;
139 #define MAX_VM_STATS 64
142 int num_entries; /* out */
144 uint64_t statbuf[MAX_VM_STATS];
147 struct vm_stat_desc {
149 char desc[128]; /* out */
154 enum x2apic_state state;
158 uint64_t gpa; /* in */
159 uint64_t pte[4]; /* out */
164 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
168 enum vm_suspend_how how;
172 int vcpuid; /* inputs */
173 int prot; /* PROT_READ or PROT_WRITE */
175 struct vm_guest_paging paging;
176 int fault; /* outputs */
180 struct vm_activate_cpu {
189 #define VM_ACTIVE_CPUS 0
190 #define VM_SUSPENDED_CPUS 1
208 /* general routines */
211 IOCNUM_SET_CAPABILITY = 2,
212 IOCNUM_GET_CAPABILITY = 3,
217 IOCNUM_MAP_MEMORY = 10,
218 IOCNUM_GET_MEMORY_SEG = 11,
219 IOCNUM_GET_GPA_PMAP = 12,
222 /* register/state accessors */
223 IOCNUM_SET_REGISTER = 20,
224 IOCNUM_GET_REGISTER = 21,
225 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
226 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
228 /* interrupt injection */
229 IOCNUM_GET_INTINFO = 28,
230 IOCNUM_SET_INTINFO = 29,
231 IOCNUM_INJECT_EXCEPTION = 30,
232 IOCNUM_LAPIC_IRQ = 31,
233 IOCNUM_INJECT_NMI = 32,
234 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
235 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
236 IOCNUM_IOAPIC_PULSE_IRQ = 35,
237 IOCNUM_LAPIC_MSI = 36,
238 IOCNUM_LAPIC_LOCAL_IRQ = 37,
239 IOCNUM_IOAPIC_PINCOUNT = 38,
242 IOCNUM_BIND_PPTDEV = 40,
243 IOCNUM_UNBIND_PPTDEV = 41,
244 IOCNUM_MAP_PPTDEV_MMIO = 42,
245 IOCNUM_PPTDEV_MSI = 43,
246 IOCNUM_PPTDEV_MSIX = 44,
249 IOCNUM_VM_STATS = 50,
250 IOCNUM_VM_STAT_DESC = 51,
252 /* kernel device state */
253 IOCNUM_SET_X2APIC_STATE = 60,
254 IOCNUM_GET_X2APIC_STATE = 61,
255 IOCNUM_GET_HPET_CAPABILITIES = 62,
257 /* legacy interrupt injection */
258 IOCNUM_ISA_ASSERT_IRQ = 80,
259 IOCNUM_ISA_DEASSERT_IRQ = 81,
260 IOCNUM_ISA_PULSE_IRQ = 82,
261 IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
264 IOCNUM_ACTIVATE_CPU = 90,
265 IOCNUM_GET_CPUSET = 91,
268 IOCNUM_RTC_READ = 100,
269 IOCNUM_RTC_WRITE = 101,
270 IOCNUM_RTC_SETTIME = 102,
271 IOCNUM_RTC_GETTIME = 103,
275 _IOWR('v', IOCNUM_RUN, struct vm_run)
277 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
279 _IO('v', IOCNUM_REINIT)
280 #define VM_MAP_MEMORY \
281 _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
282 #define VM_GET_MEMORY_SEG \
283 _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
284 #define VM_SET_REGISTER \
285 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
286 #define VM_GET_REGISTER \
287 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
288 #define VM_SET_SEGMENT_DESCRIPTOR \
289 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
290 #define VM_GET_SEGMENT_DESCRIPTOR \
291 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
292 #define VM_INJECT_EXCEPTION \
293 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
294 #define VM_LAPIC_IRQ \
295 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
296 #define VM_LAPIC_LOCAL_IRQ \
297 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
298 #define VM_LAPIC_MSI \
299 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
300 #define VM_IOAPIC_ASSERT_IRQ \
301 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
302 #define VM_IOAPIC_DEASSERT_IRQ \
303 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
304 #define VM_IOAPIC_PULSE_IRQ \
305 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
306 #define VM_IOAPIC_PINCOUNT \
307 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
308 #define VM_ISA_ASSERT_IRQ \
309 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
310 #define VM_ISA_DEASSERT_IRQ \
311 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
312 #define VM_ISA_PULSE_IRQ \
313 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
314 #define VM_ISA_SET_IRQ_TRIGGER \
315 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
316 #define VM_SET_CAPABILITY \
317 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
318 #define VM_GET_CAPABILITY \
319 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
320 #define VM_BIND_PPTDEV \
321 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
322 #define VM_UNBIND_PPTDEV \
323 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
324 #define VM_MAP_PPTDEV_MMIO \
325 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
326 #define VM_PPTDEV_MSI \
327 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
328 #define VM_PPTDEV_MSIX \
329 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
330 #define VM_INJECT_NMI \
331 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
333 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
334 #define VM_STAT_DESC \
335 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
336 #define VM_SET_X2APIC_STATE \
337 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
338 #define VM_GET_X2APIC_STATE \
339 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
340 #define VM_GET_HPET_CAPABILITIES \
341 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
342 #define VM_GET_GPA_PMAP \
343 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
345 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
346 #define VM_ACTIVATE_CPU \
347 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu)
348 #define VM_GET_CPUS \
349 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset)
350 #define VM_SET_INTINFO \
351 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo)
352 #define VM_GET_INTINFO \
353 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo)
354 #define VM_RTC_WRITE \
355 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data)
356 #define VM_RTC_READ \
357 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data)
358 #define VM_RTC_SETTIME \
359 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time)
360 #define VM_RTC_GETTIME \
361 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time)