2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 void vmmdev_init(void);
36 int vmmdev_cleanup(void);
41 int segid; /* memory segment */
42 vm_ooffset_t segoff; /* offset into memory segment */
43 size_t len; /* mmap length */
47 #define VM_MEMMAP_F_WIRED 0x01
48 #define VM_MEMMAP_F_IOMMU 0x02
50 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL)
54 char name[SPECNAMELEN + 1];
59 int regnum; /* enum vm_reg_name */
63 struct vm_seg_desc { /* data or code segment */
65 int regnum; /* enum vm_reg_name */
69 struct vm_register_set {
72 const int *regnums; /* enum vm_reg_name */
78 struct vm_exit vm_exit;
86 int restart_instruction;
99 struct vm_ioapic_irq {
108 struct vm_isa_irq_trigger {
110 enum vm_intr_trigger trigger;
113 struct vm_capability {
115 enum vm_cap_type captype;
126 struct vm_pptdev_mmio {
135 struct vm_pptdev_msi {
140 int numvec; /* 0 means disabled */
145 struct vm_pptdev_msix {
152 uint32_t vector_control;
160 #define MAX_VM_STATS 64
163 int num_entries; /* out */
165 uint64_t statbuf[MAX_VM_STATS];
168 struct vm_stat_desc {
170 char desc[128]; /* out */
175 enum x2apic_state state;
179 uint64_t gpa; /* in */
180 uint64_t pte[4]; /* out */
185 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
189 enum vm_suspend_how how;
193 int vcpuid; /* inputs */
194 int prot; /* PROT_READ or PROT_WRITE */
196 struct vm_guest_paging paging;
197 int fault; /* outputs */
201 struct vm_activate_cpu {
210 #define VM_ACTIVE_CPUS 0
211 #define VM_SUSPENDED_CPUS 1
229 /* general routines */
232 IOCNUM_SET_CAPABILITY = 2,
233 IOCNUM_GET_CAPABILITY = 3,
238 IOCNUM_MAP_MEMORY = 10, /* deprecated */
239 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */
240 IOCNUM_GET_GPA_PMAP = 12,
242 IOCNUM_ALLOC_MEMSEG = 14,
243 IOCNUM_GET_MEMSEG = 15,
244 IOCNUM_MMAP_MEMSEG = 16,
245 IOCNUM_MMAP_GETNEXT = 17,
247 /* register/state accessors */
248 IOCNUM_SET_REGISTER = 20,
249 IOCNUM_GET_REGISTER = 21,
250 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
251 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
252 IOCNUM_SET_REGISTER_SET = 24,
253 IOCNUM_GET_REGISTER_SET = 25,
255 /* interrupt injection */
256 IOCNUM_GET_INTINFO = 28,
257 IOCNUM_SET_INTINFO = 29,
258 IOCNUM_INJECT_EXCEPTION = 30,
259 IOCNUM_LAPIC_IRQ = 31,
260 IOCNUM_INJECT_NMI = 32,
261 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
262 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
263 IOCNUM_IOAPIC_PULSE_IRQ = 35,
264 IOCNUM_LAPIC_MSI = 36,
265 IOCNUM_LAPIC_LOCAL_IRQ = 37,
266 IOCNUM_IOAPIC_PINCOUNT = 38,
267 IOCNUM_RESTART_INSTRUCTION = 39,
270 IOCNUM_BIND_PPTDEV = 40,
271 IOCNUM_UNBIND_PPTDEV = 41,
272 IOCNUM_MAP_PPTDEV_MMIO = 42,
273 IOCNUM_PPTDEV_MSI = 43,
274 IOCNUM_PPTDEV_MSIX = 44,
277 IOCNUM_VM_STATS = 50,
278 IOCNUM_VM_STAT_DESC = 51,
280 /* kernel device state */
281 IOCNUM_SET_X2APIC_STATE = 60,
282 IOCNUM_GET_X2APIC_STATE = 61,
283 IOCNUM_GET_HPET_CAPABILITIES = 62,
285 /* legacy interrupt injection */
286 IOCNUM_ISA_ASSERT_IRQ = 80,
287 IOCNUM_ISA_DEASSERT_IRQ = 81,
288 IOCNUM_ISA_PULSE_IRQ = 82,
289 IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
292 IOCNUM_ACTIVATE_CPU = 90,
293 IOCNUM_GET_CPUSET = 91,
296 IOCNUM_RTC_READ = 100,
297 IOCNUM_RTC_WRITE = 101,
298 IOCNUM_RTC_SETTIME = 102,
299 IOCNUM_RTC_GETTIME = 103,
303 _IOWR('v', IOCNUM_RUN, struct vm_run)
305 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
307 _IO('v', IOCNUM_REINIT)
308 #define VM_ALLOC_MEMSEG \
309 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg)
310 #define VM_GET_MEMSEG \
311 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg)
312 #define VM_MMAP_MEMSEG \
313 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap)
314 #define VM_MMAP_GETNEXT \
315 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap)
316 #define VM_SET_REGISTER \
317 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
318 #define VM_GET_REGISTER \
319 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
320 #define VM_SET_SEGMENT_DESCRIPTOR \
321 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
322 #define VM_GET_SEGMENT_DESCRIPTOR \
323 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
324 #define VM_SET_REGISTER_SET \
325 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set)
326 #define VM_GET_REGISTER_SET \
327 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set)
328 #define VM_INJECT_EXCEPTION \
329 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
330 #define VM_LAPIC_IRQ \
331 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
332 #define VM_LAPIC_LOCAL_IRQ \
333 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
334 #define VM_LAPIC_MSI \
335 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
336 #define VM_IOAPIC_ASSERT_IRQ \
337 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
338 #define VM_IOAPIC_DEASSERT_IRQ \
339 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
340 #define VM_IOAPIC_PULSE_IRQ \
341 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
342 #define VM_IOAPIC_PINCOUNT \
343 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
344 #define VM_ISA_ASSERT_IRQ \
345 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
346 #define VM_ISA_DEASSERT_IRQ \
347 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
348 #define VM_ISA_PULSE_IRQ \
349 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
350 #define VM_ISA_SET_IRQ_TRIGGER \
351 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
352 #define VM_SET_CAPABILITY \
353 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
354 #define VM_GET_CAPABILITY \
355 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
356 #define VM_BIND_PPTDEV \
357 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
358 #define VM_UNBIND_PPTDEV \
359 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
360 #define VM_MAP_PPTDEV_MMIO \
361 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
362 #define VM_PPTDEV_MSI \
363 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
364 #define VM_PPTDEV_MSIX \
365 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
366 #define VM_INJECT_NMI \
367 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
369 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
370 #define VM_STAT_DESC \
371 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
372 #define VM_SET_X2APIC_STATE \
373 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
374 #define VM_GET_X2APIC_STATE \
375 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
376 #define VM_GET_HPET_CAPABILITIES \
377 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
378 #define VM_GET_GPA_PMAP \
379 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
381 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
382 #define VM_ACTIVATE_CPU \
383 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu)
384 #define VM_GET_CPUS \
385 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset)
386 #define VM_SET_INTINFO \
387 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo)
388 #define VM_GET_INTINFO \
389 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo)
390 #define VM_RTC_WRITE \
391 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data)
392 #define VM_RTC_READ \
393 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data)
394 #define VM_RTC_SETTIME \
395 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time)
396 #define VM_RTC_GETTIME \
397 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time)
398 #define VM_RESTART_INSTRUCTION \
399 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int)