2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 void vmmdev_init(void);
36 int vmmdev_cleanup(void);
41 int segid; /* memory segment */
42 vm_ooffset_t segoff; /* offset into memory segment */
43 size_t len; /* mmap length */
47 #define VM_MEMMAP_F_WIRED 0x01
48 #define VM_MEMMAP_F_IOMMU 0x02
50 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL)
54 char name[SPECNAMELEN + 1];
59 int regnum; /* enum vm_reg_name */
63 struct vm_seg_desc { /* data or code segment */
65 int regnum; /* enum vm_reg_name */
69 struct vm_register_set {
72 const int *regnums; /* enum vm_reg_name */
78 struct vm_exit vm_exit;
86 int restart_instruction;
99 struct vm_ioapic_irq {
108 struct vm_isa_irq_trigger {
110 enum vm_intr_trigger trigger;
113 struct vm_capability {
115 enum vm_cap_type captype;
126 struct vm_pptdev_mmio {
135 struct vm_pptdev_msi {
140 int numvec; /* 0 means disabled */
145 struct vm_pptdev_msix {
152 uint32_t vector_control;
160 #define MAX_VM_STATS 64
163 int num_entries; /* out */
165 uint64_t statbuf[MAX_VM_STATS];
168 struct vm_stat_desc {
170 char desc[128]; /* out */
175 enum x2apic_state state;
179 uint64_t gpa; /* in */
180 uint64_t pte[4]; /* out */
185 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
189 enum vm_suspend_how how;
193 int vcpuid; /* inputs */
194 int prot; /* PROT_READ or PROT_WRITE */
196 struct vm_guest_paging paging;
197 int fault; /* outputs */
201 struct vm_activate_cpu {
210 #define VM_ACTIVE_CPUS 0
211 #define VM_SUSPENDED_CPUS 1
212 #define VM_DEBUG_CPUS 2
229 struct vm_cpu_topology {
237 /* general routines */
240 IOCNUM_SET_CAPABILITY = 2,
241 IOCNUM_GET_CAPABILITY = 3,
246 IOCNUM_MAP_MEMORY = 10, /* deprecated */
247 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */
248 IOCNUM_GET_GPA_PMAP = 12,
250 IOCNUM_ALLOC_MEMSEG = 14,
251 IOCNUM_GET_MEMSEG = 15,
252 IOCNUM_MMAP_MEMSEG = 16,
253 IOCNUM_MMAP_GETNEXT = 17,
254 IOCNUM_GLA2GPA_NOFAULT = 18,
256 /* register/state accessors */
257 IOCNUM_SET_REGISTER = 20,
258 IOCNUM_GET_REGISTER = 21,
259 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
260 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
261 IOCNUM_SET_REGISTER_SET = 24,
262 IOCNUM_GET_REGISTER_SET = 25,
264 /* interrupt injection */
265 IOCNUM_GET_INTINFO = 28,
266 IOCNUM_SET_INTINFO = 29,
267 IOCNUM_INJECT_EXCEPTION = 30,
268 IOCNUM_LAPIC_IRQ = 31,
269 IOCNUM_INJECT_NMI = 32,
270 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
271 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
272 IOCNUM_IOAPIC_PULSE_IRQ = 35,
273 IOCNUM_LAPIC_MSI = 36,
274 IOCNUM_LAPIC_LOCAL_IRQ = 37,
275 IOCNUM_IOAPIC_PINCOUNT = 38,
276 IOCNUM_RESTART_INSTRUCTION = 39,
279 IOCNUM_BIND_PPTDEV = 40,
280 IOCNUM_UNBIND_PPTDEV = 41,
281 IOCNUM_MAP_PPTDEV_MMIO = 42,
282 IOCNUM_PPTDEV_MSI = 43,
283 IOCNUM_PPTDEV_MSIX = 44,
286 IOCNUM_VM_STATS = 50,
287 IOCNUM_VM_STAT_DESC = 51,
289 /* kernel device state */
290 IOCNUM_SET_X2APIC_STATE = 60,
291 IOCNUM_GET_X2APIC_STATE = 61,
292 IOCNUM_GET_HPET_CAPABILITIES = 62,
295 IOCNUM_SET_TOPOLOGY = 63,
296 IOCNUM_GET_TOPOLOGY = 64,
298 /* legacy interrupt injection */
299 IOCNUM_ISA_ASSERT_IRQ = 80,
300 IOCNUM_ISA_DEASSERT_IRQ = 81,
301 IOCNUM_ISA_PULSE_IRQ = 82,
302 IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
305 IOCNUM_ACTIVATE_CPU = 90,
306 IOCNUM_GET_CPUSET = 91,
307 IOCNUM_SUSPEND_CPU = 92,
308 IOCNUM_RESUME_CPU = 93,
311 IOCNUM_RTC_READ = 100,
312 IOCNUM_RTC_WRITE = 101,
313 IOCNUM_RTC_SETTIME = 102,
314 IOCNUM_RTC_GETTIME = 103,
318 _IOWR('v', IOCNUM_RUN, struct vm_run)
320 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
322 _IO('v', IOCNUM_REINIT)
323 #define VM_ALLOC_MEMSEG \
324 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg)
325 #define VM_GET_MEMSEG \
326 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg)
327 #define VM_MMAP_MEMSEG \
328 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap)
329 #define VM_MMAP_GETNEXT \
330 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap)
331 #define VM_SET_REGISTER \
332 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
333 #define VM_GET_REGISTER \
334 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
335 #define VM_SET_SEGMENT_DESCRIPTOR \
336 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
337 #define VM_GET_SEGMENT_DESCRIPTOR \
338 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
339 #define VM_SET_REGISTER_SET \
340 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set)
341 #define VM_GET_REGISTER_SET \
342 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set)
343 #define VM_INJECT_EXCEPTION \
344 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
345 #define VM_LAPIC_IRQ \
346 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
347 #define VM_LAPIC_LOCAL_IRQ \
348 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
349 #define VM_LAPIC_MSI \
350 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
351 #define VM_IOAPIC_ASSERT_IRQ \
352 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
353 #define VM_IOAPIC_DEASSERT_IRQ \
354 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
355 #define VM_IOAPIC_PULSE_IRQ \
356 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
357 #define VM_IOAPIC_PINCOUNT \
358 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
359 #define VM_ISA_ASSERT_IRQ \
360 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
361 #define VM_ISA_DEASSERT_IRQ \
362 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
363 #define VM_ISA_PULSE_IRQ \
364 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
365 #define VM_ISA_SET_IRQ_TRIGGER \
366 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
367 #define VM_SET_CAPABILITY \
368 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
369 #define VM_GET_CAPABILITY \
370 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
371 #define VM_BIND_PPTDEV \
372 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
373 #define VM_UNBIND_PPTDEV \
374 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
375 #define VM_MAP_PPTDEV_MMIO \
376 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
377 #define VM_PPTDEV_MSI \
378 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
379 #define VM_PPTDEV_MSIX \
380 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
381 #define VM_INJECT_NMI \
382 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
384 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
385 #define VM_STAT_DESC \
386 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
387 #define VM_SET_X2APIC_STATE \
388 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
389 #define VM_GET_X2APIC_STATE \
390 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
391 #define VM_GET_HPET_CAPABILITIES \
392 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
393 #define VM_SET_TOPOLOGY \
394 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology)
395 #define VM_GET_TOPOLOGY \
396 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology)
397 #define VM_GET_GPA_PMAP \
398 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
400 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
401 #define VM_GLA2GPA_NOFAULT \
402 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa)
403 #define VM_ACTIVATE_CPU \
404 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu)
405 #define VM_GET_CPUS \
406 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset)
407 #define VM_SUSPEND_CPU \
408 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu)
409 #define VM_RESUME_CPU \
410 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu)
411 #define VM_SET_INTINFO \
412 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo)
413 #define VM_GET_INTINFO \
414 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo)
415 #define VM_RTC_WRITE \
416 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data)
417 #define VM_RTC_READ \
418 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data)
419 #define VM_RTC_SETTIME \
420 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time)
421 #define VM_RTC_GETTIME \
422 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time)
423 #define VM_RESTART_INSTRUCTION \
424 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int)