2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
40 #include "opt_auto_eoi.h"
44 #include <sys/param.h>
47 #include <machine/lock.h>
50 #include <sys/systm.h>
51 #include <sys/syslog.h>
52 #include <sys/kernel.h>
53 #include <sys/kthread.h>
54 #include <sys/malloc.h>
55 #include <sys/module.h>
56 #include <sys/unistd.h>
57 #include <sys/errno.h>
58 #include <sys/interrupt.h>
59 #include <machine/ipl.h>
60 #include <machine/md_var.h>
61 #include <machine/segments.h>
65 #include <machine/smp.h>
66 #include <machine/smptests.h> /** FAST_HI */
67 #include <machine/resource.h>
70 #include <pc98/pc98/pc98.h>
71 #include <pc98/pc98/pc98_machdep.h>
72 #include <pc98/pc98/epsonio.h>
74 #include <i386/isa/isa.h>
76 #include <i386/isa/icu.h>
79 #include <isa/isavar.h>
81 #include <i386/isa/intr_machdep.h>
82 #include <sys/interrupt.h>
84 #include <machine/clock.h>
89 #include <i386/isa/mca_machdep.h>
95 u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
96 driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
97 struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
98 void *intr_unit[ICU_LEN];
100 static inthand_t *fastintr[ICU_LEN] = {
101 &IDTVEC(fastintr0), &IDTVEC(fastintr1),
102 &IDTVEC(fastintr2), &IDTVEC(fastintr3),
103 &IDTVEC(fastintr4), &IDTVEC(fastintr5),
104 &IDTVEC(fastintr6), &IDTVEC(fastintr7),
105 &IDTVEC(fastintr8), &IDTVEC(fastintr9),
106 &IDTVEC(fastintr10), &IDTVEC(fastintr11),
107 &IDTVEC(fastintr12), &IDTVEC(fastintr13),
108 &IDTVEC(fastintr14), &IDTVEC(fastintr15),
110 &IDTVEC(fastintr16), &IDTVEC(fastintr17),
111 &IDTVEC(fastintr18), &IDTVEC(fastintr19),
112 &IDTVEC(fastintr20), &IDTVEC(fastintr21),
113 &IDTVEC(fastintr22), &IDTVEC(fastintr23),
117 static inthand_t *slowintr[ICU_LEN] = {
118 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
119 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
120 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
121 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
123 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
124 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
128 static driver_intr_t isa_strayintr;
131 #define NMI_PARITY 0x04
132 #define NMI_EPARITY 0x02
134 #define NMI_PARITY (1 << 7)
135 #define NMI_IOCHAN (1 << 6)
136 #define ENMI_WATCHDOG (1 << 7)
137 #define ENMI_BUSTIMER (1 << 6)
138 #define ENMI_IOSTATUS (1 << 5)
142 * Bus attachment for the ISA PIC.
144 static struct isa_pnp_id atpic_ids[] = {
145 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
150 atpic_probe(device_t dev)
154 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
160 * In the APIC_IO case we might be granted IRQ 2, as this is typically
161 * consumed by chaining between the two PIC components. If we're using
162 * the APIC, however, this may not be the case, and as such we should
163 * free the resource. (XXX untested)
165 * The generic ISA attachment code will handle allocating any other resources
166 * that we don't explicitly claim here.
169 atpic_attach(device_t dev)
173 struct resource *res;
175 /* try to allocate our IRQ and then free it */
177 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
179 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
184 static device_method_t atpic_methods[] = {
185 /* Device interface */
186 DEVMETHOD(device_probe, atpic_probe),
187 DEVMETHOD(device_attach, atpic_attach),
188 DEVMETHOD(device_detach, bus_generic_detach),
189 DEVMETHOD(device_shutdown, bus_generic_shutdown),
190 DEVMETHOD(device_suspend, bus_generic_suspend),
191 DEVMETHOD(device_resume, bus_generic_resume),
195 static driver_t atpic_driver = {
201 static devclass_t atpic_devclass;
203 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
206 * Handle a NMI, possibly a machine check.
207 * return true to panic system, false to ignore.
215 int port = inb(0x33);
217 log(LOG_CRIT, "NMI PC98 port = %x\n", port);
218 if (epson_machine_id == 0x20)
219 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
220 if (port & NMI_PARITY) {
221 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
223 } else if (port & NMI_EPARITY) {
224 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
227 log(LOG_CRIT, "\nNMI Resume ??\n");
230 int isa_port = inb(0x61);
231 int eisa_port = inb(0x461);
233 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
235 if (MCA_system && mca_bus_nmi())
239 if (isa_port & NMI_PARITY) {
240 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
244 if (isa_port & NMI_IOCHAN) {
245 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
250 * On a real EISA machine, this will never happen. However it can
251 * happen on ISA machines which implement XT style floating point
252 * error handling (very rare). Save them from a meaningless panic.
254 if (eisa_port == 0xff)
257 if (eisa_port & ENMI_WATCHDOG) {
258 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
262 if (eisa_port & ENMI_BUSTIMER) {
263 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
267 if (eisa_port & ENMI_IOSTATUS) {
268 log(LOG_CRIT, "EISA I/O port status error.");
276 * Create a default interrupt table to avoid problems caused by
277 * spurious interrupts during configuration of kernel, then setup
278 * interrupt control unit.
286 for (i = 0; i < ICU_LEN; i++)
287 icu_unset(i, (driver_intr_t *)NULL);
289 /* initialize 8259's */
292 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
295 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
297 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
298 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
301 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
303 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
307 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
309 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
312 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
313 outb(IO_ICU1, 0x0a); /* default to IRR on read */
315 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
320 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
323 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
325 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
326 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
328 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
331 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
333 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
336 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
337 outb(IO_ICU2, 0x0a); /* default to IRR on read */
341 * Caught a stray interrupt, notify
344 isa_strayintr(vcookiep)
347 int intr = (void **)vcookiep - &intr_unit[0];
350 * XXX TODO print a different message for #7 if it is for a
351 * glitch. Glitches can be distinguished from real #7's by
352 * testing that the in-service bit is _not_ set. The test
353 * must be done before sending an EOI so it can't be done if
354 * we are using AUTO_EOI_1.
356 if (intrcnt[1 + intr] <= 5)
357 log(LOG_ERR, "stray irq %d\n", intr);
358 if (intrcnt[1 + intr] == 5)
360 "too many stray irq %d's; not logging any more\n", intr);
365 * Return a bitmap of the current interrupt requests. This is 8259-specific
366 * and is only suitable for use at probe time.
376 return ((irr2 << 8) | irr1);
381 * Update intrnames array with the specified name. This is used by
382 * vmstat(8) and the like.
385 update_intrname(int intr, char *name)
389 int name_index, off, strayintr;
392 * Initialise strings for bitbucket and stray interrupt counters.
393 * These have statically allocated indices 0 and 1 through ICU_LEN.
395 if (intrnames[0] == '\0') {
396 off = sprintf(intrnames, "???") + 1;
397 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
398 off += sprintf(intrnames + off, "stray irq%d",
404 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
408 * Search for `buf' in `intrnames'. In the usual case when it is
409 * not found, append it to the end if there is enough space (the \0
410 * terminator for the previous string, if any, becomes a separator).
412 for (cp = intrnames, name_index = 0;
413 cp != eintrnames && name_index < NR_INTRNAMES;
414 cp += strlen(cp) + 1, name_index++) {
416 if (strlen(buf) >= eintrnames - cp)
421 if (strcmp(cp, buf) == 0)
426 printf("update_intrname: counting %s irq%d as %s\n", name, intr,
430 intr_countp[intr] = &intrcnt[name_index];
434 icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
437 int select; /* the select register is 8 bits */
439 u_int32_t value; /* the window register is 32 bits */
444 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
446 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
448 if (intr_handler[intr] != isa_strayintr)
453 intr_handler[intr] = handler;
454 intr_unit[intr] = arg;
456 if (flags & INTR_FAST) {
457 vector = TPR_FAST_INTS + intr;
458 setidt(vector, fastintr[intr],
459 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
462 vector = TPR_SLOW_INTS + intr;
463 #ifdef APIC_INTR_REORDER
464 #ifdef APIC_INTR_HIGHPRI_CLOCK
465 /* XXX: Hack (kludge?) for more accurate clock. */
466 if (intr == apic_8254_intr || intr == 8) {
467 vector = TPR_FAST_INTS + intr;
471 setidt(vector, slowintr[intr],
472 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
474 #ifdef APIC_INTR_REORDER
475 set_lapic_isrloc(intr, vector);
478 * Reprogram the vector in the IO APIC.
480 if (int_to_apicintpin[intr].ioapic >= 0) {
481 select = int_to_apicintpin[intr].redirindex;
482 value = io_apic_read(int_to_apicintpin[intr].ioapic,
483 select) & ~IOART_INTVEC;
484 io_apic_write(int_to_apicintpin[intr].ioapic,
485 select, value | vector);
488 setidt(ICU_OFFSET + intr,
489 flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
490 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
498 * Dissociate an interrupt handler from an IRQ and set the handler to
499 * the stray interrupt handler. The 'handler' parameter is used only
500 * for consistency checking.
503 icu_unset(intr, handler)
505 driver_intr_t *handler;
509 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
515 intr_countp[intr] = &intrcnt[1 + intr];
516 intr_handler[intr] = isa_strayintr;
517 intr_unit[intr] = &intr_unit[intr];
519 /* XXX how do I re-create dvp here? */
520 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
521 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
523 #ifdef APIC_INTR_REORDER
524 set_lapic_isrloc(intr, ICU_OFFSET + intr);
526 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
527 GSEL(GCODE_SEL, SEL_KPL));
534 inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
537 struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */
538 struct intrec *head; /* chain of handlers for IRQ */
539 struct intrec *idesc; /* descriptor for this handler */
540 struct proc *p; /* interrupt thread */
543 if (name == NULL) /* no name? */
544 panic ("anonymous interrupt");
545 if (ithd == NULL || ithd->it_ih == NULL) {
546 /* first handler for this irq. */
548 ithd = malloc(sizeof (struct ithd), M_DEVBUF, M_WAITOK);
551 bzero(ithd, sizeof(struct ithd));
556 * If we have a fast interrupt, we need to set the
557 * handler address directly. Do that below. For a
558 * slow interrupt, we don't need to know more details,
559 * so do it here because it's tidier.
561 if ((flags & INTR_FAST) == 0) {
563 * Only create a kernel thread if we don't already
566 if (ithd->it_proc == NULL) {
567 errcode = kthread_create(ithd_loop, NULL, &p,
568 RFSTOPPED | RFHIGHPID, "irq%d: %s", irq,
571 panic("inthand_add: Can't create "
573 p->p_rtprio.type = RTP_PRIO_ITHREAD;
574 p->p_stat = SWAIT; /* we're idle */
576 /* Put in linkages. */
580 snprintf(ithd->it_proc->p_comm, MAXCOMLEN,
581 "irq%d: %s", irq, name);
582 p->p_rtprio.prio = pri;
585 * The interrupt process must be in place, but
586 * not necessarily schedulable, before we
587 * initialize the ICU, since it may cause an
588 * immediate interrupt.
590 if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
591 panic("inthand_add: Can't initialize ICU");
593 } else if ((flags & INTR_EXCL) != 0
594 || (ithd->it_ih->flags & INTR_EXCL) != 0) {
596 * We can't append the new handler if either
597 * list ithd or new handler do not allow
598 * interrupts to be shared.
601 printf("\tdevice combination %s and %s "
602 "doesn't support shared irq%d\n",
603 ithd->it_ih->name, name, irq);
605 } else if (flags & INTR_FAST) {
606 /* We can only have one fast interrupt by itself. */
608 printf("\tCan't add fast interrupt %s"
609 " to normal interrupt %s on irq%d",
610 name, ithd->it_ih->name, irq);
612 } else { /* update p_comm */
614 if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) {
615 strcat(p->p_comm, " ");
616 strcat(p->p_comm, name);
617 } else if (strlen(p->p_comm) == MAXCOMLEN)
618 p->p_comm[MAXCOMLEN - 1] = '+';
620 strcat(p->p_comm, "+");
622 idesc = malloc(sizeof (struct intrec), M_DEVBUF, M_WAITOK);
625 bzero(idesc, sizeof (struct intrec));
627 idesc->handler = handler;
628 idesc->argument = arg;
629 idesc->flags = flags;
632 idesc->name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK);
633 if (idesc->name == NULL) {
634 free(idesc, M_DEVBUF);
637 strcpy(idesc->name, name);
639 /* Slow interrupts got set up above. */
640 if ((flags & INTR_FAST)
641 && (icu_setup(irq, idesc->handler, idesc->argument,
642 idesc->flags) != 0) ) {
644 printf("\tinthand_add(irq%d) failed, result=%d\n",
646 free(idesc->name, M_DEVBUF);
647 free(idesc, M_DEVBUF);
650 head = ithd->it_ih; /* look at chain of handlers */
652 while (head->next != NULL)
653 head = head->next; /* find the end */
654 head->next = idesc; /* hook it in there */
656 ithd->it_ih = idesc; /* put it up front */
657 update_intrname(irq, idesc->name);
662 * Deactivate and remove linked list the interrupt handler descriptor
663 * data connected created by an earlier call of inthand_add(), then
664 * adjust the interrupt masks if necessary.
666 * Return the memory held by the interrupt handler descriptor data
667 * structure to the system. First ensure the handler is not actively
672 inthand_remove(struct intrec *idesc)
674 struct ithd *ithd; /* descriptor for the IRQ */
675 struct intrec *ih; /* chain of handlers */
682 if (ih == idesc) /* first in the chain */
683 ithd->it_ih = idesc->next; /* unhook it */
686 && (ih->next != idesc) )
688 if (ih->next != idesc)
690 ih->next = ih->next->next;
693 if (ithd->it_ih == NULL) /* no handlers left, */
694 icu_unset(ithd->irq, idesc->handler);
695 free(idesc, M_DEVBUF);