2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000, BSDi
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/mutex.h>
40 #include <sys/sysctl.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
45 #include <machine/pci_cfgreg.h>
47 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
49 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
50 unsigned reg, unsigned bytes);
51 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
52 unsigned reg, int data, unsigned bytes);
53 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
54 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
59 * For amd64 we assume that type 1 I/O port-based access always works.
60 * If an ACPI MCFG table exists, pcie_cfgregopen() will be called to
61 * switch to memory-mapped access.
63 int cfgmech = CFGMECH_1;
65 static vm_offset_t pcie_base;
66 static int pcie_minbus, pcie_maxbus;
67 static uint32_t pcie_badslots;
68 static struct mtx pcicfg_mtx;
69 MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
70 static int mcfg_enable = 1;
71 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
72 "Enable support for PCI-e memory mapped config access");
82 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
85 if (cfgmech == CFGMECH_PCIE &&
86 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
87 (bus != 0 || !(1 << slot & pcie_badslots)))
88 return (pciereg_cfgread(bus, slot, func, reg, bytes));
90 return (pcireg_cfgread(bus, slot, func, reg, bytes));
94 * Read configuration space register
97 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
102 * Some BIOS writers seem to want to ignore the spec and put
103 * 0 in the intline rather than 255 to indicate none. Some use
104 * numbers in the range 128-254 to indicate something strange and
105 * apparently undocumented anywhere. Assume these are completely bogus
106 * and map them to 255, which the rest of the PCI code recognizes as
109 if (reg == PCIR_INTLINE && bytes == 1) {
110 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
111 if (line == 0 || line >= 128)
112 line = PCI_INVALID_IRQ;
115 return (pci_docfgregread(bus, slot, func, reg, bytes));
119 * Write configuration space register
122 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
125 if (cfgmech == CFGMECH_PCIE &&
126 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
127 (bus != 0 || !(1 << slot & pcie_badslots)))
128 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
130 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
134 * Configuration space access using direct register operations
137 /* enable configuration space accesses and return data port address */
139 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
143 if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
144 (unsigned)reg <= PCI_REGMAX && bytes != 3 &&
145 (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
146 outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11)
147 | (func << 8) | (reg & ~0x03));
148 dataport = CONF1_DATA_PORT + (reg & 0x03);
153 /* disable configuration space accesses */
159 * Do nothing. Writing a 0 to the address port can apparently
160 * confuse some bridges and cause spurious access failures.
165 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
170 mtx_lock_spin(&pcicfg_mtx);
171 port = pci_cfgenable(bus, slot, func, reg, bytes);
186 mtx_unlock_spin(&pcicfg_mtx);
191 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
195 mtx_lock_spin(&pcicfg_mtx);
196 port = pci_cfgenable(bus, slot, func, reg, bytes);
211 mtx_unlock_spin(&pcicfg_mtx);
215 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
227 printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
230 /* XXX: We should make sure this really fits into the direct map. */
231 pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20);
232 pcie_minbus = minbus;
233 pcie_maxbus = maxbus;
234 cfgmech = CFGMECH_PCIE;
237 * On some AMD systems, some of the devices on bus 0 are
238 * inaccessible using memory-mapped PCI config access. Walk
239 * bus 0 looking for such devices. For these devices, we will
240 * fall back to using type 1 config access instead.
242 if (pci_cfgregopen() != 0) {
243 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
244 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
245 if (val1 == 0xffffffff)
248 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
250 pcie_badslots |= (1 << slot);
257 #define PCIE_VADDR(base, reg, bus, slot, func) \
259 ((((bus) & 0xff) << 20) | \
260 (((slot) & 0x1f) << 15) | \
261 (((func) & 0x7) << 12) | \
265 * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
266 * have a requirement that all accesses to the memory mapped PCI configuration
267 * space are done using AX class of registers.
268 * Since other vendors do not currently have any contradicting requirements
269 * the AMD access pattern is applied universally.
273 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
279 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
280 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
283 va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
287 __asm("movl %1, %0" : "=a" (data)
288 : "m" (*(volatile uint32_t *)va));
291 __asm("movzwl %1, %0" : "=a" (data)
292 : "m" (*(volatile uint16_t *)va));
295 __asm("movzbl %1, %0" : "=a" (data)
296 : "m" (*(volatile uint8_t *)va));
304 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
309 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
310 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
313 va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
317 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
321 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
322 : "a" ((uint16_t)data));
325 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
326 : "a" ((uint8_t)data));