2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/param.h> /* XXX trim includes */
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
40 #include <machine/md_var.h>
41 #include <pci/pcivar.h>
42 #include <pci/pcireg.h>
43 #include <isa/isavar.h>
44 #include <machine/nexusvar.h>
45 #include <machine/pci_cfgreg.h>
46 #include <machine/segments.h>
47 #include <machine/pc/bios.h>
50 #include <machine/smp.h>
59 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
60 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
61 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
62 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
64 static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
65 static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
66 static int pcibios_cfgopen(void);
67 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
68 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
69 static int pcireg_cfgopen(void);
71 static struct PIR_table *pci_route_table;
72 static int pci_route_count;
75 * Initialise access to PCI configuration space
80 static int opened = 0;
82 static struct PIR_table *pt;
89 if (pcibios_cfgopen() != 0) {
91 } else if (pcireg_cfgopen() != 0) {
98 * Look for the interrupt routing table.
100 /* XXX use PCI BIOS if it's available */
102 if ((pt == NULL) && ((sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0)) != 0)) {
103 pt = (struct PIR_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
104 for (cv = (u_int8_t *)pt, ck = 0, i = 0; i < (pt->pt_header.ph_length); i++) {
108 pci_route_table = pt;
109 pci_route_count = (pt->pt_header.ph_length - sizeof(struct PIR_header)) / sizeof(struct PIR_entry);
110 printf("Using $PIR table, %d entries at %p\n", pci_route_count, pci_route_table);
119 * Read configuration space register
122 pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
125 pcibios_cfgread(bus, slot, func, reg, bytes) :
126 pcireg_cfgread(bus, slot, func, reg, bytes));
130 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
134 * If we are using the APIC, the contents of the intline register will probably
135 * be wrong (since they are set up for use with the PIC.
136 * Rather than rewrite these registers (maybe that would be smarter) we trap
137 * attempts to read them and translate to our private vector numbers.
139 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
142 pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
143 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
148 airq = pci_apic_irq(bus, slot, pin);
150 /* PCI specific entry found in MP table */
152 undirect_pci_irq(line);
156 * PCI interrupts might be redirected to the
157 * ISA bus according to some MP tables. Use the
158 * same methods as used by the ISA devices
159 * devices to find the proper IOAPIC int pin.
161 airq = isa_apic_irq(line);
162 if ((airq >= 0) && (airq != line)) {
163 /* XXX: undirect_pci_irq() ? */
164 undirect_isa_irq(line);
172 return(pci_do_cfgregread(bus, slot, func, reg, bytes));
176 * Write configuration space register
179 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
182 pcibios_cfgwrite(bus, slot, func, reg, data, bytes) :
183 pcireg_cfgwrite(bus, slot, func, reg, data, bytes));
187 * Route a PCI interrupt
189 * XXX we don't do anything "right" with the function number in the PIR table
190 * (because the consumer isn't currently passing it in). We don't care
191 * anyway, due to the way PCI interrupts are assigned.
194 pci_cfgintr(int bus, int device, int pin)
196 struct PIR_entry *pe;
198 struct bios_regs args;
200 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
201 (pin < 1) || (pin > 4))
205 * Scan the entry table for a contender
207 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, pe++) {
208 if ((bus != pe->pe_bus) || (device != pe->pe_device))
211 irq = pci_cfgintr_unique(pe, pin);
213 irq = pci_cfgintr_linked(pe, pin);
215 irq = pci_cfgintr_virgin(pe, pin);
222 * Ask the BIOS to route the interrupt
224 args.eax = PCIBIOS_ROUTE_INTERRUPT;
225 args.ebx = (bus << 8) | (device << 3);
226 args.ecx = (irq << 8) | (0xa + pin - 1); /* pin value is 0xa - 0xd */
227 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
230 * XXX if it fails, we should try to smack the router hardware directly
233 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n",
234 bus, device, 'A' + pin - 1, irq);
238 printf("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, device, 'A' + pin - 1);
243 * Look to see if the routing table claims this pin is uniquely routed.
246 pci_cfgintr_unique(struct PIR_entry *pe, int pin)
250 if (powerof2(pe->pe_intpin[pin - 1].irqs)) {
251 irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
252 printf("pci_cfgintr_unique: hard-routed to irq %d\n", irq);
259 * Look for another device which shares the same link byte and
260 * already has a unique IRQ, or which has had one routed already.
263 pci_cfgintr_linked(struct PIR_entry *pe, int pin)
265 struct PIR_entry *oe;
266 struct PIR_intpin *pi;
272 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, oe++) {
274 /* scan interrupt pins */
275 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
277 /* don't look at the entry we're trying to match with */
278 if ((pe == oe) && (i == (pin - 1)))
281 /* compare link bytes */
282 if (pi->link != pe->pe_intpin[pin - 1].link)
285 /* link destination mapped to a unique interrupt? */
286 if (powerof2(pi->irqs)) {
287 irq = ffs(pi->irqs) - 1;
288 printf("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
293 /* look for the real PCI device that matches this table entry */
294 if ((irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, j, pin)) != 255)
302 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
303 * see if it has already been assigned an interrupt.
306 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
308 devclass_t pci_devclass;
309 device_t *pci_devices;
311 device_t *pci_children;
313 device_t *busp, *childp;
317 * Find all the PCI busses.
320 if ((pci_devclass = devclass_find("pci")) != NULL)
321 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
324 * Scan all the PCI busses/devices looking for this one.
326 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
328 device_get_children(*busp, &pci_children, &pci_childcount);
330 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
331 if ((pci_get_bus(*childp) == bus) &&
332 (pci_get_slot(*childp) == device) &&
333 (pci_get_intpin(*childp) == matchpin) &&
334 ((irq = pci_get_irq(*childp)) != 255)) {
335 printf("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
336 irq, pe->pe_intpin[pin - 1].link,
337 pci_get_bus(*childp), pci_get_slot(*childp), pci_get_function(*childp));
346 * Pick a suitable IRQ from those listed as routable to this device.
349 pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
353 /* first scan the set of PCI-only interrupts and see if any of these are routable */
354 for (irq = 0; irq < 16; irq++) {
357 /* can we use this interrupt? */
358 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
359 (pe->pe_intpin[pin - 1].irqs & ibit)) {
360 printf("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq);
365 /* life is tough, so just pick an interrupt */
366 for (irq = 0; irq < 16; irq++) {
369 if (pe->pe_intpin[pin - 1].irqs & ibit) {
370 printf("pci_cfgintr_virgin: using routable interrupt %d\n", irq);
379 * Config space access using BIOS functions
382 pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
384 struct bios_regs args;
389 args.eax = PCIBIOS_READ_CONFIG_BYTE;
393 args.eax = PCIBIOS_READ_CONFIG_WORD;
397 args.eax = PCIBIOS_READ_CONFIG_DWORD;
403 args.ebx = (bus << 8) | (slot << 3) | func;
405 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
406 /* check call results? */
407 return(args.ecx & mask);
411 pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
413 struct bios_regs args;
417 args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
420 args.eax = PCIBIOS_WRITE_CONFIG_WORD;
423 args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
428 args.ebx = (bus << 8) | (slot << 3) | func;
431 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
435 * Determine whether there is a PCI BIOS present
438 pcibios_cfgopen(void)
440 /* check for a found entrypoint */
441 return(PCIbios.entry != 0);
445 * Configuration space access using direct register operations
448 /* enable configuration space accesses and return data port address */
450 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
454 if (bus <= PCI_BUSMAX
456 && func <= PCI_FUNCMAX
459 && (unsigned) bytes <= 4
460 && (reg & (bytes -1)) == 0) {
463 outl(CONF1_ADDR_PORT, (1 << 31)
464 | (bus << 16) | (slot << 11)
465 | (func << 8) | (reg & ~0x03));
466 dataport = CONF1_DATA_PORT + (reg & 0x03);
469 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
470 outb(CONF2_FORWARD_PORT, bus);
471 dataport = 0xc000 | (slot << 8) | reg;
478 /* disable configuration space accesses */
484 outl(CONF1_ADDR_PORT, 0);
487 outb(CONF2_ENABLE_PORT, 0);
488 outb(CONF2_FORWARD_PORT, 0);
494 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
499 port = pci_cfgenable(bus, slot, func, reg, bytes);
519 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
523 port = pci_cfgenable(bus, slot, func, reg, bytes);
540 /* check whether the configuration mechanism has been correctly identified */
542 pci_cfgcheck(int maxdev)
547 printf("pci_cfgcheck:\tdevice ");
549 for (device = 0; device < maxdev; device++) {
550 unsigned id, class, header;
552 printf("%d ", device);
554 id = inl(pci_cfgenable(0, device, 0, 0, 4));
555 if (id == 0 || id == -1)
558 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
560 printf("[class=%06x] ", class);
561 if (class == 0 || (class & 0xf870ff) != 0)
564 header = inb(pci_cfgenable(0, device, 0, 14, 1));
566 printf("[hdr=%02x] ", header);
567 if ((header & 0x7e) != 0)
571 printf("is there (id=%08x)\n", id);
577 printf("-- nothing found\n");
586 unsigned long mode1res,oldval1;
587 unsigned char mode2res,oldval2;
589 oldval1 = inl(CONF1_ADDR_PORT);
592 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
596 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
601 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
602 outb(CONF1_ADDR_PORT +3, 0);
603 mode1res = inl(CONF1_ADDR_PORT);
604 outl(CONF1_ADDR_PORT, oldval1);
607 printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
608 mode1res, CONF1_ENABLE_CHK);
611 if (pci_cfgcheck(32))
615 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
616 mode1res = inl(CONF1_ADDR_PORT);
617 outl(CONF1_ADDR_PORT, oldval1);
620 printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
621 mode1res, CONF1_ENABLE_CHK1);
623 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
624 if (pci_cfgcheck(32))
629 oldval2 = inb(CONF2_ENABLE_PORT);
632 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
636 if ((oldval2 & 0xf0) == 0) {
641 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
642 mode2res = inb(CONF2_ENABLE_PORT);
643 outb(CONF2_ENABLE_PORT, oldval2);
646 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
647 mode2res, CONF2_ENABLE_CHK);
649 if (mode2res == CONF2_ENABLE_RES) {
651 printf("pci_open(2a):\tnow trying mechanism 2\n");
653 if (pci_cfgcheck(16))