2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/param.h> /* XXX trim includes */
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
40 #include <machine/md_var.h>
41 #include <pci/pcivar.h>
42 #include <pci/pcireg.h>
43 #include <isa/isavar.h>
44 #include <machine/nexusvar.h>
45 #include <machine/pci_cfgreg.h>
46 #include <machine/segments.h>
47 #include <machine/pc/bios.h>
55 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
56 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
57 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
58 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
60 static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
61 static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
62 static int pcibios_cfgopen(void);
63 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
64 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
65 static int pcireg_cfgopen(void);
67 static struct PIR_table *pci_route_table;
68 static int pci_route_count;
71 * Initialise access to PCI configuration space
76 static int opened = 0;
78 static struct PIR_table *pt;
85 if (pcibios_cfgopen() != 0) {
87 } else if (pcireg_cfgopen() != 0) {
94 * Look for the interrupt routing table.
96 /* XXX use PCI BIOS if it's available */
98 if ((pt == NULL) && ((sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0)) != 0)) {
99 pt = (struct PIR_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
100 for (cv = (u_int8_t *)pt, ck = 0, i = 0; i < (pt->pt_header.ph_length); i++) {
104 pci_route_table = pt;
105 pci_route_count = (pt->pt_header.ph_length - sizeof(struct PIR_header)) / sizeof(struct PIR_entry);
106 printf("Using $PIR table, %d entries at %p\n", pci_route_count, pci_route_table);
115 * Read configuration space register
118 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
121 pcibios_cfgread(bus, slot, func, reg, bytes) :
122 pcireg_cfgread(bus, slot, func, reg, bytes));
126 * Write configuration space register
129 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
132 pcibios_cfgwrite(bus, slot, func, reg, data, bytes) :
133 pcireg_cfgwrite(bus, slot, func, reg, data, bytes));
137 * Route a PCI interrupt
139 * XXX we don't do anything "right" with the function number in the PIR table
140 * (because the consumer isn't currently passing it in). We don't care
141 * anyway, due to the way PCI interrupts are assigned.
144 pci_cfgintr(int bus, int device, int pin)
146 struct PIR_entry *pe;
148 struct bios_regs args;
150 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
151 (pin < 1) || (pin > 4))
155 * Scan the entry table for a contender
157 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, pe++) {
158 if ((bus != pe->pe_bus) || (device != pe->pe_device))
161 irq = pci_cfgintr_unique(pe, pin);
163 irq = pci_cfgintr_linked(pe, pin);
165 irq = pci_cfgintr_virgin(pe, pin);
172 * Ask the BIOS to route the interrupt
174 args.eax = PCIBIOS_ROUTE_INTERRUPT;
175 args.ebx = (bus << 8) | (device << 3);
176 args.ecx = (irq << 8) | (0xa + pin - 1); /* pin value is 0xa - 0xd */
177 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
180 * XXX if it fails, we should try to smack the router hardware directly
183 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n",
184 bus, device, 'A' + pin - 1, irq);
188 printf("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, device, 'A' + pin - 1);
193 * Look to see if the routing table claims this pin is uniquely routed.
196 pci_cfgintr_unique(struct PIR_entry *pe, int pin)
200 if (powerof2(pe->pe_intpin[pin - 1].irqs)) {
201 irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
202 printf("pci_cfgintr_unique: hard-routed to irq %d\n", irq);
209 * Look for another device which shares the same link byte and
210 * already has a unique IRQ, or which has had one routed already.
213 pci_cfgintr_linked(struct PIR_entry *pe, int pin)
215 struct PIR_entry *oe;
216 struct PIR_intpin *pi;
222 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, oe++) {
224 /* scan interrupt pins */
225 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
227 /* don't look at the entry we're trying to match with */
228 if ((pe == oe) && (i == (pin - 1)))
231 /* compare link bytes */
232 if (pi->link != pe->pe_intpin[pin - 1].link)
235 /* link destination mapped to a unique interrupt? */
236 if (powerof2(pi->irqs)) {
237 irq = ffs(pi->irqs) - 1;
238 printf("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
243 /* look for the real PCI device that matches this table entry */
244 if ((irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, j, pin)) != 255)
252 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
253 * see if it has already been assigned an interrupt.
256 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
258 devclass_t pci_devclass;
259 device_t *pci_devices;
261 device_t *pci_children;
263 device_t *busp, *childp;
267 * Find all the PCI busses.
270 if ((pci_devclass = devclass_find("pci")) != NULL)
271 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
274 * Scan all the PCI busses/devices looking for this one.
276 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
278 device_get_children(*busp, &pci_children, &pci_childcount);
280 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
281 if ((pci_get_bus(*childp) == bus) &&
282 (pci_get_slot(*childp) == device) &&
283 (pci_get_intpin(*childp) == matchpin) &&
284 ((irq = pci_get_irq(*childp)) != 255)) {
285 printf("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
286 irq, pe->pe_intpin[pin - 1].link,
287 pci_get_bus(*childp), pci_get_slot(*childp), pci_get_function(*childp));
296 * Pick a suitable IRQ from those listed as routable to this device.
299 pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
303 /* first scan the set of PCI-only interrupts and see if any of these are routable */
304 for (irq = 0; irq < 16; irq++) {
307 /* can we use this interrupt? */
308 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
309 (pe->pe_intpin[pin - 1].irqs & ibit)) {
310 printf("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq);
315 /* life is tough, so just pick an interrupt */
316 for (irq = 0; irq < 16; irq++) {
319 if (pe->pe_intpin[pin - 1].irqs & ibit) {
320 printf("pci_cfgintr_virgin: using routable interrupt %d\n", irq);
329 * Config space access using BIOS functions
332 pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
334 struct bios_regs args;
339 args.eax = PCIBIOS_READ_CONFIG_BYTE;
343 args.eax = PCIBIOS_READ_CONFIG_WORD;
347 args.eax = PCIBIOS_READ_CONFIG_DWORD;
353 args.ebx = (bus << 8) | (slot << 3) | func;
355 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
356 /* check call results? */
357 return(args.ecx & mask);
361 pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
363 struct bios_regs args;
367 args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
370 args.eax = PCIBIOS_WRITE_CONFIG_WORD;
373 args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
378 args.ebx = (bus << 8) | (slot << 3) | func;
381 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
385 * Determine whether there is a PCI BIOS present
388 pcibios_cfgopen(void)
390 /* check for a found entrypoint */
391 return(PCIbios.entry != 0);
395 * Configuration space access using direct register operations
398 /* enable configuration space accesses and return data port address */
400 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
404 if (bus <= PCI_BUSMAX
406 && func <= PCI_FUNCMAX
409 && (unsigned) bytes <= 4
410 && (reg & (bytes -1)) == 0) {
413 outl(CONF1_ADDR_PORT, (1 << 31)
414 | (bus << 16) | (slot << 11)
415 | (func << 8) | (reg & ~0x03));
416 dataport = CONF1_DATA_PORT + (reg & 0x03);
419 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
420 outb(CONF2_FORWARD_PORT, bus);
421 dataport = 0xc000 | (slot << 8) | reg;
428 /* disable configuration space accesses */
434 outl(CONF1_ADDR_PORT, 0);
437 outb(CONF2_ENABLE_PORT, 0);
438 outb(CONF2_FORWARD_PORT, 0);
444 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
449 port = pci_cfgenable(bus, slot, func, reg, bytes);
469 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
473 port = pci_cfgenable(bus, slot, func, reg, bytes);
490 /* check whether the configuration mechanism has been correctly identified */
492 pci_cfgcheck(int maxdev)
497 printf("pci_cfgcheck:\tdevice ");
499 for (device = 0; device < maxdev; device++) {
500 unsigned id, class, header;
502 printf("%d ", device);
504 id = inl(pci_cfgenable(0, device, 0, 0, 4));
505 if (id == 0 || id == -1)
508 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
510 printf("[class=%06x] ", class);
511 if (class == 0 || (class & 0xf870ff) != 0)
514 header = inb(pci_cfgenable(0, device, 0, 14, 1));
516 printf("[hdr=%02x] ", header);
517 if ((header & 0x7e) != 0)
521 printf("is there (id=%08x)\n", id);
527 printf("-- nothing found\n");
536 unsigned long mode1res,oldval1;
537 unsigned char mode2res,oldval2;
539 oldval1 = inl(CONF1_ADDR_PORT);
542 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
546 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
551 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
552 outb(CONF1_ADDR_PORT +3, 0);
553 mode1res = inl(CONF1_ADDR_PORT);
554 outl(CONF1_ADDR_PORT, oldval1);
557 printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
558 mode1res, CONF1_ENABLE_CHK);
561 if (pci_cfgcheck(32))
565 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
566 mode1res = inl(CONF1_ADDR_PORT);
567 outl(CONF1_ADDR_PORT, oldval1);
570 printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
571 mode1res, CONF1_ENABLE_CHK1);
573 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
574 if (pci_cfgcheck(32))
579 oldval2 = inb(CONF2_ENABLE_PORT);
582 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
586 if ((oldval2 & 0xf0) == 0) {
591 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
592 mode2res = inb(CONF2_ENABLE_PORT);
593 outb(CONF2_ENABLE_PORT, oldval2);
596 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
597 mode2res, CONF2_ENABLE_CHK);
599 if (mode2res == CONF2_ENABLE_RES) {
601 printf("pci_open(2a):\tnow trying mechanism 2\n");
603 if (pci_cfgcheck(16))