2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013, Anish Gupta (akgupt3@gmail.com)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
39 #include <sys/sysctl.h>
44 #include <machine/cpufunc.h>
45 #include <machine/psl.h>
46 #include <machine/md_var.h>
47 #include <machine/reg.h>
48 #include <machine/specialreg.h>
49 #include <machine/smp.h>
50 #include <machine/vmm.h>
51 #include <machine/vmm_dev.h>
52 #include <machine/vmm_instruction_emul.h>
54 #include "vmm_lapic.h"
57 #include "vmm_ioport.h"
60 #include "vlapic_priv.h"
65 #include "svm_softc.h"
70 SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW, NULL, NULL);
73 * SVM CPUID function 0x8000_000A, edx bit decoding.
75 #define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */
76 #define AMD_CPUID_SVM_LBR BIT(1) /* Last branch virtualization */
77 #define AMD_CPUID_SVM_SVML BIT(2) /* SVM lock */
78 #define AMD_CPUID_SVM_NRIP_SAVE BIT(3) /* Next RIP is saved */
79 #define AMD_CPUID_SVM_TSC_RATE BIT(4) /* TSC rate control. */
80 #define AMD_CPUID_SVM_VMCB_CLEAN BIT(5) /* VMCB state caching */
81 #define AMD_CPUID_SVM_FLUSH_BY_ASID BIT(6) /* Flush by ASID */
82 #define AMD_CPUID_SVM_DECODE_ASSIST BIT(7) /* Decode assist */
83 #define AMD_CPUID_SVM_PAUSE_INC BIT(10) /* Pause intercept filter. */
84 #define AMD_CPUID_SVM_PAUSE_FTH BIT(12) /* Pause filter threshold */
85 #define AMD_CPUID_SVM_AVIC BIT(13) /* AVIC present */
87 #define VMCB_CACHE_DEFAULT (VMCB_CACHE_ASID | \
98 static uint32_t vmcb_clean = VMCB_CACHE_DEFAULT;
99 SYSCTL_INT(_hw_vmm_svm, OID_AUTO, vmcb_clean, CTLFLAG_RDTUN, &vmcb_clean,
102 static MALLOC_DEFINE(M_SVM, "svm", "svm");
103 static MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic");
105 static uint32_t svm_feature = ~0U; /* AMD SVM features. */
106 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RDTUN, &svm_feature, 0,
107 "SVM features advertised by CPUID.8000000AH:EDX");
109 static int disable_npf_assist;
110 SYSCTL_INT(_hw_vmm_svm, OID_AUTO, disable_npf_assist, CTLFLAG_RWTUN,
111 &disable_npf_assist, 0, NULL);
113 /* Maximum ASIDs supported by the processor */
114 static uint32_t nasid;
115 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RDTUN, &nasid, 0,
116 "Number of ASIDs supported by this processor");
118 /* Current ASID generation for each host cpu */
119 static struct asid asid[MAXCPU];
122 * SVM host state saved area of size 4KB for each core.
124 static uint8_t hsave[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE);
126 static VMM_STAT_AMD(VCPU_EXITINTINFO, "VM exits during event delivery");
127 static VMM_STAT_AMD(VCPU_INTINFO_INJECTED, "Events pending at VM entry");
128 static VMM_STAT_AMD(VMEXIT_VINTR, "VM exits due to interrupt window");
130 static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val);
136 return (svm_feature & AMD_CPUID_SVM_FLUSH_BY_ASID);
143 return (svm_feature & AMD_CPUID_SVM_DECODE_ASSIST);
147 svm_disable(void *arg __unused)
151 efer = rdmsr(MSR_EFER);
153 wrmsr(MSR_EFER, efer);
157 * Disable SVM on all CPUs.
163 smp_rendezvous(NULL, svm_disable, NULL, NULL);
168 * Verify that all the features required by bhyve are available.
171 check_svm_features(void)
175 /* CPUID Fn8000_000A is for SVM */
176 do_cpuid(0x8000000A, regs);
177 svm_feature &= regs[3];
180 * The number of ASIDs can be configured to be less than what is
181 * supported by the hardware but not more.
183 if (nasid == 0 || nasid > regs[1])
185 KASSERT(nasid > 1, ("Insufficient ASIDs for guests: %#x", nasid));
187 /* bhyve requires the Nested Paging feature */
188 if (!(svm_feature & AMD_CPUID_SVM_NP)) {
189 printf("SVM: Nested Paging feature not available.\n");
193 /* bhyve requires the NRIP Save feature */
194 if (!(svm_feature & AMD_CPUID_SVM_NRIP_SAVE)) {
195 printf("SVM: NRIP Save feature not available.\n");
203 svm_enable(void *arg __unused)
207 efer = rdmsr(MSR_EFER);
209 wrmsr(MSR_EFER, efer);
211 wrmsr(MSR_VM_HSAVE_PA, vtophys(hsave[curcpu]));
215 * Return 1 if SVM is enabled on this processor and 0 otherwise.
222 /* Section 15.4 Enabling SVM from APM2. */
223 if ((amd_feature2 & AMDID2_SVM) == 0) {
224 printf("SVM: not available.\n");
228 msr = rdmsr(MSR_VM_CR);
229 if ((msr & VM_CR_SVMDIS) != 0) {
230 printf("SVM: disabled by BIOS.\n");
242 if (!svm_available())
245 error = check_svm_features();
249 vmcb_clean &= VMCB_CACHE_DEFAULT;
251 for (cpu = 0; cpu < MAXCPU; cpu++) {
253 * Initialize the host ASIDs to their "highest" valid values.
255 * The next ASID allocation will rollover both 'gen' and 'num'
256 * and start off the sequence at {1,1}.
258 asid[cpu].gen = ~0UL;
259 asid[cpu].num = nasid - 1;
263 svm_npt_init(ipinum);
265 /* Enable SVM on all CPUs */
266 smp_rendezvous(NULL, svm_enable, NULL, NULL);
278 /* Pentium compatible MSRs */
279 #define MSR_PENTIUM_START 0
280 #define MSR_PENTIUM_END 0x1FFF
281 /* AMD 6th generation and Intel compatible MSRs */
282 #define MSR_AMD6TH_START 0xC0000000UL
283 #define MSR_AMD6TH_END 0xC0001FFFUL
284 /* AMD 7th and 8th generation compatible MSRs */
285 #define MSR_AMD7TH_START 0xC0010000UL
286 #define MSR_AMD7TH_END 0xC0011FFFUL
289 * Get the index and bit position for a MSR in permission bitmap.
290 * Two bits are used for each MSR: lower bit for read and higher bit for write.
293 svm_msr_index(uint64_t msr, int *index, int *bit)
298 *bit = (msr % 4) * 2;
301 if (msr >= MSR_PENTIUM_START && msr <= MSR_PENTIUM_END) {
306 base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1);
307 if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) {
308 off = (msr - MSR_AMD6TH_START);
309 *index = (off + base) / 4;
313 base += (MSR_AMD6TH_END - MSR_AMD6TH_START + 1);
314 if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) {
315 off = (msr - MSR_AMD7TH_START);
316 *index = (off + base) / 4;
324 * Allow vcpu to read or write the 'msr' without trapping into the hypervisor.
327 svm_msr_perm(uint8_t *perm_bitmap, uint64_t msr, bool read, bool write)
329 int index, bit, error;
331 error = svm_msr_index(msr, &index, &bit);
332 KASSERT(error == 0, ("%s: invalid msr %#lx", __func__, msr));
333 KASSERT(index >= 0 && index < SVM_MSR_BITMAP_SIZE,
334 ("%s: invalid index %d for msr %#lx", __func__, index, msr));
335 KASSERT(bit >= 0 && bit <= 6, ("%s: invalid bit position %d "
336 "msr %#lx", __func__, bit, msr));
339 perm_bitmap[index] &= ~(1UL << bit);
342 perm_bitmap[index] &= ~(2UL << bit);
346 svm_msr_rw_ok(uint8_t *perm_bitmap, uint64_t msr)
349 svm_msr_perm(perm_bitmap, msr, true, true);
353 svm_msr_rd_ok(uint8_t *perm_bitmap, uint64_t msr)
356 svm_msr_perm(perm_bitmap, msr, true, false);
360 svm_get_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask)
362 struct vmcb_ctrl *ctrl;
364 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx));
366 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
367 return (ctrl->intercept[idx] & bitmask ? 1 : 0);
371 svm_set_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask,
374 struct vmcb_ctrl *ctrl;
377 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx));
379 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
380 oldval = ctrl->intercept[idx];
383 ctrl->intercept[idx] |= bitmask;
385 ctrl->intercept[idx] &= ~bitmask;
387 if (ctrl->intercept[idx] != oldval) {
388 svm_set_dirty(sc, vcpu, VMCB_CACHE_I);
389 VCPU_CTR3(sc->vm, vcpu, "intercept[%d] modified "
390 "from %#x to %#x", idx, oldval, ctrl->intercept[idx]);
395 svm_disable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask)
398 svm_set_intercept(sc, vcpu, off, bitmask, 0);
402 svm_enable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask)
405 svm_set_intercept(sc, vcpu, off, bitmask, 1);
409 vmcb_init(struct svm_softc *sc, int vcpu, uint64_t iopm_base_pa,
410 uint64_t msrpm_base_pa, uint64_t np_pml4)
412 struct vmcb_ctrl *ctrl;
413 struct vmcb_state *state;
417 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
418 state = svm_get_vmcb_state(sc, vcpu);
420 ctrl->iopm_base_pa = iopm_base_pa;
421 ctrl->msrpm_base_pa = msrpm_base_pa;
423 /* Enable nested paging */
425 ctrl->n_cr3 = np_pml4;
428 * Intercept accesses to the control registers that are not shadowed
429 * in the VMCB - i.e. all except cr0, cr2, cr3, cr4 and cr8.
431 for (n = 0; n < 16; n++) {
432 mask = (BIT(n) << 16) | BIT(n);
433 if (n == 0 || n == 2 || n == 3 || n == 4 || n == 8)
434 svm_disable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask);
436 svm_enable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask);
441 * Intercept everything when tracing guest exceptions otherwise
442 * just intercept machine check exception.
444 if (vcpu_trace_exceptions(sc->vm, vcpu)) {
445 for (n = 0; n < 32; n++) {
447 * Skip unimplemented vectors in the exception bitmap.
449 if (n == 2 || n == 9) {
452 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(n));
455 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(IDT_MC));
458 /* Intercept various events (for e.g. I/O, MSR and CPUID accesses) */
459 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IO);
460 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_MSR);
461 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_CPUID);
462 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INTR);
463 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INIT);
464 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_NMI);
465 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SMI);
466 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SHUTDOWN);
467 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
468 VMCB_INTCPT_FERR_FREEZE);
470 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MONITOR);
471 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MWAIT);
474 * From section "Canonicalization and Consistency Checks" in APMv2
475 * the VMRUN intercept bit must be set to pass the consistency check.
477 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMRUN);
480 * The ASID will be set to a non-zero value just before VMRUN.
485 * Section 15.21.1, Interrupt Masking in EFLAGS
486 * Section 15.21.2, Virtualizing APIC.TPR
488 * This must be set for %rflag and %cr8 isolation of guest and host.
490 ctrl->v_intr_masking = 1;
492 /* Enable Last Branch Record aka LBR for debugging */
493 ctrl->lbr_virt_en = 1;
494 state->dbgctl = BIT(0);
496 /* EFER_SVM must always be set when the guest is executing */
497 state->efer = EFER_SVM;
499 /* Set up the PAT to power-on state */
500 state->g_pat = PAT_VALUE(0, PAT_WRITE_BACK) |
501 PAT_VALUE(1, PAT_WRITE_THROUGH) |
502 PAT_VALUE(2, PAT_UNCACHED) |
503 PAT_VALUE(3, PAT_UNCACHEABLE) |
504 PAT_VALUE(4, PAT_WRITE_BACK) |
505 PAT_VALUE(5, PAT_WRITE_THROUGH) |
506 PAT_VALUE(6, PAT_UNCACHED) |
507 PAT_VALUE(7, PAT_UNCACHEABLE);
509 /* Set up DR6/7 to power-on state */
510 state->dr6 = DBREG_DR6_RESERVED1;
511 state->dr7 = DBREG_DR7_RESERVED1;
515 * Initialize a virtual machine.
518 svm_vminit(struct vm *vm, pmap_t pmap)
520 struct svm_softc *svm_sc;
521 struct svm_vcpu *vcpu;
522 vm_paddr_t msrpm_pa, iopm_pa, pml4_pa;
526 svm_sc = malloc(sizeof (*svm_sc), M_SVM, M_WAITOK | M_ZERO);
527 if (((uintptr_t)svm_sc & PAGE_MASK) != 0)
528 panic("malloc of svm_softc not aligned on page boundary");
530 svm_sc->msr_bitmap = contigmalloc(SVM_MSR_BITMAP_SIZE, M_SVM,
531 M_WAITOK, 0, ~(vm_paddr_t)0, PAGE_SIZE, 0);
532 if (svm_sc->msr_bitmap == NULL)
533 panic("contigmalloc of SVM MSR bitmap failed");
534 svm_sc->iopm_bitmap = contigmalloc(SVM_IO_BITMAP_SIZE, M_SVM,
535 M_WAITOK, 0, ~(vm_paddr_t)0, PAGE_SIZE, 0);
536 if (svm_sc->iopm_bitmap == NULL)
537 panic("contigmalloc of SVM IO bitmap failed");
540 svm_sc->nptp = (vm_offset_t)vtophys(pmap->pm_pml4);
543 * Intercept read and write accesses to all MSRs.
545 memset(svm_sc->msr_bitmap, 0xFF, SVM_MSR_BITMAP_SIZE);
548 * Access to the following MSRs is redirected to the VMCB when the
549 * guest is executing. Therefore it is safe to allow the guest to
550 * read/write these MSRs directly without hypervisor involvement.
552 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_GSBASE);
553 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_FSBASE);
554 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_KGSBASE);
556 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_STAR);
557 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_LSTAR);
558 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_CSTAR);
559 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SF_MASK);
560 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_CS_MSR);
561 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_ESP_MSR);
562 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_EIP_MSR);
563 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_PAT);
565 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_TSC);
568 * Intercept writes to make sure that the EFER_SVM bit is not cleared.
570 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_EFER);
572 /* Intercept access to all I/O ports. */
573 memset(svm_sc->iopm_bitmap, 0xFF, SVM_IO_BITMAP_SIZE);
575 iopm_pa = vtophys(svm_sc->iopm_bitmap);
576 msrpm_pa = vtophys(svm_sc->msr_bitmap);
577 pml4_pa = svm_sc->nptp;
578 maxcpus = vm_get_maxcpus(svm_sc->vm);
579 for (i = 0; i < maxcpus; i++) {
580 vcpu = svm_get_vcpu(svm_sc, i);
582 vcpu->lastcpu = NOCPU;
583 vcpu->vmcb_pa = vtophys(&vcpu->vmcb);
584 vmcb_init(svm_sc, i, iopm_pa, msrpm_pa, pml4_pa);
585 svm_msr_guest_init(svm_sc, i);
591 * Collateral for a generic SVM VM-exit.
594 vm_exit_svm(struct vm_exit *vme, uint64_t code, uint64_t info1, uint64_t info2)
597 vme->exitcode = VM_EXITCODE_SVM;
598 vme->u.svm.exitcode = code;
599 vme->u.svm.exitinfo1 = info1;
600 vme->u.svm.exitinfo2 = info2;
604 svm_cpl(struct vmcb_state *state)
609 * "Retrieve the CPL from the CPL field in the VMCB, not
610 * from any segment DPL"
615 static enum vm_cpu_mode
616 svm_vcpu_mode(struct vmcb *vmcb)
618 struct vmcb_segment seg;
619 struct vmcb_state *state;
622 state = &vmcb->state;
624 if (state->efer & EFER_LMA) {
625 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg);
626 KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__,
630 * Section 4.8.1 for APM2, check if Code Segment has
631 * Long attribute set in descriptor.
633 if (seg.attrib & VMCB_CS_ATTRIB_L)
634 return (CPU_MODE_64BIT);
636 return (CPU_MODE_COMPATIBILITY);
637 } else if (state->cr0 & CR0_PE) {
638 return (CPU_MODE_PROTECTED);
640 return (CPU_MODE_REAL);
644 static enum vm_paging_mode
645 svm_paging_mode(uint64_t cr0, uint64_t cr4, uint64_t efer)
648 if ((cr0 & CR0_PG) == 0)
649 return (PAGING_MODE_FLAT);
650 if ((cr4 & CR4_PAE) == 0)
651 return (PAGING_MODE_32);
653 return (PAGING_MODE_64);
655 return (PAGING_MODE_PAE);
659 * ins/outs utility routines
662 svm_inout_str_index(struct svm_regctx *regs, int in)
666 val = in ? regs->sctx_rdi : regs->sctx_rsi;
672 svm_inout_str_count(struct svm_regctx *regs, int rep)
676 val = rep ? regs->sctx_rcx : 1;
682 svm_inout_str_seginfo(struct svm_softc *svm_sc, int vcpu, int64_t info1,
683 int in, struct vm_inout_str *vis)
688 vis->seg_name = VM_REG_GUEST_ES;
690 /* The segment field has standard encoding */
691 s = (info1 >> 10) & 0x7;
692 vis->seg_name = vm_segment_name(s);
695 error = vmcb_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc);
696 KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error));
700 svm_inout_str_addrsize(uint64_t info1)
704 size = (info1 >> 7) & 0x7;
707 return (2); /* 16 bit */
709 return (4); /* 32 bit */
711 return (8); /* 64 bit */
713 panic("%s: invalid size encoding %d", __func__, size);
718 svm_paging_info(struct vmcb *vmcb, struct vm_guest_paging *paging)
720 struct vmcb_state *state;
722 state = &vmcb->state;
723 paging->cr3 = state->cr3;
724 paging->cpl = svm_cpl(state);
725 paging->cpu_mode = svm_vcpu_mode(vmcb);
726 paging->paging_mode = svm_paging_mode(state->cr0, state->cr4,
733 * Handle guest I/O intercept.
736 svm_handle_io(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit)
738 struct vmcb_ctrl *ctrl;
739 struct vmcb_state *state;
740 struct svm_regctx *regs;
741 struct vm_inout_str *vis;
745 state = svm_get_vmcb_state(svm_sc, vcpu);
746 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu);
747 regs = svm_get_guest_regctx(svm_sc, vcpu);
749 info1 = ctrl->exitinfo1;
750 inout_string = info1 & BIT(2) ? 1 : 0;
753 * The effective segment number in EXITINFO1[12:10] is populated
754 * only if the processor has the DecodeAssist capability.
756 * XXX this is not specified explicitly in APMv2 but can be verified
759 if (inout_string && !decode_assist())
762 vmexit->exitcode = VM_EXITCODE_INOUT;
763 vmexit->u.inout.in = (info1 & BIT(0)) ? 1 : 0;
764 vmexit->u.inout.string = inout_string;
765 vmexit->u.inout.rep = (info1 & BIT(3)) ? 1 : 0;
766 vmexit->u.inout.bytes = (info1 >> 4) & 0x7;
767 vmexit->u.inout.port = (uint16_t)(info1 >> 16);
768 vmexit->u.inout.eax = (uint32_t)(state->rax);
771 vmexit->exitcode = VM_EXITCODE_INOUT_STR;
772 vis = &vmexit->u.inout_str;
773 svm_paging_info(svm_get_vmcb(svm_sc, vcpu), &vis->paging);
774 vis->rflags = state->rflags;
775 vis->cr0 = state->cr0;
776 vis->index = svm_inout_str_index(regs, vmexit->u.inout.in);
777 vis->count = svm_inout_str_count(regs, vmexit->u.inout.rep);
778 vis->addrsize = svm_inout_str_addrsize(info1);
779 svm_inout_str_seginfo(svm_sc, vcpu, info1,
780 vmexit->u.inout.in, vis);
787 npf_fault_type(uint64_t exitinfo1)
790 if (exitinfo1 & VMCB_NPF_INFO1_W)
791 return (VM_PROT_WRITE);
792 else if (exitinfo1 & VMCB_NPF_INFO1_ID)
793 return (VM_PROT_EXECUTE);
795 return (VM_PROT_READ);
799 svm_npf_emul_fault(uint64_t exitinfo1)
802 if (exitinfo1 & VMCB_NPF_INFO1_ID) {
806 if (exitinfo1 & VMCB_NPF_INFO1_GPT) {
810 if ((exitinfo1 & VMCB_NPF_INFO1_GPA) == 0) {
818 svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit)
820 struct vm_guest_paging *paging;
821 struct vmcb_segment seg;
822 struct vmcb_ctrl *ctrl;
827 paging = &vmexit->u.inst_emul.paging;
829 vmexit->exitcode = VM_EXITCODE_INST_EMUL;
830 vmexit->u.inst_emul.gpa = gpa;
831 vmexit->u.inst_emul.gla = VIE_INVALID_GLA;
832 svm_paging_info(vmcb, paging);
834 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg);
835 KASSERT(error == 0, ("%s: vmcb_seg(CS) error %d", __func__, error));
837 switch(paging->cpu_mode) {
839 vmexit->u.inst_emul.cs_base = seg.base;
840 vmexit->u.inst_emul.cs_d = 0;
842 case CPU_MODE_PROTECTED:
843 case CPU_MODE_COMPATIBILITY:
844 vmexit->u.inst_emul.cs_base = seg.base;
847 * Section 4.8.1 of APM2, Default Operand Size or D bit.
849 vmexit->u.inst_emul.cs_d = (seg.attrib & VMCB_CS_ATTRIB_D) ?
853 vmexit->u.inst_emul.cs_base = 0;
854 vmexit->u.inst_emul.cs_d = 0;
859 * Copy the instruction bytes into 'vie' if available.
861 if (decode_assist() && !disable_npf_assist) {
862 inst_len = ctrl->inst_len;
863 inst_bytes = ctrl->inst_bytes;
868 vie_init(&vmexit->u.inst_emul.vie, inst_bytes, inst_len);
873 intrtype_to_str(int intr_type)
876 case VMCB_EVENTINJ_TYPE_INTR:
878 case VMCB_EVENTINJ_TYPE_NMI:
880 case VMCB_EVENTINJ_TYPE_INTn:
882 case VMCB_EVENTINJ_TYPE_EXCEPTION:
883 return ("exception");
885 panic("%s: unknown intr_type %d", __func__, intr_type);
891 * Inject an event to vcpu as described in section 15.20, "Event injection".
894 svm_eventinject(struct svm_softc *sc, int vcpu, int intr_type, int vector,
895 uint32_t error, bool ec_valid)
897 struct vmcb_ctrl *ctrl;
899 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
901 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0,
902 ("%s: event already pending %#lx", __func__, ctrl->eventinj));
904 KASSERT(vector >=0 && vector <= 255, ("%s: invalid vector %d",
908 case VMCB_EVENTINJ_TYPE_INTR:
909 case VMCB_EVENTINJ_TYPE_NMI:
910 case VMCB_EVENTINJ_TYPE_INTn:
912 case VMCB_EVENTINJ_TYPE_EXCEPTION:
913 if (vector >= 0 && vector <= 31 && vector != 2)
917 panic("%s: invalid intr_type/vector: %d/%d", __func__,
920 ctrl->eventinj = vector | (intr_type << 8) | VMCB_EVENTINJ_VALID;
922 ctrl->eventinj |= VMCB_EVENTINJ_EC_VALID;
923 ctrl->eventinj |= (uint64_t)error << 32;
924 VCPU_CTR3(sc->vm, vcpu, "Injecting %s at vector %d errcode %#x",
925 intrtype_to_str(intr_type), vector, error);
927 VCPU_CTR2(sc->vm, vcpu, "Injecting %s at vector %d",
928 intrtype_to_str(intr_type), vector);
933 svm_update_virqinfo(struct svm_softc *sc, int vcpu)
936 struct vlapic *vlapic;
937 struct vmcb_ctrl *ctrl;
940 vlapic = vm_lapic(vm, vcpu);
941 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
943 /* Update %cr8 in the emulated vlapic */
944 vlapic_set_cr8(vlapic, ctrl->v_tpr);
946 /* Virtual interrupt injection is not used. */
947 KASSERT(ctrl->v_intr_vector == 0, ("%s: invalid "
948 "v_intr_vector %d", __func__, ctrl->v_intr_vector));
952 svm_save_intinfo(struct svm_softc *svm_sc, int vcpu)
954 struct vmcb_ctrl *ctrl;
957 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu);
958 intinfo = ctrl->exitintinfo;
959 if (!VMCB_EXITINTINFO_VALID(intinfo))
963 * From APMv2, Section "Intercepts during IDT interrupt delivery"
965 * If a #VMEXIT happened during event delivery then record the event
966 * that was being delivered.
968 VCPU_CTR2(svm_sc->vm, vcpu, "SVM:Pending INTINFO(0x%lx), vector=%d.\n",
969 intinfo, VMCB_EXITINTINFO_VECTOR(intinfo));
970 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_EXITINTINFO, 1);
971 vm_exit_intinfo(svm_sc->vm, vcpu, intinfo);
976 vintr_intercept_enabled(struct svm_softc *sc, int vcpu)
979 return (svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
985 enable_intr_window_exiting(struct svm_softc *sc, int vcpu)
987 struct vmcb_ctrl *ctrl;
989 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
991 if (ctrl->v_irq && ctrl->v_intr_vector == 0) {
992 KASSERT(ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__));
993 KASSERT(vintr_intercept_enabled(sc, vcpu),
994 ("%s: vintr intercept should be enabled", __func__));
998 VCPU_CTR0(sc->vm, vcpu, "Enable intr window exiting");
1000 ctrl->v_ign_tpr = 1;
1001 ctrl->v_intr_vector = 0;
1002 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
1003 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR);
1006 static __inline void
1007 disable_intr_window_exiting(struct svm_softc *sc, int vcpu)
1009 struct vmcb_ctrl *ctrl;
1011 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1013 if (!ctrl->v_irq && ctrl->v_intr_vector == 0) {
1014 KASSERT(!vintr_intercept_enabled(sc, vcpu),
1015 ("%s: vintr intercept should be disabled", __func__));
1019 VCPU_CTR0(sc->vm, vcpu, "Disable intr window exiting");
1021 ctrl->v_intr_vector = 0;
1022 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
1023 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR);
1027 svm_modify_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t val)
1029 struct vmcb_ctrl *ctrl;
1032 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1033 oldval = ctrl->intr_shadow;
1034 newval = val ? 1 : 0;
1035 if (newval != oldval) {
1036 ctrl->intr_shadow = newval;
1037 VCPU_CTR1(sc->vm, vcpu, "Setting intr_shadow to %d", newval);
1043 svm_get_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t *val)
1045 struct vmcb_ctrl *ctrl;
1047 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1048 *val = ctrl->intr_shadow;
1053 * Once an NMI is injected it blocks delivery of further NMIs until the handler
1054 * executes an IRET. The IRET intercept is enabled when an NMI is injected to
1055 * to track when the vcpu is done handling the NMI.
1058 nmi_blocked(struct svm_softc *sc, int vcpu)
1062 blocked = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
1068 enable_nmi_blocking(struct svm_softc *sc, int vcpu)
1071 KASSERT(!nmi_blocked(sc, vcpu), ("vNMI already blocked"));
1072 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking enabled");
1073 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET);
1077 clear_nmi_blocking(struct svm_softc *sc, int vcpu)
1081 KASSERT(nmi_blocked(sc, vcpu), ("vNMI already unblocked"));
1082 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking cleared");
1084 * When the IRET intercept is cleared the vcpu will attempt to execute
1085 * the "iret" when it runs next. However, it is possible to inject
1086 * another NMI into the vcpu before the "iret" has actually executed.
1088 * For e.g. if the "iret" encounters a #NPF when accessing the stack
1089 * it will trap back into the hypervisor. If an NMI is pending for
1090 * the vcpu it will be injected into the guest.
1092 * XXX this needs to be fixed
1094 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET);
1097 * Set 'intr_shadow' to prevent an NMI from being injected on the
1100 error = svm_modify_intr_shadow(sc, vcpu, 1);
1101 KASSERT(!error, ("%s: error %d setting intr_shadow", __func__, error));
1104 #define EFER_MBZ_BITS 0xFFFFFFFFFFFF0200UL
1107 svm_write_efer(struct svm_softc *sc, int vcpu, uint64_t newval, bool *retu)
1109 struct vm_exit *vme;
1110 struct vmcb_state *state;
1111 uint64_t changed, lma, oldval;
1114 state = svm_get_vmcb_state(sc, vcpu);
1116 oldval = state->efer;
1117 VCPU_CTR2(sc->vm, vcpu, "wrmsr(efer) %#lx/%#lx", oldval, newval);
1119 newval &= ~0xFE; /* clear the Read-As-Zero (RAZ) bits */
1120 changed = oldval ^ newval;
1122 if (newval & EFER_MBZ_BITS)
1125 /* APMv2 Table 14-5 "Long-Mode Consistency Checks" */
1126 if (changed & EFER_LME) {
1127 if (state->cr0 & CR0_PG)
1131 /* EFER.LMA = EFER.LME & CR0.PG */
1132 if ((newval & EFER_LME) != 0 && (state->cr0 & CR0_PG) != 0)
1137 if ((newval & EFER_LMA) != lma)
1140 if (newval & EFER_NXE) {
1141 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_NO_EXECUTE))
1146 * XXX bhyve does not enforce segment limits in 64-bit mode. Until
1147 * this is fixed flag guest attempt to set EFER_LMSLE as an error.
1149 if (newval & EFER_LMSLE) {
1150 vme = vm_exitinfo(sc->vm, vcpu);
1151 vm_exit_svm(vme, VMCB_EXIT_MSR, 1, 0);
1156 if (newval & EFER_FFXSR) {
1157 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_FFXSR))
1161 if (newval & EFER_TCE) {
1162 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_TCE))
1166 error = svm_setreg(sc, vcpu, VM_REG_GUEST_EFER, newval);
1167 KASSERT(error == 0, ("%s: error %d updating efer", __func__, error));
1170 vm_inject_gp(sc->vm, vcpu);
1175 emulate_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val,
1181 error = lapic_wrmsr(sc->vm, vcpu, num, val, retu);
1182 else if (num == MSR_EFER)
1183 error = svm_write_efer(sc, vcpu, val, retu);
1185 error = svm_wrmsr(sc, vcpu, num, val, retu);
1191 emulate_rdmsr(struct svm_softc *sc, int vcpu, u_int num, bool *retu)
1193 struct vmcb_state *state;
1194 struct svm_regctx *ctx;
1199 error = lapic_rdmsr(sc->vm, vcpu, num, &result, retu);
1201 error = svm_rdmsr(sc, vcpu, num, &result, retu);
1204 state = svm_get_vmcb_state(sc, vcpu);
1205 ctx = svm_get_guest_regctx(sc, vcpu);
1206 state->rax = result & 0xffffffff;
1207 ctx->sctx_rdx = result >> 32;
1215 exit_reason_to_str(uint64_t reason)
1217 static char reasonbuf[32];
1220 case VMCB_EXIT_INVALID:
1221 return ("invalvmcb");
1222 case VMCB_EXIT_SHUTDOWN:
1223 return ("shutdown");
1225 return ("nptfault");
1226 case VMCB_EXIT_PAUSE:
1230 case VMCB_EXIT_CPUID:
1236 case VMCB_EXIT_INTR:
1240 case VMCB_EXIT_VINTR:
1244 case VMCB_EXIT_IRET:
1246 case VMCB_EXIT_MONITOR:
1248 case VMCB_EXIT_MWAIT:
1251 snprintf(reasonbuf, sizeof(reasonbuf), "%#lx", reason);
1258 * From section "State Saved on Exit" in APMv2: nRIP is saved for all #VMEXITs
1259 * that are due to instruction intercepts as well as MSR and IOIO intercepts
1260 * and exceptions caused by INT3, INTO and BOUND instructions.
1262 * Return 1 if the nRIP is valid and 0 otherwise.
1265 nrip_valid(uint64_t exitcode)
1268 case 0x00 ... 0x0F: /* read of CR0 through CR15 */
1269 case 0x10 ... 0x1F: /* write of CR0 through CR15 */
1270 case 0x20 ... 0x2F: /* read of DR0 through DR15 */
1271 case 0x30 ... 0x3F: /* write of DR0 through DR15 */
1272 case 0x43: /* INT3 */
1273 case 0x44: /* INTO */
1274 case 0x45: /* BOUND */
1275 case 0x65 ... 0x7C: /* VMEXIT_CR0_SEL_WRITE ... VMEXIT_MSR */
1276 case 0x80 ... 0x8D: /* VMEXIT_VMRUN ... VMEXIT_XSETBV */
1284 svm_vmexit(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit)
1287 struct vmcb_state *state;
1288 struct vmcb_ctrl *ctrl;
1289 struct svm_regctx *ctx;
1290 uint64_t code, info1, info2, val;
1291 uint32_t eax, ecx, edx;
1292 int error, errcode_valid, handled, idtvec, reflect;
1295 ctx = svm_get_guest_regctx(svm_sc, vcpu);
1296 vmcb = svm_get_vmcb(svm_sc, vcpu);
1297 state = &vmcb->state;
1301 code = ctrl->exitcode;
1302 info1 = ctrl->exitinfo1;
1303 info2 = ctrl->exitinfo2;
1305 vmexit->exitcode = VM_EXITCODE_BOGUS;
1306 vmexit->rip = state->rip;
1307 vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0;
1309 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_COUNT, 1);
1312 * #VMEXIT(INVALID) needs to be handled early because the VMCB is
1313 * in an inconsistent state and can trigger assertions that would
1314 * never happen otherwise.
1316 if (code == VMCB_EXIT_INVALID) {
1317 vm_exit_svm(vmexit, code, info1, info2);
1321 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event "
1322 "injection valid bit is set %#lx", __func__, ctrl->eventinj));
1324 KASSERT(vmexit->inst_length >= 0 && vmexit->inst_length <= 15,
1325 ("invalid inst_length %d: code (%#lx), info1 (%#lx), info2 (%#lx)",
1326 vmexit->inst_length, code, info1, info2));
1328 svm_update_virqinfo(svm_sc, vcpu);
1329 svm_save_intinfo(svm_sc, vcpu);
1332 case VMCB_EXIT_IRET:
1334 * Restart execution at "iret" but with the intercept cleared.
1336 vmexit->inst_length = 0;
1337 clear_nmi_blocking(svm_sc, vcpu);
1340 case VMCB_EXIT_VINTR: /* interrupt window exiting */
1341 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_VINTR, 1);
1344 case VMCB_EXIT_INTR: /* external interrupt */
1345 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXTINT, 1);
1348 case VMCB_EXIT_NMI: /* external NMI */
1352 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXCEPTION, 1);
1354 idtvec = code - 0x40;
1358 * Call the machine check handler by hand. Also don't
1359 * reflect the machine check back into the guest.
1362 VCPU_CTR0(svm_sc->vm, vcpu, "Vectoring to MCE handler");
1363 __asm __volatile("int $18");
1366 error = svm_setreg(svm_sc, vcpu, VM_REG_GUEST_CR2,
1368 KASSERT(error == 0, ("%s: error %d updating cr2",
1388 * The 'nrip' field is populated for INT3, INTO and
1389 * BOUND exceptions and this also implies that
1390 * 'inst_length' is non-zero.
1392 * Reset 'inst_length' to zero so the guest %rip at
1393 * event injection is identical to what it was when
1394 * the exception originally happened.
1396 VCPU_CTR2(svm_sc->vm, vcpu, "Reset inst_length from %d "
1397 "to zero before injecting exception %d",
1398 vmexit->inst_length, idtvec);
1399 vmexit->inst_length = 0;
1406 KASSERT(vmexit->inst_length == 0, ("invalid inst_length (%d) "
1407 "when reflecting exception %d into guest",
1408 vmexit->inst_length, idtvec));
1411 /* Reflect the exception back into the guest */
1412 VCPU_CTR2(svm_sc->vm, vcpu, "Reflecting exception "
1413 "%d/%#x into the guest", idtvec, (int)info1);
1414 error = vm_inject_exception(svm_sc->vm, vcpu, idtvec,
1415 errcode_valid, info1, 0);
1416 KASSERT(error == 0, ("%s: vm_inject_exception error %d",
1421 case VMCB_EXIT_MSR: /* MSR access. */
1423 ecx = ctx->sctx_rcx;
1424 edx = ctx->sctx_rdx;
1428 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_WRMSR, 1);
1429 val = (uint64_t)edx << 32 | eax;
1430 VCPU_CTR2(svm_sc->vm, vcpu, "wrmsr %#x val %#lx",
1432 if (emulate_wrmsr(svm_sc, vcpu, ecx, val, &retu)) {
1433 vmexit->exitcode = VM_EXITCODE_WRMSR;
1434 vmexit->u.msr.code = ecx;
1435 vmexit->u.msr.wval = val;
1439 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
1440 ("emulate_wrmsr retu with bogus exitcode"));
1443 VCPU_CTR1(svm_sc->vm, vcpu, "rdmsr %#x", ecx);
1444 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_RDMSR, 1);
1445 if (emulate_rdmsr(svm_sc, vcpu, ecx, &retu)) {
1446 vmexit->exitcode = VM_EXITCODE_RDMSR;
1447 vmexit->u.msr.code = ecx;
1451 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
1452 ("emulate_rdmsr retu with bogus exitcode"));
1457 handled = svm_handle_io(svm_sc, vcpu, vmexit);
1458 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INOUT, 1);
1460 case VMCB_EXIT_CPUID:
1461 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_CPUID, 1);
1462 handled = x86_emulate_cpuid(svm_sc->vm, vcpu,
1463 (uint32_t *)&state->rax,
1464 (uint32_t *)&ctx->sctx_rbx,
1465 (uint32_t *)&ctx->sctx_rcx,
1466 (uint32_t *)&ctx->sctx_rdx);
1469 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_HLT, 1);
1470 vmexit->exitcode = VM_EXITCODE_HLT;
1471 vmexit->u.hlt.rflags = state->rflags;
1473 case VMCB_EXIT_PAUSE:
1474 vmexit->exitcode = VM_EXITCODE_PAUSE;
1475 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_PAUSE, 1);
1478 /* EXITINFO2 contains the faulting guest physical address */
1479 if (info1 & VMCB_NPF_INFO1_RSV) {
1480 VCPU_CTR2(svm_sc->vm, vcpu, "nested page fault with "
1481 "reserved bits set: info1(%#lx) info2(%#lx)",
1483 } else if (vm_mem_allocated(svm_sc->vm, vcpu, info2)) {
1484 vmexit->exitcode = VM_EXITCODE_PAGING;
1485 vmexit->u.paging.gpa = info2;
1486 vmexit->u.paging.fault_type = npf_fault_type(info1);
1487 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_NESTED_FAULT, 1);
1488 VCPU_CTR3(svm_sc->vm, vcpu, "nested page fault "
1489 "on gpa %#lx/%#lx at rip %#lx",
1490 info2, info1, state->rip);
1491 } else if (svm_npf_emul_fault(info1)) {
1492 svm_handle_inst_emul(vmcb, info2, vmexit);
1493 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INST_EMUL, 1);
1494 VCPU_CTR3(svm_sc->vm, vcpu, "inst_emul fault "
1495 "for gpa %#lx/%#lx at rip %#lx",
1496 info2, info1, state->rip);
1499 case VMCB_EXIT_MONITOR:
1500 vmexit->exitcode = VM_EXITCODE_MONITOR;
1502 case VMCB_EXIT_MWAIT:
1503 vmexit->exitcode = VM_EXITCODE_MWAIT;
1506 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_UNKNOWN, 1);
1510 VCPU_CTR4(svm_sc->vm, vcpu, "%s %s vmexit at %#lx/%d",
1511 handled ? "handled" : "unhandled", exit_reason_to_str(code),
1512 vmexit->rip, vmexit->inst_length);
1515 vmexit->rip += vmexit->inst_length;
1516 vmexit->inst_length = 0;
1517 state->rip = vmexit->rip;
1519 if (vmexit->exitcode == VM_EXITCODE_BOGUS) {
1521 * If this VM exit was not claimed by anybody then
1522 * treat it as a generic SVM exit.
1524 vm_exit_svm(vmexit, code, info1, info2);
1527 * The exitcode and collateral have been populated.
1528 * The VM exit will be processed further in userland.
1536 svm_inj_intinfo(struct svm_softc *svm_sc, int vcpu)
1540 if (!vm_entry_intinfo(svm_sc->vm, vcpu, &intinfo))
1543 KASSERT(VMCB_EXITINTINFO_VALID(intinfo), ("%s: entry intinfo is not "
1544 "valid: %#lx", __func__, intinfo));
1546 svm_eventinject(svm_sc, vcpu, VMCB_EXITINTINFO_TYPE(intinfo),
1547 VMCB_EXITINTINFO_VECTOR(intinfo),
1548 VMCB_EXITINTINFO_EC(intinfo),
1549 VMCB_EXITINTINFO_EC_VALID(intinfo));
1550 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_INTINFO_INJECTED, 1);
1551 VCPU_CTR1(svm_sc->vm, vcpu, "Injected entry intinfo: %#lx", intinfo);
1555 * Inject event to virtual cpu.
1558 svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic)
1560 struct vmcb_ctrl *ctrl;
1561 struct vmcb_state *state;
1562 struct svm_vcpu *vcpustate;
1564 int vector, need_intr_window;
1567 state = svm_get_vmcb_state(sc, vcpu);
1568 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1569 vcpustate = svm_get_vcpu(sc, vcpu);
1571 need_intr_window = 0;
1573 if (vcpustate->nextrip != state->rip) {
1574 ctrl->intr_shadow = 0;
1575 VCPU_CTR2(sc->vm, vcpu, "Guest interrupt blocking "
1576 "cleared due to rip change: %#lx/%#lx",
1577 vcpustate->nextrip, state->rip);
1581 * Inject pending events or exceptions for this vcpu.
1583 * An event might be pending because the previous #VMEXIT happened
1584 * during event delivery (i.e. ctrl->exitintinfo).
1586 * An event might also be pending because an exception was injected
1587 * by the hypervisor (e.g. #PF during instruction emulation).
1589 svm_inj_intinfo(sc, vcpu);
1591 /* NMI event has priority over interrupts. */
1592 if (vm_nmi_pending(sc->vm, vcpu)) {
1593 if (nmi_blocked(sc, vcpu)) {
1595 * Can't inject another NMI if the guest has not
1596 * yet executed an "iret" after the last NMI.
1598 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due "
1600 } else if (ctrl->intr_shadow) {
1602 * Can't inject an NMI if the vcpu is in an intr_shadow.
1604 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due to "
1605 "interrupt shadow");
1606 need_intr_window = 1;
1608 } else if (ctrl->eventinj & VMCB_EVENTINJ_VALID) {
1610 * If there is already an exception/interrupt pending
1611 * then defer the NMI until after that.
1613 VCPU_CTR1(sc->vm, vcpu, "Cannot inject NMI due to "
1614 "eventinj %#lx", ctrl->eventinj);
1617 * Use self-IPI to trigger a VM-exit as soon as
1618 * possible after the event injection is completed.
1620 * This works only if the external interrupt exiting
1621 * is at a lower priority than the event injection.
1623 * Although not explicitly specified in APMv2 the
1624 * relative priorities were verified empirically.
1626 ipi_cpu(curcpu, IPI_AST); /* XXX vmm_ipinum? */
1628 vm_nmi_clear(sc->vm, vcpu);
1630 /* Inject NMI, vector number is not used */
1631 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_NMI,
1634 /* virtual NMI blocking is now in effect */
1635 enable_nmi_blocking(sc, vcpu);
1637 VCPU_CTR0(sc->vm, vcpu, "Injecting vNMI");
1641 extint_pending = vm_extint_pending(sc->vm, vcpu);
1642 if (!extint_pending) {
1643 if (!vlapic_pending_intr(vlapic, &vector))
1645 KASSERT(vector >= 16 && vector <= 255,
1646 ("invalid vector %d from local APIC", vector));
1648 /* Ask the legacy pic for a vector to inject */
1649 vatpic_pending_intr(sc->vm, &vector);
1650 KASSERT(vector >= 0 && vector <= 255,
1651 ("invalid vector %d from INTR", vector));
1655 * If the guest has disabled interrupts or is in an interrupt shadow
1656 * then we cannot inject the pending interrupt.
1658 if ((state->rflags & PSL_I) == 0) {
1659 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to "
1660 "rflags %#lx", vector, state->rflags);
1661 need_intr_window = 1;
1665 if (ctrl->intr_shadow) {
1666 VCPU_CTR1(sc->vm, vcpu, "Cannot inject vector %d due to "
1667 "interrupt shadow", vector);
1668 need_intr_window = 1;
1672 if (ctrl->eventinj & VMCB_EVENTINJ_VALID) {
1673 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to "
1674 "eventinj %#lx", vector, ctrl->eventinj);
1675 need_intr_window = 1;
1679 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_INTR, vector, 0, false);
1681 if (!extint_pending) {
1682 vlapic_intr_accepted(vlapic, vector);
1684 vm_extint_clear(sc->vm, vcpu);
1685 vatpic_intr_accepted(sc->vm, vector);
1689 * Force a VM-exit as soon as the vcpu is ready to accept another
1690 * interrupt. This is done because the PIC might have another vector
1691 * that it wants to inject. Also, if the APIC has a pending interrupt
1692 * that was preempted by the ExtInt then it allows us to inject the
1693 * APIC vector as soon as possible.
1695 need_intr_window = 1;
1698 * The guest can modify the TPR by writing to %CR8. In guest mode
1699 * the processor reflects this write to V_TPR without hypervisor
1702 * The guest can also modify the TPR by writing to it via the memory
1703 * mapped APIC page. In this case, the write will be emulated by the
1704 * hypervisor. For this reason V_TPR must be updated before every
1707 v_tpr = vlapic_get_cr8(vlapic);
1708 KASSERT(v_tpr <= 15, ("invalid v_tpr %#x", v_tpr));
1709 if (ctrl->v_tpr != v_tpr) {
1710 VCPU_CTR2(sc->vm, vcpu, "VMCB V_TPR changed from %#x to %#x",
1711 ctrl->v_tpr, v_tpr);
1712 ctrl->v_tpr = v_tpr;
1713 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
1716 if (need_intr_window) {
1718 * We use V_IRQ in conjunction with the VINTR intercept to
1719 * trap into the hypervisor as soon as a virtual interrupt
1722 * Since injected events are not subject to intercept checks
1723 * we need to ensure that the V_IRQ is not actually going to
1724 * be delivered on VM entry. The KASSERT below enforces this.
1726 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 ||
1727 (state->rflags & PSL_I) == 0 || ctrl->intr_shadow,
1728 ("Bogus intr_window_exiting: eventinj (%#lx), "
1729 "intr_shadow (%u), rflags (%#lx)",
1730 ctrl->eventinj, ctrl->intr_shadow, state->rflags));
1731 enable_intr_window_exiting(sc, vcpu);
1733 disable_intr_window_exiting(sc, vcpu);
1737 static __inline void
1738 restore_host_tss(void)
1740 struct system_segment_descriptor *tss_sd;
1743 * The TSS descriptor was in use prior to launching the guest so it
1744 * has been marked busy.
1746 * 'ltr' requires the descriptor to be marked available so change the
1747 * type to "64-bit available TSS".
1749 tss_sd = PCPU_GET(tss);
1750 tss_sd->sd_type = SDT_SYSTSS;
1751 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1755 check_asid(struct svm_softc *sc, int vcpuid, pmap_t pmap, u_int thiscpu)
1757 struct svm_vcpu *vcpustate;
1758 struct vmcb_ctrl *ctrl;
1762 KASSERT(CPU_ISSET(thiscpu, &pmap->pm_active), ("%s: nested pmap not "
1763 "active on cpu %u", __func__, thiscpu));
1765 vcpustate = svm_get_vcpu(sc, vcpuid);
1766 ctrl = svm_get_vmcb_ctrl(sc, vcpuid);
1769 * The TLB entries associated with the vcpu's ASID are not valid
1770 * if either of the following conditions is true:
1772 * 1. The vcpu's ASID generation is different than the host cpu's
1773 * ASID generation. This happens when the vcpu migrates to a new
1774 * host cpu. It can also happen when the number of vcpus executing
1775 * on a host cpu is greater than the number of ASIDs available.
1777 * 2. The pmap generation number is different than the value cached in
1778 * the 'vcpustate'. This happens when the host invalidates pages
1779 * belonging to the guest.
1781 * asidgen eptgen Action
1788 * (a) There is no mismatch in eptgen or ASID generation and therefore
1789 * no further action is needed.
1791 * (b1) If the cpu supports FlushByAsid then the vcpu's ASID is
1792 * retained and the TLB entries associated with this ASID
1793 * are flushed by VMRUN.
1795 * (b2) If the cpu does not support FlushByAsid then a new ASID is
1798 * (c) A new ASID is allocated.
1800 * (d) A new ASID is allocated.
1804 eptgen = pmap->pm_eptgen;
1805 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_NOTHING;
1807 if (vcpustate->asid.gen != asid[thiscpu].gen) {
1808 alloc_asid = true; /* (c) and (d) */
1809 } else if (vcpustate->eptgen != eptgen) {
1810 if (flush_by_asid())
1811 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; /* (b1) */
1813 alloc_asid = true; /* (b2) */
1816 * This is the common case (a).
1818 KASSERT(!alloc_asid, ("ASID allocation not necessary"));
1819 KASSERT(ctrl->tlb_ctrl == VMCB_TLB_FLUSH_NOTHING,
1820 ("Invalid VMCB tlb_ctrl: %#x", ctrl->tlb_ctrl));
1824 if (++asid[thiscpu].num >= nasid) {
1825 asid[thiscpu].num = 1;
1826 if (++asid[thiscpu].gen == 0)
1827 asid[thiscpu].gen = 1;
1829 * If this cpu does not support "flush-by-asid"
1830 * then flush the entire TLB on a generation
1831 * bump. Subsequent ASID allocation in this
1832 * generation can be done without a TLB flush.
1834 if (!flush_by_asid())
1835 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_ALL;
1837 vcpustate->asid.gen = asid[thiscpu].gen;
1838 vcpustate->asid.num = asid[thiscpu].num;
1840 ctrl->asid = vcpustate->asid.num;
1841 svm_set_dirty(sc, vcpuid, VMCB_CACHE_ASID);
1843 * If this cpu supports "flush-by-asid" then the TLB
1844 * was not flushed after the generation bump. The TLB
1845 * is flushed selectively after every new ASID allocation.
1847 if (flush_by_asid())
1848 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST;
1850 vcpustate->eptgen = eptgen;
1852 KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero"));
1853 KASSERT(ctrl->asid == vcpustate->asid.num,
1854 ("ASID mismatch: %u/%u", ctrl->asid, vcpustate->asid.num));
1857 static __inline void
1861 __asm __volatile("clgi");
1864 static __inline void
1868 __asm __volatile("stgi");
1871 static __inline void
1872 svm_dr_enter_guest(struct svm_regctx *gctx)
1875 /* Save host control debug registers. */
1876 gctx->host_dr7 = rdr7();
1877 gctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);
1880 * Disable debugging in DR7 and DEBUGCTL to avoid triggering
1881 * exceptions in the host based on the guest DRx values. The
1882 * guest DR6, DR7, and DEBUGCTL are saved/restored in the
1886 wrmsr(MSR_DEBUGCTLMSR, 0);
1888 /* Save host debug registers. */
1889 gctx->host_dr0 = rdr0();
1890 gctx->host_dr1 = rdr1();
1891 gctx->host_dr2 = rdr2();
1892 gctx->host_dr3 = rdr3();
1893 gctx->host_dr6 = rdr6();
1895 /* Restore guest debug registers. */
1896 load_dr0(gctx->sctx_dr0);
1897 load_dr1(gctx->sctx_dr1);
1898 load_dr2(gctx->sctx_dr2);
1899 load_dr3(gctx->sctx_dr3);
1902 static __inline void
1903 svm_dr_leave_guest(struct svm_regctx *gctx)
1906 /* Save guest debug registers. */
1907 gctx->sctx_dr0 = rdr0();
1908 gctx->sctx_dr1 = rdr1();
1909 gctx->sctx_dr2 = rdr2();
1910 gctx->sctx_dr3 = rdr3();
1913 * Restore host debug registers. Restore DR7 and DEBUGCTL
1916 load_dr0(gctx->host_dr0);
1917 load_dr1(gctx->host_dr1);
1918 load_dr2(gctx->host_dr2);
1919 load_dr3(gctx->host_dr3);
1920 load_dr6(gctx->host_dr6);
1921 wrmsr(MSR_DEBUGCTLMSR, gctx->host_debugctl);
1922 load_dr7(gctx->host_dr7);
1926 * Start vcpu with specified RIP.
1929 svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap,
1930 struct vm_eventinfo *evinfo)
1932 struct svm_regctx *gctx;
1933 struct svm_softc *svm_sc;
1934 struct svm_vcpu *vcpustate;
1935 struct vmcb_state *state;
1936 struct vmcb_ctrl *ctrl;
1937 struct vm_exit *vmexit;
1938 struct vlapic *vlapic;
1947 vcpustate = svm_get_vcpu(svm_sc, vcpu);
1948 state = svm_get_vmcb_state(svm_sc, vcpu);
1949 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu);
1950 vmexit = vm_exitinfo(vm, vcpu);
1951 vlapic = vm_lapic(vm, vcpu);
1953 gctx = svm_get_guest_regctx(svm_sc, vcpu);
1954 vmcb_pa = svm_sc->vcpu[vcpu].vmcb_pa;
1956 if (vcpustate->lastcpu != curcpu) {
1958 * Force new ASID allocation by invalidating the generation.
1960 vcpustate->asid.gen = 0;
1963 * Invalidate the VMCB state cache by marking all fields dirty.
1965 svm_set_dirty(svm_sc, vcpu, 0xffffffff);
1969 * Setting 'vcpustate->lastcpu' here is bit premature because
1970 * we may return from this function without actually executing
1971 * the VMRUN instruction. This could happen if a rendezvous
1972 * or an AST is pending on the first time through the loop.
1974 * This works for now but any new side-effects of vcpu
1975 * migration should take this case into account.
1977 vcpustate->lastcpu = curcpu;
1978 vmm_stat_incr(vm, vcpu, VCPU_MIGRATIONS, 1);
1981 svm_msr_guest_enter(svm_sc, vcpu);
1983 /* Update Guest RIP */
1988 * Disable global interrupts to guarantee atomicity during
1989 * loading of guest state. This includes not only the state
1990 * loaded by the "vmrun" instruction but also software state
1991 * maintained by the hypervisor: suspended and rendezvous
1992 * state, NPT generation number, vlapic interrupts etc.
1996 if (vcpu_suspended(evinfo)) {
1998 vm_exit_suspended(vm, vcpu, state->rip);
2002 if (vcpu_rendezvous_pending(evinfo)) {
2004 vm_exit_rendezvous(vm, vcpu, state->rip);
2008 if (vcpu_reqidle(evinfo)) {
2010 vm_exit_reqidle(vm, vcpu, state->rip);
2014 /* We are asked to give the cpu by scheduler. */
2015 if (vcpu_should_yield(vm, vcpu)) {
2017 vm_exit_astpending(vm, vcpu, state->rip);
2021 if (vcpu_debugged(vm, vcpu)) {
2023 vm_exit_debug(vm, vcpu, state->rip);
2028 * #VMEXIT resumes the host with the guest LDTR, so
2029 * save the current LDT selector so it can be restored
2030 * after an exit. The userspace hypervisor probably
2031 * doesn't use a LDT, but save and restore it to be
2036 svm_inj_interrupts(svm_sc, vcpu, vlapic);
2038 /* Activate the nested pmap on 'curcpu' */
2039 CPU_SET_ATOMIC_ACQ(curcpu, &pmap->pm_active);
2042 * Check the pmap generation and the ASID generation to
2043 * ensure that the vcpu does not use stale TLB mappings.
2045 check_asid(svm_sc, vcpu, pmap, curcpu);
2047 ctrl->vmcb_clean = vmcb_clean & ~vcpustate->dirty;
2048 vcpustate->dirty = 0;
2049 VCPU_CTR1(vm, vcpu, "vmcb clean %#x", ctrl->vmcb_clean);
2051 /* Launch Virtual Machine. */
2052 VCPU_CTR1(vm, vcpu, "Resume execution at %#lx", state->rip);
2053 svm_dr_enter_guest(gctx);
2054 svm_launch(vmcb_pa, gctx, get_pcpu());
2055 svm_dr_leave_guest(gctx);
2057 CPU_CLR_ATOMIC(curcpu, &pmap->pm_active);
2060 * The host GDTR and IDTR is saved by VMRUN and restored
2061 * automatically on #VMEXIT. However, the host TSS needs
2062 * to be restored explicitly.
2066 /* Restore host LDTR. */
2069 /* #VMEXIT disables interrupts so re-enable them here. */
2072 /* Update 'nextrip' */
2073 vcpustate->nextrip = state->rip;
2075 /* Handle #VMEXIT and if required return to user space. */
2076 handled = svm_vmexit(svm_sc, vcpu, vmexit);
2079 svm_msr_guest_exit(svm_sc, vcpu);
2085 svm_vmcleanup(void *arg)
2087 struct svm_softc *sc = arg;
2089 contigfree(sc->iopm_bitmap, SVM_IO_BITMAP_SIZE, M_SVM);
2090 contigfree(sc->msr_bitmap, SVM_MSR_BITMAP_SIZE, M_SVM);
2095 swctx_regptr(struct svm_regctx *regctx, int reg)
2099 case VM_REG_GUEST_RBX:
2100 return (®ctx->sctx_rbx);
2101 case VM_REG_GUEST_RCX:
2102 return (®ctx->sctx_rcx);
2103 case VM_REG_GUEST_RDX:
2104 return (®ctx->sctx_rdx);
2105 case VM_REG_GUEST_RDI:
2106 return (®ctx->sctx_rdi);
2107 case VM_REG_GUEST_RSI:
2108 return (®ctx->sctx_rsi);
2109 case VM_REG_GUEST_RBP:
2110 return (®ctx->sctx_rbp);
2111 case VM_REG_GUEST_R8:
2112 return (®ctx->sctx_r8);
2113 case VM_REG_GUEST_R9:
2114 return (®ctx->sctx_r9);
2115 case VM_REG_GUEST_R10:
2116 return (®ctx->sctx_r10);
2117 case VM_REG_GUEST_R11:
2118 return (®ctx->sctx_r11);
2119 case VM_REG_GUEST_R12:
2120 return (®ctx->sctx_r12);
2121 case VM_REG_GUEST_R13:
2122 return (®ctx->sctx_r13);
2123 case VM_REG_GUEST_R14:
2124 return (®ctx->sctx_r14);
2125 case VM_REG_GUEST_R15:
2126 return (®ctx->sctx_r15);
2127 case VM_REG_GUEST_DR0:
2128 return (®ctx->sctx_dr0);
2129 case VM_REG_GUEST_DR1:
2130 return (®ctx->sctx_dr1);
2131 case VM_REG_GUEST_DR2:
2132 return (®ctx->sctx_dr2);
2133 case VM_REG_GUEST_DR3:
2134 return (®ctx->sctx_dr3);
2141 svm_getreg(void *arg, int vcpu, int ident, uint64_t *val)
2143 struct svm_softc *svm_sc;
2148 if (ident == VM_REG_GUEST_INTR_SHADOW) {
2149 return (svm_get_intr_shadow(svm_sc, vcpu, val));
2152 if (vmcb_read(svm_sc, vcpu, ident, val) == 0) {
2156 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident);
2163 VCPU_CTR1(svm_sc->vm, vcpu, "svm_getreg: unknown register %#x", ident);
2168 svm_setreg(void *arg, int vcpu, int ident, uint64_t val)
2170 struct svm_softc *svm_sc;
2175 if (ident == VM_REG_GUEST_INTR_SHADOW) {
2176 return (svm_modify_intr_shadow(svm_sc, vcpu, val));
2179 if (vmcb_write(svm_sc, vcpu, ident, val) == 0) {
2183 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident);
2191 * XXX deal with CR3 and invalidate TLB entries tagged with the
2192 * vcpu's ASID. This needs to be treated differently depending on
2193 * whether 'running' is true/false.
2196 VCPU_CTR1(svm_sc->vm, vcpu, "svm_setreg: unknown register %#x", ident);
2201 svm_setcap(void *arg, int vcpu, int type, int val)
2203 struct svm_softc *sc;
2209 case VM_CAP_HALT_EXIT:
2210 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2211 VMCB_INTCPT_HLT, val);
2213 case VM_CAP_PAUSE_EXIT:
2214 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2215 VMCB_INTCPT_PAUSE, val);
2217 case VM_CAP_UNRESTRICTED_GUEST:
2218 /* Unrestricted guest execution cannot be disabled in SVM */
2230 svm_getcap(void *arg, int vcpu, int type, int *retval)
2232 struct svm_softc *sc;
2239 case VM_CAP_HALT_EXIT:
2240 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2243 case VM_CAP_PAUSE_EXIT:
2244 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2247 case VM_CAP_UNRESTRICTED_GUEST:
2248 *retval = 1; /* unrestricted guest is always enabled */
2257 static struct vlapic *
2258 svm_vlapic_init(void *arg, int vcpuid)
2260 struct svm_softc *svm_sc;
2261 struct vlapic *vlapic;
2264 vlapic = malloc(sizeof(struct vlapic), M_SVM_VLAPIC, M_WAITOK | M_ZERO);
2265 vlapic->vm = svm_sc->vm;
2266 vlapic->vcpuid = vcpuid;
2267 vlapic->apic_page = (struct LAPIC *)&svm_sc->apic_page[vcpuid];
2269 vlapic_init(vlapic);
2275 svm_vlapic_cleanup(void *arg, struct vlapic *vlapic)
2278 vlapic_cleanup(vlapic);
2279 free(vlapic, M_SVM_VLAPIC);
2282 struct vmm_ops vmm_ops_amd = {
2284 .cleanup = svm_cleanup,
2285 .resume = svm_restore,
2286 .vminit = svm_vminit,
2288 .vmcleanup = svm_vmcleanup,
2289 .vmgetreg = svm_getreg,
2290 .vmsetreg = svm_setreg,
2291 .vmgetdesc = vmcb_getdesc,
2292 .vmsetdesc = vmcb_setdesc,
2293 .vmgetcap = svm_getcap,
2294 .vmsetcap = svm_setcap,
2295 .vmspace_alloc = svm_npt_alloc,
2296 .vmspace_free = svm_npt_free,
2297 .vlapic_init = svm_vlapic_init,
2298 .vlapic_cleanup = svm_vlapic_cleanup,