2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013, Anish Gupta (akgupt3@gmail.com)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "opt_bhyve_snapshot.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
41 #include <sys/sysctl.h>
46 #include <machine/cpufunc.h>
47 #include <machine/psl.h>
48 #include <machine/md_var.h>
49 #include <machine/reg.h>
50 #include <machine/specialreg.h>
51 #include <machine/smp.h>
52 #include <machine/vmm.h>
53 #include <machine/vmm_dev.h>
54 #include <machine/vmm_instruction_emul.h>
55 #include <machine/vmm_snapshot.h>
57 #include "vmm_lapic.h"
60 #include "vmm_ioport.h"
63 #include "vlapic_priv.h"
68 #include "svm_softc.h"
73 SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
77 * SVM CPUID function 0x8000_000A, edx bit decoding.
79 #define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */
80 #define AMD_CPUID_SVM_LBR BIT(1) /* Last branch virtualization */
81 #define AMD_CPUID_SVM_SVML BIT(2) /* SVM lock */
82 #define AMD_CPUID_SVM_NRIP_SAVE BIT(3) /* Next RIP is saved */
83 #define AMD_CPUID_SVM_TSC_RATE BIT(4) /* TSC rate control. */
84 #define AMD_CPUID_SVM_VMCB_CLEAN BIT(5) /* VMCB state caching */
85 #define AMD_CPUID_SVM_FLUSH_BY_ASID BIT(6) /* Flush by ASID */
86 #define AMD_CPUID_SVM_DECODE_ASSIST BIT(7) /* Decode assist */
87 #define AMD_CPUID_SVM_PAUSE_INC BIT(10) /* Pause intercept filter. */
88 #define AMD_CPUID_SVM_PAUSE_FTH BIT(12) /* Pause filter threshold */
89 #define AMD_CPUID_SVM_AVIC BIT(13) /* AVIC present */
91 #define VMCB_CACHE_DEFAULT (VMCB_CACHE_ASID | \
102 static uint32_t vmcb_clean = VMCB_CACHE_DEFAULT;
103 SYSCTL_INT(_hw_vmm_svm, OID_AUTO, vmcb_clean, CTLFLAG_RDTUN, &vmcb_clean,
106 static MALLOC_DEFINE(M_SVM, "svm", "svm");
107 static MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic");
109 static uint32_t svm_feature = ~0U; /* AMD SVM features. */
110 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RDTUN, &svm_feature, 0,
111 "SVM features advertised by CPUID.8000000AH:EDX");
113 static int disable_npf_assist;
114 SYSCTL_INT(_hw_vmm_svm, OID_AUTO, disable_npf_assist, CTLFLAG_RWTUN,
115 &disable_npf_assist, 0, NULL);
117 /* Maximum ASIDs supported by the processor */
118 static uint32_t nasid;
119 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RDTUN, &nasid, 0,
120 "Number of ASIDs supported by this processor");
122 /* Current ASID generation for each host cpu */
123 static struct asid asid[MAXCPU];
126 * SVM host state saved area of size 4KB for each core.
128 static uint8_t hsave[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE);
130 static VMM_STAT_AMD(VCPU_EXITINTINFO, "VM exits during event delivery");
131 static VMM_STAT_AMD(VCPU_INTINFO_INJECTED, "Events pending at VM entry");
132 static VMM_STAT_AMD(VMEXIT_VINTR, "VM exits due to interrupt window");
134 static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val);
140 return (svm_feature & AMD_CPUID_SVM_FLUSH_BY_ASID);
147 return (svm_feature & AMD_CPUID_SVM_DECODE_ASSIST);
151 svm_disable(void *arg __unused)
155 efer = rdmsr(MSR_EFER);
157 wrmsr(MSR_EFER, efer);
161 * Disable SVM on all CPUs.
167 smp_rendezvous(NULL, svm_disable, NULL, NULL);
172 * Verify that all the features required by bhyve are available.
175 check_svm_features(void)
179 /* CPUID Fn8000_000A is for SVM */
180 do_cpuid(0x8000000A, regs);
181 svm_feature &= regs[3];
184 * The number of ASIDs can be configured to be less than what is
185 * supported by the hardware but not more.
187 if (nasid == 0 || nasid > regs[1])
189 KASSERT(nasid > 1, ("Insufficient ASIDs for guests: %#x", nasid));
191 /* bhyve requires the Nested Paging feature */
192 if (!(svm_feature & AMD_CPUID_SVM_NP)) {
193 printf("SVM: Nested Paging feature not available.\n");
197 /* bhyve requires the NRIP Save feature */
198 if (!(svm_feature & AMD_CPUID_SVM_NRIP_SAVE)) {
199 printf("SVM: NRIP Save feature not available.\n");
207 svm_enable(void *arg __unused)
211 efer = rdmsr(MSR_EFER);
213 wrmsr(MSR_EFER, efer);
215 wrmsr(MSR_VM_HSAVE_PA, vtophys(hsave[curcpu]));
219 * Return 1 if SVM is enabled on this processor and 0 otherwise.
226 /* Section 15.4 Enabling SVM from APM2. */
227 if ((amd_feature2 & AMDID2_SVM) == 0) {
228 printf("SVM: not available.\n");
232 msr = rdmsr(MSR_VM_CR);
233 if ((msr & VM_CR_SVMDIS) != 0) {
234 printf("SVM: disabled by BIOS.\n");
246 if (!svm_available())
249 error = check_svm_features();
253 vmcb_clean &= VMCB_CACHE_DEFAULT;
255 for (cpu = 0; cpu < MAXCPU; cpu++) {
257 * Initialize the host ASIDs to their "highest" valid values.
259 * The next ASID allocation will rollover both 'gen' and 'num'
260 * and start off the sequence at {1,1}.
262 asid[cpu].gen = ~0UL;
263 asid[cpu].num = nasid - 1;
267 svm_npt_init(ipinum);
269 /* Enable SVM on all CPUs */
270 smp_rendezvous(NULL, svm_enable, NULL, NULL);
282 #ifdef BHYVE_SNAPSHOT
284 svm_set_tsc_offset(struct svm_softc *sc, int vcpu, uint64_t offset)
287 struct vmcb_ctrl *ctrl;
289 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
290 ctrl->tsc_offset = offset;
292 svm_set_dirty(sc, vcpu, VMCB_CACHE_I);
293 VCPU_CTR1(sc->vm, vcpu, "tsc offset changed to %#lx", offset);
295 error = vm_set_tsc_offset(sc->vm, vcpu, offset);
301 /* Pentium compatible MSRs */
302 #define MSR_PENTIUM_START 0
303 #define MSR_PENTIUM_END 0x1FFF
304 /* AMD 6th generation and Intel compatible MSRs */
305 #define MSR_AMD6TH_START 0xC0000000UL
306 #define MSR_AMD6TH_END 0xC0001FFFUL
307 /* AMD 7th and 8th generation compatible MSRs */
308 #define MSR_AMD7TH_START 0xC0010000UL
309 #define MSR_AMD7TH_END 0xC0011FFFUL
312 * Get the index and bit position for a MSR in permission bitmap.
313 * Two bits are used for each MSR: lower bit for read and higher bit for write.
316 svm_msr_index(uint64_t msr, int *index, int *bit)
321 *bit = (msr % 4) * 2;
324 if (msr >= MSR_PENTIUM_START && msr <= MSR_PENTIUM_END) {
329 base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1);
330 if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) {
331 off = (msr - MSR_AMD6TH_START);
332 *index = (off + base) / 4;
336 base += (MSR_AMD6TH_END - MSR_AMD6TH_START + 1);
337 if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) {
338 off = (msr - MSR_AMD7TH_START);
339 *index = (off + base) / 4;
347 * Allow vcpu to read or write the 'msr' without trapping into the hypervisor.
350 svm_msr_perm(uint8_t *perm_bitmap, uint64_t msr, bool read, bool write)
352 int index, bit, error;
354 error = svm_msr_index(msr, &index, &bit);
355 KASSERT(error == 0, ("%s: invalid msr %#lx", __func__, msr));
356 KASSERT(index >= 0 && index < SVM_MSR_BITMAP_SIZE,
357 ("%s: invalid index %d for msr %#lx", __func__, index, msr));
358 KASSERT(bit >= 0 && bit <= 6, ("%s: invalid bit position %d "
359 "msr %#lx", __func__, bit, msr));
362 perm_bitmap[index] &= ~(1UL << bit);
365 perm_bitmap[index] &= ~(2UL << bit);
369 svm_msr_rw_ok(uint8_t *perm_bitmap, uint64_t msr)
372 svm_msr_perm(perm_bitmap, msr, true, true);
376 svm_msr_rd_ok(uint8_t *perm_bitmap, uint64_t msr)
379 svm_msr_perm(perm_bitmap, msr, true, false);
383 svm_get_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask)
385 struct vmcb_ctrl *ctrl;
387 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx));
389 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
390 return (ctrl->intercept[idx] & bitmask ? 1 : 0);
394 svm_set_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask,
397 struct vmcb_ctrl *ctrl;
400 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx));
402 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
403 oldval = ctrl->intercept[idx];
406 ctrl->intercept[idx] |= bitmask;
408 ctrl->intercept[idx] &= ~bitmask;
410 if (ctrl->intercept[idx] != oldval) {
411 svm_set_dirty(sc, vcpu, VMCB_CACHE_I);
412 VCPU_CTR3(sc->vm, vcpu, "intercept[%d] modified "
413 "from %#x to %#x", idx, oldval, ctrl->intercept[idx]);
418 svm_disable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask)
421 svm_set_intercept(sc, vcpu, off, bitmask, 0);
425 svm_enable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask)
428 svm_set_intercept(sc, vcpu, off, bitmask, 1);
432 vmcb_init(struct svm_softc *sc, int vcpu, uint64_t iopm_base_pa,
433 uint64_t msrpm_base_pa, uint64_t np_pml4)
435 struct vmcb_ctrl *ctrl;
436 struct vmcb_state *state;
440 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
441 state = svm_get_vmcb_state(sc, vcpu);
443 ctrl->iopm_base_pa = iopm_base_pa;
444 ctrl->msrpm_base_pa = msrpm_base_pa;
446 /* Enable nested paging */
448 ctrl->n_cr3 = np_pml4;
451 * Intercept accesses to the control registers that are not shadowed
452 * in the VMCB - i.e. all except cr0, cr2, cr3, cr4 and cr8.
454 for (n = 0; n < 16; n++) {
455 mask = (BIT(n) << 16) | BIT(n);
456 if (n == 0 || n == 2 || n == 3 || n == 4 || n == 8)
457 svm_disable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask);
459 svm_enable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask);
463 * Intercept everything when tracing guest exceptions otherwise
464 * just intercept machine check exception.
466 if (vcpu_trace_exceptions(sc->vm, vcpu)) {
467 for (n = 0; n < 32; n++) {
469 * Skip unimplemented vectors in the exception bitmap.
471 if (n == 2 || n == 9) {
474 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(n));
477 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(IDT_MC));
480 /* Intercept various events (for e.g. I/O, MSR and CPUID accesses) */
481 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IO);
482 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_MSR);
483 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_CPUID);
484 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INTR);
485 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INIT);
486 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_NMI);
487 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SMI);
488 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SHUTDOWN);
489 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
490 VMCB_INTCPT_FERR_FREEZE);
491 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INVD);
492 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INVLPGA);
494 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MONITOR);
495 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MWAIT);
498 * Intercept SVM instructions since AMD enables them in guests otherwise.
499 * Non-intercepted VMMCALL causes #UD, skip it.
501 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMLOAD);
502 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMSAVE);
503 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_STGI);
504 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_CLGI);
505 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_SKINIT);
506 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_ICEBP);
509 * From section "Canonicalization and Consistency Checks" in APMv2
510 * the VMRUN intercept bit must be set to pass the consistency check.
512 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMRUN);
515 * The ASID will be set to a non-zero value just before VMRUN.
520 * Section 15.21.1, Interrupt Masking in EFLAGS
521 * Section 15.21.2, Virtualizing APIC.TPR
523 * This must be set for %rflag and %cr8 isolation of guest and host.
525 ctrl->v_intr_masking = 1;
527 /* Enable Last Branch Record aka LBR for debugging */
528 ctrl->lbr_virt_en = 1;
529 state->dbgctl = BIT(0);
531 /* EFER_SVM must always be set when the guest is executing */
532 state->efer = EFER_SVM;
534 /* Set up the PAT to power-on state */
535 state->g_pat = PAT_VALUE(0, PAT_WRITE_BACK) |
536 PAT_VALUE(1, PAT_WRITE_THROUGH) |
537 PAT_VALUE(2, PAT_UNCACHED) |
538 PAT_VALUE(3, PAT_UNCACHEABLE) |
539 PAT_VALUE(4, PAT_WRITE_BACK) |
540 PAT_VALUE(5, PAT_WRITE_THROUGH) |
541 PAT_VALUE(6, PAT_UNCACHED) |
542 PAT_VALUE(7, PAT_UNCACHEABLE);
544 /* Set up DR6/7 to power-on state */
545 state->dr6 = DBREG_DR6_RESERVED1;
546 state->dr7 = DBREG_DR7_RESERVED1;
550 * Initialize a virtual machine.
553 svm_vminit(struct vm *vm, pmap_t pmap)
555 struct svm_softc *svm_sc;
556 struct svm_vcpu *vcpu;
557 vm_paddr_t msrpm_pa, iopm_pa, pml4_pa;
561 svm_sc = malloc(sizeof (*svm_sc), M_SVM, M_WAITOK | M_ZERO);
562 if (((uintptr_t)svm_sc & PAGE_MASK) != 0)
563 panic("malloc of svm_softc not aligned on page boundary");
565 svm_sc->msr_bitmap = contigmalloc(SVM_MSR_BITMAP_SIZE, M_SVM,
566 M_WAITOK, 0, ~(vm_paddr_t)0, PAGE_SIZE, 0);
567 if (svm_sc->msr_bitmap == NULL)
568 panic("contigmalloc of SVM MSR bitmap failed");
569 svm_sc->iopm_bitmap = contigmalloc(SVM_IO_BITMAP_SIZE, M_SVM,
570 M_WAITOK, 0, ~(vm_paddr_t)0, PAGE_SIZE, 0);
571 if (svm_sc->iopm_bitmap == NULL)
572 panic("contigmalloc of SVM IO bitmap failed");
575 svm_sc->nptp = (vm_offset_t)vtophys(pmap->pm_pmltop);
578 * Intercept read and write accesses to all MSRs.
580 memset(svm_sc->msr_bitmap, 0xFF, SVM_MSR_BITMAP_SIZE);
583 * Access to the following MSRs is redirected to the VMCB when the
584 * guest is executing. Therefore it is safe to allow the guest to
585 * read/write these MSRs directly without hypervisor involvement.
587 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_GSBASE);
588 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_FSBASE);
589 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_KGSBASE);
591 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_STAR);
592 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_LSTAR);
593 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_CSTAR);
594 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SF_MASK);
595 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_CS_MSR);
596 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_ESP_MSR);
597 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_EIP_MSR);
598 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_PAT);
600 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_TSC);
603 * Intercept writes to make sure that the EFER_SVM bit is not cleared.
605 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_EFER);
607 /* Intercept access to all I/O ports. */
608 memset(svm_sc->iopm_bitmap, 0xFF, SVM_IO_BITMAP_SIZE);
610 iopm_pa = vtophys(svm_sc->iopm_bitmap);
611 msrpm_pa = vtophys(svm_sc->msr_bitmap);
612 pml4_pa = svm_sc->nptp;
613 maxcpus = vm_get_maxcpus(svm_sc->vm);
614 for (i = 0; i < maxcpus; i++) {
615 vcpu = svm_get_vcpu(svm_sc, i);
617 vcpu->lastcpu = NOCPU;
618 vcpu->vmcb_pa = vtophys(&vcpu->vmcb);
619 vmcb_init(svm_sc, i, iopm_pa, msrpm_pa, pml4_pa);
620 svm_msr_guest_init(svm_sc, i);
626 * Collateral for a generic SVM VM-exit.
629 vm_exit_svm(struct vm_exit *vme, uint64_t code, uint64_t info1, uint64_t info2)
632 vme->exitcode = VM_EXITCODE_SVM;
633 vme->u.svm.exitcode = code;
634 vme->u.svm.exitinfo1 = info1;
635 vme->u.svm.exitinfo2 = info2;
639 svm_cpl(struct vmcb_state *state)
644 * "Retrieve the CPL from the CPL field in the VMCB, not
645 * from any segment DPL"
650 static enum vm_cpu_mode
651 svm_vcpu_mode(struct vmcb *vmcb)
653 struct vmcb_segment seg;
654 struct vmcb_state *state;
657 state = &vmcb->state;
659 if (state->efer & EFER_LMA) {
660 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg);
661 KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__,
665 * Section 4.8.1 for APM2, check if Code Segment has
666 * Long attribute set in descriptor.
668 if (seg.attrib & VMCB_CS_ATTRIB_L)
669 return (CPU_MODE_64BIT);
671 return (CPU_MODE_COMPATIBILITY);
672 } else if (state->cr0 & CR0_PE) {
673 return (CPU_MODE_PROTECTED);
675 return (CPU_MODE_REAL);
679 static enum vm_paging_mode
680 svm_paging_mode(uint64_t cr0, uint64_t cr4, uint64_t efer)
683 if ((cr0 & CR0_PG) == 0)
684 return (PAGING_MODE_FLAT);
685 if ((cr4 & CR4_PAE) == 0)
686 return (PAGING_MODE_32);
688 return (PAGING_MODE_64);
690 return (PAGING_MODE_PAE);
694 * ins/outs utility routines
697 svm_inout_str_index(struct svm_regctx *regs, int in)
701 val = in ? regs->sctx_rdi : regs->sctx_rsi;
707 svm_inout_str_count(struct svm_regctx *regs, int rep)
711 val = rep ? regs->sctx_rcx : 1;
717 svm_inout_str_seginfo(struct svm_softc *svm_sc, int vcpu, int64_t info1,
718 int in, struct vm_inout_str *vis)
723 vis->seg_name = VM_REG_GUEST_ES;
725 /* The segment field has standard encoding */
726 s = (info1 >> 10) & 0x7;
727 vis->seg_name = vm_segment_name(s);
730 error = vmcb_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc);
731 KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error));
735 svm_inout_str_addrsize(uint64_t info1)
739 size = (info1 >> 7) & 0x7;
742 return (2); /* 16 bit */
744 return (4); /* 32 bit */
746 return (8); /* 64 bit */
748 panic("%s: invalid size encoding %d", __func__, size);
753 svm_paging_info(struct vmcb *vmcb, struct vm_guest_paging *paging)
755 struct vmcb_state *state;
757 state = &vmcb->state;
758 paging->cr3 = state->cr3;
759 paging->cpl = svm_cpl(state);
760 paging->cpu_mode = svm_vcpu_mode(vmcb);
761 paging->paging_mode = svm_paging_mode(state->cr0, state->cr4,
768 * Handle guest I/O intercept.
771 svm_handle_io(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit)
773 struct vmcb_ctrl *ctrl;
774 struct vmcb_state *state;
775 struct svm_regctx *regs;
776 struct vm_inout_str *vis;
780 state = svm_get_vmcb_state(svm_sc, vcpu);
781 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu);
782 regs = svm_get_guest_regctx(svm_sc, vcpu);
784 info1 = ctrl->exitinfo1;
785 inout_string = info1 & BIT(2) ? 1 : 0;
788 * The effective segment number in EXITINFO1[12:10] is populated
789 * only if the processor has the DecodeAssist capability.
791 * XXX this is not specified explicitly in APMv2 but can be verified
794 if (inout_string && !decode_assist())
797 vmexit->exitcode = VM_EXITCODE_INOUT;
798 vmexit->u.inout.in = (info1 & BIT(0)) ? 1 : 0;
799 vmexit->u.inout.string = inout_string;
800 vmexit->u.inout.rep = (info1 & BIT(3)) ? 1 : 0;
801 vmexit->u.inout.bytes = (info1 >> 4) & 0x7;
802 vmexit->u.inout.port = (uint16_t)(info1 >> 16);
803 vmexit->u.inout.eax = (uint32_t)(state->rax);
806 vmexit->exitcode = VM_EXITCODE_INOUT_STR;
807 vis = &vmexit->u.inout_str;
808 svm_paging_info(svm_get_vmcb(svm_sc, vcpu), &vis->paging);
809 vis->rflags = state->rflags;
810 vis->cr0 = state->cr0;
811 vis->index = svm_inout_str_index(regs, vmexit->u.inout.in);
812 vis->count = svm_inout_str_count(regs, vmexit->u.inout.rep);
813 vis->addrsize = svm_inout_str_addrsize(info1);
814 svm_inout_str_seginfo(svm_sc, vcpu, info1,
815 vmexit->u.inout.in, vis);
822 npf_fault_type(uint64_t exitinfo1)
825 if (exitinfo1 & VMCB_NPF_INFO1_W)
826 return (VM_PROT_WRITE);
827 else if (exitinfo1 & VMCB_NPF_INFO1_ID)
828 return (VM_PROT_EXECUTE);
830 return (VM_PROT_READ);
834 svm_npf_emul_fault(uint64_t exitinfo1)
837 if (exitinfo1 & VMCB_NPF_INFO1_ID) {
841 if (exitinfo1 & VMCB_NPF_INFO1_GPT) {
845 if ((exitinfo1 & VMCB_NPF_INFO1_GPA) == 0) {
853 svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit)
855 struct vm_guest_paging *paging;
856 struct vmcb_segment seg;
857 struct vmcb_ctrl *ctrl;
862 paging = &vmexit->u.inst_emul.paging;
864 vmexit->exitcode = VM_EXITCODE_INST_EMUL;
865 vmexit->u.inst_emul.gpa = gpa;
866 vmexit->u.inst_emul.gla = VIE_INVALID_GLA;
867 svm_paging_info(vmcb, paging);
869 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg);
870 KASSERT(error == 0, ("%s: vmcb_seg(CS) error %d", __func__, error));
872 switch(paging->cpu_mode) {
874 vmexit->u.inst_emul.cs_base = seg.base;
875 vmexit->u.inst_emul.cs_d = 0;
877 case CPU_MODE_PROTECTED:
878 case CPU_MODE_COMPATIBILITY:
879 vmexit->u.inst_emul.cs_base = seg.base;
882 * Section 4.8.1 of APM2, Default Operand Size or D bit.
884 vmexit->u.inst_emul.cs_d = (seg.attrib & VMCB_CS_ATTRIB_D) ?
888 vmexit->u.inst_emul.cs_base = 0;
889 vmexit->u.inst_emul.cs_d = 0;
894 * Copy the instruction bytes into 'vie' if available.
896 if (decode_assist() && !disable_npf_assist) {
897 inst_len = ctrl->inst_len;
898 inst_bytes = ctrl->inst_bytes;
903 vie_init(&vmexit->u.inst_emul.vie, inst_bytes, inst_len);
908 intrtype_to_str(int intr_type)
911 case VMCB_EVENTINJ_TYPE_INTR:
913 case VMCB_EVENTINJ_TYPE_NMI:
915 case VMCB_EVENTINJ_TYPE_INTn:
917 case VMCB_EVENTINJ_TYPE_EXCEPTION:
918 return ("exception");
920 panic("%s: unknown intr_type %d", __func__, intr_type);
926 * Inject an event to vcpu as described in section 15.20, "Event injection".
929 svm_eventinject(struct svm_softc *sc, int vcpu, int intr_type, int vector,
930 uint32_t error, bool ec_valid)
932 struct vmcb_ctrl *ctrl;
934 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
936 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0,
937 ("%s: event already pending %#lx", __func__, ctrl->eventinj));
939 KASSERT(vector >=0 && vector <= 255, ("%s: invalid vector %d",
943 case VMCB_EVENTINJ_TYPE_INTR:
944 case VMCB_EVENTINJ_TYPE_NMI:
945 case VMCB_EVENTINJ_TYPE_INTn:
947 case VMCB_EVENTINJ_TYPE_EXCEPTION:
948 if (vector >= 0 && vector <= 31 && vector != 2)
952 panic("%s: invalid intr_type/vector: %d/%d", __func__,
955 ctrl->eventinj = vector | (intr_type << 8) | VMCB_EVENTINJ_VALID;
957 ctrl->eventinj |= VMCB_EVENTINJ_EC_VALID;
958 ctrl->eventinj |= (uint64_t)error << 32;
959 VCPU_CTR3(sc->vm, vcpu, "Injecting %s at vector %d errcode %#x",
960 intrtype_to_str(intr_type), vector, error);
962 VCPU_CTR2(sc->vm, vcpu, "Injecting %s at vector %d",
963 intrtype_to_str(intr_type), vector);
968 svm_update_virqinfo(struct svm_softc *sc, int vcpu)
971 struct vlapic *vlapic;
972 struct vmcb_ctrl *ctrl;
975 vlapic = vm_lapic(vm, vcpu);
976 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
978 /* Update %cr8 in the emulated vlapic */
979 vlapic_set_cr8(vlapic, ctrl->v_tpr);
981 /* Virtual interrupt injection is not used. */
982 KASSERT(ctrl->v_intr_vector == 0, ("%s: invalid "
983 "v_intr_vector %d", __func__, ctrl->v_intr_vector));
987 svm_save_intinfo(struct svm_softc *svm_sc, int vcpu)
989 struct vmcb_ctrl *ctrl;
992 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu);
993 intinfo = ctrl->exitintinfo;
994 if (!VMCB_EXITINTINFO_VALID(intinfo))
998 * From APMv2, Section "Intercepts during IDT interrupt delivery"
1000 * If a #VMEXIT happened during event delivery then record the event
1001 * that was being delivered.
1003 VCPU_CTR2(svm_sc->vm, vcpu, "SVM:Pending INTINFO(0x%lx), vector=%d.\n",
1004 intinfo, VMCB_EXITINTINFO_VECTOR(intinfo));
1005 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_EXITINTINFO, 1);
1006 vm_exit_intinfo(svm_sc->vm, vcpu, intinfo);
1011 vintr_intercept_enabled(struct svm_softc *sc, int vcpu)
1014 return (svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
1015 VMCB_INTCPT_VINTR));
1019 static __inline void
1020 enable_intr_window_exiting(struct svm_softc *sc, int vcpu)
1022 struct vmcb_ctrl *ctrl;
1024 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1026 if (ctrl->v_irq && ctrl->v_intr_vector == 0) {
1027 KASSERT(ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__));
1028 KASSERT(vintr_intercept_enabled(sc, vcpu),
1029 ("%s: vintr intercept should be enabled", __func__));
1033 VCPU_CTR0(sc->vm, vcpu, "Enable intr window exiting");
1035 ctrl->v_ign_tpr = 1;
1036 ctrl->v_intr_vector = 0;
1037 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
1038 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR);
1041 static __inline void
1042 disable_intr_window_exiting(struct svm_softc *sc, int vcpu)
1044 struct vmcb_ctrl *ctrl;
1046 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1048 if (!ctrl->v_irq && ctrl->v_intr_vector == 0) {
1049 KASSERT(!vintr_intercept_enabled(sc, vcpu),
1050 ("%s: vintr intercept should be disabled", __func__));
1054 VCPU_CTR0(sc->vm, vcpu, "Disable intr window exiting");
1056 ctrl->v_intr_vector = 0;
1057 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
1058 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR);
1062 svm_modify_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t val)
1064 struct vmcb_ctrl *ctrl;
1067 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1068 oldval = ctrl->intr_shadow;
1069 newval = val ? 1 : 0;
1070 if (newval != oldval) {
1071 ctrl->intr_shadow = newval;
1072 VCPU_CTR1(sc->vm, vcpu, "Setting intr_shadow to %d", newval);
1078 svm_get_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t *val)
1080 struct vmcb_ctrl *ctrl;
1082 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1083 *val = ctrl->intr_shadow;
1088 * Once an NMI is injected it blocks delivery of further NMIs until the handler
1089 * executes an IRET. The IRET intercept is enabled when an NMI is injected to
1090 * to track when the vcpu is done handling the NMI.
1093 nmi_blocked(struct svm_softc *sc, int vcpu)
1097 blocked = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
1103 enable_nmi_blocking(struct svm_softc *sc, int vcpu)
1106 KASSERT(!nmi_blocked(sc, vcpu), ("vNMI already blocked"));
1107 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking enabled");
1108 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET);
1112 clear_nmi_blocking(struct svm_softc *sc, int vcpu)
1116 KASSERT(nmi_blocked(sc, vcpu), ("vNMI already unblocked"));
1117 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking cleared");
1119 * When the IRET intercept is cleared the vcpu will attempt to execute
1120 * the "iret" when it runs next. However, it is possible to inject
1121 * another NMI into the vcpu before the "iret" has actually executed.
1123 * For e.g. if the "iret" encounters a #NPF when accessing the stack
1124 * it will trap back into the hypervisor. If an NMI is pending for
1125 * the vcpu it will be injected into the guest.
1127 * XXX this needs to be fixed
1129 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET);
1132 * Set 'intr_shadow' to prevent an NMI from being injected on the
1135 error = svm_modify_intr_shadow(sc, vcpu, 1);
1136 KASSERT(!error, ("%s: error %d setting intr_shadow", __func__, error));
1139 #define EFER_MBZ_BITS 0xFFFFFFFFFFFF0200UL
1142 svm_write_efer(struct svm_softc *sc, int vcpu, uint64_t newval, bool *retu)
1144 struct vm_exit *vme;
1145 struct vmcb_state *state;
1146 uint64_t changed, lma, oldval;
1149 state = svm_get_vmcb_state(sc, vcpu);
1151 oldval = state->efer;
1152 VCPU_CTR2(sc->vm, vcpu, "wrmsr(efer) %#lx/%#lx", oldval, newval);
1154 newval &= ~0xFE; /* clear the Read-As-Zero (RAZ) bits */
1155 changed = oldval ^ newval;
1157 if (newval & EFER_MBZ_BITS)
1160 /* APMv2 Table 14-5 "Long-Mode Consistency Checks" */
1161 if (changed & EFER_LME) {
1162 if (state->cr0 & CR0_PG)
1166 /* EFER.LMA = EFER.LME & CR0.PG */
1167 if ((newval & EFER_LME) != 0 && (state->cr0 & CR0_PG) != 0)
1172 if ((newval & EFER_LMA) != lma)
1175 if (newval & EFER_NXE) {
1176 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_NO_EXECUTE))
1181 * XXX bhyve does not enforce segment limits in 64-bit mode. Until
1182 * this is fixed flag guest attempt to set EFER_LMSLE as an error.
1184 if (newval & EFER_LMSLE) {
1185 vme = vm_exitinfo(sc->vm, vcpu);
1186 vm_exit_svm(vme, VMCB_EXIT_MSR, 1, 0);
1191 if (newval & EFER_FFXSR) {
1192 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_FFXSR))
1196 if (newval & EFER_TCE) {
1197 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_TCE))
1201 error = svm_setreg(sc, vcpu, VM_REG_GUEST_EFER, newval);
1202 KASSERT(error == 0, ("%s: error %d updating efer", __func__, error));
1205 vm_inject_gp(sc->vm, vcpu);
1210 emulate_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val,
1216 error = lapic_wrmsr(sc->vm, vcpu, num, val, retu);
1217 else if (num == MSR_EFER)
1218 error = svm_write_efer(sc, vcpu, val, retu);
1220 error = svm_wrmsr(sc, vcpu, num, val, retu);
1226 emulate_rdmsr(struct svm_softc *sc, int vcpu, u_int num, bool *retu)
1228 struct vmcb_state *state;
1229 struct svm_regctx *ctx;
1234 error = lapic_rdmsr(sc->vm, vcpu, num, &result, retu);
1236 error = svm_rdmsr(sc, vcpu, num, &result, retu);
1239 state = svm_get_vmcb_state(sc, vcpu);
1240 ctx = svm_get_guest_regctx(sc, vcpu);
1241 state->rax = result & 0xffffffff;
1242 ctx->sctx_rdx = result >> 32;
1250 exit_reason_to_str(uint64_t reason)
1253 static char reasonbuf[32];
1254 static const struct {
1258 { .reason = VMCB_EXIT_INVALID, .str = "invalvmcb" },
1259 { .reason = VMCB_EXIT_SHUTDOWN, .str = "shutdown" },
1260 { .reason = VMCB_EXIT_NPF, .str = "nptfault" },
1261 { .reason = VMCB_EXIT_PAUSE, .str = "pause" },
1262 { .reason = VMCB_EXIT_HLT, .str = "hlt" },
1263 { .reason = VMCB_EXIT_CPUID, .str = "cpuid" },
1264 { .reason = VMCB_EXIT_IO, .str = "inout" },
1265 { .reason = VMCB_EXIT_MC, .str = "mchk" },
1266 { .reason = VMCB_EXIT_INTR, .str = "extintr" },
1267 { .reason = VMCB_EXIT_NMI, .str = "nmi" },
1268 { .reason = VMCB_EXIT_VINTR, .str = "vintr" },
1269 { .reason = VMCB_EXIT_MSR, .str = "msr" },
1270 { .reason = VMCB_EXIT_IRET, .str = "iret" },
1271 { .reason = VMCB_EXIT_MONITOR, .str = "monitor" },
1272 { .reason = VMCB_EXIT_MWAIT, .str = "mwait" },
1273 { .reason = VMCB_EXIT_VMRUN, .str = "vmrun" },
1274 { .reason = VMCB_EXIT_VMMCALL, .str = "vmmcall" },
1275 { .reason = VMCB_EXIT_VMLOAD, .str = "vmload" },
1276 { .reason = VMCB_EXIT_VMSAVE, .str = "vmsave" },
1277 { .reason = VMCB_EXIT_STGI, .str = "stgi" },
1278 { .reason = VMCB_EXIT_CLGI, .str = "clgi" },
1279 { .reason = VMCB_EXIT_SKINIT, .str = "skinit" },
1280 { .reason = VMCB_EXIT_ICEBP, .str = "icebp" },
1281 { .reason = VMCB_EXIT_INVD, .str = "invd" },
1282 { .reason = VMCB_EXIT_INVLPGA, .str = "invlpga" },
1285 for (i = 0; i < nitems(reasons); i++) {
1286 if (reasons[i].reason == reason)
1287 return (reasons[i].str);
1289 snprintf(reasonbuf, sizeof(reasonbuf), "%#lx", reason);
1295 * From section "State Saved on Exit" in APMv2: nRIP is saved for all #VMEXITs
1296 * that are due to instruction intercepts as well as MSR and IOIO intercepts
1297 * and exceptions caused by INT3, INTO and BOUND instructions.
1299 * Return 1 if the nRIP is valid and 0 otherwise.
1302 nrip_valid(uint64_t exitcode)
1305 case 0x00 ... 0x0F: /* read of CR0 through CR15 */
1306 case 0x10 ... 0x1F: /* write of CR0 through CR15 */
1307 case 0x20 ... 0x2F: /* read of DR0 through DR15 */
1308 case 0x30 ... 0x3F: /* write of DR0 through DR15 */
1309 case 0x43: /* INT3 */
1310 case 0x44: /* INTO */
1311 case 0x45: /* BOUND */
1312 case 0x65 ... 0x7C: /* VMEXIT_CR0_SEL_WRITE ... VMEXIT_MSR */
1313 case 0x80 ... 0x8D: /* VMEXIT_VMRUN ... VMEXIT_XSETBV */
1321 svm_vmexit(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit)
1324 struct vmcb_state *state;
1325 struct vmcb_ctrl *ctrl;
1326 struct svm_regctx *ctx;
1327 uint64_t code, info1, info2, val;
1328 uint32_t eax, ecx, edx;
1329 int error, errcode_valid, handled, idtvec, reflect;
1332 ctx = svm_get_guest_regctx(svm_sc, vcpu);
1333 vmcb = svm_get_vmcb(svm_sc, vcpu);
1334 state = &vmcb->state;
1338 code = ctrl->exitcode;
1339 info1 = ctrl->exitinfo1;
1340 info2 = ctrl->exitinfo2;
1342 vmexit->exitcode = VM_EXITCODE_BOGUS;
1343 vmexit->rip = state->rip;
1344 vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0;
1346 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_COUNT, 1);
1349 * #VMEXIT(INVALID) needs to be handled early because the VMCB is
1350 * in an inconsistent state and can trigger assertions that would
1351 * never happen otherwise.
1353 if (code == VMCB_EXIT_INVALID) {
1354 vm_exit_svm(vmexit, code, info1, info2);
1358 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event "
1359 "injection valid bit is set %#lx", __func__, ctrl->eventinj));
1361 KASSERT(vmexit->inst_length >= 0 && vmexit->inst_length <= 15,
1362 ("invalid inst_length %d: code (%#lx), info1 (%#lx), info2 (%#lx)",
1363 vmexit->inst_length, code, info1, info2));
1365 svm_update_virqinfo(svm_sc, vcpu);
1366 svm_save_intinfo(svm_sc, vcpu);
1369 case VMCB_EXIT_IRET:
1371 * Restart execution at "iret" but with the intercept cleared.
1373 vmexit->inst_length = 0;
1374 clear_nmi_blocking(svm_sc, vcpu);
1377 case VMCB_EXIT_VINTR: /* interrupt window exiting */
1378 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_VINTR, 1);
1381 case VMCB_EXIT_INTR: /* external interrupt */
1382 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXTINT, 1);
1385 case VMCB_EXIT_NMI: /* external NMI */
1389 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXCEPTION, 1);
1391 idtvec = code - 0x40;
1395 * Call the machine check handler by hand. Also don't
1396 * reflect the machine check back into the guest.
1399 VCPU_CTR0(svm_sc->vm, vcpu, "Vectoring to MCE handler");
1400 __asm __volatile("int $18");
1403 error = svm_setreg(svm_sc, vcpu, VM_REG_GUEST_CR2,
1405 KASSERT(error == 0, ("%s: error %d updating cr2",
1425 * The 'nrip' field is populated for INT3, INTO and
1426 * BOUND exceptions and this also implies that
1427 * 'inst_length' is non-zero.
1429 * Reset 'inst_length' to zero so the guest %rip at
1430 * event injection is identical to what it was when
1431 * the exception originally happened.
1433 VCPU_CTR2(svm_sc->vm, vcpu, "Reset inst_length from %d "
1434 "to zero before injecting exception %d",
1435 vmexit->inst_length, idtvec);
1436 vmexit->inst_length = 0;
1443 KASSERT(vmexit->inst_length == 0, ("invalid inst_length (%d) "
1444 "when reflecting exception %d into guest",
1445 vmexit->inst_length, idtvec));
1448 /* Reflect the exception back into the guest */
1449 VCPU_CTR2(svm_sc->vm, vcpu, "Reflecting exception "
1450 "%d/%#x into the guest", idtvec, (int)info1);
1451 error = vm_inject_exception(svm_sc->vm, vcpu, idtvec,
1452 errcode_valid, info1, 0);
1453 KASSERT(error == 0, ("%s: vm_inject_exception error %d",
1458 case VMCB_EXIT_MSR: /* MSR access. */
1460 ecx = ctx->sctx_rcx;
1461 edx = ctx->sctx_rdx;
1465 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_WRMSR, 1);
1466 val = (uint64_t)edx << 32 | eax;
1467 VCPU_CTR2(svm_sc->vm, vcpu, "wrmsr %#x val %#lx",
1469 if (emulate_wrmsr(svm_sc, vcpu, ecx, val, &retu)) {
1470 vmexit->exitcode = VM_EXITCODE_WRMSR;
1471 vmexit->u.msr.code = ecx;
1472 vmexit->u.msr.wval = val;
1476 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
1477 ("emulate_wrmsr retu with bogus exitcode"));
1480 VCPU_CTR1(svm_sc->vm, vcpu, "rdmsr %#x", ecx);
1481 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_RDMSR, 1);
1482 if (emulate_rdmsr(svm_sc, vcpu, ecx, &retu)) {
1483 vmexit->exitcode = VM_EXITCODE_RDMSR;
1484 vmexit->u.msr.code = ecx;
1488 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
1489 ("emulate_rdmsr retu with bogus exitcode"));
1494 handled = svm_handle_io(svm_sc, vcpu, vmexit);
1495 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INOUT, 1);
1497 case VMCB_EXIT_CPUID:
1498 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_CPUID, 1);
1499 handled = x86_emulate_cpuid(svm_sc->vm, vcpu,
1500 (uint32_t *)&state->rax,
1501 (uint32_t *)&ctx->sctx_rbx,
1502 (uint32_t *)&ctx->sctx_rcx,
1503 (uint32_t *)&ctx->sctx_rdx);
1506 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_HLT, 1);
1507 vmexit->exitcode = VM_EXITCODE_HLT;
1508 vmexit->u.hlt.rflags = state->rflags;
1510 case VMCB_EXIT_PAUSE:
1511 vmexit->exitcode = VM_EXITCODE_PAUSE;
1512 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_PAUSE, 1);
1515 /* EXITINFO2 contains the faulting guest physical address */
1516 if (info1 & VMCB_NPF_INFO1_RSV) {
1517 VCPU_CTR2(svm_sc->vm, vcpu, "nested page fault with "
1518 "reserved bits set: info1(%#lx) info2(%#lx)",
1520 } else if (vm_mem_allocated(svm_sc->vm, vcpu, info2)) {
1521 vmexit->exitcode = VM_EXITCODE_PAGING;
1522 vmexit->u.paging.gpa = info2;
1523 vmexit->u.paging.fault_type = npf_fault_type(info1);
1524 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_NESTED_FAULT, 1);
1525 VCPU_CTR3(svm_sc->vm, vcpu, "nested page fault "
1526 "on gpa %#lx/%#lx at rip %#lx",
1527 info2, info1, state->rip);
1528 } else if (svm_npf_emul_fault(info1)) {
1529 svm_handle_inst_emul(vmcb, info2, vmexit);
1530 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INST_EMUL, 1);
1531 VCPU_CTR3(svm_sc->vm, vcpu, "inst_emul fault "
1532 "for gpa %#lx/%#lx at rip %#lx",
1533 info2, info1, state->rip);
1536 case VMCB_EXIT_MONITOR:
1537 vmexit->exitcode = VM_EXITCODE_MONITOR;
1539 case VMCB_EXIT_MWAIT:
1540 vmexit->exitcode = VM_EXITCODE_MWAIT;
1542 case VMCB_EXIT_SHUTDOWN:
1543 case VMCB_EXIT_VMRUN:
1544 case VMCB_EXIT_VMMCALL:
1545 case VMCB_EXIT_VMLOAD:
1546 case VMCB_EXIT_VMSAVE:
1547 case VMCB_EXIT_STGI:
1548 case VMCB_EXIT_CLGI:
1549 case VMCB_EXIT_SKINIT:
1550 case VMCB_EXIT_ICEBP:
1551 case VMCB_EXIT_INVD:
1552 case VMCB_EXIT_INVLPGA:
1553 vm_inject_ud(svm_sc->vm, vcpu);
1557 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_UNKNOWN, 1);
1561 VCPU_CTR4(svm_sc->vm, vcpu, "%s %s vmexit at %#lx/%d",
1562 handled ? "handled" : "unhandled", exit_reason_to_str(code),
1563 vmexit->rip, vmexit->inst_length);
1566 vmexit->rip += vmexit->inst_length;
1567 vmexit->inst_length = 0;
1568 state->rip = vmexit->rip;
1570 if (vmexit->exitcode == VM_EXITCODE_BOGUS) {
1572 * If this VM exit was not claimed by anybody then
1573 * treat it as a generic SVM exit.
1575 vm_exit_svm(vmexit, code, info1, info2);
1578 * The exitcode and collateral have been populated.
1579 * The VM exit will be processed further in userland.
1587 svm_inj_intinfo(struct svm_softc *svm_sc, int vcpu)
1591 if (!vm_entry_intinfo(svm_sc->vm, vcpu, &intinfo))
1594 KASSERT(VMCB_EXITINTINFO_VALID(intinfo), ("%s: entry intinfo is not "
1595 "valid: %#lx", __func__, intinfo));
1597 svm_eventinject(svm_sc, vcpu, VMCB_EXITINTINFO_TYPE(intinfo),
1598 VMCB_EXITINTINFO_VECTOR(intinfo),
1599 VMCB_EXITINTINFO_EC(intinfo),
1600 VMCB_EXITINTINFO_EC_VALID(intinfo));
1601 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_INTINFO_INJECTED, 1);
1602 VCPU_CTR1(svm_sc->vm, vcpu, "Injected entry intinfo: %#lx", intinfo);
1606 * Inject event to virtual cpu.
1609 svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic)
1611 struct vmcb_ctrl *ctrl;
1612 struct vmcb_state *state;
1613 struct svm_vcpu *vcpustate;
1615 int vector, need_intr_window;
1618 state = svm_get_vmcb_state(sc, vcpu);
1619 ctrl = svm_get_vmcb_ctrl(sc, vcpu);
1620 vcpustate = svm_get_vcpu(sc, vcpu);
1622 need_intr_window = 0;
1624 if (vcpustate->nextrip != state->rip) {
1625 ctrl->intr_shadow = 0;
1626 VCPU_CTR2(sc->vm, vcpu, "Guest interrupt blocking "
1627 "cleared due to rip change: %#lx/%#lx",
1628 vcpustate->nextrip, state->rip);
1632 * Inject pending events or exceptions for this vcpu.
1634 * An event might be pending because the previous #VMEXIT happened
1635 * during event delivery (i.e. ctrl->exitintinfo).
1637 * An event might also be pending because an exception was injected
1638 * by the hypervisor (e.g. #PF during instruction emulation).
1640 svm_inj_intinfo(sc, vcpu);
1642 /* NMI event has priority over interrupts. */
1643 if (vm_nmi_pending(sc->vm, vcpu)) {
1644 if (nmi_blocked(sc, vcpu)) {
1646 * Can't inject another NMI if the guest has not
1647 * yet executed an "iret" after the last NMI.
1649 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due "
1651 } else if (ctrl->intr_shadow) {
1653 * Can't inject an NMI if the vcpu is in an intr_shadow.
1655 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due to "
1656 "interrupt shadow");
1657 need_intr_window = 1;
1659 } else if (ctrl->eventinj & VMCB_EVENTINJ_VALID) {
1661 * If there is already an exception/interrupt pending
1662 * then defer the NMI until after that.
1664 VCPU_CTR1(sc->vm, vcpu, "Cannot inject NMI due to "
1665 "eventinj %#lx", ctrl->eventinj);
1668 * Use self-IPI to trigger a VM-exit as soon as
1669 * possible after the event injection is completed.
1671 * This works only if the external interrupt exiting
1672 * is at a lower priority than the event injection.
1674 * Although not explicitly specified in APMv2 the
1675 * relative priorities were verified empirically.
1677 ipi_cpu(curcpu, IPI_AST); /* XXX vmm_ipinum? */
1679 vm_nmi_clear(sc->vm, vcpu);
1681 /* Inject NMI, vector number is not used */
1682 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_NMI,
1685 /* virtual NMI blocking is now in effect */
1686 enable_nmi_blocking(sc, vcpu);
1688 VCPU_CTR0(sc->vm, vcpu, "Injecting vNMI");
1692 extint_pending = vm_extint_pending(sc->vm, vcpu);
1693 if (!extint_pending) {
1694 if (!vlapic_pending_intr(vlapic, &vector))
1696 KASSERT(vector >= 16 && vector <= 255,
1697 ("invalid vector %d from local APIC", vector));
1699 /* Ask the legacy pic for a vector to inject */
1700 vatpic_pending_intr(sc->vm, &vector);
1701 KASSERT(vector >= 0 && vector <= 255,
1702 ("invalid vector %d from INTR", vector));
1706 * If the guest has disabled interrupts or is in an interrupt shadow
1707 * then we cannot inject the pending interrupt.
1709 if ((state->rflags & PSL_I) == 0) {
1710 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to "
1711 "rflags %#lx", vector, state->rflags);
1712 need_intr_window = 1;
1716 if (ctrl->intr_shadow) {
1717 VCPU_CTR1(sc->vm, vcpu, "Cannot inject vector %d due to "
1718 "interrupt shadow", vector);
1719 need_intr_window = 1;
1723 if (ctrl->eventinj & VMCB_EVENTINJ_VALID) {
1724 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to "
1725 "eventinj %#lx", vector, ctrl->eventinj);
1726 need_intr_window = 1;
1730 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_INTR, vector, 0, false);
1732 if (!extint_pending) {
1733 vlapic_intr_accepted(vlapic, vector);
1735 vm_extint_clear(sc->vm, vcpu);
1736 vatpic_intr_accepted(sc->vm, vector);
1740 * Force a VM-exit as soon as the vcpu is ready to accept another
1741 * interrupt. This is done because the PIC might have another vector
1742 * that it wants to inject. Also, if the APIC has a pending interrupt
1743 * that was preempted by the ExtInt then it allows us to inject the
1744 * APIC vector as soon as possible.
1746 need_intr_window = 1;
1749 * The guest can modify the TPR by writing to %CR8. In guest mode
1750 * the processor reflects this write to V_TPR without hypervisor
1753 * The guest can also modify the TPR by writing to it via the memory
1754 * mapped APIC page. In this case, the write will be emulated by the
1755 * hypervisor. For this reason V_TPR must be updated before every
1758 v_tpr = vlapic_get_cr8(vlapic);
1759 KASSERT(v_tpr <= 15, ("invalid v_tpr %#x", v_tpr));
1760 if (ctrl->v_tpr != v_tpr) {
1761 VCPU_CTR2(sc->vm, vcpu, "VMCB V_TPR changed from %#x to %#x",
1762 ctrl->v_tpr, v_tpr);
1763 ctrl->v_tpr = v_tpr;
1764 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
1767 if (need_intr_window) {
1769 * We use V_IRQ in conjunction with the VINTR intercept to
1770 * trap into the hypervisor as soon as a virtual interrupt
1773 * Since injected events are not subject to intercept checks
1774 * we need to ensure that the V_IRQ is not actually going to
1775 * be delivered on VM entry. The KASSERT below enforces this.
1777 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 ||
1778 (state->rflags & PSL_I) == 0 || ctrl->intr_shadow,
1779 ("Bogus intr_window_exiting: eventinj (%#lx), "
1780 "intr_shadow (%u), rflags (%#lx)",
1781 ctrl->eventinj, ctrl->intr_shadow, state->rflags));
1782 enable_intr_window_exiting(sc, vcpu);
1784 disable_intr_window_exiting(sc, vcpu);
1788 static __inline void
1789 restore_host_tss(void)
1791 struct system_segment_descriptor *tss_sd;
1794 * The TSS descriptor was in use prior to launching the guest so it
1795 * has been marked busy.
1797 * 'ltr' requires the descriptor to be marked available so change the
1798 * type to "64-bit available TSS".
1800 tss_sd = PCPU_GET(tss);
1801 tss_sd->sd_type = SDT_SYSTSS;
1802 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1806 check_asid(struct svm_softc *sc, int vcpuid, pmap_t pmap, u_int thiscpu)
1808 struct svm_vcpu *vcpustate;
1809 struct vmcb_ctrl *ctrl;
1813 KASSERT(CPU_ISSET(thiscpu, &pmap->pm_active), ("%s: nested pmap not "
1814 "active on cpu %u", __func__, thiscpu));
1816 vcpustate = svm_get_vcpu(sc, vcpuid);
1817 ctrl = svm_get_vmcb_ctrl(sc, vcpuid);
1820 * The TLB entries associated with the vcpu's ASID are not valid
1821 * if either of the following conditions is true:
1823 * 1. The vcpu's ASID generation is different than the host cpu's
1824 * ASID generation. This happens when the vcpu migrates to a new
1825 * host cpu. It can also happen when the number of vcpus executing
1826 * on a host cpu is greater than the number of ASIDs available.
1828 * 2. The pmap generation number is different than the value cached in
1829 * the 'vcpustate'. This happens when the host invalidates pages
1830 * belonging to the guest.
1832 * asidgen eptgen Action
1839 * (a) There is no mismatch in eptgen or ASID generation and therefore
1840 * no further action is needed.
1842 * (b1) If the cpu supports FlushByAsid then the vcpu's ASID is
1843 * retained and the TLB entries associated with this ASID
1844 * are flushed by VMRUN.
1846 * (b2) If the cpu does not support FlushByAsid then a new ASID is
1849 * (c) A new ASID is allocated.
1851 * (d) A new ASID is allocated.
1855 eptgen = pmap->pm_eptgen;
1856 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_NOTHING;
1858 if (vcpustate->asid.gen != asid[thiscpu].gen) {
1859 alloc_asid = true; /* (c) and (d) */
1860 } else if (vcpustate->eptgen != eptgen) {
1861 if (flush_by_asid())
1862 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; /* (b1) */
1864 alloc_asid = true; /* (b2) */
1867 * This is the common case (a).
1869 KASSERT(!alloc_asid, ("ASID allocation not necessary"));
1870 KASSERT(ctrl->tlb_ctrl == VMCB_TLB_FLUSH_NOTHING,
1871 ("Invalid VMCB tlb_ctrl: %#x", ctrl->tlb_ctrl));
1875 if (++asid[thiscpu].num >= nasid) {
1876 asid[thiscpu].num = 1;
1877 if (++asid[thiscpu].gen == 0)
1878 asid[thiscpu].gen = 1;
1880 * If this cpu does not support "flush-by-asid"
1881 * then flush the entire TLB on a generation
1882 * bump. Subsequent ASID allocation in this
1883 * generation can be done without a TLB flush.
1885 if (!flush_by_asid())
1886 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_ALL;
1888 vcpustate->asid.gen = asid[thiscpu].gen;
1889 vcpustate->asid.num = asid[thiscpu].num;
1891 ctrl->asid = vcpustate->asid.num;
1892 svm_set_dirty(sc, vcpuid, VMCB_CACHE_ASID);
1894 * If this cpu supports "flush-by-asid" then the TLB
1895 * was not flushed after the generation bump. The TLB
1896 * is flushed selectively after every new ASID allocation.
1898 if (flush_by_asid())
1899 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST;
1901 vcpustate->eptgen = eptgen;
1903 KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero"));
1904 KASSERT(ctrl->asid == vcpustate->asid.num,
1905 ("ASID mismatch: %u/%u", ctrl->asid, vcpustate->asid.num));
1908 static __inline void
1912 __asm __volatile("clgi");
1915 static __inline void
1919 __asm __volatile("stgi");
1922 static __inline void
1923 svm_dr_enter_guest(struct svm_regctx *gctx)
1926 /* Save host control debug registers. */
1927 gctx->host_dr7 = rdr7();
1928 gctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);
1931 * Disable debugging in DR7 and DEBUGCTL to avoid triggering
1932 * exceptions in the host based on the guest DRx values. The
1933 * guest DR6, DR7, and DEBUGCTL are saved/restored in the
1937 wrmsr(MSR_DEBUGCTLMSR, 0);
1939 /* Save host debug registers. */
1940 gctx->host_dr0 = rdr0();
1941 gctx->host_dr1 = rdr1();
1942 gctx->host_dr2 = rdr2();
1943 gctx->host_dr3 = rdr3();
1944 gctx->host_dr6 = rdr6();
1946 /* Restore guest debug registers. */
1947 load_dr0(gctx->sctx_dr0);
1948 load_dr1(gctx->sctx_dr1);
1949 load_dr2(gctx->sctx_dr2);
1950 load_dr3(gctx->sctx_dr3);
1953 static __inline void
1954 svm_dr_leave_guest(struct svm_regctx *gctx)
1957 /* Save guest debug registers. */
1958 gctx->sctx_dr0 = rdr0();
1959 gctx->sctx_dr1 = rdr1();
1960 gctx->sctx_dr2 = rdr2();
1961 gctx->sctx_dr3 = rdr3();
1964 * Restore host debug registers. Restore DR7 and DEBUGCTL
1967 load_dr0(gctx->host_dr0);
1968 load_dr1(gctx->host_dr1);
1969 load_dr2(gctx->host_dr2);
1970 load_dr3(gctx->host_dr3);
1971 load_dr6(gctx->host_dr6);
1972 wrmsr(MSR_DEBUGCTLMSR, gctx->host_debugctl);
1973 load_dr7(gctx->host_dr7);
1977 * Start vcpu with specified RIP.
1980 svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap,
1981 struct vm_eventinfo *evinfo)
1983 struct svm_regctx *gctx;
1984 struct svm_softc *svm_sc;
1985 struct svm_vcpu *vcpustate;
1986 struct vmcb_state *state;
1987 struct vmcb_ctrl *ctrl;
1988 struct vm_exit *vmexit;
1989 struct vlapic *vlapic;
1998 vcpustate = svm_get_vcpu(svm_sc, vcpu);
1999 state = svm_get_vmcb_state(svm_sc, vcpu);
2000 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu);
2001 vmexit = vm_exitinfo(vm, vcpu);
2002 vlapic = vm_lapic(vm, vcpu);
2004 gctx = svm_get_guest_regctx(svm_sc, vcpu);
2005 vmcb_pa = svm_sc->vcpu[vcpu].vmcb_pa;
2007 if (vcpustate->lastcpu != curcpu) {
2009 * Force new ASID allocation by invalidating the generation.
2011 vcpustate->asid.gen = 0;
2014 * Invalidate the VMCB state cache by marking all fields dirty.
2016 svm_set_dirty(svm_sc, vcpu, 0xffffffff);
2020 * Setting 'vcpustate->lastcpu' here is bit premature because
2021 * we may return from this function without actually executing
2022 * the VMRUN instruction. This could happen if a rendezvous
2023 * or an AST is pending on the first time through the loop.
2025 * This works for now but any new side-effects of vcpu
2026 * migration should take this case into account.
2028 vcpustate->lastcpu = curcpu;
2029 vmm_stat_incr(vm, vcpu, VCPU_MIGRATIONS, 1);
2032 svm_msr_guest_enter(svm_sc, vcpu);
2034 /* Update Guest RIP */
2039 * Disable global interrupts to guarantee atomicity during
2040 * loading of guest state. This includes not only the state
2041 * loaded by the "vmrun" instruction but also software state
2042 * maintained by the hypervisor: suspended and rendezvous
2043 * state, NPT generation number, vlapic interrupts etc.
2047 if (vcpu_suspended(evinfo)) {
2049 vm_exit_suspended(vm, vcpu, state->rip);
2053 if (vcpu_rendezvous_pending(evinfo)) {
2055 vm_exit_rendezvous(vm, vcpu, state->rip);
2059 if (vcpu_reqidle(evinfo)) {
2061 vm_exit_reqidle(vm, vcpu, state->rip);
2065 /* We are asked to give the cpu by scheduler. */
2066 if (vcpu_should_yield(vm, vcpu)) {
2068 vm_exit_astpending(vm, vcpu, state->rip);
2072 if (vcpu_debugged(vm, vcpu)) {
2074 vm_exit_debug(vm, vcpu, state->rip);
2079 * #VMEXIT resumes the host with the guest LDTR, so
2080 * save the current LDT selector so it can be restored
2081 * after an exit. The userspace hypervisor probably
2082 * doesn't use a LDT, but save and restore it to be
2087 svm_inj_interrupts(svm_sc, vcpu, vlapic);
2089 /* Activate the nested pmap on 'curcpu' */
2090 CPU_SET_ATOMIC_ACQ(curcpu, &pmap->pm_active);
2093 * Check the pmap generation and the ASID generation to
2094 * ensure that the vcpu does not use stale TLB mappings.
2096 check_asid(svm_sc, vcpu, pmap, curcpu);
2098 ctrl->vmcb_clean = vmcb_clean & ~vcpustate->dirty;
2099 vcpustate->dirty = 0;
2100 VCPU_CTR1(vm, vcpu, "vmcb clean %#x", ctrl->vmcb_clean);
2102 /* Launch Virtual Machine. */
2103 VCPU_CTR1(vm, vcpu, "Resume execution at %#lx", state->rip);
2104 svm_dr_enter_guest(gctx);
2105 svm_launch(vmcb_pa, gctx, get_pcpu());
2106 svm_dr_leave_guest(gctx);
2108 CPU_CLR_ATOMIC(curcpu, &pmap->pm_active);
2111 * The host GDTR and IDTR is saved by VMRUN and restored
2112 * automatically on #VMEXIT. However, the host TSS needs
2113 * to be restored explicitly.
2117 /* Restore host LDTR. */
2120 /* #VMEXIT disables interrupts so re-enable them here. */
2123 /* Update 'nextrip' */
2124 vcpustate->nextrip = state->rip;
2126 /* Handle #VMEXIT and if required return to user space. */
2127 handled = svm_vmexit(svm_sc, vcpu, vmexit);
2130 svm_msr_guest_exit(svm_sc, vcpu);
2136 svm_vmcleanup(void *arg)
2138 struct svm_softc *sc = arg;
2140 contigfree(sc->iopm_bitmap, SVM_IO_BITMAP_SIZE, M_SVM);
2141 contigfree(sc->msr_bitmap, SVM_MSR_BITMAP_SIZE, M_SVM);
2146 swctx_regptr(struct svm_regctx *regctx, int reg)
2150 case VM_REG_GUEST_RBX:
2151 return (®ctx->sctx_rbx);
2152 case VM_REG_GUEST_RCX:
2153 return (®ctx->sctx_rcx);
2154 case VM_REG_GUEST_RDX:
2155 return (®ctx->sctx_rdx);
2156 case VM_REG_GUEST_RDI:
2157 return (®ctx->sctx_rdi);
2158 case VM_REG_GUEST_RSI:
2159 return (®ctx->sctx_rsi);
2160 case VM_REG_GUEST_RBP:
2161 return (®ctx->sctx_rbp);
2162 case VM_REG_GUEST_R8:
2163 return (®ctx->sctx_r8);
2164 case VM_REG_GUEST_R9:
2165 return (®ctx->sctx_r9);
2166 case VM_REG_GUEST_R10:
2167 return (®ctx->sctx_r10);
2168 case VM_REG_GUEST_R11:
2169 return (®ctx->sctx_r11);
2170 case VM_REG_GUEST_R12:
2171 return (®ctx->sctx_r12);
2172 case VM_REG_GUEST_R13:
2173 return (®ctx->sctx_r13);
2174 case VM_REG_GUEST_R14:
2175 return (®ctx->sctx_r14);
2176 case VM_REG_GUEST_R15:
2177 return (®ctx->sctx_r15);
2178 case VM_REG_GUEST_DR0:
2179 return (®ctx->sctx_dr0);
2180 case VM_REG_GUEST_DR1:
2181 return (®ctx->sctx_dr1);
2182 case VM_REG_GUEST_DR2:
2183 return (®ctx->sctx_dr2);
2184 case VM_REG_GUEST_DR3:
2185 return (®ctx->sctx_dr3);
2192 svm_getreg(void *arg, int vcpu, int ident, uint64_t *val)
2194 struct svm_softc *svm_sc;
2199 if (ident == VM_REG_GUEST_INTR_SHADOW) {
2200 return (svm_get_intr_shadow(svm_sc, vcpu, val));
2203 if (vmcb_read(svm_sc, vcpu, ident, val) == 0) {
2207 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident);
2214 VCPU_CTR1(svm_sc->vm, vcpu, "svm_getreg: unknown register %#x", ident);
2219 svm_setreg(void *arg, int vcpu, int ident, uint64_t val)
2221 struct svm_softc *svm_sc;
2226 if (ident == VM_REG_GUEST_INTR_SHADOW) {
2227 return (svm_modify_intr_shadow(svm_sc, vcpu, val));
2230 /* Do not permit user write access to VMCB fields by offset. */
2231 if (!VMCB_ACCESS_OK(ident)) {
2232 if (vmcb_write(svm_sc, vcpu, ident, val) == 0) {
2237 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident);
2244 if (ident == VM_REG_GUEST_ENTRY_INST_LENGTH) {
2250 * XXX deal with CR3 and invalidate TLB entries tagged with the
2251 * vcpu's ASID. This needs to be treated differently depending on
2252 * whether 'running' is true/false.
2255 VCPU_CTR1(svm_sc->vm, vcpu, "svm_setreg: unknown register %#x", ident);
2259 #ifdef BHYVE_SNAPSHOT
2261 svm_snapshot_reg(void *arg, int vcpu, int ident,
2262 struct vm_snapshot_meta *meta)
2267 if (meta->op == VM_SNAPSHOT_SAVE) {
2268 ret = svm_getreg(arg, vcpu, ident, &val);
2272 SNAPSHOT_VAR_OR_LEAVE(val, meta, ret, done);
2273 } else if (meta->op == VM_SNAPSHOT_RESTORE) {
2274 SNAPSHOT_VAR_OR_LEAVE(val, meta, ret, done);
2276 ret = svm_setreg(arg, vcpu, ident, val);
2290 svm_setcap(void *arg, int vcpu, int type, int val)
2292 struct svm_softc *sc;
2298 case VM_CAP_HALT_EXIT:
2299 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2300 VMCB_INTCPT_HLT, val);
2302 case VM_CAP_PAUSE_EXIT:
2303 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2304 VMCB_INTCPT_PAUSE, val);
2306 case VM_CAP_UNRESTRICTED_GUEST:
2307 /* Unrestricted guest execution cannot be disabled in SVM */
2319 svm_getcap(void *arg, int vcpu, int type, int *retval)
2321 struct svm_softc *sc;
2328 case VM_CAP_HALT_EXIT:
2329 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2332 case VM_CAP_PAUSE_EXIT:
2333 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT,
2336 case VM_CAP_UNRESTRICTED_GUEST:
2337 *retval = 1; /* unrestricted guest is always enabled */
2346 static struct vlapic *
2347 svm_vlapic_init(void *arg, int vcpuid)
2349 struct svm_softc *svm_sc;
2350 struct vlapic *vlapic;
2353 vlapic = malloc(sizeof(struct vlapic), M_SVM_VLAPIC, M_WAITOK | M_ZERO);
2354 vlapic->vm = svm_sc->vm;
2355 vlapic->vcpuid = vcpuid;
2356 vlapic->apic_page = (struct LAPIC *)&svm_sc->apic_page[vcpuid];
2358 vlapic_init(vlapic);
2364 svm_vlapic_cleanup(void *arg, struct vlapic *vlapic)
2367 vlapic_cleanup(vlapic);
2368 free(vlapic, M_SVM_VLAPIC);
2371 #ifdef BHYVE_SNAPSHOT
2373 svm_snapshot_vmi(void *arg, struct vm_snapshot_meta *meta)
2375 /* struct svm_softc is AMD's representation for SVM softc */
2376 struct svm_softc *sc;
2377 struct svm_vcpu *vcpu;
2385 KASSERT(sc != NULL, ("%s: arg was NULL", __func__));
2387 SNAPSHOT_VAR_OR_LEAVE(sc->nptp, meta, ret, done);
2389 for (i = 0; i < VM_MAXCPU; i++) {
2390 vcpu = &sc->vcpu[i];
2393 /* VMCB fields for virtual cpu i */
2394 SNAPSHOT_VAR_OR_LEAVE(vmcb->ctrl.v_tpr, meta, ret, done);
2395 val = vmcb->ctrl.v_tpr;
2396 SNAPSHOT_VAR_OR_LEAVE(val, meta, ret, done);
2397 vmcb->ctrl.v_tpr = val;
2399 SNAPSHOT_VAR_OR_LEAVE(vmcb->ctrl.asid, meta, ret, done);
2400 val = vmcb->ctrl.np_enable;
2401 SNAPSHOT_VAR_OR_LEAVE(val, meta, ret, done);
2402 vmcb->ctrl.np_enable = val;
2404 val = vmcb->ctrl.intr_shadow;
2405 SNAPSHOT_VAR_OR_LEAVE(val, meta, ret, done);
2406 vmcb->ctrl.intr_shadow = val;
2407 SNAPSHOT_VAR_OR_LEAVE(vmcb->ctrl.tlb_ctrl, meta, ret, done);
2409 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad1,
2410 sizeof(vmcb->state.pad1),
2412 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.cpl, meta, ret, done);
2413 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad2,
2414 sizeof(vmcb->state.pad2),
2416 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.efer, meta, ret, done);
2417 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad3,
2418 sizeof(vmcb->state.pad3),
2420 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.cr4, meta, ret, done);
2421 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.cr3, meta, ret, done);
2422 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.cr0, meta, ret, done);
2423 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.dr7, meta, ret, done);
2424 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.dr6, meta, ret, done);
2425 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.rflags, meta, ret, done);
2426 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.rip, meta, ret, done);
2427 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad4,
2428 sizeof(vmcb->state.pad4),
2430 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.rsp, meta, ret, done);
2431 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad5,
2432 sizeof(vmcb->state.pad5),
2434 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.rax, meta, ret, done);
2435 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.star, meta, ret, done);
2436 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.lstar, meta, ret, done);
2437 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.cstar, meta, ret, done);
2438 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.sfmask, meta, ret, done);
2439 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.kernelgsbase,
2441 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.sysenter_cs, meta, ret, done);
2442 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.sysenter_esp,
2444 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.sysenter_eip,
2446 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.cr2, meta, ret, done);
2447 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad6,
2448 sizeof(vmcb->state.pad6),
2450 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.g_pat, meta, ret, done);
2451 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.dbgctl, meta, ret, done);
2452 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.br_from, meta, ret, done);
2453 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.br_to, meta, ret, done);
2454 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.int_from, meta, ret, done);
2455 SNAPSHOT_VAR_OR_LEAVE(vmcb->state.int_to, meta, ret, done);
2456 SNAPSHOT_BUF_OR_LEAVE(vmcb->state.pad7,
2457 sizeof(vmcb->state.pad7),
2460 /* Snapshot swctx for virtual cpu i */
2461 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_rbp, meta, ret, done);
2462 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_rbx, meta, ret, done);
2463 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_rcx, meta, ret, done);
2464 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_rdx, meta, ret, done);
2465 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_rdi, meta, ret, done);
2466 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_rsi, meta, ret, done);
2467 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r8, meta, ret, done);
2468 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r9, meta, ret, done);
2469 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r10, meta, ret, done);
2470 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r11, meta, ret, done);
2471 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r12, meta, ret, done);
2472 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r13, meta, ret, done);
2473 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r14, meta, ret, done);
2474 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_r15, meta, ret, done);
2475 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_dr0, meta, ret, done);
2476 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_dr1, meta, ret, done);
2477 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_dr2, meta, ret, done);
2478 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.sctx_dr3, meta, ret, done);
2480 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_dr0, meta, ret, done);
2481 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_dr1, meta, ret, done);
2482 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_dr2, meta, ret, done);
2483 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_dr3, meta, ret, done);
2484 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_dr6, meta, ret, done);
2485 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_dr7, meta, ret, done);
2486 SNAPSHOT_VAR_OR_LEAVE(vcpu->swctx.host_debugctl, meta, ret,
2489 /* Restore other svm_vcpu struct fields */
2491 /* Restore NEXTRIP field */
2492 SNAPSHOT_VAR_OR_LEAVE(vcpu->nextrip, meta, ret, done);
2494 /* Restore lastcpu field */
2495 SNAPSHOT_VAR_OR_LEAVE(vcpu->lastcpu, meta, ret, done);
2496 SNAPSHOT_VAR_OR_LEAVE(vcpu->dirty, meta, ret, done);
2498 /* Restore EPTGEN field - EPT is Extended Page Tabel */
2499 SNAPSHOT_VAR_OR_LEAVE(vcpu->eptgen, meta, ret, done);
2501 SNAPSHOT_VAR_OR_LEAVE(vcpu->asid.gen, meta, ret, done);
2502 SNAPSHOT_VAR_OR_LEAVE(vcpu->asid.num, meta, ret, done);
2504 /* Set all caches dirty */
2505 if (meta->op == VM_SNAPSHOT_RESTORE) {
2506 svm_set_dirty(sc, i, VMCB_CACHE_ASID);
2507 svm_set_dirty(sc, i, VMCB_CACHE_IOPM);
2508 svm_set_dirty(sc, i, VMCB_CACHE_I);
2509 svm_set_dirty(sc, i, VMCB_CACHE_TPR);
2510 svm_set_dirty(sc, i, VMCB_CACHE_CR2);
2511 svm_set_dirty(sc, i, VMCB_CACHE_CR);
2512 svm_set_dirty(sc, i, VMCB_CACHE_DT);
2513 svm_set_dirty(sc, i, VMCB_CACHE_SEG);
2514 svm_set_dirty(sc, i, VMCB_CACHE_NP);
2518 if (meta->op == VM_SNAPSHOT_RESTORE)
2526 svm_snapshot_vmcx(void *arg, struct vm_snapshot_meta *meta, int vcpu)
2529 struct svm_softc *sc;
2530 int err, running, hostcpu;
2532 sc = (struct svm_softc *)arg;
2535 KASSERT(arg != NULL, ("%s: arg was NULL", __func__));
2536 vmcb = svm_get_vmcb(sc, vcpu);
2538 running = vcpu_is_running(sc->vm, vcpu, &hostcpu);
2539 if (running && hostcpu !=curcpu) {
2540 printf("%s: %s%d is running", __func__, vm_name(sc->vm), vcpu);
2544 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_CR0, meta);
2545 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_CR2, meta);
2546 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_CR3, meta);
2547 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_CR4, meta);
2549 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_DR7, meta);
2551 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_RAX, meta);
2553 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_RSP, meta);
2554 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_RIP, meta);
2555 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_RFLAGS, meta);
2557 /* Guest segments */
2559 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_ES, meta);
2560 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_ES, meta);
2563 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_CS, meta);
2564 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_CS, meta);
2567 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_SS, meta);
2568 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_SS, meta);
2571 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_DS, meta);
2572 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_DS, meta);
2575 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_FS, meta);
2576 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_FS, meta);
2579 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_GS, meta);
2580 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_GS, meta);
2583 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_TR, meta);
2584 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_TR, meta);
2587 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_LDTR, meta);
2588 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_LDTR, meta);
2591 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_EFER, meta);
2594 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_IDTR, meta);
2595 err += vmcb_snapshot_desc(sc, vcpu, VM_REG_GUEST_GDTR, meta);
2597 /* Specific AMD registers */
2598 err += vmcb_snapshot_any(sc, vcpu,
2599 VMCB_ACCESS(VMCB_OFF_SYSENTER_CS, 8), meta);
2600 err += vmcb_snapshot_any(sc, vcpu,
2601 VMCB_ACCESS(VMCB_OFF_SYSENTER_ESP, 8), meta);
2602 err += vmcb_snapshot_any(sc, vcpu,
2603 VMCB_ACCESS(VMCB_OFF_SYSENTER_EIP, 8), meta);
2605 err += vmcb_snapshot_any(sc, vcpu,
2606 VMCB_ACCESS(VMCB_OFF_NPT_BASE, 8), meta);
2608 err += vmcb_snapshot_any(sc, vcpu,
2609 VMCB_ACCESS(VMCB_OFF_CR_INTERCEPT, 4), meta);
2610 err += vmcb_snapshot_any(sc, vcpu,
2611 VMCB_ACCESS(VMCB_OFF_DR_INTERCEPT, 4), meta);
2612 err += vmcb_snapshot_any(sc, vcpu,
2613 VMCB_ACCESS(VMCB_OFF_EXC_INTERCEPT, 4), meta);
2614 err += vmcb_snapshot_any(sc, vcpu,
2615 VMCB_ACCESS(VMCB_OFF_INST1_INTERCEPT, 4), meta);
2616 err += vmcb_snapshot_any(sc, vcpu,
2617 VMCB_ACCESS(VMCB_OFF_INST2_INTERCEPT, 4), meta);
2619 err += vmcb_snapshot_any(sc, vcpu,
2620 VMCB_ACCESS(VMCB_OFF_TLB_CTRL, 4), meta);
2622 err += vmcb_snapshot_any(sc, vcpu,
2623 VMCB_ACCESS(VMCB_OFF_EXITINFO1, 8), meta);
2624 err += vmcb_snapshot_any(sc, vcpu,
2625 VMCB_ACCESS(VMCB_OFF_EXITINFO2, 8), meta);
2626 err += vmcb_snapshot_any(sc, vcpu,
2627 VMCB_ACCESS(VMCB_OFF_EXITINTINFO, 8), meta);
2629 err += vmcb_snapshot_any(sc, vcpu,
2630 VMCB_ACCESS(VMCB_OFF_VIRQ, 8), meta);
2632 err += vmcb_snapshot_any(sc, vcpu,
2633 VMCB_ACCESS(VMCB_OFF_GUEST_PAT, 8), meta);
2635 err += vmcb_snapshot_any(sc, vcpu,
2636 VMCB_ACCESS(VMCB_OFF_AVIC_BAR, 8), meta);
2637 err += vmcb_snapshot_any(sc, vcpu,
2638 VMCB_ACCESS(VMCB_OFF_AVIC_PAGE, 8), meta);
2639 err += vmcb_snapshot_any(sc, vcpu,
2640 VMCB_ACCESS(VMCB_OFF_AVIC_LT, 8), meta);
2641 err += vmcb_snapshot_any(sc, vcpu,
2642 VMCB_ACCESS(VMCB_OFF_AVIC_PT, 8), meta);
2644 err += vmcb_snapshot_any(sc, vcpu,
2645 VMCB_ACCESS(VMCB_OFF_IO_PERM, 8), meta);
2646 err += vmcb_snapshot_any(sc, vcpu,
2647 VMCB_ACCESS(VMCB_OFF_MSR_PERM, 8), meta);
2649 err += vmcb_snapshot_any(sc, vcpu,
2650 VMCB_ACCESS(VMCB_OFF_ASID, 4), meta);
2652 err += vmcb_snapshot_any(sc, vcpu,
2653 VMCB_ACCESS(VMCB_OFF_EXIT_REASON, 8), meta);
2655 err += svm_snapshot_reg(sc, vcpu, VM_REG_GUEST_INTR_SHADOW, meta);
2661 svm_restore_tsc(void *arg, int vcpu, uint64_t offset)
2665 err = svm_set_tsc_offset(arg, vcpu, offset);
2671 struct vmm_ops vmm_ops_amd = {
2673 .cleanup = svm_cleanup,
2674 .resume = svm_restore,
2675 .vminit = svm_vminit,
2677 .vmcleanup = svm_vmcleanup,
2678 .vmgetreg = svm_getreg,
2679 .vmsetreg = svm_setreg,
2680 .vmgetdesc = vmcb_getdesc,
2681 .vmsetdesc = vmcb_setdesc,
2682 .vmgetcap = svm_getcap,
2683 .vmsetcap = svm_setcap,
2684 .vmspace_alloc = svm_npt_alloc,
2685 .vmspace_free = svm_npt_free,
2686 .vlapic_init = svm_vlapic_init,
2687 .vlapic_cleanup = svm_vlapic_cleanup,
2688 #ifdef BHYVE_SNAPSHOT
2689 .vmsnapshot = svm_snapshot_vmi,
2690 .vmcx_snapshot = svm_snapshot_vmcx,
2691 .vm_restore_tsc = svm_restore_tsc,