2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
41 #include <machine/segments.h>
42 #include <machine/pmap.h>
44 #include <machine/vmm.h>
47 #include "vmx_cpufunc.h"
56 vmcs_fix_regval(uint32_t encoding, uint64_t val)
61 val = vmx_fix_cr0(val);
64 val = vmx_fix_cr4(val);
73 vmcs_field_encoding(int ident)
76 case VM_REG_GUEST_CR0:
77 return (VMCS_GUEST_CR0);
78 case VM_REG_GUEST_CR3:
79 return (VMCS_GUEST_CR3);
80 case VM_REG_GUEST_CR4:
81 return (VMCS_GUEST_CR4);
82 case VM_REG_GUEST_DR7:
83 return (VMCS_GUEST_DR7);
84 case VM_REG_GUEST_RSP:
85 return (VMCS_GUEST_RSP);
86 case VM_REG_GUEST_RIP:
87 return (VMCS_GUEST_RIP);
88 case VM_REG_GUEST_RFLAGS:
89 return (VMCS_GUEST_RFLAGS);
91 return (VMCS_GUEST_ES_SELECTOR);
93 return (VMCS_GUEST_CS_SELECTOR);
95 return (VMCS_GUEST_SS_SELECTOR);
97 return (VMCS_GUEST_DS_SELECTOR);
99 return (VMCS_GUEST_FS_SELECTOR);
100 case VM_REG_GUEST_GS:
101 return (VMCS_GUEST_GS_SELECTOR);
102 case VM_REG_GUEST_TR:
103 return (VMCS_GUEST_TR_SELECTOR);
104 case VM_REG_GUEST_LDTR:
105 return (VMCS_GUEST_LDTR_SELECTOR);
106 case VM_REG_GUEST_EFER:
107 return (VMCS_GUEST_IA32_EFER);
115 vmcs_seg_desc_encoding(int seg, uint32_t *base, uint32_t *lim, uint32_t *acc)
119 case VM_REG_GUEST_ES:
120 *base = VMCS_GUEST_ES_BASE;
121 *lim = VMCS_GUEST_ES_LIMIT;
122 *acc = VMCS_GUEST_ES_ACCESS_RIGHTS;
124 case VM_REG_GUEST_CS:
125 *base = VMCS_GUEST_CS_BASE;
126 *lim = VMCS_GUEST_CS_LIMIT;
127 *acc = VMCS_GUEST_CS_ACCESS_RIGHTS;
129 case VM_REG_GUEST_SS:
130 *base = VMCS_GUEST_SS_BASE;
131 *lim = VMCS_GUEST_SS_LIMIT;
132 *acc = VMCS_GUEST_SS_ACCESS_RIGHTS;
134 case VM_REG_GUEST_DS:
135 *base = VMCS_GUEST_DS_BASE;
136 *lim = VMCS_GUEST_DS_LIMIT;
137 *acc = VMCS_GUEST_DS_ACCESS_RIGHTS;
139 case VM_REG_GUEST_FS:
140 *base = VMCS_GUEST_FS_BASE;
141 *lim = VMCS_GUEST_FS_LIMIT;
142 *acc = VMCS_GUEST_FS_ACCESS_RIGHTS;
144 case VM_REG_GUEST_GS:
145 *base = VMCS_GUEST_GS_BASE;
146 *lim = VMCS_GUEST_GS_LIMIT;
147 *acc = VMCS_GUEST_GS_ACCESS_RIGHTS;
149 case VM_REG_GUEST_TR:
150 *base = VMCS_GUEST_TR_BASE;
151 *lim = VMCS_GUEST_TR_LIMIT;
152 *acc = VMCS_GUEST_TR_ACCESS_RIGHTS;
154 case VM_REG_GUEST_LDTR:
155 *base = VMCS_GUEST_LDTR_BASE;
156 *lim = VMCS_GUEST_LDTR_LIMIT;
157 *acc = VMCS_GUEST_LDTR_ACCESS_RIGHTS;
159 case VM_REG_GUEST_IDTR:
160 *base = VMCS_GUEST_IDTR_BASE;
161 *lim = VMCS_GUEST_IDTR_LIMIT;
162 *acc = VMCS_INVALID_ENCODING;
164 case VM_REG_GUEST_GDTR:
165 *base = VMCS_GUEST_GDTR_BASE;
166 *lim = VMCS_GUEST_GDTR_LIMIT;
167 *acc = VMCS_INVALID_ENCODING;
177 vmcs_getreg(struct vmcs *vmcs, int running, int ident, uint64_t *retval)
183 * If we need to get at vmx-specific state in the VMCS we can bypass
184 * the translation of 'ident' to 'encoding' by simply setting the
185 * sign bit. As it so happens the upper 16 bits are reserved (i.e
186 * set to 0) in the encodings for the VMCS so we are free to use the
190 encoding = ident & 0x7fffffff;
192 encoding = vmcs_field_encoding(ident);
194 if (encoding == (uint32_t)-1)
200 error = vmread(encoding, retval);
209 vmcs_setreg(struct vmcs *vmcs, int running, int ident, uint64_t val)
215 encoding = ident & 0x7fffffff;
217 encoding = vmcs_field_encoding(ident);
219 if (encoding == (uint32_t)-1)
222 val = vmcs_fix_regval(encoding, val);
227 error = vmwrite(encoding, val);
236 vmcs_setdesc(struct vmcs *vmcs, int seg, struct seg_desc *desc)
239 uint32_t base, limit, access;
241 error = vmcs_seg_desc_encoding(seg, &base, &limit, &access);
243 panic("vmcs_setdesc: invalid segment register %d", seg);
246 if ((error = vmwrite(base, desc->base)) != 0)
249 if ((error = vmwrite(limit, desc->limit)) != 0)
252 if (access != VMCS_INVALID_ENCODING) {
253 if ((error = vmwrite(access, desc->access)) != 0)
262 vmcs_getdesc(struct vmcs *vmcs, int seg, struct seg_desc *desc)
265 uint32_t base, limit, access;
268 error = vmcs_seg_desc_encoding(seg, &base, &limit, &access);
270 panic("vmcs_getdesc: invalid segment register %d", seg);
273 if ((error = vmread(base, &u64)) != 0)
277 if ((error = vmread(limit, &u64)) != 0)
281 if (access != VMCS_INVALID_ENCODING) {
282 if ((error = vmread(access, &u64)) != 0)
292 vmcs_set_msr_save(struct vmcs *vmcs, u_long g_area, u_int g_count)
299 * Guest MSRs are saved in the VM-exit MSR-store area.
300 * Guest MSRs are loaded from the VM-entry MSR-load area.
301 * Both areas point to the same location in memory.
303 if ((error = vmwrite(VMCS_EXIT_MSR_STORE, g_area)) != 0)
305 if ((error = vmwrite(VMCS_EXIT_MSR_STORE_COUNT, g_count)) != 0)
308 if ((error = vmwrite(VMCS_ENTRY_MSR_LOAD, g_area)) != 0)
310 if ((error = vmwrite(VMCS_ENTRY_MSR_LOAD_COUNT, g_count)) != 0)
320 vmcs_set_defaults(struct vmcs *vmcs,
321 u_long host_rip, u_long host_rsp, uint64_t eptp,
322 uint32_t pinbased_ctls, uint32_t procbased_ctls,
323 uint32_t procbased_ctls2, uint32_t exit_ctls,
324 uint32_t entry_ctls, u_long msr_bitmap, uint16_t vpid)
326 int error, codesel, datasel, tsssel;
327 u_long cr0, cr4, efer;
328 uint64_t pat, fsbase, idtrbase;
331 codesel = vmm_get_host_codesel();
332 datasel = vmm_get_host_datasel();
333 tsssel = vmm_get_host_tsssel();
336 * Make sure we have a "current" VMCS to work with.
341 * Load the VMX controls
343 if ((error = vmwrite(VMCS_PIN_BASED_CTLS, pinbased_ctls)) != 0)
345 if ((error = vmwrite(VMCS_PRI_PROC_BASED_CTLS, procbased_ctls)) != 0)
347 if ((error = vmwrite(VMCS_SEC_PROC_BASED_CTLS, procbased_ctls2)) != 0)
349 if ((error = vmwrite(VMCS_EXIT_CTLS, exit_ctls)) != 0)
351 if ((error = vmwrite(VMCS_ENTRY_CTLS, entry_ctls)) != 0)
356 /* Initialize guest IA32_PAT MSR with the default value */
357 pat = PAT_VALUE(0, PAT_WRITE_BACK) |
358 PAT_VALUE(1, PAT_WRITE_THROUGH) |
359 PAT_VALUE(2, PAT_UNCACHED) |
360 PAT_VALUE(3, PAT_UNCACHEABLE) |
361 PAT_VALUE(4, PAT_WRITE_BACK) |
362 PAT_VALUE(5, PAT_WRITE_THROUGH) |
363 PAT_VALUE(6, PAT_UNCACHED) |
364 PAT_VALUE(7, PAT_UNCACHEABLE);
365 if ((error = vmwrite(VMCS_GUEST_IA32_PAT, pat)) != 0)
370 /* Initialize host IA32_PAT MSR */
371 pat = vmm_get_host_pat();
372 if ((error = vmwrite(VMCS_HOST_IA32_PAT, pat)) != 0)
375 /* Load the IA32_EFER MSR */
376 efer = vmm_get_host_efer();
377 if ((error = vmwrite(VMCS_HOST_IA32_EFER, efer)) != 0)
380 /* Load the control registers */
382 cr0 = vmm_get_host_cr0();
383 if ((error = vmwrite(VMCS_HOST_CR0, cr0)) != 0)
386 cr4 = vmm_get_host_cr4() | CR4_VMXE;
387 if ((error = vmwrite(VMCS_HOST_CR4, cr4)) != 0)
390 /* Load the segment selectors */
391 if ((error = vmwrite(VMCS_HOST_ES_SELECTOR, datasel)) != 0)
394 if ((error = vmwrite(VMCS_HOST_CS_SELECTOR, codesel)) != 0)
397 if ((error = vmwrite(VMCS_HOST_SS_SELECTOR, datasel)) != 0)
400 if ((error = vmwrite(VMCS_HOST_DS_SELECTOR, datasel)) != 0)
403 if ((error = vmwrite(VMCS_HOST_FS_SELECTOR, datasel)) != 0)
406 if ((error = vmwrite(VMCS_HOST_GS_SELECTOR, datasel)) != 0)
409 if ((error = vmwrite(VMCS_HOST_TR_SELECTOR, tsssel)) != 0)
413 * Load the Base-Address for %fs and idtr.
415 * Note that we exclude %gs, tss and gdtr here because their base
416 * address is pcpu specific.
418 fsbase = vmm_get_host_fsbase();
419 if ((error = vmwrite(VMCS_HOST_FS_BASE, fsbase)) != 0)
422 idtrbase = vmm_get_host_idtrbase();
423 if ((error = vmwrite(VMCS_HOST_IDTR_BASE, idtrbase)) != 0)
426 /* instruction pointer */
427 if ((error = vmwrite(VMCS_HOST_RIP, host_rip)) != 0)
431 if ((error = vmwrite(VMCS_HOST_RSP, host_rsp)) != 0)
435 if ((error = vmwrite(VMCS_EPTP, eptp)) != 0)
439 if ((error = vmwrite(VMCS_VPID, vpid)) != 0)
443 if ((error = vmwrite(VMCS_MSR_BITMAP, msr_bitmap)) != 0)
446 /* exception bitmap */
447 exc_bitmap = 1 << IDT_MC;
448 if ((error = vmwrite(VMCS_EXCEPTION_BITMAP, exc_bitmap)) != 0)
452 if ((error = vmwrite(VMCS_LINK_POINTER, ~0)) != 0)
460 vmcs_read(uint32_t encoding)
465 error = vmread(encoding, &val);
467 panic("vmcs_read(%u) error %d", encoding, error);
473 extern int vmxon_enabled[];
475 DB_SHOW_COMMAND(vmcs, db_show_vmcs)
477 uint64_t cur_vmcs, val;
480 if (!vmxon_enabled[curcpu]) {
481 db_printf("VMX not enabled\n");
486 db_printf("Only current VMCS supported\n");
491 if (cur_vmcs == VMCS_INITIAL) {
492 db_printf("No current VM context\n");
495 db_printf("VMCS: %jx\n", cur_vmcs);
496 db_printf("VPID: %lu\n", vmcs_read(VMCS_VPID));
497 db_printf("Activity: ");
498 val = vmcs_read(VMCS_GUEST_ACTIVITY);
507 db_printf("Shutdown");
510 db_printf("Wait for SIPI");
513 db_printf("Unknown: %#lx", val);
516 exit = vmcs_read(VMCS_EXIT_REASON);
517 if (exit & 0x80000000)
518 db_printf("Entry Failure Reason: %u\n", exit & 0xffff);
520 db_printf("Exit Reason: %u\n", exit & 0xffff);
521 db_printf("Qualification: %#lx\n", vmcs_exit_qualification());
522 db_printf("Guest Linear Address: %#lx\n",
523 vmcs_read(VMCS_GUEST_LINEAR_ADDRESS));
524 switch (exit & 0x8000ffff) {
525 case EXIT_REASON_EXCEPTION:
526 case EXIT_REASON_EXT_INTR:
527 val = vmcs_read(VMCS_EXIT_INTERRUPTION_INFO);
528 db_printf("Interrupt Type: ");
529 switch (val >> 8 & 0x7) {
531 db_printf("external");
537 db_printf("HW exception");
540 db_printf("SW exception");
543 db_printf("?? %lu", val >> 8 & 0x7);
546 db_printf(" Vector: %lu", val & 0xff);
548 db_printf(" Error Code: %lx",
549 vmcs_read(VMCS_EXIT_INTERRUPTION_ERROR));
552 case EXIT_REASON_EPT_FAULT:
553 case EXIT_REASON_EPT_MISCONFIG:
554 db_printf("Guest Physical Address: %#lx\n",
555 vmcs_read(VMCS_GUEST_PHYSICAL_ADDRESS));
558 db_printf("VM-instruction error: %#lx\n", vmcs_instruction_error());