2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
44 #include <machine/segments.h>
45 #include <machine/vmm.h>
47 #include "vmx_cpufunc.h"
56 SYSCTL_DECL(_hw_vmm_vmx);
58 static int no_flush_rsb;
59 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, no_flush_rsb, CTLFLAG_RW,
60 &no_flush_rsb, 0, "Do not flush RSB upon vmexit");
63 vmcs_fix_regval(uint32_t encoding, uint64_t val)
68 val = vmx_fix_cr0(val);
71 val = vmx_fix_cr4(val);
80 vmcs_field_encoding(int ident)
83 case VM_REG_GUEST_CR0:
84 return (VMCS_GUEST_CR0);
85 case VM_REG_GUEST_CR3:
86 return (VMCS_GUEST_CR3);
87 case VM_REG_GUEST_CR4:
88 return (VMCS_GUEST_CR4);
89 case VM_REG_GUEST_DR7:
90 return (VMCS_GUEST_DR7);
91 case VM_REG_GUEST_RSP:
92 return (VMCS_GUEST_RSP);
93 case VM_REG_GUEST_RIP:
94 return (VMCS_GUEST_RIP);
95 case VM_REG_GUEST_RFLAGS:
96 return (VMCS_GUEST_RFLAGS);
98 return (VMCS_GUEST_ES_SELECTOR);
100 return (VMCS_GUEST_CS_SELECTOR);
101 case VM_REG_GUEST_SS:
102 return (VMCS_GUEST_SS_SELECTOR);
103 case VM_REG_GUEST_DS:
104 return (VMCS_GUEST_DS_SELECTOR);
105 case VM_REG_GUEST_FS:
106 return (VMCS_GUEST_FS_SELECTOR);
107 case VM_REG_GUEST_GS:
108 return (VMCS_GUEST_GS_SELECTOR);
109 case VM_REG_GUEST_TR:
110 return (VMCS_GUEST_TR_SELECTOR);
111 case VM_REG_GUEST_LDTR:
112 return (VMCS_GUEST_LDTR_SELECTOR);
113 case VM_REG_GUEST_EFER:
114 return (VMCS_GUEST_IA32_EFER);
115 case VM_REG_GUEST_PDPTE0:
116 return (VMCS_GUEST_PDPTE0);
117 case VM_REG_GUEST_PDPTE1:
118 return (VMCS_GUEST_PDPTE1);
119 case VM_REG_GUEST_PDPTE2:
120 return (VMCS_GUEST_PDPTE2);
121 case VM_REG_GUEST_PDPTE3:
122 return (VMCS_GUEST_PDPTE3);
123 case VM_REG_GUEST_ENTRY_INST_LENGTH:
124 return (VMCS_ENTRY_INST_LENGTH);
132 vmcs_seg_desc_encoding(int seg, uint32_t *base, uint32_t *lim, uint32_t *acc)
136 case VM_REG_GUEST_ES:
137 *base = VMCS_GUEST_ES_BASE;
138 *lim = VMCS_GUEST_ES_LIMIT;
139 *acc = VMCS_GUEST_ES_ACCESS_RIGHTS;
141 case VM_REG_GUEST_CS:
142 *base = VMCS_GUEST_CS_BASE;
143 *lim = VMCS_GUEST_CS_LIMIT;
144 *acc = VMCS_GUEST_CS_ACCESS_RIGHTS;
146 case VM_REG_GUEST_SS:
147 *base = VMCS_GUEST_SS_BASE;
148 *lim = VMCS_GUEST_SS_LIMIT;
149 *acc = VMCS_GUEST_SS_ACCESS_RIGHTS;
151 case VM_REG_GUEST_DS:
152 *base = VMCS_GUEST_DS_BASE;
153 *lim = VMCS_GUEST_DS_LIMIT;
154 *acc = VMCS_GUEST_DS_ACCESS_RIGHTS;
156 case VM_REG_GUEST_FS:
157 *base = VMCS_GUEST_FS_BASE;
158 *lim = VMCS_GUEST_FS_LIMIT;
159 *acc = VMCS_GUEST_FS_ACCESS_RIGHTS;
161 case VM_REG_GUEST_GS:
162 *base = VMCS_GUEST_GS_BASE;
163 *lim = VMCS_GUEST_GS_LIMIT;
164 *acc = VMCS_GUEST_GS_ACCESS_RIGHTS;
166 case VM_REG_GUEST_TR:
167 *base = VMCS_GUEST_TR_BASE;
168 *lim = VMCS_GUEST_TR_LIMIT;
169 *acc = VMCS_GUEST_TR_ACCESS_RIGHTS;
171 case VM_REG_GUEST_LDTR:
172 *base = VMCS_GUEST_LDTR_BASE;
173 *lim = VMCS_GUEST_LDTR_LIMIT;
174 *acc = VMCS_GUEST_LDTR_ACCESS_RIGHTS;
176 case VM_REG_GUEST_IDTR:
177 *base = VMCS_GUEST_IDTR_BASE;
178 *lim = VMCS_GUEST_IDTR_LIMIT;
179 *acc = VMCS_INVALID_ENCODING;
181 case VM_REG_GUEST_GDTR:
182 *base = VMCS_GUEST_GDTR_BASE;
183 *lim = VMCS_GUEST_GDTR_LIMIT;
184 *acc = VMCS_INVALID_ENCODING;
194 vmcs_getreg(struct vmcs *vmcs, int running, int ident, uint64_t *retval)
200 * If we need to get at vmx-specific state in the VMCS we can bypass
201 * the translation of 'ident' to 'encoding' by simply setting the
202 * sign bit. As it so happens the upper 16 bits are reserved (i.e
203 * set to 0) in the encodings for the VMCS so we are free to use the
207 encoding = ident & 0x7fffffff;
209 encoding = vmcs_field_encoding(ident);
211 if (encoding == (uint32_t)-1)
217 error = vmread(encoding, retval);
226 vmcs_setreg(struct vmcs *vmcs, int running, int ident, uint64_t val)
232 encoding = ident & 0x7fffffff;
234 encoding = vmcs_field_encoding(ident);
236 if (encoding == (uint32_t)-1)
239 val = vmcs_fix_regval(encoding, val);
244 error = vmwrite(encoding, val);
253 vmcs_setdesc(struct vmcs *vmcs, int running, int seg, struct seg_desc *desc)
256 uint32_t base, limit, access;
258 error = vmcs_seg_desc_encoding(seg, &base, &limit, &access);
260 panic("vmcs_setdesc: invalid segment register %d", seg);
264 if ((error = vmwrite(base, desc->base)) != 0)
267 if ((error = vmwrite(limit, desc->limit)) != 0)
270 if (access != VMCS_INVALID_ENCODING) {
271 if ((error = vmwrite(access, desc->access)) != 0)
281 vmcs_getdesc(struct vmcs *vmcs, int running, int seg, struct seg_desc *desc)
284 uint32_t base, limit, access;
287 error = vmcs_seg_desc_encoding(seg, &base, &limit, &access);
289 panic("vmcs_getdesc: invalid segment register %d", seg);
293 if ((error = vmread(base, &u64)) != 0)
297 if ((error = vmread(limit, &u64)) != 0)
301 if (access != VMCS_INVALID_ENCODING) {
302 if ((error = vmread(access, &u64)) != 0)
313 vmcs_set_msr_save(struct vmcs *vmcs, u_long g_area, u_int g_count)
320 * Guest MSRs are saved in the VM-exit MSR-store area.
321 * Guest MSRs are loaded from the VM-entry MSR-load area.
322 * Both areas point to the same location in memory.
324 if ((error = vmwrite(VMCS_EXIT_MSR_STORE, g_area)) != 0)
326 if ((error = vmwrite(VMCS_EXIT_MSR_STORE_COUNT, g_count)) != 0)
329 if ((error = vmwrite(VMCS_ENTRY_MSR_LOAD, g_area)) != 0)
331 if ((error = vmwrite(VMCS_ENTRY_MSR_LOAD_COUNT, g_count)) != 0)
341 vmcs_init(struct vmcs *vmcs)
343 int error, codesel, datasel, tsssel;
344 u_long cr0, cr4, efer;
345 uint64_t pat, fsbase, idtrbase;
347 codesel = vmm_get_host_codesel();
348 datasel = vmm_get_host_datasel();
349 tsssel = vmm_get_host_tsssel();
352 * Make sure we have a "current" VMCS to work with.
358 /* Initialize host IA32_PAT MSR */
359 pat = vmm_get_host_pat();
360 if ((error = vmwrite(VMCS_HOST_IA32_PAT, pat)) != 0)
363 /* Load the IA32_EFER MSR */
364 efer = vmm_get_host_efer();
365 if ((error = vmwrite(VMCS_HOST_IA32_EFER, efer)) != 0)
368 /* Load the control registers */
370 cr0 = vmm_get_host_cr0();
371 if ((error = vmwrite(VMCS_HOST_CR0, cr0)) != 0)
374 cr4 = vmm_get_host_cr4() | CR4_VMXE;
375 if ((error = vmwrite(VMCS_HOST_CR4, cr4)) != 0)
378 /* Load the segment selectors */
379 if ((error = vmwrite(VMCS_HOST_ES_SELECTOR, datasel)) != 0)
382 if ((error = vmwrite(VMCS_HOST_CS_SELECTOR, codesel)) != 0)
385 if ((error = vmwrite(VMCS_HOST_SS_SELECTOR, datasel)) != 0)
388 if ((error = vmwrite(VMCS_HOST_DS_SELECTOR, datasel)) != 0)
391 if ((error = vmwrite(VMCS_HOST_FS_SELECTOR, datasel)) != 0)
394 if ((error = vmwrite(VMCS_HOST_GS_SELECTOR, datasel)) != 0)
397 if ((error = vmwrite(VMCS_HOST_TR_SELECTOR, tsssel)) != 0)
401 * Load the Base-Address for %fs and idtr.
403 * Note that we exclude %gs, tss and gdtr here because their base
404 * address is pcpu specific.
406 fsbase = vmm_get_host_fsbase();
407 if ((error = vmwrite(VMCS_HOST_FS_BASE, fsbase)) != 0)
410 idtrbase = vmm_get_host_idtrbase();
411 if ((error = vmwrite(VMCS_HOST_IDTR_BASE, idtrbase)) != 0)
414 /* instruction pointer */
416 if ((error = vmwrite(VMCS_HOST_RIP,
417 (u_long)vmx_exit_guest)) != 0)
420 if ((error = vmwrite(VMCS_HOST_RIP,
421 (u_long)vmx_exit_guest_flush_rsb)) != 0)
426 if ((error = vmwrite(VMCS_LINK_POINTER, ~0)) != 0)
434 extern int vmxon_enabled[];
436 DB_SHOW_COMMAND(vmcs, db_show_vmcs)
438 uint64_t cur_vmcs, val;
441 if (!vmxon_enabled[curcpu]) {
442 db_printf("VMX not enabled\n");
447 db_printf("Only current VMCS supported\n");
452 if (cur_vmcs == VMCS_INITIAL) {
453 db_printf("No current VM context\n");
456 db_printf("VMCS: %jx\n", cur_vmcs);
457 db_printf("VPID: %lu\n", vmcs_read(VMCS_VPID));
458 db_printf("Activity: ");
459 val = vmcs_read(VMCS_GUEST_ACTIVITY);
468 db_printf("Shutdown");
471 db_printf("Wait for SIPI");
474 db_printf("Unknown: %#lx", val);
477 exit = vmcs_read(VMCS_EXIT_REASON);
478 if (exit & 0x80000000)
479 db_printf("Entry Failure Reason: %u\n", exit & 0xffff);
481 db_printf("Exit Reason: %u\n", exit & 0xffff);
482 db_printf("Qualification: %#lx\n", vmcs_exit_qualification());
483 db_printf("Guest Linear Address: %#lx\n",
484 vmcs_read(VMCS_GUEST_LINEAR_ADDRESS));
485 switch (exit & 0x8000ffff) {
486 case EXIT_REASON_EXCEPTION:
487 case EXIT_REASON_EXT_INTR:
488 val = vmcs_read(VMCS_EXIT_INTR_INFO);
489 db_printf("Interrupt Type: ");
490 switch (val >> 8 & 0x7) {
492 db_printf("external");
498 db_printf("HW exception");
501 db_printf("SW exception");
504 db_printf("?? %lu", val >> 8 & 0x7);
507 db_printf(" Vector: %lu", val & 0xff);
509 db_printf(" Error Code: %lx",
510 vmcs_read(VMCS_EXIT_INTR_ERRCODE));
513 case EXIT_REASON_EPT_FAULT:
514 case EXIT_REASON_EPT_MISCONFIG:
515 db_printf("Guest Physical Address: %#lx\n",
516 vmcs_read(VMCS_GUEST_PHYSICAL_ADDRESS));
519 db_printf("VM-instruction error: %#lx\n", vmcs_instruction_error());