2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
42 #include <dev/pci/pcireg.h>
44 #include <machine/vmparam.h>
45 #include <contrib/dev/acpica/include/acpi.h>
50 * Documented in the "Intel Virtualization Technology for Directed I/O",
51 * Architecture Spec, September 2008.
54 /* Section 10.4 "Register Descriptions" */
56 volatile uint32_t version;
57 volatile uint32_t res0;
58 volatile uint64_t cap;
59 volatile uint64_t ext_cap;
60 volatile uint32_t gcr;
61 volatile uint32_t gsr;
62 volatile uint64_t rta;
63 volatile uint64_t ccr;
66 #define VTD_CAP_SAGAW(cap) (((cap) >> 8) & 0x1F)
67 #define VTD_CAP_ND(cap) ((cap) & 0x7)
68 #define VTD_CAP_CM(cap) (((cap) >> 7) & 0x1)
69 #define VTD_CAP_SPS(cap) (((cap) >> 34) & 0xF)
70 #define VTD_CAP_RWBF(cap) (((cap) >> 4) & 0x1)
72 #define VTD_ECAP_DI(ecap) (((ecap) >> 2) & 0x1)
73 #define VTD_ECAP_COHERENCY(ecap) ((ecap) & 0x1)
74 #define VTD_ECAP_IRO(ecap) (((ecap) >> 8) & 0x3FF)
76 #define VTD_GCR_WBF (1 << 27)
77 #define VTD_GCR_SRTP (1 << 30)
78 #define VTD_GCR_TE (1U << 31)
80 #define VTD_GSR_WBFS (1 << 27)
81 #define VTD_GSR_RTPS (1 << 30)
82 #define VTD_GSR_TES (1U << 31)
84 #define VTD_CCR_ICC (1UL << 63) /* invalidate context cache */
85 #define VTD_CCR_CIRG_GLOBAL (1UL << 61) /* global invalidation */
87 #define VTD_IIR_IVT (1UL << 63) /* invalidation IOTLB */
88 #define VTD_IIR_IIRG_GLOBAL (1ULL << 60) /* global IOTLB invalidation */
89 #define VTD_IIR_IIRG_DOMAIN (2ULL << 60) /* domain IOTLB invalidation */
90 #define VTD_IIR_IIRG_PAGE (3ULL << 60) /* page IOTLB invalidation */
91 #define VTD_IIR_DRAIN_READS (1ULL << 49) /* drain pending DMA reads */
92 #define VTD_IIR_DRAIN_WRITES (1ULL << 48) /* drain pending DMA writes */
93 #define VTD_IIR_DOMAIN_P 32
95 #define VTD_ROOT_PRESENT 0x1
96 #define VTD_CTX_PRESENT 0x1
97 #define VTD_CTX_TT_ALL (1UL << 2)
99 #define VTD_PTE_RD (1UL << 0)
100 #define VTD_PTE_WR (1UL << 1)
101 #define VTD_PTE_SUPERPAGE (1UL << 7)
102 #define VTD_PTE_ADDR_M (0x000FFFFFFFFFF000UL)
104 #define VTD_RID2IDX(rid) (((rid) & 0xff) * 2)
107 uint64_t *ptp; /* first level page table page */
108 int pt_levels; /* number of page table levels */
109 int addrwidth; /* 'AW' field in context entry */
110 int spsmask; /* supported super page sizes */
111 u_int id; /* domain id */
112 vm_paddr_t maxaddr; /* highest address to be mapped */
113 SLIST_ENTRY(domain) next;
116 static SLIST_HEAD(, domain) domhead;
118 #define DRHD_MAX_UNITS 8
120 static struct vtdmap *vtdmaps[DRHD_MAX_UNITS];
121 static int max_domains;
122 typedef int (*drhd_ident_func_t)(void);
124 static uint64_t root_table[PAGE_SIZE / sizeof(uint64_t)] __aligned(4096);
125 static uint64_t ctx_tables[256][PAGE_SIZE / sizeof(uint64_t)] __aligned(4096);
127 static MALLOC_DEFINE(M_VTD, "vtd", "vtd");
130 vtd_max_domains(struct vtdmap *vtdmap)
134 nd = VTD_CAP_ND(vtdmap->cap);
152 panic("vtd_max_domains: invalid value of nd (0x%0x)", nd);
162 /* Skip domain id 0 - it is reserved when Caching Mode field is set */
163 for (id = 1; id < max_domains; id++) {
164 SLIST_FOREACH(dom, &domhead, next) {
169 break; /* found it */
172 if (id >= max_domains)
173 panic("domain ids exhausted");
179 vtd_wbflush(struct vtdmap *vtdmap)
182 if (VTD_ECAP_COHERENCY(vtdmap->ext_cap) == 0)
183 pmap_invalidate_cache();
185 if (VTD_CAP_RWBF(vtdmap->cap)) {
186 vtdmap->gcr = VTD_GCR_WBF;
187 while ((vtdmap->gsr & VTD_GSR_WBFS) != 0)
193 vtd_ctx_global_invalidate(struct vtdmap *vtdmap)
196 vtdmap->ccr = VTD_CCR_ICC | VTD_CCR_CIRG_GLOBAL;
197 while ((vtdmap->ccr & VTD_CCR_ICC) != 0)
202 vtd_iotlb_global_invalidate(struct vtdmap *vtdmap)
205 volatile uint64_t *iotlb_reg, val;
209 offset = VTD_ECAP_IRO(vtdmap->ext_cap) * 16;
210 iotlb_reg = (volatile uint64_t *)((caddr_t)vtdmap + offset + 8);
212 *iotlb_reg = VTD_IIR_IVT | VTD_IIR_IIRG_GLOBAL |
213 VTD_IIR_DRAIN_READS | VTD_IIR_DRAIN_WRITES;
217 if ((val & VTD_IIR_IVT) == 0)
223 vtd_translation_enable(struct vtdmap *vtdmap)
226 vtdmap->gcr = VTD_GCR_TE;
227 while ((vtdmap->gsr & VTD_GSR_TES) == 0)
232 vtd_translation_disable(struct vtdmap *vtdmap)
236 while ((vtdmap->gsr & VTD_GSR_TES) != 0)
243 int i, units, remaining;
244 struct vtdmap *vtdmap;
245 vm_paddr_t ctx_paddr;
246 char *end, envname[32];
247 unsigned long mapaddr;
249 ACPI_TABLE_DMAR *dmar;
250 ACPI_DMAR_HEADER *hdr;
251 ACPI_DMAR_HARDWARE_UNIT *drhd;
254 * Allow the user to override the ACPI DMAR table by specifying the
255 * physical address of each remapping unit.
257 * The following example specifies two remapping units at
258 * physical addresses 0xfed90000 and 0xfeda0000 respectively.
259 * set vtd.regmap.0.addr=0xfed90000
260 * set vtd.regmap.1.addr=0xfeda0000
262 for (units = 0; units < DRHD_MAX_UNITS; units++) {
263 snprintf(envname, sizeof(envname), "vtd.regmap.%d.addr", units);
264 if (getenv_ulong(envname, &mapaddr) == 0)
266 vtdmaps[units] = (struct vtdmap *)PHYS_TO_DMAP(mapaddr);
272 /* Search for DMAR table. */
273 status = AcpiGetTable(ACPI_SIG_DMAR, 0, (ACPI_TABLE_HEADER **)&dmar);
274 if (ACPI_FAILURE(status))
277 end = (char *)dmar + dmar->Header.Length;
278 remaining = dmar->Header.Length - sizeof(ACPI_TABLE_DMAR);
279 while (remaining > sizeof(ACPI_DMAR_HEADER)) {
280 hdr = (ACPI_DMAR_HEADER *)(end - remaining);
281 if (hdr->Length > remaining)
284 * From Intel VT-d arch spec, version 1.3:
285 * BIOS implementations must report mapping structures
286 * in numerical order, i.e. All remapping structures of
287 * type 0 (DRHD) enumerated before remapping structures of
288 * type 1 (RMRR) and so forth.
290 if (hdr->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
293 drhd = (ACPI_DMAR_HARDWARE_UNIT *)hdr;
294 vtdmaps[units++] = (struct vtdmap *)PHYS_TO_DMAP(drhd->Address);
295 if (units >= DRHD_MAX_UNITS)
297 remaining -= hdr->Length;
307 if (VTD_CAP_CM(vtdmap->cap) != 0)
308 panic("vtd_init: invalid caching mode");
310 max_domains = vtd_max_domains(vtdmap);
313 * Set up the root-table to point to the context-entry tables
315 for (i = 0; i < 256; i++) {
316 ctx_paddr = vtophys(ctx_tables[i]);
317 if (ctx_paddr & PAGE_MASK)
318 panic("ctx table (0x%0lx) not page aligned", ctx_paddr);
320 root_table[i * 2] = ctx_paddr | VTD_ROOT_PRESENT;
335 struct vtdmap *vtdmap;
337 for (i = 0; i < drhd_num; i++) {
341 /* Update the root table address */
342 vtdmap->rta = vtophys(root_table);
343 vtdmap->gcr = VTD_GCR_SRTP;
344 while ((vtdmap->gsr & VTD_GSR_RTPS) == 0)
347 vtd_ctx_global_invalidate(vtdmap);
348 vtd_iotlb_global_invalidate(vtdmap);
350 vtd_translation_enable(vtdmap);
358 struct vtdmap *vtdmap;
360 for (i = 0; i < drhd_num; i++) {
362 vtd_translation_disable(vtdmap);
367 vtd_add_device(void *arg, uint16_t rid)
371 struct domain *dom = arg;
373 struct vtdmap *vtdmap;
377 bus = PCI_RID2BUS(rid);
378 ctxp = ctx_tables[bus];
379 pt_paddr = vtophys(dom->ptp);
380 idx = VTD_RID2IDX(rid);
382 if (ctxp[idx] & VTD_CTX_PRESENT) {
383 panic("vtd_add_device: device %x is already owned by "
385 (uint16_t)(ctxp[idx + 1] >> 8));
389 * Order is important. The 'present' bit is set only after all fields
390 * of the context pointer are initialized.
392 ctxp[idx + 1] = dom->addrwidth | (dom->id << 8);
394 if (VTD_ECAP_DI(vtdmap->ext_cap))
395 ctxp[idx] = VTD_CTX_TT_ALL;
399 ctxp[idx] |= pt_paddr | VTD_CTX_PRESENT;
402 * 'Not Present' entries are not cached in either the Context Cache
403 * or in the IOTLB, so there is no need to invalidate either of them.
408 vtd_remove_device(void *arg, uint16_t rid)
412 struct vtdmap *vtdmap;
415 bus = PCI_RID2BUS(rid);
416 ctxp = ctx_tables[bus];
417 idx = VTD_RID2IDX(rid);
420 * Order is important. The 'present' bit is must be cleared first.
426 * Invalidate the Context Cache and the IOTLB.
428 * XXX use device-selective invalidation for Context Cache
429 * XXX use domain-selective invalidation for IOTLB
431 for (i = 0; i < drhd_num; i++) {
433 vtd_ctx_global_invalidate(vtdmap);
434 vtd_iotlb_global_invalidate(vtdmap);
438 #define CREATE_MAPPING 0
439 #define REMOVE_MAPPING 1
442 vtd_update_mapping(void *arg, vm_paddr_t gpa, vm_paddr_t hpa, uint64_t len,
446 int i, spshift, ptpshift, ptpindex, nlevels;
447 uint64_t spsize, *ptp;
453 KASSERT(gpa + len > gpa, ("%s: invalid gpa range %#lx/%#lx", __func__,
455 KASSERT(gpa + len <= dom->maxaddr, ("%s: gpa range %#lx/%#lx beyond "
456 "domain maxaddr %#lx", __func__, gpa, len, dom->maxaddr));
459 panic("vtd_create_mapping: unaligned gpa 0x%0lx", gpa);
462 panic("vtd_create_mapping: unaligned hpa 0x%0lx", hpa);
465 panic("vtd_create_mapping: unaligned len 0x%0lx", len);
468 * Compute the size of the mapping that we can accommodate.
470 * This is based on three factors:
471 * - supported super page size
472 * - alignment of the region starting at 'gpa' and 'hpa'
473 * - length of the region 'len'
476 for (i = 3; i >= 0; i--) {
477 spsize = 1UL << spshift;
478 if ((dom->spsmask & (1 << i)) != 0 &&
479 (gpa & (spsize - 1)) == 0 &&
480 (hpa & (spsize - 1)) == 0 &&
488 nlevels = dom->pt_levels;
489 while (--nlevels >= 0) {
490 ptpshift = 12 + nlevels * 9;
491 ptpindex = (gpa >> ptpshift) & 0x1FF;
493 /* We have reached the leaf mapping */
494 if (spshift >= ptpshift) {
499 * We are working on a non-leaf page table page.
501 * Create a downstream page table page if necessary and point
502 * to it from the current page table.
504 if (ptp[ptpindex] == 0) {
505 void *nlp = malloc(PAGE_SIZE, M_VTD, M_WAITOK | M_ZERO);
506 ptp[ptpindex] = vtophys(nlp)| VTD_PTE_RD | VTD_PTE_WR;
509 ptp = (uint64_t *)PHYS_TO_DMAP(ptp[ptpindex] & VTD_PTE_ADDR_M);
512 if ((gpa & ((1UL << ptpshift) - 1)) != 0)
513 panic("gpa 0x%lx and ptpshift %d mismatch", gpa, ptpshift);
516 * Update the 'gpa' -> 'hpa' mapping
521 ptp[ptpindex] = hpa | VTD_PTE_RD | VTD_PTE_WR;
524 ptp[ptpindex] |= VTD_PTE_SUPERPAGE;
527 return (1UL << ptpshift);
531 vtd_create_mapping(void *arg, vm_paddr_t gpa, vm_paddr_t hpa, uint64_t len)
534 return (vtd_update_mapping(arg, gpa, hpa, len, CREATE_MAPPING));
538 vtd_remove_mapping(void *arg, vm_paddr_t gpa, uint64_t len)
541 return (vtd_update_mapping(arg, gpa, 0, len, REMOVE_MAPPING));
545 vtd_invalidate_tlb(void *dom)
548 struct vtdmap *vtdmap;
551 * Invalidate the IOTLB.
552 * XXX use domain-selective invalidation for IOTLB
554 for (i = 0; i < drhd_num; i++) {
556 vtd_iotlb_global_invalidate(vtdmap);
561 vtd_create_domain(vm_paddr_t maxaddr)
565 int tmp, i, gaw, agaw, sagaw, res, pt_levels, addrwidth;
566 struct vtdmap *vtdmap;
569 panic("vtd_create_domain: no dma remapping hardware available");
575 * Section 3.4.2 "Adjusted Guest Address Width", Architecture Spec.
578 for (gaw = 0; addr < maxaddr; gaw++)
581 res = (gaw - 12) % 9;
585 agaw = gaw + 9 - res;
591 * Select the smallest Supported AGAW and the corresponding number
592 * of page table levels.
597 tmp = VTD_CAP_SAGAW(vtdmap->cap);
598 for (i = 0; i < 5; i++) {
599 if ((tmp & (1 << i)) != 0 && sagaw >= agaw)
609 panic("vtd_create_domain: SAGAW 0x%lx does not support AGAW %d",
610 VTD_CAP_SAGAW(vtdmap->cap), agaw);
613 dom = malloc(sizeof(struct domain), M_VTD, M_ZERO | M_WAITOK);
614 dom->pt_levels = pt_levels;
615 dom->addrwidth = addrwidth;
616 dom->id = domain_id();
617 dom->maxaddr = maxaddr;
618 dom->ptp = malloc(PAGE_SIZE, M_VTD, M_ZERO | M_WAITOK);
619 if ((uintptr_t)dom->ptp & PAGE_MASK)
620 panic("vtd_create_domain: ptp (%p) not page aligned", dom->ptp);
624 * XXX superpage mappings for the iommu do not work correctly.
626 * By default all physical memory is mapped into the host_domain.
627 * When a VM is allocated wired memory the pages belonging to it
628 * are removed from the host_domain and added to the vm's domain.
630 * If the page being removed was mapped using a superpage mapping
631 * in the host_domain then we need to demote the mapping before
634 * There is not any code to deal with the demotion at the moment
635 * so we disable superpage mappings altogether.
637 dom->spsmask = VTD_CAP_SPS(vtdmap->cap);
640 SLIST_INSERT_HEAD(&domhead, dom, next);
646 vtd_free_ptp(uint64_t *ptp, int level)
652 for (i = 0; i < 512; i++) {
653 if ((ptp[i] & (VTD_PTE_RD | VTD_PTE_WR)) == 0)
655 if ((ptp[i] & VTD_PTE_SUPERPAGE) != 0)
657 nlp = (uint64_t *)PHYS_TO_DMAP(ptp[i] & VTD_PTE_ADDR_M);
658 vtd_free_ptp(nlp, level - 1);
662 bzero(ptp, PAGE_SIZE);
667 vtd_destroy_domain(void *arg)
673 SLIST_REMOVE(&domhead, dom, domain, next);
674 vtd_free_ptp(dom->ptp, dom->pt_levels);
678 struct iommu_ops iommu_ops_intel = {