2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2014 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "opt_bhyve_snapshot.h"
34 #include <sys/param.h>
35 #include <sys/types.h>
36 #include <sys/queue.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/mutex.h>
41 #include <sys/systm.h>
43 #include <x86/apicreg.h>
44 #include <dev/ic/i8259.h>
46 #include <machine/vmm.h>
47 #include <machine/vmm_snapshot.h>
50 #include "vmm_lapic.h"
54 static MALLOC_DEFINE(M_VATPIC, "atpic", "bhyve virtual atpic (8259)");
56 #define VATPIC_LOCK(vatpic) mtx_lock_spin(&((vatpic)->mtx))
57 #define VATPIC_UNLOCK(vatpic) mtx_unlock_spin(&((vatpic)->mtx))
58 #define VATPIC_LOCKED(vatpic) mtx_owned(&((vatpic)->mtx))
74 bool sfn; /* special fully-nested mode */
77 uint8_t request; /* Interrupt Request Register (IIR) */
78 uint8_t service; /* Interrupt Service (ISR) */
79 uint8_t mask; /* Interrupt Mask Register (IMR) */
80 uint8_t smm; /* special mask mode */
82 int acnt[8]; /* sum of pin asserts and deasserts */
83 int lowprio; /* lowest priority irq */
91 struct atpic atpic[2];
95 #define VATPIC_CTR0(vatpic, fmt) \
96 VM_CTR0((vatpic)->vm, fmt)
98 #define VATPIC_CTR1(vatpic, fmt, a1) \
99 VM_CTR1((vatpic)->vm, fmt, a1)
101 #define VATPIC_CTR2(vatpic, fmt, a1, a2) \
102 VM_CTR2((vatpic)->vm, fmt, a1, a2)
104 #define VATPIC_CTR3(vatpic, fmt, a1, a2, a3) \
105 VM_CTR3((vatpic)->vm, fmt, a1, a2, a3)
107 #define VATPIC_CTR4(vatpic, fmt, a1, a2, a3, a4) \
108 VM_CTR4((vatpic)->vm, fmt, a1, a2, a3, a4)
111 * Loop over all the pins in priority order from highest to lowest.
113 #define ATPIC_PIN_FOREACH(pinvar, atpic, tmpvar) \
114 for (tmpvar = 0, pinvar = (atpic->lowprio + 1) & 0x7; \
116 tmpvar++, pinvar = (pinvar + 1) & 0x7)
118 static void vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate);
121 master_atpic(struct vatpic *vatpic, struct atpic *atpic)
124 if (atpic == &vatpic->atpic[0])
131 vatpic_get_highest_isrpin(struct atpic *atpic)
136 ATPIC_PIN_FOREACH(pin, atpic, i) {
139 if (atpic->service & bit) {
141 * An IS bit that is masked by an IMR bit will not be
142 * cleared by a non-specific EOI in Special Mask Mode.
144 if (atpic->smm && (atpic->mask & bit) != 0)
155 vatpic_get_highest_irrpin(struct atpic *atpic)
161 * In 'Special Fully-Nested Mode' when an interrupt request from
162 * a slave is in service, the slave is not locked out from the
163 * master's priority logic.
165 serviced = atpic->service;
167 serviced &= ~(1 << 2);
170 * In 'Special Mask Mode', when a mask bit is set in OCW1 it inhibits
171 * further interrupts at that level and enables interrupts from all
172 * other levels that are not masked. In other words the ISR has no
173 * bearing on the levels that can generate interrupts.
178 ATPIC_PIN_FOREACH(pin, atpic, tmp) {
182 * If there is already an interrupt in service at the same
183 * or higher priority then bail.
185 if ((serviced & bit) != 0)
189 * If an interrupt is asserted and not masked then return
190 * the corresponding 'pin' to the caller.
192 if ((atpic->request & bit) != 0 && (atpic->mask & bit) == 0)
200 vatpic_notify_intr(struct vatpic *vatpic)
205 KASSERT(VATPIC_LOCKED(vatpic), ("vatpic_notify_intr not locked"));
208 * First check the slave.
210 atpic = &vatpic->atpic[1];
211 if (!atpic->intr_raised &&
212 (pin = vatpic_get_highest_irrpin(atpic)) != -1) {
213 VATPIC_CTR4(vatpic, "atpic slave notify pin = %d "
214 "(imr 0x%x irr 0x%x isr 0x%x)", pin,
215 atpic->mask, atpic->request, atpic->service);
218 * Cascade the request from the slave to the master.
220 atpic->intr_raised = true;
221 vatpic_set_pinstate(vatpic, 2, true);
222 vatpic_set_pinstate(vatpic, 2, false);
224 VATPIC_CTR3(vatpic, "atpic slave no eligible interrupts "
225 "(imr 0x%x irr 0x%x isr 0x%x)",
226 atpic->mask, atpic->request, atpic->service);
230 * Then check the master.
232 atpic = &vatpic->atpic[0];
233 if (!atpic->intr_raised &&
234 (pin = vatpic_get_highest_irrpin(atpic)) != -1) {
235 VATPIC_CTR4(vatpic, "atpic master notify pin = %d "
236 "(imr 0x%x irr 0x%x isr 0x%x)", pin,
237 atpic->mask, atpic->request, atpic->service);
240 * From Section 3.6.2, "Interrupt Modes", in the
241 * MPtable Specification, Version 1.4
243 * PIC interrupts are routed to both the Local APIC
244 * and the I/O APIC to support operation in 1 of 3
247 * 1. Legacy PIC Mode: the PIC effectively bypasses
248 * all APIC components. In this mode the local APIC is
249 * disabled and LINT0 is reconfigured as INTR to
250 * deliver the PIC interrupt directly to the CPU.
252 * 2. Virtual Wire Mode: the APIC is treated as a
253 * virtual wire which delivers interrupts from the PIC
254 * to the CPU. In this mode LINT0 is programmed as
255 * ExtINT to indicate that the PIC is the source of
258 * 3. Virtual Wire Mode via I/O APIC: PIC interrupts are
259 * fielded by the I/O APIC and delivered to the appropriate
260 * CPU. In this mode the I/O APIC input 0 is programmed
261 * as ExtINT to indicate that the PIC is the source of the
264 atpic->intr_raised = true;
265 lapic_set_local_intr(vatpic->vm, -1, APIC_LVT_LINT0);
266 vioapic_pulse_irq(vatpic->vm, 0);
268 VATPIC_CTR3(vatpic, "atpic master no eligible interrupts "
269 "(imr 0x%x irr 0x%x isr 0x%x)",
270 atpic->mask, atpic->request, atpic->service);
275 vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
277 VATPIC_CTR1(vatpic, "atpic icw1 0x%x", val);
279 atpic->ready = false;
285 atpic->rd_cmd_reg = 0;
289 if ((val & ICW1_SNGL) != 0) {
290 VATPIC_CTR0(vatpic, "vatpic cascade mode required");
294 if ((val & ICW1_IC4) == 0) {
295 VATPIC_CTR0(vatpic, "vatpic icw4 required");
305 vatpic_icw2(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
307 VATPIC_CTR1(vatpic, "atpic icw2 0x%x", val);
309 atpic->irq_base = val & 0xf8;
317 vatpic_icw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
319 VATPIC_CTR1(vatpic, "atpic icw3 0x%x", val);
327 vatpic_icw4(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
329 VATPIC_CTR1(vatpic, "atpic icw4 0x%x", val);
331 if ((val & ICW4_8086) == 0) {
332 VATPIC_CTR0(vatpic, "vatpic microprocessor mode required");
336 if ((val & ICW4_AEOI) != 0)
339 if ((val & ICW4_SFNM) != 0) {
340 if (master_atpic(vatpic, atpic)) {
343 VATPIC_CTR1(vatpic, "Ignoring special fully nested "
344 "mode on slave atpic: %#x", val);
355 vatpic_ocw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
357 VATPIC_CTR1(vatpic, "atpic ocw1 0x%x", val);
359 atpic->mask = val & 0xff;
365 vatpic_ocw2(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
367 VATPIC_CTR1(vatpic, "atpic ocw2 0x%x", val);
369 atpic->rotate = ((val & OCW2_R) != 0);
371 if ((val & OCW2_EOI) != 0) {
374 if ((val & OCW2_SL) != 0) {
378 /* non-specific EOI */
379 isr_bit = vatpic_get_highest_isrpin(atpic);
383 atpic->service &= ~(1 << isr_bit);
386 atpic->lowprio = isr_bit;
388 } else if ((val & OCW2_SL) != 0 && atpic->rotate == true) {
389 /* specific priority */
390 atpic->lowprio = val & 0x7;
397 vatpic_ocw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
399 VATPIC_CTR1(vatpic, "atpic ocw3 0x%x", val);
401 if (val & OCW3_ESMM) {
402 atpic->smm = val & OCW3_SMM ? 1 : 0;
403 VATPIC_CTR2(vatpic, "%s atpic special mask mode %s",
404 master_atpic(vatpic, atpic) ? "master" : "slave",
405 atpic->smm ? "enabled" : "disabled");
409 /* read register command */
410 atpic->rd_cmd_reg = val & OCW3_RIS;
413 atpic->poll = ((val & OCW3_P) != 0);
420 vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate)
426 KASSERT(pin >= 0 && pin < 16,
427 ("vatpic_set_pinstate: invalid pin number %d", pin));
428 KASSERT(VATPIC_LOCKED(vatpic),
429 ("vatpic_set_pinstate: vatpic is not locked"));
431 atpic = &vatpic->atpic[pin >> 3];
433 oldcnt = atpic->acnt[pin & 0x7];
435 atpic->acnt[pin & 0x7]++;
437 atpic->acnt[pin & 0x7]--;
438 newcnt = atpic->acnt[pin & 0x7];
441 VATPIC_CTR2(vatpic, "atpic pin%d: bad acnt %d", pin, newcnt);
444 level = ((vatpic->elc[pin >> 3] & (1 << (pin & 0x7))) != 0);
446 if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
447 /* rising edge or level */
448 VATPIC_CTR1(vatpic, "atpic pin%d: asserted", pin);
449 atpic->request |= (1 << (pin & 0x7));
450 } else if (oldcnt == 1 && newcnt == 0) {
452 VATPIC_CTR1(vatpic, "atpic pin%d: deasserted", pin);
454 atpic->request &= ~(1 << (pin & 0x7));
456 VATPIC_CTR3(vatpic, "atpic pin%d: %s, ignored, acnt %d",
457 pin, newstate ? "asserted" : "deasserted", newcnt);
460 vatpic_notify_intr(vatpic);
464 vatpic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
466 struct vatpic *vatpic;
469 if (irq < 0 || irq > 15)
472 vatpic = vm_atpic(vm);
473 atpic = &vatpic->atpic[irq >> 3];
475 if (atpic->ready == false)
480 case IRQSTATE_ASSERT:
481 vatpic_set_pinstate(vatpic, irq, true);
483 case IRQSTATE_DEASSERT:
484 vatpic_set_pinstate(vatpic, irq, false);
487 vatpic_set_pinstate(vatpic, irq, true);
488 vatpic_set_pinstate(vatpic, irq, false);
491 panic("vatpic_set_irqstate: invalid irqstate %d", irqstate);
493 VATPIC_UNLOCK(vatpic);
499 vatpic_assert_irq(struct vm *vm, int irq)
501 return (vatpic_set_irqstate(vm, irq, IRQSTATE_ASSERT));
505 vatpic_deassert_irq(struct vm *vm, int irq)
507 return (vatpic_set_irqstate(vm, irq, IRQSTATE_DEASSERT));
511 vatpic_pulse_irq(struct vm *vm, int irq)
513 return (vatpic_set_irqstate(vm, irq, IRQSTATE_PULSE));
517 vatpic_set_irq_trigger(struct vm *vm, int irq, enum vm_intr_trigger trigger)
519 struct vatpic *vatpic;
521 if (irq < 0 || irq > 15)
525 * See comment in vatpic_elc_handler. These IRQs must be
528 if (trigger == LEVEL_TRIGGER) {
539 vatpic = vm_atpic(vm);
543 if (trigger == LEVEL_TRIGGER)
544 vatpic->elc[irq >> 3] |= 1 << (irq & 0x7);
546 vatpic->elc[irq >> 3] &= ~(1 << (irq & 0x7));
548 VATPIC_UNLOCK(vatpic);
554 vatpic_pending_intr(struct vm *vm, int *vecptr)
556 struct vatpic *vatpic;
560 vatpic = vm_atpic(vm);
562 atpic = &vatpic->atpic[0];
566 pin = vatpic_get_highest_irrpin(atpic);
568 atpic = &vatpic->atpic[1];
569 pin = vatpic_get_highest_irrpin(atpic);
573 * If there are no pins active at this moment then return the spurious
574 * interrupt vector instead.
579 KASSERT(pin >= 0 && pin <= 7, ("%s: invalid pin %d", __func__, pin));
580 *vecptr = atpic->irq_base + pin;
582 VATPIC_UNLOCK(vatpic);
586 vatpic_pin_accepted(struct atpic *atpic, int pin)
588 atpic->intr_raised = false;
590 if (atpic->acnt[pin] == 0)
591 atpic->request &= ~(1 << pin);
593 if (atpic->aeoi == true) {
594 if (atpic->rotate == true)
595 atpic->lowprio = pin;
597 atpic->service |= (1 << pin);
602 vatpic_intr_accepted(struct vm *vm, int vector)
604 struct vatpic *vatpic;
607 vatpic = vm_atpic(vm);
613 if ((vector & ~0x7) == vatpic->atpic[1].irq_base) {
614 vatpic_pin_accepted(&vatpic->atpic[1], pin);
616 * If this vector originated from the slave,
617 * accept the cascaded interrupt too.
619 vatpic_pin_accepted(&vatpic->atpic[0], 2);
621 vatpic_pin_accepted(&vatpic->atpic[0], pin);
624 vatpic_notify_intr(vatpic);
626 VATPIC_UNLOCK(vatpic);
630 vatpic_read(struct vatpic *vatpic, struct atpic *atpic, bool in, int port,
631 int bytes, uint32_t *eax)
639 pin = vatpic_get_highest_irrpin(atpic);
641 vatpic_pin_accepted(atpic, pin);
647 if (port & ICU_IMR_OFFSET) {
648 /* read interrrupt mask register */
651 if (atpic->rd_cmd_reg == OCW3_RIS) {
652 /* read interrupt service register */
653 *eax = atpic->service;
655 /* read interrupt request register */
656 *eax = atpic->request;
661 VATPIC_UNLOCK(vatpic);
668 vatpic_write(struct vatpic *vatpic, struct atpic *atpic, bool in, int port,
669 int bytes, uint32_t *eax)
679 if (port & ICU_IMR_OFFSET) {
680 switch (atpic->icw_num) {
682 error = vatpic_icw2(vatpic, atpic, val);
685 error = vatpic_icw3(vatpic, atpic, val);
688 error = vatpic_icw4(vatpic, atpic, val);
691 error = vatpic_ocw1(vatpic, atpic, val);
696 error = vatpic_icw1(vatpic, atpic, val);
700 error = vatpic_ocw3(vatpic, atpic, val);
702 error = vatpic_ocw2(vatpic, atpic, val);
707 vatpic_notify_intr(vatpic);
709 VATPIC_UNLOCK(vatpic);
715 vatpic_master_handler(struct vm *vm, int vcpuid, bool in, int port, int bytes,
718 struct vatpic *vatpic;
721 vatpic = vm_atpic(vm);
722 atpic = &vatpic->atpic[0];
728 return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
731 return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
735 vatpic_slave_handler(struct vm *vm, int vcpuid, bool in, int port, int bytes,
738 struct vatpic *vatpic;
741 vatpic = vm_atpic(vm);
742 atpic = &vatpic->atpic[1];
748 return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
751 return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
755 vatpic_elc_handler(struct vm *vm, int vcpuid, bool in, int port, int bytes,
758 struct vatpic *vatpic;
761 vatpic = vm_atpic(vm);
762 is_master = (port == IO_ELCR1);
771 *eax = vatpic->elc[0];
773 *eax = vatpic->elc[1];
776 * For the master PIC the cascade channel (IRQ2), the
777 * heart beat timer (IRQ0), and the keyboard
778 * controller (IRQ1) cannot be programmed for level
781 * For the slave PIC the real time clock (IRQ8) and
782 * the floating point error interrupt (IRQ13) cannot
783 * be programmed for level mode.
786 vatpic->elc[0] = (*eax & 0xf8);
788 vatpic->elc[1] = (*eax & 0xde);
791 VATPIC_UNLOCK(vatpic);
797 vatpic_init(struct vm *vm)
799 struct vatpic *vatpic;
801 vatpic = malloc(sizeof(struct vatpic), M_VATPIC, M_WAITOK | M_ZERO);
804 mtx_init(&vatpic->mtx, "vatpic lock", NULL, MTX_SPIN);
810 vatpic_cleanup(struct vatpic *vatpic)
812 free(vatpic, M_VATPIC);
815 #ifdef BHYVE_SNAPSHOT
817 vatpic_snapshot(struct vatpic *vatpic, struct vm_snapshot_meta *meta)
823 for (i = 0; i < nitems(vatpic->atpic); i++) {
824 atpic = &vatpic->atpic[i];
826 SNAPSHOT_VAR_OR_LEAVE(atpic->ready, meta, ret, done);
827 SNAPSHOT_VAR_OR_LEAVE(atpic->icw_num, meta, ret, done);
828 SNAPSHOT_VAR_OR_LEAVE(atpic->rd_cmd_reg, meta, ret, done);
830 SNAPSHOT_VAR_OR_LEAVE(atpic->aeoi, meta, ret, done);
831 SNAPSHOT_VAR_OR_LEAVE(atpic->poll, meta, ret, done);
832 SNAPSHOT_VAR_OR_LEAVE(atpic->rotate, meta, ret, done);
833 SNAPSHOT_VAR_OR_LEAVE(atpic->sfn, meta, ret, done);
834 SNAPSHOT_VAR_OR_LEAVE(atpic->irq_base, meta, ret, done);
835 SNAPSHOT_VAR_OR_LEAVE(atpic->request, meta, ret, done);
836 SNAPSHOT_VAR_OR_LEAVE(atpic->service, meta, ret, done);
837 SNAPSHOT_VAR_OR_LEAVE(atpic->mask, meta, ret, done);
838 SNAPSHOT_VAR_OR_LEAVE(atpic->smm, meta, ret, done);
840 SNAPSHOT_BUF_OR_LEAVE(atpic->acnt, sizeof(atpic->acnt),
842 SNAPSHOT_VAR_OR_LEAVE(atpic->lowprio, meta, ret, done);
843 SNAPSHOT_VAR_OR_LEAVE(atpic->intr_raised, meta, ret, done);
847 SNAPSHOT_BUF_OR_LEAVE(vatpic->elc, sizeof(vatpic->elc),