2 * Copyright (c) 2014 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/types.h>
32 #include <sys/queue.h>
33 #include <sys/cpuset.h>
34 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/mutex.h>
38 #include <sys/systm.h>
40 #include <x86/apicreg.h>
41 #include <dev/ic/i8259.h>
43 #include <machine/vmm.h>
46 #include "vmm_lapic.h"
50 static MALLOC_DEFINE(M_VATPIC, "atpic", "bhyve virtual atpic (8259)");
52 #define VATPIC_LOCK(vatpic) mtx_lock_spin(&((vatpic)->mtx))
53 #define VATPIC_UNLOCK(vatpic) mtx_unlock_spin(&((vatpic)->mtx))
54 #define VATPIC_LOCKED(vatpic) mtx_owned(&((vatpic)->mtx))
70 bool sfn; /* special fully-nested mode */
73 uint8_t request; /* Interrupt Request Register (IIR) */
74 uint8_t service; /* Interrupt Service (ISR) */
75 uint8_t mask; /* Interrupt Mask Register (IMR) */
76 uint8_t smm; /* special mask mode */
78 int acnt[8]; /* sum of pin asserts and deasserts */
79 int lowprio; /* lowest priority irq */
87 struct atpic atpic[2];
91 #define VATPIC_CTR0(vatpic, fmt) \
92 VM_CTR0((vatpic)->vm, fmt)
94 #define VATPIC_CTR1(vatpic, fmt, a1) \
95 VM_CTR1((vatpic)->vm, fmt, a1)
97 #define VATPIC_CTR2(vatpic, fmt, a1, a2) \
98 VM_CTR2((vatpic)->vm, fmt, a1, a2)
100 #define VATPIC_CTR3(vatpic, fmt, a1, a2, a3) \
101 VM_CTR3((vatpic)->vm, fmt, a1, a2, a3)
103 #define VATPIC_CTR4(vatpic, fmt, a1, a2, a3, a4) \
104 VM_CTR4((vatpic)->vm, fmt, a1, a2, a3, a4)
107 * Loop over all the pins in priority order from highest to lowest.
109 #define ATPIC_PIN_FOREACH(pinvar, atpic, tmpvar) \
110 for (tmpvar = 0, pinvar = (atpic->lowprio + 1) & 0x7; \
112 tmpvar++, pinvar = (pinvar + 1) & 0x7)
114 static void vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate);
117 master_atpic(struct vatpic *vatpic, struct atpic *atpic)
120 if (atpic == &vatpic->atpic[0])
127 vatpic_get_highest_isrpin(struct atpic *atpic)
132 ATPIC_PIN_FOREACH(pin, atpic, i) {
135 if (atpic->service & bit) {
137 * An IS bit that is masked by an IMR bit will not be
138 * cleared by a non-specific EOI in Special Mask Mode.
140 if (atpic->smm && (atpic->mask & bit) != 0)
151 vatpic_get_highest_irrpin(struct atpic *atpic)
157 * In 'Special Fully-Nested Mode' when an interrupt request from
158 * a slave is in service, the slave is not locked out from the
159 * master's priority logic.
161 serviced = atpic->service;
163 serviced &= ~(1 << 2);
166 * In 'Special Mask Mode', when a mask bit is set in OCW1 it inhibits
167 * further interrupts at that level and enables interrupts from all
168 * other levels that are not masked. In other words the ISR has no
169 * bearing on the levels that can generate interrupts.
174 ATPIC_PIN_FOREACH(pin, atpic, tmp) {
178 * If there is already an interrupt in service at the same
179 * or higher priority then bail.
181 if ((serviced & bit) != 0)
185 * If an interrupt is asserted and not masked then return
186 * the corresponding 'pin' to the caller.
188 if ((atpic->request & bit) != 0 && (atpic->mask & bit) == 0)
196 vatpic_notify_intr(struct vatpic *vatpic)
201 KASSERT(VATPIC_LOCKED(vatpic), ("vatpic_notify_intr not locked"));
204 * First check the slave.
206 atpic = &vatpic->atpic[1];
207 if (!atpic->intr_raised &&
208 (pin = vatpic_get_highest_irrpin(atpic)) != -1) {
209 VATPIC_CTR4(vatpic, "atpic slave notify pin = %d "
210 "(imr 0x%x irr 0x%x isr 0x%x)", pin,
211 atpic->mask, atpic->request, atpic->service);
214 * Cascade the request from the slave to the master.
216 atpic->intr_raised = true;
217 vatpic_set_pinstate(vatpic, 2, true);
218 vatpic_set_pinstate(vatpic, 2, false);
220 VATPIC_CTR3(vatpic, "atpic slave no eligible interrupts "
221 "(imr 0x%x irr 0x%x isr 0x%x)",
222 atpic->mask, atpic->request, atpic->service);
226 * Then check the master.
228 atpic = &vatpic->atpic[0];
229 if (!atpic->intr_raised &&
230 (pin = vatpic_get_highest_irrpin(atpic)) != -1) {
231 VATPIC_CTR4(vatpic, "atpic master notify pin = %d "
232 "(imr 0x%x irr 0x%x isr 0x%x)", pin,
233 atpic->mask, atpic->request, atpic->service);
236 * From Section 3.6.2, "Interrupt Modes", in the
237 * MPtable Specification, Version 1.4
239 * PIC interrupts are routed to both the Local APIC
240 * and the I/O APIC to support operation in 1 of 3
243 * 1. Legacy PIC Mode: the PIC effectively bypasses
244 * all APIC components. In this mode the local APIC is
245 * disabled and LINT0 is reconfigured as INTR to
246 * deliver the PIC interrupt directly to the CPU.
248 * 2. Virtual Wire Mode: the APIC is treated as a
249 * virtual wire which delivers interrupts from the PIC
250 * to the CPU. In this mode LINT0 is programmed as
251 * ExtINT to indicate that the PIC is the source of
254 * 3. Virtual Wire Mode via I/O APIC: PIC interrupts are
255 * fielded by the I/O APIC and delivered to the appropriate
256 * CPU. In this mode the I/O APIC input 0 is programmed
257 * as ExtINT to indicate that the PIC is the source of the
260 atpic->intr_raised = true;
261 lapic_set_local_intr(vatpic->vm, -1, APIC_LVT_LINT0);
262 vioapic_pulse_irq(vatpic->vm, 0);
264 VATPIC_CTR3(vatpic, "atpic master no eligible interrupts "
265 "(imr 0x%x irr 0x%x isr 0x%x)",
266 atpic->mask, atpic->request, atpic->service);
271 vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
273 VATPIC_CTR1(vatpic, "atpic icw1 0x%x", val);
275 atpic->ready = false;
280 atpic->rd_cmd_reg = 0;
284 if ((val & ICW1_SNGL) != 0) {
285 VATPIC_CTR0(vatpic, "vatpic cascade mode required");
289 if ((val & ICW1_IC4) == 0) {
290 VATPIC_CTR0(vatpic, "vatpic icw4 required");
300 vatpic_icw2(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
302 VATPIC_CTR1(vatpic, "atpic icw2 0x%x", val);
304 atpic->irq_base = val & 0xf8;
312 vatpic_icw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
314 VATPIC_CTR1(vatpic, "atpic icw3 0x%x", val);
322 vatpic_icw4(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
324 VATPIC_CTR1(vatpic, "atpic icw4 0x%x", val);
326 if ((val & ICW4_8086) == 0) {
327 VATPIC_CTR0(vatpic, "vatpic microprocessor mode required");
331 if ((val & ICW4_AEOI) != 0)
334 if ((val & ICW4_SFNM) != 0) {
335 if (master_atpic(vatpic, atpic)) {
338 VATPIC_CTR1(vatpic, "Ignoring special fully nested "
339 "mode on slave atpic: %#x", val);
350 vatpic_ocw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
352 VATPIC_CTR1(vatpic, "atpic ocw1 0x%x", val);
354 atpic->mask = val & 0xff;
360 vatpic_ocw2(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
362 VATPIC_CTR1(vatpic, "atpic ocw2 0x%x", val);
364 atpic->rotate = ((val & OCW2_R) != 0);
366 if ((val & OCW2_EOI) != 0) {
369 if ((val & OCW2_SL) != 0) {
373 /* non-specific EOI */
374 isr_bit = vatpic_get_highest_isrpin(atpic);
378 atpic->service &= ~(1 << isr_bit);
381 atpic->lowprio = isr_bit;
383 } else if ((val & OCW2_SL) != 0 && atpic->rotate == true) {
384 /* specific priority */
385 atpic->lowprio = val & 0x7;
392 vatpic_ocw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
394 VATPIC_CTR1(vatpic, "atpic ocw3 0x%x", val);
396 if (val & OCW3_ESMM) {
397 atpic->smm = val & OCW3_SMM ? 1 : 0;
398 VATPIC_CTR2(vatpic, "%s atpic special mask mode %s",
399 master_atpic(vatpic, atpic) ? "master" : "slave",
400 atpic->smm ? "enabled" : "disabled");
404 /* read register command */
405 atpic->rd_cmd_reg = val & OCW3_RIS;
408 atpic->poll = ((val & OCW3_P) != 0);
415 vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate)
421 KASSERT(pin >= 0 && pin < 16,
422 ("vatpic_set_pinstate: invalid pin number %d", pin));
423 KASSERT(VATPIC_LOCKED(vatpic),
424 ("vatpic_set_pinstate: vatpic is not locked"));
426 atpic = &vatpic->atpic[pin >> 3];
428 oldcnt = atpic->acnt[pin & 0x7];
430 atpic->acnt[pin & 0x7]++;
432 atpic->acnt[pin & 0x7]--;
433 newcnt = atpic->acnt[pin & 0x7];
436 VATPIC_CTR2(vatpic, "atpic pin%d: bad acnt %d", pin, newcnt);
439 level = ((vatpic->elc[pin >> 3] & (1 << (pin & 0x7))) != 0);
441 if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
442 /* rising edge or level */
443 VATPIC_CTR1(vatpic, "atpic pin%d: asserted", pin);
444 atpic->request |= (1 << (pin & 0x7));
445 } else if (oldcnt == 1 && newcnt == 0) {
447 VATPIC_CTR1(vatpic, "atpic pin%d: deasserted", pin);
449 atpic->request &= ~(1 << (pin & 0x7));
451 VATPIC_CTR3(vatpic, "atpic pin%d: %s, ignored, acnt %d",
452 pin, newstate ? "asserted" : "deasserted", newcnt);
455 vatpic_notify_intr(vatpic);
459 vatpic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
461 struct vatpic *vatpic;
464 if (irq < 0 || irq > 15)
467 vatpic = vm_atpic(vm);
468 atpic = &vatpic->atpic[irq >> 3];
470 if (atpic->ready == false)
475 case IRQSTATE_ASSERT:
476 vatpic_set_pinstate(vatpic, irq, true);
478 case IRQSTATE_DEASSERT:
479 vatpic_set_pinstate(vatpic, irq, false);
482 vatpic_set_pinstate(vatpic, irq, true);
483 vatpic_set_pinstate(vatpic, irq, false);
486 panic("vatpic_set_irqstate: invalid irqstate %d", irqstate);
488 VATPIC_UNLOCK(vatpic);
494 vatpic_assert_irq(struct vm *vm, int irq)
496 return (vatpic_set_irqstate(vm, irq, IRQSTATE_ASSERT));
500 vatpic_deassert_irq(struct vm *vm, int irq)
502 return (vatpic_set_irqstate(vm, irq, IRQSTATE_DEASSERT));
506 vatpic_pulse_irq(struct vm *vm, int irq)
508 return (vatpic_set_irqstate(vm, irq, IRQSTATE_PULSE));
512 vatpic_set_irq_trigger(struct vm *vm, int irq, enum vm_intr_trigger trigger)
514 struct vatpic *vatpic;
516 if (irq < 0 || irq > 15)
520 * See comment in vatpic_elc_handler. These IRQs must be
523 if (trigger == LEVEL_TRIGGER) {
534 vatpic = vm_atpic(vm);
538 if (trigger == LEVEL_TRIGGER)
539 vatpic->elc[irq >> 3] |= 1 << (irq & 0x7);
541 vatpic->elc[irq >> 3] &= ~(1 << (irq & 0x7));
543 VATPIC_UNLOCK(vatpic);
549 vatpic_pending_intr(struct vm *vm, int *vecptr)
551 struct vatpic *vatpic;
555 vatpic = vm_atpic(vm);
557 atpic = &vatpic->atpic[0];
561 pin = vatpic_get_highest_irrpin(atpic);
563 atpic = &vatpic->atpic[1];
564 pin = vatpic_get_highest_irrpin(atpic);
568 * If there are no pins active at this moment then return the spurious
569 * interrupt vector instead.
574 KASSERT(pin >= 0 && pin <= 7, ("%s: invalid pin %d", __func__, pin));
575 *vecptr = atpic->irq_base + pin;
577 VATPIC_UNLOCK(vatpic);
581 vatpic_pin_accepted(struct atpic *atpic, int pin)
583 atpic->intr_raised = false;
585 if (atpic->acnt[pin] == 0)
586 atpic->request &= ~(1 << pin);
588 if (atpic->aeoi == true) {
589 if (atpic->rotate == true)
590 atpic->lowprio = pin;
592 atpic->service |= (1 << pin);
597 vatpic_intr_accepted(struct vm *vm, int vector)
599 struct vatpic *vatpic;
602 vatpic = vm_atpic(vm);
608 if ((vector & ~0x7) == vatpic->atpic[1].irq_base) {
609 vatpic_pin_accepted(&vatpic->atpic[1], pin);
611 * If this vector originated from the slave,
612 * accept the cascaded interrupt too.
614 vatpic_pin_accepted(&vatpic->atpic[0], 2);
616 vatpic_pin_accepted(&vatpic->atpic[0], pin);
619 vatpic_notify_intr(vatpic);
621 VATPIC_UNLOCK(vatpic);
625 vatpic_read(struct vatpic *vatpic, struct atpic *atpic, bool in, int port,
626 int bytes, uint32_t *eax)
634 pin = vatpic_get_highest_irrpin(atpic);
636 vatpic_pin_accepted(atpic, pin);
642 if (port & ICU_IMR_OFFSET) {
643 /* read interrrupt mask register */
646 if (atpic->rd_cmd_reg == OCW3_RIS) {
647 /* read interrupt service register */
648 *eax = atpic->service;
650 /* read interrupt request register */
651 *eax = atpic->request;
656 VATPIC_UNLOCK(vatpic);
663 vatpic_write(struct vatpic *vatpic, struct atpic *atpic, bool in, int port,
664 int bytes, uint32_t *eax)
674 if (port & ICU_IMR_OFFSET) {
675 switch (atpic->icw_num) {
677 error = vatpic_icw2(vatpic, atpic, val);
680 error = vatpic_icw3(vatpic, atpic, val);
683 error = vatpic_icw4(vatpic, atpic, val);
686 error = vatpic_ocw1(vatpic, atpic, val);
691 error = vatpic_icw1(vatpic, atpic, val);
695 error = vatpic_ocw3(vatpic, atpic, val);
697 error = vatpic_ocw2(vatpic, atpic, val);
702 vatpic_notify_intr(vatpic);
704 VATPIC_UNLOCK(vatpic);
710 vatpic_master_handler(struct vm *vm, int vcpuid, bool in, int port, int bytes,
713 struct vatpic *vatpic;
716 vatpic = vm_atpic(vm);
717 atpic = &vatpic->atpic[0];
723 return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
726 return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
730 vatpic_slave_handler(struct vm *vm, int vcpuid, bool in, int port, int bytes,
733 struct vatpic *vatpic;
736 vatpic = vm_atpic(vm);
737 atpic = &vatpic->atpic[1];
743 return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
746 return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
750 vatpic_elc_handler(struct vm *vm, int vcpuid, bool in, int port, int bytes,
753 struct vatpic *vatpic;
756 vatpic = vm_atpic(vm);
757 is_master = (port == IO_ELCR1);
766 *eax = vatpic->elc[0];
768 *eax = vatpic->elc[1];
771 * For the master PIC the cascade channel (IRQ2), the
772 * heart beat timer (IRQ0), and the keyboard
773 * controller (IRQ1) cannot be programmed for level
776 * For the slave PIC the real time clock (IRQ8) and
777 * the floating point error interrupt (IRQ13) cannot
778 * be programmed for level mode.
781 vatpic->elc[0] = (*eax & 0xf8);
783 vatpic->elc[1] = (*eax & 0xde);
786 VATPIC_UNLOCK(vatpic);
792 vatpic_init(struct vm *vm)
794 struct vatpic *vatpic;
796 vatpic = malloc(sizeof(struct vatpic), M_VATPIC, M_WAITOK | M_ZERO);
799 mtx_init(&vatpic->mtx, "vatpic lock", NULL, MTX_SPIN);
805 vatpic_cleanup(struct vatpic *vatpic)
807 free(vatpic, M_VATPIC);