2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include "opt_bhyve_snapshot.h"
37 #include <sys/param.h>
38 #include <sys/queue.h>
40 #include <sys/mutex.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
45 #include <x86/apicreg.h>
46 #include <machine/vmm.h>
47 #include <machine/vmm_snapshot.h>
50 #include "vmm_lapic.h"
57 #define REDIR_ENTRIES 32
58 #define RTBL_RO_BITS ((uint64_t)(IOART_REM_IRR | IOART_DELIVS))
67 int acnt; /* sum of pin asserts (+1) and deasserts (-1) */
68 } rtbl[REDIR_ENTRIES];
71 #define VIOAPIC_LOCK(vioapic) mtx_lock_spin(&((vioapic)->mtx))
72 #define VIOAPIC_UNLOCK(vioapic) mtx_unlock_spin(&((vioapic)->mtx))
73 #define VIOAPIC_LOCKED(vioapic) mtx_owned(&((vioapic)->mtx))
75 static MALLOC_DEFINE(M_VIOAPIC, "vioapic", "bhyve virtual ioapic");
77 #define VIOAPIC_CTR1(vioapic, fmt, a1) \
78 VM_CTR1((vioapic)->vm, fmt, a1)
80 #define VIOAPIC_CTR2(vioapic, fmt, a1, a2) \
81 VM_CTR2((vioapic)->vm, fmt, a1, a2)
83 #define VIOAPIC_CTR3(vioapic, fmt, a1, a2, a3) \
84 VM_CTR3((vioapic)->vm, fmt, a1, a2, a3)
86 #define VIOAPIC_CTR4(vioapic, fmt, a1, a2, a3, a4) \
87 VM_CTR4((vioapic)->vm, fmt, a1, a2, a3, a4)
91 pinstate_str(bool asserted)
97 return ("deasserted");
102 vioapic_send_intr(struct vioapic *vioapic, int pin)
105 uint32_t low, high, dest;
108 KASSERT(pin >= 0 && pin < REDIR_ENTRIES,
109 ("vioapic_set_pinstate: invalid pin number %d", pin));
111 KASSERT(VIOAPIC_LOCKED(vioapic),
112 ("vioapic_set_pinstate: vioapic is not locked"));
114 low = vioapic->rtbl[pin].reg;
115 high = vioapic->rtbl[pin].reg >> 32;
117 if ((low & IOART_INTMASK) == IOART_INTMSET) {
118 VIOAPIC_CTR1(vioapic, "ioapic pin%d: masked", pin);
122 phys = ((low & IOART_DESTMOD) == IOART_DESTPHY);
123 delmode = low & IOART_DELMOD;
124 level = low & IOART_TRGRLVL ? true : false;
126 if ((low & IOART_REM_IRR) != 0) {
127 VIOAPIC_CTR1(vioapic, "ioapic pin%d: irr pending",
131 vioapic->rtbl[pin].reg |= IOART_REM_IRR;
134 vector = low & IOART_INTVEC;
135 dest = high >> APIC_ID_SHIFT;
136 vlapic_deliver_intr(vioapic->vm, level, dest, phys, delmode, vector);
140 vioapic_set_pinstate(struct vioapic *vioapic, int pin, bool newstate)
145 KASSERT(pin >= 0 && pin < REDIR_ENTRIES,
146 ("vioapic_set_pinstate: invalid pin number %d", pin));
148 KASSERT(VIOAPIC_LOCKED(vioapic),
149 ("vioapic_set_pinstate: vioapic is not locked"));
151 oldcnt = vioapic->rtbl[pin].acnt;
153 vioapic->rtbl[pin].acnt++;
155 vioapic->rtbl[pin].acnt--;
156 newcnt = vioapic->rtbl[pin].acnt;
159 VIOAPIC_CTR2(vioapic, "ioapic pin%d: bad acnt %d",
164 if (oldcnt == 0 && newcnt == 1) {
166 VIOAPIC_CTR1(vioapic, "ioapic pin%d: asserted", pin);
167 } else if (oldcnt == 1 && newcnt == 0) {
168 VIOAPIC_CTR1(vioapic, "ioapic pin%d: deasserted", pin);
170 VIOAPIC_CTR3(vioapic, "ioapic pin%d: %s, ignored, acnt %d",
171 pin, pinstate_str(newstate), newcnt);
175 vioapic_send_intr(vioapic, pin);
185 vioapic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
187 struct vioapic *vioapic;
189 if (irq < 0 || irq >= REDIR_ENTRIES)
192 vioapic = vm_ioapic(vm);
194 VIOAPIC_LOCK(vioapic);
196 case IRQSTATE_ASSERT:
197 vioapic_set_pinstate(vioapic, irq, true);
199 case IRQSTATE_DEASSERT:
200 vioapic_set_pinstate(vioapic, irq, false);
203 vioapic_set_pinstate(vioapic, irq, true);
204 vioapic_set_pinstate(vioapic, irq, false);
207 panic("vioapic_set_irqstate: invalid irqstate %d", irqstate);
209 VIOAPIC_UNLOCK(vioapic);
215 vioapic_assert_irq(struct vm *vm, int irq)
218 return (vioapic_set_irqstate(vm, irq, IRQSTATE_ASSERT));
222 vioapic_deassert_irq(struct vm *vm, int irq)
225 return (vioapic_set_irqstate(vm, irq, IRQSTATE_DEASSERT));
229 vioapic_pulse_irq(struct vm *vm, int irq)
232 return (vioapic_set_irqstate(vm, irq, IRQSTATE_PULSE));
236 * Reset the vlapic's trigger-mode register to reflect the ioapic pin
240 vioapic_update_tmr(struct vm *vm, int vcpuid, void *arg)
242 struct vioapic *vioapic;
243 struct vlapic *vlapic;
244 uint32_t low, high, dest;
245 int delmode, pin, vector;
248 vlapic = vm_lapic(vm, vcpuid);
249 vioapic = vm_ioapic(vm);
251 VIOAPIC_LOCK(vioapic);
253 * Reset all vectors to be edge-triggered.
255 vlapic_reset_tmr(vlapic);
256 for (pin = 0; pin < REDIR_ENTRIES; pin++) {
257 low = vioapic->rtbl[pin].reg;
258 high = vioapic->rtbl[pin].reg >> 32;
260 level = low & IOART_TRGRLVL ? true : false;
265 * For a level-triggered 'pin' let the vlapic figure out if
266 * an assertion on this 'pin' would result in an interrupt
267 * being delivered to it. If yes, then it will modify the
268 * TMR bit associated with this vector to level-triggered.
270 phys = ((low & IOART_DESTMOD) == IOART_DESTPHY);
271 delmode = low & IOART_DELMOD;
272 vector = low & IOART_INTVEC;
273 dest = high >> APIC_ID_SHIFT;
274 vlapic_set_tmr_level(vlapic, dest, phys, delmode, vector);
276 VIOAPIC_UNLOCK(vioapic);
280 vioapic_read(struct vioapic *vioapic, int vcpuid, uint32_t addr)
282 int regnum, pin, rshift;
284 regnum = addr & 0xff;
287 return (vioapic->id);
290 return (((REDIR_ENTRIES - 1) << MAXREDIRSHIFT) | 0x11);
293 return (vioapic->id);
299 /* redirection table entries */
300 if (regnum >= IOAPIC_REDTBL &&
301 regnum < IOAPIC_REDTBL + REDIR_ENTRIES * 2) {
302 pin = (regnum - IOAPIC_REDTBL) / 2;
303 if ((regnum - IOAPIC_REDTBL) % 2)
308 return (vioapic->rtbl[pin].reg >> rshift);
315 vioapic_write(struct vioapic *vioapic, int vcpuid, uint32_t addr, uint32_t data)
317 uint64_t data64, mask64;
318 uint64_t last, changed;
319 int regnum, pin, lshift;
322 regnum = addr & 0xff;
325 vioapic->id = data & APIC_ID_MASK;
335 /* redirection table entries */
336 if (regnum >= IOAPIC_REDTBL &&
337 regnum < IOAPIC_REDTBL + REDIR_ENTRIES * 2) {
338 pin = (regnum - IOAPIC_REDTBL) / 2;
339 if ((regnum - IOAPIC_REDTBL) % 2)
344 last = vioapic->rtbl[pin].reg;
346 data64 = (uint64_t)data << lshift;
347 mask64 = (uint64_t)0xffffffff << lshift;
348 vioapic->rtbl[pin].reg &= ~mask64 | RTBL_RO_BITS;
349 vioapic->rtbl[pin].reg |= data64 & ~RTBL_RO_BITS;
352 * Switching from level to edge triggering will clear the IRR
353 * bit. This is what FreeBSD will do in order to EOI an
354 * interrupt when the IO-APIC doesn't support targeted EOI (see
355 * _ioapic_eoi_source).
357 if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGREDG &&
358 (vioapic->rtbl[pin].reg & IOART_REM_IRR) != 0)
359 vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;
361 VIOAPIC_CTR2(vioapic, "ioapic pin%d: redir table entry %#lx",
362 pin, vioapic->rtbl[pin].reg);
365 * If any fields in the redirection table entry (except mask
366 * or polarity) have changed then rendezvous all the vcpus
367 * to update their vlapic trigger-mode registers.
369 changed = last ^ vioapic->rtbl[pin].reg;
370 if (changed & ~(IOART_INTMASK | IOART_INTPOL)) {
371 VIOAPIC_CTR1(vioapic, "ioapic pin%d: recalculate "
372 "vlapic trigger-mode register", pin);
373 VIOAPIC_UNLOCK(vioapic);
374 allvcpus = vm_active_cpus(vioapic->vm);
375 (void)vm_smp_rendezvous(vioapic->vm, vcpuid, allvcpus,
376 vioapic_update_tmr, NULL);
377 VIOAPIC_LOCK(vioapic);
381 * Generate an interrupt if the following conditions are met:
382 * - pin trigger mode is level
383 * - pin level is asserted
385 if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGRLVL &&
386 (vioapic->rtbl[pin].acnt > 0)) {
387 VIOAPIC_CTR2(vioapic, "ioapic pin%d: asserted at rtbl "
388 "write, acnt %d", pin, vioapic->rtbl[pin].acnt);
389 vioapic_send_intr(vioapic, pin);
395 vioapic_mmio_rw(struct vioapic *vioapic, int vcpuid, uint64_t gpa,
396 uint64_t *data, int size, bool doread)
400 offset = gpa - VIOAPIC_BASE;
403 * The IOAPIC specification allows 32-bit wide accesses to the
404 * IOREGSEL (offset 0) and IOWIN (offset 16) registers.
406 if (size != 4 || (offset != IOREGSEL && offset != IOWIN)) {
412 VIOAPIC_LOCK(vioapic);
413 if (offset == IOREGSEL) {
415 *data = vioapic->ioregsel;
417 vioapic->ioregsel = *data;
420 *data = vioapic_read(vioapic, vcpuid,
423 vioapic_write(vioapic, vcpuid, vioapic->ioregsel,
427 VIOAPIC_UNLOCK(vioapic);
433 vioapic_mmio_read(void *vm, int vcpuid, uint64_t gpa, uint64_t *rval,
437 struct vioapic *vioapic;
439 vioapic = vm_ioapic(vm);
440 error = vioapic_mmio_rw(vioapic, vcpuid, gpa, rval, size, true);
445 vioapic_mmio_write(void *vm, int vcpuid, uint64_t gpa, uint64_t wval,
449 struct vioapic *vioapic;
451 vioapic = vm_ioapic(vm);
452 error = vioapic_mmio_rw(vioapic, vcpuid, gpa, &wval, size, false);
457 vioapic_process_eoi(struct vm *vm, int vcpuid, int vector)
459 struct vioapic *vioapic;
462 KASSERT(vector >= 0 && vector < 256,
463 ("vioapic_process_eoi: invalid vector %d", vector));
465 vioapic = vm_ioapic(vm);
466 VIOAPIC_CTR1(vioapic, "ioapic processing eoi for vector %d", vector);
469 * XXX keep track of the pins associated with this vector instead
470 * of iterating on every single pin each time.
472 VIOAPIC_LOCK(vioapic);
473 for (pin = 0; pin < REDIR_ENTRIES; pin++) {
474 if ((vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0)
476 if ((vioapic->rtbl[pin].reg & IOART_INTVEC) != vector)
478 vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;
479 if (vioapic->rtbl[pin].acnt > 0) {
480 VIOAPIC_CTR2(vioapic, "ioapic pin%d: asserted at eoi, "
481 "acnt %d", pin, vioapic->rtbl[pin].acnt);
482 vioapic_send_intr(vioapic, pin);
485 VIOAPIC_UNLOCK(vioapic);
489 vioapic_init(struct vm *vm)
492 struct vioapic *vioapic;
494 vioapic = malloc(sizeof(struct vioapic), M_VIOAPIC, M_WAITOK | M_ZERO);
497 mtx_init(&vioapic->mtx, "vioapic lock", NULL, MTX_SPIN);
499 /* Initialize all redirection entries to mask all interrupts */
500 for (i = 0; i < REDIR_ENTRIES; i++)
501 vioapic->rtbl[i].reg = 0x0001000000010000UL;
507 vioapic_cleanup(struct vioapic *vioapic)
510 free(vioapic, M_VIOAPIC);
514 vioapic_pincount(struct vm *vm)
517 return (REDIR_ENTRIES);
520 #ifdef BHYVE_SNAPSHOT
522 vioapic_snapshot(struct vioapic *vioapic, struct vm_snapshot_meta *meta)
527 SNAPSHOT_VAR_OR_LEAVE(vioapic->ioregsel, meta, ret, done);
529 for (i = 0; i < nitems(vioapic->rtbl); i++) {
530 SNAPSHOT_VAR_OR_LEAVE(vioapic->rtbl[i].reg, meta, ret, done);
531 SNAPSHOT_VAR_OR_LEAVE(vioapic->rtbl[i].acnt, meta, ret, done);