2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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35 struct vm_snapshot_meta;
38 int vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
39 uint64_t data, bool *retu);
40 int vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
41 uint64_t *data, bool *retu);
44 * Returns 0 if there is no eligible vector that can be delivered to the
45 * guest at this time and non-zero otherwise.
47 * If an eligible vector number is found and 'vecptr' is not NULL then it will
48 * be stored in the location pointed to by 'vecptr'.
50 * Note that the vector does not automatically transition to the ISR as a
51 * result of calling this function.
53 int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
56 * Transition 'vector' from IRR to ISR. This function is called with the
57 * vector returned by 'vlapic_pending_intr()' when the guest is able to
58 * accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
59 * block interrupt delivery).
61 void vlapic_intr_accepted(struct vlapic *vlapic, int vector);
64 * Returns 1 if the vcpu needs to be notified of the interrupt and 0 otherwise.
66 int vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level);
69 * Post an interrupt to the vcpu running on 'hostcpu'. This will use a
70 * hardware assist if available (e.g. Posted Interrupt) or fall back to
71 * sending an 'ipinum' to interrupt the 'hostcpu'.
73 void vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum);
75 void vlapic_fire_cmci(struct vlapic *vlapic);
76 int vlapic_trigger_lvt(struct vlapic *vlapic, int vector);
78 void vlapic_sync_tpr(struct vlapic *vlapic);
80 uint64_t vlapic_get_apicbase(struct vlapic *vlapic);
81 int vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val);
82 void vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state s);
83 bool vlapic_enabled(struct vlapic *vlapic);
85 void vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
86 int delmode, int vec);
88 /* Reset the trigger-mode bits for all vectors to be edge-triggered */
89 void vlapic_reset_tmr(struct vlapic *vlapic);
92 * Set the trigger-mode bit associated with 'vector' to level-triggered if
93 * the (dest,phys,delmode) tuple resolves to an interrupt being delivered to
96 void vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,
97 int delmode, int vector);
99 void vlapic_set_cr8(struct vlapic *vlapic, uint64_t val);
100 uint64_t vlapic_get_cr8(struct vlapic *vlapic);
102 /* APIC write handlers */
103 void vlapic_id_write_handler(struct vlapic *vlapic);
104 void vlapic_ldr_write_handler(struct vlapic *vlapic);
105 void vlapic_dfr_write_handler(struct vlapic *vlapic);
106 void vlapic_svr_write_handler(struct vlapic *vlapic);
107 void vlapic_esr_write_handler(struct vlapic *vlapic);
108 int vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu);
109 void vlapic_icrtmr_write_handler(struct vlapic *vlapic);
110 void vlapic_dcr_write_handler(struct vlapic *vlapic);
111 void vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset);
112 void vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val);
114 #ifdef BHYVE_SNAPSHOT
115 int vlapic_snapshot(struct vm *vm, struct vm_snapshot_meta *meta);
118 #endif /* _VLAPIC_H_ */